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ath9k: Fix bug in rate table
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c 29#include <linux/init.h>
5a0e3ad6 30#include <linux/slab.h>
b481de9c
ZY		 31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
d43c36dc 34#include <linux/sched.h>
b481de9c
ZY		 35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/wireless.h>
38#include <linux/firmware.h>
b481de9c 39#include <linux/etherdevice.h>
12342c47
ZY		 40#include <asm/unaligned.h>
41#include <net/mac80211.h>
b481de9c 42
dbb6654c 43#include "iwl-fh.h"
bddadf86 44#include "iwl-3945-fh.h"
600c0e11 45#include "iwl-commands.h"
17f841cd 46#include "iwl-sta.h"
b481de9c 47#include "iwl-3945.h"
e6148917 48#include "iwl-eeprom.h"
5747d47f 49#include "iwl-core.h"
4a6547c7 50#include "iwl-helpers.h"
e932a609
JB		 51#include "iwl-led.h"
52#include "iwl-3945-led.h"
17f36fc6 53#include "iwl-3945-debugfs.h"
b481de9c
ZY		 54
55#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 66
67/*
68 * Parameter order:
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
d9829a67 75const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 88};
89
bb8c093b 90/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 91#define IWL_EVT_DISABLE (0)
92#define IWL_EVT_DISABLE_SIZE (1532/32)
93
94/**
bb8c093b 95 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 96 *
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 103void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 104{
b481de9c
ZY		 105 int i;
106 u32 base; /* SRAM address of event log header */
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
108 u32 array_size; /* # of u32 entries in array */
109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
157 };
158
159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 167
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 170 disable_ptr);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 172 iwl_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
b481de9c 176 } else {
e1623446
TW		 177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 180 disable_ptr, array_size);
181 }
182
183}
184
17744ff6
TW		 185static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
186{
187 int idx;
188
1d79e53c 189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
17744ff6
TW		 190 if (iwl3945_rates[idx].plcp == plcp)
191 return idx;
192 return -1;
193}
194
d08853a3 195#ifdef CONFIG_IWLWIFI_DEBUG
04569cbe 196#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2
TW		 197
198static const char *iwl3945_get_tx_fail_reason(u32 status)
199{
200 switch (status & TX_STATUS_MSK) {
04569cbe 201 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 202 return "SUCCESS";
203 TX_STATUS_ENTRY(SHORT_LIMIT);
204 TX_STATUS_ENTRY(LONG_LIMIT);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN);
206 TX_STATUS_ENTRY(MGMNT_ABORT);
207 TX_STATUS_ENTRY(NEXT_FRAG);
208 TX_STATUS_ENTRY(LIFE_EXPIRE);
209 TX_STATUS_ENTRY(DEST_PS);
210 TX_STATUS_ENTRY(ABORTED);
211 TX_STATUS_ENTRY(BT_RETRY);
212 TX_STATUS_ENTRY(STA_INVALID);
213 TX_STATUS_ENTRY(FRAG_DROPPED);
214 TX_STATUS_ENTRY(TID_DISABLE);
215 TX_STATUS_ENTRY(FRAME_FLUSHED);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
217 TX_STATUS_ENTRY(TX_LOCKED);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
219 }
220
221 return "UNKNOWN";
222}
223#else
224static inline const char *iwl3945_get_tx_fail_reason(u32 status)
225{
226 return "";
227}
228#endif
229
e6a9854b
JB		 230/*
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
233 * value
234 */
4a8a4322 235int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 236{
237 int next_rate = iwl3945_get_prev_ieee_rate(rate);
238
239 switch (priv->band) {
240 case IEEE80211_BAND_5GHZ:
241 if (rate == IWL_RATE_12M_INDEX)
242 next_rate = IWL_RATE_9M_INDEX;
243 else if (rate == IWL_RATE_6M_INDEX)
244 next_rate = IWL_RATE_6M_INDEX;
245 break;
7262796a 246 case IEEE80211_BAND_2GHZ:
ee525d13 247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 248 iwl_is_associated(priv)) {
7262796a
AM		 249 if (rate == IWL_RATE_11M_INDEX)
250 next_rate = IWL_RATE_5M_INDEX;
251 }
e6a9854b 252 break;
7262796a 253
e6a9854b
JB		 254 default:
255 break;
256 }
257
258 return next_rate;
259}
260
91c066f2
TW		 261
262/**
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
264 *
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
268 */
4a8a4322 269static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 270 int txq_id, int index)
271{
188cf6c7 272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 273 struct iwl_queue *q = &txq->q;
dbb6654c 274 struct iwl_tx_info *tx_info;
91c066f2
TW		 275
276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
277
278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
280
281 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 283 tx_info->skb[0] = NULL;
7aaa1d79 284 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 285 }
286
d20b3c65 287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 288 (txq_id != IWL_CMD_QUEUE_NUM) &&
289 priv->mac80211_registered)
e4e72fb4 290 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 291}
292
293/**
294 * iwl3945_rx_reply_tx - Handle Tx response
295 */
4a8a4322 296static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
17f36fc6 297 struct iwl_rx_mem_buffer *rxb)
91c066f2 298{
2f301227 299 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 300 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
301 int txq_id = SEQ_TO_QUEUE(sequence);
302 int index = SEQ_TO_INDEX(sequence);
188cf6c7 303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 304 struct ieee80211_tx_info *info;
91c066f2
TW		 305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
306 u32 status = le32_to_cpu(tx_resp->status);
307 int rate_idx;
74221d07 308 int fail;
91c066f2 309
625a381a 310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 312 "is out of range [0-%d] %d %d\n", txq_id,
313 index, txq->q.n_bd, txq->q.write_ptr,
314 txq->q.read_ptr);
315 return;
316 }
317
e039fa4a 318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 319 ieee80211_tx_info_clear_status(info);
320
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
323 if (info->band == IEEE80211_BAND_5GHZ)
324 rate_idx -= IWL_FIRST_OFDM_RATE;
325
326 fail = tx_resp->failure_frame;
74221d07
AM		 327
328 info->status.rates[0].idx = rate_idx;
329 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 330
91c066f2 331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
333 IEEE80211_TX_STAT_ACK : 0;
91c066f2 334
e1623446 335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 336 txq_id, iwl3945_get_tx_fail_reason(status), status,
337 tx_resp->rate, tx_resp->failure_frame);
338
e1623446 339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
341
342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 344}
345
346
347
b481de9c
ZY		 348/*****************************************************************************
349 *
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
351 *
352 * RX handler implementations
353 *
b481de9c 354 *****************************************************************************/
d73e4923 355#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 356/*
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
360 */
361static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
362 __le32 *stats)
363{
364 int i;
365 __le32 *prev_stats;
366 u32 *accum_stats;
367 u32 *delta, *max_delta;
368
369 prev_stats = (__le32 *)&priv->_3945.statistics;
370 accum_stats = (u32 *)&priv->_3945.accum_statistics;
371 delta = (u32 *)&priv->_3945.delta_statistics;
372 max_delta = (u32 *)&priv->_3945.max_delta;
373
374 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
375 i += sizeof(__le32), stats++, prev_stats++, delta++,
376 max_delta++, accum_stats++) {
377 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
378 *delta = (le32_to_cpu(*stats) -
379 le32_to_cpu(*prev_stats));
380 *accum_stats += *delta;
381 if (*delta > *max_delta)
382 *max_delta = *delta;
383 }
384 }
385
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv->_3945.accum_statistics.general.temperature =
388 priv->_3945.statistics.general.temperature;
389 priv->_3945.accum_statistics.general.ttl_timestamp =
390 priv->_3945.statistics.general.ttl_timestamp;
391}
392#endif
b481de9c 393
a29576a7
AK		 394/**
395 * iwl3945_good_plcp_health - checks for plcp error.
396 *
397 * When the plcp error is exceeding the thresholds, reset the radio
398 * to improve the throughput.
399 */
400static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
401 struct iwl_rx_packet *pkt)
402{
403 bool rc = true;
404 struct iwl3945_notif_statistics current_stat;
405 int combined_plcp_delta;
406 unsigned int plcp_msec;
407 unsigned long plcp_received_jiffies;
408
409 memcpy(&current_stat, pkt->u.raw, sizeof(struct
410 iwl3945_notif_statistics));
411 /*
412 * check for plcp_err and trigger radio reset if it exceeds
413 * the plcp error threshold plcp_delta.
414 */
415 plcp_received_jiffies = jiffies;
416 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
417 (long) priv->plcp_jiffies);
418 priv->plcp_jiffies = plcp_received_jiffies;
419 /*
420 * check to make sure plcp_msec is not 0 to prevent division
421 * by zero.
422 */
423 if (plcp_msec) {
424 combined_plcp_delta =
425 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
426 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
427
428 if ((combined_plcp_delta > 0) &&
429 ((combined_plcp_delta * 100) / plcp_msec) >
430 priv->cfg->plcp_delta_threshold) {
431 /*
432 * if plcp_err exceed the threshold, the following
433 * data is printed in csv format:
434 * Text: plcp_err exceeded %d,
435 * Received ofdm.plcp_err,
436 * Current ofdm.plcp_err,
437 * combined_plcp_delta,
438 * plcp_msec
439 */
440 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
441 "%u, %d, %u mSecs\n",
442 priv->cfg->plcp_delta_threshold,
443 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
444 combined_plcp_delta, plcp_msec);
445 /*
446 * Reset the RF radio due to the high plcp
447 * error rate
448 */
449 rc = false;
450 }
451 }
452 return rc;
453}
454
396887a2
DH		 455void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
456 struct iwl_rx_mem_buffer *rxb)
b481de9c 457{
2f301227 458 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17f36fc6 459
e1623446 460 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 461 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 462 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
d73e4923 463#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 464 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
465#endif
a29576a7 466 iwl_recover_from_statistics(priv, pkt);
b481de9c 467
ee525d13 468 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 469}
470
17f36fc6
AK		 471void iwl3945_reply_statistics(struct iwl_priv *priv,
472 struct iwl_rx_mem_buffer *rxb)
473{
474 struct iwl_rx_packet *pkt = rxb_addr(rxb);
475 __le32 *flag = (__le32 *)&pkt->u.raw;
476
477 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
d73e4923 478#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 479 memset(&priv->_3945.accum_statistics, 0,
480 sizeof(struct iwl3945_notif_statistics));
481 memset(&priv->_3945.delta_statistics, 0,
482 sizeof(struct iwl3945_notif_statistics));
483 memset(&priv->_3945.max_delta, 0,
484 sizeof(struct iwl3945_notif_statistics));
485#endif
486 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
487 }
488 iwl3945_hw_rx_statistics(priv, rxb);
489}
490
491
17744ff6
TW		 492/******************************************************************************
493 *
494 * Misc. internal state and helper functions
495 *
496 ******************************************************************************/
d08853a3 497#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 498
499/**
500 * iwl3945_report_frame - dump frame to syslog during debug sessions
501 *
502 * You may hack this function to show different aspects of received frames,
503 * including selective frame dumps.
504 * group100 parameter selects whether to show 1 out of 100 good frames.
505 */
d08853a3 506static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 507 struct iwl_rx_packet *pkt,
17744ff6
TW		 508 struct ieee80211_hdr *header, int group100)
509{
510 u32 to_us;
511 u32 print_summary = 0;
512 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
513 u32 hundred = 0;
514 u32 dataframe = 0;
fd7c8a40 515 __le16 fc;
17744ff6
TW		 516 u16 seq_ctl;
517 u16 channel;
518 u16 phy_flags;
519 u16 length;
520 u16 status;
521 u16 bcn_tmr;
522 u32 tsf_low;
523 u64 tsf;
524 u8 rssi;
525 u8 agc;
526 u16 sig_avg;
527 u16 noise_diff;
528 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
529 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
530 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
531 u8 *data = IWL_RX_DATA(pkt);
532
533 /* MAC header */
fd7c8a40 534 fc = header->frame_control;
17744ff6
TW		 535 seq_ctl = le16_to_cpu(header->seq_ctrl);
536
537 /* metadata */
538 channel = le16_to_cpu(rx_hdr->channel);
539 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
540 length = le16_to_cpu(rx_hdr->len);
541
542 /* end-of-frame status and timestamp */
543 status = le32_to_cpu(rx_end->status);
544 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
545 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
546 tsf = le64_to_cpu(rx_end->timestamp);
547
548 /* signal statistics */
549 rssi = rx_stats->rssi;
550 agc = rx_stats->agc;
551 sig_avg = le16_to_cpu(rx_stats->sig_avg);
552 noise_diff = le16_to_cpu(rx_stats->noise_diff);
553
554 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
555
556 /* if data frame is to us and all is good,
557 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 558 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
559 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 560 dataframe = 1;
561 if (!group100)
562 print_summary = 1; /* print each frame */
563 else if (priv->framecnt_to_us < 100) {
564 priv->framecnt_to_us++;
565 print_summary = 0;
566 } else {
567 priv->framecnt_to_us = 0;
568 print_summary = 1;
569 hundred = 1;
570 }
571 } else {
572 /* print summary for all other frames */
573 print_summary = 1;
574 }
575
576 if (print_summary) {
577 char *title;
0ff1cca0 578 int rate;
17744ff6
TW		 579
580 if (hundred)
581 title = "100Frames";
fd7c8a40 582 else if (ieee80211_has_retry(fc))
17744ff6 583 title = "Retry";
fd7c8a40 584 else if (ieee80211_is_assoc_resp(fc))
17744ff6 585 title = "AscRsp";
fd7c8a40 586 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 587 title = "RasRsp";
fd7c8a40 588 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 589 title = "PrbRsp";
590 print_dump = 1; /* dump frame contents */
591 } else if (ieee80211_is_beacon(fc)) {
592 title = "Beacon";
593 print_dump = 1; /* dump frame contents */
594 } else if (ieee80211_is_atim(fc))
595 title = "ATIM";
596 else if (ieee80211_is_auth(fc))
597 title = "Auth";
598 else if (ieee80211_is_deauth(fc))
599 title = "DeAuth";
600 else if (ieee80211_is_disassoc(fc))
601 title = "DisAssoc";
602 else
603 title = "Frame";
604
605 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
606 if (rate == -1)
607 rate = 0;
608 else
609 rate = iwl3945_rates[rate].ieee / 2;
610
611 /* print frame summary.
612 * MAC addresses show just the last byte (for brevity),
613 * but you can hack it to show more, if you'd like to. */
614 if (dataframe)
e1623446 615 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
91dd6c27 616 "len=%u, rssi=%d, chnl=%d, rate=%d,\n",
fd7c8a40 617 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 618 length, rssi, channel, rate);
619 else {
620 /* src/dst addresses assume managed mode */
e1623446 621 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 622 "src=0x%02x, rssi=%u, tim=%lu usec, "
623 "phy=0x%02x, chnl=%d\n",
fd7c8a40 624 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 625 header->addr3[5], rssi,
626 tsf_low - priv->scan_start_tsf,
627 phy_flags, channel);
628 }
629 }
630 if (print_dump)
3d816c77 631 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 632}
d08853a3
SO		 633
634static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
635 struct iwl_rx_packet *pkt,
636 struct ieee80211_hdr *header, int group100)
637{
3d816c77 638 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 639 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
640}
641
17744ff6 642#else
4a8a4322 643static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 644 struct iwl_rx_packet *pkt,
17744ff6
TW		 645 struct ieee80211_hdr *header, int group100)
646{
647}
648#endif
649
4bd9b4f3 650/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 651static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 652 struct ieee80211_hdr *header)
653{
654 /* Filter incoming packets to determine if they are targeted toward
655 * this network, discarding packets coming from ourselves */
656 switch (priv->iw_mode) {
05c914fe 657 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 658 /* packets to our IBSS update information */
659 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 660 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 661 /* packets to our IBSS update information */
662 return !compare_ether_addr(header->addr2, priv->bssid);
663 default:
664 return 1;
665 }
666}
17744ff6 667
4a8a4322 668static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 669 struct iwl_rx_mem_buffer *rxb,
12342c47 670 struct ieee80211_rx_status *stats)
b481de9c 671{
2f301227 672 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 673 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 674 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
675 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 676 u16 len = le16_to_cpu(rx_hdr->len);
677 struct sk_buff *skb;
29b1b268 678 __le16 fc = hdr->frame_control;
b481de9c
ZY		 679
680 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 681 if (unlikely(len + IWL39_RX_FRAME_SIZE >
682 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 683 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 684 return;
685 }
686
687 /* We only process data packets if the interface is open */
688 if (unlikely(!priv->is_open)) {
e1623446
TW		 689 IWL_DEBUG_DROP_LIMIT(priv,
690 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 691 return;
692 }
b481de9c 693
ecdf94b8 694 skb = dev_alloc_skb(128);
2f301227 695 if (!skb) {
ecdf94b8 696 IWL_ERR(priv, "dev_alloc_skb failed\n");
2f301227
ZY		 697 return;
698 }
b481de9c 699
9c74d9fb 700 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 701 iwl_set_decrypted_flag(priv,
2f301227 702 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 703 le32_to_cpu(rx_end->status), stats);
704
2f301227
ZY		 705 skb_add_rx_frag(skb, 0, rxb->page,
706 (void *)rx_hdr->payload - (void *)pkt, len);
707
29b1b268 708 iwl_update_stats(priv, false, fc, len);
2f301227 709 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 710
29b1b268 711 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 712 priv->alloc_rxb_page--;
713 rxb->page = NULL;
b481de9c
ZY		 714}
715
7878a5a4
MA		 716#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
717
4a8a4322 718static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 719 struct iwl_rx_mem_buffer *rxb)
b481de9c 720{
17744ff6
TW		 721 struct ieee80211_hdr *header;
722 struct ieee80211_rx_status rx_status;
2f301227 723 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 724 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
725 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
726 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
f875f518
RC		 727 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
728 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
b481de9c 729 u8 network_packet;
17744ff6 730
17744ff6
TW		 731 rx_status.flag = 0;
732 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 733 rx_status.freq =
c0186078 734 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 735 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
736 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
737
738 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 739 if (rx_status.band == IEEE80211_BAND_5GHZ)
740 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 741
9024adf5 742 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 743 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
744
745 /* set the preamble flag if appropriate */
746 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
747 rx_status.flag |= RX_FLAG_SHORTPRE;
748
b481de9c 749 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 750 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
751 rx_stats->phy_count);
b481de9c
ZY		 752 return;
753 }
754
755 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
756 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 757 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 758 return;
759 }
760
56decd3c 761
b481de9c
ZY		 762
763 /* Convert 3945's rssi indicator to dBm */
250bdd21 764 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c 765
ed1b6e99
JB		 766 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
767 rx_status.signal, rx_stats_sig_avg,
768 rx_stats_noise_diff);
b481de9c 769
b481de9c
ZY		 770 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
771
bb8c093b 772 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 773
ed1b6e99 774 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
17744ff6
TW		 775 network_packet ? '*' : ' ',
776 le16_to_cpu(rx_hdr->channel),
566bfe5a 777 rx_status.signal, rx_status.signal,
ed1b6e99 778 rx_status.rate_idx);
b481de9c 779
d08853a3
SO		 780 /* Set "1" to report good data frames in groups of 100 */
781 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 782 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 783
784 if (network_packet) {
e99f168c
JB		 785 priv->_3945.last_beacon_time =
786 le32_to_cpu(rx_end->beacon_timestamp);
787 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
788 priv->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 789 }
790
12e5e22d 791 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 792}
793
7aaa1d79
SO		 794int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
795 struct iwl_tx_queue *txq,
796 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 797{
798 int count;
7aaa1d79 799 struct iwl_queue *q;
59606ffa 800 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 801
802 q = &txq->q;
59606ffa
SO		 803 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
804 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 805
806 if (reset)
807 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 808
809 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 810
811 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 812 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 813 NUM_TFD_CHUNKS);
814 return -EINVAL;
815 }
816
dbb6654c
WT		 817 tfd->tbs[count].addr = cpu_to_le32(addr);
818 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 819
820 count++;
821
822 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
823 TFD_CTL_PAD_SET(pad));
824
825 return 0;
826}
827
828/**
bb8c093b 829 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 830 *
831 * Does NOT advance any indexes
832 */
7aaa1d79 833void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 834{
59606ffa 835 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 836 int index = txq->q.read_ptr;
837 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 838 struct pci_dev *dev = priv->pci_dev;
839 int i;
840 int counter;
841
b481de9c 842 /* sanity check */
dbb6654c 843 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 844 if (counter > NUM_TFD_CHUNKS) {
15b1687c 845 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 846 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 847 return;
b481de9c
ZY		 848 }
849
fd9377ee
RC		 850 /* Unmap tx_cmd */
851 if (counter)
852 pci_unmap_single(dev,
c2acea8e
JB		 853 pci_unmap_addr(&txq->meta[index], mapping),
854 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 855 PCI_DMA_TODEVICE);
856
b481de9c
ZY		 857 /* unmap chunks if any */
858
859 for (i = 1; i < counter; i++) {
dbb6654c
WT		 860 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
861 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 862 if (txq->txb[txq->q.read_ptr].skb[0]) {
863 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
864 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 865 /* Can be called from interrupt context */
866 dev_kfree_skb_any(skb);
fc4b6853 867 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 868 }
869 }
870 }
7aaa1d79 871 return ;
b481de9c
ZY		 872}
873
b481de9c 874/**
bb8c093b 875 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 876 *
877*/
c2acea8e
JB		 878void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
879 struct iwl_device_cmd *cmd,
880 struct ieee80211_tx_info *info,
881 struct ieee80211_hdr *hdr,
882 int sta_id, int tx_id)
b481de9c 883{
e039fa4a 884 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
1d79e53c 885 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
b481de9c
ZY		 886 u16 rate_mask;
887 int rate;
888 u8 rts_retry_limit;
889 u8 data_retry_limit;
890 __le32 tx_flags;
fd7c8a40 891 __le16 fc = hdr->frame_control;
9744c91f 892 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 893
bb8c093b 894 rate = iwl3945_rates[rate_index].plcp;
9744c91f 895 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 896
897 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 898 * in this running context */
b481de9c
ZY		 899 rate_mask = IWL_RATES_MASK;
900
768db982
AK		 901
902 /* Set retry limit on DATA packets and Probe Responses*/
903 if (ieee80211_is_probe_resp(fc))
904 data_retry_limit = 3;
905 else
906 data_retry_limit = IWL_DEFAULT_TX_RETRY;
907 tx_cmd->data_retry_limit = data_retry_limit;
908
b481de9c
ZY		 909 if (tx_id >= IWL_CMD_QUEUE_NUM)
910 rts_retry_limit = 3;
911 else
912 rts_retry_limit = 7;
913
768db982
AK		 914 if (data_retry_limit < rts_retry_limit)
915 rts_retry_limit = data_retry_limit;
916 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 917
fd7c8a40
HH		 918 if (ieee80211_is_mgmt(fc)) {
919 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
920 case cpu_to_le16(IEEE80211_STYPE_AUTH):
921 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
922 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
923 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 924 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
925 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
926 tx_flags |= TX_CMD_FLG_CTS_MSK;
927 }
928 break;
929 default:
930 break;
931 }
932 }
933
9744c91f
AK		 934 tx_cmd->rate = rate;
935 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 936
937 /* OFDM */
9744c91f 938 tx_cmd->supp_rates[0] =
14577f23 939 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 940
941 /* CCK */
9744c91f 942 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 943
e1623446 944 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 945 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 946 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
947 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 948}
949
9c5ac091 950static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
b481de9c
ZY		 951{
952 unsigned long flags_spin;
c587de0b 953 struct iwl_station_entry *station;
b481de9c
ZY		 954
955 if (sta_id == IWL_INVALID_STATION)
956 return IWL_INVALID_STATION;
957
958 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 959 station = &priv->stations[sta_id];
b481de9c
ZY		 960
961 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
962 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c 963 station->sta.mode = STA_CONTROL_MODIFY_MSK;
9c5ac091 964 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
b481de9c
ZY		 965 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
966
e1623446 967 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 968 sta_id, tx_rate);
969 return sta_id;
970}
971
854682ed 972static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 973{
854682ed 974 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 975 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 976 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 977 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
978 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 979
5d49f498 980 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 981 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
982 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 983 }
b481de9c 984 } else {
5d49f498 985 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 986 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
987 ~APMG_PS_CTRL_MSK_PWR_SRC);
988
5d49f498 989 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 990 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
991 }
b481de9c 992
a8b50a0a 993 return 0;
b481de9c
ZY		 994}
995
4a8a4322 996static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 997{
5d49f498 998 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 999 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 1000 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
1001 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 1002 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
1003 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
1004 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
1005 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
1006 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
1007 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
1008 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1009 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 1010
1011 /* fake read to flush all prev I/O */
5d49f498 1012 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 1013
b481de9c
ZY		 1014 return 0;
1015}
1016
4a8a4322 1017static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 1018{
b481de9c
ZY		 1019
1020 /* bypass mode */
5d49f498 1021 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1022
1023 /* RA 0 is active */
5d49f498 1024 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1025
1026 /* all 6 fifo are active */
5d49f498 1027 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1028
5d49f498
AK		 1029 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1030 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1031 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1032 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1033
5d49f498 1034 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 1035 priv->_3945.shared_phys);
b481de9c 1036
5d49f498 1037 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1038 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1039 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1040 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1041 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1042 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1043 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1044 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1045
b481de9c
ZY		 1046
1047 return 0;
1048}
1049
1050/**
1051 * iwl3945_txq_ctx_reset - Reset TX queue context
1052 *
1053 * Destroys all DMA structures and initialize them again
1054 */
4a8a4322 1055static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1056{
1057 int rc;
1058 int txq_id, slots_num;
1059
bb8c093b 1060 iwl3945_hw_txq_ctx_free(priv);
b481de9c 1061
88804e2b
WYG		 1062 /* allocate tx queue structure */
1063 rc = iwl_alloc_txq_mem(priv);
1064 if (rc)
1065 return rc;
1066
b481de9c
ZY		 1067 /* Tx CMD queue */
1068 rc = iwl3945_tx_reset(priv);
1069 if (rc)
1070 goto error;
1071
1072 /* Tx queue(s) */
5905a1aa 1073 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 1074 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1075 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1076 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1077 txq_id);
b481de9c 1078 if (rc) {
15b1687c 1079 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1080 goto error;
1081 }
1082 }
1083
1084 return rc;
1085
1086 error:
bb8c093b 1087 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1088 return rc;
1089}
1090
fadb3582 1091
f33269b8 1092/*
fadb3582
BC		 1093 * Start up 3945's basic functionality after it has been reset
1094 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 1095 * NOTE: This does not load uCode nor start the embedded processor
1096 */
01ec616d 1097static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1098{
fadb3582 1099 int ret = iwl_apm_init(priv);
01ec616d 1100
f33269b8
BC		 1101 /* Clear APMG (NIC's internal power management) interrupts */
1102 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1103 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1104
1105 /* Reset radio chip */
1106 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1107 udelay(5);
1108 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1109
01ec616d
KA		 1110 return ret;
1111}
b481de9c 1112
01ec616d
KA		 1113static void iwl3945_nic_config(struct iwl_priv *priv)
1114{
e6148917 1115 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1116 unsigned long flags;
1117 u8 rev_id = 0;
b481de9c 1118
b481de9c
ZY		 1119 spin_lock_irqsave(&priv->lock, flags);
1120
43121432
AK		 1121 /* Determine HW type */
1122 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1123
1124 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1125
b481de9c 1126 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
91dd6c27 1127 IWL_DEBUG_INFO(priv, "RTP type\n");
b481de9c 1128 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1129 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1130 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1131 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1132 } else {
e1623446 1133 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1134 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1136 }
1137
e6148917 1138 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1139 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1140 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1141 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1142 } else
e1623446 1143 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1144
e6148917 1145 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1146 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1147 eeprom->board_revision);
5d49f498 1148 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1149 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1150 } else {
e1623446 1151 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1152 eeprom->board_revision);
5d49f498 1153 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1154 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1155 }
1156
e6148917 1157 if (eeprom->almgor_m_version <= 1) {
5d49f498 1158 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1159 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1160 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1161 eeprom->almgor_m_version);
b481de9c 1162 } else {
e1623446 1163 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1164 eeprom->almgor_m_version);
5d49f498 1165 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1166 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1167 }
1168 spin_unlock_irqrestore(&priv->lock, flags);
1169
e6148917 1170 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1171 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1172
e6148917 1173 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1174 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1175}
1176
1177int iwl3945_hw_nic_init(struct iwl_priv *priv)
1178{
01ec616d
KA		 1179 int rc;
1180 unsigned long flags;
1181 struct iwl_rx_queue *rxq = &priv->rxq;
1182
1183 spin_lock_irqsave(&priv->lock, flags);
1184 priv->cfg->ops->lib->apm_ops.init(priv);
1185 spin_unlock_irqrestore(&priv->lock, flags);
1186
854682ed 1187 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1188 if (rc)
854682ed
KA		 1189 return rc;
1190
01ec616d 1191 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1192
1193 /* Allocate the RX queue, or reset if it is already allocated */
1194 if (!rxq->bd) {
51af3d3f 1195 rc = iwl_rx_queue_alloc(priv);
b481de9c 1196 if (rc) {
15b1687c 1197 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1198 return -ENOMEM;
1199 }
1200 } else
df833b1d 1201 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1202
bb8c093b 1203 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1204
1205 iwl3945_rx_init(priv, rxq);
1206
b481de9c
ZY		 1207
1208 /* Look at using this instead:
1209 rxq->need_update = 1;
141c43a3 1210 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1211 */
1212
5d49f498 1213 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1214
1215 rc = iwl3945_txq_ctx_reset(priv);
1216 if (rc)
1217 return rc;
1218
1219 set_bit(STATUS_INIT, &priv->status);
1220
1221 return 0;
1222}
1223
1224/**
bb8c093b 1225 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1226 *
1227 * Destroy all TX DMA queues and structures
1228 */
4a8a4322 1229void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1230{
1231 int txq_id;
1232
1233 /* Tx queues */
88804e2b
WYG		 1234 if (priv->txq)
1235 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1236 txq_id++)
1237 if (txq_id == IWL_CMD_QUEUE_NUM)
1238 iwl_cmd_queue_free(priv);
1239 else
1240 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1241
88804e2b
WYG		 1242 /* free tx queue structure */
1243 iwl_free_txq_mem(priv);
b481de9c
ZY		 1244}
1245
4a8a4322 1246void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1247{
bddadf86 1248 int txq_id;
b481de9c
ZY		 1249
1250 /* stop SCD */
5d49f498 1251 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1252 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1253
1254 /* reset TFD queues */
5905a1aa 1255 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1256 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1257 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1258 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1259 1000);
1260 }
1261
bb8c093b 1262 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1263}
1264
b481de9c 1265/**
bb8c093b 1266 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1267 * return index delta into power gain settings table
1268*/
bb8c093b 1269static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1270{
1271 return (new_reading - old_reading) * (-11) / 100;
1272}
1273
1274/**
bb8c093b 1275 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1276 */
bb8c093b 1277static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1278{
3ac7f146 1279 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1280}
1281
4a8a4322 1282int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1283{
5d49f498 1284 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1285}
1286
1287/**
bb8c093b 1288 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1289 * get the current temperature by reading from NIC
1290*/
4a8a4322 1291static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1292{
e6148917 1293 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1294 int temperature;
1295
bb8c093b 1296 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1297
1298 /* driver's okay range is -260 to +25.
1299 * human readable okay range is 0 to +285 */
e1623446 1300 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1301
1302 /* handle insane temp reading */
bb8c093b 1303 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1304 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1305
1306 /* if really really hot(?),
1307 * substitute the 3rd band/group's temp measured at factory */
1308 if (priv->last_temperature > 100)
e6148917 1309 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1310 else /* else use most recent "sane" value from driver */
1311 temperature = priv->last_temperature;
1312 }
1313
1314 return temperature; /* raw, not "human readable" */
1315}
1316
1317/* Adjust Txpower only if temperature variance is greater than threshold.
1318 *
1319 * Both are lower than older versions' 9 degrees */
1320#define IWL_TEMPERATURE_LIMIT_TIMER 6
1321
1322/**
1323 * is_temp_calib_needed - determines if new calibration is needed
1324 *
1325 * records new temperature in tx_mgr->temperature.
1326 * replaces tx_mgr->last_temperature *only* if calib needed
1327 * (assumes caller will actually do the calibration!). */
4a8a4322 1328static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1329{
1330 int temp_diff;
1331
bb8c093b 1332 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1333 temp_diff = priv->temperature - priv->last_temperature;
1334
1335 /* get absolute value */
1336 if (temp_diff < 0) {
e1623446 1337 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1338 temp_diff = -temp_diff;
1339 } else if (temp_diff == 0)
e1623446 1340 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1341 else
e1623446 1342 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1343
1344 /* if we don't need calibration, *don't* update last_temperature */
1345 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1346 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1347 return 0;
1348 }
1349
e1623446 1350 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1351
1352 /* assume that caller will actually do calib ...
1353 * update the "last temperature" value */
1354 priv->last_temperature = priv->temperature;
1355 return 1;
1356}
1357
1358#define IWL_MAX_GAIN_ENTRIES 78
1359#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1360#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1361
1362/* radio and DSP power table, each step is 1/2 dB.
1363 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1364static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1365 {
1366 {251, 127}, /* 2.4 GHz, highest power */
1367 {251, 127},
1368 {251, 127},
1369 {251, 127},
1370 {251, 125},
1371 {251, 110},
1372 {251, 105},
1373 {251, 98},
1374 {187, 125},
1375 {187, 115},
1376 {187, 108},
1377 {187, 99},
1378 {243, 119},
1379 {243, 111},
1380 {243, 105},
1381 {243, 97},
1382 {243, 92},
1383 {211, 106},
1384 {211, 100},
1385 {179, 120},
1386 {179, 113},
1387 {179, 107},
1388 {147, 125},
1389 {147, 119},
1390 {147, 112},
1391 {147, 106},
1392 {147, 101},
1393 {147, 97},
1394 {147, 91},
1395 {115, 107},
1396 {235, 121},
1397 {235, 115},
1398 {235, 109},
1399 {203, 127},
1400 {203, 121},
1401 {203, 115},
1402 {203, 108},
1403 {203, 102},
1404 {203, 96},
1405 {203, 92},
1406 {171, 110},
1407 {171, 104},
1408 {171, 98},
1409 {139, 116},
1410 {227, 125},
1411 {227, 119},
1412 {227, 113},
1413 {227, 107},
1414 {227, 101},
1415 {227, 96},
1416 {195, 113},
1417 {195, 106},
1418 {195, 102},
1419 {195, 95},
1420 {163, 113},
1421 {163, 106},
1422 {163, 102},
1423 {163, 95},
1424 {131, 113},
1425 {131, 106},
1426 {131, 102},
1427 {131, 95},
1428 {99, 113},
1429 {99, 106},
1430 {99, 102},
1431 {99, 95},
1432 {67, 113},
1433 {67, 106},
1434 {67, 102},
1435 {67, 95},
1436 {35, 113},
1437 {35, 106},
1438 {35, 102},
1439 {35, 95},
1440 {3, 113},
1441 {3, 106},
1442 {3, 102},
1443 {3, 95} }, /* 2.4 GHz, lowest power */
1444 {
1445 {251, 127}, /* 5.x GHz, highest power */
1446 {251, 120},
1447 {251, 114},
1448 {219, 119},
1449 {219, 101},
1450 {187, 113},
1451 {187, 102},
1452 {155, 114},
1453 {155, 103},
1454 {123, 117},
1455 {123, 107},
1456 {123, 99},
1457 {123, 92},
1458 {91, 108},
1459 {59, 125},
1460 {59, 118},
1461 {59, 109},
1462 {59, 102},
1463 {59, 96},
1464 {59, 90},
1465 {27, 104},
1466 {27, 98},
1467 {27, 92},
1468 {115, 118},
1469 {115, 111},
1470 {115, 104},
1471 {83, 126},
1472 {83, 121},
1473 {83, 113},
1474 {83, 105},
1475 {83, 99},
1476 {51, 118},
1477 {51, 111},
1478 {51, 104},
1479 {51, 98},
1480 {19, 116},
1481 {19, 109},
1482 {19, 102},
1483 {19, 98},
1484 {19, 93},
1485 {171, 113},
1486 {171, 107},
1487 {171, 99},
1488 {139, 120},
1489 {139, 113},
1490 {139, 107},
1491 {139, 99},
1492 {107, 120},
1493 {107, 113},
1494 {107, 107},
1495 {107, 99},
1496 {75, 120},
1497 {75, 113},
1498 {75, 107},
1499 {75, 99},
1500 {43, 120},
1501 {43, 113},
1502 {43, 107},
1503 {43, 99},
1504 {11, 120},
1505 {11, 113},
1506 {11, 107},
1507 {11, 99},
1508 {131, 107},
1509 {131, 99},
1510 {99, 120},
1511 {99, 113},
1512 {99, 107},
1513 {99, 99},
1514 {67, 120},
1515 {67, 113},
1516 {67, 107},
1517 {67, 99},
1518 {35, 120},
1519 {35, 113},
1520 {35, 107},
1521 {35, 99},
1522 {3, 120} } /* 5.x GHz, lowest power */
1523};
1524
bb8c093b 1525static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1526{
1527 if (index < 0)
1528 return 0;
1529 if (index >= IWL_MAX_GAIN_ENTRIES)
1530 return IWL_MAX_GAIN_ENTRIES - 1;
1531 return (u8) index;
1532}
1533
1534/* Kick off thermal recalibration check every 60 seconds */
1535#define REG_RECALIB_PERIOD (60)
1536
1537/**
bb8c093b 1538 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1539 *
1540 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1541 * or 6 Mbit (OFDM) rates.
1542 */
4a8a4322 1543static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1544 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1545 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1546 int band_index)
1547{
bb8c093b 1548 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1549 s8 power;
1550 u8 power_index;
1551
1552 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1553
1554 /* use this channel group's 6Mbit clipping/saturation pwr,
1555 * but cap at regulatory scan power restriction (set during init
1556 * based on eeprom channel data) for this channel. */
14577f23 1557 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1558
1559 /* further limit to user's max power preference.
1560 * FIXME: Other spectrum management power limitations do not
1561 * seem to apply?? */
62ea9c5b 1562 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1563 scan_power_info->requested_power = power;
1564
1565 /* find difference between new scan *power* and current "normal"
1566 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1567 * current "normal" temperature-compensated Tx power *index* for
1568 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1569 * *index*. */
1570 power_index = ch_info->power_info[rate_index].power_table_index
1571 - (power - ch_info->power_info
14577f23 1572 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1573
1574 /* store reference index that we use when adjusting *all* scan
1575 * powers. So we can accommodate user (all channel) or spectrum
1576 * management (single channel) power changes "between" temperature
1577 * feedback compensation procedures.
1578 * don't force fit this reference index into gain table; it may be a
1579 * negative number. This will help avoid errors when we're at
1580 * the lower bounds (highest gains, for warmest temperatures)
1581 * of the table. */
1582
1583 /* don't exceed table bounds for "real" setting */
bb8c093b 1584 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1585
1586 scan_power_info->power_table_index = power_index;
1587 scan_power_info->tpc.tx_gain =
1588 power_gain_table[band_index][power_index].tx_gain;
1589 scan_power_info->tpc.dsp_atten =
1590 power_gain_table[band_index][power_index].dsp_atten;
1591}
1592
1593/**
75bcfae9 1594 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1595 *
1596 * Configures power settings for all rates for the current channel,
1597 * using values from channel info struct, and send to NIC
1598 */
dfb39e82 1599static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1600{
14577f23 1601 int rate_idx, i;
d20b3c65 1602 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1603 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1604 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1605 };
1606
8318d78a 1607 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1608 ch_info = iwl_get_channel_info(priv,
8318d78a 1609 priv->band,
8ccde88a 1610 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1611 if (!ch_info) {
15b1687c
WT		 1612 IWL_ERR(priv,
1613 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1614 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1615 return -EINVAL;
1616 }
1617
1618 if (!is_channel_valid(ch_info)) {
e1623446 1619 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1620 "non-Tx channel.\n");
1621 return 0;
1622 }
1623
1624 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1625 /* Fill OFDM rate */
1626 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1627 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1628
1629 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1630 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1631
e1623446 1632 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1633 le16_to_cpu(txpower.channel),
1634 txpower.band,
14577f23
MA		 1635 txpower.power[i].tpc.tx_gain,
1636 txpower.power[i].tpc.dsp_atten,
1637 txpower.power[i].rate);
1638 }
1639 /* Fill CCK rates */
1640 for (rate_idx = IWL_FIRST_CCK_RATE;
1641 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1642 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1643 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1644
e1623446 1645 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1646 le16_to_cpu(txpower.channel),
1647 txpower.band,
1648 txpower.power[i].tpc.tx_gain,
1649 txpower.power[i].tpc.dsp_atten,
1650 txpower.power[i].rate);
b481de9c
ZY		 1651 }
1652
518099a8
SO		 1653 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1654 sizeof(struct iwl3945_txpowertable_cmd),
1655 &txpower);
b481de9c
ZY		 1656
1657}
1658
1659/**
bb8c093b 1660 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1661 * @ch_info: Channel to update. Uses power_info.requested_power.
1662 *
1663 * Replace requested_power and base_power_index ch_info fields for
1664 * one channel.
1665 *
1666 * Called if user or spectrum management changes power preferences.
1667 * Takes into account h/w and modulation limitations (clip power).
1668 *
1669 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1670 *
1671 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1672 * properly fill out the scan powers, and actual h/w gain settings,
1673 * and send changes to NIC
1674 */
4a8a4322 1675static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1676 struct iwl_channel_info *ch_info)
b481de9c 1677{
bb8c093b 1678 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1679 int power_changed = 0;
1680 int i;
1681 const s8 *clip_pwrs;
1682 int power;
1683
1684 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1685 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1686
1687 /* Get this channel's rate-to-current-power settings table */
1688 power_info = ch_info->power_info;
1689
1690 /* update OFDM Txpower settings */
14577f23 1691 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1692 i++, ++power_info) {
1693 int delta_idx;
1694
1695 /* limit new power to be no more than h/w capability */
1696 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1697 if (power == power_info->requested_power)
1698 continue;
1699
1700 /* find difference between old and new requested powers,
1701 * update base (non-temp-compensated) power index */
1702 delta_idx = (power - power_info->requested_power) * 2;
1703 power_info->base_power_index -= delta_idx;
1704
1705 /* save new requested power value */
1706 power_info->requested_power = power;
1707
1708 power_changed = 1;
1709 }
1710
1711 /* update CCK Txpower settings, based on OFDM 12M setting ...
1712 * ... all CCK power settings for a given channel are the *same*. */
1713 if (power_changed) {
1714 power =
14577f23 1715 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1716 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1717
bb8c093b 1718 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1719 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1720 power_info->requested_power = power;
1721 power_info->base_power_index =
14577f23 1722 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1723 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1724 ++power_info;
1725 }
1726 }
1727
1728 return 0;
1729}
1730
1731/**
bb8c093b 1732 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1733 *
1734 * NOTE: Returned power limit may be less (but not more) than requested,
1735 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1736 * (no consideration for h/w clipping limitations).
1737 */
d20b3c65 1738static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1739{
1740 s8 max_power;
1741
1742#if 0
1743 /* if we're using TGd limits, use lower of TGd or EEPROM */
1744 if (ch_info->tgd_data.max_power != 0)
1745 max_power = min(ch_info->tgd_data.max_power,
1746 ch_info->eeprom.max_power_avg);
1747
1748 /* else just use EEPROM limits */
1749 else
1750#endif
1751 max_power = ch_info->eeprom.max_power_avg;
1752
1753 return min(max_power, ch_info->max_power_avg);
1754}
1755
1756/**
bb8c093b 1757 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1758 *
1759 * Compensate txpower settings of *all* channels for temperature.
1760 * This only accounts for the difference between current temperature
1761 * and the factory calibration temperatures, and bases the new settings
1762 * on the channel's base_power_index.
1763 *
1764 * If RxOn is "associated", this sends the new Txpower to NIC!
1765 */
4a8a4322 1766static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1767{
d20b3c65 1768 struct iwl_channel_info *ch_info = NULL;
e6148917 1769 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1770 int delta_index;
1771 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1772 u8 a_band;
1773 u8 rate_index;
1774 u8 scan_tbl_index;
1775 u8 i;
1776 int ref_temp;
1777 int temperature = priv->temperature;
1778
4e7033ef
WYG		 1779 if (priv->disable_tx_power_cal ||
1780 test_bit(STATUS_SCANNING, &priv->status)) {
1781 /* do not perform tx power calibration */
1782 return 0;
1783 }
b481de9c
ZY		 1784 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1785 for (i = 0; i < priv->channel_count; i++) {
1786 ch_info = &priv->channel_info[i];
1787 a_band = is_channel_a_band(ch_info);
1788
1789 /* Get this chnlgrp's factory calibration temperature */
e6148917 1790 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1791 temperature;
1792
a96a27f9 1793 /* get power index adjustment based on current and factory
b481de9c 1794 * temps */
bb8c093b 1795 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1796 ref_temp);
1797
1798 /* set tx power value for all rates, OFDM and CCK */
1799 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1800 rate_index++) {
1801 int power_idx =
1802 ch_info->power_info[rate_index].base_power_index;
1803
1804 /* temperature compensate */
1805 power_idx += delta_index;
1806
1807 /* stay within table range */
bb8c093b 1808 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1809 ch_info->power_info[rate_index].
1810 power_table_index = (u8) power_idx;
1811 ch_info->power_info[rate_index].tpc =
1812 power_gain_table[a_band][power_idx];
1813 }
1814
1815 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1816 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1817
1818 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1819 for (scan_tbl_index = 0;
1820 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1821 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1822 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1823 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1824 actual_index, clip_pwrs,
1825 ch_info, a_band);
1826 }
1827 }
1828
1829 /* send Txpower command for current channel to ucode */
75bcfae9 1830 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1831}
1832
4a8a4322 1833int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1834{
d20b3c65 1835 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1836 s8 max_power;
1837 u8 a_band;
1838 u8 i;
1839
62ea9c5b 1840 if (priv->tx_power_user_lmt == power) {
e1623446 1841 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1842 "limit: %ddBm.\n", power);
1843 return 0;
1844 }
1845
e1623446 1846 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1847 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1848
1849 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1850
1851 for (i = 0; i < priv->channel_count; i++) {
1852 ch_info = &priv->channel_info[i];
1853 a_band = is_channel_a_band(ch_info);
1854
1855 /* find minimum power of all user and regulatory constraints
1856 * (does not consider h/w clipping limitations) */
bb8c093b 1857 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1858 max_power = min(power, max_power);
1859 if (max_power != ch_info->curr_txpow) {
1860 ch_info->curr_txpow = max_power;
1861
1862 /* this considers the h/w clipping limitations */
bb8c093b 1863 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1864 }
1865 }
1866
1867 /* update txpower settings for all channels,
1868 * send to NIC if associated. */
1869 is_temp_calib_needed(priv);
bb8c093b 1870 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1871
1872 return 0;
1873}
1874
5bbe233b
AK		 1875static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1876{
1877 int rc = 0;
2f301227 1878 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1879 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1880 struct iwl_host_cmd cmd = {
1881 .id = REPLY_RXON_ASSOC,
1882 .len = sizeof(rxon_assoc),
c2acea8e 1883 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1884 .data = &rxon_assoc,
1885 };
1886 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1887 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1888
1889 if ((rxon1->flags == rxon2->flags) &&
1890 (rxon1->filter_flags == rxon2->filter_flags) &&
1891 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1892 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1893 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1894 return 0;
1895 }
1896
1897 rxon_assoc.flags = priv->staging_rxon.flags;
1898 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1899 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1900 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1901 rxon_assoc.reserved = 0;
1902
1903 rc = iwl_send_cmd_sync(priv, &cmd);
1904 if (rc)
1905 return rc;
1906
2f301227
ZY		 1907 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1908 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1909 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1910 rc = -EIO;
1911 }
1912
64a76b50 1913 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1914
1915 return rc;
1916}
1917
e0158e61
AK		 1918/**
1919 * iwl3945_commit_rxon - commit staging_rxon to hardware
1920 *
1921 * The RXON command in staging_rxon is committed to the hardware and
1922 * the active_rxon structure is updated with the new data. This
1923 * function correctly transitions out of the RXON_ASSOC_MSK state if
1924 * a HW tune is required based on the RXON structure changes.
1925 */
1926static int iwl3945_commit_rxon(struct iwl_priv *priv)
1927{
1928 /* cast away the const for active_rxon in this function */
1929 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1930 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1931 int rc = 0;
1932 bool new_assoc =
1933 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1934
1935 if (!iwl_is_alive(priv))
1936 return -1;
1937
1938 /* always get timestamp with Rx frame */
1939 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1940
1941 /* select antenna */
1942 staging_rxon->flags &=
1943 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1944 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1945
1946 rc = iwl_check_rxon_cmd(priv);
1947 if (rc) {
1948 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1949 return -EINVAL;
1950 }
1951
1952 /* If we don't need to send a full RXON, we can use
1953 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1954 * and other flags for the current radio configuration. */
1955 if (!iwl_full_rxon_required(priv)) {
1956 rc = iwl_send_rxon_assoc(priv);
1957 if (rc) {
1958 IWL_ERR(priv, "Error setting RXON_ASSOC "
1959 "configuration (%d).\n", rc);
1960 return rc;
1961 }
1962
1963 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1964
1965 return 0;
1966 }
1967
1968 /* If we are currently associated and the new config requires
1969 * an RXON_ASSOC and the new config wants the associated mask enabled,
1970 * we must clear the associated from the active configuration
1971 * before we apply the new config */
1972 if (iwl_is_associated(priv) && new_assoc) {
1973 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1974 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1975
1976 /*
1977 * reserved4 and 5 could have been filled by the iwlcore code.
1978 * Let's clear them before pushing to the 3945.
1979 */
1980 active_rxon->reserved4 = 0;
1981 active_rxon->reserved5 = 0;
1982 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1983 sizeof(struct iwl3945_rxon_cmd),
1984 &priv->active_rxon);
1985
1986 /* If the mask clearing failed then we set
1987 * active_rxon back to what it was previously */
1988 if (rc) {
1989 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1990 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1991 "configuration (%d).\n", rc);
1992 return rc;
1993 }
2c810ccd 1994 iwl_clear_ucode_stations(priv);
7e246191 1995 iwl_restore_stations(priv);
e0158e61
AK		 1996 }
1997
1998 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1999 "* with%s RXON_FILTER_ASSOC_MSK\n"
2000 "* channel = %d\n"
2001 "* bssid = %pM\n",
2002 (new_assoc ? "" : "out"),
2003 le16_to_cpu(staging_rxon->channel),
2004 staging_rxon->bssid_addr);
2005
2006 /*
2007 * reserved4 and 5 could have been filled by the iwlcore code.
2008 * Let's clear them before pushing to the 3945.
2009 */
2010 staging_rxon->reserved4 = 0;
2011 staging_rxon->reserved5 = 0;
2012
90e8e424 2013 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 2014
2015 /* Apply the new configuration */
2016 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
2017 sizeof(struct iwl3945_rxon_cmd),
2018 staging_rxon);
2019 if (rc) {
2020 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
2021 return rc;
2022 }
2023
2024 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2025
7e246191 2026 if (!new_assoc) {
2c810ccd 2027 iwl_clear_ucode_stations(priv);
7e246191
RC		 2028 iwl_restore_stations(priv);
2029 }
e0158e61
AK		 2030
2031 /* If we issue a new RXON command which required a tune then we must
2032 * send a new TXPOWER command or we won't be able to Tx any frames */
2033 rc = priv->cfg->ops->lib->send_tx_power(priv);
2034 if (rc) {
2035 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2036 return rc;
2037 }
2038
e0158e61
AK		 2039 /* Init the hardware's rate fallback order based on the band */
2040 rc = iwl3945_init_hw_rate_table(priv);
2041 if (rc) {
2042 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2043 return -EIO;
2044 }
2045
2046 return 0;
2047}
2048
b481de9c
ZY		 2049/**
2050 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2051 *
2052 * -- reset periodic timer
2053 * -- see if temp has changed enough to warrant re-calibration ... if so:
2054 * -- correct coeffs for temp (can reset temp timer)
2055 * -- save this temp as "last",
2056 * -- send new set of gain settings to NIC
2057 * NOTE: This should continue working, even when we're not associated,
2058 * so we can keep our internal table of scan powers current. */
4a8a4322 2059void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2060{
2061 /* This will kick in the "brute force"
bb8c093b 2062 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2063 if (!is_temp_calib_needed(priv))
2064 goto reschedule;
2065
2066 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2067 * This is based *only* on current temperature,
2068 * ignoring any previous power measurements */
bb8c093b 2069 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2070
2071 reschedule:
2072 queue_delayed_work(priv->workqueue,
ee525d13 2073 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 2074}
2075
416e1438 2076static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2077{
4a8a4322 2078 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 2079 _3945.thermal_periodic.work);
b481de9c
ZY		 2080
2081 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2082 return;
2083
2084 mutex_lock(&priv->mutex);
2085 iwl3945_reg_txpower_periodic(priv);
2086 mutex_unlock(&priv->mutex);
2087}
2088
2089/**
bb8c093b 2090 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2091 * for the channel.
2092 *
2093 * This function is used when initializing channel-info structs.
2094 *
2095 * NOTE: These channel groups do *NOT* match the bands above!
2096 * These channel groups are based on factory-tested channels;
2097 * on A-band, EEPROM's "group frequency" entries represent the top
2098 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2099 */
4a8a4322 2100static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2101 const struct iwl_channel_info *ch_info)
b481de9c 2102{
e6148917
SO		 2103 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2104 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2105 u8 group;
2106 u16 group_index = 0; /* based on factory calib frequencies */
2107 u8 grp_channel;
2108
2109 /* Find the group index for the channel ... don't use index 1(?) */
2110 if (is_channel_a_band(ch_info)) {
2111 for (group = 1; group < 5; group++) {
2112 grp_channel = ch_grp[group].group_channel;
2113 if (ch_info->channel <= grp_channel) {
2114 group_index = group;
2115 break;
2116 }
2117 }
2118 /* group 4 has a few channels *above* its factory cal freq */
2119 if (group == 5)
2120 group_index = 4;
2121 } else
2122 group_index = 0; /* 2.4 GHz, group 0 */
2123
e1623446 2124 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2125 group_index);
2126 return group_index;
2127}
2128
2129/**
bb8c093b 2130 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2131 *
2132 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2133 * into radio/DSP gain settings table for requested power.
2134 */
4a8a4322 2135static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2136 s8 requested_power,
2137 s32 setting_index, s32 *new_index)
2138{
bb8c093b 2139 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2140 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2141 s32 index0, index1;
2142 s32 power = 2 * requested_power;
2143 s32 i;
bb8c093b 2144 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2145 s32 gains0, gains1;
2146 s32 res;
2147 s32 denominator;
2148
e6148917 2149 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2150 samples = chnl_grp->samples;
2151 for (i = 0; i < 5; i++) {
2152 if (power == samples[i].power) {
2153 *new_index = samples[i].gain_index;
2154 return 0;
2155 }
2156 }
2157
2158 if (power > samples[1].power) {
2159 index0 = 0;
2160 index1 = 1;
2161 } else if (power > samples[2].power) {
2162 index0 = 1;
2163 index1 = 2;
2164 } else if (power > samples[3].power) {
2165 index0 = 2;
2166 index1 = 3;
2167 } else {
2168 index0 = 3;
2169 index1 = 4;
2170 }
2171
2172 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2173 if (denominator == 0)
2174 return -EINVAL;
2175 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2176 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2177 res = gains0 + (gains1 - gains0) *
2178 ((s32) power - (s32) samples[index0].power) / denominator +
2179 (1 << 18);
2180 *new_index = res >> 19;
2181 return 0;
2182}
2183
4a8a4322 2184static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2185{
2186 u32 i;
2187 s32 rate_index;
e6148917 2188 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2189 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2190
e1623446 2191 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2192
2193 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2194 s8 *clip_pwrs; /* table of power levels for each rate */
2195 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2196 group = &eeprom->groups[i];
b481de9c
ZY		 2197
2198 /* sanity check on factory saturation power value */
2199 if (group->saturation_power < 40) {
39aadf8c 2200 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2201 "less than minimum expected 40\n",
2202 group->saturation_power);
2203 return;
2204 }
2205
2206 /*
2207 * Derive requested power levels for each rate, based on
2208 * hardware capabilities (saturation power for band).
2209 * Basic value is 3dB down from saturation, with further
2210 * power reductions for highest 3 data rates. These
2211 * backoffs provide headroom for high rate modulation
2212 * power peaks, without too much distortion (clipping).
2213 */
2214 /* we'll fill in this array with h/w max power levels */
67d613ae 2215 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2216
2217 /* divide factory saturation power by 2 to find -3dB level */
2218 satur_pwr = (s8) (group->saturation_power >> 1);
2219
2220 /* fill in channel group's nominal powers for each rate */
2221 for (rate_index = 0;
1d79e53c 2222 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
b481de9c 2223 switch (rate_index) {
14577f23 2224 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2225 if (i == 0) /* B/G */
2226 *clip_pwrs = satur_pwr;
2227 else /* A */
2228 *clip_pwrs = satur_pwr - 5;
2229 break;
14577f23 2230 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2231 if (i == 0)
2232 *clip_pwrs = satur_pwr - 7;
2233 else
2234 *clip_pwrs = satur_pwr - 10;
2235 break;
14577f23 2236 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2237 if (i == 0)
2238 *clip_pwrs = satur_pwr - 9;
2239 else
2240 *clip_pwrs = satur_pwr - 12;
2241 break;
2242 default:
2243 *clip_pwrs = satur_pwr;
2244 break;
2245 }
2246 }
2247 }
2248}
2249
2250/**
2251 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2252 *
2253 * Second pass (during init) to set up priv->channel_info
2254 *
2255 * Set up Tx-power settings in our channel info database for each VALID
2256 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2257 * and current temperature.
2258 *
2259 * Since this is based on current temperature (at init time), these values may
2260 * not be valid for very long, but it gives us a starting/default point,
2261 * and allows us to active (i.e. using Tx) scan.
2262 *
2263 * This does *not* write values to NIC, just sets up our internal table.
2264 */
4a8a4322 2265int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2266{
d20b3c65 2267 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2268 struct iwl3945_channel_power_info *pwr_info;
e6148917 2269 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2270 int delta_index;
2271 u8 rate_index;
2272 u8 scan_tbl_index;
2273 const s8 *clip_pwrs; /* array of power levels for each rate */
2274 u8 gain, dsp_atten;
2275 s8 power;
2276 u8 pwr_index, base_pwr_index, a_band;
2277 u8 i;
2278 int temperature;
2279
2280 /* save temperature reference,
2281 * so we can determine next time to calibrate */
bb8c093b 2282 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2283 priv->last_temperature = temperature;
2284
bb8c093b 2285 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2286
2287 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2288 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2289 i++, ch_info++) {
2290 a_band = is_channel_a_band(ch_info);
2291 if (!is_channel_valid(ch_info))
2292 continue;
2293
2294 /* find this channel's channel group (*not* "band") index */
2295 ch_info->group_index =
bb8c093b 2296 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2297
2298 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2299 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2300
2301 /* calculate power index *adjustment* value according to
2302 * diff between current temperature and factory temperature */
bb8c093b 2303 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2304 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2305 temperature);
2306
e1623446 2307 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2308 ch_info->channel, delta_index, temperature +
2309 IWL_TEMP_CONVERT);
2310
2311 /* set tx power value for all OFDM rates */
2312 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2313 rate_index++) {
25a4ccea 2314 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2315 int rc;
2316
2317 /* use channel group's clip-power table,
2318 * but don't exceed channel's max power */
2319 s8 pwr = min(ch_info->max_power_avg,
2320 clip_pwrs[rate_index]);
2321
2322 pwr_info = &ch_info->power_info[rate_index];
2323
2324 /* get base (i.e. at factory-measured temperature)
2325 * power table index for this rate's power */
bb8c093b 2326 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2327 ch_info->group_index,
2328 &power_idx);
2329 if (rc) {
15b1687c 2330 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2331 return rc;
2332 }
2333 pwr_info->base_power_index = (u8) power_idx;
2334
2335 /* temperature compensate */
2336 power_idx += delta_index;
2337
2338 /* stay within range of gain table */
bb8c093b 2339 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2340
bb8c093b 2341 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2342 pwr_info->requested_power = pwr;
2343 pwr_info->power_table_index = (u8) power_idx;
2344 pwr_info->tpc.tx_gain =
2345 power_gain_table[a_band][power_idx].tx_gain;
2346 pwr_info->tpc.dsp_atten =
2347 power_gain_table[a_band][power_idx].dsp_atten;
2348 }
2349
2350 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2351 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2352 power = pwr_info->requested_power +
2353 IWL_CCK_FROM_OFDM_POWER_DIFF;
2354 pwr_index = pwr_info->power_table_index +
2355 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2356 base_pwr_index = pwr_info->base_power_index +
2357 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2358
2359 /* stay within table range */
bb8c093b 2360 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2361 gain = power_gain_table[a_band][pwr_index].tx_gain;
2362 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2363
bb8c093b 2364 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2365 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2366 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2367 for (rate_index = 0;
2368 rate_index < IWL_CCK_RATES; rate_index++) {
2369 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2370 pwr_info->requested_power = power;
2371 pwr_info->power_table_index = pwr_index;
2372 pwr_info->base_power_index = base_pwr_index;
2373 pwr_info->tpc.tx_gain = gain;
2374 pwr_info->tpc.dsp_atten = dsp_atten;
2375 }
2376
2377 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2378 for (scan_tbl_index = 0;
2379 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2380 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2381 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2382 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2383 actual_index, clip_pwrs, ch_info, a_band);
2384 }
2385 }
2386
2387 return 0;
2388}
2389
4a8a4322 2390int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2391{
2392 int rc;
b481de9c 2393
5d49f498
AK		 2394 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2395 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2396 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2397 if (rc < 0)
15b1687c 2398 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2399
b481de9c
ZY		 2400 return 0;
2401}
2402
188cf6c7 2403int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2404{
b481de9c
ZY		 2405 int txq_id = txq->q.id;
2406
ee525d13 2407 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2408
2409 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2410
5d49f498
AK		 2411 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2412 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2413
5d49f498 2414 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2415 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2416 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2417 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2418 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2419 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2420
2421 /* fake read to flush all prev. writes */
5d49f498 2422 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2423
2424 return 0;
2425}
2426
42427b4e
KA		 2427/*
2428 * HCMD utils
2429 */
2430static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2431{
2432 switch (cmd_id) {
2433 case REPLY_RXON:
d25aabb0
WT		 2434 return sizeof(struct iwl3945_rxon_cmd);
2435 case POWER_TABLE_CMD:
2436 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2437 default:
2438 return len;
2439 }
2440}
2441
c587de0b 2442
17f841cd
SO		 2443static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2444{
c587de0b
TW		 2445 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2446 addsta->mode = cmd->mode;
2447 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2448 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2449 addsta->station_flags = cmd->station_flags;
2450 addsta->station_flags_msk = cmd->station_flags_msk;
2451 addsta->tid_disable_tx = cpu_to_le16(0);
2452 addsta->rate_n_flags = cmd->rate_n_flags;
2453 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2454 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2455 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2456
2457 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2458}
2459
1fa61b2e
JB		 2460static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2461 struct ieee80211_vif *vif, bool add)
2462{
fd1af15d 2463 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1fa61b2e
JB		 2464 int ret;
2465
1fa61b2e 2466 if (add) {
57f8db89 2467 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false,
fd1af15d 2468 &vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2469 if (ret)
2470 return ret;
2471
fd1af15d 2472 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
1fa61b2e 2473 (priv->band == IEEE80211_BAND_5GHZ) ?
9c5ac091 2474 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
fd1af15d 2475 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2476
2477 return 0;
2478 }
2479
fd1af15d
JB		 2480 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2481 vif->bss_conf.bssid);
1fa61b2e 2482}
c587de0b 2483
b481de9c
ZY		 2484/**
2485 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2486 */
4a8a4322 2487int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2488{
14577f23 2489 int rc, i, index, prev_index;
bb8c093b 2490 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2491 .reserved = {0, 0, 0},
2492 };
bb8c093b 2493 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2494
bb8c093b
CH		 2495 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2496 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2497
2498 table[index].rate_n_flags =
bb8c093b 2499 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2500 table[index].try_cnt = priv->retry_rate;
bb8c093b 2501 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2502 table[index].next_rate_index =
2503 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2504 }
2505
8318d78a
JB		 2506 switch (priv->band) {
2507 case IEEE80211_BAND_5GHZ:
e1623446 2508 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2509 /* If one of the following CCK rates is used,
2510 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2511 for (i = IWL_RATE_1M_INDEX_TABLE;
2512 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2513 table[i].next_rate_index =
2514 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2515
2516 /* Don't fall back to CCK rates */
7262796a
AM		 2517 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2518 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2519
2520 /* Don't drop out of OFDM rates */
14577f23 2521 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2522 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2523 break;
2524
8318d78a 2525 case IEEE80211_BAND_2GHZ:
e1623446 2526 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2527 /* If an OFDM rate is used, have it fall back to the
2528 * 1M CCK rates */
b481de9c 2529
ee525d13 2530 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2531 iwl_is_associated(priv)) {
7262796a
AM		 2532
2533 index = IWL_FIRST_CCK_RATE;
2534 for (i = IWL_RATE_6M_INDEX_TABLE;
2535 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2536 table[i].next_rate_index =
2537 iwl3945_rates[index].table_rs_index;
2538
2539 index = IWL_RATE_11M_INDEX_TABLE;
2540 /* CCK shouldn't fall back to OFDM... */
2541 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2542 }
b481de9c
ZY		 2543 break;
2544
2545 default:
8318d78a 2546 WARN_ON(1);
b481de9c
ZY		 2547 break;
2548 }
2549
2550 /* Update the rate scaling for control frame Tx */
2551 rate_cmd.table_id = 0;
518099a8 2552 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2553 &rate_cmd);
2554 if (rc)
2555 return rc;
2556
2557 /* Update the rate scaling for data frame Tx */
2558 rate_cmd.table_id = 1;
518099a8 2559 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2560 &rate_cmd);
2561}
2562
796083cb 2563/* Called when initializing driver */
4a8a4322 2564int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2565{
3832ec9d
AK		 2566 memset((void *)&priv->hw_params, 0,
2567 sizeof(struct iwl_hw_params));
b481de9c 2568
ee525d13
JB		 2569 priv->_3945.shared_virt =
2570 dma_alloc_coherent(&priv->pci_dev->dev,
2571 sizeof(struct iwl3945_shared),
2572 &priv->_3945.shared_phys, GFP_KERNEL);
2573 if (!priv->_3945.shared_virt) {
15b1687c 2574 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2575 return -ENOMEM;
2576 }
2577
21c02a1a 2578 /* Assign number of Usable TX queues */
88804e2b 2579 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2580
a8e74e27 2581 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2582 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2583 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2584 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2585 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2586 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2587
141c43a3 2588 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2589 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2590
b481de9c
ZY		 2591 return 0;
2592}
2593
4a8a4322 2594unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2595 struct iwl3945_frame *frame, u8 rate)
b481de9c 2596{
bb8c093b 2597 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2598 unsigned int frame_size;
2599
bb8c093b 2600 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2601 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2602
3832ec9d 2603 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2604 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2605
bb8c093b 2606 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2607 tx_beacon_cmd->frame,
b481de9c
ZY		 2608 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2609
2610 BUG_ON(frame_size > MAX_MPDU_SIZE);
2611 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2612
2613 tx_beacon_cmd->tx.rate = rate;
2614 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2615 TX_CMD_FLG_TSF_MSK);
2616
14577f23
MA		 2617 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2618 tx_beacon_cmd->tx.supp_rates[0] =
2619 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2620
b481de9c 2621 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2622 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2623
3ac7f146 2624 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2625}
2626
4a8a4322 2627void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2628{
91c066f2 2629 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2630 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2631}
2632
4a8a4322 2633void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2634{
ee525d13 2635 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2636 iwl3945_bg_reg_txpower_periodic);
2637}
2638
4a8a4322 2639void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2640{
ee525d13 2641 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2642}
2643
0164b9b4
KA		 2644/* check contents of special bootstrap uCode SRAM */
2645static int iwl3945_verify_bsm(struct iwl_priv *priv)
2646 {
2647 __le32 *image = priv->ucode_boot.v_addr;
2648 u32 len = priv->ucode_boot.len;
2649 u32 reg;
2650 u32 val;
2651
e1623446 2652 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2653
2654 /* verify BSM SRAM contents */
2655 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2656 for (reg = BSM_SRAM_LOWER_BOUND;
2657 reg < BSM_SRAM_LOWER_BOUND + len;
2658 reg += sizeof(u32), image++) {
2659 val = iwl_read_prph(priv, reg);
2660 if (val != le32_to_cpu(*image)) {
2661 IWL_ERR(priv, "BSM uCode verification failed at "
2662 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2663 BSM_SRAM_LOWER_BOUND,
2664 reg - BSM_SRAM_LOWER_BOUND, len,
2665 val, le32_to_cpu(*image));
2666 return -EIO;
2667 }
2668 }
2669
e1623446 2670 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2671
2672 return 0;
2673}
2674
e6148917
SO		 2675
2676/******************************************************************************
2677 *
2678 * EEPROM related functions
2679 *
2680 ******************************************************************************/
2681
2682/*
2683 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2684 * embedded controller) as EEPROM reader; each read is a series of pulses
2685 * to/from the EEPROM chip, not a single event, so even reads could conflict
2686 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2687 * simply claims ownership, which should be safe when this function is called
2688 * (i.e. before loading uCode!).
2689 */
2690static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2691{
2692 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2693 return 0;
2694}
2695
2696
2697static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2698{
2699 return;
2700}
2701
0164b9b4
KA		 2702 /**
2703 * iwl3945_load_bsm - Load bootstrap instructions
2704 *
2705 * BSM operation:
2706 *
2707 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2708 * in special SRAM that does not power down during RFKILL. When powering back
2709 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2710 * the bootstrap program into the on-board processor, and starts it.
2711 *
2712 * The bootstrap program loads (via DMA) instructions and data for a new
2713 * program from host DRAM locations indicated by the host driver in the
2714 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2715 * automatically.
2716 *
2717 * When initializing the NIC, the host driver points the BSM to the
2718 * "initialize" uCode image. This uCode sets up some internal data, then
2719 * notifies host via "initialize alive" that it is complete.
2720 *
2721 * The host then replaces the BSM_DRAM_* pointer values to point to the
2722 * normal runtime uCode instructions and a backup uCode data cache buffer
2723 * (filled initially with starting data values for the on-board processor),
2724 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2725 * which begins normal operation.
2726 *
2727 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2728 * the backup data cache in DRAM before SRAM is powered down.
2729 *
2730 * When powering back up, the BSM loads the bootstrap program. This reloads
2731 * the runtime uCode instructions and the backup data cache into SRAM,
2732 * and re-launches the runtime uCode from where it left off.
2733 */
2734static int iwl3945_load_bsm(struct iwl_priv *priv)
2735{
2736 __le32 *image = priv->ucode_boot.v_addr;
2737 u32 len = priv->ucode_boot.len;
2738 dma_addr_t pinst;
2739 dma_addr_t pdata;
2740 u32 inst_len;
2741 u32 data_len;
2742 int rc;
2743 int i;
2744 u32 done;
2745 u32 reg_offset;
2746
e1623446 2747 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2748
2749 /* make sure bootstrap program is no larger than BSM's SRAM size */
2750 if (len > IWL39_MAX_BSM_SIZE)
2751 return -EINVAL;
2752
2753 /* Tell bootstrap uCode where to find the "Initialize" uCode
2754 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2755 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2756 * after the "initialize" uCode has run, to point to
2757 * runtime/protocol instructions and backup data cache. */
2758 pinst = priv->ucode_init.p_addr;
2759 pdata = priv->ucode_init_data.p_addr;
2760 inst_len = priv->ucode_init.len;
2761 data_len = priv->ucode_init_data.len;
2762
0164b9b4
KA		 2763 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2764 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2765 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2766 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2767
2768 /* Fill BSM memory with bootstrap instructions */
2769 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2770 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2771 reg_offset += sizeof(u32), image++)
2772 _iwl_write_prph(priv, reg_offset,
2773 le32_to_cpu(*image));
2774
2775 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2776 if (rc)
0164b9b4 2777 return rc;
0164b9b4
KA		 2778
2779 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2780 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2781 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2782 IWL39_RTC_INST_LOWER_BOUND);
2783 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2784
2785 /* Load bootstrap code into instruction SRAM now,
2786 * to prepare to load "initialize" uCode */
2787 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2788 BSM_WR_CTRL_REG_BIT_START);
2789
2790 /* Wait for load of bootstrap uCode to finish */
2791 for (i = 0; i < 100; i++) {
2792 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2793 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2794 break;
2795 udelay(10);
2796 }
2797 if (i < 100)
e1623446 2798 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2799 else {
2800 IWL_ERR(priv, "BSM write did not complete!\n");
2801 return -EIO;
2802 }
2803
2804 /* Enable future boot loads whenever power management unit triggers it
2805 * (e.g. when powering back up after power-save shutdown) */
2806 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2807 BSM_WR_CTRL_REG_BIT_START_EN);
2808
0164b9b4
KA		 2809 return 0;
2810}
2811
5bbe233b
AK		 2812static struct iwl_hcmd_ops iwl3945_hcmd = {
2813 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2814 .commit_rxon = iwl3945_commit_rxon,
65b52bde 2815 .send_bt_config = iwl_send_bt_config,
5bbe233b
AK		 2816};
2817
0164b9b4 2818static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2819 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2820 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2821 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2822 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2823 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2824 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2825 .apm_ops = {
2826 .init = iwl3945_apm_init,
d68b603c 2827 .stop = iwl_apm_stop,
01ec616d 2828 .config = iwl3945_nic_config,
854682ed 2829 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2830 },
e6148917
SO		 2831 .eeprom_ops = {
2832 .regulatory_bands = {
2833 EEPROM_REGULATORY_BAND_1_CHANNELS,
2834 EEPROM_REGULATORY_BAND_2_CHANNELS,
2835 EEPROM_REGULATORY_BAND_3_CHANNELS,
2836 EEPROM_REGULATORY_BAND_4_CHANNELS,
2837 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2838 EEPROM_REGULATORY_BAND_NO_HT40,
2839 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2840 },
2841 .verify_signature = iwlcore_eeprom_verify_signature,
2842 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2843 .release_semaphore = iwl3945_eeprom_release_semaphore,
2844 .query_addr = iwlcore_eeprom_query_addr,
2845 },
75bcfae9 2846 .send_tx_power = iwl3945_send_tx_power,
c2436980 2847 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2848 .post_associate = iwl3945_post_associate,
ef850d7c 2849 .isr = iwl_isr_legacy,
60690a6a 2850 .config_ap = iwl3945_config_ap,
1fa61b2e 2851 .manage_ibss_station = iwl3945_manage_ibss_station,
a29576a7 2852 .check_plcp_health = iwl3945_good_plcp_health,
17f36fc6
AK		 2853
2854 .debugfs_ops = {
2855 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2856 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2857 .general_stats_read = iwl3945_ucode_general_stats_read,
2858 },
0164b9b4
KA		 2859};
2860
42427b4e
KA		 2861static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2862 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2863 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2864 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
b6e4c55a 2865 .request_scan = iwl3945_request_scan,
42427b4e
KA		 2866};
2867
45d5d805 2868static const struct iwl_ops iwl3945_ops = {
0164b9b4 2869 .lib = &iwl3945_lib,
5bbe233b 2870 .hcmd = &iwl3945_hcmd,
42427b4e 2871 .utils = &iwl3945_hcmd_utils,
e932a609 2872 .led = &iwl3945_led_ops,
0164b9b4
KA		 2873};
2874
c0f20d91 2875static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2876 .name = "3945BG",
a0987a8d
RC		 2877 .fw_name_pre = IWL3945_FW_PRE,
2878 .ucode_api_max = IWL3945_UCODE_API_MAX,
2879 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2880 .sku = IWL_SKU_G,
e6148917
SO		 2881 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2882 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2883 .ops = &iwl3945_ops,
88804e2b 2884 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2885 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2886 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2887 .set_l0s = false,
2888 .use_bsm = true,
b261793d
DH		 2889 .use_isr_legacy = true,
2890 .ht_greenfield_support = false,
f2d0d0e2 2891 .led_compensation = 64,
bc45a670 2892 .broken_powersave = true,
a29576a7 2893 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
b74e31a9 2894 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2895 .max_event_log_size = 512,
4e7033ef 2896 .tx_power_by_driver = true,
82b9a121
TW		 2897};
2898
c0f20d91 2899static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2900 .name = "3945ABG",
a0987a8d
RC		 2901 .fw_name_pre = IWL3945_FW_PRE,
2902 .ucode_api_max = IWL3945_UCODE_API_MAX,
2903 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2904 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2905 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2906 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2907 .ops = &iwl3945_ops,
88804e2b 2908 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2909 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2910 .use_isr_legacy = true,
2911 .ht_greenfield_support = false,
f2d0d0e2 2912 .led_compensation = 64,
bc45a670 2913 .broken_powersave = true,
a29576a7 2914 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
b74e31a9 2915 .monitor_recover_period = IWL_MONITORING_PERIOD,
678b385d 2916 .max_event_log_size = 512,
4e7033ef 2917 .tx_power_by_driver = true,
82b9a121
TW		 2918};
2919
a3aa1884 2920DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2921 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2922 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2923 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2924 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2925 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2926 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2927 {0}
2928};
2929
bb8c093b 2930MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree