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Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c 29#include <linux/init.h>
5a0e3ad6 30#include <linux/slab.h>
b481de9c
ZY		 31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
d43c36dc 34#include <linux/sched.h>
b481de9c
ZY		 35#include <linux/skbuff.h>
36#include <linux/netdevice.h>
37#include <linux/wireless.h>
38#include <linux/firmware.h>
b481de9c 39#include <linux/etherdevice.h>
12342c47
ZY		 40#include <asm/unaligned.h>
41#include <net/mac80211.h>
b481de9c 42
dbb6654c 43#include "iwl-fh.h"
bddadf86 44#include "iwl-3945-fh.h"
600c0e11 45#include "iwl-commands.h"
17f841cd 46#include "iwl-sta.h"
b481de9c 47#include "iwl-3945.h"
e6148917 48#include "iwl-eeprom.h"
5747d47f 49#include "iwl-core.h"
4a6547c7 50#include "iwl-helpers.h"
e932a609
JB		 51#include "iwl-led.h"
52#include "iwl-3945-led.h"
17f36fc6 53#include "iwl-3945-debugfs.h"
b481de9c
ZY		 54
55#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
57 IWL_RATE_##r##M_IEEE, \
58 IWL_RATE_##ip##M_INDEX, \
59 IWL_RATE_##in##M_INDEX, \
60 IWL_RATE_##rp##M_INDEX, \
61 IWL_RATE_##rn##M_INDEX, \
62 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 63 IWL_RATE_##np##M_INDEX, \
64 IWL_RATE_##r##M_INDEX_TABLE, \
65 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 66
67/*
68 * Parameter order:
69 * rate, prev rate, next rate, prev tgg rate, next tgg rate
70 *
71 * If there isn't a valid next or previous rate then INV is used which
72 * maps to IWL_RATE_INVALID
73 *
74 */
d9829a67 75const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 88};
89
bb8c093b 90/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 91#define IWL_EVT_DISABLE (0)
92#define IWL_EVT_DISABLE_SIZE (1532/32)
93
94/**
bb8c093b 95 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 96 *
97 * Disable an event by writing "1"s into "disable"
98 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
99 * Default values of 0 enable uCode events to be logged.
100 * Use for only special debugging. This function is just a placeholder as-is,
101 * you'll need to provide the special bits! ...
102 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 103void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 104{
b481de9c
ZY		 105 int i;
106 u32 base; /* SRAM address of event log header */
107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
108 u32 array_size; /* # of u32 entries in array */
109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
110 0x00000000, /* 31 - 0 Event id numbers */
111 0x00000000, /* 63 - 32 */
112 0x00000000, /* 95 - 64 */
113 0x00000000, /* 127 - 96 */
114 0x00000000, /* 159 - 128 */
115 0x00000000, /* 191 - 160 */
116 0x00000000, /* 223 - 192 */
117 0x00000000, /* 255 - 224 */
118 0x00000000, /* 287 - 256 */
119 0x00000000, /* 319 - 288 */
120 0x00000000, /* 351 - 320 */
121 0x00000000, /* 383 - 352 */
122 0x00000000, /* 415 - 384 */
123 0x00000000, /* 447 - 416 */
124 0x00000000, /* 479 - 448 */
125 0x00000000, /* 511 - 480 */
126 0x00000000, /* 543 - 512 */
127 0x00000000, /* 575 - 544 */
128 0x00000000, /* 607 - 576 */
129 0x00000000, /* 639 - 608 */
130 0x00000000, /* 671 - 640 */
131 0x00000000, /* 703 - 672 */
132 0x00000000, /* 735 - 704 */
133 0x00000000, /* 767 - 736 */
134 0x00000000, /* 799 - 768 */
135 0x00000000, /* 831 - 800 */
136 0x00000000, /* 863 - 832 */
137 0x00000000, /* 895 - 864 */
138 0x00000000, /* 927 - 896 */
139 0x00000000, /* 959 - 928 */
140 0x00000000, /* 991 - 960 */
141 0x00000000, /* 1023 - 992 */
142 0x00000000, /* 1055 - 1024 */
143 0x00000000, /* 1087 - 1056 */
144 0x00000000, /* 1119 - 1088 */
145 0x00000000, /* 1151 - 1120 */
146 0x00000000, /* 1183 - 1152 */
147 0x00000000, /* 1215 - 1184 */
148 0x00000000, /* 1247 - 1216 */
149 0x00000000, /* 1279 - 1248 */
150 0x00000000, /* 1311 - 1280 */
151 0x00000000, /* 1343 - 1312 */
152 0x00000000, /* 1375 - 1344 */
153 0x00000000, /* 1407 - 1376 */
154 0x00000000, /* 1439 - 1408 */
155 0x00000000, /* 1471 - 1440 */
156 0x00000000, /* 1503 - 1472 */
157 };
158
159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 160 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 167
168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 170 disable_ptr);
b481de9c 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 172 iwl_write_targ_mem(priv,
af7cca2a
TW		 173 disable_ptr + (i * sizeof(u32)),
174 evt_disable[i]);
b481de9c 175
b481de9c 176 } else {
e1623446
TW		 177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 180 disable_ptr, array_size);
181 }
182
183}
184
17744ff6
TW		 185static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
186{
187 int idx;
188
1d79e53c 189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++)
17744ff6
TW		 190 if (iwl3945_rates[idx].plcp == plcp)
191 return idx;
192 return -1;
193}
194
d08853a3 195#ifdef CONFIG_IWLWIFI_DEBUG
04569cbe 196#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x
91c066f2
TW		 197
198static const char *iwl3945_get_tx_fail_reason(u32 status)
199{
200 switch (status & TX_STATUS_MSK) {
04569cbe 201 case TX_3945_STATUS_SUCCESS:
91c066f2
TW		 202 return "SUCCESS";
203 TX_STATUS_ENTRY(SHORT_LIMIT);
204 TX_STATUS_ENTRY(LONG_LIMIT);
205 TX_STATUS_ENTRY(FIFO_UNDERRUN);
206 TX_STATUS_ENTRY(MGMNT_ABORT);
207 TX_STATUS_ENTRY(NEXT_FRAG);
208 TX_STATUS_ENTRY(LIFE_EXPIRE);
209 TX_STATUS_ENTRY(DEST_PS);
210 TX_STATUS_ENTRY(ABORTED);
211 TX_STATUS_ENTRY(BT_RETRY);
212 TX_STATUS_ENTRY(STA_INVALID);
213 TX_STATUS_ENTRY(FRAG_DROPPED);
214 TX_STATUS_ENTRY(TID_DISABLE);
215 TX_STATUS_ENTRY(FRAME_FLUSHED);
216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
217 TX_STATUS_ENTRY(TX_LOCKED);
218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
219 }
220
221 return "UNKNOWN";
222}
223#else
224static inline const char *iwl3945_get_tx_fail_reason(u32 status)
225{
226 return "";
227}
228#endif
229
e6a9854b
JB		 230/*
231 * get ieee prev rate from rate scale table.
232 * for A and B mode we need to overright prev
233 * value
234 */
4a8a4322 235int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 236{
237 int next_rate = iwl3945_get_prev_ieee_rate(rate);
238
239 switch (priv->band) {
240 case IEEE80211_BAND_5GHZ:
241 if (rate == IWL_RATE_12M_INDEX)
242 next_rate = IWL_RATE_9M_INDEX;
243 else if (rate == IWL_RATE_6M_INDEX)
244 next_rate = IWL_RATE_6M_INDEX;
245 break;
7262796a 246 case IEEE80211_BAND_2GHZ:
ee525d13 247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 248 iwl_is_associated(priv)) {
7262796a
AM		 249 if (rate == IWL_RATE_11M_INDEX)
250 next_rate = IWL_RATE_5M_INDEX;
251 }
e6a9854b 252 break;
7262796a 253
e6a9854b
JB		 254 default:
255 break;
256 }
257
258 return next_rate;
259}
260
91c066f2
TW		 261
262/**
263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
264 *
265 * When FW advances 'R' index, all entries between old and new 'R' index
266 * need to be reclaimed. As result, some free space forms. If there is
267 * enough free space (> low mark), wake the stack that feeds us.
268 */
4a8a4322 269static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 270 int txq_id, int index)
271{
188cf6c7 272 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 273 struct iwl_queue *q = &txq->q;
dbb6654c 274 struct iwl_tx_info *tx_info;
91c066f2
TW		 275
276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
277
278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
280
281 tx_info = &txq->txb[txq->q.read_ptr];
ff0d91c3
JB		 282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb);
283 tx_info->skb = NULL;
7aaa1d79 284 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 285 }
286
d20b3c65 287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 288 (txq_id != IWL_CMD_QUEUE_NUM) &&
289 priv->mac80211_registered)
e4e72fb4 290 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 291}
292
293/**
294 * iwl3945_rx_reply_tx - Handle Tx response
295 */
4a8a4322 296static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
17f36fc6 297 struct iwl_rx_mem_buffer *rxb)
91c066f2 298{
2f301227 299 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 300 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
301 int txq_id = SEQ_TO_QUEUE(sequence);
302 int index = SEQ_TO_INDEX(sequence);
188cf6c7 303 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 304 struct ieee80211_tx_info *info;
91c066f2
TW		 305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
306 u32 status = le32_to_cpu(tx_resp->status);
307 int rate_idx;
74221d07 308 int fail;
91c066f2 309
625a381a 310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 312 "is out of range [0-%d] %d %d\n", txq_id,
313 index, txq->q.n_bd, txq->q.write_ptr,
314 txq->q.read_ptr);
315 return;
316 }
317
ff0d91c3 318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
e6a9854b
JB		 319 ieee80211_tx_info_clear_status(info);
320
321 /* Fill the MRR chain with some info about on-chip retransmissions */
322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
323 if (info->band == IEEE80211_BAND_5GHZ)
324 rate_idx -= IWL_FIRST_OFDM_RATE;
325
326 fail = tx_resp->failure_frame;
74221d07
AM		 327
328 info->status.rates[0].idx = rate_idx;
329 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 330
91c066f2 331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
333 IEEE80211_TX_STAT_ACK : 0;
91c066f2 334
e1623446 335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 336 txq_id, iwl3945_get_tx_fail_reason(status), status,
337 tx_resp->rate, tx_resp->failure_frame);
338
e1623446 339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 340 iwl3945_tx_queue_reclaim(priv, txq_id, index);
341
342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 344}
345
346
347
b481de9c
ZY		 348/*****************************************************************************
349 *
350 * Intel PRO/Wireless 3945ABG/BG Network Connection
351 *
352 * RX handler implementations
353 *
b481de9c 354 *****************************************************************************/
d73e4923 355#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 356/*
357 * based on the assumption of all statistics counter are in DWORD
358 * FIXME: This function is for debugging, do not deal with
359 * the case of counters roll-over.
360 */
361static void iwl3945_accumulative_statistics(struct iwl_priv *priv,
362 __le32 *stats)
363{
364 int i;
365 __le32 *prev_stats;
366 u32 *accum_stats;
367 u32 *delta, *max_delta;
368
369 prev_stats = (__le32 *)&priv->_3945.statistics;
370 accum_stats = (u32 *)&priv->_3945.accum_statistics;
371 delta = (u32 *)&priv->_3945.delta_statistics;
372 max_delta = (u32 *)&priv->_3945.max_delta;
373
374 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics);
375 i += sizeof(__le32), stats++, prev_stats++, delta++,
376 max_delta++, accum_stats++) {
377 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) {
378 *delta = (le32_to_cpu(*stats) -
379 le32_to_cpu(*prev_stats));
380 *accum_stats += *delta;
381 if (*delta > *max_delta)
382 *max_delta = *delta;
383 }
384 }
385
386 /* reset accumulative statistics for "no-counter" type statistics */
387 priv->_3945.accum_statistics.general.temperature =
388 priv->_3945.statistics.general.temperature;
389 priv->_3945.accum_statistics.general.ttl_timestamp =
390 priv->_3945.statistics.general.ttl_timestamp;
391}
392#endif
b481de9c 393
a29576a7
AK		 394/**
395 * iwl3945_good_plcp_health - checks for plcp error.
396 *
397 * When the plcp error is exceeding the thresholds, reset the radio
398 * to improve the throughput.
399 */
400static bool iwl3945_good_plcp_health(struct iwl_priv *priv,
401 struct iwl_rx_packet *pkt)
402{
403 bool rc = true;
404 struct iwl3945_notif_statistics current_stat;
405 int combined_plcp_delta;
406 unsigned int plcp_msec;
407 unsigned long plcp_received_jiffies;
408
680788ac
WYG		 409 if (priv->cfg->plcp_delta_threshold ==
410 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) {
411 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n");
412 return rc;
413 }
a29576a7
AK		 414 memcpy(&current_stat, pkt->u.raw, sizeof(struct
415 iwl3945_notif_statistics));
416 /*
417 * check for plcp_err and trigger radio reset if it exceeds
418 * the plcp error threshold plcp_delta.
419 */
420 plcp_received_jiffies = jiffies;
421 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies -
422 (long) priv->plcp_jiffies);
423 priv->plcp_jiffies = plcp_received_jiffies;
424 /*
425 * check to make sure plcp_msec is not 0 to prevent division
426 * by zero.
427 */
428 if (plcp_msec) {
429 combined_plcp_delta =
430 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) -
431 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err));
432
433 if ((combined_plcp_delta > 0) &&
434 ((combined_plcp_delta * 100) / plcp_msec) >
435 priv->cfg->plcp_delta_threshold) {
436 /*
437 * if plcp_err exceed the threshold, the following
438 * data is printed in csv format:
439 * Text: plcp_err exceeded %d,
440 * Received ofdm.plcp_err,
441 * Current ofdm.plcp_err,
442 * combined_plcp_delta,
443 * plcp_msec
444 */
445 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, "
446 "%u, %d, %u mSecs\n",
447 priv->cfg->plcp_delta_threshold,
448 le32_to_cpu(current_stat.rx.ofdm.plcp_err),
449 combined_plcp_delta, plcp_msec);
450 /*
451 * Reset the RF radio due to the high plcp
452 * error rate
453 */
454 rc = false;
455 }
456 }
457 return rc;
458}
459
396887a2
DH		 460void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
461 struct iwl_rx_mem_buffer *rxb)
b481de9c 462{
2f301227 463 struct iwl_rx_packet *pkt = rxb_addr(rxb);
17f36fc6 464
e1623446 465 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 466 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 467 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
d73e4923 468#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 469 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw);
470#endif
a29576a7 471 iwl_recover_from_statistics(priv, pkt);
b481de9c 472
ee525d13 473 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 474}
475
17f36fc6
AK		 476void iwl3945_reply_statistics(struct iwl_priv *priv,
477 struct iwl_rx_mem_buffer *rxb)
478{
479 struct iwl_rx_packet *pkt = rxb_addr(rxb);
480 __le32 *flag = (__le32 *)&pkt->u.raw;
481
482 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) {
d73e4923 483#ifdef CONFIG_IWLWIFI_DEBUGFS
17f36fc6
AK		 484 memset(&priv->_3945.accum_statistics, 0,
485 sizeof(struct iwl3945_notif_statistics));
486 memset(&priv->_3945.delta_statistics, 0,
487 sizeof(struct iwl3945_notif_statistics));
488 memset(&priv->_3945.max_delta, 0,
489 sizeof(struct iwl3945_notif_statistics));
490#endif
491 IWL_DEBUG_RX(priv, "Statistics have been cleared\n");
492 }
493 iwl3945_hw_rx_statistics(priv, rxb);
494}
495
496
17744ff6
TW		 497/******************************************************************************
498 *
499 * Misc. internal state and helper functions
500 *
501 ******************************************************************************/
17744ff6 502
4bd9b4f3 503/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 504static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 505 struct ieee80211_hdr *header)
506{
507 /* Filter incoming packets to determine if they are targeted toward
508 * this network, discarding packets coming from ourselves */
509 switch (priv->iw_mode) {
05c914fe 510 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 511 /* packets to our IBSS update information */
512 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 513 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 514 /* packets to our IBSS update information */
515 return !compare_ether_addr(header->addr2, priv->bssid);
516 default:
517 return 1;
518 }
519}
17744ff6 520
4a8a4322 521static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 522 struct iwl_rx_mem_buffer *rxb,
12342c47 523 struct ieee80211_rx_status *stats)
b481de9c 524{
2f301227 525 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 526 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 527 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
528 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 529 u16 len = le16_to_cpu(rx_hdr->len);
530 struct sk_buff *skb;
29b1b268 531 __le16 fc = hdr->frame_control;
b481de9c
ZY		 532
533 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 534 if (unlikely(len + IWL39_RX_FRAME_SIZE >
535 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 536 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 537 return;
538 }
539
540 /* We only process data packets if the interface is open */
541 if (unlikely(!priv->is_open)) {
e1623446
TW		 542 IWL_DEBUG_DROP_LIMIT(priv,
543 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 544 return;
545 }
b481de9c 546
ecdf94b8 547 skb = dev_alloc_skb(128);
2f301227 548 if (!skb) {
ecdf94b8 549 IWL_ERR(priv, "dev_alloc_skb failed\n");
2f301227
ZY		 550 return;
551 }
b481de9c 552
9c74d9fb 553 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 554 iwl_set_decrypted_flag(priv,
2f301227 555 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 556 le32_to_cpu(rx_end->status), stats);
557
2f301227
ZY		 558 skb_add_rx_frag(skb, 0, rxb->page,
559 (void *)rx_hdr->payload - (void *)pkt, len);
560
29b1b268 561 iwl_update_stats(priv, false, fc, len);
2f301227 562 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 563
29b1b268 564 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 565 priv->alloc_rxb_page--;
566 rxb->page = NULL;
b481de9c
ZY		 567}
568
7878a5a4
MA		 569#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
570
4a8a4322 571static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 572 struct iwl_rx_mem_buffer *rxb)
b481de9c 573{
17744ff6
TW		 574 struct ieee80211_hdr *header;
575 struct ieee80211_rx_status rx_status;
2f301227 576 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 577 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
578 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
579 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
f875f518
RC		 580 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg);
581 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff);
b481de9c 582 u8 network_packet;
17744ff6 583
17744ff6
TW		 584 rx_status.flag = 0;
585 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 586 rx_status.freq =
c0186078 587 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 588 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
589 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
590
591 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 592 if (rx_status.band == IEEE80211_BAND_5GHZ)
593 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 594
9024adf5 595 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 596 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
597
598 /* set the preamble flag if appropriate */
599 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
600 rx_status.flag |= RX_FLAG_SHORTPRE;
601
b481de9c 602 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 603 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
604 rx_stats->phy_count);
b481de9c
ZY		 605 return;
606 }
607
608 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
609 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 610 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 611 return;
612 }
613
56decd3c 614
b481de9c
ZY		 615
616 /* Convert 3945's rssi indicator to dBm */
250bdd21 617 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c 618
ed1b6e99
JB		 619 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n",
620 rx_status.signal, rx_stats_sig_avg,
621 rx_stats_noise_diff);
b481de9c 622
b481de9c
ZY		 623 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
624
bb8c093b 625 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 626
ed1b6e99 627 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n",
17744ff6
TW		 628 network_packet ? '*' : ' ',
629 le16_to_cpu(rx_hdr->channel),
566bfe5a 630 rx_status.signal, rx_status.signal,
ed1b6e99 631 rx_status.rate_idx);
b481de9c 632
20594eb0 633 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 634
635 if (network_packet) {
e99f168c
JB		 636 priv->_3945.last_beacon_time =
637 le32_to_cpu(rx_end->beacon_timestamp);
638 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
639 priv->_3945.last_rx_rssi = rx_status.signal;
b481de9c
ZY		 640 }
641
12e5e22d 642 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 643}
644
7aaa1d79
SO		 645int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
646 struct iwl_tx_queue *txq,
647 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 648{
649 int count;
7aaa1d79 650 struct iwl_queue *q;
59606ffa 651 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 652
653 q = &txq->q;
59606ffa
SO		 654 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
655 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 656
657 if (reset)
658 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 659
660 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 661
662 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 663 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 664 NUM_TFD_CHUNKS);
665 return -EINVAL;
666 }
667
dbb6654c
WT		 668 tfd->tbs[count].addr = cpu_to_le32(addr);
669 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 670
671 count++;
672
673 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
674 TFD_CTL_PAD_SET(pad));
675
676 return 0;
677}
678
679/**
bb8c093b 680 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 681 *
682 * Does NOT advance any indexes
683 */
7aaa1d79 684void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 685{
59606ffa 686 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 687 int index = txq->q.read_ptr;
688 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 689 struct pci_dev *dev = priv->pci_dev;
690 int i;
691 int counter;
692
b481de9c 693 /* sanity check */
dbb6654c 694 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 695 if (counter > NUM_TFD_CHUNKS) {
15b1687c 696 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 697 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 698 return;
b481de9c
ZY		 699 }
700
fd9377ee
RC		 701 /* Unmap tx_cmd */
702 if (counter)
703 pci_unmap_single(dev,
2e724443
FT		 704 dma_unmap_addr(&txq->meta[index], mapping),
705 dma_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 706 PCI_DMA_TODEVICE);
707
b481de9c
ZY		 708 /* unmap chunks if any */
709
ff0d91c3 710 for (i = 1; i < counter; i++)
dbb6654c
WT		 711 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
712 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
4f5fa237 713
ff0d91c3
JB		 714 /* free SKB */
715 if (txq->txb) {
716 struct sk_buff *skb;
4f5fa237 717
ff0d91c3
JB		 718 skb = txq->txb[txq->q.read_ptr].skb;
719
720 /* can be called from irqs-disabled context */
721 if (skb) {
722 dev_kfree_skb_any(skb);
723 txq->txb[txq->q.read_ptr].skb = NULL;
b481de9c
ZY		 724 }
725 }
b481de9c
ZY		 726}
727
b481de9c 728/**
bb8c093b 729 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 730 *
731*/
c2acea8e
JB		 732void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
733 struct iwl_device_cmd *cmd,
734 struct ieee80211_tx_info *info,
735 struct ieee80211_hdr *hdr,
736 int sta_id, int tx_id)
b481de9c 737{
e039fa4a 738 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
1d79e53c 739 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945);
b481de9c
ZY		 740 u16 rate_mask;
741 int rate;
742 u8 rts_retry_limit;
743 u8 data_retry_limit;
744 __le32 tx_flags;
fd7c8a40 745 __le16 fc = hdr->frame_control;
9744c91f 746 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 747
bb8c093b 748 rate = iwl3945_rates[rate_index].plcp;
9744c91f 749 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 750
751 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 752 * in this running context */
b481de9c
ZY		 753 rate_mask = IWL_RATES_MASK;
754
768db982
AK		 755
756 /* Set retry limit on DATA packets and Probe Responses*/
757 if (ieee80211_is_probe_resp(fc))
758 data_retry_limit = 3;
759 else
760 data_retry_limit = IWL_DEFAULT_TX_RETRY;
761 tx_cmd->data_retry_limit = data_retry_limit;
762
b481de9c
ZY		 763 if (tx_id >= IWL_CMD_QUEUE_NUM)
764 rts_retry_limit = 3;
765 else
766 rts_retry_limit = 7;
767
768db982
AK		 768 if (data_retry_limit < rts_retry_limit)
769 rts_retry_limit = data_retry_limit;
770 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 771
9744c91f
AK		 772 tx_cmd->rate = rate;
773 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 774
775 /* OFDM */
9744c91f 776 tx_cmd->supp_rates[0] =
14577f23 777 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 778
779 /* CCK */
9744c91f 780 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 781
e1623446 782 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 783 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 784 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
785 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 786}
787
9c5ac091 788static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate)
b481de9c
ZY		 789{
790 unsigned long flags_spin;
c587de0b 791 struct iwl_station_entry *station;
b481de9c
ZY		 792
793 if (sta_id == IWL_INVALID_STATION)
794 return IWL_INVALID_STATION;
795
796 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 797 station = &priv->stations[sta_id];
b481de9c
ZY		 798
799 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
800 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c 801 station->sta.mode = STA_CONTROL_MODIFY_MSK;
9c5ac091 802 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC);
b481de9c
ZY		 803 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
804
e1623446 805 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 806 sta_id, tx_rate);
807 return sta_id;
808}
809
854682ed 810static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 811{
854682ed 812 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 813 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 814 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 815 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
816 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 817
5d49f498 818 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 819 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
820 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 821 }
b481de9c 822 } else {
5d49f498 823 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 824 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
825 ~APMG_PS_CTRL_MSK_PWR_SRC);
826
5d49f498 827 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 828 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
829 }
b481de9c 830
a8b50a0a 831 return 0;
b481de9c
ZY		 832}
833
4a8a4322 834static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 835{
d5b25c90 836 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma);
8cd812bc 837 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 838 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
839 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 840 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
841 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
842 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
843 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
844 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
845 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
846 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
847 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 848
849 /* fake read to flush all prev I/O */
5d49f498 850 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 851
b481de9c
ZY		 852 return 0;
853}
854
4a8a4322 855static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 856{
b481de9c
ZY		 857
858 /* bypass mode */
5d49f498 859 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 860
861 /* RA 0 is active */
5d49f498 862 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 863
864 /* all 6 fifo are active */
5d49f498 865 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 866
5d49f498
AK		 867 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
868 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
869 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
870 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 871
5d49f498 872 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 873 priv->_3945.shared_phys);
b481de9c 874
5d49f498 875 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 876 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
877 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
878 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
879 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
880 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
881 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
882 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 883
b481de9c
ZY		 884
885 return 0;
886}
887
888/**
889 * iwl3945_txq_ctx_reset - Reset TX queue context
890 *
891 * Destroys all DMA structures and initialize them again
892 */
4a8a4322 893static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 894{
895 int rc;
896 int txq_id, slots_num;
897
bb8c093b 898 iwl3945_hw_txq_ctx_free(priv);
b481de9c 899
88804e2b
WYG		 900 /* allocate tx queue structure */
901 rc = iwl_alloc_txq_mem(priv);
902 if (rc)
903 return rc;
904
b481de9c
ZY		 905 /* Tx CMD queue */
906 rc = iwl3945_tx_reset(priv);
907 if (rc)
908 goto error;
909
910 /* Tx queue(s) */
5905a1aa 911 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 912 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
913 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 914 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
915 txq_id);
b481de9c 916 if (rc) {
15b1687c 917 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 918 goto error;
919 }
920 }
921
922 return rc;
923
924 error:
bb8c093b 925 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 926 return rc;
927}
928
fadb3582 929
f33269b8 930/*
fadb3582
BC		 931 * Start up 3945's basic functionality after it has been reset
932 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 933 * NOTE: This does not load uCode nor start the embedded processor
934 */
01ec616d 935static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 936{
fadb3582 937 int ret = iwl_apm_init(priv);
01ec616d 938
f33269b8
BC		 939 /* Clear APMG (NIC's internal power management) interrupts */
940 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
941 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
942
943 /* Reset radio chip */
944 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
945 udelay(5);
946 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
947
01ec616d
KA		 948 return ret;
949}
b481de9c 950
01ec616d
KA		 951static void iwl3945_nic_config(struct iwl_priv *priv)
952{
e6148917 953 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 954 unsigned long flags;
955 u8 rev_id = 0;
b481de9c 956
b481de9c
ZY		 957 spin_lock_irqsave(&priv->lock, flags);
958
43121432
AK		 959 /* Determine HW type */
960 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
961
962 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
963
b481de9c 964 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
91dd6c27 965 IWL_DEBUG_INFO(priv, "RTP type\n");
b481de9c 966 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 967 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 968 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 969 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 970 } else {
e1623446 971 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 972 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 973 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 974 }
975
e6148917 976 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 977 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 978 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 979 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 980 } else
e1623446 981 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 982
e6148917 983 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 984 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 985 eeprom->board_revision);
5d49f498 986 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 987 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 988 } else {
e1623446 989 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 990 eeprom->board_revision);
5d49f498 991 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 992 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 993 }
994
e6148917 995 if (eeprom->almgor_m_version <= 1) {
5d49f498 996 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 997 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 998 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 999 eeprom->almgor_m_version);
b481de9c 1000 } else {
e1623446 1001 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1002 eeprom->almgor_m_version);
5d49f498 1003 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1004 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1005 }
1006 spin_unlock_irqrestore(&priv->lock, flags);
1007
e6148917 1008 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1009 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1010
e6148917 1011 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1012 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1013}
1014
1015int iwl3945_hw_nic_init(struct iwl_priv *priv)
1016{
01ec616d
KA		 1017 int rc;
1018 unsigned long flags;
1019 struct iwl_rx_queue *rxq = &priv->rxq;
1020
1021 spin_lock_irqsave(&priv->lock, flags);
1022 priv->cfg->ops->lib->apm_ops.init(priv);
1023 spin_unlock_irqrestore(&priv->lock, flags);
1024
854682ed 1025 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1026 if (rc)
854682ed
KA		 1027 return rc;
1028
01ec616d 1029 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1030
1031 /* Allocate the RX queue, or reset if it is already allocated */
1032 if (!rxq->bd) {
51af3d3f 1033 rc = iwl_rx_queue_alloc(priv);
b481de9c 1034 if (rc) {
15b1687c 1035 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1036 return -ENOMEM;
1037 }
1038 } else
df833b1d 1039 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1040
bb8c093b 1041 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1042
1043 iwl3945_rx_init(priv, rxq);
1044
b481de9c
ZY		 1045
1046 /* Look at using this instead:
1047 rxq->need_update = 1;
141c43a3 1048 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1049 */
1050
5d49f498 1051 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1052
1053 rc = iwl3945_txq_ctx_reset(priv);
1054 if (rc)
1055 return rc;
1056
1057 set_bit(STATUS_INIT, &priv->status);
1058
1059 return 0;
1060}
1061
1062/**
bb8c093b 1063 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1064 *
1065 * Destroy all TX DMA queues and structures
1066 */
4a8a4322 1067void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1068{
1069 int txq_id;
1070
1071 /* Tx queues */
88804e2b
WYG		 1072 if (priv->txq)
1073 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1074 txq_id++)
1075 if (txq_id == IWL_CMD_QUEUE_NUM)
1076 iwl_cmd_queue_free(priv);
1077 else
1078 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1079
88804e2b
WYG		 1080 /* free tx queue structure */
1081 iwl_free_txq_mem(priv);
b481de9c
ZY		 1082}
1083
4a8a4322 1084void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1085{
bddadf86 1086 int txq_id;
b481de9c
ZY		 1087
1088 /* stop SCD */
5d49f498 1089 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1090 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1091
1092 /* reset TFD queues */
5905a1aa 1093 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1094 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1095 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1096 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1097 1000);
1098 }
1099
bb8c093b 1100 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1101}
1102
b481de9c 1103/**
bb8c093b 1104 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1105 * return index delta into power gain settings table
1106*/
bb8c093b 1107static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1108{
1109 return (new_reading - old_reading) * (-11) / 100;
1110}
1111
1112/**
bb8c093b 1113 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1114 */
bb8c093b 1115static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1116{
3ac7f146 1117 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1118}
1119
4a8a4322 1120int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1121{
5d49f498 1122 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1123}
1124
1125/**
bb8c093b 1126 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1127 * get the current temperature by reading from NIC
1128*/
4a8a4322 1129static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1130{
e6148917 1131 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1132 int temperature;
1133
bb8c093b 1134 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1135
1136 /* driver's okay range is -260 to +25.
1137 * human readable okay range is 0 to +285 */
e1623446 1138 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1139
1140 /* handle insane temp reading */
bb8c093b 1141 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1142 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1143
1144 /* if really really hot(?),
1145 * substitute the 3rd band/group's temp measured at factory */
1146 if (priv->last_temperature > 100)
e6148917 1147 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1148 else /* else use most recent "sane" value from driver */
1149 temperature = priv->last_temperature;
1150 }
1151
1152 return temperature; /* raw, not "human readable" */
1153}
1154
1155/* Adjust Txpower only if temperature variance is greater than threshold.
1156 *
1157 * Both are lower than older versions' 9 degrees */
1158#define IWL_TEMPERATURE_LIMIT_TIMER 6
1159
1160/**
1161 * is_temp_calib_needed - determines if new calibration is needed
1162 *
1163 * records new temperature in tx_mgr->temperature.
1164 * replaces tx_mgr->last_temperature *only* if calib needed
1165 * (assumes caller will actually do the calibration!). */
4a8a4322 1166static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1167{
1168 int temp_diff;
1169
bb8c093b 1170 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1171 temp_diff = priv->temperature - priv->last_temperature;
1172
1173 /* get absolute value */
1174 if (temp_diff < 0) {
e1623446 1175 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1176 temp_diff = -temp_diff;
1177 } else if (temp_diff == 0)
e1623446 1178 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1179 else
e1623446 1180 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1181
1182 /* if we don't need calibration, *don't* update last_temperature */
1183 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1184 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1185 return 0;
1186 }
1187
e1623446 1188 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1189
1190 /* assume that caller will actually do calib ...
1191 * update the "last temperature" value */
1192 priv->last_temperature = priv->temperature;
1193 return 1;
1194}
1195
1196#define IWL_MAX_GAIN_ENTRIES 78
1197#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1198#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1199
1200/* radio and DSP power table, each step is 1/2 dB.
1201 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1202static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1203 {
1204 {251, 127}, /* 2.4 GHz, highest power */
1205 {251, 127},
1206 {251, 127},
1207 {251, 127},
1208 {251, 125},
1209 {251, 110},
1210 {251, 105},
1211 {251, 98},
1212 {187, 125},
1213 {187, 115},
1214 {187, 108},
1215 {187, 99},
1216 {243, 119},
1217 {243, 111},
1218 {243, 105},
1219 {243, 97},
1220 {243, 92},
1221 {211, 106},
1222 {211, 100},
1223 {179, 120},
1224 {179, 113},
1225 {179, 107},
1226 {147, 125},
1227 {147, 119},
1228 {147, 112},
1229 {147, 106},
1230 {147, 101},
1231 {147, 97},
1232 {147, 91},
1233 {115, 107},
1234 {235, 121},
1235 {235, 115},
1236 {235, 109},
1237 {203, 127},
1238 {203, 121},
1239 {203, 115},
1240 {203, 108},
1241 {203, 102},
1242 {203, 96},
1243 {203, 92},
1244 {171, 110},
1245 {171, 104},
1246 {171, 98},
1247 {139, 116},
1248 {227, 125},
1249 {227, 119},
1250 {227, 113},
1251 {227, 107},
1252 {227, 101},
1253 {227, 96},
1254 {195, 113},
1255 {195, 106},
1256 {195, 102},
1257 {195, 95},
1258 {163, 113},
1259 {163, 106},
1260 {163, 102},
1261 {163, 95},
1262 {131, 113},
1263 {131, 106},
1264 {131, 102},
1265 {131, 95},
1266 {99, 113},
1267 {99, 106},
1268 {99, 102},
1269 {99, 95},
1270 {67, 113},
1271 {67, 106},
1272 {67, 102},
1273 {67, 95},
1274 {35, 113},
1275 {35, 106},
1276 {35, 102},
1277 {35, 95},
1278 {3, 113},
1279 {3, 106},
1280 {3, 102},
1281 {3, 95} }, /* 2.4 GHz, lowest power */
1282 {
1283 {251, 127}, /* 5.x GHz, highest power */
1284 {251, 120},
1285 {251, 114},
1286 {219, 119},
1287 {219, 101},
1288 {187, 113},
1289 {187, 102},
1290 {155, 114},
1291 {155, 103},
1292 {123, 117},
1293 {123, 107},
1294 {123, 99},
1295 {123, 92},
1296 {91, 108},
1297 {59, 125},
1298 {59, 118},
1299 {59, 109},
1300 {59, 102},
1301 {59, 96},
1302 {59, 90},
1303 {27, 104},
1304 {27, 98},
1305 {27, 92},
1306 {115, 118},
1307 {115, 111},
1308 {115, 104},
1309 {83, 126},
1310 {83, 121},
1311 {83, 113},
1312 {83, 105},
1313 {83, 99},
1314 {51, 118},
1315 {51, 111},
1316 {51, 104},
1317 {51, 98},
1318 {19, 116},
1319 {19, 109},
1320 {19, 102},
1321 {19, 98},
1322 {19, 93},
1323 {171, 113},
1324 {171, 107},
1325 {171, 99},
1326 {139, 120},
1327 {139, 113},
1328 {139, 107},
1329 {139, 99},
1330 {107, 120},
1331 {107, 113},
1332 {107, 107},
1333 {107, 99},
1334 {75, 120},
1335 {75, 113},
1336 {75, 107},
1337 {75, 99},
1338 {43, 120},
1339 {43, 113},
1340 {43, 107},
1341 {43, 99},
1342 {11, 120},
1343 {11, 113},
1344 {11, 107},
1345 {11, 99},
1346 {131, 107},
1347 {131, 99},
1348 {99, 120},
1349 {99, 113},
1350 {99, 107},
1351 {99, 99},
1352 {67, 120},
1353 {67, 113},
1354 {67, 107},
1355 {67, 99},
1356 {35, 120},
1357 {35, 113},
1358 {35, 107},
1359 {35, 99},
1360 {3, 120} } /* 5.x GHz, lowest power */
1361};
1362
bb8c093b 1363static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1364{
1365 if (index < 0)
1366 return 0;
1367 if (index >= IWL_MAX_GAIN_ENTRIES)
1368 return IWL_MAX_GAIN_ENTRIES - 1;
1369 return (u8) index;
1370}
1371
1372/* Kick off thermal recalibration check every 60 seconds */
1373#define REG_RECALIB_PERIOD (60)
1374
1375/**
bb8c093b 1376 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1377 *
1378 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1379 * or 6 Mbit (OFDM) rates.
1380 */
4a8a4322 1381static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1382 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1383 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1384 int band_index)
1385{
bb8c093b 1386 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1387 s8 power;
1388 u8 power_index;
1389
1390 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1391
1392 /* use this channel group's 6Mbit clipping/saturation pwr,
1393 * but cap at regulatory scan power restriction (set during init
1394 * based on eeprom channel data) for this channel. */
14577f23 1395 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1396
1397 /* further limit to user's max power preference.
1398 * FIXME: Other spectrum management power limitations do not
1399 * seem to apply?? */
62ea9c5b 1400 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1401 scan_power_info->requested_power = power;
1402
1403 /* find difference between new scan *power* and current "normal"
1404 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1405 * current "normal" temperature-compensated Tx power *index* for
1406 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1407 * *index*. */
1408 power_index = ch_info->power_info[rate_index].power_table_index
1409 - (power - ch_info->power_info
14577f23 1410 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1411
1412 /* store reference index that we use when adjusting *all* scan
1413 * powers. So we can accommodate user (all channel) or spectrum
1414 * management (single channel) power changes "between" temperature
1415 * feedback compensation procedures.
1416 * don't force fit this reference index into gain table; it may be a
1417 * negative number. This will help avoid errors when we're at
1418 * the lower bounds (highest gains, for warmest temperatures)
1419 * of the table. */
1420
1421 /* don't exceed table bounds for "real" setting */
bb8c093b 1422 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1423
1424 scan_power_info->power_table_index = power_index;
1425 scan_power_info->tpc.tx_gain =
1426 power_gain_table[band_index][power_index].tx_gain;
1427 scan_power_info->tpc.dsp_atten =
1428 power_gain_table[band_index][power_index].dsp_atten;
1429}
1430
1431/**
75bcfae9 1432 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1433 *
1434 * Configures power settings for all rates for the current channel,
1435 * using values from channel info struct, and send to NIC
1436 */
dfb39e82 1437static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1438{
14577f23 1439 int rate_idx, i;
d20b3c65 1440 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1441 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1442 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1443 };
1444
8318d78a 1445 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1446 ch_info = iwl_get_channel_info(priv,
8318d78a 1447 priv->band,
8ccde88a 1448 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1449 if (!ch_info) {
15b1687c
WT		 1450 IWL_ERR(priv,
1451 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1452 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1453 return -EINVAL;
1454 }
1455
1456 if (!is_channel_valid(ch_info)) {
e1623446 1457 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1458 "non-Tx channel.\n");
1459 return 0;
1460 }
1461
1462 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1463 /* Fill OFDM rate */
1464 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1465 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1466
1467 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1468 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1469
e1623446 1470 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1471 le16_to_cpu(txpower.channel),
1472 txpower.band,
14577f23
MA		 1473 txpower.power[i].tpc.tx_gain,
1474 txpower.power[i].tpc.dsp_atten,
1475 txpower.power[i].rate);
1476 }
1477 /* Fill CCK rates */
1478 for (rate_idx = IWL_FIRST_CCK_RATE;
1479 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1480 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1481 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1482
e1623446 1483 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1484 le16_to_cpu(txpower.channel),
1485 txpower.band,
1486 txpower.power[i].tpc.tx_gain,
1487 txpower.power[i].tpc.dsp_atten,
1488 txpower.power[i].rate);
b481de9c
ZY		 1489 }
1490
518099a8
SO		 1491 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1492 sizeof(struct iwl3945_txpowertable_cmd),
1493 &txpower);
b481de9c
ZY		 1494
1495}
1496
1497/**
bb8c093b 1498 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1499 * @ch_info: Channel to update. Uses power_info.requested_power.
1500 *
1501 * Replace requested_power and base_power_index ch_info fields for
1502 * one channel.
1503 *
1504 * Called if user or spectrum management changes power preferences.
1505 * Takes into account h/w and modulation limitations (clip power).
1506 *
1507 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1508 *
1509 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1510 * properly fill out the scan powers, and actual h/w gain settings,
1511 * and send changes to NIC
1512 */
4a8a4322 1513static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1514 struct iwl_channel_info *ch_info)
b481de9c 1515{
bb8c093b 1516 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1517 int power_changed = 0;
1518 int i;
1519 const s8 *clip_pwrs;
1520 int power;
1521
1522 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1523 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1524
1525 /* Get this channel's rate-to-current-power settings table */
1526 power_info = ch_info->power_info;
1527
1528 /* update OFDM Txpower settings */
14577f23 1529 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1530 i++, ++power_info) {
1531 int delta_idx;
1532
1533 /* limit new power to be no more than h/w capability */
1534 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1535 if (power == power_info->requested_power)
1536 continue;
1537
1538 /* find difference between old and new requested powers,
1539 * update base (non-temp-compensated) power index */
1540 delta_idx = (power - power_info->requested_power) * 2;
1541 power_info->base_power_index -= delta_idx;
1542
1543 /* save new requested power value */
1544 power_info->requested_power = power;
1545
1546 power_changed = 1;
1547 }
1548
1549 /* update CCK Txpower settings, based on OFDM 12M setting ...
1550 * ... all CCK power settings for a given channel are the *same*. */
1551 if (power_changed) {
1552 power =
14577f23 1553 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1554 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1555
bb8c093b 1556 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1557 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1558 power_info->requested_power = power;
1559 power_info->base_power_index =
14577f23 1560 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1561 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1562 ++power_info;
1563 }
1564 }
1565
1566 return 0;
1567}
1568
1569/**
bb8c093b 1570 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1571 *
1572 * NOTE: Returned power limit may be less (but not more) than requested,
1573 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1574 * (no consideration for h/w clipping limitations).
1575 */
d20b3c65 1576static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1577{
1578 s8 max_power;
1579
1580#if 0
1581 /* if we're using TGd limits, use lower of TGd or EEPROM */
1582 if (ch_info->tgd_data.max_power != 0)
1583 max_power = min(ch_info->tgd_data.max_power,
1584 ch_info->eeprom.max_power_avg);
1585
1586 /* else just use EEPROM limits */
1587 else
1588#endif
1589 max_power = ch_info->eeprom.max_power_avg;
1590
1591 return min(max_power, ch_info->max_power_avg);
1592}
1593
1594/**
bb8c093b 1595 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1596 *
1597 * Compensate txpower settings of *all* channels for temperature.
1598 * This only accounts for the difference between current temperature
1599 * and the factory calibration temperatures, and bases the new settings
1600 * on the channel's base_power_index.
1601 *
1602 * If RxOn is "associated", this sends the new Txpower to NIC!
1603 */
4a8a4322 1604static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1605{
d20b3c65 1606 struct iwl_channel_info *ch_info = NULL;
e6148917 1607 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1608 int delta_index;
1609 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1610 u8 a_band;
1611 u8 rate_index;
1612 u8 scan_tbl_index;
1613 u8 i;
1614 int ref_temp;
1615 int temperature = priv->temperature;
1616
4e7033ef
WYG		 1617 if (priv->disable_tx_power_cal ||
1618 test_bit(STATUS_SCANNING, &priv->status)) {
1619 /* do not perform tx power calibration */
1620 return 0;
1621 }
b481de9c
ZY		 1622 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1623 for (i = 0; i < priv->channel_count; i++) {
1624 ch_info = &priv->channel_info[i];
1625 a_band = is_channel_a_band(ch_info);
1626
1627 /* Get this chnlgrp's factory calibration temperature */
e6148917 1628 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1629 temperature;
1630
a96a27f9 1631 /* get power index adjustment based on current and factory
b481de9c 1632 * temps */
bb8c093b 1633 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1634 ref_temp);
1635
1636 /* set tx power value for all rates, OFDM and CCK */
1637 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1638 rate_index++) {
1639 int power_idx =
1640 ch_info->power_info[rate_index].base_power_index;
1641
1642 /* temperature compensate */
1643 power_idx += delta_index;
1644
1645 /* stay within table range */
bb8c093b 1646 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1647 ch_info->power_info[rate_index].
1648 power_table_index = (u8) power_idx;
1649 ch_info->power_info[rate_index].tpc =
1650 power_gain_table[a_band][power_idx];
1651 }
1652
1653 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1654 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1655
1656 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1657 for (scan_tbl_index = 0;
1658 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1659 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1660 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1661 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1662 actual_index, clip_pwrs,
1663 ch_info, a_band);
1664 }
1665 }
1666
1667 /* send Txpower command for current channel to ucode */
75bcfae9 1668 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1669}
1670
4a8a4322 1671int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1672{
d20b3c65 1673 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1674 s8 max_power;
1675 u8 a_band;
1676 u8 i;
1677
62ea9c5b 1678 if (priv->tx_power_user_lmt == power) {
e1623446 1679 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1680 "limit: %ddBm.\n", power);
1681 return 0;
1682 }
1683
e1623446 1684 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1685 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1686
1687 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1688
1689 for (i = 0; i < priv->channel_count; i++) {
1690 ch_info = &priv->channel_info[i];
1691 a_band = is_channel_a_band(ch_info);
1692
1693 /* find minimum power of all user and regulatory constraints
1694 * (does not consider h/w clipping limitations) */
bb8c093b 1695 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1696 max_power = min(power, max_power);
1697 if (max_power != ch_info->curr_txpow) {
1698 ch_info->curr_txpow = max_power;
1699
1700 /* this considers the h/w clipping limitations */
bb8c093b 1701 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1702 }
1703 }
1704
1705 /* update txpower settings for all channels,
1706 * send to NIC if associated. */
1707 is_temp_calib_needed(priv);
bb8c093b 1708 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1709
1710 return 0;
1711}
1712
5bbe233b
AK		 1713static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1714{
1715 int rc = 0;
2f301227 1716 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1717 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1718 struct iwl_host_cmd cmd = {
1719 .id = REPLY_RXON_ASSOC,
1720 .len = sizeof(rxon_assoc),
c2acea8e 1721 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1722 .data = &rxon_assoc,
1723 };
1724 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1725 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1726
1727 if ((rxon1->flags == rxon2->flags) &&
1728 (rxon1->filter_flags == rxon2->filter_flags) &&
1729 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1730 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1731 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1732 return 0;
1733 }
1734
1735 rxon_assoc.flags = priv->staging_rxon.flags;
1736 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1737 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1738 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1739 rxon_assoc.reserved = 0;
1740
1741 rc = iwl_send_cmd_sync(priv, &cmd);
1742 if (rc)
1743 return rc;
1744
2f301227
ZY		 1745 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1746 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1747 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1748 rc = -EIO;
1749 }
1750
64a76b50 1751 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1752
1753 return rc;
1754}
1755
e0158e61
AK		 1756/**
1757 * iwl3945_commit_rxon - commit staging_rxon to hardware
1758 *
1759 * The RXON command in staging_rxon is committed to the hardware and
1760 * the active_rxon structure is updated with the new data. This
1761 * function correctly transitions out of the RXON_ASSOC_MSK state if
1762 * a HW tune is required based on the RXON structure changes.
1763 */
1764static int iwl3945_commit_rxon(struct iwl_priv *priv)
1765{
1766 /* cast away the const for active_rxon in this function */
1767 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1768 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1769 int rc = 0;
1770 bool new_assoc =
1771 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1772
1773 if (!iwl_is_alive(priv))
1774 return -1;
1775
1776 /* always get timestamp with Rx frame */
1777 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1778
1779 /* select antenna */
1780 staging_rxon->flags &=
1781 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1782 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1783
1784 rc = iwl_check_rxon_cmd(priv);
1785 if (rc) {
1786 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1787 return -EINVAL;
1788 }
1789
1790 /* If we don't need to send a full RXON, we can use
1791 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1792 * and other flags for the current radio configuration. */
1793 if (!iwl_full_rxon_required(priv)) {
1794 rc = iwl_send_rxon_assoc(priv);
1795 if (rc) {
1796 IWL_ERR(priv, "Error setting RXON_ASSOC "
1797 "configuration (%d).\n", rc);
1798 return rc;
1799 }
1800
1801 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1802
1803 return 0;
1804 }
1805
1806 /* If we are currently associated and the new config requires
1807 * an RXON_ASSOC and the new config wants the associated mask enabled,
1808 * we must clear the associated from the active configuration
1809 * before we apply the new config */
1810 if (iwl_is_associated(priv) && new_assoc) {
1811 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1812 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1813
1814 /*
1815 * reserved4 and 5 could have been filled by the iwlcore code.
1816 * Let's clear them before pushing to the 3945.
1817 */
1818 active_rxon->reserved4 = 0;
1819 active_rxon->reserved5 = 0;
1820 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1821 sizeof(struct iwl3945_rxon_cmd),
1822 &priv->active_rxon);
1823
1824 /* If the mask clearing failed then we set
1825 * active_rxon back to what it was previously */
1826 if (rc) {
1827 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1828 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1829 "configuration (%d).\n", rc);
1830 return rc;
1831 }
2c810ccd 1832 iwl_clear_ucode_stations(priv);
7e246191 1833 iwl_restore_stations(priv);
e0158e61
AK		 1834 }
1835
1836 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1837 "* with%s RXON_FILTER_ASSOC_MSK\n"
1838 "* channel = %d\n"
1839 "* bssid = %pM\n",
1840 (new_assoc ? "" : "out"),
1841 le16_to_cpu(staging_rxon->channel),
1842 staging_rxon->bssid_addr);
1843
1844 /*
1845 * reserved4 and 5 could have been filled by the iwlcore code.
1846 * Let's clear them before pushing to the 3945.
1847 */
1848 staging_rxon->reserved4 = 0;
1849 staging_rxon->reserved5 = 0;
1850
90e8e424 1851 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1852
1853 /* Apply the new configuration */
1854 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1855 sizeof(struct iwl3945_rxon_cmd),
1856 staging_rxon);
1857 if (rc) {
1858 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1859 return rc;
1860 }
1861
1862 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1863
7e246191 1864 if (!new_assoc) {
2c810ccd 1865 iwl_clear_ucode_stations(priv);
7e246191
RC		 1866 iwl_restore_stations(priv);
1867 }
e0158e61
AK		 1868
1869 /* If we issue a new RXON command which required a tune then we must
1870 * send a new TXPOWER command or we won't be able to Tx any frames */
1871 rc = priv->cfg->ops->lib->send_tx_power(priv);
1872 if (rc) {
1873 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1874 return rc;
1875 }
1876
e0158e61
AK		 1877 /* Init the hardware's rate fallback order based on the band */
1878 rc = iwl3945_init_hw_rate_table(priv);
1879 if (rc) {
1880 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1881 return -EIO;
1882 }
1883
1884 return 0;
1885}
1886
b481de9c
ZY		 1887/**
1888 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1889 *
1890 * -- reset periodic timer
1891 * -- see if temp has changed enough to warrant re-calibration ... if so:
1892 * -- correct coeffs for temp (can reset temp timer)
1893 * -- save this temp as "last",
1894 * -- send new set of gain settings to NIC
1895 * NOTE: This should continue working, even when we're not associated,
1896 * so we can keep our internal table of scan powers current. */
4a8a4322 1897void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1898{
1899 /* This will kick in the "brute force"
bb8c093b 1900 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1901 if (!is_temp_calib_needed(priv))
1902 goto reschedule;
1903
1904 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1905 * This is based *only* on current temperature,
1906 * ignoring any previous power measurements */
bb8c093b 1907 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1908
1909 reschedule:
1910 queue_delayed_work(priv->workqueue,
ee525d13 1911 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 1912}
1913
416e1438 1914static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 1915{
4a8a4322 1916 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 1917 _3945.thermal_periodic.work);
b481de9c
ZY		 1918
1919 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1920 return;
1921
1922 mutex_lock(&priv->mutex);
1923 iwl3945_reg_txpower_periodic(priv);
1924 mutex_unlock(&priv->mutex);
1925}
1926
1927/**
bb8c093b 1928 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 1929 * for the channel.
1930 *
1931 * This function is used when initializing channel-info structs.
1932 *
1933 * NOTE: These channel groups do *NOT* match the bands above!
1934 * These channel groups are based on factory-tested channels;
1935 * on A-band, EEPROM's "group frequency" entries represent the top
1936 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1937 */
4a8a4322 1938static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 1939 const struct iwl_channel_info *ch_info)
b481de9c 1940{
e6148917
SO		 1941 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1942 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 1943 u8 group;
1944 u16 group_index = 0; /* based on factory calib frequencies */
1945 u8 grp_channel;
1946
1947 /* Find the group index for the channel ... don't use index 1(?) */
1948 if (is_channel_a_band(ch_info)) {
1949 for (group = 1; group < 5; group++) {
1950 grp_channel = ch_grp[group].group_channel;
1951 if (ch_info->channel <= grp_channel) {
1952 group_index = group;
1953 break;
1954 }
1955 }
1956 /* group 4 has a few channels *above* its factory cal freq */
1957 if (group == 5)
1958 group_index = 4;
1959 } else
1960 group_index = 0; /* 2.4 GHz, group 0 */
1961
e1623446 1962 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 1963 group_index);
1964 return group_index;
1965}
1966
1967/**
bb8c093b 1968 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 1969 *
1970 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1971 * into radio/DSP gain settings table for requested power.
1972 */
4a8a4322 1973static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 1974 s8 requested_power,
1975 s32 setting_index, s32 *new_index)
1976{
bb8c093b 1977 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 1978 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1979 s32 index0, index1;
1980 s32 power = 2 * requested_power;
1981 s32 i;
bb8c093b 1982 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 1983 s32 gains0, gains1;
1984 s32 res;
1985 s32 denominator;
1986
e6148917 1987 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 1988 samples = chnl_grp->samples;
1989 for (i = 0; i < 5; i++) {
1990 if (power == samples[i].power) {
1991 *new_index = samples[i].gain_index;
1992 return 0;
1993 }
1994 }
1995
1996 if (power > samples[1].power) {
1997 index0 = 0;
1998 index1 = 1;
1999 } else if (power > samples[2].power) {
2000 index0 = 1;
2001 index1 = 2;
2002 } else if (power > samples[3].power) {
2003 index0 = 2;
2004 index1 = 3;
2005 } else {
2006 index0 = 3;
2007 index1 = 4;
2008 }
2009
2010 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2011 if (denominator == 0)
2012 return -EINVAL;
2013 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2014 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2015 res = gains0 + (gains1 - gains0) *
2016 ((s32) power - (s32) samples[index0].power) / denominator +
2017 (1 << 18);
2018 *new_index = res >> 19;
2019 return 0;
2020}
2021
4a8a4322 2022static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2023{
2024 u32 i;
2025 s32 rate_index;
e6148917 2026 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2027 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2028
e1623446 2029 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2030
2031 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2032 s8 *clip_pwrs; /* table of power levels for each rate */
2033 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2034 group = &eeprom->groups[i];
b481de9c
ZY		 2035
2036 /* sanity check on factory saturation power value */
2037 if (group->saturation_power < 40) {
39aadf8c 2038 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2039 "less than minimum expected 40\n",
2040 group->saturation_power);
2041 return;
2042 }
2043
2044 /*
2045 * Derive requested power levels for each rate, based on
2046 * hardware capabilities (saturation power for band).
2047 * Basic value is 3dB down from saturation, with further
2048 * power reductions for highest 3 data rates. These
2049 * backoffs provide headroom for high rate modulation
2050 * power peaks, without too much distortion (clipping).
2051 */
2052 /* we'll fill in this array with h/w max power levels */
67d613ae 2053 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2054
2055 /* divide factory saturation power by 2 to find -3dB level */
2056 satur_pwr = (s8) (group->saturation_power >> 1);
2057
2058 /* fill in channel group's nominal powers for each rate */
2059 for (rate_index = 0;
1d79e53c 2060 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) {
b481de9c 2061 switch (rate_index) {
14577f23 2062 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2063 if (i == 0) /* B/G */
2064 *clip_pwrs = satur_pwr;
2065 else /* A */
2066 *clip_pwrs = satur_pwr - 5;
2067 break;
14577f23 2068 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2069 if (i == 0)
2070 *clip_pwrs = satur_pwr - 7;
2071 else
2072 *clip_pwrs = satur_pwr - 10;
2073 break;
14577f23 2074 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2075 if (i == 0)
2076 *clip_pwrs = satur_pwr - 9;
2077 else
2078 *clip_pwrs = satur_pwr - 12;
2079 break;
2080 default:
2081 *clip_pwrs = satur_pwr;
2082 break;
2083 }
2084 }
2085 }
2086}
2087
2088/**
2089 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2090 *
2091 * Second pass (during init) to set up priv->channel_info
2092 *
2093 * Set up Tx-power settings in our channel info database for each VALID
2094 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2095 * and current temperature.
2096 *
2097 * Since this is based on current temperature (at init time), these values may
2098 * not be valid for very long, but it gives us a starting/default point,
2099 * and allows us to active (i.e. using Tx) scan.
2100 *
2101 * This does *not* write values to NIC, just sets up our internal table.
2102 */
4a8a4322 2103int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2104{
d20b3c65 2105 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2106 struct iwl3945_channel_power_info *pwr_info;
e6148917 2107 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2108 int delta_index;
2109 u8 rate_index;
2110 u8 scan_tbl_index;
2111 const s8 *clip_pwrs; /* array of power levels for each rate */
2112 u8 gain, dsp_atten;
2113 s8 power;
2114 u8 pwr_index, base_pwr_index, a_band;
2115 u8 i;
2116 int temperature;
2117
2118 /* save temperature reference,
2119 * so we can determine next time to calibrate */
bb8c093b 2120 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2121 priv->last_temperature = temperature;
2122
bb8c093b 2123 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2124
2125 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2126 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2127 i++, ch_info++) {
2128 a_band = is_channel_a_band(ch_info);
2129 if (!is_channel_valid(ch_info))
2130 continue;
2131
2132 /* find this channel's channel group (*not* "band") index */
2133 ch_info->group_index =
bb8c093b 2134 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2135
2136 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2137 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2138
2139 /* calculate power index *adjustment* value according to
2140 * diff between current temperature and factory temperature */
bb8c093b 2141 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2142 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2143 temperature);
2144
e1623446 2145 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2146 ch_info->channel, delta_index, temperature +
2147 IWL_TEMP_CONVERT);
2148
2149 /* set tx power value for all OFDM rates */
2150 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2151 rate_index++) {
25a4ccea 2152 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2153 int rc;
2154
2155 /* use channel group's clip-power table,
2156 * but don't exceed channel's max power */
2157 s8 pwr = min(ch_info->max_power_avg,
2158 clip_pwrs[rate_index]);
2159
2160 pwr_info = &ch_info->power_info[rate_index];
2161
2162 /* get base (i.e. at factory-measured temperature)
2163 * power table index for this rate's power */
bb8c093b 2164 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2165 ch_info->group_index,
2166 &power_idx);
2167 if (rc) {
15b1687c 2168 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2169 return rc;
2170 }
2171 pwr_info->base_power_index = (u8) power_idx;
2172
2173 /* temperature compensate */
2174 power_idx += delta_index;
2175
2176 /* stay within range of gain table */
bb8c093b 2177 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2178
bb8c093b 2179 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2180 pwr_info->requested_power = pwr;
2181 pwr_info->power_table_index = (u8) power_idx;
2182 pwr_info->tpc.tx_gain =
2183 power_gain_table[a_band][power_idx].tx_gain;
2184 pwr_info->tpc.dsp_atten =
2185 power_gain_table[a_band][power_idx].dsp_atten;
2186 }
2187
2188 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2189 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2190 power = pwr_info->requested_power +
2191 IWL_CCK_FROM_OFDM_POWER_DIFF;
2192 pwr_index = pwr_info->power_table_index +
2193 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2194 base_pwr_index = pwr_info->base_power_index +
2195 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2196
2197 /* stay within table range */
bb8c093b 2198 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2199 gain = power_gain_table[a_band][pwr_index].tx_gain;
2200 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2201
bb8c093b 2202 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2203 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2204 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2205 for (rate_index = 0;
2206 rate_index < IWL_CCK_RATES; rate_index++) {
2207 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2208 pwr_info->requested_power = power;
2209 pwr_info->power_table_index = pwr_index;
2210 pwr_info->base_power_index = base_pwr_index;
2211 pwr_info->tpc.tx_gain = gain;
2212 pwr_info->tpc.dsp_atten = dsp_atten;
2213 }
2214
2215 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2216 for (scan_tbl_index = 0;
2217 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2218 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2219 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2220 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2221 actual_index, clip_pwrs, ch_info, a_band);
2222 }
2223 }
2224
2225 return 0;
2226}
2227
4a8a4322 2228int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2229{
2230 int rc;
b481de9c 2231
5d49f498
AK		 2232 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2233 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2234 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2235 if (rc < 0)
15b1687c 2236 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2237
b481de9c
ZY		 2238 return 0;
2239}
2240
188cf6c7 2241int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2242{
b481de9c
ZY		 2243 int txq_id = txq->q.id;
2244
ee525d13 2245 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2246
2247 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2248
5d49f498
AK		 2249 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2250 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2251
5d49f498 2252 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2253 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2254 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2255 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2256 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2257 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2258
2259 /* fake read to flush all prev. writes */
5d49f498 2260 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2261
2262 return 0;
2263}
2264
42427b4e
KA		 2265/*
2266 * HCMD utils
2267 */
2268static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2269{
2270 switch (cmd_id) {
2271 case REPLY_RXON:
d25aabb0
WT		 2272 return sizeof(struct iwl3945_rxon_cmd);
2273 case POWER_TABLE_CMD:
2274 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2275 default:
2276 return len;
2277 }
2278}
2279
c587de0b 2280
17f841cd
SO		 2281static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2282{
c587de0b
TW		 2283 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2284 addsta->mode = cmd->mode;
2285 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2286 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2287 addsta->station_flags = cmd->station_flags;
2288 addsta->station_flags_msk = cmd->station_flags_msk;
2289 addsta->tid_disable_tx = cpu_to_le16(0);
2290 addsta->rate_n_flags = cmd->rate_n_flags;
2291 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2292 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2293 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2294
2295 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2296}
2297
1fa61b2e
JB		 2298static int iwl3945_manage_ibss_station(struct iwl_priv *priv,
2299 struct ieee80211_vif *vif, bool add)
2300{
fd1af15d 2301 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1fa61b2e
JB		 2302 int ret;
2303
1fa61b2e 2304 if (add) {
57f8db89 2305 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false,
fd1af15d 2306 &vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2307 if (ret)
2308 return ret;
2309
fd1af15d 2310 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id,
1fa61b2e 2311 (priv->band == IEEE80211_BAND_5GHZ) ?
9c5ac091 2312 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP);
fd1af15d 2313 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id);
1fa61b2e
JB		 2314
2315 return 0;
2316 }
2317
fd1af15d
JB		 2318 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
2319 vif->bss_conf.bssid);
1fa61b2e 2320}
c587de0b 2321
b481de9c
ZY		 2322/**
2323 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2324 */
4a8a4322 2325int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2326{
14577f23 2327 int rc, i, index, prev_index;
bb8c093b 2328 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2329 .reserved = {0, 0, 0},
2330 };
bb8c093b 2331 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2332
bb8c093b
CH		 2333 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2334 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2335
2336 table[index].rate_n_flags =
bb8c093b 2337 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2338 table[index].try_cnt = priv->retry_rate;
bb8c093b 2339 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2340 table[index].next_rate_index =
2341 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2342 }
2343
8318d78a
JB		 2344 switch (priv->band) {
2345 case IEEE80211_BAND_5GHZ:
e1623446 2346 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2347 /* If one of the following CCK rates is used,
2348 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2349 for (i = IWL_RATE_1M_INDEX_TABLE;
2350 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2351 table[i].next_rate_index =
2352 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2353
2354 /* Don't fall back to CCK rates */
7262796a
AM		 2355 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2356 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2357
2358 /* Don't drop out of OFDM rates */
14577f23 2359 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2360 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2361 break;
2362
8318d78a 2363 case IEEE80211_BAND_2GHZ:
e1623446 2364 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2365 /* If an OFDM rate is used, have it fall back to the
2366 * 1M CCK rates */
b481de9c 2367
ee525d13 2368 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2369 iwl_is_associated(priv)) {
7262796a
AM		 2370
2371 index = IWL_FIRST_CCK_RATE;
2372 for (i = IWL_RATE_6M_INDEX_TABLE;
2373 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2374 table[i].next_rate_index =
2375 iwl3945_rates[index].table_rs_index;
2376
2377 index = IWL_RATE_11M_INDEX_TABLE;
2378 /* CCK shouldn't fall back to OFDM... */
2379 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2380 }
b481de9c
ZY		 2381 break;
2382
2383 default:
8318d78a 2384 WARN_ON(1);
b481de9c
ZY		 2385 break;
2386 }
2387
2388 /* Update the rate scaling for control frame Tx */
2389 rate_cmd.table_id = 0;
518099a8 2390 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2391 &rate_cmd);
2392 if (rc)
2393 return rc;
2394
2395 /* Update the rate scaling for data frame Tx */
2396 rate_cmd.table_id = 1;
518099a8 2397 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2398 &rate_cmd);
2399}
2400
796083cb 2401/* Called when initializing driver */
4a8a4322 2402int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2403{
3832ec9d
AK		 2404 memset((void *)&priv->hw_params, 0,
2405 sizeof(struct iwl_hw_params));
b481de9c 2406
ee525d13
JB		 2407 priv->_3945.shared_virt =
2408 dma_alloc_coherent(&priv->pci_dev->dev,
2409 sizeof(struct iwl3945_shared),
2410 &priv->_3945.shared_phys, GFP_KERNEL);
2411 if (!priv->_3945.shared_virt) {
15b1687c 2412 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2413 return -ENOMEM;
2414 }
2415
21c02a1a 2416 /* Assign number of Usable TX queues */
88804e2b 2417 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2418
a8e74e27 2419 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2420 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2421 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2422 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2423 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2424 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2425
141c43a3 2426 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2427 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
a0ee74cf 2428 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS;
141c43a3 2429
b481de9c
ZY		 2430 return 0;
2431}
2432
4a8a4322 2433unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2434 struct iwl3945_frame *frame, u8 rate)
b481de9c 2435{
bb8c093b 2436 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2437 unsigned int frame_size;
2438
bb8c093b 2439 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2440 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2441
3832ec9d 2442 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2443 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2444
bb8c093b 2445 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2446 tx_beacon_cmd->frame,
b481de9c
ZY		 2447 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2448
2449 BUG_ON(frame_size > MAX_MPDU_SIZE);
2450 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2451
2452 tx_beacon_cmd->tx.rate = rate;
2453 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2454 TX_CMD_FLG_TSF_MSK);
2455
14577f23
MA		 2456 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2457 tx_beacon_cmd->tx.supp_rates[0] =
2458 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2459
b481de9c 2460 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2461 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2462
3ac7f146 2463 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2464}
2465
4a8a4322 2466void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2467{
91c066f2 2468 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2469 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2470}
2471
4a8a4322 2472void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2473{
ee525d13 2474 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2475 iwl3945_bg_reg_txpower_periodic);
2476}
2477
4a8a4322 2478void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2479{
ee525d13 2480 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2481}
2482
0164b9b4
KA		 2483/* check contents of special bootstrap uCode SRAM */
2484static int iwl3945_verify_bsm(struct iwl_priv *priv)
2485 {
2486 __le32 *image = priv->ucode_boot.v_addr;
2487 u32 len = priv->ucode_boot.len;
2488 u32 reg;
2489 u32 val;
2490
e1623446 2491 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2492
2493 /* verify BSM SRAM contents */
2494 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2495 for (reg = BSM_SRAM_LOWER_BOUND;
2496 reg < BSM_SRAM_LOWER_BOUND + len;
2497 reg += sizeof(u32), image++) {
2498 val = iwl_read_prph(priv, reg);
2499 if (val != le32_to_cpu(*image)) {
2500 IWL_ERR(priv, "BSM uCode verification failed at "
2501 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2502 BSM_SRAM_LOWER_BOUND,
2503 reg - BSM_SRAM_LOWER_BOUND, len,
2504 val, le32_to_cpu(*image));
2505 return -EIO;
2506 }
2507 }
2508
e1623446 2509 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2510
2511 return 0;
2512}
2513
e6148917
SO		 2514
2515/******************************************************************************
2516 *
2517 * EEPROM related functions
2518 *
2519 ******************************************************************************/
2520
2521/*
2522 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2523 * embedded controller) as EEPROM reader; each read is a series of pulses
2524 * to/from the EEPROM chip, not a single event, so even reads could conflict
2525 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2526 * simply claims ownership, which should be safe when this function is called
2527 * (i.e. before loading uCode!).
2528 */
2529static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2530{
2531 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2532 return 0;
2533}
2534
2535
2536static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2537{
2538 return;
2539}
2540
0164b9b4
KA		 2541 /**
2542 * iwl3945_load_bsm - Load bootstrap instructions
2543 *
2544 * BSM operation:
2545 *
2546 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2547 * in special SRAM that does not power down during RFKILL. When powering back
2548 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2549 * the bootstrap program into the on-board processor, and starts it.
2550 *
2551 * The bootstrap program loads (via DMA) instructions and data for a new
2552 * program from host DRAM locations indicated by the host driver in the
2553 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2554 * automatically.
2555 *
2556 * When initializing the NIC, the host driver points the BSM to the
2557 * "initialize" uCode image. This uCode sets up some internal data, then
2558 * notifies host via "initialize alive" that it is complete.
2559 *
2560 * The host then replaces the BSM_DRAM_* pointer values to point to the
2561 * normal runtime uCode instructions and a backup uCode data cache buffer
2562 * (filled initially with starting data values for the on-board processor),
2563 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2564 * which begins normal operation.
2565 *
2566 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2567 * the backup data cache in DRAM before SRAM is powered down.
2568 *
2569 * When powering back up, the BSM loads the bootstrap program. This reloads
2570 * the runtime uCode instructions and the backup data cache into SRAM,
2571 * and re-launches the runtime uCode from where it left off.
2572 */
2573static int iwl3945_load_bsm(struct iwl_priv *priv)
2574{
2575 __le32 *image = priv->ucode_boot.v_addr;
2576 u32 len = priv->ucode_boot.len;
2577 dma_addr_t pinst;
2578 dma_addr_t pdata;
2579 u32 inst_len;
2580 u32 data_len;
2581 int rc;
2582 int i;
2583 u32 done;
2584 u32 reg_offset;
2585
e1623446 2586 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2587
2588 /* make sure bootstrap program is no larger than BSM's SRAM size */
2589 if (len > IWL39_MAX_BSM_SIZE)
2590 return -EINVAL;
2591
2592 /* Tell bootstrap uCode where to find the "Initialize" uCode
2593 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2594 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2595 * after the "initialize" uCode has run, to point to
2596 * runtime/protocol instructions and backup data cache. */
2597 pinst = priv->ucode_init.p_addr;
2598 pdata = priv->ucode_init_data.p_addr;
2599 inst_len = priv->ucode_init.len;
2600 data_len = priv->ucode_init_data.len;
2601
0164b9b4
KA		 2602 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2603 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2604 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2605 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2606
2607 /* Fill BSM memory with bootstrap instructions */
2608 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2609 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2610 reg_offset += sizeof(u32), image++)
2611 _iwl_write_prph(priv, reg_offset,
2612 le32_to_cpu(*image));
2613
2614 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2615 if (rc)
0164b9b4 2616 return rc;
0164b9b4
KA		 2617
2618 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2619 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2620 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2621 IWL39_RTC_INST_LOWER_BOUND);
2622 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2623
2624 /* Load bootstrap code into instruction SRAM now,
2625 * to prepare to load "initialize" uCode */
2626 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2627 BSM_WR_CTRL_REG_BIT_START);
2628
2629 /* Wait for load of bootstrap uCode to finish */
2630 for (i = 0; i < 100; i++) {
2631 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2632 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2633 break;
2634 udelay(10);
2635 }
2636 if (i < 100)
e1623446 2637 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2638 else {
2639 IWL_ERR(priv, "BSM write did not complete!\n");
2640 return -EIO;
2641 }
2642
2643 /* Enable future boot loads whenever power management unit triggers it
2644 * (e.g. when powering back up after power-save shutdown) */
2645 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2646 BSM_WR_CTRL_REG_BIT_START_EN);
2647
0164b9b4
KA		 2648 return 0;
2649}
2650
5bbe233b
AK		 2651static struct iwl_hcmd_ops iwl3945_hcmd = {
2652 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2653 .commit_rxon = iwl3945_commit_rxon,
65b52bde 2654 .send_bt_config = iwl_send_bt_config,
5bbe233b
AK		 2655};
2656
0164b9b4 2657static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2658 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2659 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2660 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2661 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2662 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2663 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2664 .apm_ops = {
2665 .init = iwl3945_apm_init,
d68b603c 2666 .stop = iwl_apm_stop,
01ec616d 2667 .config = iwl3945_nic_config,
854682ed 2668 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2669 },
e6148917
SO		 2670 .eeprom_ops = {
2671 .regulatory_bands = {
2672 EEPROM_REGULATORY_BAND_1_CHANNELS,
2673 EEPROM_REGULATORY_BAND_2_CHANNELS,
2674 EEPROM_REGULATORY_BAND_3_CHANNELS,
2675 EEPROM_REGULATORY_BAND_4_CHANNELS,
2676 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2677 EEPROM_REGULATORY_BAND_NO_HT40,
2678 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2679 },
2680 .verify_signature = iwlcore_eeprom_verify_signature,
2681 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2682 .release_semaphore = iwl3945_eeprom_release_semaphore,
2683 .query_addr = iwlcore_eeprom_query_addr,
2684 },
75bcfae9 2685 .send_tx_power = iwl3945_send_tx_power,
c2436980 2686 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2687 .post_associate = iwl3945_post_associate,
ef850d7c 2688 .isr = iwl_isr_legacy,
60690a6a 2689 .config_ap = iwl3945_config_ap,
1fa61b2e 2690 .manage_ibss_station = iwl3945_manage_ibss_station,
a6866ac9 2691 .recover_from_tx_stall = iwl_bg_monitor_recover,
a29576a7 2692 .check_plcp_health = iwl3945_good_plcp_health,
17f36fc6
AK		 2693
2694 .debugfs_ops = {
2695 .rx_stats_read = iwl3945_ucode_rx_stats_read,
2696 .tx_stats_read = iwl3945_ucode_tx_stats_read,
2697 .general_stats_read = iwl3945_ucode_general_stats_read,
2698 },
0164b9b4
KA		 2699};
2700
42427b4e
KA		 2701static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2702 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2703 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
94597ab2 2704 .tx_cmd_protection = iwlcore_tx_cmd_protection,
b6e4c55a 2705 .request_scan = iwl3945_request_scan,
42427b4e
KA		 2706};
2707
45d5d805 2708static const struct iwl_ops iwl3945_ops = {
0164b9b4 2709 .lib = &iwl3945_lib,
5bbe233b 2710 .hcmd = &iwl3945_hcmd,
42427b4e 2711 .utils = &iwl3945_hcmd_utils,
e932a609 2712 .led = &iwl3945_led_ops,
0164b9b4
KA		 2713};
2714
c0f20d91 2715static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2716 .name = "3945BG",
a0987a8d
RC		 2717 .fw_name_pre = IWL3945_FW_PRE,
2718 .ucode_api_max = IWL3945_UCODE_API_MAX,
2719 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2720 .sku = IWL_SKU_G,
e6148917
SO		 2721 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2722 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2723 .ops = &iwl3945_ops,
88804e2b 2724 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2725 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2726 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2727 .set_l0s = false,
2728 .use_bsm = true,
b261793d
DH		 2729 .use_isr_legacy = true,
2730 .ht_greenfield_support = false,
f2d0d0e2 2731 .led_compensation = 64,
bc45a670 2732 .broken_powersave = true,
a29576a7 2733 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
ce60659a 2734 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
678b385d 2735 .max_event_log_size = 512,
4e7033ef 2736 .tx_power_by_driver = true,
82b9a121
TW		 2737};
2738
c0f20d91 2739static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2740 .name = "3945ABG",
a0987a8d
RC		 2741 .fw_name_pre = IWL3945_FW_PRE,
2742 .ucode_api_max = IWL3945_UCODE_API_MAX,
2743 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2744 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2745 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2746 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2747 .ops = &iwl3945_ops,
88804e2b 2748 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2749 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2750 .use_isr_legacy = true,
2751 .ht_greenfield_support = false,
f2d0d0e2 2752 .led_compensation = 64,
bc45a670 2753 .broken_powersave = true,
a29576a7 2754 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
ce60659a 2755 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD,
678b385d 2756 .max_event_log_size = 512,
4e7033ef 2757 .tx_power_by_driver = true,
82b9a121
TW		 2758};
2759
a3aa1884 2760DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2761 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2762 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2763 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2764 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2765 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2766 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2767 {0}
2768};
2769
bb8c093b 2770MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
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