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iwlwifi: remove cck_flag from iwl_driver_hw_info
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
3 * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/version.h>
30#include <linux/init.h>
31#include <linux/pci.h>
32#include <linux/dma-mapping.h>
33#include <linux/delay.h>
34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <net/mac80211.h>
39
40#include <linux/etherdevice.h>
b481de9c 41
1156b2c6
ZY		 42#define IWL 3945
43
b481de9c
ZY		 44#include "iwlwifi.h"
45#include "iwl-helpers.h"
46#include "iwl-3945.h"
47#include "iwl-3945-rs.h"
48
49#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_##r##M_IEEE, \
52 IWL_RATE_##ip##M_INDEX, \
53 IWL_RATE_##in##M_INDEX, \
54 IWL_RATE_##rp##M_INDEX, \
55 IWL_RATE_##rn##M_INDEX, \
56 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 57 IWL_RATE_##np##M_INDEX, \
58 IWL_RATE_##r##M_INDEX_TABLE, \
59 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 60
61/*
62 * Parameter order:
63 * rate, prev rate, next rate, prev tgg rate, next tgg rate
64 *
65 * If there isn't a valid next or previous rate then INV is used which
66 * maps to IWL_RATE_INVALID
67 *
68 */
69const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
14577f23
MA		 70 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
71 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
72 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
73 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 74 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
75 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
76 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
77 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
78 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
79 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
80 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
81 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 82};
83
84/* 1 = enable the iwl_disable_events() function */
85#define IWL_EVT_DISABLE (0)
86#define IWL_EVT_DISABLE_SIZE (1532/32)
87
88/**
89 * iwl_disable_events - Disable selected events in uCode event log
90 *
91 * Disable an event by writing "1"s into "disable"
92 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
93 * Default values of 0 enable uCode events to be logged.
94 * Use for only special debugging. This function is just a placeholder as-is,
95 * you'll need to provide the special bits! ...
96 * ... and set IWL_EVT_DISABLE to 1. */
97void iwl_disable_events(struct iwl_priv *priv)
98{
99 int rc;
100 int i;
101 u32 base; /* SRAM address of event log header */
102 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
103 u32 array_size; /* # of u32 entries in array */
104 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
105 0x00000000, /* 31 - 0 Event id numbers */
106 0x00000000, /* 63 - 32 */
107 0x00000000, /* 95 - 64 */
108 0x00000000, /* 127 - 96 */
109 0x00000000, /* 159 - 128 */
110 0x00000000, /* 191 - 160 */
111 0x00000000, /* 223 - 192 */
112 0x00000000, /* 255 - 224 */
113 0x00000000, /* 287 - 256 */
114 0x00000000, /* 319 - 288 */
115 0x00000000, /* 351 - 320 */
116 0x00000000, /* 383 - 352 */
117 0x00000000, /* 415 - 384 */
118 0x00000000, /* 447 - 416 */
119 0x00000000, /* 479 - 448 */
120 0x00000000, /* 511 - 480 */
121 0x00000000, /* 543 - 512 */
122 0x00000000, /* 575 - 544 */
123 0x00000000, /* 607 - 576 */
124 0x00000000, /* 639 - 608 */
125 0x00000000, /* 671 - 640 */
126 0x00000000, /* 703 - 672 */
127 0x00000000, /* 735 - 704 */
128 0x00000000, /* 767 - 736 */
129 0x00000000, /* 799 - 768 */
130 0x00000000, /* 831 - 800 */
131 0x00000000, /* 863 - 832 */
132 0x00000000, /* 895 - 864 */
133 0x00000000, /* 927 - 896 */
134 0x00000000, /* 959 - 928 */
135 0x00000000, /* 991 - 960 */
136 0x00000000, /* 1023 - 992 */
137 0x00000000, /* 1055 - 1024 */
138 0x00000000, /* 1087 - 1056 */
139 0x00000000, /* 1119 - 1088 */
140 0x00000000, /* 1151 - 1120 */
141 0x00000000, /* 1183 - 1152 */
142 0x00000000, /* 1215 - 1184 */
143 0x00000000, /* 1247 - 1216 */
144 0x00000000, /* 1279 - 1248 */
145 0x00000000, /* 1311 - 1280 */
146 0x00000000, /* 1343 - 1312 */
147 0x00000000, /* 1375 - 1344 */
148 0x00000000, /* 1407 - 1376 */
149 0x00000000, /* 1439 - 1408 */
150 0x00000000, /* 1471 - 1440 */
151 0x00000000, /* 1503 - 1472 */
152 };
153
154 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
155 if (!iwl_hw_valid_rtc_data_addr(base)) {
156 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
157 return;
158 }
159
160 rc = iwl_grab_restricted_access(priv);
161 if (rc) {
162 IWL_WARNING("Can not read from adapter at this time.\n");
163 return;
164 }
165
166 disable_ptr = iwl_read_restricted_mem(priv, base + (4 * sizeof(u32)));
167 array_size = iwl_read_restricted_mem(priv, base + (5 * sizeof(u32)));
168 iwl_release_restricted_access(priv);
169
170 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
171 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
172 disable_ptr);
173 rc = iwl_grab_restricted_access(priv);
174 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
175 iwl_write_restricted_mem(priv,
176 disable_ptr +
177 (i * sizeof(u32)),
178 evt_disable[i]);
179
180 iwl_release_restricted_access(priv);
181 } else {
182 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
183 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
184 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
185 disable_ptr, array_size);
186 }
187
188}
189
190/**
191 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
192 * @priv: eeprom and antenna fields are used to determine antenna flags
193 *
194 * priv->eeprom is used to determine if antenna AUX/MAIN are reversed
195 * priv->antenna specifies the antenna diversity mode:
196 *
197 * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
198 * IWL_ANTENNA_MAIN - Force MAIN antenna
199 * IWL_ANTENNA_AUX - Force AUX antenna
200 */
201__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
202{
203 switch (priv->antenna) {
204 case IWL_ANTENNA_DIVERSITY:
205 return 0;
206
207 case IWL_ANTENNA_MAIN:
208 if (priv->eeprom.antenna_switch_type)
209 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
210 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
211
212 case IWL_ANTENNA_AUX:
213 if (priv->eeprom.antenna_switch_type)
214 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
215 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
216 }
217
218 /* bad antenna selector value */
219 IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
220 return 0; /* "diversity" is default if error */
221}
222
223/*****************************************************************************
224 *
225 * Intel PRO/Wireless 3945ABG/BG Network Connection
226 *
227 * RX handler implementations
228 *
229 * Used by iwl-base.c
230 *
231 *****************************************************************************/
232
233void iwl_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
234{
235 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
236 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
237 (int)sizeof(struct iwl_notif_statistics),
238 le32_to_cpu(pkt->len));
239
240 memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
241
242 priv->last_statistics_time = jiffies;
243}
244
245static void iwl3945_handle_data_packet(struct iwl_priv *priv, int is_data,
246 struct iwl_rx_mem_buffer *rxb,
247 struct ieee80211_rx_status *stats,
248 u16 phy_flags)
249{
250 struct ieee80211_hdr *hdr;
251 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
252 struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
253 struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt);
254 short len = le16_to_cpu(rx_hdr->len);
255
256 /* We received data from the HW, so stop the watchdog */
257 if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
258 IWL_DEBUG_DROP("Corruption detected!\n");
259 return;
260 }
261
262 /* We only process data packets if the interface is open */
263 if (unlikely(!priv->is_open)) {
264 IWL_DEBUG_DROP_LIMIT
265 ("Dropping packet while interface is not open.\n");
266 return;
267 }
268 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
269 if (iwl_param_hwcrypto)
270 iwl_set_decrypted_flag(priv, rxb->skb,
271 le32_to_cpu(rx_end->status),
272 stats);
273 iwl_handle_data_packet_monitor(priv, rxb, IWL_RX_DATA(pkt),
274 len, stats, phy_flags);
275 return;
276 }
277
278 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
279 /* Set the size of the skb to the size of the frame */
280 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
281
282 hdr = (void *)rxb->skb->data;
283
284 if (iwl_param_hwcrypto)
285 iwl_set_decrypted_flag(priv, rxb->skb,
286 le32_to_cpu(rx_end->status), stats);
287
288 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
289 rxb->skb = NULL;
290}
291
292static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
293 struct iwl_rx_mem_buffer *rxb)
294{
295 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
296 struct iwl_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
297 struct iwl_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
298 struct iwl_rx_frame_end *rx_end = IWL_RX_END(pkt);
299 struct ieee80211_hdr *header;
300 u16 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
301 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
302 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
303 struct ieee80211_rx_status stats = {
304 .mactime = le64_to_cpu(rx_end->timestamp),
305 .freq = ieee80211chan2mhz(le16_to_cpu(rx_hdr->channel)),
306 .channel = le16_to_cpu(rx_hdr->channel),
307 .phymode = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
308 MODE_IEEE80211G : MODE_IEEE80211A,
309 .antenna = 0,
310 .rate = rx_hdr->rate,
311 .flag = 0,
312 };
313 u8 network_packet;
314 int snr;
315
316 if ((unlikely(rx_stats->phy_count > 20))) {
317 IWL_DEBUG_DROP
318 ("dsp size out of range [0,20]: "
319 "%d/n", rx_stats->phy_count);
320 return;
321 }
322
323 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
324 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
325 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
326 return;
327 }
328
329 if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
330 iwl3945_handle_data_packet(priv, 1, rxb, &stats, phy_flags);
331 return;
332 }
333
334 /* Convert 3945's rssi indicator to dBm */
335 stats.ssi = rx_stats->rssi - IWL_RSSI_OFFSET;
336
337 /* Set default noise value to -127 */
338 if (priv->last_rx_noise == 0)
339 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
340
341 /* 3945 provides noise info for OFDM frames only.
342 * sig_avg and noise_diff are measured by the 3945's digital signal
343 * processor (DSP), and indicate linear levels of signal level and
344 * distortion/noise within the packet preamble after
345 * automatic gain control (AGC). sig_avg should stay fairly
346 * constant if the radio's AGC is working well.
347 * Since these values are linear (not dB or dBm), linear
348 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
349 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
350 * to obtain noise level in dBm.
351 * Calculate stats.signal (quality indicator in %) based on SNR. */
352 if (rx_stats_noise_diff) {
353 snr = rx_stats_sig_avg / rx_stats_noise_diff;
354 stats.noise = stats.ssi - iwl_calc_db_from_ratio(snr);
355 stats.signal = iwl_calc_sig_qual(stats.ssi, stats.noise);
356
357 /* If noise info not available, calculate signal quality indicator (%)
358 * using just the dBm signal level. */
359 } else {
360 stats.noise = priv->last_rx_noise;
361 stats.signal = iwl_calc_sig_qual(stats.ssi, 0);
362 }
363
364
365 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
366 stats.ssi, stats.noise, stats.signal,
367 rx_stats_sig_avg, rx_stats_noise_diff);
368
369 stats.freq = ieee80211chan2mhz(stats.channel);
370
371 /* can be covered by iwl_report_frame() in most cases */
372/* IWL_DEBUG_RX("RX status: 0x%08X\n", rx_end->status); */
373
374 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
375
376 network_packet = iwl_is_network_packet(priv, header);
377
378#ifdef CONFIG_IWLWIFI_DEBUG
379 if (iwl_debug_level & IWL_DL_STATS && net_ratelimit())
380 IWL_DEBUG_STATS
381 ("[%c] %d RSSI: %d Signal: %u, Noise: %u, Rate: %u\n",
382 network_packet ? '*' : ' ',
383 stats.channel, stats.ssi, stats.ssi,
384 stats.ssi, stats.rate);
385
386 if (iwl_debug_level & (IWL_DL_RX))
387 /* Set "1" to report good data frames in groups of 100 */
388 iwl_report_frame(priv, pkt, header, 1);
389#endif
390
391 if (network_packet) {
392 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
393 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
394 priv->last_rx_rssi = stats.ssi;
395 priv->last_rx_noise = stats.noise;
396 }
397
398 switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
399 case IEEE80211_FTYPE_MGMT:
400 switch (le16_to_cpu(header->frame_control) &
401 IEEE80211_FCTL_STYPE) {
402 case IEEE80211_STYPE_PROBE_RESP:
403 case IEEE80211_STYPE_BEACON:{
404 /* If this is a beacon or probe response for
405 * our network then cache the beacon
406 * timestamp */
407 if ((((priv->iw_mode == IEEE80211_IF_TYPE_STA)
408 && !compare_ether_addr(header->addr2,
409 priv->bssid)) ||
410 ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
411 && !compare_ether_addr(header->addr3,
412 priv->bssid)))) {
413 struct ieee80211_mgmt *mgmt =
414 (struct ieee80211_mgmt *)header;
415 __le32 *pos;
416 pos =
417 (__le32 *) & mgmt->u.beacon.
418 timestamp;
419 priv->timestamp0 = le32_to_cpu(pos[0]);
420 priv->timestamp1 = le32_to_cpu(pos[1]);
421 priv->beacon_int = le16_to_cpu(
422 mgmt->u.beacon.beacon_int);
423 if (priv->call_post_assoc_from_beacon &&
424 (priv->iw_mode ==
425 IEEE80211_IF_TYPE_STA))
426 queue_work(priv->workqueue,
427 &priv->post_associate.work);
428
429 priv->call_post_assoc_from_beacon = 0;
430 }
431
432 break;
433 }
434
435 case IEEE80211_STYPE_ACTION:
436 /* TODO: Parse 802.11h frames for CSA... */
437 break;
438
439 /*
440 * TODO: There is no callback function from upper
441 * stack to inform us when associated status. this
442 * work around to sniff assoc_resp management frame
443 * and finish the association process.
444 */
445 case IEEE80211_STYPE_ASSOC_RESP:
446 case IEEE80211_STYPE_REASSOC_RESP:{
447 struct ieee80211_mgmt *mgnt =
448 (struct ieee80211_mgmt *)header;
449 priv->assoc_id = (~((1 << 15) | (1 << 14)) &
450 le16_to_cpu(mgnt->u.
451 assoc_resp.aid));
452 priv->assoc_capability =
453 le16_to_cpu(mgnt->u.assoc_resp.capab_info);
454 if (priv->beacon_int)
455 queue_work(priv->workqueue,
456 &priv->post_associate.work);
457 else
458 priv->call_post_assoc_from_beacon = 1;
459 break;
460 }
461
462 case IEEE80211_STYPE_PROBE_REQ:{
0795af57
JP		 463 DECLARE_MAC_BUF(mac1);
464 DECLARE_MAC_BUF(mac2);
465 DECLARE_MAC_BUF(mac3);
b481de9c
ZY		 466 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS)
467 IWL_DEBUG_DROP
0795af57
JP		 468 ("Dropping (non network): %s"
469 ", %s, %s\n",
470 print_mac(mac1, header->addr1),
471 print_mac(mac2, header->addr2),
472 print_mac(mac3, header->addr3));
b481de9c
ZY		 473 return;
474 }
475 }
476
477 iwl3945_handle_data_packet(priv, 0, rxb, &stats, phy_flags);
478 break;
479
480 case IEEE80211_FTYPE_CTL:
481 break;
482
0795af57
JP		 483 case IEEE80211_FTYPE_DATA: {
484 DECLARE_MAC_BUF(mac1);
485 DECLARE_MAC_BUF(mac2);
486 DECLARE_MAC_BUF(mac3);
487
b481de9c 488 if (unlikely(is_duplicate_packet(priv, header)))
0795af57
JP		 489 IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
490 print_mac(mac1, header->addr1),
491 print_mac(mac2, header->addr2),
492 print_mac(mac3, header->addr3));
b481de9c
ZY		 493 else
494 iwl3945_handle_data_packet(priv, 1, rxb, &stats,
495 phy_flags);
496 break;
497 }
0795af57 498 }
b481de9c
ZY		 499}
500
501int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
502 dma_addr_t addr, u16 len)
503{
504 int count;
505 u32 pad;
506 struct iwl_tfd_frame *tfd = (struct iwl_tfd_frame *)ptr;
507
508 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
509 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
510
511 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
512 IWL_ERROR("Error can not send more than %d chunks\n",
513 NUM_TFD_CHUNKS);
514 return -EINVAL;
515 }
516
517 tfd->pa[count].addr = cpu_to_le32(addr);
518 tfd->pa[count].len = cpu_to_le32(len);
519
520 count++;
521
522 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
523 TFD_CTL_PAD_SET(pad));
524
525 return 0;
526}
527
528/**
fc4b6853 529 * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 530 *
531 * Does NOT advance any indexes
532 */
533int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
534{
535 struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
fc4b6853 536 struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 537 struct pci_dev *dev = priv->pci_dev;
538 int i;
539 int counter;
540
541 /* classify bd */
542 if (txq->q.id == IWL_CMD_QUEUE_NUM)
543 /* nothing to cleanup after for host commands */
544 return 0;
545
546 /* sanity check */
547 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
548 if (counter > NUM_TFD_CHUNKS) {
549 IWL_ERROR("Too many chunks: %i\n", counter);
550 /* @todo issue fatal error, it is quite serious situation */
551 return 0;
552 }
553
554 /* unmap chunks if any */
555
556 for (i = 1; i < counter; i++) {
557 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
558 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 559 if (txq->txb[txq->q.read_ptr].skb[0]) {
560 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
561 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 562 /* Can be called from interrupt context */
563 dev_kfree_skb_any(skb);
fc4b6853 564 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 565 }
566 }
567 }
568 return 0;
569}
570
571u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr)
572{
573 int i;
574 int ret = IWL_INVALID_STATION;
575 unsigned long flags;
0795af57 576 DECLARE_MAC_BUF(mac);
b481de9c
ZY		 577
578 spin_lock_irqsave(&priv->sta_lock, flags);
579 for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
580 if ((priv->stations[i].used) &&
581 (!compare_ether_addr
582 (priv->stations[i].sta.sta.addr, addr))) {
583 ret = i;
584 goto out;
585 }
586
0795af57
JP		 587 IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
588 print_mac(mac, addr), priv->num_stations);
b481de9c
ZY		 589 out:
590 spin_unlock_irqrestore(&priv->sta_lock, flags);
591 return ret;
592}
593
594/**
595 * iwl_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
596 *
597*/
598void iwl_hw_build_tx_cmd_rate(struct iwl_priv *priv,
599 struct iwl_cmd *cmd,
600 struct ieee80211_tx_control *ctrl,
601 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
602{
603 unsigned long flags;
604 u16 rate_index = min(ctrl->tx_rate & 0xffff, IWL_RATE_COUNT - 1);
605 u16 rate_mask;
606 int rate;
607 u8 rts_retry_limit;
608 u8 data_retry_limit;
609 __le32 tx_flags;
610 u16 fc = le16_to_cpu(hdr->frame_control);
611
612 rate = iwl_rates[rate_index].plcp;
613 tx_flags = cmd->cmd.tx.tx_flags;
614
615 /* We need to figure out how to get the sta->supp_rates while
616 * in this running context; perhaps encoding into ctrl->tx_rate? */
617 rate_mask = IWL_RATES_MASK;
618
619 spin_lock_irqsave(&priv->sta_lock, flags);
620
621 priv->stations[sta_id].current_rate.rate_n_flags = rate;
622
623 if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
624 (sta_id != IWL3945_BROADCAST_ID) &&
625 (sta_id != IWL_MULTICAST_ID))
626 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
627
628 spin_unlock_irqrestore(&priv->sta_lock, flags);
629
630 if (tx_id >= IWL_CMD_QUEUE_NUM)
631 rts_retry_limit = 3;
632 else
633 rts_retry_limit = 7;
634
635 if (ieee80211_is_probe_response(fc)) {
636 data_retry_limit = 3;
637 if (data_retry_limit < rts_retry_limit)
638 rts_retry_limit = data_retry_limit;
639 } else
640 data_retry_limit = IWL_DEFAULT_TX_RETRY;
641
642 if (priv->data_retry_limit != -1)
643 data_retry_limit = priv->data_retry_limit;
644
645 if ((fc & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_MGMT) {
646 switch (fc & IEEE80211_FCTL_STYPE) {
647 case IEEE80211_STYPE_AUTH:
648 case IEEE80211_STYPE_DEAUTH:
649 case IEEE80211_STYPE_ASSOC_REQ:
650 case IEEE80211_STYPE_REASSOC_REQ:
651 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
652 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
653 tx_flags |= TX_CMD_FLG_CTS_MSK;
654 }
655 break;
656 default:
657 break;
658 }
659 }
660
661 cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
662 cmd->cmd.tx.data_retry_limit = data_retry_limit;
663 cmd->cmd.tx.rate = rate;
664 cmd->cmd.tx.tx_flags = tx_flags;
665
666 /* OFDM */
14577f23
MA		 667 cmd->cmd.tx.supp_rates[0] =
668 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 669
670 /* CCK */
14577f23 671 cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 672
673 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
674 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
675 cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
676 cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
677}
678
679u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
680{
681 unsigned long flags_spin;
682 struct iwl_station_entry *station;
683
684 if (sta_id == IWL_INVALID_STATION)
685 return IWL_INVALID_STATION;
686
687 spin_lock_irqsave(&priv->sta_lock, flags_spin);
688 station = &priv->stations[sta_id];
689
690 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
691 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
692 station->current_rate.rate_n_flags = tx_rate;
693 station->sta.mode = STA_CONTROL_MODIFY_MSK;
694
695 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
696
697 iwl_send_add_station(priv, &station->sta, flags);
698 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
699 sta_id, tx_rate);
700 return sta_id;
701}
702
703void iwl_hw_card_show_info(struct iwl_priv *priv)
704{
705 IWL_DEBUG_INFO("3945ABG HW Version %u.%u.%u\n",
706 ((priv->eeprom.board_revision >> 8) & 0x0F),
707 ((priv->eeprom.board_revision >> 8) >> 4),
708 (priv->eeprom.board_revision & 0x00FF));
709
710 IWL_DEBUG_INFO("3945ABG PBA Number %.*s\n",
711 (int)sizeof(priv->eeprom.board_pba_number),
712 priv->eeprom.board_pba_number);
713
714 IWL_DEBUG_INFO("EEPROM_ANTENNA_SWITCH_TYPE is 0x%02X\n",
715 priv->eeprom.antenna_switch_type);
716}
717
718static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
719{
720 int rc;
721 unsigned long flags;
722
723 spin_lock_irqsave(&priv->lock, flags);
724 rc = iwl_grab_restricted_access(priv);
725 if (rc) {
726 spin_unlock_irqrestore(&priv->lock, flags);
727 return rc;
728 }
729
730 if (!pwr_max) {
731 u32 val;
732
733 rc = pci_read_config_dword(priv->pci_dev,
734 PCI_POWER_SOURCE, &val);
735 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
736 iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG,
737 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
738 ~APMG_PS_CTRL_MSK_PWR_SRC);
739 iwl_release_restricted_access(priv);
740
741 iwl_poll_bit(priv, CSR_GPIO_IN,
742 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
743 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
744 } else
745 iwl_release_restricted_access(priv);
746 } else {
747 iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG,
748 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
749 ~APMG_PS_CTRL_MSK_PWR_SRC);
750
751 iwl_release_restricted_access(priv);
752 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
753 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
754 }
755 spin_unlock_irqrestore(&priv->lock, flags);
756
757 return rc;
758}
759
760static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
761{
762 int rc;
763 unsigned long flags;
764
765 spin_lock_irqsave(&priv->lock, flags);
766 rc = iwl_grab_restricted_access(priv);
767 if (rc) {
768 spin_unlock_irqrestore(&priv->lock, flags);
769 return rc;
770 }
771
772 iwl_write_restricted(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
773 iwl_write_restricted(priv, FH_RCSR_RPTR_ADDR(0),
774 priv->hw_setting.shared_phys +
775 offsetof(struct iwl_shared, rx_read_ptr[0]));
776 iwl_write_restricted(priv, FH_RCSR_WPTR(0), 0);
777 iwl_write_restricted(priv, FH_RCSR_CONFIG(0),
778 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
779 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
780 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
781 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
782 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
783 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
784 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
785 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
786
787 /* fake read to flush all prev I/O */
788 iwl_read_restricted(priv, FH_RSSR_CTRL);
789
790 iwl_release_restricted_access(priv);
791 spin_unlock_irqrestore(&priv->lock, flags);
792
793 return 0;
794}
795
796static int iwl3945_tx_reset(struct iwl_priv *priv)
797{
798 int rc;
799 unsigned long flags;
800
801 spin_lock_irqsave(&priv->lock, flags);
802 rc = iwl_grab_restricted_access(priv);
803 if (rc) {
804 spin_unlock_irqrestore(&priv->lock, flags);
805 return rc;
806 }
807
808 /* bypass mode */
809 iwl_write_restricted_reg(priv, SCD_MODE_REG, 0x2);
810
811 /* RA 0 is active */
812 iwl_write_restricted_reg(priv, SCD_ARASTAT_REG, 0x01);
813
814 /* all 6 fifo are active */
815 iwl_write_restricted_reg(priv, SCD_TXFACT_REG, 0x3f);
816
817 iwl_write_restricted_reg(priv, SCD_SBYP_MODE_1_REG, 0x010000);
818 iwl_write_restricted_reg(priv, SCD_SBYP_MODE_2_REG, 0x030002);
819 iwl_write_restricted_reg(priv, SCD_TXF4MF_REG, 0x000004);
820 iwl_write_restricted_reg(priv, SCD_TXF5MF_REG, 0x000005);
821
822 iwl_write_restricted(priv, FH_TSSR_CBB_BASE,
823 priv->hw_setting.shared_phys);
824
825 iwl_write_restricted(priv, FH_TSSR_MSG_CONFIG,
826 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
827 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
828 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
829 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
830 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
831 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
832 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
833
834 iwl_release_restricted_access(priv);
835 spin_unlock_irqrestore(&priv->lock, flags);
836
837 return 0;
838}
839
840/**
841 * iwl3945_txq_ctx_reset - Reset TX queue context
842 *
843 * Destroys all DMA structures and initialize them again
844 */
845static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
846{
847 int rc;
848 int txq_id, slots_num;
849
850 iwl_hw_txq_ctx_free(priv);
851
852 /* Tx CMD queue */
853 rc = iwl3945_tx_reset(priv);
854 if (rc)
855 goto error;
856
857 /* Tx queue(s) */
858 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
859 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
860 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
861 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
862 txq_id);
863 if (rc) {
864 IWL_ERROR("Tx %d queue init failed\n", txq_id);
865 goto error;
866 }
867 }
868
869 return rc;
870
871 error:
872 iwl_hw_txq_ctx_free(priv);
873 return rc;
874}
875
876int iwl_hw_nic_init(struct iwl_priv *priv)
877{
878 u8 rev_id;
879 int rc;
880 unsigned long flags;
881 struct iwl_rx_queue *rxq = &priv->rxq;
882
883 iwl_power_init_handle(priv);
884
885 spin_lock_irqsave(&priv->lock, flags);
886 iwl_set_bit(priv, CSR_ANA_PLL_CFG, (1 << 24));
887 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
888 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
889
890 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
891 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
892 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
893 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
894 if (rc < 0) {
895 spin_unlock_irqrestore(&priv->lock, flags);
896 IWL_DEBUG_INFO("Failed to init the card\n");
897 return rc;
898 }
899
900 rc = iwl_grab_restricted_access(priv);
901 if (rc) {
902 spin_unlock_irqrestore(&priv->lock, flags);
903 return rc;
904 }
905 iwl_write_restricted_reg(priv, APMG_CLK_EN_REG,
906 APMG_CLK_VAL_DMA_CLK_RQT |
907 APMG_CLK_VAL_BSM_CLK_RQT);
908 udelay(20);
909 iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
910 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
911 iwl_release_restricted_access(priv);
912 spin_unlock_irqrestore(&priv->lock, flags);
913
914 /* Determine HW type */
915 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
916 if (rc)
917 return rc;
918 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
919
920 iwl3945_nic_set_pwr_src(priv, 1);
921 spin_lock_irqsave(&priv->lock, flags);
922
923 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
924 IWL_DEBUG_INFO("RTP type \n");
925 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
926 IWL_DEBUG_INFO("ALM-MB type\n");
927 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
928 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB);
929 } else {
930 IWL_DEBUG_INFO("ALM-MM type\n");
931 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
932 CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM);
933 }
934
935 spin_unlock_irqrestore(&priv->lock, flags);
936
937 /* Initialize the EEPROM */
938 rc = iwl_eeprom_init(priv);
939 if (rc)
940 return rc;
941
942 spin_lock_irqsave(&priv->lock, flags);
943 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
944 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
945 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
946 CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC);
947 } else
948 IWL_DEBUG_INFO("SKU OP mode is basic\n");
949
950 if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
951 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
952 priv->eeprom.board_revision);
953 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
954 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
955 } else {
956 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
957 priv->eeprom.board_revision);
958 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
959 CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
960 }
961
962 if (priv->eeprom.almgor_m_version <= 1) {
963 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
964 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
965 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
966 priv->eeprom.almgor_m_version);
967 } else {
968 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
969 priv->eeprom.almgor_m_version);
970 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
971 CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
972 }
973 spin_unlock_irqrestore(&priv->lock, flags);
974
975 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
976 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
977
978 if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
979 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
980
981 /* Allocate the RX queue, or reset if it is already allocated */
982 if (!rxq->bd) {
983 rc = iwl_rx_queue_alloc(priv);
984 if (rc) {
985 IWL_ERROR("Unable to initialize Rx queue\n");
986 return -ENOMEM;
987 }
988 } else
989 iwl_rx_queue_reset(priv, rxq);
990
991 iwl_rx_replenish(priv);
992
993 iwl3945_rx_init(priv, rxq);
994
995 spin_lock_irqsave(&priv->lock, flags);
996
997 /* Look at using this instead:
998 rxq->need_update = 1;
999 iwl_rx_queue_update_write_ptr(priv, rxq);
1000 */
1001
1002 rc = iwl_grab_restricted_access(priv);
1003 if (rc) {
1004 spin_unlock_irqrestore(&priv->lock, flags);
1005 return rc;
1006 }
1007 iwl_write_restricted(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1008 iwl_release_restricted_access(priv);
1009
1010 spin_unlock_irqrestore(&priv->lock, flags);
1011
1012 rc = iwl3945_txq_ctx_reset(priv);
1013 if (rc)
1014 return rc;
1015
1016 set_bit(STATUS_INIT, &priv->status);
1017
1018 return 0;
1019}
1020
1021/**
1022 * iwl_hw_txq_ctx_free - Free TXQ Context
1023 *
1024 * Destroy all TX DMA queues and structures
1025 */
1026void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
1027{
1028 int txq_id;
1029
1030 /* Tx queues */
1031 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1032 iwl_tx_queue_free(priv, &priv->txq[txq_id]);
1033}
1034
1035void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
1036{
1037 int queue;
1038 unsigned long flags;
1039
1040 spin_lock_irqsave(&priv->lock, flags);
1041 if (iwl_grab_restricted_access(priv)) {
1042 spin_unlock_irqrestore(&priv->lock, flags);
1043 iwl_hw_txq_ctx_free(priv);
1044 return;
1045 }
1046
1047 /* stop SCD */
1048 iwl_write_restricted_reg(priv, SCD_MODE_REG, 0);
1049
1050 /* reset TFD queues */
1051 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1052 iwl_write_restricted(priv, FH_TCSR_CONFIG(queue), 0x0);
1053 iwl_poll_restricted_bit(priv, FH_TSSR_TX_STATUS,
1054 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1055 1000);
1056 }
1057
1058 iwl_release_restricted_access(priv);
1059 spin_unlock_irqrestore(&priv->lock, flags);
1060
1061 iwl_hw_txq_ctx_free(priv);
1062}
1063
1064int iwl_hw_nic_stop_master(struct iwl_priv *priv)
1065{
1066 int rc = 0;
1067 u32 reg_val;
1068 unsigned long flags;
1069
1070 spin_lock_irqsave(&priv->lock, flags);
1071
1072 /* set stop master bit */
1073 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1074
1075 reg_val = iwl_read32(priv, CSR_GP_CNTRL);
1076
1077 if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1078 (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1079 IWL_DEBUG_INFO("Card in power save, master is already "
1080 "stopped\n");
1081 else {
1082 rc = iwl_poll_bit(priv, CSR_RESET,
1083 CSR_RESET_REG_FLAG_MASTER_DISABLED,
1084 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1085 if (rc < 0) {
1086 spin_unlock_irqrestore(&priv->lock, flags);
1087 return rc;
1088 }
1089 }
1090
1091 spin_unlock_irqrestore(&priv->lock, flags);
1092 IWL_DEBUG_INFO("stop master\n");
1093
1094 return rc;
1095}
1096
1097int iwl_hw_nic_reset(struct iwl_priv *priv)
1098{
1099 int rc;
1100 unsigned long flags;
1101
1102 iwl_hw_nic_stop_master(priv);
1103
1104 spin_lock_irqsave(&priv->lock, flags);
1105
1106 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1107
1108 rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
1109 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1110 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1111
1112 rc = iwl_grab_restricted_access(priv);
1113 if (!rc) {
1114 iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG,
1115 APMG_CLK_VAL_BSM_CLK_RQT);
1116
1117 udelay(10);
1118
1119 iwl_set_bit(priv, CSR_GP_CNTRL,
1120 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1121
1122 iwl_write_restricted_reg(priv, APMG_RTC_INT_MSK_REG, 0x0);
1123 iwl_write_restricted_reg(priv, APMG_RTC_INT_STT_REG,
1124 0xFFFFFFFF);
1125
1126 /* enable DMA */
1127 iwl_write_restricted_reg(priv, APMG_CLK_EN_REG,
1128 APMG_CLK_VAL_DMA_CLK_RQT |
1129 APMG_CLK_VAL_BSM_CLK_RQT);
1130 udelay(10);
1131
1132 iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
1133 APMG_PS_CTRL_VAL_RESET_REQ);
1134 udelay(5);
1135 iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
1136 APMG_PS_CTRL_VAL_RESET_REQ);
1137 iwl_release_restricted_access(priv);
1138 }
1139
1140 /* Clear the 'host command active' bit... */
1141 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1142
1143 wake_up_interruptible(&priv->wait_command_queue);
1144 spin_unlock_irqrestore(&priv->lock, flags);
1145
1146 return rc;
1147}
1148
1149/**
1150 * iwl_hw_reg_adjust_power_by_temp - return index delta into power gain settings table
1151 */
1152static int iwl_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1153{
1154 return (new_reading - old_reading) * (-11) / 100;
1155}
1156
1157/**
1158 * iwl_hw_reg_temp_out_of_range - Keep temperature in sane range
1159 */
1160static inline int iwl_hw_reg_temp_out_of_range(int temperature)
1161{
1162 return (((temperature < -260) || (temperature > 25)) ? 1 : 0);
1163}
1164
1165int iwl_hw_get_temperature(struct iwl_priv *priv)
1166{
1167 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1168}
1169
1170/**
1171 * iwl_hw_reg_txpower_get_temperature - get current temperature by reading from NIC
1172 */
1173static int iwl_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1174{
1175 int temperature;
1176
1177 temperature = iwl_hw_get_temperature(priv);
1178
1179 /* driver's okay range is -260 to +25.
1180 * human readable okay range is 0 to +285 */
1181 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1182
1183 /* handle insane temp reading */
1184 if (iwl_hw_reg_temp_out_of_range(temperature)) {
1185 IWL_ERROR("Error bad temperature value %d\n", temperature);
1186
1187 /* if really really hot(?),
1188 * substitute the 3rd band/group's temp measured at factory */
1189 if (priv->last_temperature > 100)
1190 temperature = priv->eeprom.groups[2].temperature;
1191 else /* else use most recent "sane" value from driver */
1192 temperature = priv->last_temperature;
1193 }
1194
1195 return temperature; /* raw, not "human readable" */
1196}
1197
1198/* Adjust Txpower only if temperature variance is greater than threshold.
1199 *
1200 * Both are lower than older versions' 9 degrees */
1201#define IWL_TEMPERATURE_LIMIT_TIMER 6
1202
1203/**
1204 * is_temp_calib_needed - determines if new calibration is needed
1205 *
1206 * records new temperature in tx_mgr->temperature.
1207 * replaces tx_mgr->last_temperature *only* if calib needed
1208 * (assumes caller will actually do the calibration!). */
1209static int is_temp_calib_needed(struct iwl_priv *priv)
1210{
1211 int temp_diff;
1212
1213 priv->temperature = iwl_hw_reg_txpower_get_temperature(priv);
1214 temp_diff = priv->temperature - priv->last_temperature;
1215
1216 /* get absolute value */
1217 if (temp_diff < 0) {
1218 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1219 temp_diff = -temp_diff;
1220 } else if (temp_diff == 0)
1221 IWL_DEBUG_POWER("Same temp,\n");
1222 else
1223 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1224
1225 /* if we don't need calibration, *don't* update last_temperature */
1226 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1227 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1228 return 0;
1229 }
1230
1231 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1232
1233 /* assume that caller will actually do calib ...
1234 * update the "last temperature" value */
1235 priv->last_temperature = priv->temperature;
1236 return 1;
1237}
1238
1239#define IWL_MAX_GAIN_ENTRIES 78
1240#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1241#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1242
1243/* radio and DSP power table, each step is 1/2 dB.
1244 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1245static struct iwl_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1246 {
1247 {251, 127}, /* 2.4 GHz, highest power */
1248 {251, 127},
1249 {251, 127},
1250 {251, 127},
1251 {251, 125},
1252 {251, 110},
1253 {251, 105},
1254 {251, 98},
1255 {187, 125},
1256 {187, 115},
1257 {187, 108},
1258 {187, 99},
1259 {243, 119},
1260 {243, 111},
1261 {243, 105},
1262 {243, 97},
1263 {243, 92},
1264 {211, 106},
1265 {211, 100},
1266 {179, 120},
1267 {179, 113},
1268 {179, 107},
1269 {147, 125},
1270 {147, 119},
1271 {147, 112},
1272 {147, 106},
1273 {147, 101},
1274 {147, 97},
1275 {147, 91},
1276 {115, 107},
1277 {235, 121},
1278 {235, 115},
1279 {235, 109},
1280 {203, 127},
1281 {203, 121},
1282 {203, 115},
1283 {203, 108},
1284 {203, 102},
1285 {203, 96},
1286 {203, 92},
1287 {171, 110},
1288 {171, 104},
1289 {171, 98},
1290 {139, 116},
1291 {227, 125},
1292 {227, 119},
1293 {227, 113},
1294 {227, 107},
1295 {227, 101},
1296 {227, 96},
1297 {195, 113},
1298 {195, 106},
1299 {195, 102},
1300 {195, 95},
1301 {163, 113},
1302 {163, 106},
1303 {163, 102},
1304 {163, 95},
1305 {131, 113},
1306 {131, 106},
1307 {131, 102},
1308 {131, 95},
1309 {99, 113},
1310 {99, 106},
1311 {99, 102},
1312 {99, 95},
1313 {67, 113},
1314 {67, 106},
1315 {67, 102},
1316 {67, 95},
1317 {35, 113},
1318 {35, 106},
1319 {35, 102},
1320 {35, 95},
1321 {3, 113},
1322 {3, 106},
1323 {3, 102},
1324 {3, 95} }, /* 2.4 GHz, lowest power */
1325 {
1326 {251, 127}, /* 5.x GHz, highest power */
1327 {251, 120},
1328 {251, 114},
1329 {219, 119},
1330 {219, 101},
1331 {187, 113},
1332 {187, 102},
1333 {155, 114},
1334 {155, 103},
1335 {123, 117},
1336 {123, 107},
1337 {123, 99},
1338 {123, 92},
1339 {91, 108},
1340 {59, 125},
1341 {59, 118},
1342 {59, 109},
1343 {59, 102},
1344 {59, 96},
1345 {59, 90},
1346 {27, 104},
1347 {27, 98},
1348 {27, 92},
1349 {115, 118},
1350 {115, 111},
1351 {115, 104},
1352 {83, 126},
1353 {83, 121},
1354 {83, 113},
1355 {83, 105},
1356 {83, 99},
1357 {51, 118},
1358 {51, 111},
1359 {51, 104},
1360 {51, 98},
1361 {19, 116},
1362 {19, 109},
1363 {19, 102},
1364 {19, 98},
1365 {19, 93},
1366 {171, 113},
1367 {171, 107},
1368 {171, 99},
1369 {139, 120},
1370 {139, 113},
1371 {139, 107},
1372 {139, 99},
1373 {107, 120},
1374 {107, 113},
1375 {107, 107},
1376 {107, 99},
1377 {75, 120},
1378 {75, 113},
1379 {75, 107},
1380 {75, 99},
1381 {43, 120},
1382 {43, 113},
1383 {43, 107},
1384 {43, 99},
1385 {11, 120},
1386 {11, 113},
1387 {11, 107},
1388 {11, 99},
1389 {131, 107},
1390 {131, 99},
1391 {99, 120},
1392 {99, 113},
1393 {99, 107},
1394 {99, 99},
1395 {67, 120},
1396 {67, 113},
1397 {67, 107},
1398 {67, 99},
1399 {35, 120},
1400 {35, 113},
1401 {35, 107},
1402 {35, 99},
1403 {3, 120} } /* 5.x GHz, lowest power */
1404};
1405
1406static inline u8 iwl_hw_reg_fix_power_index(int index)
1407{
1408 if (index < 0)
1409 return 0;
1410 if (index >= IWL_MAX_GAIN_ENTRIES)
1411 return IWL_MAX_GAIN_ENTRIES - 1;
1412 return (u8) index;
1413}
1414
1415/* Kick off thermal recalibration check every 60 seconds */
1416#define REG_RECALIB_PERIOD (60)
1417
1418/**
1419 * iwl_hw_reg_set_scan_power - Set Tx power for scan probe requests
1420 *
1421 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1422 * or 6 Mbit (OFDM) rates.
1423 */
1424static void iwl_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1425 s32 rate_index, const s8 *clip_pwrs,
1426 struct iwl_channel_info *ch_info,
1427 int band_index)
1428{
1429 struct iwl_scan_power_info *scan_power_info;
1430 s8 power;
1431 u8 power_index;
1432
1433 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1434
1435 /* use this channel group's 6Mbit clipping/saturation pwr,
1436 * but cap at regulatory scan power restriction (set during init
1437 * based on eeprom channel data) for this channel. */
14577f23 1438 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1439
1440 /* further limit to user's max power preference.
1441 * FIXME: Other spectrum management power limitations do not
1442 * seem to apply?? */
1443 power = min(power, priv->user_txpower_limit);
1444 scan_power_info->requested_power = power;
1445
1446 /* find difference between new scan *power* and current "normal"
1447 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1448 * current "normal" temperature-compensated Tx power *index* for
1449 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1450 * *index*. */
1451 power_index = ch_info->power_info[rate_index].power_table_index
1452 - (power - ch_info->power_info
14577f23 1453 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1454
1455 /* store reference index that we use when adjusting *all* scan
1456 * powers. So we can accommodate user (all channel) or spectrum
1457 * management (single channel) power changes "between" temperature
1458 * feedback compensation procedures.
1459 * don't force fit this reference index into gain table; it may be a
1460 * negative number. This will help avoid errors when we're at
1461 * the lower bounds (highest gains, for warmest temperatures)
1462 * of the table. */
1463
1464 /* don't exceed table bounds for "real" setting */
1465 power_index = iwl_hw_reg_fix_power_index(power_index);
1466
1467 scan_power_info->power_table_index = power_index;
1468 scan_power_info->tpc.tx_gain =
1469 power_gain_table[band_index][power_index].tx_gain;
1470 scan_power_info->tpc.dsp_atten =
1471 power_gain_table[band_index][power_index].dsp_atten;
1472}
1473
1474/**
1475 * iwl_hw_reg_send_txpower - fill in Tx Power command with gain settings
1476 *
1477 * Configures power settings for all rates for the current channel,
1478 * using values from channel info struct, and send to NIC
1479 */
1480int iwl_hw_reg_send_txpower(struct iwl_priv *priv)
1481{
14577f23 1482 int rate_idx, i;
b481de9c
ZY		 1483 const struct iwl_channel_info *ch_info = NULL;
1484 struct iwl_txpowertable_cmd txpower = {
1485 .channel = priv->active_rxon.channel,
1486 };
1487
1488 txpower.band = (priv->phymode == MODE_IEEE80211A) ? 0 : 1;
1489 ch_info = iwl_get_channel_info(priv,
1490 priv->phymode,
1491 le16_to_cpu(priv->active_rxon.channel));
1492 if (!ch_info) {
1493 IWL_ERROR
1494 ("Failed to get channel info for channel %d [%d]\n",
1495 le16_to_cpu(priv->active_rxon.channel), priv->phymode);
1496 return -EINVAL;
1497 }
1498
1499 if (!is_channel_valid(ch_info)) {
1500 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1501 "non-Tx channel.\n");
1502 return 0;
1503 }
1504
1505 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1506 /* Fill OFDM rate */
1507 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1508 rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1509
1510 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1511 txpower.power[i].rate = iwl_rates[rate_idx].plcp;
b481de9c
ZY		 1512
1513 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1514 le16_to_cpu(txpower.channel),
1515 txpower.band,
14577f23
MA		 1516 txpower.power[i].tpc.tx_gain,
1517 txpower.power[i].tpc.dsp_atten,
1518 txpower.power[i].rate);
1519 }
1520 /* Fill CCK rates */
1521 for (rate_idx = IWL_FIRST_CCK_RATE;
1522 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1523 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1524 txpower.power[i].rate = iwl_rates[rate_idx].plcp;
1525
1526 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1527 le16_to_cpu(txpower.channel),
1528 txpower.band,
1529 txpower.power[i].tpc.tx_gain,
1530 txpower.power[i].tpc.dsp_atten,
1531 txpower.power[i].rate);
b481de9c
ZY		 1532 }
1533
1534 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
14577f23 1535 sizeof(struct iwl_txpowertable_cmd), &txpower);
b481de9c
ZY		 1536
1537}
1538
1539/**
1540 * iwl_hw_reg_set_new_power - Configures power tables at new levels
1541 * @ch_info: Channel to update. Uses power_info.requested_power.
1542 *
1543 * Replace requested_power and base_power_index ch_info fields for
1544 * one channel.
1545 *
1546 * Called if user or spectrum management changes power preferences.
1547 * Takes into account h/w and modulation limitations (clip power).
1548 *
1549 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1550 *
1551 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1552 * properly fill out the scan powers, and actual h/w gain settings,
1553 * and send changes to NIC
1554 */
1555static int iwl_hw_reg_set_new_power(struct iwl_priv *priv,
1556 struct iwl_channel_info *ch_info)
1557{
1558 struct iwl_channel_power_info *power_info;
1559 int power_changed = 0;
1560 int i;
1561 const s8 *clip_pwrs;
1562 int power;
1563
1564 /* Get this chnlgrp's rate-to-max/clip-powers table */
1565 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1566
1567 /* Get this channel's rate-to-current-power settings table */
1568 power_info = ch_info->power_info;
1569
1570 /* update OFDM Txpower settings */
14577f23 1571 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1572 i++, ++power_info) {
1573 int delta_idx;
1574
1575 /* limit new power to be no more than h/w capability */
1576 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1577 if (power == power_info->requested_power)
1578 continue;
1579
1580 /* find difference between old and new requested powers,
1581 * update base (non-temp-compensated) power index */
1582 delta_idx = (power - power_info->requested_power) * 2;
1583 power_info->base_power_index -= delta_idx;
1584
1585 /* save new requested power value */
1586 power_info->requested_power = power;
1587
1588 power_changed = 1;
1589 }
1590
1591 /* update CCK Txpower settings, based on OFDM 12M setting ...
1592 * ... all CCK power settings for a given channel are the *same*. */
1593 if (power_changed) {
1594 power =
14577f23 1595 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1596 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1597
1598 /* do all CCK rates' iwl_channel_power_info structures */
14577f23 1599 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1600 power_info->requested_power = power;
1601 power_info->base_power_index =
14577f23 1602 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1603 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1604 ++power_info;
1605 }
1606 }
1607
1608 return 0;
1609}
1610
1611/**
1612 * iwl_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1613 *
1614 * NOTE: Returned power limit may be less (but not more) than requested,
1615 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1616 * (no consideration for h/w clipping limitations).
1617 */
1618static int iwl_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1619{
1620 s8 max_power;
1621
1622#if 0
1623 /* if we're using TGd limits, use lower of TGd or EEPROM */
1624 if (ch_info->tgd_data.max_power != 0)
1625 max_power = min(ch_info->tgd_data.max_power,
1626 ch_info->eeprom.max_power_avg);
1627
1628 /* else just use EEPROM limits */
1629 else
1630#endif
1631 max_power = ch_info->eeprom.max_power_avg;
1632
1633 return min(max_power, ch_info->max_power_avg);
1634}
1635
1636/**
1637 * iwl_hw_reg_comp_txpower_temp - Compensate for temperature
1638 *
1639 * Compensate txpower settings of *all* channels for temperature.
1640 * This only accounts for the difference between current temperature
1641 * and the factory calibration temperatures, and bases the new settings
1642 * on the channel's base_power_index.
1643 *
1644 * If RxOn is "associated", this sends the new Txpower to NIC!
1645 */
1646static int iwl_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1647{
1648 struct iwl_channel_info *ch_info = NULL;
1649 int delta_index;
1650 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1651 u8 a_band;
1652 u8 rate_index;
1653 u8 scan_tbl_index;
1654 u8 i;
1655 int ref_temp;
1656 int temperature = priv->temperature;
1657
1658 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1659 for (i = 0; i < priv->channel_count; i++) {
1660 ch_info = &priv->channel_info[i];
1661 a_band = is_channel_a_band(ch_info);
1662
1663 /* Get this chnlgrp's factory calibration temperature */
1664 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1665 temperature;
1666
1667 /* get power index adjustment based on curr and factory
1668 * temps */
1669 delta_index = iwl_hw_reg_adjust_power_by_temp(temperature,
1670 ref_temp);
1671
1672 /* set tx power value for all rates, OFDM and CCK */
1673 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1674 rate_index++) {
1675 int power_idx =
1676 ch_info->power_info[rate_index].base_power_index;
1677
1678 /* temperature compensate */
1679 power_idx += delta_index;
1680
1681 /* stay within table range */
1682 power_idx = iwl_hw_reg_fix_power_index(power_idx);
1683 ch_info->power_info[rate_index].
1684 power_table_index = (u8) power_idx;
1685 ch_info->power_info[rate_index].tpc =
1686 power_gain_table[a_band][power_idx];
1687 }
1688
1689 /* Get this chnlgrp's rate-to-max/clip-powers table */
1690 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1691
1692 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1693 for (scan_tbl_index = 0;
1694 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1695 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1696 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
b481de9c
ZY		 1697 iwl_hw_reg_set_scan_power(priv, scan_tbl_index,
1698 actual_index, clip_pwrs,
1699 ch_info, a_band);
1700 }
1701 }
1702
1703 /* send Txpower command for current channel to ucode */
1704 return iwl_hw_reg_send_txpower(priv);
1705}
1706
1707int iwl_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1708{
1709 struct iwl_channel_info *ch_info;
1710 s8 max_power;
1711 u8 a_band;
1712 u8 i;
1713
1714 if (priv->user_txpower_limit == power) {
1715 IWL_DEBUG_POWER("Requested Tx power same as current "
1716 "limit: %ddBm.\n", power);
1717 return 0;
1718 }
1719
1720 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1721 priv->user_txpower_limit = power;
1722
1723 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1724
1725 for (i = 0; i < priv->channel_count; i++) {
1726 ch_info = &priv->channel_info[i];
1727 a_band = is_channel_a_band(ch_info);
1728
1729 /* find minimum power of all user and regulatory constraints
1730 * (does not consider h/w clipping limitations) */
1731 max_power = iwl_hw_reg_get_ch_txpower_limit(ch_info);
1732 max_power = min(power, max_power);
1733 if (max_power != ch_info->curr_txpow) {
1734 ch_info->curr_txpow = max_power;
1735
1736 /* this considers the h/w clipping limitations */
1737 iwl_hw_reg_set_new_power(priv, ch_info);
1738 }
1739 }
1740
1741 /* update txpower settings for all channels,
1742 * send to NIC if associated. */
1743 is_temp_calib_needed(priv);
1744 iwl_hw_reg_comp_txpower_temp(priv);
1745
1746 return 0;
1747}
1748
1749/* will add 3945 channel switch cmd handling later */
1750int iwl_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1751{
1752 return 0;
1753}
1754
1755/**
1756 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1757 *
1758 * -- reset periodic timer
1759 * -- see if temp has changed enough to warrant re-calibration ... if so:
1760 * -- correct coeffs for temp (can reset temp timer)
1761 * -- save this temp as "last",
1762 * -- send new set of gain settings to NIC
1763 * NOTE: This should continue working, even when we're not associated,
1764 * so we can keep our internal table of scan powers current. */
1765void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
1766{
1767 /* This will kick in the "brute force"
1768 * iwl_hw_reg_comp_txpower_temp() below */
1769 if (!is_temp_calib_needed(priv))
1770 goto reschedule;
1771
1772 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1773 * This is based *only* on current temperature,
1774 * ignoring any previous power measurements */
1775 iwl_hw_reg_comp_txpower_temp(priv);
1776
1777 reschedule:
1778 queue_delayed_work(priv->workqueue,
1779 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1780}
1781
1782void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1783{
1784 struct iwl_priv *priv = container_of(work, struct iwl_priv,
1785 thermal_periodic.work);
1786
1787 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1788 return;
1789
1790 mutex_lock(&priv->mutex);
1791 iwl3945_reg_txpower_periodic(priv);
1792 mutex_unlock(&priv->mutex);
1793}
1794
1795/**
1796 * iwl_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1797 * for the channel.
1798 *
1799 * This function is used when initializing channel-info structs.
1800 *
1801 * NOTE: These channel groups do *NOT* match the bands above!
1802 * These channel groups are based on factory-tested channels;
1803 * on A-band, EEPROM's "group frequency" entries represent the top
1804 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
1805 */
1806static u16 iwl_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
1807 const struct iwl_channel_info *ch_info)
1808{
1809 struct iwl_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1810 u8 group;
1811 u16 group_index = 0; /* based on factory calib frequencies */
1812 u8 grp_channel;
1813
1814 /* Find the group index for the channel ... don't use index 1(?) */
1815 if (is_channel_a_band(ch_info)) {
1816 for (group = 1; group < 5; group++) {
1817 grp_channel = ch_grp[group].group_channel;
1818 if (ch_info->channel <= grp_channel) {
1819 group_index = group;
1820 break;
1821 }
1822 }
1823 /* group 4 has a few channels *above* its factory cal freq */
1824 if (group == 5)
1825 group_index = 4;
1826 } else
1827 group_index = 0; /* 2.4 GHz, group 0 */
1828
1829 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1830 group_index);
1831 return group_index;
1832}
1833
1834/**
1835 * iwl_hw_reg_get_matched_power_index - Interpolate to get nominal index
1836 *
1837 * Interpolate to get nominal (i.e. at factory calibration temperature) index
1838 * into radio/DSP gain settings table for requested power.
1839 */
1840static int iwl_hw_reg_get_matched_power_index(struct iwl_priv *priv,
1841 s8 requested_power,
1842 s32 setting_index, s32 *new_index)
1843{
1844 const struct iwl_eeprom_txpower_group *chnl_grp = NULL;
1845 s32 index0, index1;
1846 s32 power = 2 * requested_power;
1847 s32 i;
1848 const struct iwl_eeprom_txpower_sample *samples;
1849 s32 gains0, gains1;
1850 s32 res;
1851 s32 denominator;
1852
1853 chnl_grp = &priv->eeprom.groups[setting_index];
1854 samples = chnl_grp->samples;
1855 for (i = 0; i < 5; i++) {
1856 if (power == samples[i].power) {
1857 *new_index = samples[i].gain_index;
1858 return 0;
1859 }
1860 }
1861
1862 if (power > samples[1].power) {
1863 index0 = 0;
1864 index1 = 1;
1865 } else if (power > samples[2].power) {
1866 index0 = 1;
1867 index1 = 2;
1868 } else if (power > samples[3].power) {
1869 index0 = 2;
1870 index1 = 3;
1871 } else {
1872 index0 = 3;
1873 index1 = 4;
1874 }
1875
1876 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
1877 if (denominator == 0)
1878 return -EINVAL;
1879 gains0 = (s32) samples[index0].gain_index * (1 << 19);
1880 gains1 = (s32) samples[index1].gain_index * (1 << 19);
1881 res = gains0 + (gains1 - gains0) *
1882 ((s32) power - (s32) samples[index0].power) / denominator +
1883 (1 << 18);
1884 *new_index = res >> 19;
1885 return 0;
1886}
1887
1888static void iwl_hw_reg_init_channel_groups(struct iwl_priv *priv)
1889{
1890 u32 i;
1891 s32 rate_index;
1892 const struct iwl_eeprom_txpower_group *group;
1893
1894 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
1895
1896 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
1897 s8 *clip_pwrs; /* table of power levels for each rate */
1898 s8 satur_pwr; /* saturation power for each chnl group */
1899 group = &priv->eeprom.groups[i];
1900
1901 /* sanity check on factory saturation power value */
1902 if (group->saturation_power < 40) {
1903 IWL_WARNING("Error: saturation power is %d, "
1904 "less than minimum expected 40\n",
1905 group->saturation_power);
1906 return;
1907 }
1908
1909 /*
1910 * Derive requested power levels for each rate, based on
1911 * hardware capabilities (saturation power for band).
1912 * Basic value is 3dB down from saturation, with further
1913 * power reductions for highest 3 data rates. These
1914 * backoffs provide headroom for high rate modulation
1915 * power peaks, without too much distortion (clipping).
1916 */
1917 /* we'll fill in this array with h/w max power levels */
1918 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
1919
1920 /* divide factory saturation power by 2 to find -3dB level */
1921 satur_pwr = (s8) (group->saturation_power >> 1);
1922
1923 /* fill in channel group's nominal powers for each rate */
1924 for (rate_index = 0;
1925 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
1926 switch (rate_index) {
14577f23 1927 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 1928 if (i == 0) /* B/G */
1929 *clip_pwrs = satur_pwr;
1930 else /* A */
1931 *clip_pwrs = satur_pwr - 5;
1932 break;
14577f23 1933 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 1934 if (i == 0)
1935 *clip_pwrs = satur_pwr - 7;
1936 else
1937 *clip_pwrs = satur_pwr - 10;
1938 break;
14577f23 1939 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 1940 if (i == 0)
1941 *clip_pwrs = satur_pwr - 9;
1942 else
1943 *clip_pwrs = satur_pwr - 12;
1944 break;
1945 default:
1946 *clip_pwrs = satur_pwr;
1947 break;
1948 }
1949 }
1950 }
1951}
1952
1953/**
1954 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
1955 *
1956 * Second pass (during init) to set up priv->channel_info
1957 *
1958 * Set up Tx-power settings in our channel info database for each VALID
1959 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
1960 * and current temperature.
1961 *
1962 * Since this is based on current temperature (at init time), these values may
1963 * not be valid for very long, but it gives us a starting/default point,
1964 * and allows us to active (i.e. using Tx) scan.
1965 *
1966 * This does *not* write values to NIC, just sets up our internal table.
1967 */
1968int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
1969{
1970 struct iwl_channel_info *ch_info = NULL;
1971 struct iwl_channel_power_info *pwr_info;
1972 int delta_index;
1973 u8 rate_index;
1974 u8 scan_tbl_index;
1975 const s8 *clip_pwrs; /* array of power levels for each rate */
1976 u8 gain, dsp_atten;
1977 s8 power;
1978 u8 pwr_index, base_pwr_index, a_band;
1979 u8 i;
1980 int temperature;
1981
1982 /* save temperature reference,
1983 * so we can determine next time to calibrate */
1984 temperature = iwl_hw_reg_txpower_get_temperature(priv);
1985 priv->last_temperature = temperature;
1986
1987 iwl_hw_reg_init_channel_groups(priv);
1988
1989 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
1990 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
1991 i++, ch_info++) {
1992 a_band = is_channel_a_band(ch_info);
1993 if (!is_channel_valid(ch_info))
1994 continue;
1995
1996 /* find this channel's channel group (*not* "band") index */
1997 ch_info->group_index =
1998 iwl_hw_reg_get_ch_grp_index(priv, ch_info);
1999
2000 /* Get this chnlgrp's rate->max/clip-powers table */
2001 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2002
2003 /* calculate power index *adjustment* value according to
2004 * diff between current temperature and factory temperature */
2005 delta_index = iwl_hw_reg_adjust_power_by_temp(temperature,
2006 priv->eeprom.groups[ch_info->group_index].
2007 temperature);
2008
2009 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2010 ch_info->channel, delta_index, temperature +
2011 IWL_TEMP_CONVERT);
2012
2013 /* set tx power value for all OFDM rates */
2014 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2015 rate_index++) {
2016 s32 power_idx;
2017 int rc;
2018
2019 /* use channel group's clip-power table,
2020 * but don't exceed channel's max power */
2021 s8 pwr = min(ch_info->max_power_avg,
2022 clip_pwrs[rate_index]);
2023
2024 pwr_info = &ch_info->power_info[rate_index];
2025
2026 /* get base (i.e. at factory-measured temperature)
2027 * power table index for this rate's power */
2028 rc = iwl_hw_reg_get_matched_power_index(priv, pwr,
2029 ch_info->group_index,
2030 &power_idx);
2031 if (rc) {
2032 IWL_ERROR("Invalid power index\n");
2033 return rc;
2034 }
2035 pwr_info->base_power_index = (u8) power_idx;
2036
2037 /* temperature compensate */
2038 power_idx += delta_index;
2039
2040 /* stay within range of gain table */
2041 power_idx = iwl_hw_reg_fix_power_index(power_idx);
2042
2043 /* fill 1 OFDM rate's iwl_channel_power_info struct */
2044 pwr_info->requested_power = pwr;
2045 pwr_info->power_table_index = (u8) power_idx;
2046 pwr_info->tpc.tx_gain =
2047 power_gain_table[a_band][power_idx].tx_gain;
2048 pwr_info->tpc.dsp_atten =
2049 power_gain_table[a_band][power_idx].dsp_atten;
2050 }
2051
2052 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2053 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2054 power = pwr_info->requested_power +
2055 IWL_CCK_FROM_OFDM_POWER_DIFF;
2056 pwr_index = pwr_info->power_table_index +
2057 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2058 base_pwr_index = pwr_info->base_power_index +
2059 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2060
2061 /* stay within table range */
2062 pwr_index = iwl_hw_reg_fix_power_index(pwr_index);
2063 gain = power_gain_table[a_band][pwr_index].tx_gain;
2064 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2065
2066 /* fill each CCK rate's iwl_channel_power_info structure
2067 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2068 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2069 for (rate_index = 0;
2070 rate_index < IWL_CCK_RATES; rate_index++) {
2071 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2072 pwr_info->requested_power = power;
2073 pwr_info->power_table_index = pwr_index;
2074 pwr_info->base_power_index = base_pwr_index;
2075 pwr_info->tpc.tx_gain = gain;
2076 pwr_info->tpc.dsp_atten = dsp_atten;
2077 }
2078
2079 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2080 for (scan_tbl_index = 0;
2081 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2082 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2083 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
b481de9c
ZY		 2084 iwl_hw_reg_set_scan_power(priv, scan_tbl_index,
2085 actual_index, clip_pwrs, ch_info, a_band);
2086 }
2087 }
2088
2089 return 0;
2090}
2091
2092int iwl_hw_rxq_stop(struct iwl_priv *priv)
2093{
2094 int rc;
2095 unsigned long flags;
2096
2097 spin_lock_irqsave(&priv->lock, flags);
2098 rc = iwl_grab_restricted_access(priv);
2099 if (rc) {
2100 spin_unlock_irqrestore(&priv->lock, flags);
2101 return rc;
2102 }
2103
2104 iwl_write_restricted(priv, FH_RCSR_CONFIG(0), 0);
2105 rc = iwl_poll_restricted_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2106 if (rc < 0)
2107 IWL_ERROR("Can't stop Rx DMA.\n");
2108
2109 iwl_release_restricted_access(priv);
2110 spin_unlock_irqrestore(&priv->lock, flags);
2111
2112 return 0;
2113}
2114
2115int iwl_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2116{
2117 int rc;
2118 unsigned long flags;
2119 int txq_id = txq->q.id;
2120
2121 struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
2122
2123 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2124
2125 spin_lock_irqsave(&priv->lock, flags);
2126 rc = iwl_grab_restricted_access(priv);
2127 if (rc) {
2128 spin_unlock_irqrestore(&priv->lock, flags);
2129 return rc;
2130 }
2131 iwl_write_restricted(priv, FH_CBCC_CTRL(txq_id), 0);
2132 iwl_write_restricted(priv, FH_CBCC_BASE(txq_id), 0);
2133
2134 iwl_write_restricted(priv, FH_TCSR_CONFIG(txq_id),
2135 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2136 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2137 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2138 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2139 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2140 iwl_release_restricted_access(priv);
2141
2142 /* fake read to flush all prev. writes */
2143 iwl_read32(priv, FH_TSSR_CBB_BASE);
2144 spin_unlock_irqrestore(&priv->lock, flags);
2145
2146 return 0;
2147}
2148
2149int iwl_hw_get_rx_read(struct iwl_priv *priv)
2150{
2151 struct iwl_shared *shared_data = priv->hw_setting.shared_virt;
2152
2153 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2154}
2155
2156/**
2157 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2158 */
2159int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2160{
14577f23 2161 int rc, i, index, prev_index;
b481de9c
ZY		 2162 struct iwl_rate_scaling_cmd rate_cmd = {
2163 .reserved = {0, 0, 0},
2164 };
2165 struct iwl_rate_scaling_info *table = rate_cmd.table;
2166
2167 for (i = 0; i < ARRAY_SIZE(iwl_rates); i++) {
14577f23
MA		 2168 index = iwl_rates[i].table_rs_index;
2169
2170 table[index].rate_n_flags =
b481de9c 2171 iwl_hw_set_rate_n_flags(iwl_rates[i].plcp, 0);
14577f23
MA		 2172 table[index].try_cnt = priv->retry_rate;
2173 prev_index = iwl_get_prev_ieee_rate(i);
2174 table[index].next_rate_index = iwl_rates[prev_index].table_rs_index;
b481de9c
ZY		 2175 }
2176
2177 switch (priv->phymode) {
2178 case MODE_IEEE80211A:
2179 IWL_DEBUG_RATE("Select A mode rate scale\n");
2180 /* If one of the following CCK rates is used,
2181 * have it fall back to the 6M OFDM rate */
14577f23
MA		 2182 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2183 table[i].next_rate_index = iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2184
2185 /* Don't fall back to CCK rates */
14577f23 2186 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2187
2188 /* Don't drop out of OFDM rates */
14577f23
MA		 2189 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2190 iwl_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2191 break;
2192
2193 case MODE_IEEE80211B:
2194 IWL_DEBUG_RATE("Select B mode rate scale\n");
2195 /* If an OFDM rate is used, have it fall back to the
2196 * 1M CCK rates */
14577f23
MA		 2197 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2198 table[i].next_rate_index = iwl_rates[IWL_FIRST_CCK_RATE].table_rs_index;
b481de9c
ZY		 2199
2200 /* CCK shouldn't fall back to OFDM... */
14577f23 2201 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
b481de9c
ZY		 2202 break;
2203
2204 default:
2205 IWL_DEBUG_RATE("Select G mode rate scale\n");
2206 break;
2207 }
2208
2209 /* Update the rate scaling for control frame Tx */
2210 rate_cmd.table_id = 0;
2211 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2212 &rate_cmd);
2213 if (rc)
2214 return rc;
2215
2216 /* Update the rate scaling for data frame Tx */
2217 rate_cmd.table_id = 1;
2218 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2219 &rate_cmd);
2220}
2221
2222int iwl_hw_set_hw_setting(struct iwl_priv *priv)
2223{
2224 memset((void *)&priv->hw_setting, 0,
2225 sizeof(struct iwl_driver_hw_info));
2226
2227 priv->hw_setting.shared_virt =
2228 pci_alloc_consistent(priv->pci_dev,
2229 sizeof(struct iwl_shared),
2230 &priv->hw_setting.shared_phys);
2231
2232 if (!priv->hw_setting.shared_virt) {
2233 IWL_ERROR("failed to allocate pci memory\n");
2234 mutex_unlock(&priv->mutex);
2235 return -ENOMEM;
2236 }
2237
2238 priv->hw_setting.ac_queue_count = AC_NUM;
2239 priv->hw_setting.rx_buffer_size = IWL_RX_BUF_SIZE;
2240 priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd);
2241 priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2242 priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
b481de9c
ZY		 2243 priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2244 priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2245 return 0;
2246}
2247
2248unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
2249 struct iwl_frame *frame, u8 rate)
2250{
2251 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
2252 unsigned int frame_size;
2253
2254 tx_beacon_cmd = (struct iwl_tx_beacon_cmd *)&frame->u;
2255 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2256
2257 tx_beacon_cmd->tx.sta_id = IWL3945_BROADCAST_ID;
2258 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2259
2260 frame_size = iwl_fill_beacon_frame(priv,
2261 tx_beacon_cmd->frame,
2262 BROADCAST_ADDR,
2263 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2264
2265 BUG_ON(frame_size > MAX_MPDU_SIZE);
2266 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2267
2268 tx_beacon_cmd->tx.rate = rate;
2269 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2270 TX_CMD_FLG_TSF_MSK);
2271
14577f23
MA		 2272 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2273 tx_beacon_cmd->tx.supp_rates[0] =
2274 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2275
b481de9c 2276 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2277 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c
ZY		 2278
2279 return (sizeof(struct iwl_tx_beacon_cmd) + frame_size);
2280}
2281
2282void iwl_hw_rx_handler_setup(struct iwl_priv *priv)
2283{
2284 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2285}
2286
2287void iwl_hw_setup_deferred_work(struct iwl_priv *priv)
2288{
2289 INIT_DELAYED_WORK(&priv->thermal_periodic,
2290 iwl3945_bg_reg_txpower_periodic);
2291}
2292
2293void iwl_hw_cancel_deferred_work(struct iwl_priv *priv)
2294{
2295 cancel_delayed_work(&priv->thermal_periodic);
2296}
2297
2298struct pci_device_id iwl_hw_card_ids[] = {
2299 {0x8086, 0x4222, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2300 {0x8086, 0x4227, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
2301 {0}
2302};
2303
91e17473 2304inline int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
b481de9c
ZY		 2305{
2306 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2307 return 0;
2308}
2309
2310MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
Clone of davem's net-next-2.6 tree