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iwlwifi: move 3945 clip groups to 3945 data
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
1f447808 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
d43c36dc 33#include <linux/sched.h>
b481de9c
ZY		 34#include <linux/skbuff.h>
35#include <linux/netdevice.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
b481de9c 38#include <linux/etherdevice.h>
12342c47
ZY		 39#include <asm/unaligned.h>
40#include <net/mac80211.h>
b481de9c 41
dbb6654c 42#include "iwl-fh.h"
bddadf86 43#include "iwl-3945-fh.h"
600c0e11 44#include "iwl-commands.h"
17f841cd 45#include "iwl-sta.h"
b481de9c 46#include "iwl-3945.h"
e6148917 47#include "iwl-eeprom.h"
5747d47f 48#include "iwl-core.h"
4a6547c7 49#include "iwl-helpers.h"
e932a609
JB		 50#include "iwl-led.h"
51#include "iwl-3945-led.h"
b481de9c
ZY		 52
53#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
54 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
55 IWL_RATE_##r##M_IEEE, \
56 IWL_RATE_##ip##M_INDEX, \
57 IWL_RATE_##in##M_INDEX, \
58 IWL_RATE_##rp##M_INDEX, \
59 IWL_RATE_##rn##M_INDEX, \
60 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 61 IWL_RATE_##np##M_INDEX, \
62 IWL_RATE_##r##M_INDEX_TABLE, \
63 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 64
65/*
66 * Parameter order:
67 * rate, prev rate, next rate, prev tgg rate, next tgg rate
68 *
69 * If there isn't a valid next or previous rate then INV is used which
70 * maps to IWL_RATE_INVALID
71 *
72 */
d9829a67 73const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 74 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
75 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
76 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
77 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 78 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
79 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
80 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
81 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
82 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
83 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
84 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
85 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 86};
87
bb8c093b 88/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 89#define IWL_EVT_DISABLE (0)
90#define IWL_EVT_DISABLE_SIZE (1532/32)
91
92/**
bb8c093b 93 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 94 *
95 * Disable an event by writing "1"s into "disable"
96 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
97 * Default values of 0 enable uCode events to be logged.
98 * Use for only special debugging. This function is just a placeholder as-is,
99 * you'll need to provide the special bits! ...
100 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 101void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 102{
b481de9c
ZY		 103 int i;
104 u32 base; /* SRAM address of event log header */
105 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
106 u32 array_size; /* # of u32 entries in array */
107 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
108 0x00000000, /* 31 - 0 Event id numbers */
109 0x00000000, /* 63 - 32 */
110 0x00000000, /* 95 - 64 */
111 0x00000000, /* 127 - 96 */
112 0x00000000, /* 159 - 128 */
113 0x00000000, /* 191 - 160 */
114 0x00000000, /* 223 - 192 */
115 0x00000000, /* 255 - 224 */
116 0x00000000, /* 287 - 256 */
117 0x00000000, /* 319 - 288 */
118 0x00000000, /* 351 - 320 */
119 0x00000000, /* 383 - 352 */
120 0x00000000, /* 415 - 384 */
121 0x00000000, /* 447 - 416 */
122 0x00000000, /* 479 - 448 */
123 0x00000000, /* 511 - 480 */
124 0x00000000, /* 543 - 512 */
125 0x00000000, /* 575 - 544 */
126 0x00000000, /* 607 - 576 */
127 0x00000000, /* 639 - 608 */
128 0x00000000, /* 671 - 640 */
129 0x00000000, /* 703 - 672 */
130 0x00000000, /* 735 - 704 */
131 0x00000000, /* 767 - 736 */
132 0x00000000, /* 799 - 768 */
133 0x00000000, /* 831 - 800 */
134 0x00000000, /* 863 - 832 */
135 0x00000000, /* 895 - 864 */
136 0x00000000, /* 927 - 896 */
137 0x00000000, /* 959 - 928 */
138 0x00000000, /* 991 - 960 */
139 0x00000000, /* 1023 - 992 */
140 0x00000000, /* 1055 - 1024 */
141 0x00000000, /* 1087 - 1056 */
142 0x00000000, /* 1119 - 1088 */
143 0x00000000, /* 1151 - 1120 */
144 0x00000000, /* 1183 - 1152 */
145 0x00000000, /* 1215 - 1184 */
146 0x00000000, /* 1247 - 1216 */
147 0x00000000, /* 1279 - 1248 */
148 0x00000000, /* 1311 - 1280 */
149 0x00000000, /* 1343 - 1312 */
150 0x00000000, /* 1375 - 1344 */
151 0x00000000, /* 1407 - 1376 */
152 0x00000000, /* 1439 - 1408 */
153 0x00000000, /* 1471 - 1440 */
154 0x00000000, /* 1503 - 1472 */
155 };
156
157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 158 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 159 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 160 return;
161 }
162
5d49f498
AK		 163 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
164 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 165
166 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 167 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 168 disable_ptr);
b481de9c 169 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 170 iwl_write_targ_mem(priv,
af7cca2a
TW		 171 disable_ptr + (i * sizeof(u32)),
172 evt_disable[i]);
b481de9c 173
b481de9c 174 } else {
e1623446
TW		 175 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
176 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
177 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 178 disable_ptr, array_size);
179 }
180
181}
182
17744ff6
TW		 183static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
184{
185 int idx;
186
187 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
188 if (iwl3945_rates[idx].plcp == plcp)
189 return idx;
190 return -1;
191}
192
d08853a3 193#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 194#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
195
196static const char *iwl3945_get_tx_fail_reason(u32 status)
197{
198 switch (status & TX_STATUS_MSK) {
199 case TX_STATUS_SUCCESS:
200 return "SUCCESS";
201 TX_STATUS_ENTRY(SHORT_LIMIT);
202 TX_STATUS_ENTRY(LONG_LIMIT);
203 TX_STATUS_ENTRY(FIFO_UNDERRUN);
204 TX_STATUS_ENTRY(MGMNT_ABORT);
205 TX_STATUS_ENTRY(NEXT_FRAG);
206 TX_STATUS_ENTRY(LIFE_EXPIRE);
207 TX_STATUS_ENTRY(DEST_PS);
208 TX_STATUS_ENTRY(ABORTED);
209 TX_STATUS_ENTRY(BT_RETRY);
210 TX_STATUS_ENTRY(STA_INVALID);
211 TX_STATUS_ENTRY(FRAG_DROPPED);
212 TX_STATUS_ENTRY(TID_DISABLE);
213 TX_STATUS_ENTRY(FRAME_FLUSHED);
214 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
215 TX_STATUS_ENTRY(TX_LOCKED);
216 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
217 }
218
219 return "UNKNOWN";
220}
221#else
222static inline const char *iwl3945_get_tx_fail_reason(u32 status)
223{
224 return "";
225}
226#endif
227
e6a9854b
JB		 228/*
229 * get ieee prev rate from rate scale table.
230 * for A and B mode we need to overright prev
231 * value
232 */
4a8a4322 233int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 234{
235 int next_rate = iwl3945_get_prev_ieee_rate(rate);
236
237 switch (priv->band) {
238 case IEEE80211_BAND_5GHZ:
239 if (rate == IWL_RATE_12M_INDEX)
240 next_rate = IWL_RATE_9M_INDEX;
241 else if (rate == IWL_RATE_6M_INDEX)
242 next_rate = IWL_RATE_6M_INDEX;
243 break;
7262796a 244 case IEEE80211_BAND_2GHZ:
ee525d13 245 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 246 iwl_is_associated(priv)) {
7262796a
AM		 247 if (rate == IWL_RATE_11M_INDEX)
248 next_rate = IWL_RATE_5M_INDEX;
249 }
e6a9854b 250 break;
7262796a 251
e6a9854b
JB		 252 default:
253 break;
254 }
255
256 return next_rate;
257}
258
91c066f2
TW		 259
260/**
261 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
262 *
263 * When FW advances 'R' index, all entries between old and new 'R' index
264 * need to be reclaimed. As result, some free space forms. If there is
265 * enough free space (> low mark), wake the stack that feeds us.
266 */
4a8a4322 267static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 268 int txq_id, int index)
269{
188cf6c7 270 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 271 struct iwl_queue *q = &txq->q;
dbb6654c 272 struct iwl_tx_info *tx_info;
91c066f2
TW		 273
274 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
275
276 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
277 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
278
279 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 280 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 281 tx_info->skb[0] = NULL;
7aaa1d79 282 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 283 }
284
d20b3c65 285 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 286 (txq_id != IWL_CMD_QUEUE_NUM) &&
287 priv->mac80211_registered)
e4e72fb4 288 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 289}
290
291/**
292 * iwl3945_rx_reply_tx - Handle Tx response
293 */
4a8a4322 294static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 295 struct iwl_rx_mem_buffer *rxb)
91c066f2 296{
2f301227 297 struct iwl_rx_packet *pkt = rxb_addr(rxb);
91c066f2
TW		 298 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
299 int txq_id = SEQ_TO_QUEUE(sequence);
300 int index = SEQ_TO_INDEX(sequence);
188cf6c7 301 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 302 struct ieee80211_tx_info *info;
91c066f2
TW		 303 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
304 u32 status = le32_to_cpu(tx_resp->status);
305 int rate_idx;
74221d07 306 int fail;
91c066f2 307
625a381a 308 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 309 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 310 "is out of range [0-%d] %d %d\n", txq_id,
311 index, txq->q.n_bd, txq->q.write_ptr,
312 txq->q.read_ptr);
313 return;
314 }
315
e039fa4a 316 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 317 ieee80211_tx_info_clear_status(info);
318
319 /* Fill the MRR chain with some info about on-chip retransmissions */
320 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
321 if (info->band == IEEE80211_BAND_5GHZ)
322 rate_idx -= IWL_FIRST_OFDM_RATE;
323
324 fail = tx_resp->failure_frame;
74221d07
AM		 325
326 info->status.rates[0].idx = rate_idx;
327 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 328
91c066f2 329 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 330 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
331 IEEE80211_TX_STAT_ACK : 0;
91c066f2 332
e1623446 333 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 334 txq_id, iwl3945_get_tx_fail_reason(status), status,
335 tx_resp->rate, tx_resp->failure_frame);
336
e1623446 337 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 338 iwl3945_tx_queue_reclaim(priv, txq_id, index);
339
340 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 341 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 342}
343
344
345
b481de9c
ZY		 346/*****************************************************************************
347 *
348 * Intel PRO/Wireless 3945ABG/BG Network Connection
349 *
350 * RX handler implementations
351 *
b481de9c
ZY		 352 *****************************************************************************/
353
396887a2
DH		 354void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
355 struct iwl_rx_mem_buffer *rxb)
b481de9c 356{
2f301227 357 struct iwl_rx_packet *pkt = rxb_addr(rxb);
e1623446 358 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 359 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 360 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 361
ee525d13 362 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics));
b481de9c
ZY		 363}
364
17744ff6
TW		 365/******************************************************************************
366 *
367 * Misc. internal state and helper functions
368 *
369 ******************************************************************************/
d08853a3 370#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 371
372/**
373 * iwl3945_report_frame - dump frame to syslog during debug sessions
374 *
375 * You may hack this function to show different aspects of received frames,
376 * including selective frame dumps.
377 * group100 parameter selects whether to show 1 out of 100 good frames.
378 */
d08853a3 379static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 380 struct iwl_rx_packet *pkt,
17744ff6
TW		 381 struct ieee80211_hdr *header, int group100)
382{
383 u32 to_us;
384 u32 print_summary = 0;
385 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
386 u32 hundred = 0;
387 u32 dataframe = 0;
fd7c8a40 388 __le16 fc;
17744ff6
TW		 389 u16 seq_ctl;
390 u16 channel;
391 u16 phy_flags;
392 u16 length;
393 u16 status;
394 u16 bcn_tmr;
395 u32 tsf_low;
396 u64 tsf;
397 u8 rssi;
398 u8 agc;
399 u16 sig_avg;
400 u16 noise_diff;
401 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
402 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
403 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
404 u8 *data = IWL_RX_DATA(pkt);
405
406 /* MAC header */
fd7c8a40 407 fc = header->frame_control;
17744ff6
TW		 408 seq_ctl = le16_to_cpu(header->seq_ctrl);
409
410 /* metadata */
411 channel = le16_to_cpu(rx_hdr->channel);
412 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
413 length = le16_to_cpu(rx_hdr->len);
414
415 /* end-of-frame status and timestamp */
416 status = le32_to_cpu(rx_end->status);
417 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
418 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
419 tsf = le64_to_cpu(rx_end->timestamp);
420
421 /* signal statistics */
422 rssi = rx_stats->rssi;
423 agc = rx_stats->agc;
424 sig_avg = le16_to_cpu(rx_stats->sig_avg);
425 noise_diff = le16_to_cpu(rx_stats->noise_diff);
426
427 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
428
429 /* if data frame is to us and all is good,
430 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 431 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
432 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 433 dataframe = 1;
434 if (!group100)
435 print_summary = 1; /* print each frame */
436 else if (priv->framecnt_to_us < 100) {
437 priv->framecnt_to_us++;
438 print_summary = 0;
439 } else {
440 priv->framecnt_to_us = 0;
441 print_summary = 1;
442 hundred = 1;
443 }
444 } else {
445 /* print summary for all other frames */
446 print_summary = 1;
447 }
448
449 if (print_summary) {
450 char *title;
0ff1cca0 451 int rate;
17744ff6
TW		 452
453 if (hundred)
454 title = "100Frames";
fd7c8a40 455 else if (ieee80211_has_retry(fc))
17744ff6 456 title = "Retry";
fd7c8a40 457 else if (ieee80211_is_assoc_resp(fc))
17744ff6 458 title = "AscRsp";
fd7c8a40 459 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 460 title = "RasRsp";
fd7c8a40 461 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 462 title = "PrbRsp";
463 print_dump = 1; /* dump frame contents */
464 } else if (ieee80211_is_beacon(fc)) {
465 title = "Beacon";
466 print_dump = 1; /* dump frame contents */
467 } else if (ieee80211_is_atim(fc))
468 title = "ATIM";
469 else if (ieee80211_is_auth(fc))
470 title = "Auth";
471 else if (ieee80211_is_deauth(fc))
472 title = "DeAuth";
473 else if (ieee80211_is_disassoc(fc))
474 title = "DisAssoc";
475 else
476 title = "Frame";
477
478 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
479 if (rate == -1)
480 rate = 0;
481 else
482 rate = iwl3945_rates[rate].ieee / 2;
483
484 /* print frame summary.
485 * MAC addresses show just the last byte (for brevity),
486 * but you can hack it to show more, if you'd like to. */
487 if (dataframe)
e1623446 488 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 489 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 490 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 491 length, rssi, channel, rate);
492 else {
493 /* src/dst addresses assume managed mode */
e1623446 494 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 495 "src=0x%02x, rssi=%u, tim=%lu usec, "
496 "phy=0x%02x, chnl=%d\n",
fd7c8a40 497 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 498 header->addr3[5], rssi,
499 tsf_low - priv->scan_start_tsf,
500 phy_flags, channel);
501 }
502 }
503 if (print_dump)
3d816c77 504 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 505}
d08853a3
SO		 506
507static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
508 struct iwl_rx_packet *pkt,
509 struct ieee80211_hdr *header, int group100)
510{
3d816c77 511 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 512 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
513}
514
17744ff6 515#else
4a8a4322 516static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 517 struct iwl_rx_packet *pkt,
17744ff6
TW		 518 struct ieee80211_hdr *header, int group100)
519{
520}
521#endif
522
4bd9b4f3 523/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 524static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 525 struct ieee80211_hdr *header)
526{
527 /* Filter incoming packets to determine if they are targeted toward
528 * this network, discarding packets coming from ourselves */
529 switch (priv->iw_mode) {
05c914fe 530 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 531 /* packets to our IBSS update information */
532 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 533 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 534 /* packets to our IBSS update information */
535 return !compare_ether_addr(header->addr2, priv->bssid);
536 default:
537 return 1;
538 }
539}
17744ff6 540
4a8a4322 541static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 542 struct iwl_rx_mem_buffer *rxb,
12342c47 543 struct ieee80211_rx_status *stats)
b481de9c 544{
2f301227 545 struct iwl_rx_packet *pkt = rxb_addr(rxb);
4bd9b4f3 546 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 547 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
548 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
2f301227
ZY		 549 u16 len = le16_to_cpu(rx_hdr->len);
550 struct sk_buff *skb;
551 int ret;
29b1b268 552 __le16 fc = hdr->frame_control;
b481de9c
ZY		 553
554 /* We received data from the HW, so stop the watchdog */
2f301227
ZY		 555 if (unlikely(len + IWL39_RX_FRAME_SIZE >
556 PAGE_SIZE << priv->hw_params.rx_page_order)) {
e1623446 557 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 558 return;
559 }
560
561 /* We only process data packets if the interface is open */
562 if (unlikely(!priv->is_open)) {
e1623446
TW		 563 IWL_DEBUG_DROP_LIMIT(priv,
564 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 565 return;
566 }
b481de9c 567
a3b6bd5b 568 skb = alloc_skb(IWL_LINK_HDR_MAX * 2, GFP_ATOMIC);
2f301227
ZY		 569 if (!skb) {
570 IWL_ERR(priv, "alloc_skb failed\n");
571 return;
572 }
b481de9c 573
9c74d9fb 574 if (!iwl3945_mod_params.sw_crypto)
8ccde88a 575 iwl_set_decrypted_flag(priv,
2f301227 576 (struct ieee80211_hdr *)rxb_addr(rxb),
b481de9c
ZY		 577 le32_to_cpu(rx_end->status), stats);
578
a3b6bd5b 579 skb_reserve(skb, IWL_LINK_HDR_MAX);
2f301227
ZY		 580 skb_add_rx_frag(skb, 0, rxb->page,
581 (void *)rx_hdr->payload - (void *)pkt, len);
582
583 /* mac80211 currently doesn't support paged SKB. Convert it to
584 * linear SKB for management frame and data frame requires
585 * software decryption or software defragementation. */
29b1b268
ZY		 586 if (ieee80211_is_mgmt(fc) ||
587 ieee80211_has_protected(fc) ||
588 ieee80211_has_morefrags(fc) ||
2f301227
ZY		 589 le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)
590 ret = skb_linearize(skb);
591 else
592 ret = __pskb_pull_tail(skb, min_t(u16, IWL_LINK_HDR_MAX, len)) ?
593 0 : -ENOMEM;
594
595 if (ret) {
596 kfree_skb(skb);
597 goto out;
598 }
599
29b1b268
ZY		 600 /*
601 * XXX: We cannot touch the page and its virtual memory (pkt) after
602 * here. It might have already been freed by the above skb change.
603 */
22fdf3c9 604
29b1b268 605 iwl_update_stats(priv, false, fc, len);
2f301227 606 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
2f301227 607
29b1b268 608 ieee80211_rx(priv->hw, skb);
2f301227
ZY		 609 out:
610 priv->alloc_rxb_page--;
611 rxb->page = NULL;
b481de9c
ZY		 612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
2f301227 621 struct iwl_rx_packet *pkt = rxb_addr(rxb);
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
9024adf5 641 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c 648 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 649 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
650 rx_stats->phy_count);
b481de9c
ZY		 651 return;
652 }
653
654 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
655 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 656 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 657 return;
658 }
659
56decd3c 660
b481de9c
ZY		 661
662 /* Convert 3945's rssi indicator to dBm */
250bdd21 663 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 664
665 /* Set default noise value to -127 */
666 if (priv->last_rx_noise == 0)
667 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
668
669 /* 3945 provides noise info for OFDM frames only.
670 * sig_avg and noise_diff are measured by the 3945's digital signal
671 * processor (DSP), and indicate linear levels of signal level and
672 * distortion/noise within the packet preamble after
673 * automatic gain control (AGC). sig_avg should stay fairly
674 * constant if the radio's AGC is working well.
675 * Since these values are linear (not dB or dBm), linear
676 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
677 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
678 * to obtain noise level in dBm.
17744ff6 679 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 680 if (rx_stats_noise_diff) {
681 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 682 rx_status.noise = rx_status.signal -
17744ff6 683 iwl3945_calc_db_from_ratio(snr);
b481de9c 684 } else {
17744ff6 685 rx_status.noise = priv->last_rx_noise;
b481de9c
ZY		 686 }
687
688
671adc93
JB		 689 IWL_DEBUG_STATS(priv, "Rssi %d noise %d sig_avg %d noise_diff %d\n",
690 rx_status.signal, rx_status.noise,
b481de9c
ZY		 691 rx_stats_sig_avg, rx_stats_noise_diff);
692
b481de9c
ZY		 693 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
694
bb8c093b 695 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 696
e1623446 697 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 698 network_packet ? '*' : ' ',
699 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 700 rx_status.signal, rx_status.signal,
701 rx_status.noise, rx_status.rate_idx);
b481de9c 702
d08853a3
SO		 703 /* Set "1" to report good data frames in groups of 100 */
704 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 705 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 706
707 if (network_packet) {
e99f168c
JB		 708 priv->_3945.last_beacon_time =
709 le32_to_cpu(rx_end->beacon_timestamp);
710 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp);
711 priv->_3945.last_rx_rssi = rx_status.signal;
17744ff6 712 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 713 }
714
12e5e22d 715 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 716}
717
7aaa1d79
SO		 718int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
719 struct iwl_tx_queue *txq,
720 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 721{
722 int count;
7aaa1d79 723 struct iwl_queue *q;
59606ffa 724 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 725
726 q = &txq->q;
59606ffa
SO		 727 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
728 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 729
730 if (reset)
731 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 734
735 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 736 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 737 NUM_TFD_CHUNKS);
738 return -EINVAL;
739 }
740
dbb6654c
WT		 741 tfd->tbs[count].addr = cpu_to_le32(addr);
742 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 743
744 count++;
745
746 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
747 TFD_CTL_PAD_SET(pad));
748
749 return 0;
750}
751
752/**
bb8c093b 753 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 754 *
755 * Does NOT advance any indexes
756 */
7aaa1d79 757void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 758{
59606ffa 759 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 760 int index = txq->q.read_ptr;
761 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
b481de9c 766 /* sanity check */
dbb6654c 767 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 768 if (counter > NUM_TFD_CHUNKS) {
15b1687c 769 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 770 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 771 return;
b481de9c
ZY		 772 }
773
fd9377ee
RC		 774 /* Unmap tx_cmd */
775 if (counter)
776 pci_unmap_single(dev,
c2acea8e
JB		 777 pci_unmap_addr(&txq->meta[index], mapping),
778 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 779 PCI_DMA_TODEVICE);
780
b481de9c
ZY		 781 /* unmap chunks if any */
782
783 for (i = 1; i < counter; i++) {
dbb6654c
WT		 784 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
785 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 786 if (txq->txb[txq->q.read_ptr].skb[0]) {
787 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
788 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 789 /* Can be called from interrupt context */
790 dev_kfree_skb_any(skb);
fc4b6853 791 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 792 }
793 }
794 }
7aaa1d79 795 return ;
b481de9c
ZY		 796}
797
b481de9c 798/**
bb8c093b 799 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 800 *
801*/
c2acea8e
JB		 802void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
803 struct iwl_device_cmd *cmd,
804 struct ieee80211_tx_info *info,
805 struct ieee80211_hdr *hdr,
806 int sta_id, int tx_id)
b481de9c 807{
e039fa4a 808 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 809 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 810 u16 rate_mask;
811 int rate;
812 u8 rts_retry_limit;
813 u8 data_retry_limit;
814 __le32 tx_flags;
fd7c8a40 815 __le16 fc = hdr->frame_control;
9744c91f 816 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 817
bb8c093b 818 rate = iwl3945_rates[rate_index].plcp;
9744c91f 819 tx_flags = tx_cmd->tx_flags;
b481de9c
ZY		 820
821 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 822 * in this running context */
b481de9c
ZY		 823 rate_mask = IWL_RATES_MASK;
824
768db982
AK		 825
826 /* Set retry limit on DATA packets and Probe Responses*/
827 if (ieee80211_is_probe_resp(fc))
828 data_retry_limit = 3;
829 else
830 data_retry_limit = IWL_DEFAULT_TX_RETRY;
831 tx_cmd->data_retry_limit = data_retry_limit;
832
b481de9c
ZY		 833 if (tx_id >= IWL_CMD_QUEUE_NUM)
834 rts_retry_limit = 3;
835 else
836 rts_retry_limit = 7;
837
768db982
AK		 838 if (data_retry_limit < rts_retry_limit)
839 rts_retry_limit = data_retry_limit;
840 tx_cmd->rts_retry_limit = rts_retry_limit;
b481de9c 841
fd7c8a40
HH		 842 if (ieee80211_is_mgmt(fc)) {
843 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
844 case cpu_to_le16(IEEE80211_STYPE_AUTH):
845 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
846 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
847 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 848 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
849 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
850 tx_flags |= TX_CMD_FLG_CTS_MSK;
851 }
852 break;
853 default:
854 break;
855 }
856 }
857
9744c91f
AK		 858 tx_cmd->rate = rate;
859 tx_cmd->tx_flags = tx_flags;
b481de9c
ZY		 860
861 /* OFDM */
9744c91f 862 tx_cmd->supp_rates[0] =
14577f23 863 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 864
865 /* CCK */
9744c91f 866 tx_cmd->supp_rates[1] = (rate_mask & 0xF);
b481de9c 867
e1623446 868 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 869 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
9744c91f
AK		 870 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags),
871 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]);
b481de9c
ZY		 872}
873
4a8a4322 874u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 875{
876 unsigned long flags_spin;
c587de0b 877 struct iwl_station_entry *station;
b481de9c
ZY		 878
879 if (sta_id == IWL_INVALID_STATION)
880 return IWL_INVALID_STATION;
881
882 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 883 station = &priv->stations[sta_id];
b481de9c
ZY		 884
885 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
886 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 887 station->sta.mode = STA_CONTROL_MODIFY_MSK;
888
889 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
890
c587de0b 891 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 892 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 893 sta_id, tx_rate);
894 return sta_id;
895}
896
854682ed 897static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 898{
854682ed 899 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 900 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 901 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 902 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
903 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 904
5d49f498 905 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 906 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
907 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 908 }
b481de9c 909 } else {
5d49f498 910 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 911 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
912 ~APMG_PS_CTRL_MSK_PWR_SRC);
913
5d49f498 914 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 915 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
916 }
b481de9c 917
a8b50a0a 918 return 0;
b481de9c
ZY		 919}
920
4a8a4322 921static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 922{
5d49f498 923 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 924 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 925 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
926 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 927 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
928 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
929 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
930 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
931 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
932 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
933 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
934 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 935
936 /* fake read to flush all prev I/O */
5d49f498 937 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 938
b481de9c
ZY		 939 return 0;
940}
941
4a8a4322 942static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 943{
b481de9c
ZY		 944
945 /* bypass mode */
5d49f498 946 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 947
948 /* RA 0 is active */
5d49f498 949 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 950
951 /* all 6 fifo are active */
5d49f498 952 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 953
5d49f498
AK		 954 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
955 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
956 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
957 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 958
5d49f498 959 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
ee525d13 960 priv->_3945.shared_phys);
b481de9c 961
5d49f498 962 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 963 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
964 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
965 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
966 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
967 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
968 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
969 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 970
b481de9c
ZY		 971
972 return 0;
973}
974
975/**
976 * iwl3945_txq_ctx_reset - Reset TX queue context
977 *
978 * Destroys all DMA structures and initialize them again
979 */
4a8a4322 980static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 981{
982 int rc;
983 int txq_id, slots_num;
984
bb8c093b 985 iwl3945_hw_txq_ctx_free(priv);
b481de9c 986
88804e2b
WYG		 987 /* allocate tx queue structure */
988 rc = iwl_alloc_txq_mem(priv);
989 if (rc)
990 return rc;
991
b481de9c
ZY		 992 /* Tx CMD queue */
993 rc = iwl3945_tx_reset(priv);
994 if (rc)
995 goto error;
996
997 /* Tx queue(s) */
5905a1aa 998 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 999 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1000 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 1001 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1002 txq_id);
b481de9c 1003 if (rc) {
15b1687c 1004 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1005 goto error;
1006 }
1007 }
1008
1009 return rc;
1010
1011 error:
bb8c093b 1012 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1013 return rc;
1014}
1015
fadb3582 1016
f33269b8 1017/*
fadb3582
BC		 1018 * Start up 3945's basic functionality after it has been reset
1019 * (e.g. after platform boot, or shutdown via iwl_apm_stop())
f33269b8
BC		 1020 * NOTE: This does not load uCode nor start the embedded processor
1021 */
01ec616d 1022static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1023{
fadb3582 1024 int ret = iwl_apm_init(priv);
01ec616d 1025
f33269b8
BC		 1026 /* Clear APMG (NIC's internal power management) interrupts */
1027 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1028 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1029
1030 /* Reset radio chip */
1031 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1032 udelay(5);
1033 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1034
01ec616d
KA		 1035 return ret;
1036}
b481de9c 1037
01ec616d
KA		 1038static void iwl3945_nic_config(struct iwl_priv *priv)
1039{
e6148917 1040 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1041 unsigned long flags;
1042 u8 rev_id = 0;
b481de9c 1043
b481de9c
ZY		 1044 spin_lock_irqsave(&priv->lock, flags);
1045
43121432
AK		 1046 /* Determine HW type */
1047 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1048
1049 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1050
b481de9c 1051 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1052 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1053 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1054 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1055 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1056 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1057 } else {
e1623446 1058 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1059 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1060 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1061 }
1062
e6148917 1063 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1064 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1065 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1066 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1067 } else
e1623446 1068 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1069
e6148917 1070 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1071 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1072 eeprom->board_revision);
5d49f498 1073 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1074 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1075 } else {
e1623446 1076 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1077 eeprom->board_revision);
5d49f498 1078 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1079 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1080 }
1081
e6148917 1082 if (eeprom->almgor_m_version <= 1) {
5d49f498 1083 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1084 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1085 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1086 eeprom->almgor_m_version);
b481de9c 1087 } else {
e1623446 1088 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1089 eeprom->almgor_m_version);
5d49f498 1090 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1091 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1092 }
1093 spin_unlock_irqrestore(&priv->lock, flags);
1094
e6148917 1095 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1096 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1097
e6148917 1098 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1099 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1100}
1101
1102int iwl3945_hw_nic_init(struct iwl_priv *priv)
1103{
01ec616d
KA		 1104 int rc;
1105 unsigned long flags;
1106 struct iwl_rx_queue *rxq = &priv->rxq;
1107
1108 spin_lock_irqsave(&priv->lock, flags);
1109 priv->cfg->ops->lib->apm_ops.init(priv);
1110 spin_unlock_irqrestore(&priv->lock, flags);
1111
854682ed 1112 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1113 if (rc)
854682ed
KA		 1114 return rc;
1115
01ec616d 1116 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1117
1118 /* Allocate the RX queue, or reset if it is already allocated */
1119 if (!rxq->bd) {
51af3d3f 1120 rc = iwl_rx_queue_alloc(priv);
b481de9c 1121 if (rc) {
15b1687c 1122 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1123 return -ENOMEM;
1124 }
1125 } else
df833b1d 1126 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1127
bb8c093b 1128 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1129
1130 iwl3945_rx_init(priv, rxq);
1131
b481de9c
ZY		 1132
1133 /* Look at using this instead:
1134 rxq->need_update = 1;
141c43a3 1135 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1136 */
1137
5d49f498 1138 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1139
1140 rc = iwl3945_txq_ctx_reset(priv);
1141 if (rc)
1142 return rc;
1143
1144 set_bit(STATUS_INIT, &priv->status);
1145
1146 return 0;
1147}
1148
1149/**
bb8c093b 1150 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1151 *
1152 * Destroy all TX DMA queues and structures
1153 */
4a8a4322 1154void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1155{
1156 int txq_id;
1157
1158 /* Tx queues */
88804e2b
WYG		 1159 if (priv->txq)
1160 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1161 txq_id++)
1162 if (txq_id == IWL_CMD_QUEUE_NUM)
1163 iwl_cmd_queue_free(priv);
1164 else
1165 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1166
88804e2b
WYG		 1167 /* free tx queue structure */
1168 iwl_free_txq_mem(priv);
b481de9c
ZY		 1169}
1170
4a8a4322 1171void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1172{
bddadf86 1173 int txq_id;
b481de9c
ZY		 1174
1175 /* stop SCD */
5d49f498 1176 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1f80989e 1177 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0);
b481de9c
ZY		 1178
1179 /* reset TFD queues */
5905a1aa 1180 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1181 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1182 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1183 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1184 1000);
1185 }
1186
bb8c093b 1187 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1188}
1189
b481de9c 1190/**
bb8c093b 1191 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1192 * return index delta into power gain settings table
1193*/
bb8c093b 1194static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1195{
1196 return (new_reading - old_reading) * (-11) / 100;
1197}
1198
1199/**
bb8c093b 1200 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1201 */
bb8c093b 1202static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1203{
3ac7f146 1204 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1205}
1206
4a8a4322 1207int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1208{
5d49f498 1209 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1210}
1211
1212/**
bb8c093b 1213 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1214 * get the current temperature by reading from NIC
1215*/
4a8a4322 1216static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1217{
e6148917 1218 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1219 int temperature;
1220
bb8c093b 1221 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1222
1223 /* driver's okay range is -260 to +25.
1224 * human readable okay range is 0 to +285 */
e1623446 1225 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1226
1227 /* handle insane temp reading */
bb8c093b 1228 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1229 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1230
1231 /* if really really hot(?),
1232 * substitute the 3rd band/group's temp measured at factory */
1233 if (priv->last_temperature > 100)
e6148917 1234 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1235 else /* else use most recent "sane" value from driver */
1236 temperature = priv->last_temperature;
1237 }
1238
1239 return temperature; /* raw, not "human readable" */
1240}
1241
1242/* Adjust Txpower only if temperature variance is greater than threshold.
1243 *
1244 * Both are lower than older versions' 9 degrees */
1245#define IWL_TEMPERATURE_LIMIT_TIMER 6
1246
1247/**
1248 * is_temp_calib_needed - determines if new calibration is needed
1249 *
1250 * records new temperature in tx_mgr->temperature.
1251 * replaces tx_mgr->last_temperature *only* if calib needed
1252 * (assumes caller will actually do the calibration!). */
4a8a4322 1253static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1254{
1255 int temp_diff;
1256
bb8c093b 1257 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1258 temp_diff = priv->temperature - priv->last_temperature;
1259
1260 /* get absolute value */
1261 if (temp_diff < 0) {
e1623446 1262 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1263 temp_diff = -temp_diff;
1264 } else if (temp_diff == 0)
e1623446 1265 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1266 else
e1623446 1267 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1268
1269 /* if we don't need calibration, *don't* update last_temperature */
1270 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1271 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1272 return 0;
1273 }
1274
e1623446 1275 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1276
1277 /* assume that caller will actually do calib ...
1278 * update the "last temperature" value */
1279 priv->last_temperature = priv->temperature;
1280 return 1;
1281}
1282
1283#define IWL_MAX_GAIN_ENTRIES 78
1284#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1285#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1286
1287/* radio and DSP power table, each step is 1/2 dB.
1288 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1289static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1290 {
1291 {251, 127}, /* 2.4 GHz, highest power */
1292 {251, 127},
1293 {251, 127},
1294 {251, 127},
1295 {251, 125},
1296 {251, 110},
1297 {251, 105},
1298 {251, 98},
1299 {187, 125},
1300 {187, 115},
1301 {187, 108},
1302 {187, 99},
1303 {243, 119},
1304 {243, 111},
1305 {243, 105},
1306 {243, 97},
1307 {243, 92},
1308 {211, 106},
1309 {211, 100},
1310 {179, 120},
1311 {179, 113},
1312 {179, 107},
1313 {147, 125},
1314 {147, 119},
1315 {147, 112},
1316 {147, 106},
1317 {147, 101},
1318 {147, 97},
1319 {147, 91},
1320 {115, 107},
1321 {235, 121},
1322 {235, 115},
1323 {235, 109},
1324 {203, 127},
1325 {203, 121},
1326 {203, 115},
1327 {203, 108},
1328 {203, 102},
1329 {203, 96},
1330 {203, 92},
1331 {171, 110},
1332 {171, 104},
1333 {171, 98},
1334 {139, 116},
1335 {227, 125},
1336 {227, 119},
1337 {227, 113},
1338 {227, 107},
1339 {227, 101},
1340 {227, 96},
1341 {195, 113},
1342 {195, 106},
1343 {195, 102},
1344 {195, 95},
1345 {163, 113},
1346 {163, 106},
1347 {163, 102},
1348 {163, 95},
1349 {131, 113},
1350 {131, 106},
1351 {131, 102},
1352 {131, 95},
1353 {99, 113},
1354 {99, 106},
1355 {99, 102},
1356 {99, 95},
1357 {67, 113},
1358 {67, 106},
1359 {67, 102},
1360 {67, 95},
1361 {35, 113},
1362 {35, 106},
1363 {35, 102},
1364 {35, 95},
1365 {3, 113},
1366 {3, 106},
1367 {3, 102},
1368 {3, 95} }, /* 2.4 GHz, lowest power */
1369 {
1370 {251, 127}, /* 5.x GHz, highest power */
1371 {251, 120},
1372 {251, 114},
1373 {219, 119},
1374 {219, 101},
1375 {187, 113},
1376 {187, 102},
1377 {155, 114},
1378 {155, 103},
1379 {123, 117},
1380 {123, 107},
1381 {123, 99},
1382 {123, 92},
1383 {91, 108},
1384 {59, 125},
1385 {59, 118},
1386 {59, 109},
1387 {59, 102},
1388 {59, 96},
1389 {59, 90},
1390 {27, 104},
1391 {27, 98},
1392 {27, 92},
1393 {115, 118},
1394 {115, 111},
1395 {115, 104},
1396 {83, 126},
1397 {83, 121},
1398 {83, 113},
1399 {83, 105},
1400 {83, 99},
1401 {51, 118},
1402 {51, 111},
1403 {51, 104},
1404 {51, 98},
1405 {19, 116},
1406 {19, 109},
1407 {19, 102},
1408 {19, 98},
1409 {19, 93},
1410 {171, 113},
1411 {171, 107},
1412 {171, 99},
1413 {139, 120},
1414 {139, 113},
1415 {139, 107},
1416 {139, 99},
1417 {107, 120},
1418 {107, 113},
1419 {107, 107},
1420 {107, 99},
1421 {75, 120},
1422 {75, 113},
1423 {75, 107},
1424 {75, 99},
1425 {43, 120},
1426 {43, 113},
1427 {43, 107},
1428 {43, 99},
1429 {11, 120},
1430 {11, 113},
1431 {11, 107},
1432 {11, 99},
1433 {131, 107},
1434 {131, 99},
1435 {99, 120},
1436 {99, 113},
1437 {99, 107},
1438 {99, 99},
1439 {67, 120},
1440 {67, 113},
1441 {67, 107},
1442 {67, 99},
1443 {35, 120},
1444 {35, 113},
1445 {35, 107},
1446 {35, 99},
1447 {3, 120} } /* 5.x GHz, lowest power */
1448};
1449
bb8c093b 1450static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1451{
1452 if (index < 0)
1453 return 0;
1454 if (index >= IWL_MAX_GAIN_ENTRIES)
1455 return IWL_MAX_GAIN_ENTRIES - 1;
1456 return (u8) index;
1457}
1458
1459/* Kick off thermal recalibration check every 60 seconds */
1460#define REG_RECALIB_PERIOD (60)
1461
1462/**
bb8c093b 1463 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1464 *
1465 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1466 * or 6 Mbit (OFDM) rates.
1467 */
4a8a4322 1468static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1469 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1470 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1471 int band_index)
1472{
bb8c093b 1473 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1474 s8 power;
1475 u8 power_index;
1476
1477 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1478
1479 /* use this channel group's 6Mbit clipping/saturation pwr,
1480 * but cap at regulatory scan power restriction (set during init
1481 * based on eeprom channel data) for this channel. */
14577f23 1482 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1483
1484 /* further limit to user's max power preference.
1485 * FIXME: Other spectrum management power limitations do not
1486 * seem to apply?? */
62ea9c5b 1487 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1488 scan_power_info->requested_power = power;
1489
1490 /* find difference between new scan *power* and current "normal"
1491 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1492 * current "normal" temperature-compensated Tx power *index* for
1493 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1494 * *index*. */
1495 power_index = ch_info->power_info[rate_index].power_table_index
1496 - (power - ch_info->power_info
14577f23 1497 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1498
1499 /* store reference index that we use when adjusting *all* scan
1500 * powers. So we can accommodate user (all channel) or spectrum
1501 * management (single channel) power changes "between" temperature
1502 * feedback compensation procedures.
1503 * don't force fit this reference index into gain table; it may be a
1504 * negative number. This will help avoid errors when we're at
1505 * the lower bounds (highest gains, for warmest temperatures)
1506 * of the table. */
1507
1508 /* don't exceed table bounds for "real" setting */
bb8c093b 1509 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1510
1511 scan_power_info->power_table_index = power_index;
1512 scan_power_info->tpc.tx_gain =
1513 power_gain_table[band_index][power_index].tx_gain;
1514 scan_power_info->tpc.dsp_atten =
1515 power_gain_table[band_index][power_index].dsp_atten;
1516}
1517
1518/**
75bcfae9 1519 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1520 *
1521 * Configures power settings for all rates for the current channel,
1522 * using values from channel info struct, and send to NIC
1523 */
dfb39e82 1524static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1525{
14577f23 1526 int rate_idx, i;
d20b3c65 1527 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1528 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1529 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1530 };
1531
8318d78a 1532 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1533 ch_info = iwl_get_channel_info(priv,
8318d78a 1534 priv->band,
8ccde88a 1535 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1536 if (!ch_info) {
15b1687c
WT		 1537 IWL_ERR(priv,
1538 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1539 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1540 return -EINVAL;
1541 }
1542
1543 if (!is_channel_valid(ch_info)) {
e1623446 1544 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1545 "non-Tx channel.\n");
1546 return 0;
1547 }
1548
1549 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1550 /* Fill OFDM rate */
1551 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1552 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1553
1554 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1555 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1556
e1623446 1557 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1558 le16_to_cpu(txpower.channel),
1559 txpower.band,
14577f23
MA		 1560 txpower.power[i].tpc.tx_gain,
1561 txpower.power[i].tpc.dsp_atten,
1562 txpower.power[i].rate);
1563 }
1564 /* Fill CCK rates */
1565 for (rate_idx = IWL_FIRST_CCK_RATE;
1566 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1567 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1568 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1569
e1623446 1570 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1571 le16_to_cpu(txpower.channel),
1572 txpower.band,
1573 txpower.power[i].tpc.tx_gain,
1574 txpower.power[i].tpc.dsp_atten,
1575 txpower.power[i].rate);
b481de9c
ZY		 1576 }
1577
518099a8
SO		 1578 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1579 sizeof(struct iwl3945_txpowertable_cmd),
1580 &txpower);
b481de9c
ZY		 1581
1582}
1583
1584/**
bb8c093b 1585 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1586 * @ch_info: Channel to update. Uses power_info.requested_power.
1587 *
1588 * Replace requested_power and base_power_index ch_info fields for
1589 * one channel.
1590 *
1591 * Called if user or spectrum management changes power preferences.
1592 * Takes into account h/w and modulation limitations (clip power).
1593 *
1594 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1595 *
1596 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1597 * properly fill out the scan powers, and actual h/w gain settings,
1598 * and send changes to NIC
1599 */
4a8a4322 1600static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1601 struct iwl_channel_info *ch_info)
b481de9c 1602{
bb8c093b 1603 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1604 int power_changed = 0;
1605 int i;
1606 const s8 *clip_pwrs;
1607 int power;
1608
1609 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1610 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1611
1612 /* Get this channel's rate-to-current-power settings table */
1613 power_info = ch_info->power_info;
1614
1615 /* update OFDM Txpower settings */
14577f23 1616 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1617 i++, ++power_info) {
1618 int delta_idx;
1619
1620 /* limit new power to be no more than h/w capability */
1621 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1622 if (power == power_info->requested_power)
1623 continue;
1624
1625 /* find difference between old and new requested powers,
1626 * update base (non-temp-compensated) power index */
1627 delta_idx = (power - power_info->requested_power) * 2;
1628 power_info->base_power_index -= delta_idx;
1629
1630 /* save new requested power value */
1631 power_info->requested_power = power;
1632
1633 power_changed = 1;
1634 }
1635
1636 /* update CCK Txpower settings, based on OFDM 12M setting ...
1637 * ... all CCK power settings for a given channel are the *same*. */
1638 if (power_changed) {
1639 power =
14577f23 1640 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1641 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1642
bb8c093b 1643 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1644 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1645 power_info->requested_power = power;
1646 power_info->base_power_index =
14577f23 1647 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1648 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1649 ++power_info;
1650 }
1651 }
1652
1653 return 0;
1654}
1655
1656/**
bb8c093b 1657 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1658 *
1659 * NOTE: Returned power limit may be less (but not more) than requested,
1660 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1661 * (no consideration for h/w clipping limitations).
1662 */
d20b3c65 1663static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1664{
1665 s8 max_power;
1666
1667#if 0
1668 /* if we're using TGd limits, use lower of TGd or EEPROM */
1669 if (ch_info->tgd_data.max_power != 0)
1670 max_power = min(ch_info->tgd_data.max_power,
1671 ch_info->eeprom.max_power_avg);
1672
1673 /* else just use EEPROM limits */
1674 else
1675#endif
1676 max_power = ch_info->eeprom.max_power_avg;
1677
1678 return min(max_power, ch_info->max_power_avg);
1679}
1680
1681/**
bb8c093b 1682 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1683 *
1684 * Compensate txpower settings of *all* channels for temperature.
1685 * This only accounts for the difference between current temperature
1686 * and the factory calibration temperatures, and bases the new settings
1687 * on the channel's base_power_index.
1688 *
1689 * If RxOn is "associated", this sends the new Txpower to NIC!
1690 */
4a8a4322 1691static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1692{
d20b3c65 1693 struct iwl_channel_info *ch_info = NULL;
e6148917 1694 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1695 int delta_index;
1696 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1697 u8 a_band;
1698 u8 rate_index;
1699 u8 scan_tbl_index;
1700 u8 i;
1701 int ref_temp;
1702 int temperature = priv->temperature;
1703
1704 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1705 for (i = 0; i < priv->channel_count; i++) {
1706 ch_info = &priv->channel_info[i];
1707 a_band = is_channel_a_band(ch_info);
1708
1709 /* Get this chnlgrp's factory calibration temperature */
e6148917 1710 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1711 temperature;
1712
a96a27f9 1713 /* get power index adjustment based on current and factory
b481de9c 1714 * temps */
bb8c093b 1715 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1716 ref_temp);
1717
1718 /* set tx power value for all rates, OFDM and CCK */
1719 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1720 rate_index++) {
1721 int power_idx =
1722 ch_info->power_info[rate_index].base_power_index;
1723
1724 /* temperature compensate */
1725 power_idx += delta_index;
1726
1727 /* stay within table range */
bb8c093b 1728 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1729 ch_info->power_info[rate_index].
1730 power_table_index = (u8) power_idx;
1731 ch_info->power_info[rate_index].tpc =
1732 power_gain_table[a_band][power_idx];
1733 }
1734
1735 /* Get this chnlgrp's rate-to-max/clip-powers table */
67d613ae 1736 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1737
1738 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1739 for (scan_tbl_index = 0;
1740 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1741 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1742 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1743 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1744 actual_index, clip_pwrs,
1745 ch_info, a_band);
1746 }
1747 }
1748
1749 /* send Txpower command for current channel to ucode */
75bcfae9 1750 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1751}
1752
4a8a4322 1753int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1754{
d20b3c65 1755 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1756 s8 max_power;
1757 u8 a_band;
1758 u8 i;
1759
62ea9c5b 1760 if (priv->tx_power_user_lmt == power) {
e1623446 1761 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1762 "limit: %ddBm.\n", power);
1763 return 0;
1764 }
1765
e1623446 1766 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1767 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1768
1769 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1770
1771 for (i = 0; i < priv->channel_count; i++) {
1772 ch_info = &priv->channel_info[i];
1773 a_band = is_channel_a_band(ch_info);
1774
1775 /* find minimum power of all user and regulatory constraints
1776 * (does not consider h/w clipping limitations) */
bb8c093b 1777 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1778 max_power = min(power, max_power);
1779 if (max_power != ch_info->curr_txpow) {
1780 ch_info->curr_txpow = max_power;
1781
1782 /* this considers the h/w clipping limitations */
bb8c093b 1783 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1784 }
1785 }
1786
1787 /* update txpower settings for all channels,
1788 * send to NIC if associated. */
1789 is_temp_calib_needed(priv);
bb8c093b 1790 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1791
1792 return 0;
1793}
1794
5bbe233b
AK		 1795static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1796{
1797 int rc = 0;
2f301227 1798 struct iwl_rx_packet *pkt;
5bbe233b
AK		 1799 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1800 struct iwl_host_cmd cmd = {
1801 .id = REPLY_RXON_ASSOC,
1802 .len = sizeof(rxon_assoc),
c2acea8e 1803 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1804 .data = &rxon_assoc,
1805 };
1806 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1807 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1808
1809 if ((rxon1->flags == rxon2->flags) &&
1810 (rxon1->filter_flags == rxon2->filter_flags) &&
1811 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1812 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1813 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1814 return 0;
1815 }
1816
1817 rxon_assoc.flags = priv->staging_rxon.flags;
1818 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1819 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1820 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1821 rxon_assoc.reserved = 0;
1822
1823 rc = iwl_send_cmd_sync(priv, &cmd);
1824 if (rc)
1825 return rc;
1826
2f301227
ZY		 1827 pkt = (struct iwl_rx_packet *)cmd.reply_page;
1828 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) {
5bbe233b
AK		 1829 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1830 rc = -EIO;
1831 }
1832
64a76b50 1833 iwl_free_pages(priv, cmd.reply_page);
5bbe233b
AK		 1834
1835 return rc;
1836}
1837
e0158e61
AK		 1838/**
1839 * iwl3945_commit_rxon - commit staging_rxon to hardware
1840 *
1841 * The RXON command in staging_rxon is committed to the hardware and
1842 * the active_rxon structure is updated with the new data. This
1843 * function correctly transitions out of the RXON_ASSOC_MSK state if
1844 * a HW tune is required based on the RXON structure changes.
1845 */
1846static int iwl3945_commit_rxon(struct iwl_priv *priv)
1847{
1848 /* cast away the const for active_rxon in this function */
1849 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1850 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1851 int rc = 0;
1852 bool new_assoc =
1853 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1854
1855 if (!iwl_is_alive(priv))
1856 return -1;
1857
1858 /* always get timestamp with Rx frame */
1859 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1860
1861 /* select antenna */
1862 staging_rxon->flags &=
1863 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1864 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1865
1866 rc = iwl_check_rxon_cmd(priv);
1867 if (rc) {
1868 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1869 return -EINVAL;
1870 }
1871
1872 /* If we don't need to send a full RXON, we can use
1873 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1874 * and other flags for the current radio configuration. */
1875 if (!iwl_full_rxon_required(priv)) {
1876 rc = iwl_send_rxon_assoc(priv);
1877 if (rc) {
1878 IWL_ERR(priv, "Error setting RXON_ASSOC "
1879 "configuration (%d).\n", rc);
1880 return rc;
1881 }
1882
1883 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1884
1885 return 0;
1886 }
1887
1888 /* If we are currently associated and the new config requires
1889 * an RXON_ASSOC and the new config wants the associated mask enabled,
1890 * we must clear the associated from the active configuration
1891 * before we apply the new config */
1892 if (iwl_is_associated(priv) && new_assoc) {
1893 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1894 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1895
1896 /*
1897 * reserved4 and 5 could have been filled by the iwlcore code.
1898 * Let's clear them before pushing to the 3945.
1899 */
1900 active_rxon->reserved4 = 0;
1901 active_rxon->reserved5 = 0;
1902 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1903 sizeof(struct iwl3945_rxon_cmd),
1904 &priv->active_rxon);
1905
1906 /* If the mask clearing failed then we set
1907 * active_rxon back to what it was previously */
1908 if (rc) {
1909 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1910 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1911 "configuration (%d).\n", rc);
1912 return rc;
1913 }
1914 }
1915
1916 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1917 "* with%s RXON_FILTER_ASSOC_MSK\n"
1918 "* channel = %d\n"
1919 "* bssid = %pM\n",
1920 (new_assoc ? "" : "out"),
1921 le16_to_cpu(staging_rxon->channel),
1922 staging_rxon->bssid_addr);
1923
1924 /*
1925 * reserved4 and 5 could have been filled by the iwlcore code.
1926 * Let's clear them before pushing to the 3945.
1927 */
1928 staging_rxon->reserved4 = 0;
1929 staging_rxon->reserved5 = 0;
1930
90e8e424 1931 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1932
1933 /* Apply the new configuration */
1934 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1935 sizeof(struct iwl3945_rxon_cmd),
1936 staging_rxon);
1937 if (rc) {
1938 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1939 return rc;
1940 }
1941
1942 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1943
c587de0b 1944 iwl_clear_stations_table(priv);
e0158e61
AK		 1945
1946 /* If we issue a new RXON command which required a tune then we must
1947 * send a new TXPOWER command or we won't be able to Tx any frames */
1948 rc = priv->cfg->ops->lib->send_tx_power(priv);
1949 if (rc) {
1950 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1951 return rc;
1952 }
1953
1954 /* Add the broadcast address so we can send broadcast frames */
3459ab5a 1955 priv->cfg->ops->lib->add_bcast_station(priv);
e0158e61
AK		 1956
1957 /* If we have set the ASSOC_MSK and we are in BSS mode then
1958 * add the IWL_AP_ID to the station rate table */
1959 if (iwl_is_associated(priv) &&
1960 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 1961 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1962 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 1963 IWL_ERR(priv, "Error adding AP address for transmit\n");
1964 return -EIO;
1965 }
1966
1967 /* Init the hardware's rate fallback order based on the band */
1968 rc = iwl3945_init_hw_rate_table(priv);
1969 if (rc) {
1970 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1971 return -EIO;
1972 }
1973
1974 return 0;
1975}
1976
b481de9c
ZY		 1977/**
1978 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1979 *
1980 * -- reset periodic timer
1981 * -- see if temp has changed enough to warrant re-calibration ... if so:
1982 * -- correct coeffs for temp (can reset temp timer)
1983 * -- save this temp as "last",
1984 * -- send new set of gain settings to NIC
1985 * NOTE: This should continue working, even when we're not associated,
1986 * so we can keep our internal table of scan powers current. */
4a8a4322 1987void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1988{
1989 /* This will kick in the "brute force"
bb8c093b 1990 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1991 if (!is_temp_calib_needed(priv))
1992 goto reschedule;
1993
1994 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1995 * This is based *only* on current temperature,
1996 * ignoring any previous power measurements */
bb8c093b 1997 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1998
1999 reschedule:
2000 queue_delayed_work(priv->workqueue,
ee525d13 2001 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ);
b481de9c
ZY		 2002}
2003
416e1438 2004static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2005{
4a8a4322 2006 struct iwl_priv *priv = container_of(work, struct iwl_priv,
ee525d13 2007 _3945.thermal_periodic.work);
b481de9c
ZY		 2008
2009 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2010 return;
2011
2012 mutex_lock(&priv->mutex);
2013 iwl3945_reg_txpower_periodic(priv);
2014 mutex_unlock(&priv->mutex);
2015}
2016
2017/**
bb8c093b 2018 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2019 * for the channel.
2020 *
2021 * This function is used when initializing channel-info structs.
2022 *
2023 * NOTE: These channel groups do *NOT* match the bands above!
2024 * These channel groups are based on factory-tested channels;
2025 * on A-band, EEPROM's "group frequency" entries represent the top
2026 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2027 */
4a8a4322 2028static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2029 const struct iwl_channel_info *ch_info)
b481de9c 2030{
e6148917
SO		 2031 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2032 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2033 u8 group;
2034 u16 group_index = 0; /* based on factory calib frequencies */
2035 u8 grp_channel;
2036
2037 /* Find the group index for the channel ... don't use index 1(?) */
2038 if (is_channel_a_band(ch_info)) {
2039 for (group = 1; group < 5; group++) {
2040 grp_channel = ch_grp[group].group_channel;
2041 if (ch_info->channel <= grp_channel) {
2042 group_index = group;
2043 break;
2044 }
2045 }
2046 /* group 4 has a few channels *above* its factory cal freq */
2047 if (group == 5)
2048 group_index = 4;
2049 } else
2050 group_index = 0; /* 2.4 GHz, group 0 */
2051
e1623446 2052 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2053 group_index);
2054 return group_index;
2055}
2056
2057/**
bb8c093b 2058 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2059 *
2060 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2061 * into radio/DSP gain settings table for requested power.
2062 */
4a8a4322 2063static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2064 s8 requested_power,
2065 s32 setting_index, s32 *new_index)
2066{
bb8c093b 2067 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2068 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2069 s32 index0, index1;
2070 s32 power = 2 * requested_power;
2071 s32 i;
bb8c093b 2072 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2073 s32 gains0, gains1;
2074 s32 res;
2075 s32 denominator;
2076
e6148917 2077 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2078 samples = chnl_grp->samples;
2079 for (i = 0; i < 5; i++) {
2080 if (power == samples[i].power) {
2081 *new_index = samples[i].gain_index;
2082 return 0;
2083 }
2084 }
2085
2086 if (power > samples[1].power) {
2087 index0 = 0;
2088 index1 = 1;
2089 } else if (power > samples[2].power) {
2090 index0 = 1;
2091 index1 = 2;
2092 } else if (power > samples[3].power) {
2093 index0 = 2;
2094 index1 = 3;
2095 } else {
2096 index0 = 3;
2097 index1 = 4;
2098 }
2099
2100 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2101 if (denominator == 0)
2102 return -EINVAL;
2103 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2104 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2105 res = gains0 + (gains1 - gains0) *
2106 ((s32) power - (s32) samples[index0].power) / denominator +
2107 (1 << 18);
2108 *new_index = res >> 19;
2109 return 0;
2110}
2111
4a8a4322 2112static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2113{
2114 u32 i;
2115 s32 rate_index;
e6148917 2116 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2117 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2118
e1623446 2119 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2120
2121 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2122 s8 *clip_pwrs; /* table of power levels for each rate */
2123 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2124 group = &eeprom->groups[i];
b481de9c
ZY		 2125
2126 /* sanity check on factory saturation power value */
2127 if (group->saturation_power < 40) {
39aadf8c 2128 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2129 "less than minimum expected 40\n",
2130 group->saturation_power);
2131 return;
2132 }
2133
2134 /*
2135 * Derive requested power levels for each rate, based on
2136 * hardware capabilities (saturation power for band).
2137 * Basic value is 3dB down from saturation, with further
2138 * power reductions for highest 3 data rates. These
2139 * backoffs provide headroom for high rate modulation
2140 * power peaks, without too much distortion (clipping).
2141 */
2142 /* we'll fill in this array with h/w max power levels */
67d613ae 2143 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers;
b481de9c
ZY		 2144
2145 /* divide factory saturation power by 2 to find -3dB level */
2146 satur_pwr = (s8) (group->saturation_power >> 1);
2147
2148 /* fill in channel group's nominal powers for each rate */
2149 for (rate_index = 0;
2150 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2151 switch (rate_index) {
14577f23 2152 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2153 if (i == 0) /* B/G */
2154 *clip_pwrs = satur_pwr;
2155 else /* A */
2156 *clip_pwrs = satur_pwr - 5;
2157 break;
14577f23 2158 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2159 if (i == 0)
2160 *clip_pwrs = satur_pwr - 7;
2161 else
2162 *clip_pwrs = satur_pwr - 10;
2163 break;
14577f23 2164 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2165 if (i == 0)
2166 *clip_pwrs = satur_pwr - 9;
2167 else
2168 *clip_pwrs = satur_pwr - 12;
2169 break;
2170 default:
2171 *clip_pwrs = satur_pwr;
2172 break;
2173 }
2174 }
2175 }
2176}
2177
2178/**
2179 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2180 *
2181 * Second pass (during init) to set up priv->channel_info
2182 *
2183 * Set up Tx-power settings in our channel info database for each VALID
2184 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2185 * and current temperature.
2186 *
2187 * Since this is based on current temperature (at init time), these values may
2188 * not be valid for very long, but it gives us a starting/default point,
2189 * and allows us to active (i.e. using Tx) scan.
2190 *
2191 * This does *not* write values to NIC, just sets up our internal table.
2192 */
4a8a4322 2193int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2194{
d20b3c65 2195 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2196 struct iwl3945_channel_power_info *pwr_info;
e6148917 2197 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2198 int delta_index;
2199 u8 rate_index;
2200 u8 scan_tbl_index;
2201 const s8 *clip_pwrs; /* array of power levels for each rate */
2202 u8 gain, dsp_atten;
2203 s8 power;
2204 u8 pwr_index, base_pwr_index, a_band;
2205 u8 i;
2206 int temperature;
2207
2208 /* save temperature reference,
2209 * so we can determine next time to calibrate */
bb8c093b 2210 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2211 priv->last_temperature = temperature;
2212
bb8c093b 2213 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2214
2215 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2216 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2217 i++, ch_info++) {
2218 a_band = is_channel_a_band(ch_info);
2219 if (!is_channel_valid(ch_info))
2220 continue;
2221
2222 /* find this channel's channel group (*not* "band") index */
2223 ch_info->group_index =
bb8c093b 2224 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2225
2226 /* Get this chnlgrp's rate->max/clip-powers table */
67d613ae 2227 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2228
2229 /* calculate power index *adjustment* value according to
2230 * diff between current temperature and factory temperature */
bb8c093b 2231 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2232 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2233 temperature);
2234
e1623446 2235 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2236 ch_info->channel, delta_index, temperature +
2237 IWL_TEMP_CONVERT);
2238
2239 /* set tx power value for all OFDM rates */
2240 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2241 rate_index++) {
25a4ccea 2242 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2243 int rc;
2244
2245 /* use channel group's clip-power table,
2246 * but don't exceed channel's max power */
2247 s8 pwr = min(ch_info->max_power_avg,
2248 clip_pwrs[rate_index]);
2249
2250 pwr_info = &ch_info->power_info[rate_index];
2251
2252 /* get base (i.e. at factory-measured temperature)
2253 * power table index for this rate's power */
bb8c093b 2254 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2255 ch_info->group_index,
2256 &power_idx);
2257 if (rc) {
15b1687c 2258 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2259 return rc;
2260 }
2261 pwr_info->base_power_index = (u8) power_idx;
2262
2263 /* temperature compensate */
2264 power_idx += delta_index;
2265
2266 /* stay within range of gain table */
bb8c093b 2267 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2268
bb8c093b 2269 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2270 pwr_info->requested_power = pwr;
2271 pwr_info->power_table_index = (u8) power_idx;
2272 pwr_info->tpc.tx_gain =
2273 power_gain_table[a_band][power_idx].tx_gain;
2274 pwr_info->tpc.dsp_atten =
2275 power_gain_table[a_band][power_idx].dsp_atten;
2276 }
2277
2278 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2279 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2280 power = pwr_info->requested_power +
2281 IWL_CCK_FROM_OFDM_POWER_DIFF;
2282 pwr_index = pwr_info->power_table_index +
2283 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2284 base_pwr_index = pwr_info->base_power_index +
2285 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2286
2287 /* stay within table range */
bb8c093b 2288 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2289 gain = power_gain_table[a_band][pwr_index].tx_gain;
2290 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2291
bb8c093b 2292 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2293 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2294 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2295 for (rate_index = 0;
2296 rate_index < IWL_CCK_RATES; rate_index++) {
2297 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2298 pwr_info->requested_power = power;
2299 pwr_info->power_table_index = pwr_index;
2300 pwr_info->base_power_index = base_pwr_index;
2301 pwr_info->tpc.tx_gain = gain;
2302 pwr_info->tpc.dsp_atten = dsp_atten;
2303 }
2304
2305 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2306 for (scan_tbl_index = 0;
2307 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2308 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2309 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2310 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2311 actual_index, clip_pwrs, ch_info, a_band);
2312 }
2313 }
2314
2315 return 0;
2316}
2317
4a8a4322 2318int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2319{
2320 int rc;
b481de9c 2321
5d49f498
AK		 2322 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2323 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2324 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2325 if (rc < 0)
15b1687c 2326 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2327
b481de9c
ZY		 2328 return 0;
2329}
2330
188cf6c7 2331int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2332{
b481de9c
ZY		 2333 int txq_id = txq->q.id;
2334
ee525d13 2335 struct iwl3945_shared *shared_data = priv->_3945.shared_virt;
b481de9c
ZY		 2336
2337 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2338
5d49f498
AK		 2339 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2340 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2341
5d49f498 2342 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2343 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2344 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2345 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2346 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2347 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2348
2349 /* fake read to flush all prev. writes */
5d49f498 2350 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2351
2352 return 0;
2353}
2354
42427b4e
KA		 2355/*
2356 * HCMD utils
2357 */
2358static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2359{
2360 switch (cmd_id) {
2361 case REPLY_RXON:
d25aabb0
WT		 2362 return sizeof(struct iwl3945_rxon_cmd);
2363 case POWER_TABLE_CMD:
2364 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2365 default:
2366 return len;
2367 }
2368}
2369
c587de0b 2370
17f841cd
SO		 2371static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2372{
c587de0b
TW		 2373 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2374 addsta->mode = cmd->mode;
2375 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2376 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2377 addsta->station_flags = cmd->station_flags;
2378 addsta->station_flags_msk = cmd->station_flags_msk;
2379 addsta->tid_disable_tx = cpu_to_le16(0);
2380 addsta->rate_n_flags = cmd->rate_n_flags;
2381 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2382 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2383 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2384
2385 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2386}
2387
c587de0b 2388
b481de9c
ZY		 2389/**
2390 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2391 */
4a8a4322 2392int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2393{
14577f23 2394 int rc, i, index, prev_index;
bb8c093b 2395 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2396 .reserved = {0, 0, 0},
2397 };
bb8c093b 2398 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2399
bb8c093b
CH		 2400 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2401 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2402
2403 table[index].rate_n_flags =
bb8c093b 2404 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2405 table[index].try_cnt = priv->retry_rate;
bb8c093b 2406 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2407 table[index].next_rate_index =
2408 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2409 }
2410
8318d78a
JB		 2411 switch (priv->band) {
2412 case IEEE80211_BAND_5GHZ:
e1623446 2413 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2414 /* If one of the following CCK rates is used,
2415 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2416 for (i = IWL_RATE_1M_INDEX_TABLE;
2417 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2418 table[i].next_rate_index =
2419 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2420
2421 /* Don't fall back to CCK rates */
7262796a
AM		 2422 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2423 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2424
2425 /* Don't drop out of OFDM rates */
14577f23 2426 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2427 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2428 break;
2429
8318d78a 2430 case IEEE80211_BAND_2GHZ:
e1623446 2431 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2432 /* If an OFDM rate is used, have it fall back to the
2433 * 1M CCK rates */
b481de9c 2434
ee525d13 2435 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2436 iwl_is_associated(priv)) {
7262796a
AM		 2437
2438 index = IWL_FIRST_CCK_RATE;
2439 for (i = IWL_RATE_6M_INDEX_TABLE;
2440 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2441 table[i].next_rate_index =
2442 iwl3945_rates[index].table_rs_index;
2443
2444 index = IWL_RATE_11M_INDEX_TABLE;
2445 /* CCK shouldn't fall back to OFDM... */
2446 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2447 }
b481de9c
ZY		 2448 break;
2449
2450 default:
8318d78a 2451 WARN_ON(1);
b481de9c
ZY		 2452 break;
2453 }
2454
2455 /* Update the rate scaling for control frame Tx */
2456 rate_cmd.table_id = 0;
518099a8 2457 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2458 &rate_cmd);
2459 if (rc)
2460 return rc;
2461
2462 /* Update the rate scaling for data frame Tx */
2463 rate_cmd.table_id = 1;
518099a8 2464 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2465 &rate_cmd);
2466}
2467
796083cb 2468/* Called when initializing driver */
4a8a4322 2469int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2470{
3832ec9d
AK		 2471 memset((void *)&priv->hw_params, 0,
2472 sizeof(struct iwl_hw_params));
b481de9c 2473
ee525d13
JB		 2474 priv->_3945.shared_virt =
2475 dma_alloc_coherent(&priv->pci_dev->dev,
2476 sizeof(struct iwl3945_shared),
2477 &priv->_3945.shared_phys, GFP_KERNEL);
2478 if (!priv->_3945.shared_virt) {
15b1687c 2479 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2480 mutex_unlock(&priv->mutex);
2481 return -ENOMEM;
2482 }
2483
21c02a1a 2484 /* Assign number of Usable TX queues */
88804e2b 2485 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2486
a8e74e27 2487 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2f301227 2488 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K);
3832ec9d
AK		 2489 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2490 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2491 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2492 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2493
141c43a3 2494 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2495 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2496
b481de9c
ZY		 2497 return 0;
2498}
2499
4a8a4322 2500unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2501 struct iwl3945_frame *frame, u8 rate)
b481de9c 2502{
bb8c093b 2503 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2504 unsigned int frame_size;
2505
bb8c093b 2506 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2507 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2508
3832ec9d 2509 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2510 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2511
bb8c093b 2512 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2513 tx_beacon_cmd->frame,
b481de9c
ZY		 2514 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2515
2516 BUG_ON(frame_size > MAX_MPDU_SIZE);
2517 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2518
2519 tx_beacon_cmd->tx.rate = rate;
2520 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2521 TX_CMD_FLG_TSF_MSK);
2522
14577f23
MA		 2523 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2524 tx_beacon_cmd->tx.supp_rates[0] =
2525 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2526
b481de9c 2527 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2528 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2529
3ac7f146 2530 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2531}
2532
4a8a4322 2533void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2534{
91c066f2 2535 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2536 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2537}
2538
4a8a4322 2539void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c 2540{
ee525d13 2541 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic,
b481de9c
ZY		 2542 iwl3945_bg_reg_txpower_periodic);
2543}
2544
4a8a4322 2545void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c 2546{
ee525d13 2547 cancel_delayed_work(&priv->_3945.thermal_periodic);
b481de9c
ZY		 2548}
2549
0164b9b4
KA		 2550/* check contents of special bootstrap uCode SRAM */
2551static int iwl3945_verify_bsm(struct iwl_priv *priv)
2552 {
2553 __le32 *image = priv->ucode_boot.v_addr;
2554 u32 len = priv->ucode_boot.len;
2555 u32 reg;
2556 u32 val;
2557
e1623446 2558 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2559
2560 /* verify BSM SRAM contents */
2561 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2562 for (reg = BSM_SRAM_LOWER_BOUND;
2563 reg < BSM_SRAM_LOWER_BOUND + len;
2564 reg += sizeof(u32), image++) {
2565 val = iwl_read_prph(priv, reg);
2566 if (val != le32_to_cpu(*image)) {
2567 IWL_ERR(priv, "BSM uCode verification failed at "
2568 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2569 BSM_SRAM_LOWER_BOUND,
2570 reg - BSM_SRAM_LOWER_BOUND, len,
2571 val, le32_to_cpu(*image));
2572 return -EIO;
2573 }
2574 }
2575
e1623446 2576 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2577
2578 return 0;
2579}
2580
e6148917
SO		 2581
2582/******************************************************************************
2583 *
2584 * EEPROM related functions
2585 *
2586 ******************************************************************************/
2587
2588/*
2589 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2590 * embedded controller) as EEPROM reader; each read is a series of pulses
2591 * to/from the EEPROM chip, not a single event, so even reads could conflict
2592 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2593 * simply claims ownership, which should be safe when this function is called
2594 * (i.e. before loading uCode!).
2595 */
2596static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2597{
2598 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2599 return 0;
2600}
2601
2602
2603static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2604{
2605 return;
2606}
2607
0164b9b4
KA		 2608 /**
2609 * iwl3945_load_bsm - Load bootstrap instructions
2610 *
2611 * BSM operation:
2612 *
2613 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2614 * in special SRAM that does not power down during RFKILL. When powering back
2615 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2616 * the bootstrap program into the on-board processor, and starts it.
2617 *
2618 * The bootstrap program loads (via DMA) instructions and data for a new
2619 * program from host DRAM locations indicated by the host driver in the
2620 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2621 * automatically.
2622 *
2623 * When initializing the NIC, the host driver points the BSM to the
2624 * "initialize" uCode image. This uCode sets up some internal data, then
2625 * notifies host via "initialize alive" that it is complete.
2626 *
2627 * The host then replaces the BSM_DRAM_* pointer values to point to the
2628 * normal runtime uCode instructions and a backup uCode data cache buffer
2629 * (filled initially with starting data values for the on-board processor),
2630 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2631 * which begins normal operation.
2632 *
2633 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2634 * the backup data cache in DRAM before SRAM is powered down.
2635 *
2636 * When powering back up, the BSM loads the bootstrap program. This reloads
2637 * the runtime uCode instructions and the backup data cache into SRAM,
2638 * and re-launches the runtime uCode from where it left off.
2639 */
2640static int iwl3945_load_bsm(struct iwl_priv *priv)
2641{
2642 __le32 *image = priv->ucode_boot.v_addr;
2643 u32 len = priv->ucode_boot.len;
2644 dma_addr_t pinst;
2645 dma_addr_t pdata;
2646 u32 inst_len;
2647 u32 data_len;
2648 int rc;
2649 int i;
2650 u32 done;
2651 u32 reg_offset;
2652
e1623446 2653 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2654
2655 /* make sure bootstrap program is no larger than BSM's SRAM size */
2656 if (len > IWL39_MAX_BSM_SIZE)
2657 return -EINVAL;
2658
2659 /* Tell bootstrap uCode where to find the "Initialize" uCode
2660 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2661 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2662 * after the "initialize" uCode has run, to point to
2663 * runtime/protocol instructions and backup data cache. */
2664 pinst = priv->ucode_init.p_addr;
2665 pdata = priv->ucode_init_data.p_addr;
2666 inst_len = priv->ucode_init.len;
2667 data_len = priv->ucode_init_data.len;
2668
0164b9b4
KA		 2669 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2670 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2671 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2672 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2673
2674 /* Fill BSM memory with bootstrap instructions */
2675 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2676 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2677 reg_offset += sizeof(u32), image++)
2678 _iwl_write_prph(priv, reg_offset,
2679 le32_to_cpu(*image));
2680
2681 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2682 if (rc)
0164b9b4 2683 return rc;
0164b9b4
KA		 2684
2685 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2686 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2687 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2688 IWL39_RTC_INST_LOWER_BOUND);
2689 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2690
2691 /* Load bootstrap code into instruction SRAM now,
2692 * to prepare to load "initialize" uCode */
2693 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2694 BSM_WR_CTRL_REG_BIT_START);
2695
2696 /* Wait for load of bootstrap uCode to finish */
2697 for (i = 0; i < 100; i++) {
2698 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2699 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2700 break;
2701 udelay(10);
2702 }
2703 if (i < 100)
e1623446 2704 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2705 else {
2706 IWL_ERR(priv, "BSM write did not complete!\n");
2707 return -EIO;
2708 }
2709
2710 /* Enable future boot loads whenever power management unit triggers it
2711 * (e.g. when powering back up after power-save shutdown) */
2712 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2713 BSM_WR_CTRL_REG_BIT_START_EN);
2714
0164b9b4
KA		 2715 return 0;
2716}
2717
cc0f555d
JS		 2718#define IWL3945_UCODE_GET(item) \
2719static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2720 u32 api_ver) \
2721{ \
2722 return le32_to_cpu(ucode->u.v1.item); \
2723}
2724
2725static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2726{
2727 return UCODE_HEADER_SIZE(1);
2728}
2729static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2730 u32 api_ver)
2731{
2732 return 0;
2733}
2734static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2735 u32 api_ver)
2736{
2737 return (u8 *) ucode->u.v1.data;
2738}
2739
2740IWL3945_UCODE_GET(inst_size);
2741IWL3945_UCODE_GET(data_size);
2742IWL3945_UCODE_GET(init_size);
2743IWL3945_UCODE_GET(init_data_size);
2744IWL3945_UCODE_GET(boot_size);
2745
5bbe233b
AK		 2746static struct iwl_hcmd_ops iwl3945_hcmd = {
2747 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2748 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2749};
2750
cc0f555d
JS		 2751static struct iwl_ucode_ops iwl3945_ucode = {
2752 .get_header_size = iwl3945_ucode_get_header_size,
2753 .get_build = iwl3945_ucode_get_build,
2754 .get_inst_size = iwl3945_ucode_get_inst_size,
2755 .get_data_size = iwl3945_ucode_get_data_size,
2756 .get_init_size = iwl3945_ucode_get_init_size,
2757 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2758 .get_boot_size = iwl3945_ucode_get_boot_size,
2759 .get_data = iwl3945_ucode_get_data,
2760};
2761
0164b9b4 2762static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2763 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2764 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2765 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2766 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2767 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2768 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2769 .apm_ops = {
2770 .init = iwl3945_apm_init,
d68b603c 2771 .stop = iwl_apm_stop,
01ec616d 2772 .config = iwl3945_nic_config,
854682ed 2773 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2774 },
e6148917
SO		 2775 .eeprom_ops = {
2776 .regulatory_bands = {
2777 EEPROM_REGULATORY_BAND_1_CHANNELS,
2778 EEPROM_REGULATORY_BAND_2_CHANNELS,
2779 EEPROM_REGULATORY_BAND_3_CHANNELS,
2780 EEPROM_REGULATORY_BAND_4_CHANNELS,
2781 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2782 EEPROM_REGULATORY_BAND_NO_HT40,
2783 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2784 },
2785 .verify_signature = iwlcore_eeprom_verify_signature,
2786 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2787 .release_semaphore = iwl3945_eeprom_release_semaphore,
2788 .query_addr = iwlcore_eeprom_query_addr,
2789 },
75bcfae9 2790 .send_tx_power = iwl3945_send_tx_power,
c2436980 2791 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2792 .post_associate = iwl3945_post_associate,
ef850d7c 2793 .isr = iwl_isr_legacy,
60690a6a 2794 .config_ap = iwl3945_config_ap,
3459ab5a 2795 .add_bcast_station = iwl3945_add_bcast_station,
0164b9b4
KA		 2796};
2797
42427b4e
KA		 2798static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2799 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2800 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2801 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
42427b4e
KA		 2802};
2803
45d5d805 2804static const struct iwl_ops iwl3945_ops = {
cc0f555d 2805 .ucode = &iwl3945_ucode,
0164b9b4 2806 .lib = &iwl3945_lib,
5bbe233b 2807 .hcmd = &iwl3945_hcmd,
42427b4e 2808 .utils = &iwl3945_hcmd_utils,
e932a609 2809 .led = &iwl3945_led_ops,
0164b9b4
KA		 2810};
2811
c0f20d91 2812static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2813 .name = "3945BG",
a0987a8d
RC		 2814 .fw_name_pre = IWL3945_FW_PRE,
2815 .ucode_api_max = IWL3945_UCODE_API_MAX,
2816 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2817 .sku = IWL_SKU_G,
e6148917
SO		 2818 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2819 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2820 .ops = &iwl3945_ops,
88804e2b 2821 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2822 .mod_params = &iwl3945_mod_params,
fadb3582
BC		 2823 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL,
2824 .set_l0s = false,
2825 .use_bsm = true,
b261793d
DH		 2826 .use_isr_legacy = true,
2827 .ht_greenfield_support = false,
f2d0d0e2 2828 .led_compensation = 64,
bc45a670 2829 .broken_powersave = true,
3e4fb5fa 2830 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
82b9a121
TW		 2831};
2832
c0f20d91 2833static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2834 .name = "3945ABG",
a0987a8d
RC		 2835 .fw_name_pre = IWL3945_FW_PRE,
2836 .ucode_api_max = IWL3945_UCODE_API_MAX,
2837 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2838 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2839 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2840 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2841 .ops = &iwl3945_ops,
88804e2b 2842 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2843 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2844 .use_isr_legacy = true,
2845 .ht_greenfield_support = false,
f2d0d0e2 2846 .led_compensation = 64,
bc45a670 2847 .broken_powersave = true,
3e4fb5fa 2848 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_THRESHOLD_DEF,
82b9a121
TW		 2849};
2850
a3aa1884 2851DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = {
82b9a121
TW		 2852 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2853 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2854 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2855 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2856 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2857 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2858 {0}
2859};
2860
bb8c093b 2861MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree