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iwlwifi/iwl3945: unify rts_tx_cmd_flag
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
01f8162a 3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
dbb6654c 41#include "iwl-fh.h"
bddadf86 42#include "iwl-3945-fh.h"
600c0e11 43#include "iwl-commands.h"
17f841cd 44#include "iwl-sta.h"
b481de9c 45#include "iwl-3945.h"
e6148917 46#include "iwl-eeprom.h"
5d08cd1d 47#include "iwl-helpers.h"
5747d47f 48#include "iwl-core.h"
e932a609
JB		 49#include "iwl-led.h"
50#include "iwl-3945-led.h"
b481de9c
ZY		 51
52#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
53 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 60 IWL_RATE_##np##M_INDEX, \
61 IWL_RATE_##r##M_INDEX_TABLE, \
62 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 63
64/*
65 * Parameter order:
66 * rate, prev rate, next rate, prev tgg rate, next tgg rate
67 *
68 * If there isn't a valid next or previous rate then INV is used which
69 * maps to IWL_RATE_INVALID
70 *
71 */
d9829a67 72const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 73 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
74 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
75 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
76 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 77 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
78 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
79 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
80 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
81 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
82 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
83 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
84 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 85};
86
bb8c093b 87/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 88#define IWL_EVT_DISABLE (0)
89#define IWL_EVT_DISABLE_SIZE (1532/32)
90
91/**
bb8c093b 92 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 93 *
94 * Disable an event by writing "1"s into "disable"
95 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
96 * Default values of 0 enable uCode events to be logged.
97 * Use for only special debugging. This function is just a placeholder as-is,
98 * you'll need to provide the special bits! ...
99 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 100void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 101{
b481de9c
ZY		 102 int i;
103 u32 base; /* SRAM address of event log header */
104 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
105 u32 array_size; /* # of u32 entries in array */
106 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
107 0x00000000, /* 31 - 0 Event id numbers */
108 0x00000000, /* 63 - 32 */
109 0x00000000, /* 95 - 64 */
110 0x00000000, /* 127 - 96 */
111 0x00000000, /* 159 - 128 */
112 0x00000000, /* 191 - 160 */
113 0x00000000, /* 223 - 192 */
114 0x00000000, /* 255 - 224 */
115 0x00000000, /* 287 - 256 */
116 0x00000000, /* 319 - 288 */
117 0x00000000, /* 351 - 320 */
118 0x00000000, /* 383 - 352 */
119 0x00000000, /* 415 - 384 */
120 0x00000000, /* 447 - 416 */
121 0x00000000, /* 479 - 448 */
122 0x00000000, /* 511 - 480 */
123 0x00000000, /* 543 - 512 */
124 0x00000000, /* 575 - 544 */
125 0x00000000, /* 607 - 576 */
126 0x00000000, /* 639 - 608 */
127 0x00000000, /* 671 - 640 */
128 0x00000000, /* 703 - 672 */
129 0x00000000, /* 735 - 704 */
130 0x00000000, /* 767 - 736 */
131 0x00000000, /* 799 - 768 */
132 0x00000000, /* 831 - 800 */
133 0x00000000, /* 863 - 832 */
134 0x00000000, /* 895 - 864 */
135 0x00000000, /* 927 - 896 */
136 0x00000000, /* 959 - 928 */
137 0x00000000, /* 991 - 960 */
138 0x00000000, /* 1023 - 992 */
139 0x00000000, /* 1055 - 1024 */
140 0x00000000, /* 1087 - 1056 */
141 0x00000000, /* 1119 - 1088 */
142 0x00000000, /* 1151 - 1120 */
143 0x00000000, /* 1183 - 1152 */
144 0x00000000, /* 1215 - 1184 */
145 0x00000000, /* 1247 - 1216 */
146 0x00000000, /* 1279 - 1248 */
147 0x00000000, /* 1311 - 1280 */
148 0x00000000, /* 1343 - 1312 */
149 0x00000000, /* 1375 - 1344 */
150 0x00000000, /* 1407 - 1376 */
151 0x00000000, /* 1439 - 1408 */
152 0x00000000, /* 1471 - 1440 */
153 0x00000000, /* 1503 - 1472 */
154 };
155
156 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 157 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 158 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 159 return;
160 }
161
5d49f498
AK		 162 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
163 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
b481de9c
ZY		 164
165 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
e1623446 166 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
b481de9c 167 disable_ptr);
b481de9c 168 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 169 iwl_write_targ_mem(priv,
af7cca2a
TW		 170 disable_ptr + (i * sizeof(u32)),
171 evt_disable[i]);
b481de9c 172
b481de9c 173 } else {
e1623446
TW		 174 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
175 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n");
176 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n",
b481de9c
ZY		 177 disable_ptr, array_size);
178 }
179
180}
181
17744ff6
TW		 182static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
183{
184 int idx;
185
186 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
187 if (iwl3945_rates[idx].plcp == plcp)
188 return idx;
189 return -1;
190}
191
d08853a3 192#ifdef CONFIG_IWLWIFI_DEBUG
91c066f2
TW		 193#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
194
195static const char *iwl3945_get_tx_fail_reason(u32 status)
196{
197 switch (status & TX_STATUS_MSK) {
198 case TX_STATUS_SUCCESS:
199 return "SUCCESS";
200 TX_STATUS_ENTRY(SHORT_LIMIT);
201 TX_STATUS_ENTRY(LONG_LIMIT);
202 TX_STATUS_ENTRY(FIFO_UNDERRUN);
203 TX_STATUS_ENTRY(MGMNT_ABORT);
204 TX_STATUS_ENTRY(NEXT_FRAG);
205 TX_STATUS_ENTRY(LIFE_EXPIRE);
206 TX_STATUS_ENTRY(DEST_PS);
207 TX_STATUS_ENTRY(ABORTED);
208 TX_STATUS_ENTRY(BT_RETRY);
209 TX_STATUS_ENTRY(STA_INVALID);
210 TX_STATUS_ENTRY(FRAG_DROPPED);
211 TX_STATUS_ENTRY(TID_DISABLE);
212 TX_STATUS_ENTRY(FRAME_FLUSHED);
213 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
214 TX_STATUS_ENTRY(TX_LOCKED);
215 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
216 }
217
218 return "UNKNOWN";
219}
220#else
221static inline const char *iwl3945_get_tx_fail_reason(u32 status)
222{
223 return "";
224}
225#endif
226
e6a9854b
JB		 227/*
228 * get ieee prev rate from rate scale table.
229 * for A and B mode we need to overright prev
230 * value
231 */
4a8a4322 232int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 233{
234 int next_rate = iwl3945_get_prev_ieee_rate(rate);
235
236 switch (priv->band) {
237 case IEEE80211_BAND_5GHZ:
238 if (rate == IWL_RATE_12M_INDEX)
239 next_rate = IWL_RATE_9M_INDEX;
240 else if (rate == IWL_RATE_6M_INDEX)
241 next_rate = IWL_RATE_6M_INDEX;
242 break;
7262796a
AM		 243 case IEEE80211_BAND_2GHZ:
244 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 245 iwl_is_associated(priv)) {
7262796a
AM		 246 if (rate == IWL_RATE_11M_INDEX)
247 next_rate = IWL_RATE_5M_INDEX;
248 }
e6a9854b 249 break;
7262796a 250
e6a9854b
JB		 251 default:
252 break;
253 }
254
255 return next_rate;
256}
257
91c066f2
TW		 258
259/**
260 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
261 *
262 * When FW advances 'R' index, all entries between old and new 'R' index
263 * need to be reclaimed. As result, some free space forms. If there is
264 * enough free space (> low mark), wake the stack that feeds us.
265 */
4a8a4322 266static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 267 int txq_id, int index)
268{
188cf6c7 269 struct iwl_tx_queue *txq = &priv->txq[txq_id];
d20b3c65 270 struct iwl_queue *q = &txq->q;
dbb6654c 271 struct iwl_tx_info *tx_info;
91c066f2
TW		 272
273 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
274
275 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
276 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
277
278 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 279 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2 280 tx_info->skb[0] = NULL;
7aaa1d79 281 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
91c066f2
TW		 282 }
283
d20b3c65 284 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 285 (txq_id != IWL_CMD_QUEUE_NUM) &&
286 priv->mac80211_registered)
e4e72fb4 287 iwl_wake_queue(priv, txq_id);
91c066f2
TW		 288}
289
290/**
291 * iwl3945_rx_reply_tx - Handle Tx response
292 */
4a8a4322 293static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 294 struct iwl_rx_mem_buffer *rxb)
91c066f2 295{
3d24a9f7 296 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 297 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
298 int txq_id = SEQ_TO_QUEUE(sequence);
299 int index = SEQ_TO_INDEX(sequence);
188cf6c7 300 struct iwl_tx_queue *txq = &priv->txq[txq_id];
e039fa4a 301 struct ieee80211_tx_info *info;
91c066f2
TW		 302 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
303 u32 status = le32_to_cpu(tx_resp->status);
304 int rate_idx;
74221d07 305 int fail;
91c066f2 306
625a381a 307 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
15b1687c 308 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 309 "is out of range [0-%d] %d %d\n", txq_id,
310 index, txq->q.n_bd, txq->q.write_ptr,
311 txq->q.read_ptr);
312 return;
313 }
314
e039fa4a 315 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 316 ieee80211_tx_info_clear_status(info);
317
318 /* Fill the MRR chain with some info about on-chip retransmissions */
319 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
320 if (info->band == IEEE80211_BAND_5GHZ)
321 rate_idx -= IWL_FIRST_OFDM_RATE;
322
323 fail = tx_resp->failure_frame;
74221d07
AM		 324
325 info->status.rates[0].idx = rate_idx;
326 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 327
91c066f2 328 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 329 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
330 IEEE80211_TX_STAT_ACK : 0;
91c066f2 331
e1623446 332 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
91c066f2
TW		 333 txq_id, iwl3945_get_tx_fail_reason(status), status,
334 tx_resp->rate, tx_resp->failure_frame);
335
e1623446 336 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
91c066f2
TW		 337 iwl3945_tx_queue_reclaim(priv, txq_id, index);
338
339 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 340 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 341}
342
343
344
b481de9c
ZY		 345/*****************************************************************************
346 *
347 * Intel PRO/Wireless 3945ABG/BG Network Connection
348 *
349 * RX handler implementations
350 *
b481de9c
ZY		 351 *****************************************************************************/
352
396887a2
DH		 353void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
354 struct iwl_rx_mem_buffer *rxb)
b481de9c 355{
3d24a9f7 356 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
e1623446 357 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
bb8c093b 358 (int)sizeof(struct iwl3945_notif_statistics),
396887a2 359 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
b481de9c 360
f2c7e521 361 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 362
e932a609 363 iwl_leds_background(priv);
b481de9c
ZY		 364}
365
17744ff6
TW		 366/******************************************************************************
367 *
368 * Misc. internal state and helper functions
369 *
370 ******************************************************************************/
d08853a3 371#ifdef CONFIG_IWLWIFI_DEBUG
17744ff6
TW		 372
373/**
374 * iwl3945_report_frame - dump frame to syslog during debug sessions
375 *
376 * You may hack this function to show different aspects of received frames,
377 * including selective frame dumps.
378 * group100 parameter selects whether to show 1 out of 100 good frames.
379 */
d08853a3 380static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 381 struct iwl_rx_packet *pkt,
17744ff6
TW		 382 struct ieee80211_hdr *header, int group100)
383{
384 u32 to_us;
385 u32 print_summary = 0;
386 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
387 u32 hundred = 0;
388 u32 dataframe = 0;
fd7c8a40 389 __le16 fc;
17744ff6
TW		 390 u16 seq_ctl;
391 u16 channel;
392 u16 phy_flags;
393 u16 length;
394 u16 status;
395 u16 bcn_tmr;
396 u32 tsf_low;
397 u64 tsf;
398 u8 rssi;
399 u8 agc;
400 u16 sig_avg;
401 u16 noise_diff;
402 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
403 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
404 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
405 u8 *data = IWL_RX_DATA(pkt);
406
407 /* MAC header */
fd7c8a40 408 fc = header->frame_control;
17744ff6
TW		 409 seq_ctl = le16_to_cpu(header->seq_ctrl);
410
411 /* metadata */
412 channel = le16_to_cpu(rx_hdr->channel);
413 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
414 length = le16_to_cpu(rx_hdr->len);
415
416 /* end-of-frame status and timestamp */
417 status = le32_to_cpu(rx_end->status);
418 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
419 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
420 tsf = le64_to_cpu(rx_end->timestamp);
421
422 /* signal statistics */
423 rssi = rx_stats->rssi;
424 agc = rx_stats->agc;
425 sig_avg = le16_to_cpu(rx_stats->sig_avg);
426 noise_diff = le16_to_cpu(rx_stats->noise_diff);
427
428 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
429
430 /* if data frame is to us and all is good,
431 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 432 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
433 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 434 dataframe = 1;
435 if (!group100)
436 print_summary = 1; /* print each frame */
437 else if (priv->framecnt_to_us < 100) {
438 priv->framecnt_to_us++;
439 print_summary = 0;
440 } else {
441 priv->framecnt_to_us = 0;
442 print_summary = 1;
443 hundred = 1;
444 }
445 } else {
446 /* print summary for all other frames */
447 print_summary = 1;
448 }
449
450 if (print_summary) {
451 char *title;
0ff1cca0 452 int rate;
17744ff6
TW		 453
454 if (hundred)
455 title = "100Frames";
fd7c8a40 456 else if (ieee80211_has_retry(fc))
17744ff6 457 title = "Retry";
fd7c8a40 458 else if (ieee80211_is_assoc_resp(fc))
17744ff6 459 title = "AscRsp";
fd7c8a40 460 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 461 title = "RasRsp";
fd7c8a40 462 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 463 title = "PrbRsp";
464 print_dump = 1; /* dump frame contents */
465 } else if (ieee80211_is_beacon(fc)) {
466 title = "Beacon";
467 print_dump = 1; /* dump frame contents */
468 } else if (ieee80211_is_atim(fc))
469 title = "ATIM";
470 else if (ieee80211_is_auth(fc))
471 title = "Auth";
472 else if (ieee80211_is_deauth(fc))
473 title = "DeAuth";
474 else if (ieee80211_is_disassoc(fc))
475 title = "DisAssoc";
476 else
477 title = "Frame";
478
479 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
480 if (rate == -1)
481 rate = 0;
482 else
483 rate = iwl3945_rates[rate].ieee / 2;
484
485 /* print frame summary.
486 * MAC addresses show just the last byte (for brevity),
487 * but you can hack it to show more, if you'd like to. */
488 if (dataframe)
e1623446 489 IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 490 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 491 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 492 length, rssi, channel, rate);
493 else {
494 /* src/dst addresses assume managed mode */
e1623446 495 IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
17744ff6
TW		 496 "src=0x%02x, rssi=%u, tim=%lu usec, "
497 "phy=0x%02x, chnl=%d\n",
fd7c8a40 498 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 499 header->addr3[5], rssi,
500 tsf_low - priv->scan_start_tsf,
501 phy_flags, channel);
502 }
503 }
504 if (print_dump)
3d816c77 505 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6 506}
d08853a3
SO		 507
508static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
509 struct iwl_rx_packet *pkt,
510 struct ieee80211_hdr *header, int group100)
511{
3d816c77 512 if (iwl_get_debug_level(priv) & IWL_DL_RX)
d08853a3
SO		 513 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
514}
515
17744ff6 516#else
4a8a4322 517static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 518 struct iwl_rx_packet *pkt,
17744ff6
TW		 519 struct ieee80211_hdr *header, int group100)
520{
521}
522#endif
523
4bd9b4f3 524/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 525static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 526 struct ieee80211_hdr *header)
527{
528 /* Filter incoming packets to determine if they are targeted toward
529 * this network, discarding packets coming from ourselves */
530 switch (priv->iw_mode) {
05c914fe 531 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 532 /* packets to our IBSS update information */
533 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 534 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 535 /* packets to our IBSS update information */
536 return !compare_ether_addr(header->addr2, priv->bssid);
537 default:
538 return 1;
539 }
540}
17744ff6 541
4a8a4322 542static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 543 struct iwl_rx_mem_buffer *rxb,
12342c47 544 struct ieee80211_rx_status *stats)
b481de9c 545{
3d24a9f7 546 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
4bd9b4f3 547 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
bb8c093b
CH		 548 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
549 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 550 short len = le16_to_cpu(rx_hdr->len);
551
552 /* We received data from the HW, so stop the watchdog */
3d24a9f7 553 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
e1623446 554 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
b481de9c
ZY		 555 return;
556 }
557
558 /* We only process data packets if the interface is open */
559 if (unlikely(!priv->is_open)) {
e1623446
TW		 560 IWL_DEBUG_DROP_LIMIT(priv,
561 "Dropping packet while interface is not open.\n");
b481de9c
ZY		 562 return;
563 }
b481de9c
ZY		 564
565 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
566 /* Set the size of the skb to the size of the frame */
567 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
568
9c74d9fb 569 if (!iwl3945_mod_params.sw_crypto)
8ccde88a
SO		 570 iwl_set_decrypted_flag(priv,
571 (struct ieee80211_hdr *)rxb->skb->data,
b481de9c
ZY		 572 le32_to_cpu(rx_end->status), stats);
573
22fdf3c9
WYG		 574 iwl_update_stats(priv, false, hdr->frame_control, len);
575
f1d58c25
JB		 576 memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
577 ieee80211_rx_irqsafe(priv->hw, rxb->skb);
b481de9c
ZY		 578 rxb->skb = NULL;
579}
580
7878a5a4
MA		 581#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
582
4a8a4322 583static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 584 struct iwl_rx_mem_buffer *rxb)
b481de9c 585{
17744ff6
TW		 586 struct ieee80211_hdr *header;
587 struct ieee80211_rx_status rx_status;
3d24a9f7 588 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 589 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
590 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
591 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 592 int snr;
b481de9c
ZY		 593 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
594 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 595 u8 network_packet;
17744ff6 596
17744ff6
TW		 597 rx_status.flag = 0;
598 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 599 rx_status.freq =
c0186078 600 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 601 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
602 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
603
604 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 605 if (rx_status.band == IEEE80211_BAND_5GHZ)
606 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 607
9024adf5 608 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) &
6f0a2c4d
BR		 609 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
610
611 /* set the preamble flag if appropriate */
612 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
613 rx_status.flag |= RX_FLAG_SHORTPRE;
614
b481de9c 615 if ((unlikely(rx_stats->phy_count > 20))) {
e1623446
TW		 616 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
617 rx_stats->phy_count);
b481de9c
ZY		 618 return;
619 }
620
621 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
622 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
e1623446 623 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
b481de9c
ZY		 624 return;
625 }
626
56decd3c 627
b481de9c
ZY		 628
629 /* Convert 3945's rssi indicator to dBm */
250bdd21 630 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 631
632 /* Set default noise value to -127 */
633 if (priv->last_rx_noise == 0)
634 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
635
636 /* 3945 provides noise info for OFDM frames only.
637 * sig_avg and noise_diff are measured by the 3945's digital signal
638 * processor (DSP), and indicate linear levels of signal level and
639 * distortion/noise within the packet preamble after
640 * automatic gain control (AGC). sig_avg should stay fairly
641 * constant if the radio's AGC is working well.
642 * Since these values are linear (not dB or dBm), linear
643 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
644 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
645 * to obtain noise level in dBm.
17744ff6 646 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 647 if (rx_stats_noise_diff) {
648 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 649 rx_status.noise = rx_status.signal -
17744ff6 650 iwl3945_calc_db_from_ratio(snr);
566bfe5a 651 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 652 rx_status.noise);
b481de9c
ZY		 653
654 /* If noise info not available, calculate signal quality indicator (%)
655 * using just the dBm signal level. */
656 } else {
17744ff6 657 rx_status.noise = priv->last_rx_noise;
566bfe5a 658 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 659 }
660
661
e1623446 662 IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 663 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 664 rx_stats_sig_avg, rx_stats_noise_diff);
665
b481de9c
ZY		 666 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
667
bb8c093b 668 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 669
e1623446 670 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
17744ff6
TW		 671 network_packet ? '*' : ' ',
672 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 673 rx_status.signal, rx_status.signal,
674 rx_status.noise, rx_status.rate_idx);
b481de9c 675
d08853a3
SO		 676 /* Set "1" to report good data frames in groups of 100 */
677 iwl3945_dbg_report_frame(priv, pkt, header, 1);
20594eb0 678 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
b481de9c
ZY		 679
680 if (network_packet) {
681 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
682 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 683 priv->last_rx_rssi = rx_status.signal;
17744ff6 684 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 685 }
686
12e5e22d 687 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 688}
689
7aaa1d79
SO		 690int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
691 struct iwl_tx_queue *txq,
692 dma_addr_t addr, u16 len, u8 reset, u8 pad)
b481de9c
ZY		 693{
694 int count;
7aaa1d79 695 struct iwl_queue *q;
59606ffa 696 struct iwl3945_tfd *tfd, *tfd_tmp;
7aaa1d79
SO		 697
698 q = &txq->q;
59606ffa
SO		 699 tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
700 tfd = &tfd_tmp[q->write_ptr];
7aaa1d79
SO		 701
702 if (reset)
703 memset(tfd, 0, sizeof(*tfd));
b481de9c
ZY		 704
705 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c
ZY		 706
707 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 708 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 709 NUM_TFD_CHUNKS);
710 return -EINVAL;
711 }
712
dbb6654c
WT		 713 tfd->tbs[count].addr = cpu_to_le32(addr);
714 tfd->tbs[count].len = cpu_to_le32(len);
b481de9c
ZY		 715
716 count++;
717
718 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
719 TFD_CTL_PAD_SET(pad));
720
721 return 0;
722}
723
724/**
bb8c093b 725 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 726 *
727 * Does NOT advance any indexes
728 */
7aaa1d79 729void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 730{
59606ffa 731 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
fd9377ee
RC		 732 int index = txq->q.read_ptr;
733 struct iwl3945_tfd *tfd = &tfd_tmp[index];
b481de9c
ZY		 734 struct pci_dev *dev = priv->pci_dev;
735 int i;
736 int counter;
737
b481de9c 738 /* sanity check */
dbb6654c 739 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
b481de9c 740 if (counter > NUM_TFD_CHUNKS) {
15b1687c 741 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c 742 /* @todo issue fatal error, it is quite serious situation */
7aaa1d79 743 return;
b481de9c
ZY		 744 }
745
fd9377ee
RC		 746 /* Unmap tx_cmd */
747 if (counter)
748 pci_unmap_single(dev,
c2acea8e
JB		 749 pci_unmap_addr(&txq->meta[index], mapping),
750 pci_unmap_len(&txq->meta[index], len),
fd9377ee
RC		 751 PCI_DMA_TODEVICE);
752
b481de9c
ZY		 753 /* unmap chunks if any */
754
755 for (i = 1; i < counter; i++) {
dbb6654c
WT		 756 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
757 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 758 if (txq->txb[txq->q.read_ptr].skb[0]) {
759 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
760 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 761 /* Can be called from interrupt context */
762 dev_kfree_skb_any(skb);
fc4b6853 763 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 764 }
765 }
766 }
7aaa1d79 767 return ;
b481de9c
ZY		 768}
769
b481de9c 770/**
bb8c093b 771 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 772 *
773*/
c2acea8e
JB		 774void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
775 struct iwl_device_cmd *cmd,
776 struct ieee80211_tx_info *info,
777 struct ieee80211_hdr *hdr,
778 int sta_id, int tx_id)
b481de9c 779{
e039fa4a 780 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 781 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 782 u16 rate_mask;
783 int rate;
784 u8 rts_retry_limit;
785 u8 data_retry_limit;
786 __le32 tx_flags;
fd7c8a40 787 __le16 fc = hdr->frame_control;
c2d79b48 788 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 789
bb8c093b 790 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 791 tx_flags = tx->tx_flags;
b481de9c
ZY		 792
793 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 794 * in this running context */
b481de9c
ZY		 795 rate_mask = IWL_RATES_MASK;
796
b481de9c
ZY		 797 if (tx_id >= IWL_CMD_QUEUE_NUM)
798 rts_retry_limit = 3;
799 else
800 rts_retry_limit = 7;
801
fd7c8a40 802 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 803 data_retry_limit = 3;
804 if (data_retry_limit < rts_retry_limit)
805 rts_retry_limit = data_retry_limit;
806 } else
807 data_retry_limit = IWL_DEFAULT_TX_RETRY;
808
809 if (priv->data_retry_limit != -1)
810 data_retry_limit = priv->data_retry_limit;
811
fd7c8a40
HH		 812 if (ieee80211_is_mgmt(fc)) {
813 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
814 case cpu_to_le16(IEEE80211_STYPE_AUTH):
815 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
816 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
817 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 818 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
819 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
820 tx_flags |= TX_CMD_FLG_CTS_MSK;
821 }
822 break;
823 default:
824 break;
825 }
826 }
827
c2d79b48
WT		 828 tx->rts_retry_limit = rts_retry_limit;
829 tx->data_retry_limit = data_retry_limit;
830 tx->rate = rate;
831 tx->tx_flags = tx_flags;
b481de9c
ZY		 832
833 /* OFDM */
c2d79b48 834 tx->supp_rates[0] =
14577f23 835 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 836
837 /* CCK */
c2d79b48 838 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c 839
e1623446 840 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
b481de9c 841 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 842 tx->rate, le32_to_cpu(tx->tx_flags),
843 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 844}
845
4a8a4322 846u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 847{
848 unsigned long flags_spin;
c587de0b 849 struct iwl_station_entry *station;
b481de9c
ZY		 850
851 if (sta_id == IWL_INVALID_STATION)
852 return IWL_INVALID_STATION;
853
854 spin_lock_irqsave(&priv->sta_lock, flags_spin);
c587de0b 855 station = &priv->stations[sta_id];
b481de9c
ZY		 856
857 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
858 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 859 station->sta.mode = STA_CONTROL_MODIFY_MSK;
860
861 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
862
c587de0b 863 iwl_send_add_sta(priv, &station->sta, flags);
e1623446 864 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
b481de9c
ZY		 865 sta_id, tx_rate);
866 return sta_id;
867}
868
854682ed 869static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
b481de9c 870{
854682ed 871 if (src == IWL_PWR_SRC_VAUX) {
3fdb68de 872 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
5d49f498 873 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 874 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
875 ~APMG_PS_CTRL_MSK_PWR_SRC);
b481de9c 876
5d49f498 877 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 878 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
879 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
3fdb68de 880 }
b481de9c 881 } else {
5d49f498 882 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 883 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
884 ~APMG_PS_CTRL_MSK_PWR_SRC);
885
5d49f498 886 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 887 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
888 }
b481de9c 889
a8b50a0a 890 return 0;
b481de9c
ZY		 891}
892
4a8a4322 893static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c 894{
5d49f498 895 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
8cd812bc 896 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
5d49f498
AK		 897 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
898 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 899 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
900 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
901 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
902 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
903 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
904 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
905 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
906 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 907
908 /* fake read to flush all prev I/O */
5d49f498 909 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 910
b481de9c
ZY		 911 return 0;
912}
913
4a8a4322 914static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c 915{
b481de9c
ZY		 916
917 /* bypass mode */
5d49f498 918 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 919
920 /* RA 0 is active */
5d49f498 921 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 922
923 /* all 6 fifo are active */
5d49f498 924 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 925
5d49f498
AK		 926 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
927 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
928 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
929 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 930
5d49f498 931 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 932 priv->shared_phys);
b481de9c 933
5d49f498 934 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 935 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
936 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
937 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
938 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
939 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
940 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
941 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 942
b481de9c
ZY		 943
944 return 0;
945}
946
947/**
948 * iwl3945_txq_ctx_reset - Reset TX queue context
949 *
950 * Destroys all DMA structures and initialize them again
951 */
4a8a4322 952static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 953{
954 int rc;
955 int txq_id, slots_num;
956
bb8c093b 957 iwl3945_hw_txq_ctx_free(priv);
b481de9c 958
88804e2b
WYG		 959 /* allocate tx queue structure */
960 rc = iwl_alloc_txq_mem(priv);
961 if (rc)
962 return rc;
963
b481de9c
ZY		 964 /* Tx CMD queue */
965 rc = iwl3945_tx_reset(priv);
966 if (rc)
967 goto error;
968
969 /* Tx queue(s) */
5905a1aa 970 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
b481de9c
ZY		 971 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
972 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
a8e74e27
SO		 973 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
974 txq_id);
b481de9c 975 if (rc) {
15b1687c 976 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 977 goto error;
978 }
979 }
980
981 return rc;
982
983 error:
bb8c093b 984 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 985 return rc;
986}
987
f33269b8
BC		 988/*
989 * Start up NIC's basic functionality after it has been reset
990 * (e.g. after platform boot, or shutdown via iwl3945_apm_stop())
991 * NOTE: This does not load uCode nor start the embedded processor
992 */
01ec616d 993static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 994{
a8b50a0a 995 int ret;
b481de9c 996
f33269b8
BC		 997 /* Configure chip clock phase-lock-loop */
998 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
999
1000 /*
1001 * Disable L0S exit timer (platform NMI Work/Around)
1002 * (does this do anything on 3945, or just 4965 and beyond?)
1003 */
5d49f498 1004 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1005 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1006
f33269b8 1007 /* Disable L0s without affecting L1; don't wait for ICH (L0s bug W/A) */
01ec616d
KA		 1008 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1009 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1010
f33269b8
BC		 1011 /* Set FH wait threshold to maximum (HW error during stress W/A) */
1012 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
1013
1014 /*
1015 * Set "initialization complete" bit to move adapter from
1016 * D0U* --> D0A* (powered-up active) state.
1017 */
5d49f498 1018 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d 1019
f33269b8
BC		 1020 /*
1021 * Wait for clock stabilization; once stabilized, access to
1022 * device-internal resources is supported, e.g. iwl_write_prph()
1023 * and accesses to uCode SRAM.
1024 */
1739d332
AK		 1025 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1026 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1027 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
01ec616d 1028 if (ret < 0) {
e1623446 1029 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
01ec616d 1030 goto out;
b481de9c
ZY		 1031 }
1032
f33269b8 1033 /* Enable DMA and BSM clocks, wait for them to stabilize */
01ec616d
KA		 1034 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1035 APMG_CLK_VAL_BSM_CLK_RQT);
b481de9c 1036 udelay(20);
01ec616d 1037
f33269b8
BC		 1038 /* Clear APMG (NIC's internal power management) interrupts */
1039 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1040 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF);
1041
1042 /* Reset radio chip */
1043 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1044 udelay(5);
1045 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
1046
1047 /* Disable L1-Active */
5d49f498 1048 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1049 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1050
01ec616d
KA		 1051out:
1052 return ret;
1053}
b481de9c 1054
01ec616d
KA		 1055static void iwl3945_nic_config(struct iwl_priv *priv)
1056{
e6148917 1057 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
01ec616d
KA		 1058 unsigned long flags;
1059 u8 rev_id = 0;
b481de9c 1060
b481de9c
ZY		 1061 spin_lock_irqsave(&priv->lock, flags);
1062
43121432
AK		 1063 /* Determine HW type */
1064 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1065
1066 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1067
b481de9c 1068 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
e1623446 1069 IWL_DEBUG_INFO(priv, "RTP type \n");
b481de9c 1070 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
e1623446 1071 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
5d49f498 1072 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1073 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1074 } else {
e1623446 1075 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
5d49f498 1076 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1077 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1078 }
1079
e6148917 1080 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
e1623446 1081 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
5d49f498 1082 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1083 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c 1084 } else
e1623446 1085 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
b481de9c 1086
e6148917 1087 if ((eeprom->board_revision & 0xF0) == 0xD0) {
e1623446 1088 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1089 eeprom->board_revision);
5d49f498 1090 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1091 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c 1092 } else {
e1623446 1093 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
e6148917 1094 eeprom->board_revision);
5d49f498 1095 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1096 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1097 }
1098
e6148917 1099 if (eeprom->almgor_m_version <= 1) {
5d49f498 1100 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1101 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
e1623446 1102 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
e6148917 1103 eeprom->almgor_m_version);
b481de9c 1104 } else {
e1623446 1105 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
e6148917 1106 eeprom->almgor_m_version);
5d49f498 1107 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1108 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1109 }
1110 spin_unlock_irqrestore(&priv->lock, flags);
1111
e6148917 1112 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
e1623446 1113 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
b481de9c 1114
e6148917 1115 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
e1623446 1116 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1117}
1118
1119int iwl3945_hw_nic_init(struct iwl_priv *priv)
1120{
01ec616d
KA		 1121 int rc;
1122 unsigned long flags;
1123 struct iwl_rx_queue *rxq = &priv->rxq;
1124
1125 spin_lock_irqsave(&priv->lock, flags);
1126 priv->cfg->ops->lib->apm_ops.init(priv);
1127 spin_unlock_irqrestore(&priv->lock, flags);
1128
854682ed 1129 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1e680233 1130 if (rc)
854682ed
KA		 1131 return rc;
1132
01ec616d 1133 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1134
1135 /* Allocate the RX queue, or reset if it is already allocated */
1136 if (!rxq->bd) {
51af3d3f 1137 rc = iwl_rx_queue_alloc(priv);
b481de9c 1138 if (rc) {
15b1687c 1139 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1140 return -ENOMEM;
1141 }
1142 } else
df833b1d 1143 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1144
bb8c093b 1145 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1146
1147 iwl3945_rx_init(priv, rxq);
1148
b481de9c
ZY		 1149
1150 /* Look at using this instead:
1151 rxq->need_update = 1;
141c43a3 1152 iwl_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1153 */
1154
5d49f498 1155 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
b481de9c
ZY		 1156
1157 rc = iwl3945_txq_ctx_reset(priv);
1158 if (rc)
1159 return rc;
1160
1161 set_bit(STATUS_INIT, &priv->status);
1162
1163 return 0;
1164}
1165
1166/**
bb8c093b 1167 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1168 *
1169 * Destroy all TX DMA queues and structures
1170 */
4a8a4322 1171void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1172{
1173 int txq_id;
1174
1175 /* Tx queues */
88804e2b
WYG		 1176 if (priv->txq)
1177 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
1178 txq_id++)
1179 if (txq_id == IWL_CMD_QUEUE_NUM)
1180 iwl_cmd_queue_free(priv);
1181 else
1182 iwl_tx_queue_free(priv, txq_id);
3e5d238f 1183
88804e2b
WYG		 1184 /* free tx queue structure */
1185 iwl_free_txq_mem(priv);
b481de9c
ZY		 1186}
1187
4a8a4322 1188void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1189{
bddadf86 1190 int txq_id;
b481de9c
ZY		 1191
1192 /* stop SCD */
5d49f498 1193 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1194
1195 /* reset TFD queues */
5905a1aa 1196 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
5d49f498
AK		 1197 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1198 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1199 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1200 1000);
1201 }
1202
bb8c093b 1203 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1204}
1205
b481de9c 1206/**
bb8c093b 1207 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1208 * return index delta into power gain settings table
1209*/
bb8c093b 1210static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1211{
1212 return (new_reading - old_reading) * (-11) / 100;
1213}
1214
1215/**
bb8c093b 1216 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1217 */
bb8c093b 1218static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1219{
3ac7f146 1220 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1221}
1222
4a8a4322 1223int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1224{
5d49f498 1225 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1226}
1227
1228/**
bb8c093b 1229 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1230 * get the current temperature by reading from NIC
1231*/
4a8a4322 1232static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c 1233{
e6148917 1234 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1235 int temperature;
1236
bb8c093b 1237 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1238
1239 /* driver's okay range is -260 to +25.
1240 * human readable okay range is 0 to +285 */
e1623446 1241 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
b481de9c
ZY		 1242
1243 /* handle insane temp reading */
bb8c093b 1244 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1245 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1246
1247 /* if really really hot(?),
1248 * substitute the 3rd band/group's temp measured at factory */
1249 if (priv->last_temperature > 100)
e6148917 1250 temperature = eeprom->groups[2].temperature;
b481de9c
ZY		 1251 else /* else use most recent "sane" value from driver */
1252 temperature = priv->last_temperature;
1253 }
1254
1255 return temperature; /* raw, not "human readable" */
1256}
1257
1258/* Adjust Txpower only if temperature variance is greater than threshold.
1259 *
1260 * Both are lower than older versions' 9 degrees */
1261#define IWL_TEMPERATURE_LIMIT_TIMER 6
1262
1263/**
1264 * is_temp_calib_needed - determines if new calibration is needed
1265 *
1266 * records new temperature in tx_mgr->temperature.
1267 * replaces tx_mgr->last_temperature *only* if calib needed
1268 * (assumes caller will actually do the calibration!). */
4a8a4322 1269static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1270{
1271 int temp_diff;
1272
bb8c093b 1273 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1274 temp_diff = priv->temperature - priv->last_temperature;
1275
1276 /* get absolute value */
1277 if (temp_diff < 0) {
e1623446 1278 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
b481de9c
ZY		 1279 temp_diff = -temp_diff;
1280 } else if (temp_diff == 0)
e1623446 1281 IWL_DEBUG_POWER(priv, "Same temp,\n");
b481de9c 1282 else
e1623446 1283 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
b481de9c
ZY		 1284
1285 /* if we don't need calibration, *don't* update last_temperature */
1286 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
e1623446 1287 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
b481de9c
ZY		 1288 return 0;
1289 }
1290
e1623446 1291 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
b481de9c
ZY		 1292
1293 /* assume that caller will actually do calib ...
1294 * update the "last temperature" value */
1295 priv->last_temperature = priv->temperature;
1296 return 1;
1297}
1298
1299#define IWL_MAX_GAIN_ENTRIES 78
1300#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1301#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1302
1303/* radio and DSP power table, each step is 1/2 dB.
1304 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1305static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1306 {
1307 {251, 127}, /* 2.4 GHz, highest power */
1308 {251, 127},
1309 {251, 127},
1310 {251, 127},
1311 {251, 125},
1312 {251, 110},
1313 {251, 105},
1314 {251, 98},
1315 {187, 125},
1316 {187, 115},
1317 {187, 108},
1318 {187, 99},
1319 {243, 119},
1320 {243, 111},
1321 {243, 105},
1322 {243, 97},
1323 {243, 92},
1324 {211, 106},
1325 {211, 100},
1326 {179, 120},
1327 {179, 113},
1328 {179, 107},
1329 {147, 125},
1330 {147, 119},
1331 {147, 112},
1332 {147, 106},
1333 {147, 101},
1334 {147, 97},
1335 {147, 91},
1336 {115, 107},
1337 {235, 121},
1338 {235, 115},
1339 {235, 109},
1340 {203, 127},
1341 {203, 121},
1342 {203, 115},
1343 {203, 108},
1344 {203, 102},
1345 {203, 96},
1346 {203, 92},
1347 {171, 110},
1348 {171, 104},
1349 {171, 98},
1350 {139, 116},
1351 {227, 125},
1352 {227, 119},
1353 {227, 113},
1354 {227, 107},
1355 {227, 101},
1356 {227, 96},
1357 {195, 113},
1358 {195, 106},
1359 {195, 102},
1360 {195, 95},
1361 {163, 113},
1362 {163, 106},
1363 {163, 102},
1364 {163, 95},
1365 {131, 113},
1366 {131, 106},
1367 {131, 102},
1368 {131, 95},
1369 {99, 113},
1370 {99, 106},
1371 {99, 102},
1372 {99, 95},
1373 {67, 113},
1374 {67, 106},
1375 {67, 102},
1376 {67, 95},
1377 {35, 113},
1378 {35, 106},
1379 {35, 102},
1380 {35, 95},
1381 {3, 113},
1382 {3, 106},
1383 {3, 102},
1384 {3, 95} }, /* 2.4 GHz, lowest power */
1385 {
1386 {251, 127}, /* 5.x GHz, highest power */
1387 {251, 120},
1388 {251, 114},
1389 {219, 119},
1390 {219, 101},
1391 {187, 113},
1392 {187, 102},
1393 {155, 114},
1394 {155, 103},
1395 {123, 117},
1396 {123, 107},
1397 {123, 99},
1398 {123, 92},
1399 {91, 108},
1400 {59, 125},
1401 {59, 118},
1402 {59, 109},
1403 {59, 102},
1404 {59, 96},
1405 {59, 90},
1406 {27, 104},
1407 {27, 98},
1408 {27, 92},
1409 {115, 118},
1410 {115, 111},
1411 {115, 104},
1412 {83, 126},
1413 {83, 121},
1414 {83, 113},
1415 {83, 105},
1416 {83, 99},
1417 {51, 118},
1418 {51, 111},
1419 {51, 104},
1420 {51, 98},
1421 {19, 116},
1422 {19, 109},
1423 {19, 102},
1424 {19, 98},
1425 {19, 93},
1426 {171, 113},
1427 {171, 107},
1428 {171, 99},
1429 {139, 120},
1430 {139, 113},
1431 {139, 107},
1432 {139, 99},
1433 {107, 120},
1434 {107, 113},
1435 {107, 107},
1436 {107, 99},
1437 {75, 120},
1438 {75, 113},
1439 {75, 107},
1440 {75, 99},
1441 {43, 120},
1442 {43, 113},
1443 {43, 107},
1444 {43, 99},
1445 {11, 120},
1446 {11, 113},
1447 {11, 107},
1448 {11, 99},
1449 {131, 107},
1450 {131, 99},
1451 {99, 120},
1452 {99, 113},
1453 {99, 107},
1454 {99, 99},
1455 {67, 120},
1456 {67, 113},
1457 {67, 107},
1458 {67, 99},
1459 {35, 120},
1460 {35, 113},
1461 {35, 107},
1462 {35, 99},
1463 {3, 120} } /* 5.x GHz, lowest power */
1464};
1465
bb8c093b 1466static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1467{
1468 if (index < 0)
1469 return 0;
1470 if (index >= IWL_MAX_GAIN_ENTRIES)
1471 return IWL_MAX_GAIN_ENTRIES - 1;
1472 return (u8) index;
1473}
1474
1475/* Kick off thermal recalibration check every 60 seconds */
1476#define REG_RECALIB_PERIOD (60)
1477
1478/**
bb8c093b 1479 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1480 *
1481 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1482 * or 6 Mbit (OFDM) rates.
1483 */
4a8a4322 1484static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1485 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1486 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1487 int band_index)
1488{
bb8c093b 1489 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1490 s8 power;
1491 u8 power_index;
1492
1493 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1494
1495 /* use this channel group's 6Mbit clipping/saturation pwr,
1496 * but cap at regulatory scan power restriction (set during init
1497 * based on eeprom channel data) for this channel. */
14577f23 1498 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1499
1500 /* further limit to user's max power preference.
1501 * FIXME: Other spectrum management power limitations do not
1502 * seem to apply?? */
62ea9c5b 1503 power = min(power, priv->tx_power_user_lmt);
b481de9c
ZY		 1504 scan_power_info->requested_power = power;
1505
1506 /* find difference between new scan *power* and current "normal"
1507 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1508 * current "normal" temperature-compensated Tx power *index* for
1509 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1510 * *index*. */
1511 power_index = ch_info->power_info[rate_index].power_table_index
1512 - (power - ch_info->power_info
14577f23 1513 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1514
1515 /* store reference index that we use when adjusting *all* scan
1516 * powers. So we can accommodate user (all channel) or spectrum
1517 * management (single channel) power changes "between" temperature
1518 * feedback compensation procedures.
1519 * don't force fit this reference index into gain table; it may be a
1520 * negative number. This will help avoid errors when we're at
1521 * the lower bounds (highest gains, for warmest temperatures)
1522 * of the table. */
1523
1524 /* don't exceed table bounds for "real" setting */
bb8c093b 1525 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1526
1527 scan_power_info->power_table_index = power_index;
1528 scan_power_info->tpc.tx_gain =
1529 power_gain_table[band_index][power_index].tx_gain;
1530 scan_power_info->tpc.dsp_atten =
1531 power_gain_table[band_index][power_index].dsp_atten;
1532}
1533
1534/**
75bcfae9 1535 * iwl3945_send_tx_power - fill in Tx Power command with gain settings
b481de9c
ZY		 1536 *
1537 * Configures power settings for all rates for the current channel,
1538 * using values from channel info struct, and send to NIC
1539 */
dfb39e82 1540static int iwl3945_send_tx_power(struct iwl_priv *priv)
b481de9c 1541{
14577f23 1542 int rate_idx, i;
d20b3c65 1543 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1544 struct iwl3945_txpowertable_cmd txpower = {
8ccde88a 1545 .channel = priv->active_rxon.channel,
b481de9c
ZY		 1546 };
1547
8318d78a 1548 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
e6148917 1549 ch_info = iwl_get_channel_info(priv,
8318d78a 1550 priv->band,
8ccde88a 1551 le16_to_cpu(priv->active_rxon.channel));
b481de9c 1552 if (!ch_info) {
15b1687c
WT		 1553 IWL_ERR(priv,
1554 "Failed to get channel info for channel %d [%d]\n",
8ccde88a 1555 le16_to_cpu(priv->active_rxon.channel), priv->band);
b481de9c
ZY		 1556 return -EINVAL;
1557 }
1558
1559 if (!is_channel_valid(ch_info)) {
e1623446 1560 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
b481de9c
ZY		 1561 "non-Tx channel.\n");
1562 return 0;
1563 }
1564
1565 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1566 /* Fill OFDM rate */
1567 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1568 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1569
1570 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1571 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c 1572
e1623446 1573 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
b481de9c
ZY		 1574 le16_to_cpu(txpower.channel),
1575 txpower.band,
14577f23
MA		 1576 txpower.power[i].tpc.tx_gain,
1577 txpower.power[i].tpc.dsp_atten,
1578 txpower.power[i].rate);
1579 }
1580 /* Fill CCK rates */
1581 for (rate_idx = IWL_FIRST_CCK_RATE;
1582 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1583 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1584 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23 1585
e1623446 1586 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
14577f23
MA		 1587 le16_to_cpu(txpower.channel),
1588 txpower.band,
1589 txpower.power[i].tpc.tx_gain,
1590 txpower.power[i].tpc.dsp_atten,
1591 txpower.power[i].rate);
b481de9c
ZY		 1592 }
1593
518099a8
SO		 1594 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1595 sizeof(struct iwl3945_txpowertable_cmd),
1596 &txpower);
b481de9c
ZY		 1597
1598}
1599
1600/**
bb8c093b 1601 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1602 * @ch_info: Channel to update. Uses power_info.requested_power.
1603 *
1604 * Replace requested_power and base_power_index ch_info fields for
1605 * one channel.
1606 *
1607 * Called if user or spectrum management changes power preferences.
1608 * Takes into account h/w and modulation limitations (clip power).
1609 *
1610 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1611 *
1612 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1613 * properly fill out the scan powers, and actual h/w gain settings,
1614 * and send changes to NIC
1615 */
4a8a4322 1616static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1617 struct iwl_channel_info *ch_info)
b481de9c 1618{
bb8c093b 1619 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1620 int power_changed = 0;
1621 int i;
1622 const s8 *clip_pwrs;
1623 int power;
1624
1625 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1626 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1627
1628 /* Get this channel's rate-to-current-power settings table */
1629 power_info = ch_info->power_info;
1630
1631 /* update OFDM Txpower settings */
14577f23 1632 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1633 i++, ++power_info) {
1634 int delta_idx;
1635
1636 /* limit new power to be no more than h/w capability */
1637 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1638 if (power == power_info->requested_power)
1639 continue;
1640
1641 /* find difference between old and new requested powers,
1642 * update base (non-temp-compensated) power index */
1643 delta_idx = (power - power_info->requested_power) * 2;
1644 power_info->base_power_index -= delta_idx;
1645
1646 /* save new requested power value */
1647 power_info->requested_power = power;
1648
1649 power_changed = 1;
1650 }
1651
1652 /* update CCK Txpower settings, based on OFDM 12M setting ...
1653 * ... all CCK power settings for a given channel are the *same*. */
1654 if (power_changed) {
1655 power =
14577f23 1656 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1657 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1658
bb8c093b 1659 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1660 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1661 power_info->requested_power = power;
1662 power_info->base_power_index =
14577f23 1663 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1664 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1665 ++power_info;
1666 }
1667 }
1668
1669 return 0;
1670}
1671
1672/**
bb8c093b 1673 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1674 *
1675 * NOTE: Returned power limit may be less (but not more) than requested,
1676 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1677 * (no consideration for h/w clipping limitations).
1678 */
d20b3c65 1679static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1680{
1681 s8 max_power;
1682
1683#if 0
1684 /* if we're using TGd limits, use lower of TGd or EEPROM */
1685 if (ch_info->tgd_data.max_power != 0)
1686 max_power = min(ch_info->tgd_data.max_power,
1687 ch_info->eeprom.max_power_avg);
1688
1689 /* else just use EEPROM limits */
1690 else
1691#endif
1692 max_power = ch_info->eeprom.max_power_avg;
1693
1694 return min(max_power, ch_info->max_power_avg);
1695}
1696
1697/**
bb8c093b 1698 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1699 *
1700 * Compensate txpower settings of *all* channels for temperature.
1701 * This only accounts for the difference between current temperature
1702 * and the factory calibration temperatures, and bases the new settings
1703 * on the channel's base_power_index.
1704 *
1705 * If RxOn is "associated", this sends the new Txpower to NIC!
1706 */
4a8a4322 1707static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1708{
d20b3c65 1709 struct iwl_channel_info *ch_info = NULL;
e6148917 1710 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 1711 int delta_index;
1712 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1713 u8 a_band;
1714 u8 rate_index;
1715 u8 scan_tbl_index;
1716 u8 i;
1717 int ref_temp;
1718 int temperature = priv->temperature;
1719
1720 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1721 for (i = 0; i < priv->channel_count; i++) {
1722 ch_info = &priv->channel_info[i];
1723 a_band = is_channel_a_band(ch_info);
1724
1725 /* Get this chnlgrp's factory calibration temperature */
e6148917 1726 ref_temp = (s16)eeprom->groups[ch_info->group_index].
b481de9c
ZY		 1727 temperature;
1728
a96a27f9 1729 /* get power index adjustment based on current and factory
b481de9c 1730 * temps */
bb8c093b 1731 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1732 ref_temp);
1733
1734 /* set tx power value for all rates, OFDM and CCK */
1735 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1736 rate_index++) {
1737 int power_idx =
1738 ch_info->power_info[rate_index].base_power_index;
1739
1740 /* temperature compensate */
1741 power_idx += delta_index;
1742
1743 /* stay within table range */
bb8c093b 1744 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1745 ch_info->power_info[rate_index].
1746 power_table_index = (u8) power_idx;
1747 ch_info->power_info[rate_index].tpc =
1748 power_gain_table[a_band][power_idx];
1749 }
1750
1751 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1752 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1753
1754 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1755 for (scan_tbl_index = 0;
1756 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1757 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1758 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1759 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1760 actual_index, clip_pwrs,
1761 ch_info, a_band);
1762 }
1763 }
1764
1765 /* send Txpower command for current channel to ucode */
75bcfae9 1766 return priv->cfg->ops->lib->send_tx_power(priv);
b481de9c
ZY		 1767}
1768
4a8a4322 1769int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1770{
d20b3c65 1771 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1772 s8 max_power;
1773 u8 a_band;
1774 u8 i;
1775
62ea9c5b 1776 if (priv->tx_power_user_lmt == power) {
e1623446 1777 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
b481de9c
ZY		 1778 "limit: %ddBm.\n", power);
1779 return 0;
1780 }
1781
e1623446 1782 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
62ea9c5b 1783 priv->tx_power_user_lmt = power;
b481de9c
ZY		 1784
1785 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1786
1787 for (i = 0; i < priv->channel_count; i++) {
1788 ch_info = &priv->channel_info[i];
1789 a_band = is_channel_a_band(ch_info);
1790
1791 /* find minimum power of all user and regulatory constraints
1792 * (does not consider h/w clipping limitations) */
bb8c093b 1793 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1794 max_power = min(power, max_power);
1795 if (max_power != ch_info->curr_txpow) {
1796 ch_info->curr_txpow = max_power;
1797
1798 /* this considers the h/w clipping limitations */
bb8c093b 1799 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1800 }
1801 }
1802
1803 /* update txpower settings for all channels,
1804 * send to NIC if associated. */
1805 is_temp_calib_needed(priv);
bb8c093b 1806 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1807
1808 return 0;
1809}
1810
5bbe233b
AK		 1811static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1812{
1813 int rc = 0;
1814 struct iwl_rx_packet *res = NULL;
1815 struct iwl3945_rxon_assoc_cmd rxon_assoc;
1816 struct iwl_host_cmd cmd = {
1817 .id = REPLY_RXON_ASSOC,
1818 .len = sizeof(rxon_assoc),
c2acea8e 1819 .flags = CMD_WANT_SKB,
5bbe233b
AK		 1820 .data = &rxon_assoc,
1821 };
1822 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1823 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1824
1825 if ((rxon1->flags == rxon2->flags) &&
1826 (rxon1->filter_flags == rxon2->filter_flags) &&
1827 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1828 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1829 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1830 return 0;
1831 }
1832
1833 rxon_assoc.flags = priv->staging_rxon.flags;
1834 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1835 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1836 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1837 rxon_assoc.reserved = 0;
1838
1839 rc = iwl_send_cmd_sync(priv, &cmd);
1840 if (rc)
1841 return rc;
1842
c2acea8e 1843 res = (struct iwl_rx_packet *)cmd.reply_skb->data;
5bbe233b
AK		 1844 if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1845 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1846 rc = -EIO;
1847 }
1848
1849 priv->alloc_rxb_skb--;
c2acea8e 1850 dev_kfree_skb_any(cmd.reply_skb);
5bbe233b
AK		 1851
1852 return rc;
1853}
1854
e0158e61
AK		 1855/**
1856 * iwl3945_commit_rxon - commit staging_rxon to hardware
1857 *
1858 * The RXON command in staging_rxon is committed to the hardware and
1859 * the active_rxon structure is updated with the new data. This
1860 * function correctly transitions out of the RXON_ASSOC_MSK state if
1861 * a HW tune is required based on the RXON structure changes.
1862 */
1863static int iwl3945_commit_rxon(struct iwl_priv *priv)
1864{
1865 /* cast away the const for active_rxon in this function */
1866 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1867 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1868 int rc = 0;
1869 bool new_assoc =
1870 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1871
1872 if (!iwl_is_alive(priv))
1873 return -1;
1874
1875 /* always get timestamp with Rx frame */
1876 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1877
1878 /* select antenna */
1879 staging_rxon->flags &=
1880 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1881 staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1882
1883 rc = iwl_check_rxon_cmd(priv);
1884 if (rc) {
1885 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
1886 return -EINVAL;
1887 }
1888
1889 /* If we don't need to send a full RXON, we can use
1890 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1891 * and other flags for the current radio configuration. */
1892 if (!iwl_full_rxon_required(priv)) {
1893 rc = iwl_send_rxon_assoc(priv);
1894 if (rc) {
1895 IWL_ERR(priv, "Error setting RXON_ASSOC "
1896 "configuration (%d).\n", rc);
1897 return rc;
1898 }
1899
1900 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1901
1902 return 0;
1903 }
1904
1905 /* If we are currently associated and the new config requires
1906 * an RXON_ASSOC and the new config wants the associated mask enabled,
1907 * we must clear the associated from the active configuration
1908 * before we apply the new config */
1909 if (iwl_is_associated(priv) && new_assoc) {
1910 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1911 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1912
1913 /*
1914 * reserved4 and 5 could have been filled by the iwlcore code.
1915 * Let's clear them before pushing to the 3945.
1916 */
1917 active_rxon->reserved4 = 0;
1918 active_rxon->reserved5 = 0;
1919 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1920 sizeof(struct iwl3945_rxon_cmd),
1921 &priv->active_rxon);
1922
1923 /* If the mask clearing failed then we set
1924 * active_rxon back to what it was previously */
1925 if (rc) {
1926 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1927 IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1928 "configuration (%d).\n", rc);
1929 return rc;
1930 }
1931 }
1932
1933 IWL_DEBUG_INFO(priv, "Sending RXON\n"
1934 "* with%s RXON_FILTER_ASSOC_MSK\n"
1935 "* channel = %d\n"
1936 "* bssid = %pM\n",
1937 (new_assoc ? "" : "out"),
1938 le16_to_cpu(staging_rxon->channel),
1939 staging_rxon->bssid_addr);
1940
1941 /*
1942 * reserved4 and 5 could have been filled by the iwlcore code.
1943 * Let's clear them before pushing to the 3945.
1944 */
1945 staging_rxon->reserved4 = 0;
1946 staging_rxon->reserved5 = 0;
1947
90e8e424 1948 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
e0158e61
AK		 1949
1950 /* Apply the new configuration */
1951 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1952 sizeof(struct iwl3945_rxon_cmd),
1953 staging_rxon);
1954 if (rc) {
1955 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1956 return rc;
1957 }
1958
1959 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1960
c587de0b 1961 iwl_clear_stations_table(priv);
e0158e61
AK		 1962
1963 /* If we issue a new RXON command which required a tune then we must
1964 * send a new TXPOWER command or we won't be able to Tx any frames */
1965 rc = priv->cfg->ops->lib->send_tx_power(priv);
1966 if (rc) {
1967 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1968 return rc;
1969 }
1970
1971 /* Add the broadcast address so we can send broadcast frames */
c587de0b 1972 if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
e0158e61
AK		 1973 IWL_INVALID_STATION) {
1974 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1975 return -EIO;
1976 }
1977
1978 /* If we have set the ASSOC_MSK and we are in BSS mode then
1979 * add the IWL_AP_ID to the station rate table */
1980 if (iwl_is_associated(priv) &&
1981 (priv->iw_mode == NL80211_IFTYPE_STATION))
c587de0b
TW		 1982 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1983 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
e0158e61
AK		 1984 IWL_ERR(priv, "Error adding AP address for transmit\n");
1985 return -EIO;
1986 }
1987
1988 /* Init the hardware's rate fallback order based on the band */
1989 rc = iwl3945_init_hw_rate_table(priv);
1990 if (rc) {
1991 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1992 return -EIO;
1993 }
1994
1995 return 0;
1996}
1997
b481de9c 1998/* will add 3945 channel switch cmd handling later */
4a8a4322 1999int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 2000{
2001 return 0;
2002}
2003
2004/**
2005 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
2006 *
2007 * -- reset periodic timer
2008 * -- see if temp has changed enough to warrant re-calibration ... if so:
2009 * -- correct coeffs for temp (can reset temp timer)
2010 * -- save this temp as "last",
2011 * -- send new set of gain settings to NIC
2012 * NOTE: This should continue working, even when we're not associated,
2013 * so we can keep our internal table of scan powers current. */
4a8a4322 2014void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 2015{
2016 /* This will kick in the "brute force"
bb8c093b 2017 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 2018 if (!is_temp_calib_needed(priv))
2019 goto reschedule;
2020
2021 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2022 * This is based *only* on current temperature,
2023 * ignoring any previous power measurements */
bb8c093b 2024 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2025
2026 reschedule:
2027 queue_delayed_work(priv->workqueue,
2028 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2029}
2030
416e1438 2031static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2032{
4a8a4322 2033 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2034 thermal_periodic.work);
2035
2036 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2037 return;
2038
2039 mutex_lock(&priv->mutex);
2040 iwl3945_reg_txpower_periodic(priv);
2041 mutex_unlock(&priv->mutex);
2042}
2043
2044/**
bb8c093b 2045 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2046 * for the channel.
2047 *
2048 * This function is used when initializing channel-info structs.
2049 *
2050 * NOTE: These channel groups do *NOT* match the bands above!
2051 * These channel groups are based on factory-tested channels;
2052 * on A-band, EEPROM's "group frequency" entries represent the top
2053 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2054 */
4a8a4322 2055static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2056 const struct iwl_channel_info *ch_info)
b481de9c 2057{
e6148917
SO		 2058 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2059 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
b481de9c
ZY		 2060 u8 group;
2061 u16 group_index = 0; /* based on factory calib frequencies */
2062 u8 grp_channel;
2063
2064 /* Find the group index for the channel ... don't use index 1(?) */
2065 if (is_channel_a_band(ch_info)) {
2066 for (group = 1; group < 5; group++) {
2067 grp_channel = ch_grp[group].group_channel;
2068 if (ch_info->channel <= grp_channel) {
2069 group_index = group;
2070 break;
2071 }
2072 }
2073 /* group 4 has a few channels *above* its factory cal freq */
2074 if (group == 5)
2075 group_index = 4;
2076 } else
2077 group_index = 0; /* 2.4 GHz, group 0 */
2078
e1623446 2079 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
b481de9c
ZY		 2080 group_index);
2081 return group_index;
2082}
2083
2084/**
bb8c093b 2085 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2086 *
2087 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2088 * into radio/DSP gain settings table for requested power.
2089 */
4a8a4322 2090static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2091 s8 requested_power,
2092 s32 setting_index, s32 *new_index)
2093{
bb8c093b 2094 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
e6148917 2095 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2096 s32 index0, index1;
2097 s32 power = 2 * requested_power;
2098 s32 i;
bb8c093b 2099 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2100 s32 gains0, gains1;
2101 s32 res;
2102 s32 denominator;
2103
e6148917 2104 chnl_grp = &eeprom->groups[setting_index];
b481de9c
ZY		 2105 samples = chnl_grp->samples;
2106 for (i = 0; i < 5; i++) {
2107 if (power == samples[i].power) {
2108 *new_index = samples[i].gain_index;
2109 return 0;
2110 }
2111 }
2112
2113 if (power > samples[1].power) {
2114 index0 = 0;
2115 index1 = 1;
2116 } else if (power > samples[2].power) {
2117 index0 = 1;
2118 index1 = 2;
2119 } else if (power > samples[3].power) {
2120 index0 = 2;
2121 index1 = 3;
2122 } else {
2123 index0 = 3;
2124 index1 = 4;
2125 }
2126
2127 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2128 if (denominator == 0)
2129 return -EINVAL;
2130 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2131 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2132 res = gains0 + (gains1 - gains0) *
2133 ((s32) power - (s32) samples[index0].power) / denominator +
2134 (1 << 18);
2135 *new_index = res >> 19;
2136 return 0;
2137}
2138
4a8a4322 2139static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2140{
2141 u32 i;
2142 s32 rate_index;
e6148917 2143 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
bb8c093b 2144 const struct iwl3945_eeprom_txpower_group *group;
b481de9c 2145
e1623446 2146 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
b481de9c
ZY		 2147
2148 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2149 s8 *clip_pwrs; /* table of power levels for each rate */
2150 s8 satur_pwr; /* saturation power for each chnl group */
e6148917 2151 group = &eeprom->groups[i];
b481de9c
ZY		 2152
2153 /* sanity check on factory saturation power value */
2154 if (group->saturation_power < 40) {
39aadf8c 2155 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2156 "less than minimum expected 40\n",
2157 group->saturation_power);
2158 return;
2159 }
2160
2161 /*
2162 * Derive requested power levels for each rate, based on
2163 * hardware capabilities (saturation power for band).
2164 * Basic value is 3dB down from saturation, with further
2165 * power reductions for highest 3 data rates. These
2166 * backoffs provide headroom for high rate modulation
2167 * power peaks, without too much distortion (clipping).
2168 */
2169 /* we'll fill in this array with h/w max power levels */
f2c7e521 2170 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2171
2172 /* divide factory saturation power by 2 to find -3dB level */
2173 satur_pwr = (s8) (group->saturation_power >> 1);
2174
2175 /* fill in channel group's nominal powers for each rate */
2176 for (rate_index = 0;
2177 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2178 switch (rate_index) {
14577f23 2179 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2180 if (i == 0) /* B/G */
2181 *clip_pwrs = satur_pwr;
2182 else /* A */
2183 *clip_pwrs = satur_pwr - 5;
2184 break;
14577f23 2185 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2186 if (i == 0)
2187 *clip_pwrs = satur_pwr - 7;
2188 else
2189 *clip_pwrs = satur_pwr - 10;
2190 break;
14577f23 2191 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2192 if (i == 0)
2193 *clip_pwrs = satur_pwr - 9;
2194 else
2195 *clip_pwrs = satur_pwr - 12;
2196 break;
2197 default:
2198 *clip_pwrs = satur_pwr;
2199 break;
2200 }
2201 }
2202 }
2203}
2204
2205/**
2206 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2207 *
2208 * Second pass (during init) to set up priv->channel_info
2209 *
2210 * Set up Tx-power settings in our channel info database for each VALID
2211 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2212 * and current temperature.
2213 *
2214 * Since this is based on current temperature (at init time), these values may
2215 * not be valid for very long, but it gives us a starting/default point,
2216 * and allows us to active (i.e. using Tx) scan.
2217 *
2218 * This does *not* write values to NIC, just sets up our internal table.
2219 */
4a8a4322 2220int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2221{
d20b3c65 2222 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2223 struct iwl3945_channel_power_info *pwr_info;
e6148917 2224 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
b481de9c
ZY		 2225 int delta_index;
2226 u8 rate_index;
2227 u8 scan_tbl_index;
2228 const s8 *clip_pwrs; /* array of power levels for each rate */
2229 u8 gain, dsp_atten;
2230 s8 power;
2231 u8 pwr_index, base_pwr_index, a_band;
2232 u8 i;
2233 int temperature;
2234
2235 /* save temperature reference,
2236 * so we can determine next time to calibrate */
bb8c093b 2237 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2238 priv->last_temperature = temperature;
2239
bb8c093b 2240 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2241
2242 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2243 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2244 i++, ch_info++) {
2245 a_band = is_channel_a_band(ch_info);
2246 if (!is_channel_valid(ch_info))
2247 continue;
2248
2249 /* find this channel's channel group (*not* "band") index */
2250 ch_info->group_index =
bb8c093b 2251 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2252
2253 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2254 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2255
2256 /* calculate power index *adjustment* value according to
2257 * diff between current temperature and factory temperature */
bb8c093b 2258 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
e6148917 2259 eeprom->groups[ch_info->group_index].
b481de9c
ZY		 2260 temperature);
2261
e1623446 2262 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
b481de9c
ZY		 2263 ch_info->channel, delta_index, temperature +
2264 IWL_TEMP_CONVERT);
2265
2266 /* set tx power value for all OFDM rates */
2267 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2268 rate_index++) {
25a4ccea 2269 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2270 int rc;
2271
2272 /* use channel group's clip-power table,
2273 * but don't exceed channel's max power */
2274 s8 pwr = min(ch_info->max_power_avg,
2275 clip_pwrs[rate_index]);
2276
2277 pwr_info = &ch_info->power_info[rate_index];
2278
2279 /* get base (i.e. at factory-measured temperature)
2280 * power table index for this rate's power */
bb8c093b 2281 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2282 ch_info->group_index,
2283 &power_idx);
2284 if (rc) {
15b1687c 2285 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2286 return rc;
2287 }
2288 pwr_info->base_power_index = (u8) power_idx;
2289
2290 /* temperature compensate */
2291 power_idx += delta_index;
2292
2293 /* stay within range of gain table */
bb8c093b 2294 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2295
bb8c093b 2296 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2297 pwr_info->requested_power = pwr;
2298 pwr_info->power_table_index = (u8) power_idx;
2299 pwr_info->tpc.tx_gain =
2300 power_gain_table[a_band][power_idx].tx_gain;
2301 pwr_info->tpc.dsp_atten =
2302 power_gain_table[a_band][power_idx].dsp_atten;
2303 }
2304
2305 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2306 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2307 power = pwr_info->requested_power +
2308 IWL_CCK_FROM_OFDM_POWER_DIFF;
2309 pwr_index = pwr_info->power_table_index +
2310 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2311 base_pwr_index = pwr_info->base_power_index +
2312 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2313
2314 /* stay within table range */
bb8c093b 2315 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2316 gain = power_gain_table[a_band][pwr_index].tx_gain;
2317 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2318
bb8c093b 2319 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2320 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2321 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2322 for (rate_index = 0;
2323 rate_index < IWL_CCK_RATES; rate_index++) {
2324 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2325 pwr_info->requested_power = power;
2326 pwr_info->power_table_index = pwr_index;
2327 pwr_info->base_power_index = base_pwr_index;
2328 pwr_info->tpc.tx_gain = gain;
2329 pwr_info->tpc.dsp_atten = dsp_atten;
2330 }
2331
2332 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2333 for (scan_tbl_index = 0;
2334 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2335 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2336 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2337 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2338 actual_index, clip_pwrs, ch_info, a_band);
2339 }
2340 }
2341
2342 return 0;
2343}
2344
4a8a4322 2345int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2346{
2347 int rc;
b481de9c 2348
5d49f498
AK		 2349 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2350 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2351 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2352 if (rc < 0)
15b1687c 2353 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2354
b481de9c
ZY		 2355 return 0;
2356}
2357
188cf6c7 2358int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
b481de9c 2359{
b481de9c
ZY		 2360 int txq_id = txq->q.id;
2361
3832ec9d 2362 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2363
2364 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2365
5d49f498
AK		 2366 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2367 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2368
5d49f498 2369 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2370 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2371 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2372 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2373 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2374 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
b481de9c
ZY		 2375
2376 /* fake read to flush all prev. writes */
5d49f498 2377 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2378
2379 return 0;
2380}
2381
42427b4e
KA		 2382/*
2383 * HCMD utils
2384 */
2385static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2386{
2387 switch (cmd_id) {
2388 case REPLY_RXON:
d25aabb0
WT		 2389 return sizeof(struct iwl3945_rxon_cmd);
2390 case POWER_TABLE_CMD:
2391 return sizeof(struct iwl3945_powertable_cmd);
42427b4e
KA		 2392 default:
2393 return len;
2394 }
2395}
2396
c587de0b 2397
17f841cd
SO		 2398static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2399{
c587de0b
TW		 2400 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2401 addsta->mode = cmd->mode;
2402 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2403 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2404 addsta->station_flags = cmd->station_flags;
2405 addsta->station_flags_msk = cmd->station_flags_msk;
2406 addsta->tid_disable_tx = cpu_to_le16(0);
2407 addsta->rate_n_flags = cmd->rate_n_flags;
2408 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2409 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2410 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2411
2412 return (u16)sizeof(struct iwl3945_addsta_cmd);
17f841cd
SO		 2413}
2414
c587de0b 2415
b481de9c
ZY		 2416/**
2417 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2418 */
4a8a4322 2419int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2420{
14577f23 2421 int rc, i, index, prev_index;
bb8c093b 2422 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2423 .reserved = {0, 0, 0},
2424 };
bb8c093b 2425 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2426
bb8c093b
CH		 2427 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2428 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2429
2430 table[index].rate_n_flags =
bb8c093b 2431 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2432 table[index].try_cnt = priv->retry_rate;
bb8c093b 2433 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2434 table[index].next_rate_index =
2435 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2436 }
2437
8318d78a
JB		 2438 switch (priv->band) {
2439 case IEEE80211_BAND_5GHZ:
e1623446 2440 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
b481de9c
ZY		 2441 /* If one of the following CCK rates is used,
2442 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2443 for (i = IWL_RATE_1M_INDEX_TABLE;
2444 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2445 table[i].next_rate_index =
2446 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2447
2448 /* Don't fall back to CCK rates */
7262796a
AM		 2449 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2450 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2451
2452 /* Don't drop out of OFDM rates */
14577f23 2453 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2454 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2455 break;
2456
8318d78a 2457 case IEEE80211_BAND_2GHZ:
e1623446 2458 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
b481de9c
ZY		 2459 /* If an OFDM rate is used, have it fall back to the
2460 * 1M CCK rates */
b481de9c 2461
7262796a 2462 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
8ccde88a 2463 iwl_is_associated(priv)) {
7262796a
AM		 2464
2465 index = IWL_FIRST_CCK_RATE;
2466 for (i = IWL_RATE_6M_INDEX_TABLE;
2467 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2468 table[i].next_rate_index =
2469 iwl3945_rates[index].table_rs_index;
2470
2471 index = IWL_RATE_11M_INDEX_TABLE;
2472 /* CCK shouldn't fall back to OFDM... */
2473 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2474 }
b481de9c
ZY		 2475 break;
2476
2477 default:
8318d78a 2478 WARN_ON(1);
b481de9c
ZY		 2479 break;
2480 }
2481
2482 /* Update the rate scaling for control frame Tx */
2483 rate_cmd.table_id = 0;
518099a8 2484 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2485 &rate_cmd);
2486 if (rc)
2487 return rc;
2488
2489 /* Update the rate scaling for data frame Tx */
2490 rate_cmd.table_id = 1;
518099a8 2491 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2492 &rate_cmd);
2493}
2494
796083cb 2495/* Called when initializing driver */
4a8a4322 2496int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2497{
3832ec9d
AK		 2498 memset((void *)&priv->hw_params, 0,
2499 sizeof(struct iwl_hw_params));
b481de9c 2500
3832ec9d 2501 priv->shared_virt =
b481de9c 2502 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2503 sizeof(struct iwl3945_shared),
3832ec9d 2504 &priv->shared_phys);
b481de9c 2505
3832ec9d 2506 if (!priv->shared_virt) {
15b1687c 2507 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2508 mutex_unlock(&priv->mutex);
2509 return -ENOMEM;
2510 }
2511
21c02a1a 2512 /* Assign number of Usable TX queues */
88804e2b 2513 priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
21c02a1a 2514
a8e74e27 2515 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
1e33dc64 2516 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
3832ec9d
AK		 2517 priv->hw_params.max_pkt_size = 2342;
2518 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2519 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2520 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2521 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2522
141c43a3 2523 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2c2f3b33 2524 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
141c43a3 2525
b481de9c
ZY		 2526 return 0;
2527}
2528
4a8a4322 2529unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2530 struct iwl3945_frame *frame, u8 rate)
b481de9c 2531{
bb8c093b 2532 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2533 unsigned int frame_size;
2534
bb8c093b 2535 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2536 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2537
3832ec9d 2538 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2539 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2540
bb8c093b 2541 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2542 tx_beacon_cmd->frame,
b481de9c
ZY		 2543 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2544
2545 BUG_ON(frame_size > MAX_MPDU_SIZE);
2546 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2547
2548 tx_beacon_cmd->tx.rate = rate;
2549 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2550 TX_CMD_FLG_TSF_MSK);
2551
14577f23
MA		 2552 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2553 tx_beacon_cmd->tx.supp_rates[0] =
2554 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2555
b481de9c 2556 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2557 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2558
3ac7f146 2559 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2560}
2561
4a8a4322 2562void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2563{
91c066f2 2564 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2565 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2566}
2567
4a8a4322 2568void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2569{
2570 INIT_DELAYED_WORK(&priv->thermal_periodic,
2571 iwl3945_bg_reg_txpower_periodic);
2572}
2573
4a8a4322 2574void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2575{
2576 cancel_delayed_work(&priv->thermal_periodic);
2577}
2578
0164b9b4
KA		 2579/* check contents of special bootstrap uCode SRAM */
2580static int iwl3945_verify_bsm(struct iwl_priv *priv)
2581 {
2582 __le32 *image = priv->ucode_boot.v_addr;
2583 u32 len = priv->ucode_boot.len;
2584 u32 reg;
2585 u32 val;
2586
e1623446 2587 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
0164b9b4
KA		 2588
2589 /* verify BSM SRAM contents */
2590 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2591 for (reg = BSM_SRAM_LOWER_BOUND;
2592 reg < BSM_SRAM_LOWER_BOUND + len;
2593 reg += sizeof(u32), image++) {
2594 val = iwl_read_prph(priv, reg);
2595 if (val != le32_to_cpu(*image)) {
2596 IWL_ERR(priv, "BSM uCode verification failed at "
2597 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2598 BSM_SRAM_LOWER_BOUND,
2599 reg - BSM_SRAM_LOWER_BOUND, len,
2600 val, le32_to_cpu(*image));
2601 return -EIO;
2602 }
2603 }
2604
e1623446 2605 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
0164b9b4
KA		 2606
2607 return 0;
2608}
2609
e6148917
SO		 2610
2611/******************************************************************************
2612 *
2613 * EEPROM related functions
2614 *
2615 ******************************************************************************/
2616
2617/*
2618 * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2619 * embedded controller) as EEPROM reader; each read is a series of pulses
2620 * to/from the EEPROM chip, not a single event, so even reads could conflict
2621 * if they weren't arbitrated by some ownership mechanism. Here, the driver
2622 * simply claims ownership, which should be safe when this function is called
2623 * (i.e. before loading uCode!).
2624 */
2625static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2626{
2627 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2628 return 0;
2629}
2630
2631
2632static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2633{
2634 return;
2635}
2636
0164b9b4
KA		 2637 /**
2638 * iwl3945_load_bsm - Load bootstrap instructions
2639 *
2640 * BSM operation:
2641 *
2642 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2643 * in special SRAM that does not power down during RFKILL. When powering back
2644 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2645 * the bootstrap program into the on-board processor, and starts it.
2646 *
2647 * The bootstrap program loads (via DMA) instructions and data for a new
2648 * program from host DRAM locations indicated by the host driver in the
2649 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2650 * automatically.
2651 *
2652 * When initializing the NIC, the host driver points the BSM to the
2653 * "initialize" uCode image. This uCode sets up some internal data, then
2654 * notifies host via "initialize alive" that it is complete.
2655 *
2656 * The host then replaces the BSM_DRAM_* pointer values to point to the
2657 * normal runtime uCode instructions and a backup uCode data cache buffer
2658 * (filled initially with starting data values for the on-board processor),
2659 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2660 * which begins normal operation.
2661 *
2662 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2663 * the backup data cache in DRAM before SRAM is powered down.
2664 *
2665 * When powering back up, the BSM loads the bootstrap program. This reloads
2666 * the runtime uCode instructions and the backup data cache into SRAM,
2667 * and re-launches the runtime uCode from where it left off.
2668 */
2669static int iwl3945_load_bsm(struct iwl_priv *priv)
2670{
2671 __le32 *image = priv->ucode_boot.v_addr;
2672 u32 len = priv->ucode_boot.len;
2673 dma_addr_t pinst;
2674 dma_addr_t pdata;
2675 u32 inst_len;
2676 u32 data_len;
2677 int rc;
2678 int i;
2679 u32 done;
2680 u32 reg_offset;
2681
e1623446 2682 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
0164b9b4
KA		 2683
2684 /* make sure bootstrap program is no larger than BSM's SRAM size */
2685 if (len > IWL39_MAX_BSM_SIZE)
2686 return -EINVAL;
2687
2688 /* Tell bootstrap uCode where to find the "Initialize" uCode
2689 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2690 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2691 * after the "initialize" uCode has run, to point to
2692 * runtime/protocol instructions and backup data cache. */
2693 pinst = priv->ucode_init.p_addr;
2694 pdata = priv->ucode_init_data.p_addr;
2695 inst_len = priv->ucode_init.len;
2696 data_len = priv->ucode_init_data.len;
2697
0164b9b4
KA		 2698 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2699 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2700 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2701 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2702
2703 /* Fill BSM memory with bootstrap instructions */
2704 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2705 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2706 reg_offset += sizeof(u32), image++)
2707 _iwl_write_prph(priv, reg_offset,
2708 le32_to_cpu(*image));
2709
2710 rc = iwl3945_verify_bsm(priv);
a8b50a0a 2711 if (rc)
0164b9b4 2712 return rc;
0164b9b4
KA		 2713
2714 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2715 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2716 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2717 IWL39_RTC_INST_LOWER_BOUND);
2718 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2719
2720 /* Load bootstrap code into instruction SRAM now,
2721 * to prepare to load "initialize" uCode */
2722 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2723 BSM_WR_CTRL_REG_BIT_START);
2724
2725 /* Wait for load of bootstrap uCode to finish */
2726 for (i = 0; i < 100; i++) {
2727 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2728 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2729 break;
2730 udelay(10);
2731 }
2732 if (i < 100)
e1623446 2733 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
0164b9b4
KA		 2734 else {
2735 IWL_ERR(priv, "BSM write did not complete!\n");
2736 return -EIO;
2737 }
2738
2739 /* Enable future boot loads whenever power management unit triggers it
2740 * (e.g. when powering back up after power-save shutdown) */
2741 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2742 BSM_WR_CTRL_REG_BIT_START_EN);
2743
0164b9b4
KA		 2744 return 0;
2745}
2746
cc0f555d
JS		 2747#define IWL3945_UCODE_GET(item) \
2748static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2749 u32 api_ver) \
2750{ \
2751 return le32_to_cpu(ucode->u.v1.item); \
2752}
2753
2754static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2755{
2756 return UCODE_HEADER_SIZE(1);
2757}
2758static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2759 u32 api_ver)
2760{
2761 return 0;
2762}
2763static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2764 u32 api_ver)
2765{
2766 return (u8 *) ucode->u.v1.data;
2767}
2768
2769IWL3945_UCODE_GET(inst_size);
2770IWL3945_UCODE_GET(data_size);
2771IWL3945_UCODE_GET(init_size);
2772IWL3945_UCODE_GET(init_data_size);
2773IWL3945_UCODE_GET(boot_size);
2774
5bbe233b
AK		 2775static struct iwl_hcmd_ops iwl3945_hcmd = {
2776 .rxon_assoc = iwl3945_send_rxon_assoc,
e0158e61 2777 .commit_rxon = iwl3945_commit_rxon,
5bbe233b
AK		 2778};
2779
cc0f555d
JS		 2780static struct iwl_ucode_ops iwl3945_ucode = {
2781 .get_header_size = iwl3945_ucode_get_header_size,
2782 .get_build = iwl3945_ucode_get_build,
2783 .get_inst_size = iwl3945_ucode_get_inst_size,
2784 .get_data_size = iwl3945_ucode_get_data_size,
2785 .get_init_size = iwl3945_ucode_get_init_size,
2786 .get_init_data_size = iwl3945_ucode_get_init_data_size,
2787 .get_boot_size = iwl3945_ucode_get_boot_size,
2788 .get_data = iwl3945_ucode_get_data,
2789};
2790
0164b9b4 2791static struct iwl_lib_ops iwl3945_lib = {
7aaa1d79
SO		 2792 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2793 .txq_free_tfd = iwl3945_hw_txq_free_tfd,
a8e74e27 2794 .txq_init = iwl3945_hw_tx_queue_init,
0164b9b4 2795 .load_ucode = iwl3945_load_bsm,
b7a79404
RC		 2796 .dump_nic_event_log = iwl3945_dump_nic_event_log,
2797 .dump_nic_error_log = iwl3945_dump_nic_error_log,
01ec616d
KA		 2798 .apm_ops = {
2799 .init = iwl3945_apm_init,
d68b603c 2800 .stop = iwl_apm_stop,
01ec616d 2801 .config = iwl3945_nic_config,
854682ed 2802 .set_pwr_src = iwl3945_set_pwr_src,
01ec616d 2803 },
e6148917
SO		 2804 .eeprom_ops = {
2805 .regulatory_bands = {
2806 EEPROM_REGULATORY_BAND_1_CHANNELS,
2807 EEPROM_REGULATORY_BAND_2_CHANNELS,
2808 EEPROM_REGULATORY_BAND_3_CHANNELS,
2809 EEPROM_REGULATORY_BAND_4_CHANNELS,
2810 EEPROM_REGULATORY_BAND_5_CHANNELS,
7aafef1c
WYG		 2811 EEPROM_REGULATORY_BAND_NO_HT40,
2812 EEPROM_REGULATORY_BAND_NO_HT40,
e6148917
SO		 2813 },
2814 .verify_signature = iwlcore_eeprom_verify_signature,
2815 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2816 .release_semaphore = iwl3945_eeprom_release_semaphore,
2817 .query_addr = iwlcore_eeprom_query_addr,
2818 },
75bcfae9 2819 .send_tx_power = iwl3945_send_tx_power,
c2436980 2820 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
5bbe233b 2821 .post_associate = iwl3945_post_associate,
ef850d7c 2822 .isr = iwl_isr_legacy,
60690a6a 2823 .config_ap = iwl3945_config_ap,
0164b9b4
KA		 2824};
2825
42427b4e
KA		 2826static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2827 .get_hcmd_size = iwl3945_get_hcmd_size,
17f841cd 2828 .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
37dc70fe 2829 .rts_tx_cmd_flag = iwlcore_rts_tx_cmd_flag,
42427b4e
KA		 2830};
2831
0164b9b4 2832static struct iwl_ops iwl3945_ops = {
cc0f555d 2833 .ucode = &iwl3945_ucode,
0164b9b4 2834 .lib = &iwl3945_lib,
5bbe233b 2835 .hcmd = &iwl3945_hcmd,
42427b4e 2836 .utils = &iwl3945_hcmd_utils,
e932a609 2837 .led = &iwl3945_led_ops,
0164b9b4
KA		 2838};
2839
c0f20d91 2840static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2841 .name = "3945BG",
a0987a8d
RC		 2842 .fw_name_pre = IWL3945_FW_PRE,
2843 .ucode_api_max = IWL3945_UCODE_API_MAX,
2844 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2845 .sku = IWL_SKU_G,
e6148917
SO		 2846 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2847 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2848 .ops = &iwl3945_ops,
88804e2b 2849 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2850 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2851 .use_isr_legacy = true,
2852 .ht_greenfield_support = false,
f2d0d0e2 2853 .led_compensation = 64,
82b9a121
TW		 2854};
2855
c0f20d91 2856static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2857 .name = "3945ABG",
a0987a8d
RC		 2858 .fw_name_pre = IWL3945_FW_PRE,
2859 .ucode_api_max = IWL3945_UCODE_API_MAX,
2860 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2861 .sku = IWL_SKU_A|IWL_SKU_G,
e6148917
SO		 2862 .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2863 .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
0164b9b4 2864 .ops = &iwl3945_ops,
88804e2b 2865 .num_of_queues = IWL39_NUM_QUEUES,
ef850d7c 2866 .mod_params = &iwl3945_mod_params,
b261793d
DH		 2867 .use_isr_legacy = true,
2868 .ht_greenfield_support = false,
f2d0d0e2 2869 .led_compensation = 64,
82b9a121
TW		 2870};
2871
bb8c093b 2872struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2873 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2874 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2875 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2876 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2877 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2878 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2879 {0}
2880};
2881
bb8c093b 2882MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree