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iwl3945: add apm ops
[net-next-2.6.git] / drivers / net / wireless / iwlwifi / iwl-3945.c
CommitLineData
b481de9c
ZY		 1/******************************************************************************
2 *
eb7ae89c 3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
b481de9c
ZY		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
759ef89f 22 * Intel Linux Wireless <ilw@linux.intel.com>
b481de9c
ZY		 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27#include <linux/kernel.h>
28#include <linux/module.h>
b481de9c
ZY		 29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/delay.h>
33#include <linux/skbuff.h>
34#include <linux/netdevice.h>
35#include <linux/wireless.h>
36#include <linux/firmware.h>
b481de9c 37#include <linux/etherdevice.h>
12342c47
ZY		 38#include <asm/unaligned.h>
39#include <net/mac80211.h>
b481de9c 40
bddadf86 41#include "iwl-3945-fh.h"
600c0e11 42#include "iwl-commands.h"
b481de9c 43#include "iwl-3945.h"
5d08cd1d 44#include "iwl-helpers.h"
5747d47f 45#include "iwl-core.h"
d9829a67 46#include "iwl-agn-rs.h"
b481de9c
ZY		 47
48#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \
49 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
50 IWL_RATE_##r##M_IEEE, \
51 IWL_RATE_##ip##M_INDEX, \
52 IWL_RATE_##in##M_INDEX, \
53 IWL_RATE_##rp##M_INDEX, \
54 IWL_RATE_##rn##M_INDEX, \
55 IWL_RATE_##pp##M_INDEX, \
14577f23
MA		 56 IWL_RATE_##np##M_INDEX, \
57 IWL_RATE_##r##M_INDEX_TABLE, \
58 IWL_RATE_##ip##M_INDEX_TABLE }
b481de9c
ZY		 59
60/*
61 * Parameter order:
62 * rate, prev rate, next rate, prev tgg rate, next tgg rate
63 *
64 * If there isn't a valid next or previous rate then INV is used which
65 * maps to IWL_RATE_INVALID
66 *
67 */
d9829a67 68const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
14577f23
MA		 69 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */
70 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */
71 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */
72 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */
b481de9c
ZY		 73 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */
74 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */
75 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */
76 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */
77 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */
78 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */
79 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */
80 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
b481de9c
ZY		 81};
82
bb8c093b 83/* 1 = enable the iwl3945_disable_events() function */
b481de9c
ZY		 84#define IWL_EVT_DISABLE (0)
85#define IWL_EVT_DISABLE_SIZE (1532/32)
86
87/**
bb8c093b 88 * iwl3945_disable_events - Disable selected events in uCode event log
b481de9c
ZY		 89 *
90 * Disable an event by writing "1"s into "disable"
91 * bitmap in SRAM. Bit position corresponds to Event # (id/type).
92 * Default values of 0 enable uCode events to be logged.
93 * Use for only special debugging. This function is just a placeholder as-is,
94 * you'll need to provide the special bits! ...
95 * ... and set IWL_EVT_DISABLE to 1. */
4a8a4322 96void iwl3945_disable_events(struct iwl_priv *priv)
b481de9c 97{
af7cca2a 98 int ret;
b481de9c
ZY		 99 int i;
100 u32 base; /* SRAM address of event log header */
101 u32 disable_ptr; /* SRAM address of event-disable bitmap array */
102 u32 array_size; /* # of u32 entries in array */
103 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
104 0x00000000, /* 31 - 0 Event id numbers */
105 0x00000000, /* 63 - 32 */
106 0x00000000, /* 95 - 64 */
107 0x00000000, /* 127 - 96 */
108 0x00000000, /* 159 - 128 */
109 0x00000000, /* 191 - 160 */
110 0x00000000, /* 223 - 192 */
111 0x00000000, /* 255 - 224 */
112 0x00000000, /* 287 - 256 */
113 0x00000000, /* 319 - 288 */
114 0x00000000, /* 351 - 320 */
115 0x00000000, /* 383 - 352 */
116 0x00000000, /* 415 - 384 */
117 0x00000000, /* 447 - 416 */
118 0x00000000, /* 479 - 448 */
119 0x00000000, /* 511 - 480 */
120 0x00000000, /* 543 - 512 */
121 0x00000000, /* 575 - 544 */
122 0x00000000, /* 607 - 576 */
123 0x00000000, /* 639 - 608 */
124 0x00000000, /* 671 - 640 */
125 0x00000000, /* 703 - 672 */
126 0x00000000, /* 735 - 704 */
127 0x00000000, /* 767 - 736 */
128 0x00000000, /* 799 - 768 */
129 0x00000000, /* 831 - 800 */
130 0x00000000, /* 863 - 832 */
131 0x00000000, /* 895 - 864 */
132 0x00000000, /* 927 - 896 */
133 0x00000000, /* 959 - 928 */
134 0x00000000, /* 991 - 960 */
135 0x00000000, /* 1023 - 992 */
136 0x00000000, /* 1055 - 1024 */
137 0x00000000, /* 1087 - 1056 */
138 0x00000000, /* 1119 - 1088 */
139 0x00000000, /* 1151 - 1120 */
140 0x00000000, /* 1183 - 1152 */
141 0x00000000, /* 1215 - 1184 */
142 0x00000000, /* 1247 - 1216 */
143 0x00000000, /* 1279 - 1248 */
144 0x00000000, /* 1311 - 1280 */
145 0x00000000, /* 1343 - 1312 */
146 0x00000000, /* 1375 - 1344 */
147 0x00000000, /* 1407 - 1376 */
148 0x00000000, /* 1439 - 1408 */
149 0x00000000, /* 1471 - 1440 */
150 0x00000000, /* 1503 - 1472 */
151 };
152
153 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
bb8c093b 154 if (!iwl3945_hw_valid_rtc_data_addr(base)) {
15b1687c 155 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
b481de9c
ZY		 156 return;
157 }
158
5d49f498 159 ret = iwl_grab_nic_access(priv);
af7cca2a 160 if (ret) {
39aadf8c 161 IWL_WARN(priv, "Can not read from adapter at this time.\n");
b481de9c
ZY		 162 return;
163 }
164
5d49f498
AK		 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
167 iwl_release_nic_access(priv);
b481de9c
ZY		 168
169 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
170 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
171 disable_ptr);
5d49f498 172 ret = iwl_grab_nic_access(priv);
b481de9c 173 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
5d49f498 174 iwl_write_targ_mem(priv,
af7cca2a
TW		 175 disable_ptr + (i * sizeof(u32)),
176 evt_disable[i]);
b481de9c 177
5d49f498 178 iwl_release_nic_access(priv);
b481de9c
ZY		 179 } else {
180 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
181 IWL_DEBUG_INFO(" by writing \"1\"s into disable bitmap\n");
182 IWL_DEBUG_INFO(" in SRAM at 0x%x, size %d u32s\n",
183 disable_ptr, array_size);
184 }
185
186}
187
17744ff6
TW		 188static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
189{
190 int idx;
191
192 for (idx = 0; idx < IWL_RATE_COUNT; idx++)
193 if (iwl3945_rates[idx].plcp == plcp)
194 return idx;
195 return -1;
196}
197
b481de9c
ZY		 198/**
199 * iwl3945_get_antenna_flags - Get antenna flags for RXON command
200 * @priv: eeprom and antenna fields are used to determine antenna flags
201 *
f2c7e521 202 * priv->eeprom39 is used to determine if antenna AUX/MAIN are reversed
b481de9c
ZY		 203 * priv->antenna specifies the antenna diversity mode:
204 *
a96a27f9 205 * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
b481de9c
ZY		 206 * IWL_ANTENNA_MAIN - Force MAIN antenna
207 * IWL_ANTENNA_AUX - Force AUX antenna
208 */
4a8a4322 209__le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
b481de9c
ZY		 210{
211 switch (priv->antenna) {
212 case IWL_ANTENNA_DIVERSITY:
213 return 0;
214
215 case IWL_ANTENNA_MAIN:
f2c7e521 216 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 217 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
218 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
219
220 case IWL_ANTENNA_AUX:
f2c7e521 221 if (priv->eeprom39.antenna_switch_type)
b481de9c
ZY		 222 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
223 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
224 }
225
226 /* bad antenna selector value */
15b1687c 227 IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
b481de9c
ZY		 228 return 0; /* "diversity" is default if error */
229}
230
91c066f2
TW		 231#ifdef CONFIG_IWL3945_DEBUG
232#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
233
234static const char *iwl3945_get_tx_fail_reason(u32 status)
235{
236 switch (status & TX_STATUS_MSK) {
237 case TX_STATUS_SUCCESS:
238 return "SUCCESS";
239 TX_STATUS_ENTRY(SHORT_LIMIT);
240 TX_STATUS_ENTRY(LONG_LIMIT);
241 TX_STATUS_ENTRY(FIFO_UNDERRUN);
242 TX_STATUS_ENTRY(MGMNT_ABORT);
243 TX_STATUS_ENTRY(NEXT_FRAG);
244 TX_STATUS_ENTRY(LIFE_EXPIRE);
245 TX_STATUS_ENTRY(DEST_PS);
246 TX_STATUS_ENTRY(ABORTED);
247 TX_STATUS_ENTRY(BT_RETRY);
248 TX_STATUS_ENTRY(STA_INVALID);
249 TX_STATUS_ENTRY(FRAG_DROPPED);
250 TX_STATUS_ENTRY(TID_DISABLE);
251 TX_STATUS_ENTRY(FRAME_FLUSHED);
252 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
253 TX_STATUS_ENTRY(TX_LOCKED);
254 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
255 }
256
257 return "UNKNOWN";
258}
259#else
260static inline const char *iwl3945_get_tx_fail_reason(u32 status)
261{
262 return "";
263}
264#endif
265
e6a9854b
JB		 266/*
267 * get ieee prev rate from rate scale table.
268 * for A and B mode we need to overright prev
269 * value
270 */
4a8a4322 271int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
e6a9854b
JB		 272{
273 int next_rate = iwl3945_get_prev_ieee_rate(rate);
274
275 switch (priv->band) {
276 case IEEE80211_BAND_5GHZ:
277 if (rate == IWL_RATE_12M_INDEX)
278 next_rate = IWL_RATE_9M_INDEX;
279 else if (rate == IWL_RATE_6M_INDEX)
280 next_rate = IWL_RATE_6M_INDEX;
281 break;
7262796a
AM		 282 case IEEE80211_BAND_2GHZ:
283 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
284 iwl3945_is_associated(priv)) {
285 if (rate == IWL_RATE_11M_INDEX)
286 next_rate = IWL_RATE_5M_INDEX;
287 }
e6a9854b 288 break;
7262796a 289
e6a9854b
JB		 290 default:
291 break;
292 }
293
294 return next_rate;
295}
296
91c066f2
TW		 297
298/**
299 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
300 *
301 * When FW advances 'R' index, all entries between old and new 'R' index
302 * need to be reclaimed. As result, some free space forms. If there is
303 * enough free space (> low mark), wake the stack that feeds us.
304 */
4a8a4322 305static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
91c066f2
TW		 306 int txq_id, int index)
307{
f2c7e521 308 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
d20b3c65 309 struct iwl_queue *q = &txq->q;
91c066f2
TW		 310 struct iwl3945_tx_info *tx_info;
311
312 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
313
314 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
315 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
316
317 tx_info = &txq->txb[txq->q.read_ptr];
e039fa4a 318 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
91c066f2
TW		 319 tx_info->skb[0] = NULL;
320 iwl3945_hw_txq_free_tfd(priv, txq);
321 }
322
d20b3c65 323 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
91c066f2
TW		 324 (txq_id != IWL_CMD_QUEUE_NUM) &&
325 priv->mac80211_registered)
326 ieee80211_wake_queue(priv->hw, txq_id);
327}
328
329/**
330 * iwl3945_rx_reply_tx - Handle Tx response
331 */
4a8a4322 332static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
6100b588 333 struct iwl_rx_mem_buffer *rxb)
91c066f2 334{
3d24a9f7 335 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
91c066f2
TW		 336 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
337 int txq_id = SEQ_TO_QUEUE(sequence);
338 int index = SEQ_TO_INDEX(sequence);
f2c7e521 339 struct iwl3945_tx_queue *txq = &priv->txq39[txq_id];
e039fa4a 340 struct ieee80211_tx_info *info;
91c066f2
TW		 341 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
342 u32 status = le32_to_cpu(tx_resp->status);
343 int rate_idx;
74221d07 344 int fail;
91c066f2
TW		 345
346 if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
15b1687c 347 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
91c066f2
TW		 348 "is out of range [0-%d] %d %d\n", txq_id,
349 index, txq->q.n_bd, txq->q.write_ptr,
350 txq->q.read_ptr);
351 return;
352 }
353
e039fa4a 354 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
e6a9854b
JB		 355 ieee80211_tx_info_clear_status(info);
356
357 /* Fill the MRR chain with some info about on-chip retransmissions */
358 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
359 if (info->band == IEEE80211_BAND_5GHZ)
360 rate_idx -= IWL_FIRST_OFDM_RATE;
361
362 fail = tx_resp->failure_frame;
74221d07
AM		 363
364 info->status.rates[0].idx = rate_idx;
365 info->status.rates[0].count = fail + 1; /* add final attempt */
91c066f2 366
91c066f2 367 /* tx_status->rts_retry_count = tx_resp->failure_rts; */
e039fa4a
JB		 368 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
369 IEEE80211_TX_STAT_ACK : 0;
91c066f2
TW		 370
371 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
372 txq_id, iwl3945_get_tx_fail_reason(status), status,
373 tx_resp->rate, tx_resp->failure_frame);
374
91c066f2
TW		 375 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
376 iwl3945_tx_queue_reclaim(priv, txq_id, index);
377
378 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
15b1687c 379 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
91c066f2
TW		 380}
381
382
383
b481de9c
ZY		 384/*****************************************************************************
385 *
386 * Intel PRO/Wireless 3945ABG/BG Network Connection
387 *
388 * RX handler implementations
389 *
b481de9c
ZY		 390 *****************************************************************************/
391
4a8a4322 392void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
b481de9c 393{
3d24a9f7 394 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
b481de9c 395 IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
bb8c093b 396 (int)sizeof(struct iwl3945_notif_statistics),
b481de9c
ZY		 397 le32_to_cpu(pkt->len));
398
f2c7e521 399 memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
b481de9c 400
ab53d8af
MA		 401 iwl3945_led_background(priv);
402
b481de9c
ZY		 403 priv->last_statistics_time = jiffies;
404}
405
17744ff6
TW		 406/******************************************************************************
407 *
408 * Misc. internal state and helper functions
409 *
410 ******************************************************************************/
411#ifdef CONFIG_IWL3945_DEBUG
412
413/**
414 * iwl3945_report_frame - dump frame to syslog during debug sessions
415 *
416 * You may hack this function to show different aspects of received frames,
417 * including selective frame dumps.
418 * group100 parameter selects whether to show 1 out of 100 good frames.
419 */
4a8a4322 420static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 421 struct iwl_rx_packet *pkt,
17744ff6
TW		 422 struct ieee80211_hdr *header, int group100)
423{
424 u32 to_us;
425 u32 print_summary = 0;
426 u32 print_dump = 0; /* set to 1 to dump all frames' contents */
427 u32 hundred = 0;
428 u32 dataframe = 0;
fd7c8a40 429 __le16 fc;
17744ff6
TW		 430 u16 seq_ctl;
431 u16 channel;
432 u16 phy_flags;
433 u16 length;
434 u16 status;
435 u16 bcn_tmr;
436 u32 tsf_low;
437 u64 tsf;
438 u8 rssi;
439 u8 agc;
440 u16 sig_avg;
441 u16 noise_diff;
442 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
443 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
444 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
445 u8 *data = IWL_RX_DATA(pkt);
446
447 /* MAC header */
fd7c8a40 448 fc = header->frame_control;
17744ff6
TW		 449 seq_ctl = le16_to_cpu(header->seq_ctrl);
450
451 /* metadata */
452 channel = le16_to_cpu(rx_hdr->channel);
453 phy_flags = le16_to_cpu(rx_hdr->phy_flags);
454 length = le16_to_cpu(rx_hdr->len);
455
456 /* end-of-frame status and timestamp */
457 status = le32_to_cpu(rx_end->status);
458 bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
459 tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
460 tsf = le64_to_cpu(rx_end->timestamp);
461
462 /* signal statistics */
463 rssi = rx_stats->rssi;
464 agc = rx_stats->agc;
465 sig_avg = le16_to_cpu(rx_stats->sig_avg);
466 noise_diff = le16_to_cpu(rx_stats->noise_diff);
467
468 to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
469
470 /* if data frame is to us and all is good,
471 * (optionally) print summary for only 1 out of every 100 */
fd7c8a40
HH		 472 if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
473 cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
17744ff6
TW		 474 dataframe = 1;
475 if (!group100)
476 print_summary = 1; /* print each frame */
477 else if (priv->framecnt_to_us < 100) {
478 priv->framecnt_to_us++;
479 print_summary = 0;
480 } else {
481 priv->framecnt_to_us = 0;
482 print_summary = 1;
483 hundred = 1;
484 }
485 } else {
486 /* print summary for all other frames */
487 print_summary = 1;
488 }
489
490 if (print_summary) {
491 char *title;
0ff1cca0 492 int rate;
17744ff6
TW		 493
494 if (hundred)
495 title = "100Frames";
fd7c8a40 496 else if (ieee80211_has_retry(fc))
17744ff6 497 title = "Retry";
fd7c8a40 498 else if (ieee80211_is_assoc_resp(fc))
17744ff6 499 title = "AscRsp";
fd7c8a40 500 else if (ieee80211_is_reassoc_resp(fc))
17744ff6 501 title = "RasRsp";
fd7c8a40 502 else if (ieee80211_is_probe_resp(fc)) {
17744ff6
TW		 503 title = "PrbRsp";
504 print_dump = 1; /* dump frame contents */
505 } else if (ieee80211_is_beacon(fc)) {
506 title = "Beacon";
507 print_dump = 1; /* dump frame contents */
508 } else if (ieee80211_is_atim(fc))
509 title = "ATIM";
510 else if (ieee80211_is_auth(fc))
511 title = "Auth";
512 else if (ieee80211_is_deauth(fc))
513 title = "DeAuth";
514 else if (ieee80211_is_disassoc(fc))
515 title = "DisAssoc";
516 else
517 title = "Frame";
518
519 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
520 if (rate == -1)
521 rate = 0;
522 else
523 rate = iwl3945_rates[rate].ieee / 2;
524
525 /* print frame summary.
526 * MAC addresses show just the last byte (for brevity),
527 * but you can hack it to show more, if you'd like to. */
528 if (dataframe)
529 IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
0ff1cca0 530 "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
fd7c8a40 531 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 532 length, rssi, channel, rate);
533 else {
534 /* src/dst addresses assume managed mode */
535 IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
536 "src=0x%02x, rssi=%u, tim=%lu usec, "
537 "phy=0x%02x, chnl=%d\n",
fd7c8a40 538 title, le16_to_cpu(fc), header->addr1[5],
17744ff6
TW		 539 header->addr3[5], rssi,
540 tsf_low - priv->scan_start_tsf,
541 phy_flags, channel);
542 }
543 }
544 if (print_dump)
40b8ec0b 545 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
17744ff6
TW		 546}
547#else
4a8a4322 548static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
3d24a9f7 549 struct iwl_rx_packet *pkt,
17744ff6
TW		 550 struct ieee80211_hdr *header, int group100)
551{
552}
553#endif
554
4bd9b4f3 555/* This is necessary only for a number of statistics, see the caller. */
4a8a4322 556static int iwl3945_is_network_packet(struct iwl_priv *priv,
4bd9b4f3
AG		 557 struct ieee80211_hdr *header)
558{
559 /* Filter incoming packets to determine if they are targeted toward
560 * this network, discarding packets coming from ourselves */
561 switch (priv->iw_mode) {
05c914fe 562 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */
4bd9b4f3
AG		 563 /* packets to our IBSS update information */
564 return !compare_ether_addr(header->addr3, priv->bssid);
05c914fe 565 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
4bd9b4f3
AG		 566 /* packets to our IBSS update information */
567 return !compare_ether_addr(header->addr2, priv->bssid);
568 default:
569 return 1;
570 }
571}
17744ff6 572
4a8a4322 573static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
6100b588 574 struct iwl_rx_mem_buffer *rxb,
12342c47 575 struct ieee80211_rx_status *stats)
b481de9c 576{
3d24a9f7 577 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
699669f3 578#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 579 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
699669f3 580#endif
bb8c093b
CH		 581 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
582 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
b481de9c
ZY		 583 short len = le16_to_cpu(rx_hdr->len);
584
585 /* We received data from the HW, so stop the watchdog */
3d24a9f7 586 if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
b481de9c
ZY		 587 IWL_DEBUG_DROP("Corruption detected!\n");
588 return;
589 }
590
591 /* We only process data packets if the interface is open */
592 if (unlikely(!priv->is_open)) {
593 IWL_DEBUG_DROP_LIMIT
594 ("Dropping packet while interface is not open.\n");
595 return;
596 }
b481de9c
ZY		 597
598 skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
599 /* Set the size of the skb to the size of the frame */
600 skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
601
df878d8f 602 if (iwl3945_mod_params.sw_crypto)
bb8c093b 603 iwl3945_set_decrypted_flag(priv, rxb->skb,
b481de9c
ZY		 604 le32_to_cpu(rx_end->status), stats);
605
ab53d8af 606#ifdef CONFIG_IWL3945_LEDS
4bd9b4f3 607 if (ieee80211_is_data(hdr->frame_control))
ab53d8af
MA		 608 priv->rxtxpackets += len;
609#endif
b481de9c
ZY		 610 ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
611 rxb->skb = NULL;
612}
613
7878a5a4
MA		 614#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
615
4a8a4322 616static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
6100b588 617 struct iwl_rx_mem_buffer *rxb)
b481de9c 618{
17744ff6
TW		 619 struct ieee80211_hdr *header;
620 struct ieee80211_rx_status rx_status;
3d24a9f7 621 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
bb8c093b
CH		 622 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
623 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
624 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
17744ff6 625 int snr;
b481de9c
ZY		 626 u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
627 u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
b481de9c 628 u8 network_packet;
17744ff6 629
17744ff6
TW		 630 rx_status.flag = 0;
631 rx_status.mactime = le64_to_cpu(rx_end->timestamp);
dc92e497 632 rx_status.freq =
c0186078 633 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
17744ff6
TW		 634 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
635 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
636
637 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
17744ff6
TW		 638 if (rx_status.band == IEEE80211_BAND_5GHZ)
639 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
b481de9c 640
6f0a2c4d
BR		 641 rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
642 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
643
644 /* set the preamble flag if appropriate */
645 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
646 rx_status.flag |= RX_FLAG_SHORTPRE;
647
b481de9c
ZY		 648 if ((unlikely(rx_stats->phy_count > 20))) {
649 IWL_DEBUG_DROP
650 ("dsp size out of range [0,20]: "
651 "%d/n", rx_stats->phy_count);
652 return;
653 }
654
655 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
656 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
657 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
658 return;
659 }
660
56decd3c 661
b481de9c
ZY		 662
663 /* Convert 3945's rssi indicator to dBm */
250bdd21 664 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
b481de9c
ZY		 665
666 /* Set default noise value to -127 */
667 if (priv->last_rx_noise == 0)
668 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
669
670 /* 3945 provides noise info for OFDM frames only.
671 * sig_avg and noise_diff are measured by the 3945's digital signal
672 * processor (DSP), and indicate linear levels of signal level and
673 * distortion/noise within the packet preamble after
674 * automatic gain control (AGC). sig_avg should stay fairly
675 * constant if the radio's AGC is working well.
676 * Since these values are linear (not dB or dBm), linear
677 * signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
678 * Convert linear SNR to dB SNR, then subtract that from rssi dBm
679 * to obtain noise level in dBm.
17744ff6 680 * Calculate rx_status.signal (quality indicator in %) based on SNR. */
b481de9c
ZY		 681 if (rx_stats_noise_diff) {
682 snr = rx_stats_sig_avg / rx_stats_noise_diff;
566bfe5a 683 rx_status.noise = rx_status.signal -
17744ff6 684 iwl3945_calc_db_from_ratio(snr);
566bfe5a 685 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
17744ff6 686 rx_status.noise);
b481de9c
ZY		 687
688 /* If noise info not available, calculate signal quality indicator (%)
689 * using just the dBm signal level. */
690 } else {
17744ff6 691 rx_status.noise = priv->last_rx_noise;
566bfe5a 692 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
b481de9c
ZY		 693 }
694
695
696 IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
566bfe5a 697 rx_status.signal, rx_status.noise, rx_status.qual,
b481de9c
ZY		 698 rx_stats_sig_avg, rx_stats_noise_diff);
699
b481de9c
ZY		 700 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
701
bb8c093b 702 network_packet = iwl3945_is_network_packet(priv, header);
b481de9c 703
17744ff6
TW		 704 IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
705 network_packet ? '*' : ' ',
706 le16_to_cpu(rx_hdr->channel),
566bfe5a
BR		 707 rx_status.signal, rx_status.signal,
708 rx_status.noise, rx_status.rate_idx);
b481de9c 709
17744ff6 710#ifdef CONFIG_IWL3945_DEBUG
40b8ec0b 711 if (priv->debug_level & (IWL_DL_RX))
b481de9c 712 /* Set "1" to report good data frames in groups of 100 */
17744ff6 713 iwl3945_dbg_report_frame(priv, pkt, header, 1);
b481de9c
ZY		 714#endif
715
716 if (network_packet) {
717 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
718 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
566bfe5a 719 priv->last_rx_rssi = rx_status.signal;
17744ff6 720 priv->last_rx_noise = rx_status.noise;
b481de9c
ZY		 721 }
722
12e5e22d 723 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
b481de9c
ZY		 724}
725
4a8a4322 726int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
b481de9c
ZY		 727 dma_addr_t addr, u16 len)
728{
729 int count;
730 u32 pad;
bb8c093b 731 struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
b481de9c
ZY		 732
733 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
734 pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
735
736 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
15b1687c 737 IWL_ERR(priv, "Error can not send more than %d chunks\n",
b481de9c
ZY		 738 NUM_TFD_CHUNKS);
739 return -EINVAL;
740 }
741
742 tfd->pa[count].addr = cpu_to_le32(addr);
743 tfd->pa[count].len = cpu_to_le32(len);
744
745 count++;
746
747 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
748 TFD_CTL_PAD_SET(pad));
749
750 return 0;
751}
752
753/**
bb8c093b 754 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
b481de9c
ZY		 755 *
756 * Does NOT advance any indexes
757 */
4a8a4322 758int iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c 759{
bb8c093b
CH		 760 struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
761 struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
b481de9c
ZY		 762 struct pci_dev *dev = priv->pci_dev;
763 int i;
764 int counter;
765
766 /* classify bd */
767 if (txq->q.id == IWL_CMD_QUEUE_NUM)
768 /* nothing to cleanup after for host commands */
769 return 0;
770
771 /* sanity check */
772 counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
773 if (counter > NUM_TFD_CHUNKS) {
15b1687c 774 IWL_ERR(priv, "Too many chunks: %i\n", counter);
b481de9c
ZY		 775 /* @todo issue fatal error, it is quite serious situation */
776 return 0;
777 }
778
779 /* unmap chunks if any */
780
781 for (i = 1; i < counter; i++) {
782 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
783 le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
fc4b6853
TW		 784 if (txq->txb[txq->q.read_ptr].skb[0]) {
785 struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
786 if (txq->txb[txq->q.read_ptr].skb[0]) {
b481de9c
ZY		 787 /* Can be called from interrupt context */
788 dev_kfree_skb_any(skb);
fc4b6853 789 txq->txb[txq->q.read_ptr].skb[0] = NULL;
b481de9c
ZY		 790 }
791 }
792 }
793 return 0;
794}
795
4a8a4322 796u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
b481de9c 797{
c93007ef 798 int i, start = IWL_AP_ID;
b481de9c
ZY		 799 int ret = IWL_INVALID_STATION;
800 unsigned long flags;
801
c93007ef
SO		 802 if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
803 (priv->iw_mode == NL80211_IFTYPE_AP))
804 start = IWL_STA_ID;
805
806 if (is_broadcast_ether_addr(addr))
3832ec9d 807 return priv->hw_params.bcast_sta_id;
c93007ef 808
b481de9c 809 spin_lock_irqsave(&priv->sta_lock, flags);
3832ec9d 810 for (i = start; i < priv->hw_params.max_stations; i++)
f2c7e521 811 if ((priv->stations_39[i].used) &&
b481de9c 812 (!compare_ether_addr
f2c7e521 813 (priv->stations_39[i].sta.sta.addr, addr))) {
b481de9c
ZY		 814 ret = i;
815 goto out;
816 }
817
e174961c
JB		 818 IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
819 addr, priv->num_stations);
b481de9c
ZY		 820 out:
821 spin_unlock_irqrestore(&priv->sta_lock, flags);
822 return ret;
823}
824
825/**
bb8c093b 826 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
b481de9c
ZY		 827 *
828*/
c2d79b48 829void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
e039fa4a 830 struct ieee80211_tx_info *info,
b481de9c
ZY		 831 struct ieee80211_hdr *hdr, int sta_id, int tx_id)
832{
e039fa4a 833 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
2e92e6f2 834 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
b481de9c
ZY		 835 u16 rate_mask;
836 int rate;
837 u8 rts_retry_limit;
838 u8 data_retry_limit;
839 __le32 tx_flags;
fd7c8a40 840 __le16 fc = hdr->frame_control;
c2d79b48 841 struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
b481de9c 842
bb8c093b 843 rate = iwl3945_rates[rate_index].plcp;
c2d79b48 844 tx_flags = tx->tx_flags;
b481de9c
ZY		 845
846 /* We need to figure out how to get the sta->supp_rates while
e039fa4a 847 * in this running context */
b481de9c
ZY		 848 rate_mask = IWL_RATES_MASK;
849
b481de9c
ZY		 850 if (tx_id >= IWL_CMD_QUEUE_NUM)
851 rts_retry_limit = 3;
852 else
853 rts_retry_limit = 7;
854
fd7c8a40 855 if (ieee80211_is_probe_resp(fc)) {
b481de9c
ZY		 856 data_retry_limit = 3;
857 if (data_retry_limit < rts_retry_limit)
858 rts_retry_limit = data_retry_limit;
859 } else
860 data_retry_limit = IWL_DEFAULT_TX_RETRY;
861
862 if (priv->data_retry_limit != -1)
863 data_retry_limit = priv->data_retry_limit;
864
fd7c8a40
HH		 865 if (ieee80211_is_mgmt(fc)) {
866 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
867 case cpu_to_le16(IEEE80211_STYPE_AUTH):
868 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
869 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
870 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
b481de9c
ZY		 871 if (tx_flags & TX_CMD_FLG_RTS_MSK) {
872 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
873 tx_flags |= TX_CMD_FLG_CTS_MSK;
874 }
875 break;
876 default:
877 break;
878 }
879 }
880
c2d79b48
WT		 881 tx->rts_retry_limit = rts_retry_limit;
882 tx->data_retry_limit = data_retry_limit;
883 tx->rate = rate;
884 tx->tx_flags = tx_flags;
b481de9c
ZY		 885
886 /* OFDM */
c2d79b48 887 tx->supp_rates[0] =
14577f23 888 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
b481de9c
ZY		 889
890 /* CCK */
c2d79b48 891 tx->supp_rates[1] = (rate_mask & 0xF);
b481de9c
ZY		 892
893 IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
894 "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
c2d79b48
WT		 895 tx->rate, le32_to_cpu(tx->tx_flags),
896 tx->supp_rates[1], tx->supp_rates[0]);
b481de9c
ZY		 897}
898
4a8a4322 899u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
b481de9c
ZY		 900{
901 unsigned long flags_spin;
bb8c093b 902 struct iwl3945_station_entry *station;
b481de9c
ZY		 903
904 if (sta_id == IWL_INVALID_STATION)
905 return IWL_INVALID_STATION;
906
907 spin_lock_irqsave(&priv->sta_lock, flags_spin);
f2c7e521 908 station = &priv->stations_39[sta_id];
b481de9c
ZY		 909
910 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
911 station->sta.rate_n_flags = cpu_to_le16(tx_rate);
b481de9c
ZY		 912 station->sta.mode = STA_CONTROL_MODIFY_MSK;
913
914 spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
915
bb8c093b 916 iwl3945_send_add_station(priv, &station->sta, flags);
b481de9c
ZY		 917 IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
918 sta_id, tx_rate);
919 return sta_id;
920}
921
4a8a4322 922static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
b481de9c
ZY		 923{
924 int rc;
925 unsigned long flags;
926
927 spin_lock_irqsave(&priv->lock, flags);
5d49f498 928 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 929 if (rc) {
930 spin_unlock_irqrestore(&priv->lock, flags);
931 return rc;
932 }
933
934 if (!pwr_max) {
935 u32 val;
936
937 rc = pci_read_config_dword(priv->pci_dev,
938 PCI_POWER_SOURCE, &val);
939 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
5d49f498 940 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 941 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
942 ~APMG_PS_CTRL_MSK_PWR_SRC);
5d49f498 943 iwl_release_nic_access(priv);
b481de9c 944
5d49f498 945 iwl_poll_bit(priv, CSR_GPIO_IN,
b481de9c
ZY		 946 CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
947 CSR_GPIO_IN_BIT_AUX_POWER, 5000);
948 } else
5d49f498 949 iwl_release_nic_access(priv);
b481de9c 950 } else {
5d49f498 951 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 952 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
953 ~APMG_PS_CTRL_MSK_PWR_SRC);
954
5d49f498
AK		 955 iwl_release_nic_access(priv);
956 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
b481de9c
ZY		 957 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */
958 }
959 spin_unlock_irqrestore(&priv->lock, flags);
960
961 return rc;
962}
963
4a8a4322 964static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
b481de9c
ZY		 965{
966 int rc;
967 unsigned long flags;
968
969 spin_lock_irqsave(&priv->lock, flags);
5d49f498 970 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 971 if (rc) {
972 spin_unlock_irqrestore(&priv->lock, flags);
973 return rc;
974 }
975
5d49f498
AK		 976 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
977 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
3832ec9d 978 priv->shared_phys +
bb8c093b 979 offsetof(struct iwl3945_shared, rx_read_ptr[0]));
5d49f498
AK		 980 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
981 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
bddadf86
TW		 982 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
983 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
984 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
985 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
986 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
987 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
988 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
989 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
b481de9c
ZY		 990
991 /* fake read to flush all prev I/O */
5d49f498 992 iwl_read_direct32(priv, FH39_RSSR_CTRL);
b481de9c 993
5d49f498 994 iwl_release_nic_access(priv);
b481de9c
ZY		 995 spin_unlock_irqrestore(&priv->lock, flags);
996
997 return 0;
998}
999
4a8a4322 1000static int iwl3945_tx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1001{
1002 int rc;
1003 unsigned long flags;
1004
1005 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1006 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1007 if (rc) {
1008 spin_unlock_irqrestore(&priv->lock, flags);
1009 return rc;
1010 }
1011
1012 /* bypass mode */
5d49f498 1013 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
b481de9c
ZY		 1014
1015 /* RA 0 is active */
5d49f498 1016 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
b481de9c
ZY		 1017
1018 /* all 6 fifo are active */
5d49f498 1019 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
b481de9c 1020
5d49f498
AK		 1021 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1022 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1023 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1024 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
b481de9c 1025
5d49f498 1026 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
3832ec9d 1027 priv->shared_phys);
b481de9c 1028
5d49f498 1029 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
bddadf86
TW		 1030 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1031 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1032 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1033 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1034 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1035 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1036 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
b481de9c 1037
5d49f498 1038 iwl_release_nic_access(priv);
b481de9c
ZY		 1039 spin_unlock_irqrestore(&priv->lock, flags);
1040
1041 return 0;
1042}
1043
1044/**
1045 * iwl3945_txq_ctx_reset - Reset TX queue context
1046 *
1047 * Destroys all DMA structures and initialize them again
1048 */
4a8a4322 1049static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
b481de9c
ZY		 1050{
1051 int rc;
1052 int txq_id, slots_num;
1053
bb8c093b 1054 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1055
1056 /* Tx CMD queue */
1057 rc = iwl3945_tx_reset(priv);
1058 if (rc)
1059 goto error;
1060
1061 /* Tx queue(s) */
1062 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1063 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1064 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
f2c7e521 1065 rc = iwl3945_tx_queue_init(priv, &priv->txq39[txq_id], slots_num,
b481de9c
ZY		 1066 txq_id);
1067 if (rc) {
15b1687c 1068 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
b481de9c
ZY		 1069 goto error;
1070 }
1071 }
1072
1073 return rc;
1074
1075 error:
bb8c093b 1076 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1077 return rc;
1078}
1079
01ec616d 1080static int iwl3945_apm_init(struct iwl_priv *priv)
b481de9c 1081{
01ec616d 1082 int ret = 0;
b481de9c 1083
bb8c093b 1084 iwl3945_power_init_handle(priv);
b481de9c 1085
5d49f498 1086 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
01ec616d
KA		 1087 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1088
1089 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1090 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1091 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
b481de9c 1092
01ec616d
KA		 1093 /* set "initialization complete" bit to move adapter
1094 * D0U* --> D0A* state */
5d49f498 1095 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
01ec616d
KA		 1096
1097 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1098 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1099 if (ret < 0) {
b481de9c 1100 IWL_DEBUG_INFO("Failed to init the card\n");
01ec616d 1101 goto out;
b481de9c
ZY		 1102 }
1103
01ec616d
KA		 1104 ret = iwl_grab_nic_access(priv);
1105 if (ret)
1106 goto out;
1107
1108 /* enable DMA */
1109 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1110 APMG_CLK_VAL_BSM_CLK_RQT);
1111
b481de9c 1112 udelay(20);
01ec616d
KA		 1113
1114 /* disable L1-Active */
5d49f498 1115 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
01ec616d
KA		 1116 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1117
5d49f498 1118 iwl_release_nic_access(priv);
01ec616d
KA		 1119out:
1120 return ret;
1121}
b481de9c 1122
01ec616d
KA		 1123static void iwl3945_nic_config(struct iwl_priv *priv)
1124{
1125 unsigned long flags;
1126 u8 rev_id = 0;
b481de9c 1127
b481de9c
ZY		 1128 spin_lock_irqsave(&priv->lock, flags);
1129
1130 if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1131 IWL_DEBUG_INFO("RTP type \n");
1132 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
6f83eaa1 1133 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
5d49f498 1134 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1135 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
b481de9c 1136 } else {
6f83eaa1 1137 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
5d49f498 1138 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1139 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
b481de9c
ZY		 1140 }
1141
f2c7e521 1142 if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom39.sku_cap) {
b481de9c 1143 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
5d49f498 1144 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1145 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
b481de9c
ZY		 1146 } else
1147 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1148
f2c7e521 1149 if ((priv->eeprom39.board_revision & 0xF0) == 0xD0) {
b481de9c 1150 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1151 priv->eeprom39.board_revision);
5d49f498 1152 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1153 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1154 } else {
1155 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
f2c7e521 1156 priv->eeprom39.board_revision);
5d49f498 1157 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1158 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
b481de9c
ZY		 1159 }
1160
f2c7e521 1161 if (priv->eeprom39.almgor_m_version <= 1) {
5d49f498 1162 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1163 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
b481de9c 1164 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
f2c7e521 1165 priv->eeprom39.almgor_m_version);
b481de9c
ZY		 1166 } else {
1167 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
f2c7e521 1168 priv->eeprom39.almgor_m_version);
5d49f498 1169 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
6f83eaa1 1170 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
b481de9c
ZY		 1171 }
1172 spin_unlock_irqrestore(&priv->lock, flags);
1173
f2c7e521 1174 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
b481de9c
ZY		 1175 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1176
f2c7e521 1177 if (priv->eeprom39.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
b481de9c 1178 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
01ec616d
KA		 1179}
1180
1181int iwl3945_hw_nic_init(struct iwl_priv *priv)
1182{
1183 u8 rev_id;
1184 int rc;
1185 unsigned long flags;
1186 struct iwl_rx_queue *rxq = &priv->rxq;
1187
1188 spin_lock_irqsave(&priv->lock, flags);
1189 priv->cfg->ops->lib->apm_ops.init(priv);
1190 spin_unlock_irqrestore(&priv->lock, flags);
1191
1192 /* Determine HW type */
1193 rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1194 if (rc)
1195 return rc;
1196 IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1197
1198 iwl3945_nic_set_pwr_src(priv, 1);
1199 priv->cfg->ops->lib->apm_ops.config(priv);
b481de9c
ZY		 1200
1201 /* Allocate the RX queue, or reset if it is already allocated */
1202 if (!rxq->bd) {
bb8c093b 1203 rc = iwl3945_rx_queue_alloc(priv);
b481de9c 1204 if (rc) {
15b1687c 1205 IWL_ERR(priv, "Unable to initialize Rx queue\n");
b481de9c
ZY		 1206 return -ENOMEM;
1207 }
1208 } else
bb8c093b 1209 iwl3945_rx_queue_reset(priv, rxq);
b481de9c 1210
bb8c093b 1211 iwl3945_rx_replenish(priv);
b481de9c
ZY		 1212
1213 iwl3945_rx_init(priv, rxq);
1214
1215 spin_lock_irqsave(&priv->lock, flags);
1216
1217 /* Look at using this instead:
1218 rxq->need_update = 1;
bb8c093b 1219 iwl3945_rx_queue_update_write_ptr(priv, rxq);
b481de9c
ZY		 1220 */
1221
5d49f498 1222 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 1223 if (rc) {
1224 spin_unlock_irqrestore(&priv->lock, flags);
1225 return rc;
1226 }
5d49f498
AK		 1227 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1228 iwl_release_nic_access(priv);
b481de9c
ZY		 1229
1230 spin_unlock_irqrestore(&priv->lock, flags);
1231
1232 rc = iwl3945_txq_ctx_reset(priv);
1233 if (rc)
1234 return rc;
1235
1236 set_bit(STATUS_INIT, &priv->status);
1237
1238 return 0;
1239}
1240
1241/**
bb8c093b 1242 * iwl3945_hw_txq_ctx_free - Free TXQ Context
b481de9c
ZY		 1243 *
1244 * Destroy all TX DMA queues and structures
1245 */
4a8a4322 1246void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
b481de9c
ZY		 1247{
1248 int txq_id;
1249
1250 /* Tx queues */
1251 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
f2c7e521 1252 iwl3945_tx_queue_free(priv, &priv->txq39[txq_id]);
b481de9c
ZY		 1253}
1254
4a8a4322 1255void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
b481de9c 1256{
bddadf86 1257 int txq_id;
b481de9c
ZY		 1258 unsigned long flags;
1259
1260 spin_lock_irqsave(&priv->lock, flags);
5d49f498 1261 if (iwl_grab_nic_access(priv)) {
b481de9c 1262 spin_unlock_irqrestore(&priv->lock, flags);
bb8c093b 1263 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1264 return;
1265 }
1266
1267 /* stop SCD */
5d49f498 1268 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
b481de9c
ZY		 1269
1270 /* reset TFD queues */
bddadf86 1271 for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
5d49f498
AK		 1272 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1273 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
bddadf86 1274 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
b481de9c
ZY		 1275 1000);
1276 }
1277
5d49f498 1278 iwl_release_nic_access(priv);
b481de9c
ZY		 1279 spin_unlock_irqrestore(&priv->lock, flags);
1280
bb8c093b 1281 iwl3945_hw_txq_ctx_free(priv);
b481de9c
ZY		 1282}
1283
01ec616d 1284static int iwl3945_apm_stop_master(struct iwl_priv *priv)
b481de9c 1285{
01ec616d 1286 int ret = 0;
b481de9c
ZY		 1287 unsigned long flags;
1288
1289 spin_lock_irqsave(&priv->lock, flags);
1290
1291 /* set stop master bit */
5d49f498 1292 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
b481de9c 1293
01ec616d
KA		 1294 iwl_poll_direct_bit(priv, CSR_RESET,
1295 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
b481de9c 1296
01ec616d
KA		 1297 if (ret < 0)
1298 goto out;
b481de9c 1299
01ec616d 1300out:
b481de9c
ZY		 1301 spin_unlock_irqrestore(&priv->lock, flags);
1302 IWL_DEBUG_INFO("stop master\n");
1303
01ec616d
KA		 1304 return ret;
1305}
1306
1307static void iwl3945_apm_stop(struct iwl_priv *priv)
1308{
1309 unsigned long flags;
1310
1311 iwl3945_apm_stop_master(priv);
1312
1313 spin_lock_irqsave(&priv->lock, flags);
1314
1315 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1316
1317 udelay(10);
1318 /* clear "init complete" move adapter D0A* --> D0U state */
1319 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1320 spin_unlock_irqrestore(&priv->lock, flags);
b481de9c
ZY		 1321}
1322
01ec616d 1323int iwl3945_apm_reset(struct iwl_priv *priv)
b481de9c
ZY		 1324{
1325 int rc;
1326 unsigned long flags;
1327
01ec616d 1328 iwl3945_apm_stop_master(priv);
b481de9c
ZY		 1329
1330 spin_lock_irqsave(&priv->lock, flags);
1331
5d49f498 1332 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
b481de9c 1333
5d49f498 1334 iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
73d7b5ac 1335 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
b481de9c 1336
5d49f498 1337 rc = iwl_grab_nic_access(priv);
b481de9c 1338 if (!rc) {
5d49f498 1339 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
b481de9c
ZY		 1340 APMG_CLK_VAL_BSM_CLK_RQT);
1341
1342 udelay(10);
1343
5d49f498 1344 iwl_set_bit(priv, CSR_GP_CNTRL,
b481de9c
ZY		 1345 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1346
5d49f498
AK		 1347 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1348 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
b481de9c
ZY		 1349 0xFFFFFFFF);
1350
1351 /* enable DMA */
5d49f498 1352 iwl_write_prph(priv, APMG_CLK_EN_REG,
b481de9c
ZY		 1353 APMG_CLK_VAL_DMA_CLK_RQT |
1354 APMG_CLK_VAL_BSM_CLK_RQT);
1355 udelay(10);
1356
5d49f498 1357 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c
ZY		 1358 APMG_PS_CTRL_VAL_RESET_REQ);
1359 udelay(5);
5d49f498 1360 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
b481de9c 1361 APMG_PS_CTRL_VAL_RESET_REQ);
5d49f498 1362 iwl_release_nic_access(priv);
b481de9c
ZY		 1363 }
1364
1365 /* Clear the 'host command active' bit... */
1366 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1367
1368 wake_up_interruptible(&priv->wait_command_queue);
1369 spin_unlock_irqrestore(&priv->lock, flags);
1370
1371 return rc;
1372}
1373
1374/**
bb8c093b 1375 * iwl3945_hw_reg_adjust_power_by_temp
bbc5807b
IS		 1376 * return index delta into power gain settings table
1377*/
bb8c093b 1378static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
b481de9c
ZY		 1379{
1380 return (new_reading - old_reading) * (-11) / 100;
1381}
1382
1383/**
bb8c093b 1384 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
b481de9c 1385 */
bb8c093b 1386static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
b481de9c 1387{
3ac7f146 1388 return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
b481de9c
ZY		 1389}
1390
4a8a4322 1391int iwl3945_hw_get_temperature(struct iwl_priv *priv)
b481de9c 1392{
5d49f498 1393 return iwl_read32(priv, CSR_UCODE_DRV_GP2);
b481de9c
ZY		 1394}
1395
1396/**
bb8c093b 1397 * iwl3945_hw_reg_txpower_get_temperature
bbc5807b
IS		 1398 * get the current temperature by reading from NIC
1399*/
4a8a4322 1400static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
b481de9c
ZY		 1401{
1402 int temperature;
1403
bb8c093b 1404 temperature = iwl3945_hw_get_temperature(priv);
b481de9c
ZY		 1405
1406 /* driver's okay range is -260 to +25.
1407 * human readable okay range is 0 to +285 */
1408 IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1409
1410 /* handle insane temp reading */
bb8c093b 1411 if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
15b1687c 1412 IWL_ERR(priv, "Error bad temperature value %d\n", temperature);
b481de9c
ZY		 1413
1414 /* if really really hot(?),
1415 * substitute the 3rd band/group's temp measured at factory */
1416 if (priv->last_temperature > 100)
f2c7e521 1417 temperature = priv->eeprom39.groups[2].temperature;
b481de9c
ZY		 1418 else /* else use most recent "sane" value from driver */
1419 temperature = priv->last_temperature;
1420 }
1421
1422 return temperature; /* raw, not "human readable" */
1423}
1424
1425/* Adjust Txpower only if temperature variance is greater than threshold.
1426 *
1427 * Both are lower than older versions' 9 degrees */
1428#define IWL_TEMPERATURE_LIMIT_TIMER 6
1429
1430/**
1431 * is_temp_calib_needed - determines if new calibration is needed
1432 *
1433 * records new temperature in tx_mgr->temperature.
1434 * replaces tx_mgr->last_temperature *only* if calib needed
1435 * (assumes caller will actually do the calibration!). */
4a8a4322 1436static int is_temp_calib_needed(struct iwl_priv *priv)
b481de9c
ZY		 1437{
1438 int temp_diff;
1439
bb8c093b 1440 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 1441 temp_diff = priv->temperature - priv->last_temperature;
1442
1443 /* get absolute value */
1444 if (temp_diff < 0) {
1445 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1446 temp_diff = -temp_diff;
1447 } else if (temp_diff == 0)
1448 IWL_DEBUG_POWER("Same temp,\n");
1449 else
1450 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1451
1452 /* if we don't need calibration, *don't* update last_temperature */
1453 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1454 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1455 return 0;
1456 }
1457
1458 IWL_DEBUG_POWER("Timed thermal calib needed\n");
1459
1460 /* assume that caller will actually do calib ...
1461 * update the "last temperature" value */
1462 priv->last_temperature = priv->temperature;
1463 return 1;
1464}
1465
1466#define IWL_MAX_GAIN_ENTRIES 78
1467#define IWL_CCK_FROM_OFDM_POWER_DIFF -5
1468#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1469
1470/* radio and DSP power table, each step is 1/2 dB.
1471 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
bb8c093b 1472static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
b481de9c
ZY		 1473 {
1474 {251, 127}, /* 2.4 GHz, highest power */
1475 {251, 127},
1476 {251, 127},
1477 {251, 127},
1478 {251, 125},
1479 {251, 110},
1480 {251, 105},
1481 {251, 98},
1482 {187, 125},
1483 {187, 115},
1484 {187, 108},
1485 {187, 99},
1486 {243, 119},
1487 {243, 111},
1488 {243, 105},
1489 {243, 97},
1490 {243, 92},
1491 {211, 106},
1492 {211, 100},
1493 {179, 120},
1494 {179, 113},
1495 {179, 107},
1496 {147, 125},
1497 {147, 119},
1498 {147, 112},
1499 {147, 106},
1500 {147, 101},
1501 {147, 97},
1502 {147, 91},
1503 {115, 107},
1504 {235, 121},
1505 {235, 115},
1506 {235, 109},
1507 {203, 127},
1508 {203, 121},
1509 {203, 115},
1510 {203, 108},
1511 {203, 102},
1512 {203, 96},
1513 {203, 92},
1514 {171, 110},
1515 {171, 104},
1516 {171, 98},
1517 {139, 116},
1518 {227, 125},
1519 {227, 119},
1520 {227, 113},
1521 {227, 107},
1522 {227, 101},
1523 {227, 96},
1524 {195, 113},
1525 {195, 106},
1526 {195, 102},
1527 {195, 95},
1528 {163, 113},
1529 {163, 106},
1530 {163, 102},
1531 {163, 95},
1532 {131, 113},
1533 {131, 106},
1534 {131, 102},
1535 {131, 95},
1536 {99, 113},
1537 {99, 106},
1538 {99, 102},
1539 {99, 95},
1540 {67, 113},
1541 {67, 106},
1542 {67, 102},
1543 {67, 95},
1544 {35, 113},
1545 {35, 106},
1546 {35, 102},
1547 {35, 95},
1548 {3, 113},
1549 {3, 106},
1550 {3, 102},
1551 {3, 95} }, /* 2.4 GHz, lowest power */
1552 {
1553 {251, 127}, /* 5.x GHz, highest power */
1554 {251, 120},
1555 {251, 114},
1556 {219, 119},
1557 {219, 101},
1558 {187, 113},
1559 {187, 102},
1560 {155, 114},
1561 {155, 103},
1562 {123, 117},
1563 {123, 107},
1564 {123, 99},
1565 {123, 92},
1566 {91, 108},
1567 {59, 125},
1568 {59, 118},
1569 {59, 109},
1570 {59, 102},
1571 {59, 96},
1572 {59, 90},
1573 {27, 104},
1574 {27, 98},
1575 {27, 92},
1576 {115, 118},
1577 {115, 111},
1578 {115, 104},
1579 {83, 126},
1580 {83, 121},
1581 {83, 113},
1582 {83, 105},
1583 {83, 99},
1584 {51, 118},
1585 {51, 111},
1586 {51, 104},
1587 {51, 98},
1588 {19, 116},
1589 {19, 109},
1590 {19, 102},
1591 {19, 98},
1592 {19, 93},
1593 {171, 113},
1594 {171, 107},
1595 {171, 99},
1596 {139, 120},
1597 {139, 113},
1598 {139, 107},
1599 {139, 99},
1600 {107, 120},
1601 {107, 113},
1602 {107, 107},
1603 {107, 99},
1604 {75, 120},
1605 {75, 113},
1606 {75, 107},
1607 {75, 99},
1608 {43, 120},
1609 {43, 113},
1610 {43, 107},
1611 {43, 99},
1612 {11, 120},
1613 {11, 113},
1614 {11, 107},
1615 {11, 99},
1616 {131, 107},
1617 {131, 99},
1618 {99, 120},
1619 {99, 113},
1620 {99, 107},
1621 {99, 99},
1622 {67, 120},
1623 {67, 113},
1624 {67, 107},
1625 {67, 99},
1626 {35, 120},
1627 {35, 113},
1628 {35, 107},
1629 {35, 99},
1630 {3, 120} } /* 5.x GHz, lowest power */
1631};
1632
bb8c093b 1633static inline u8 iwl3945_hw_reg_fix_power_index(int index)
b481de9c
ZY		 1634{
1635 if (index < 0)
1636 return 0;
1637 if (index >= IWL_MAX_GAIN_ENTRIES)
1638 return IWL_MAX_GAIN_ENTRIES - 1;
1639 return (u8) index;
1640}
1641
1642/* Kick off thermal recalibration check every 60 seconds */
1643#define REG_RECALIB_PERIOD (60)
1644
1645/**
bb8c093b 1646 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
b481de9c
ZY		 1647 *
1648 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1649 * or 6 Mbit (OFDM) rates.
1650 */
4a8a4322 1651static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
b481de9c 1652 s32 rate_index, const s8 *clip_pwrs,
d20b3c65 1653 struct iwl_channel_info *ch_info,
b481de9c
ZY		 1654 int band_index)
1655{
bb8c093b 1656 struct iwl3945_scan_power_info *scan_power_info;
b481de9c
ZY		 1657 s8 power;
1658 u8 power_index;
1659
1660 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1661
1662 /* use this channel group's 6Mbit clipping/saturation pwr,
1663 * but cap at regulatory scan power restriction (set during init
1664 * based on eeprom channel data) for this channel. */
14577f23 1665 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
b481de9c
ZY		 1666
1667 /* further limit to user's max power preference.
1668 * FIXME: Other spectrum management power limitations do not
1669 * seem to apply?? */
1670 power = min(power, priv->user_txpower_limit);
1671 scan_power_info->requested_power = power;
1672
1673 /* find difference between new scan *power* and current "normal"
1674 * Tx *power* for 6Mb. Use this difference (x2) to adjust the
1675 * current "normal" temperature-compensated Tx power *index* for
1676 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1677 * *index*. */
1678 power_index = ch_info->power_info[rate_index].power_table_index
1679 - (power - ch_info->power_info
14577f23 1680 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
b481de9c
ZY		 1681
1682 /* store reference index that we use when adjusting *all* scan
1683 * powers. So we can accommodate user (all channel) or spectrum
1684 * management (single channel) power changes "between" temperature
1685 * feedback compensation procedures.
1686 * don't force fit this reference index into gain table; it may be a
1687 * negative number. This will help avoid errors when we're at
1688 * the lower bounds (highest gains, for warmest temperatures)
1689 * of the table. */
1690
1691 /* don't exceed table bounds for "real" setting */
bb8c093b 1692 power_index = iwl3945_hw_reg_fix_power_index(power_index);
b481de9c
ZY		 1693
1694 scan_power_info->power_table_index = power_index;
1695 scan_power_info->tpc.tx_gain =
1696 power_gain_table[band_index][power_index].tx_gain;
1697 scan_power_info->tpc.dsp_atten =
1698 power_gain_table[band_index][power_index].dsp_atten;
1699}
1700
1701/**
bb8c093b 1702 * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
b481de9c
ZY		 1703 *
1704 * Configures power settings for all rates for the current channel,
1705 * using values from channel info struct, and send to NIC
1706 */
4a8a4322 1707int iwl3945_hw_reg_send_txpower(struct iwl_priv *priv)
b481de9c 1708{
14577f23 1709 int rate_idx, i;
d20b3c65 1710 const struct iwl_channel_info *ch_info = NULL;
bb8c093b 1711 struct iwl3945_txpowertable_cmd txpower = {
f2c7e521 1712 .channel = priv->active39_rxon.channel,
b481de9c
ZY		 1713 };
1714
8318d78a 1715 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
bb8c093b 1716 ch_info = iwl3945_get_channel_info(priv,
8318d78a 1717 priv->band,
f2c7e521 1718 le16_to_cpu(priv->active39_rxon.channel));
b481de9c 1719 if (!ch_info) {
15b1687c
WT		 1720 IWL_ERR(priv,
1721 "Failed to get channel info for channel %d [%d]\n",
1722 le16_to_cpu(priv->active39_rxon.channel), priv->band);
b481de9c
ZY		 1723 return -EINVAL;
1724 }
1725
1726 if (!is_channel_valid(ch_info)) {
1727 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1728 "non-Tx channel.\n");
1729 return 0;
1730 }
1731
1732 /* fill cmd with power settings for all rates for current channel */
14577f23
MA		 1733 /* Fill OFDM rate */
1734 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
d9829a67 1735 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
14577f23
MA		 1736
1737 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1738 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
b481de9c
ZY		 1739
1740 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1741 le16_to_cpu(txpower.channel),
1742 txpower.band,
14577f23
MA		 1743 txpower.power[i].tpc.tx_gain,
1744 txpower.power[i].tpc.dsp_atten,
1745 txpower.power[i].rate);
1746 }
1747 /* Fill CCK rates */
1748 for (rate_idx = IWL_FIRST_CCK_RATE;
1749 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1750 txpower.power[i].tpc = ch_info->power_info[i].tpc;
bb8c093b 1751 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
14577f23
MA		 1752
1753 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1754 le16_to_cpu(txpower.channel),
1755 txpower.band,
1756 txpower.power[i].tpc.tx_gain,
1757 txpower.power[i].tpc.dsp_atten,
1758 txpower.power[i].rate);
b481de9c
ZY		 1759 }
1760
bb8c093b
CH		 1761 return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1762 sizeof(struct iwl3945_txpowertable_cmd), &txpower);
b481de9c
ZY		 1763
1764}
1765
1766/**
bb8c093b 1767 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
b481de9c
ZY		 1768 * @ch_info: Channel to update. Uses power_info.requested_power.
1769 *
1770 * Replace requested_power and base_power_index ch_info fields for
1771 * one channel.
1772 *
1773 * Called if user or spectrum management changes power preferences.
1774 * Takes into account h/w and modulation limitations (clip power).
1775 *
1776 * This does *not* send anything to NIC, just sets up ch_info for one channel.
1777 *
1778 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1779 * properly fill out the scan powers, and actual h/w gain settings,
1780 * and send changes to NIC
1781 */
4a8a4322 1782static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
d20b3c65 1783 struct iwl_channel_info *ch_info)
b481de9c 1784{
bb8c093b 1785 struct iwl3945_channel_power_info *power_info;
b481de9c
ZY		 1786 int power_changed = 0;
1787 int i;
1788 const s8 *clip_pwrs;
1789 int power;
1790
1791 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1792 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1793
1794 /* Get this channel's rate-to-current-power settings table */
1795 power_info = ch_info->power_info;
1796
1797 /* update OFDM Txpower settings */
14577f23 1798 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
b481de9c
ZY		 1799 i++, ++power_info) {
1800 int delta_idx;
1801
1802 /* limit new power to be no more than h/w capability */
1803 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1804 if (power == power_info->requested_power)
1805 continue;
1806
1807 /* find difference between old and new requested powers,
1808 * update base (non-temp-compensated) power index */
1809 delta_idx = (power - power_info->requested_power) * 2;
1810 power_info->base_power_index -= delta_idx;
1811
1812 /* save new requested power value */
1813 power_info->requested_power = power;
1814
1815 power_changed = 1;
1816 }
1817
1818 /* update CCK Txpower settings, based on OFDM 12M setting ...
1819 * ... all CCK power settings for a given channel are the *same*. */
1820 if (power_changed) {
1821 power =
14577f23 1822 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1823 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1824
bb8c093b 1825 /* do all CCK rates' iwl3945_channel_power_info structures */
14577f23 1826 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
b481de9c
ZY		 1827 power_info->requested_power = power;
1828 power_info->base_power_index =
14577f23 1829 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
b481de9c
ZY		 1830 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1831 ++power_info;
1832 }
1833 }
1834
1835 return 0;
1836}
1837
1838/**
bb8c093b 1839 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
b481de9c
ZY		 1840 *
1841 * NOTE: Returned power limit may be less (but not more) than requested,
1842 * based strictly on regulatory (eeprom and spectrum mgt) limitations
1843 * (no consideration for h/w clipping limitations).
1844 */
d20b3c65 1845static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
b481de9c
ZY		 1846{
1847 s8 max_power;
1848
1849#if 0
1850 /* if we're using TGd limits, use lower of TGd or EEPROM */
1851 if (ch_info->tgd_data.max_power != 0)
1852 max_power = min(ch_info->tgd_data.max_power,
1853 ch_info->eeprom.max_power_avg);
1854
1855 /* else just use EEPROM limits */
1856 else
1857#endif
1858 max_power = ch_info->eeprom.max_power_avg;
1859
1860 return min(max_power, ch_info->max_power_avg);
1861}
1862
1863/**
bb8c093b 1864 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
b481de9c
ZY		 1865 *
1866 * Compensate txpower settings of *all* channels for temperature.
1867 * This only accounts for the difference between current temperature
1868 * and the factory calibration temperatures, and bases the new settings
1869 * on the channel's base_power_index.
1870 *
1871 * If RxOn is "associated", this sends the new Txpower to NIC!
1872 */
4a8a4322 1873static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
b481de9c 1874{
d20b3c65 1875 struct iwl_channel_info *ch_info = NULL;
b481de9c
ZY		 1876 int delta_index;
1877 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1878 u8 a_band;
1879 u8 rate_index;
1880 u8 scan_tbl_index;
1881 u8 i;
1882 int ref_temp;
1883 int temperature = priv->temperature;
1884
1885 /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1886 for (i = 0; i < priv->channel_count; i++) {
1887 ch_info = &priv->channel_info[i];
1888 a_band = is_channel_a_band(ch_info);
1889
1890 /* Get this chnlgrp's factory calibration temperature */
f2c7e521 1891 ref_temp = (s16)priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 1892 temperature;
1893
a96a27f9 1894 /* get power index adjustment based on current and factory
b481de9c 1895 * temps */
bb8c093b 1896 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
b481de9c
ZY		 1897 ref_temp);
1898
1899 /* set tx power value for all rates, OFDM and CCK */
1900 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1901 rate_index++) {
1902 int power_idx =
1903 ch_info->power_info[rate_index].base_power_index;
1904
1905 /* temperature compensate */
1906 power_idx += delta_index;
1907
1908 /* stay within table range */
bb8c093b 1909 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c
ZY		 1910 ch_info->power_info[rate_index].
1911 power_table_index = (u8) power_idx;
1912 ch_info->power_info[rate_index].tpc =
1913 power_gain_table[a_band][power_idx];
1914 }
1915
1916 /* Get this chnlgrp's rate-to-max/clip-powers table */
f2c7e521 1917 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 1918
1919 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1920 for (scan_tbl_index = 0;
1921 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1922 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 1923 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 1924 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 1925 actual_index, clip_pwrs,
1926 ch_info, a_band);
1927 }
1928 }
1929
1930 /* send Txpower command for current channel to ucode */
bb8c093b 1931 return iwl3945_hw_reg_send_txpower(priv);
b481de9c
ZY		 1932}
1933
4a8a4322 1934int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
b481de9c 1935{
d20b3c65 1936 struct iwl_channel_info *ch_info;
b481de9c
ZY		 1937 s8 max_power;
1938 u8 a_band;
1939 u8 i;
1940
1941 if (priv->user_txpower_limit == power) {
1942 IWL_DEBUG_POWER("Requested Tx power same as current "
1943 "limit: %ddBm.\n", power);
1944 return 0;
1945 }
1946
1947 IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1948 priv->user_txpower_limit = power;
1949
1950 /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1951
1952 for (i = 0; i < priv->channel_count; i++) {
1953 ch_info = &priv->channel_info[i];
1954 a_band = is_channel_a_band(ch_info);
1955
1956 /* find minimum power of all user and regulatory constraints
1957 * (does not consider h/w clipping limitations) */
bb8c093b 1958 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
b481de9c
ZY		 1959 max_power = min(power, max_power);
1960 if (max_power != ch_info->curr_txpow) {
1961 ch_info->curr_txpow = max_power;
1962
1963 /* this considers the h/w clipping limitations */
bb8c093b 1964 iwl3945_hw_reg_set_new_power(priv, ch_info);
b481de9c
ZY		 1965 }
1966 }
1967
1968 /* update txpower settings for all channels,
1969 * send to NIC if associated. */
1970 is_temp_calib_needed(priv);
bb8c093b 1971 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 1972
1973 return 0;
1974}
1975
1976/* will add 3945 channel switch cmd handling later */
4a8a4322 1977int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
b481de9c
ZY		 1978{
1979 return 0;
1980}
1981
1982/**
1983 * iwl3945_reg_txpower_periodic - called when time to check our temperature.
1984 *
1985 * -- reset periodic timer
1986 * -- see if temp has changed enough to warrant re-calibration ... if so:
1987 * -- correct coeffs for temp (can reset temp timer)
1988 * -- save this temp as "last",
1989 * -- send new set of gain settings to NIC
1990 * NOTE: This should continue working, even when we're not associated,
1991 * so we can keep our internal table of scan powers current. */
4a8a4322 1992void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
b481de9c
ZY		 1993{
1994 /* This will kick in the "brute force"
bb8c093b 1995 * iwl3945_hw_reg_comp_txpower_temp() below */
b481de9c
ZY		 1996 if (!is_temp_calib_needed(priv))
1997 goto reschedule;
1998
1999 /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2000 * This is based *only* on current temperature,
2001 * ignoring any previous power measurements */
bb8c093b 2002 iwl3945_hw_reg_comp_txpower_temp(priv);
b481de9c
ZY		 2003
2004 reschedule:
2005 queue_delayed_work(priv->workqueue,
2006 &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2007}
2008
416e1438 2009static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
b481de9c 2010{
4a8a4322 2011 struct iwl_priv *priv = container_of(work, struct iwl_priv,
b481de9c
ZY		 2012 thermal_periodic.work);
2013
2014 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2015 return;
2016
2017 mutex_lock(&priv->mutex);
2018 iwl3945_reg_txpower_periodic(priv);
2019 mutex_unlock(&priv->mutex);
2020}
2021
2022/**
bb8c093b 2023 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
b481de9c
ZY		 2024 * for the channel.
2025 *
2026 * This function is used when initializing channel-info structs.
2027 *
2028 * NOTE: These channel groups do *NOT* match the bands above!
2029 * These channel groups are based on factory-tested channels;
2030 * on A-band, EEPROM's "group frequency" entries represent the top
2031 * channel in each group 1-4. Group 5 All B/G channels are in group 0.
2032 */
4a8a4322 2033static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
d20b3c65 2034 const struct iwl_channel_info *ch_info)
b481de9c 2035{
f2c7e521 2036 struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom39.groups[0];
b481de9c
ZY		 2037 u8 group;
2038 u16 group_index = 0; /* based on factory calib frequencies */
2039 u8 grp_channel;
2040
2041 /* Find the group index for the channel ... don't use index 1(?) */
2042 if (is_channel_a_band(ch_info)) {
2043 for (group = 1; group < 5; group++) {
2044 grp_channel = ch_grp[group].group_channel;
2045 if (ch_info->channel <= grp_channel) {
2046 group_index = group;
2047 break;
2048 }
2049 }
2050 /* group 4 has a few channels *above* its factory cal freq */
2051 if (group == 5)
2052 group_index = 4;
2053 } else
2054 group_index = 0; /* 2.4 GHz, group 0 */
2055
2056 IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2057 group_index);
2058 return group_index;
2059}
2060
2061/**
bb8c093b 2062 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
b481de9c
ZY		 2063 *
2064 * Interpolate to get nominal (i.e. at factory calibration temperature) index
2065 * into radio/DSP gain settings table for requested power.
2066 */
4a8a4322 2067static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
b481de9c
ZY		 2068 s8 requested_power,
2069 s32 setting_index, s32 *new_index)
2070{
bb8c093b 2071 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
b481de9c
ZY		 2072 s32 index0, index1;
2073 s32 power = 2 * requested_power;
2074 s32 i;
bb8c093b 2075 const struct iwl3945_eeprom_txpower_sample *samples;
b481de9c
ZY		 2076 s32 gains0, gains1;
2077 s32 res;
2078 s32 denominator;
2079
f2c7e521 2080 chnl_grp = &priv->eeprom39.groups[setting_index];
b481de9c
ZY		 2081 samples = chnl_grp->samples;
2082 for (i = 0; i < 5; i++) {
2083 if (power == samples[i].power) {
2084 *new_index = samples[i].gain_index;
2085 return 0;
2086 }
2087 }
2088
2089 if (power > samples[1].power) {
2090 index0 = 0;
2091 index1 = 1;
2092 } else if (power > samples[2].power) {
2093 index0 = 1;
2094 index1 = 2;
2095 } else if (power > samples[3].power) {
2096 index0 = 2;
2097 index1 = 3;
2098 } else {
2099 index0 = 3;
2100 index1 = 4;
2101 }
2102
2103 denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2104 if (denominator == 0)
2105 return -EINVAL;
2106 gains0 = (s32) samples[index0].gain_index * (1 << 19);
2107 gains1 = (s32) samples[index1].gain_index * (1 << 19);
2108 res = gains0 + (gains1 - gains0) *
2109 ((s32) power - (s32) samples[index0].power) / denominator +
2110 (1 << 18);
2111 *new_index = res >> 19;
2112 return 0;
2113}
2114
4a8a4322 2115static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
b481de9c
ZY		 2116{
2117 u32 i;
2118 s32 rate_index;
bb8c093b 2119 const struct iwl3945_eeprom_txpower_group *group;
b481de9c
ZY		 2120
2121 IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2122
2123 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2124 s8 *clip_pwrs; /* table of power levels for each rate */
2125 s8 satur_pwr; /* saturation power for each chnl group */
f2c7e521 2126 group = &priv->eeprom39.groups[i];
b481de9c
ZY		 2127
2128 /* sanity check on factory saturation power value */
2129 if (group->saturation_power < 40) {
39aadf8c 2130 IWL_WARN(priv, "Error: saturation power is %d, "
b481de9c
ZY		 2131 "less than minimum expected 40\n",
2132 group->saturation_power);
2133 return;
2134 }
2135
2136 /*
2137 * Derive requested power levels for each rate, based on
2138 * hardware capabilities (saturation power for band).
2139 * Basic value is 3dB down from saturation, with further
2140 * power reductions for highest 3 data rates. These
2141 * backoffs provide headroom for high rate modulation
2142 * power peaks, without too much distortion (clipping).
2143 */
2144 /* we'll fill in this array with h/w max power levels */
f2c7e521 2145 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
b481de9c
ZY		 2146
2147 /* divide factory saturation power by 2 to find -3dB level */
2148 satur_pwr = (s8) (group->saturation_power >> 1);
2149
2150 /* fill in channel group's nominal powers for each rate */
2151 for (rate_index = 0;
2152 rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2153 switch (rate_index) {
14577f23 2154 case IWL_RATE_36M_INDEX_TABLE:
b481de9c
ZY		 2155 if (i == 0) /* B/G */
2156 *clip_pwrs = satur_pwr;
2157 else /* A */
2158 *clip_pwrs = satur_pwr - 5;
2159 break;
14577f23 2160 case IWL_RATE_48M_INDEX_TABLE:
b481de9c
ZY		 2161 if (i == 0)
2162 *clip_pwrs = satur_pwr - 7;
2163 else
2164 *clip_pwrs = satur_pwr - 10;
2165 break;
14577f23 2166 case IWL_RATE_54M_INDEX_TABLE:
b481de9c
ZY		 2167 if (i == 0)
2168 *clip_pwrs = satur_pwr - 9;
2169 else
2170 *clip_pwrs = satur_pwr - 12;
2171 break;
2172 default:
2173 *clip_pwrs = satur_pwr;
2174 break;
2175 }
2176 }
2177 }
2178}
2179
2180/**
2181 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2182 *
2183 * Second pass (during init) to set up priv->channel_info
2184 *
2185 * Set up Tx-power settings in our channel info database for each VALID
2186 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2187 * and current temperature.
2188 *
2189 * Since this is based on current temperature (at init time), these values may
2190 * not be valid for very long, but it gives us a starting/default point,
2191 * and allows us to active (i.e. using Tx) scan.
2192 *
2193 * This does *not* write values to NIC, just sets up our internal table.
2194 */
4a8a4322 2195int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
b481de9c 2196{
d20b3c65 2197 struct iwl_channel_info *ch_info = NULL;
bb8c093b 2198 struct iwl3945_channel_power_info *pwr_info;
b481de9c
ZY		 2199 int delta_index;
2200 u8 rate_index;
2201 u8 scan_tbl_index;
2202 const s8 *clip_pwrs; /* array of power levels for each rate */
2203 u8 gain, dsp_atten;
2204 s8 power;
2205 u8 pwr_index, base_pwr_index, a_band;
2206 u8 i;
2207 int temperature;
2208
2209 /* save temperature reference,
2210 * so we can determine next time to calibrate */
bb8c093b 2211 temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
b481de9c
ZY		 2212 priv->last_temperature = temperature;
2213
bb8c093b 2214 iwl3945_hw_reg_init_channel_groups(priv);
b481de9c
ZY		 2215
2216 /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2217 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2218 i++, ch_info++) {
2219 a_band = is_channel_a_band(ch_info);
2220 if (!is_channel_valid(ch_info))
2221 continue;
2222
2223 /* find this channel's channel group (*not* "band") index */
2224 ch_info->group_index =
bb8c093b 2225 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
b481de9c
ZY		 2226
2227 /* Get this chnlgrp's rate->max/clip-powers table */
f2c7e521 2228 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
b481de9c
ZY		 2229
2230 /* calculate power index *adjustment* value according to
2231 * diff between current temperature and factory temperature */
bb8c093b 2232 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
f2c7e521 2233 priv->eeprom39.groups[ch_info->group_index].
b481de9c
ZY		 2234 temperature);
2235
2236 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2237 ch_info->channel, delta_index, temperature +
2238 IWL_TEMP_CONVERT);
2239
2240 /* set tx power value for all OFDM rates */
2241 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2242 rate_index++) {
25a4ccea 2243 s32 uninitialized_var(power_idx);
b481de9c
ZY		 2244 int rc;
2245
2246 /* use channel group's clip-power table,
2247 * but don't exceed channel's max power */
2248 s8 pwr = min(ch_info->max_power_avg,
2249 clip_pwrs[rate_index]);
2250
2251 pwr_info = &ch_info->power_info[rate_index];
2252
2253 /* get base (i.e. at factory-measured temperature)
2254 * power table index for this rate's power */
bb8c093b 2255 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
b481de9c
ZY		 2256 ch_info->group_index,
2257 &power_idx);
2258 if (rc) {
15b1687c 2259 IWL_ERR(priv, "Invalid power index\n");
b481de9c
ZY		 2260 return rc;
2261 }
2262 pwr_info->base_power_index = (u8) power_idx;
2263
2264 /* temperature compensate */
2265 power_idx += delta_index;
2266
2267 /* stay within range of gain table */
bb8c093b 2268 power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
b481de9c 2269
bb8c093b 2270 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
b481de9c
ZY		 2271 pwr_info->requested_power = pwr;
2272 pwr_info->power_table_index = (u8) power_idx;
2273 pwr_info->tpc.tx_gain =
2274 power_gain_table[a_band][power_idx].tx_gain;
2275 pwr_info->tpc.dsp_atten =
2276 power_gain_table[a_band][power_idx].dsp_atten;
2277 }
2278
2279 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
14577f23 2280 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
b481de9c
ZY		 2281 power = pwr_info->requested_power +
2282 IWL_CCK_FROM_OFDM_POWER_DIFF;
2283 pwr_index = pwr_info->power_table_index +
2284 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2285 base_pwr_index = pwr_info->base_power_index +
2286 IWL_CCK_FROM_OFDM_INDEX_DIFF;
2287
2288 /* stay within table range */
bb8c093b 2289 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
b481de9c
ZY		 2290 gain = power_gain_table[a_band][pwr_index].tx_gain;
2291 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2292
bb8c093b 2293 /* fill each CCK rate's iwl3945_channel_power_info structure
b481de9c
ZY		 2294 * NOTE: All CCK-rate Txpwrs are the same for a given chnl!
2295 * NOTE: CCK rates start at end of OFDM rates! */
14577f23
MA		 2296 for (rate_index = 0;
2297 rate_index < IWL_CCK_RATES; rate_index++) {
2298 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
b481de9c
ZY		 2299 pwr_info->requested_power = power;
2300 pwr_info->power_table_index = pwr_index;
2301 pwr_info->base_power_index = base_pwr_index;
2302 pwr_info->tpc.tx_gain = gain;
2303 pwr_info->tpc.dsp_atten = dsp_atten;
2304 }
2305
2306 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2307 for (scan_tbl_index = 0;
2308 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2309 s32 actual_index = (scan_tbl_index == 0) ?
14577f23 2310 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
bb8c093b 2311 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
b481de9c
ZY		 2312 actual_index, clip_pwrs, ch_info, a_band);
2313 }
2314 }
2315
2316 return 0;
2317}
2318
4a8a4322 2319int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
b481de9c
ZY		 2320{
2321 int rc;
2322 unsigned long flags;
2323
2324 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2325 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2326 if (rc) {
2327 spin_unlock_irqrestore(&priv->lock, flags);
2328 return rc;
2329 }
2330
5d49f498
AK		 2331 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2332 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
bddadf86 2333 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
b481de9c 2334 if (rc < 0)
15b1687c 2335 IWL_ERR(priv, "Can't stop Rx DMA.\n");
b481de9c 2336
5d49f498 2337 iwl_release_nic_access(priv);
b481de9c
ZY		 2338 spin_unlock_irqrestore(&priv->lock, flags);
2339
2340 return 0;
2341}
2342
4a8a4322 2343int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl3945_tx_queue *txq)
b481de9c
ZY		 2344{
2345 int rc;
2346 unsigned long flags;
2347 int txq_id = txq->q.id;
2348
3832ec9d 2349 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2350
2351 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2352
2353 spin_lock_irqsave(&priv->lock, flags);
5d49f498 2354 rc = iwl_grab_nic_access(priv);
b481de9c
ZY		 2355 if (rc) {
2356 spin_unlock_irqrestore(&priv->lock, flags);
2357 return rc;
2358 }
5d49f498
AK		 2359 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2360 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
bddadf86 2361
5d49f498 2362 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
bddadf86
TW		 2363 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2364 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2365 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2366 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2367 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
5d49f498 2368 iwl_release_nic_access(priv);
b481de9c
ZY		 2369
2370 /* fake read to flush all prev. writes */
5d49f498 2371 iwl_read32(priv, FH39_TSSR_CBB_BASE);
b481de9c
ZY		 2372 spin_unlock_irqrestore(&priv->lock, flags);
2373
2374 return 0;
2375}
2376
4a8a4322 2377int iwl3945_hw_get_rx_read(struct iwl_priv *priv)
b481de9c 2378{
3832ec9d 2379 struct iwl3945_shared *shared_data = priv->shared_virt;
b481de9c
ZY		 2380
2381 return le32_to_cpu(shared_data->rx_read_ptr[0]);
2382}
2383
2384/**
2385 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2386 */
4a8a4322 2387int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
b481de9c 2388{
14577f23 2389 int rc, i, index, prev_index;
bb8c093b 2390 struct iwl3945_rate_scaling_cmd rate_cmd = {
b481de9c
ZY		 2391 .reserved = {0, 0, 0},
2392 };
bb8c093b 2393 struct iwl3945_rate_scaling_info *table = rate_cmd.table;
b481de9c 2394
bb8c093b
CH		 2395 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2396 index = iwl3945_rates[i].table_rs_index;
14577f23
MA		 2397
2398 table[index].rate_n_flags =
bb8c093b 2399 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
14577f23 2400 table[index].try_cnt = priv->retry_rate;
bb8c093b 2401 prev_index = iwl3945_get_prev_ieee_rate(i);
7262796a
AM		 2402 table[index].next_rate_index =
2403 iwl3945_rates[prev_index].table_rs_index;
b481de9c
ZY		 2404 }
2405
8318d78a
JB		 2406 switch (priv->band) {
2407 case IEEE80211_BAND_5GHZ:
b481de9c
ZY		 2408 IWL_DEBUG_RATE("Select A mode rate scale\n");
2409 /* If one of the following CCK rates is used,
2410 * have it fall back to the 6M OFDM rate */
7262796a
AM		 2411 for (i = IWL_RATE_1M_INDEX_TABLE;
2412 i <= IWL_RATE_11M_INDEX_TABLE; i++)
2413 table[i].next_rate_index =
2414 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2415
2416 /* Don't fall back to CCK rates */
7262796a
AM		 2417 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2418 IWL_RATE_9M_INDEX_TABLE;
b481de9c
ZY		 2419
2420 /* Don't drop out of OFDM rates */
14577f23 2421 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
bb8c093b 2422 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
b481de9c
ZY		 2423 break;
2424
8318d78a
JB		 2425 case IEEE80211_BAND_2GHZ:
2426 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
b481de9c
ZY		 2427 /* If an OFDM rate is used, have it fall back to the
2428 * 1M CCK rates */
b481de9c 2429
7262796a
AM		 2430 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2431 iwl3945_is_associated(priv)) {
2432
2433 index = IWL_FIRST_CCK_RATE;
2434 for (i = IWL_RATE_6M_INDEX_TABLE;
2435 i <= IWL_RATE_54M_INDEX_TABLE; i++)
2436 table[i].next_rate_index =
2437 iwl3945_rates[index].table_rs_index;
2438
2439 index = IWL_RATE_11M_INDEX_TABLE;
2440 /* CCK shouldn't fall back to OFDM... */
2441 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2442 }
b481de9c
ZY		 2443 break;
2444
2445 default:
8318d78a 2446 WARN_ON(1);
b481de9c
ZY		 2447 break;
2448 }
2449
2450 /* Update the rate scaling for control frame Tx */
2451 rate_cmd.table_id = 0;
bb8c093b 2452 rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2453 &rate_cmd);
2454 if (rc)
2455 return rc;
2456
2457 /* Update the rate scaling for data frame Tx */
2458 rate_cmd.table_id = 1;
bb8c093b 2459 return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
b481de9c
ZY		 2460 &rate_cmd);
2461}
2462
796083cb 2463/* Called when initializing driver */
4a8a4322 2464int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
b481de9c 2465{
3832ec9d
AK		 2466 memset((void *)&priv->hw_params, 0,
2467 sizeof(struct iwl_hw_params));
b481de9c 2468
3832ec9d 2469 priv->shared_virt =
b481de9c 2470 pci_alloc_consistent(priv->pci_dev,
bb8c093b 2471 sizeof(struct iwl3945_shared),
3832ec9d 2472 &priv->shared_phys);
b481de9c 2473
3832ec9d 2474 if (!priv->shared_virt) {
15b1687c 2475 IWL_ERR(priv, "failed to allocate pci memory\n");
b481de9c
ZY		 2476 mutex_unlock(&priv->mutex);
2477 return -ENOMEM;
2478 }
2479
3832ec9d
AK		 2480 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE;
2481 priv->hw_params.max_pkt_size = 2342;
2482 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2483 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2484 priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2485 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
3e82a822 2486
3832ec9d 2487 priv->hw_params.tx_ant_num = 2;
b481de9c
ZY		 2488 return 0;
2489}
2490
4a8a4322 2491unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
bb8c093b 2492 struct iwl3945_frame *frame, u8 rate)
b481de9c 2493{
bb8c093b 2494 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
b481de9c
ZY		 2495 unsigned int frame_size;
2496
bb8c093b 2497 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
b481de9c
ZY		 2498 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2499
3832ec9d 2500 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
b481de9c
ZY		 2501 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2502
bb8c093b 2503 frame_size = iwl3945_fill_beacon_frame(priv,
b481de9c 2504 tx_beacon_cmd->frame,
b481de9c
ZY		 2505 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2506
2507 BUG_ON(frame_size > MAX_MPDU_SIZE);
2508 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2509
2510 tx_beacon_cmd->tx.rate = rate;
2511 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2512 TX_CMD_FLG_TSF_MSK);
2513
14577f23
MA		 2514 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2515 tx_beacon_cmd->tx.supp_rates[0] =
2516 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2517
b481de9c 2518 tx_beacon_cmd->tx.supp_rates[1] =
14577f23 2519 (IWL_CCK_BASIC_RATES_MASK & 0xF);
b481de9c 2520
3ac7f146 2521 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
b481de9c
ZY		 2522}
2523
4a8a4322 2524void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
b481de9c 2525{
91c066f2 2526 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
b481de9c
ZY		 2527 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2528}
2529
4a8a4322 2530void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2531{
2532 INIT_DELAYED_WORK(&priv->thermal_periodic,
2533 iwl3945_bg_reg_txpower_periodic);
2534}
2535
4a8a4322 2536void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
b481de9c
ZY		 2537{
2538 cancel_delayed_work(&priv->thermal_periodic);
2539}
2540
0164b9b4
KA		 2541/* check contents of special bootstrap uCode SRAM */
2542static int iwl3945_verify_bsm(struct iwl_priv *priv)
2543 {
2544 __le32 *image = priv->ucode_boot.v_addr;
2545 u32 len = priv->ucode_boot.len;
2546 u32 reg;
2547 u32 val;
2548
2549 IWL_DEBUG_INFO("Begin verify bsm\n");
2550
2551 /* verify BSM SRAM contents */
2552 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2553 for (reg = BSM_SRAM_LOWER_BOUND;
2554 reg < BSM_SRAM_LOWER_BOUND + len;
2555 reg += sizeof(u32), image++) {
2556 val = iwl_read_prph(priv, reg);
2557 if (val != le32_to_cpu(*image)) {
2558 IWL_ERR(priv, "BSM uCode verification failed at "
2559 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2560 BSM_SRAM_LOWER_BOUND,
2561 reg - BSM_SRAM_LOWER_BOUND, len,
2562 val, le32_to_cpu(*image));
2563 return -EIO;
2564 }
2565 }
2566
2567 IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2568
2569 return 0;
2570}
2571
2572 /**
2573 * iwl3945_load_bsm - Load bootstrap instructions
2574 *
2575 * BSM operation:
2576 *
2577 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2578 * in special SRAM that does not power down during RFKILL. When powering back
2579 * up after power-saving sleeps (or during initial uCode load), the BSM loads
2580 * the bootstrap program into the on-board processor, and starts it.
2581 *
2582 * The bootstrap program loads (via DMA) instructions and data for a new
2583 * program from host DRAM locations indicated by the host driver in the
2584 * BSM_DRAM_* registers. Once the new program is loaded, it starts
2585 * automatically.
2586 *
2587 * When initializing the NIC, the host driver points the BSM to the
2588 * "initialize" uCode image. This uCode sets up some internal data, then
2589 * notifies host via "initialize alive" that it is complete.
2590 *
2591 * The host then replaces the BSM_DRAM_* pointer values to point to the
2592 * normal runtime uCode instructions and a backup uCode data cache buffer
2593 * (filled initially with starting data values for the on-board processor),
2594 * then triggers the "initialize" uCode to load and launch the runtime uCode,
2595 * which begins normal operation.
2596 *
2597 * When doing a power-save shutdown, runtime uCode saves data SRAM into
2598 * the backup data cache in DRAM before SRAM is powered down.
2599 *
2600 * When powering back up, the BSM loads the bootstrap program. This reloads
2601 * the runtime uCode instructions and the backup data cache into SRAM,
2602 * and re-launches the runtime uCode from where it left off.
2603 */
2604static int iwl3945_load_bsm(struct iwl_priv *priv)
2605{
2606 __le32 *image = priv->ucode_boot.v_addr;
2607 u32 len = priv->ucode_boot.len;
2608 dma_addr_t pinst;
2609 dma_addr_t pdata;
2610 u32 inst_len;
2611 u32 data_len;
2612 int rc;
2613 int i;
2614 u32 done;
2615 u32 reg_offset;
2616
2617 IWL_DEBUG_INFO("Begin load bsm\n");
2618
2619 /* make sure bootstrap program is no larger than BSM's SRAM size */
2620 if (len > IWL39_MAX_BSM_SIZE)
2621 return -EINVAL;
2622
2623 /* Tell bootstrap uCode where to find the "Initialize" uCode
2624 * in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2625 * NOTE: iwl3945_initialize_alive_start() will replace these values,
2626 * after the "initialize" uCode has run, to point to
2627 * runtime/protocol instructions and backup data cache. */
2628 pinst = priv->ucode_init.p_addr;
2629 pdata = priv->ucode_init_data.p_addr;
2630 inst_len = priv->ucode_init.len;
2631 data_len = priv->ucode_init_data.len;
2632
2633 rc = iwl_grab_nic_access(priv);
2634 if (rc)
2635 return rc;
2636
2637 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2638 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2639 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2640 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2641
2642 /* Fill BSM memory with bootstrap instructions */
2643 for (reg_offset = BSM_SRAM_LOWER_BOUND;
2644 reg_offset < BSM_SRAM_LOWER_BOUND + len;
2645 reg_offset += sizeof(u32), image++)
2646 _iwl_write_prph(priv, reg_offset,
2647 le32_to_cpu(*image));
2648
2649 rc = iwl3945_verify_bsm(priv);
2650 if (rc) {
2651 iwl_release_nic_access(priv);
2652 return rc;
2653 }
2654
2655 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2656 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2657 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2658 IWL39_RTC_INST_LOWER_BOUND);
2659 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2660
2661 /* Load bootstrap code into instruction SRAM now,
2662 * to prepare to load "initialize" uCode */
2663 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2664 BSM_WR_CTRL_REG_BIT_START);
2665
2666 /* Wait for load of bootstrap uCode to finish */
2667 for (i = 0; i < 100; i++) {
2668 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2669 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2670 break;
2671 udelay(10);
2672 }
2673 if (i < 100)
2674 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2675 else {
2676 IWL_ERR(priv, "BSM write did not complete!\n");
2677 return -EIO;
2678 }
2679
2680 /* Enable future boot loads whenever power management unit triggers it
2681 * (e.g. when powering back up after power-save shutdown) */
2682 iwl_write_prph(priv, BSM_WR_CTRL_REG,
2683 BSM_WR_CTRL_REG_BIT_START_EN);
2684
2685 iwl_release_nic_access(priv);
2686
2687 return 0;
2688}
2689
2690static struct iwl_lib_ops iwl3945_lib = {
2691 .load_ucode = iwl3945_load_bsm,
01ec616d
KA		 2692 .apm_ops = {
2693 .init = iwl3945_apm_init,
2694 .reset = iwl3945_apm_reset,
2695 .stop = iwl3945_apm_stop,
2696 .config = iwl3945_nic_config,
2697 },
0164b9b4
KA		 2698};
2699
2700static struct iwl_ops iwl3945_ops = {
2701 .lib = &iwl3945_lib,
2702};
2703
c0f20d91 2704static struct iwl_cfg iwl3945_bg_cfg = {
82b9a121 2705 .name = "3945BG",
a0987a8d
RC		 2706 .fw_name_pre = IWL3945_FW_PRE,
2707 .ucode_api_max = IWL3945_UCODE_API_MAX,
2708 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2709 .sku = IWL_SKU_G,
0164b9b4 2710 .ops = &iwl3945_ops,
df878d8f 2711 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2712};
2713
c0f20d91 2714static struct iwl_cfg iwl3945_abg_cfg = {
82b9a121 2715 .name = "3945ABG",
a0987a8d
RC		 2716 .fw_name_pre = IWL3945_FW_PRE,
2717 .ucode_api_max = IWL3945_UCODE_API_MAX,
2718 .ucode_api_min = IWL3945_UCODE_API_MIN,
82b9a121 2719 .sku = IWL_SKU_A|IWL_SKU_G,
0164b9b4 2720 .ops = &iwl3945_ops,
df878d8f 2721 .mod_params = &iwl3945_mod_params
82b9a121
TW		 2722};
2723
bb8c093b 2724struct pci_device_id iwl3945_hw_card_ids[] = {
82b9a121
TW		 2725 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2726 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2727 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2728 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2729 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2730 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
b481de9c
ZY		 2731 {0}
2732};
2733
bb8c093b 2734MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);
Clone of davem's net-next-2.6 tree