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b43: N-PHY: move RF sequence declarations top, add missing calls
[net-next-2.6.git] / drivers / net / wireless / b43 / phy_n.c
CommitLineData
424047e6
MB		 1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
819d772b
JL		 25#include <linux/delay.h>
26#include <linux/types.h>
27
424047e6 28#include "b43.h"
3d0da751 29#include "phy_n.h"
53a6e234 30#include "tables_nphy.h"
bbec398c 31#include "main.h"
424047e6 32
f8187b5b
RM		 33struct nphy_txgains {
34 u16 txgm[2];
35 u16 pga[2];
36 u16 pad[2];
37 u16 ipa[2];
38};
39
40struct nphy_iqcal_params {
41 u16 txgm;
42 u16 pga;
43 u16 pad;
44 u16 ipa;
45 u16 cal_gain;
46 u16 ncorr[5];
47};
48
49struct nphy_iq_est {
50 s32 iq0_prod;
51 u32 i0_pwr;
52 u32 q0_pwr;
53 s32 iq1_prod;
54 u32 i1_pwr;
55 u32 q1_pwr;
56};
424047e6 57
67c0d6e2
RM		 58enum b43_nphy_rf_sequence {
59 B43_RFSEQ_RX2TX,
60 B43_RFSEQ_TX2RX,
61 B43_RFSEQ_RESET2RX,
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
65};
66
67static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
68 enum b43_nphy_rf_sequence seq);
69
53a6e234
MB		 70void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
71{//TODO
72}
73
18c8adeb 74static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
53a6e234
MB		 75{//TODO
76}
77
18c8adeb
MB		 78static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
79 bool ignore_tssi)
80{//TODO
81 return B43_TXPWR_RES_DONE;
82}
83
d1591314
MB		 84static void b43_chantab_radio_upload(struct b43_wldev *dev,
85 const struct b43_nphy_channeltab_entry *e)
86{
87 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
88 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
89 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
90 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
91 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
92 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
93 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
94 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
95 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
96 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
97 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
98 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
99 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
100 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
101 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
102 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
103 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
104 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
105 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
106 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
107 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
108 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
109}
110
111static void b43_chantab_phy_upload(struct b43_wldev *dev,
112 const struct b43_nphy_channeltab_entry *e)
113{
114 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
115 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
116 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
117 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
118 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
119 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
120}
121
122static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
123{
124 //TODO
125}
126
ef1a628d
MB		 127/* Tune the hardware to a new channel. */
128static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
53a6e234 129{
d1591314
MB		 130 const struct b43_nphy_channeltab_entry *tabent;
131
132 tabent = b43_nphy_get_chantabent(dev, channel);
133 if (!tabent)
134 return -ESRCH;
135
136 //FIXME enable/disable band select upper20 in RXCTL
137 if (0 /*FIXME 5Ghz*/)
138 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
139 else
140 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
141 b43_chantab_radio_upload(dev, tabent);
142 udelay(50);
143 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
144 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
145 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
146 udelay(300);
147 if (0 /*FIXME 5Ghz*/)
148 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
149 else
150 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
151 b43_chantab_phy_upload(dev, tabent);
152 b43_nphy_tx_power_fix(dev);
53a6e234 153
d1591314 154 return 0;
53a6e234
MB		 155}
156
157static void b43_radio_init2055_pre(struct b43_wldev *dev)
158{
159 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
160 ~B43_NPHY_RFCTL_CMD_PORFORCE);
161 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
162 B43_NPHY_RFCTL_CMD_CHIP0PU |
163 B43_NPHY_RFCTL_CMD_OEPORFORCE);
164 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
165 B43_NPHY_RFCTL_CMD_PORFORCE);
166}
167
168static void b43_radio_init2055_post(struct b43_wldev *dev)
169{
170 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
171 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
172 int i;
173 u16 val;
174
175 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
176 msleep(1);
738f0f43
GS		 177 if ((sprom->revision != 4) ||
178 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
53a6e234
MB		 179 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
180 (binfo->type != 0x46D) ||
181 (binfo->rev < 0x41)) {
182 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
183 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
184 msleep(1);
185 }
186 }
187 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
188 msleep(1);
189 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
190 msleep(1);
191 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
192 msleep(1);
193 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
194 msleep(1);
195 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
196 msleep(1);
197 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
198 msleep(1);
199 for (i = 0; i < 100; i++) {
200 val = b43_radio_read16(dev, B2055_CAL_COUT2);
201 if (val & 0x80)
202 break;
203 udelay(10);
204 }
205 msleep(1);
206 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
207 msleep(1);
ef1a628d 208 nphy_channel_switch(dev, dev->phy.channel);
53a6e234
MB		 209 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
210 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
211 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
212 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
213}
214
215/* Initialize a Broadcom 2055 N-radio */
216static void b43_radio_init2055(struct b43_wldev *dev)
217{
218 b43_radio_init2055_pre(dev);
219 if (b43_status(dev) < B43_STAT_INITIALIZED)
220 b2055_upload_inittab(dev, 0, 1);
221 else
222 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
223 b43_radio_init2055_post(dev);
224}
225
226void b43_nphy_radio_turn_on(struct b43_wldev *dev)
227{
228 b43_radio_init2055(dev);
229}
230
231void b43_nphy_radio_turn_off(struct b43_wldev *dev)
232{
233 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
234 ~B43_NPHY_RFCTL_CMD_EN);
235}
236
4772ae10
RM		 237/*
238 * Upload the N-PHY tables.
239 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
240 */
95b66bad
MB		 241static void b43_nphy_tables_init(struct b43_wldev *dev)
242{
4772ae10
RM		 243 if (dev->phy.rev < 3)
244 b43_nphy_rev0_1_2_tables_init(dev);
245 else
246 b43_nphy_rev3plus_tables_init(dev);
95b66bad
MB		 247}
248
249static void b43_nphy_workarounds(struct b43_wldev *dev)
250{
251 struct b43_phy *phy = &dev->phy;
252 unsigned int i;
253
254 b43_phy_set(dev, B43_NPHY_IQFLIP,
255 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
95b66bad
MB		 256 if (1 /* FIXME band is 2.4GHz */) {
257 b43_phy_set(dev, B43_NPHY_CLASSCTL,
258 B43_NPHY_CLASSCTL_CCKEN);
259 } else {
260 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
261 ~B43_NPHY_CLASSCTL_CCKEN);
262 }
263 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
264 b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
265
266 /* Fixup some tables */
267 b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
268 b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
269 b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
270 b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
271 b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
272 b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
273 b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
274 b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
275 b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
276 b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
277
278 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
279 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
280 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
281 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
282
283 //TODO set RF sequence
284
285 /* Set narrowband clip threshold */
286 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
287 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
288
289 /* Set wideband clip 2 threshold */
290 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
291 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
292 21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
293 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
294 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
295 21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
296
297 /* Set Clip 2 detect */
298 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
299 B43_NPHY_C1_CGAINI_CL2DETECT);
300 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
301 B43_NPHY_C2_CGAINI_CL2DETECT);
302
303 if (0 /*FIXME*/) {
304 /* Set dwell lengths */
305 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
306 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
307 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
308 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
309
310 /* Set gain backoff */
311 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
312 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
313 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
314 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
315 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
316 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
317
318 /* Set HPVGA2 index */
319 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
320 ~B43_NPHY_C1_INITGAIN_HPVGA2,
321 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
322 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
323 ~B43_NPHY_C2_INITGAIN_HPVGA2,
324 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
325
326 //FIXME verify that the specs really mean to use autoinc here.
327 for (i = 0; i < 3; i++)
328 b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
329 }
330
331 /* Set minimum gain value */
332 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
333 ~B43_NPHY_C1_MINGAIN,
334 23 << B43_NPHY_C1_MINGAIN_SHIFT);
335 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
336 ~B43_NPHY_C2_MINGAIN,
337 23 << B43_NPHY_C2_MINGAIN_SHIFT);
338
339 if (phy->rev < 2) {
340 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
341 ~B43_NPHY_SCRAM_SIGCTL_SCM);
342 }
343
344 /* Set phase track alpha and beta */
345 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
346 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
347 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
348 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
349 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
350 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
351}
352
e50cbcf6
RM		 353/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
354static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
355{
356 struct b43_phy_n *nphy = dev->phy.n;
357 enum ieee80211_band band;
358 u16 tmp;
359
360 if (!enable) {
361 nphy->rfctrl_intc1_save = b43_phy_read(dev,
362 B43_NPHY_RFCTL_INTC1);
363 nphy->rfctrl_intc2_save = b43_phy_read(dev,
364 B43_NPHY_RFCTL_INTC2);
365 band = b43_current_band(dev->wl);
366 if (dev->phy.rev >= 3) {
367 if (band == IEEE80211_BAND_5GHZ)
368 tmp = 0x600;
369 else
370 tmp = 0x480;
371 } else {
372 if (band == IEEE80211_BAND_5GHZ)
373 tmp = 0x180;
374 else
375 tmp = 0x120;
376 }
377 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
378 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
379 } else {
380 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
381 nphy->rfctrl_intc1_save);
382 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
383 nphy->rfctrl_intc2_save);
384 }
385}
386
fe3e46e8
RM		 387/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
388static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
389{
390 struct b43_phy_n *nphy = dev->phy.n;
391 u16 tmp;
392 enum ieee80211_band band = b43_current_band(dev->wl);
393 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
394 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
395
396 if (dev->phy.rev >= 3) {
397 if (ipa) {
398 tmp = 4;
399 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
400 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
401 }
402
403 tmp = 1;
404 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
405 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
406 }
407}
408
4a933c85
RM		 409/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
410static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
411{
412 u32 tmslow;
413
414 if (dev->phy.type != B43_PHYTYPE_N)
415 return;
416
417 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
418 if (force)
419 tmslow |= SSB_TMSLOW_FGC;
420 else
421 tmslow &= ~SSB_TMSLOW_FGC;
422 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
423}
424
425/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
95b66bad
MB		 426static void b43_nphy_reset_cca(struct b43_wldev *dev)
427{
428 u16 bbcfg;
429
4a933c85 430 b43_nphy_bmac_clock_fgc(dev, 1);
95b66bad 431 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
4a933c85
RM		 432 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
433 udelay(1);
434 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
435 b43_nphy_bmac_clock_fgc(dev, 0);
67c0d6e2 436 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
95b66bad
MB		 437}
438
ad9716e8
RM		 439/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
440static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
441{
442 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
443
444 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
445 if (preamble == 1)
446 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
447 else
448 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
449
450 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
451}
452
4f4ab6cd
RM		 453/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
454static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
455{
456 struct b43_phy_n *nphy = dev->phy.n;
457
458 bool override = false;
459 u16 chain = 0x33;
460
461 if (nphy->txrx_chain == 0) {
462 chain = 0x11;
463 override = true;
464 } else if (nphy->txrx_chain == 1) {
465 chain = 0x22;
466 override = true;
467 }
468
469 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
470 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
471 chain);
472
473 if (override)
474 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
475 B43_NPHY_RFSEQMODE_CAOVER);
476 else
477 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
478 ~B43_NPHY_RFSEQMODE_CAOVER);
479}
480
2faa6b83
RM		 481/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
482static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
483 u16 samps, u8 time, bool wait)
484{
485 int i;
486 u16 tmp;
487
488 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
489 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
490 if (wait)
491 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
492 else
493 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
494
495 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
496
497 for (i = 1000; i; i--) {
498 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
499 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
500 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
501 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
502 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
503 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
504 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
505 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
506
507 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
508 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
509 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
510 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
511 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
512 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
513 return;
514 }
515 udelay(10);
516 }
517 memset(est, 0, sizeof(*est));
518}
519
a67162ab
RM		 520/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
521static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
522 struct b43_phy_n_iq_comp *pcomp)
523{
524 if (write) {
525 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
526 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
527 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
528 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
529 } else {
530 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
531 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
532 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
533 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
534 }
535}
536
026816fc
RM		 537/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
538static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
539{
540 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
541
542 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
543 if (core == 0) {
544 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
545 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
546 } else {
547 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
548 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
549 }
550 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
551 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
552 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
553 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
554 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
555 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
556 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
557 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
558}
559
560/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
561static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
562{
563 u8 rxval, txval;
564 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
565
566 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
567 if (core == 0) {
568 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
569 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
570 } else {
571 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
572 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
573 }
574 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
575 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
576 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
577 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
578 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
579 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
580 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
581 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
582
583 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
584 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
585
586 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
587 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
588 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
589 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
590 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
591 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
592 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
593 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
594
595 if (core == 0) {
596 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
597 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
598 } else {
599 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
600 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
601 }
602
603 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
604 /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
67c0d6e2 605 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
026816fc
RM		 606
607 if (core == 0) {
608 rxval = 1;
609 txval = 8;
610 } else {
611 rxval = 4;
612 txval = 2;
613 }
614
615 /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
616 /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
617}
618
34a56f2c
RM		 619/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
620static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
621{
622 int i;
623 s32 iq;
624 u32 ii;
625 u32 qq;
626 int iq_nbits, qq_nbits;
627 int arsh, brsh;
628 u16 tmp, a, b;
629
630 struct nphy_iq_est est;
631 struct b43_phy_n_iq_comp old;
632 struct b43_phy_n_iq_comp new = { };
633 bool error = false;
634
635 if (mask == 0)
636 return;
637
638 b43_nphy_rx_iq_coeffs(dev, false, &old);
639 b43_nphy_rx_iq_coeffs(dev, true, &new);
640 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
641 new = old;
642
643 for (i = 0; i < 2; i++) {
644 if (i == 0 && (mask & 1)) {
645 iq = est.iq0_prod;
646 ii = est.i0_pwr;
647 qq = est.q0_pwr;
648 } else if (i == 1 && (mask & 2)) {
649 iq = est.iq1_prod;
650 ii = est.i1_pwr;
651 qq = est.q1_pwr;
652 } else {
653 B43_WARN_ON(1);
654 continue;
655 }
656
657 if (ii + qq < 2) {
658 error = true;
659 break;
660 }
661
662 iq_nbits = fls(abs(iq));
663 qq_nbits = fls(qq);
664
665 arsh = iq_nbits - 20;
666 if (arsh >= 0) {
667 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
668 tmp = ii >> arsh;
669 } else {
670 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
671 tmp = ii << -arsh;
672 }
673 if (tmp == 0) {
674 error = true;
675 break;
676 }
677 a /= tmp;
678
679 brsh = qq_nbits - 11;
680 if (brsh >= 0) {
681 b = (qq << (31 - qq_nbits));
682 tmp = ii >> brsh;
683 } else {
684 b = (qq << (31 - qq_nbits));
685 tmp = ii << -brsh;
686 }
687 if (tmp == 0) {
688 error = true;
689 break;
690 }
691 b = int_sqrt(b / tmp - a * a) - (1 << 10);
692
693 if (i == 0 && (mask & 0x1)) {
694 if (dev->phy.rev >= 3) {
695 new.a0 = a & 0x3FF;
696 new.b0 = b & 0x3FF;
697 } else {
698 new.a0 = b & 0x3FF;
699 new.b0 = a & 0x3FF;
700 }
701 } else if (i == 1 && (mask & 0x2)) {
702 if (dev->phy.rev >= 3) {
703 new.a1 = a & 0x3FF;
704 new.b1 = b & 0x3FF;
705 } else {
706 new.a1 = b & 0x3FF;
707 new.b1 = a & 0x3FF;
708 }
709 }
710 }
711
712 if (error)
713 new = old;
714
715 b43_nphy_rx_iq_coeffs(dev, true, &new);
716}
717
09146400
RM		 718/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
719static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
720{
721 u16 array[4];
722 int i;
723
724 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
725 for (i = 0; i < 4; i++)
726 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
727
728 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
729 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
730 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
731 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
732}
733
bbec398c
RM		 734/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
735static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
736{
737 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
738 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
739}
740
741/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
742static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
743{
744 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
745 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
746}
747
748/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
749static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
750{
751 u16 tmp;
752
753 if (dev->dev->id.revision == 16)
754 b43_mac_suspend(dev);
755
756 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
757 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
758 B43_NPHY_CLASSCTL_WAITEDEN);
759 tmp &= ~mask;
760 tmp |= (val & mask);
761 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
762
763 if (dev->dev->id.revision == 16)
764 b43_mac_enable(dev);
765
766 return tmp;
767}
768
5c1a140a
RM		 769/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
770static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
771{
772 struct b43_phy *phy = &dev->phy;
773 struct b43_phy_n *nphy = phy->n;
774
775 if (enable) {
776 u16 clip[] = { 0xFFFF, 0xFFFF };
777 if (nphy->deaf_count++ == 0) {
778 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
779 b43_nphy_classifier(dev, 0x7, 0);
780 b43_nphy_read_clip_detection(dev, nphy->clip_state);
781 b43_nphy_write_clip_detection(dev, clip);
782 }
783 b43_nphy_reset_cca(dev);
784 } else {
785 if (--nphy->deaf_count == 0) {
786 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
787 b43_nphy_write_clip_detection(dev, nphy->clip_state);
788 }
789 }
790}
791
53ae8e8c
RM		 792/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
793static void b43_nphy_stop_playback(struct b43_wldev *dev)
794{
795 struct b43_phy_n *nphy = dev->phy.n;
796 u16 tmp;
797
798 if (nphy->hang_avoid)
799 b43_nphy_stay_in_carrier_search(dev, 1);
800
801 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
802 if (tmp & 0x1)
803 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
804 else if (tmp & 0x2)
805 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
806
807 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
808
809 if (nphy->bb_mult_save & 0x80000000) {
810 tmp = nphy->bb_mult_save & 0xFFFF;
811 /* TODO: Write an N PHY Table with ID 15, length 1, offset 87,
812 width 16 and data from tmp */
813 nphy->bb_mult_save = 0;
814 }
815
816 if (nphy->hang_avoid)
817 b43_nphy_stay_in_carrier_search(dev, 0);
818}
819
6dcd9d91
RM		 820/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
821static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
822{
823 struct b43_phy_n *nphy = dev->phy.n;
824 int i, j;
825 u32 tmp;
826 u32 cur_real, cur_imag, real_part, imag_part;
827
828 u16 buffer[7];
829
830 if (nphy->hang_avoid)
831 b43_nphy_stay_in_carrier_search(dev, true);
832
833 /* TODO: Read an N PHY Table with ID 15, length 7, offset 80,
834 width 16, and data pointer buffer */
835
836 for (i = 0; i < 2; i++) {
837 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
838 (buffer[i * 2 + 1] & 0x3FF);
839 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
840 (((i + 26) << 10) | 320));
841 for (j = 0; j < 128; j++) {
842 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
843 ((tmp >> 16) & 0xFFFF));
844 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
845 (tmp & 0xFFFF));
846 }
847 }
848
849 for (i = 0; i < 2; i++) {
850 tmp = buffer[5 + i];
851 real_part = (tmp >> 8) & 0xFF;
852 imag_part = (tmp & 0xFF);
853 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
854 (((i + 26) << 10) | 448));
855
856 if (dev->phy.rev >= 3) {
857 cur_real = real_part;
858 cur_imag = imag_part;
859 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
860 }
861
862 for (j = 0; j < 128; j++) {
863 if (dev->phy.rev < 3) {
864 cur_real = (real_part * loscale[j] + 128) >> 8;
865 cur_imag = (imag_part * loscale[j] + 128) >> 8;
866 tmp = ((cur_real & 0xFF) << 8) |
867 (cur_imag & 0xFF);
868 }
869 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
870 ((tmp >> 16) & 0xFFFF));
871 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
872 (tmp & 0xFFFF));
873 }
874 }
875
876 if (dev->phy.rev >= 3) {
877 b43_shm_write16(dev, B43_SHM_SHARED,
878 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
879 b43_shm_write16(dev, B43_SHM_SHARED,
880 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
881 }
882
883 if (nphy->hang_avoid)
884 b43_nphy_stay_in_carrier_search(dev, false);
885}
886
67c0d6e2 887/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
95b66bad
MB		 888static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
889 enum b43_nphy_rf_sequence seq)
890{
891 static const u16 trigger[] = {
892 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
893 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
894 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
895 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
896 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
897 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
898 };
899 int i;
900
901 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
902
903 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
904 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
905 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
906 for (i = 0; i < 200; i++) {
907 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
908 goto ok;
909 msleep(1);
910 }
911 b43err(dev->wl, "RF sequence status timeout\n");
912ok:
913 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
914 ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
915}
916
917static void b43_nphy_bphy_init(struct b43_wldev *dev)
918{
919 unsigned int i;
920 u16 val;
921
922 val = 0x1E1F;
923 for (i = 0; i < 14; i++) {
924 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
925 val -= 0x202;
926 }
927 val = 0x3E3F;
928 for (i = 0; i < 16; i++) {
929 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
930 val -= 0x202;
931 }
932 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
933}
934
3c95627d
RM		 935/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
936static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
937 s8 offset, u8 core, u8 rail, u8 type)
938{
939 u16 tmp;
940 bool core1or5 = (core == 1) || (core == 5);
941 bool core2or5 = (core == 2) || (core == 5);
942
943 offset = clamp_val(offset, -32, 31);
944 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
945
946 if (core1or5 && (rail == 0) && (type == 2))
947 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
948 if (core1or5 && (rail == 1) && (type == 2))
949 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
950 if (core2or5 && (rail == 0) && (type == 2))
951 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
952 if (core2or5 && (rail == 1) && (type == 2))
953 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
954 if (core1or5 && (rail == 0) && (type == 0))
955 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
956 if (core1or5 && (rail == 1) && (type == 0))
957 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
958 if (core2or5 && (rail == 0) && (type == 0))
959 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
960 if (core2or5 && (rail == 1) && (type == 0))
961 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
962 if (core1or5 && (rail == 0) && (type == 1))
963 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
964 if (core1or5 && (rail == 1) && (type == 1))
965 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
966 if (core2or5 && (rail == 0) && (type == 1))
967 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
968 if (core2or5 && (rail == 1) && (type == 1))
969 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
970 if (core1or5 && (rail == 0) && (type == 6))
971 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
972 if (core1or5 && (rail == 1) && (type == 6))
973 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
974 if (core2or5 && (rail == 0) && (type == 6))
975 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
976 if (core2or5 && (rail == 1) && (type == 6))
977 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
978 if (core1or5 && (rail == 0) && (type == 3))
979 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
980 if (core1or5 && (rail == 1) && (type == 3))
981 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
982 if (core2or5 && (rail == 0) && (type == 3))
983 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
984 if (core2or5 && (rail == 1) && (type == 3))
985 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
986 if (core1or5 && (type == 4))
987 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
988 if (core2or5 && (type == 4))
989 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
990 if (core1or5 && (type == 5))
991 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
992 if (core2or5 && (type == 5))
993 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
994}
995
996/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
997static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
998{
999 u16 val;
1000
1001 if (dev->phy.rev >= 3) {
1002 /* TODO */
1003 } else {
1004 if (type < 3)
1005 val = 0;
1006 else if (type == 6)
1007 val = 1;
1008 else if (type == 3)
1009 val = 2;
1010 else
1011 val = 3;
1012
1013 val = (val << 12) | (val << 14);
1014 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1015 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1016
1017 if (type < 3) {
1018 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1019 (type + 1) << 4);
1020 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1021 (type + 1) << 4);
1022 }
1023
1024 /* TODO use some definitions */
1025 if (code == 0) {
1026 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1027 if (type < 3) {
1028 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1029 0xFEC7, 0);
1030 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1031 0xEFDC, 0);
1032 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1033 0xFFFE, 0);
1034 udelay(20);
1035 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1036 0xFFFE, 0);
1037 }
1038 } else {
1039 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1040 0x3000);
1041 if (type < 3) {
1042 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1043 0xFEC7, 0x0180);
1044 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1045 0xEFDC, (code << 1 | 0x1021));
1046 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1047 0xFFFE, 0x0001);
1048 udelay(20);
1049 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1050 0xFFFE, 0);
1051 }
1052 }
1053 }
1054}
1055
dfb4aa5d
RM		 1056/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1057static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1058{
1059 int i;
1060 for (i = 0; i < 2; i++) {
1061 if (type == 2) {
1062 if (i == 0) {
1063 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1064 0xFC, buf[0]);
1065 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1066 0xFC, buf[1]);
1067 } else {
1068 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1069 0xFC, buf[2 * i]);
1070 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1071 0xFC, buf[2 * i + 1]);
1072 }
1073 } else {
1074 if (i == 0)
1075 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1076 0xF3, buf[0] << 2);
1077 else
1078 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1079 0xF3, buf[2 * i + 1] << 2);
1080 }
1081 }
1082}
1083
1084/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1085static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1086 u8 nsamp)
1087{
1088 int i;
1089 int out;
1090 u16 save_regs_phy[9];
1091 u16 s[2];
1092
1093 if (dev->phy.rev >= 3) {
1094 save_regs_phy[0] = b43_phy_read(dev,
1095 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1096 save_regs_phy[1] = b43_phy_read(dev,
1097 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1098 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1099 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1100 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1101 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1102 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1103 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1104 }
1105
1106 b43_nphy_rssi_select(dev, 5, type);
1107
1108 if (dev->phy.rev < 2) {
1109 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1110 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1111 }
1112
1113 for (i = 0; i < 4; i++)
1114 buf[i] = 0;
1115
1116 for (i = 0; i < nsamp; i++) {
1117 if (dev->phy.rev < 2) {
1118 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1119 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1120 } else {
1121 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1122 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1123 }
1124
1125 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1126 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1127 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1128 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1129 }
1130 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1131 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1132
1133 if (dev->phy.rev < 2)
1134 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1135
1136 if (dev->phy.rev >= 3) {
1137 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1138 save_regs_phy[0]);
1139 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1140 save_regs_phy[1]);
1141 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1142 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1143 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1144 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1145 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1146 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1147 }
1148
1149 return out;
1150}
1151
4cb99775
RM		 1152/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1153static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
95b66bad 1154{
90b9738d
RM		 1155 int i, j;
1156 u8 state[4];
1157 u8 code, val;
1158 u16 class, override;
1159 u8 regs_save_radio[2];
1160 u16 regs_save_phy[2];
1161 s8 offset[4];
1162
1163 u16 clip_state[2];
1164 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1165 s32 results_min[4] = { };
1166 u8 vcm_final[4] = { };
1167 s32 results[4][4] = { };
1168 s32 miniq[4][2] = { };
1169
1170 if (type == 2) {
1171 code = 0;
1172 val = 6;
1173 } else if (type < 2) {
1174 code = 25;
1175 val = 4;
1176 } else {
1177 B43_WARN_ON(1);
1178 return;
1179 }
1180
1181 class = b43_nphy_classifier(dev, 0, 0);
1182 b43_nphy_classifier(dev, 7, 4);
1183 b43_nphy_read_clip_detection(dev, clip_state);
1184 b43_nphy_write_clip_detection(dev, clip_off);
1185
1186 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1187 override = 0x140;
1188 else
1189 override = 0x110;
1190
1191 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1192 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1193 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1194 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1195
1196 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1197 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1198 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1199 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1200
1201 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1202 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1203 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1204 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1205 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1206 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1207
1208 b43_nphy_rssi_select(dev, 5, type);
1209 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1210 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1211
1212 for (i = 0; i < 4; i++) {
1213 u8 tmp[4];
1214 for (j = 0; j < 4; j++)
1215 tmp[j] = i;
1216 if (type != 1)
1217 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1218 b43_nphy_poll_rssi(dev, type, results[i], 8);
1219 if (type < 2)
1220 for (j = 0; j < 2; j++)
1221 miniq[i][j] = min(results[i][2 * j],
1222 results[i][2 * j + 1]);
1223 }
1224
1225 for (i = 0; i < 4; i++) {
1226 s32 mind = 40;
1227 u8 minvcm = 0;
1228 s32 minpoll = 249;
1229 s32 curr;
1230 for (j = 0; j < 4; j++) {
1231 if (type == 2)
1232 curr = abs(results[j][i]);
1233 else
1234 curr = abs(miniq[j][i / 2] - code * 8);
1235
1236 if (curr < mind) {
1237 mind = curr;
1238 minvcm = j;
1239 }
1240
1241 if (results[j][i] < minpoll)
1242 minpoll = results[j][i];
1243 }
1244 results_min[i] = minpoll;
1245 vcm_final[i] = minvcm;
1246 }
1247
1248 if (type != 1)
1249 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1250
1251 for (i = 0; i < 4; i++) {
1252 offset[i] = (code * 8) - results[vcm_final[i]][i];
1253
1254 if (offset[i] < 0)
1255 offset[i] = -((abs(offset[i]) + 4) / 8);
1256 else
1257 offset[i] = (offset[i] + 4) / 8;
1258
1259 if (results_min[i] == 248)
1260 offset[i] = code - 32;
1261
1262 if (i % 2 == 0)
1263 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1264 type);
1265 else
1266 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1267 type);
1268 }
1269
1270 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1271 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1272
1273 switch (state[2]) {
1274 case 1:
1275 b43_nphy_rssi_select(dev, 1, 2);
1276 break;
1277 case 4:
1278 b43_nphy_rssi_select(dev, 1, 0);
1279 break;
1280 case 2:
1281 b43_nphy_rssi_select(dev, 1, 1);
1282 break;
1283 default:
1284 b43_nphy_rssi_select(dev, 1, 1);
1285 break;
1286 }
1287
1288 switch (state[3]) {
1289 case 1:
1290 b43_nphy_rssi_select(dev, 2, 2);
1291 break;
1292 case 4:
1293 b43_nphy_rssi_select(dev, 2, 0);
1294 break;
1295 default:
1296 b43_nphy_rssi_select(dev, 2, 1);
1297 break;
1298 }
1299
1300 b43_nphy_rssi_select(dev, 0, type);
1301
1302 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1303 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1304 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1305 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1306
1307 b43_nphy_classifier(dev, 7, class);
1308 b43_nphy_write_clip_detection(dev, clip_state);
4cb99775
RM		 1309}
1310
1311/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1312static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1313{
1314 /* TODO */
1315}
1316
1317/*
1318 * RSSI Calibration
1319 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1320 */
1321static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1322{
1323 if (dev->phy.rev >= 3) {
1324 b43_nphy_rev3_rssi_cal(dev);
1325 } else {
1326 b43_nphy_rev2_rssi_cal(dev, 2);
1327 b43_nphy_rev2_rssi_cal(dev, 0);
1328 b43_nphy_rev2_rssi_cal(dev, 1);
1329 }
95b66bad
MB		 1330}
1331
42e1547e
RM		 1332/*
1333 * Restore RSSI Calibration
1334 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1335 */
1336static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1337{
1338 struct b43_phy_n *nphy = dev->phy.n;
1339
1340 u16 *rssical_radio_regs = NULL;
1341 u16 *rssical_phy_regs = NULL;
1342
1343 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1344 if (!nphy->rssical_chanspec_2G)
1345 return;
1346 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1347 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1348 } else {
1349 if (!nphy->rssical_chanspec_5G)
1350 return;
1351 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1352 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1353 }
1354
1355 /* TODO use some definitions */
1356 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1357 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1358
1359 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1360 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1361 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1362 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1363
1364 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1365 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1366 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1367 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1368
1369 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1370 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1371 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1372 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1373}
1374
2f258b74
RM		 1375/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1376static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1377{
1378 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1379 if (dev->phy.rev >= 6) {
1380 /* TODO If the chip is 47162
1381 return txpwrctrl_tx_gain_ipa_rev5 */
1382 return txpwrctrl_tx_gain_ipa_rev6;
1383 } else if (dev->phy.rev >= 5) {
1384 return txpwrctrl_tx_gain_ipa_rev5;
1385 } else {
1386 return txpwrctrl_tx_gain_ipa;
1387 }
1388 } else {
1389 return txpwrctrl_tx_gain_ipa_5g;
1390 }
1391}
1392
c4a92003
RM		 1393/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1394static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1395{
1396 struct b43_phy_n *nphy = dev->phy.n;
1397 u16 *save = nphy->tx_rx_cal_radio_saveregs;
1398
1399 if (dev->phy.rev >= 3) {
1400 /* TODO */
1401 } else {
1402 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1403 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1404
1405 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1406 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1407
1408 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1409 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1410
1411 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1412 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1413
1414 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1415 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1416
1417 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1418 B43_NPHY_BANDCTL_5GHZ)) {
1419 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1420 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1421 } else {
1422 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1423 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1424 }
1425
1426 if (dev->phy.rev < 2) {
1427 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1428 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1429 } else {
1430 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1431 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1432 }
1433 }
1434}
1435
e9762492
RM		 1436/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1437static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1438 struct nphy_txgains target,
1439 struct nphy_iqcal_params *params)
1440{
1441 int i, j, indx;
1442 u16 gain;
1443
1444 if (dev->phy.rev >= 3) {
1445 params->txgm = target.txgm[core];
1446 params->pga = target.pga[core];
1447 params->pad = target.pad[core];
1448 params->ipa = target.ipa[core];
1449 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1450 (params->pad << 4) | (params->ipa);
1451 for (j = 0; j < 5; j++)
1452 params->ncorr[j] = 0x79;
1453 } else {
1454 gain = (target.pad[core]) | (target.pga[core] << 4) |
1455 (target.txgm[core] << 8);
1456
1457 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1458 1 : 0;
1459 for (i = 0; i < 9; i++)
1460 if (tbl_iqcal_gainparams[indx][i][0] == gain)
1461 break;
1462 i = min(i, 8);
1463
1464 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1465 params->pga = tbl_iqcal_gainparams[indx][i][2];
1466 params->pad = tbl_iqcal_gainparams[indx][i][3];
1467 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1468 (params->pad << 2);
1469 for (j = 0; j < 4; j++)
1470 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1471 }
1472}
1473
de7ed0c6
RM		 1474/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1475static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1476{
1477 struct b43_phy_n *nphy = dev->phy.n;
1478 int i;
1479 u16 scale, entry;
1480
1481 u16 tmp = nphy->txcal_bbmult;
1482 if (core == 0)
1483 tmp >>= 8;
1484 tmp &= 0xff;
1485
1486 for (i = 0; i < 18; i++) {
1487 scale = (ladder_lo[i].percent * tmp) / 100;
1488 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
1489 /* TODO: Write an N PHY Table with ID 15, length 1,
1490 offset i, width 16, and data entry */
1491
1492 scale = (ladder_iq[i].percent * tmp) / 100;
1493 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
1494 /* TODO: Write an N PHY Table with ID 15, length 1,
1495 offset i + 32, width 16, and data entry */
1496 }
1497}
1498
b0022e15
RM		 1499/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1500static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1501{
1502 struct b43_phy_n *nphy = dev->phy.n;
1503
1504 u16 curr_gain[2];
1505 struct nphy_txgains target;
1506 const u32 *table = NULL;
1507
1508 if (nphy->txpwrctrl == 0) {
1509 int i;
1510
1511 if (nphy->hang_avoid)
1512 b43_nphy_stay_in_carrier_search(dev, true);
1513 /* TODO: Read an N PHY Table with ID 7, length 2,
1514 offset 0x110, width 16, and curr_gain */
1515 if (nphy->hang_avoid)
1516 b43_nphy_stay_in_carrier_search(dev, false);
1517
1518 for (i = 0; i < 2; ++i) {
1519 if (dev->phy.rev >= 3) {
1520 target.ipa[i] = curr_gain[i] & 0x000F;
1521 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1522 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1523 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1524 } else {
1525 target.ipa[i] = curr_gain[i] & 0x0003;
1526 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1527 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1528 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1529 }
1530 }
1531 } else {
1532 int i;
1533 u16 index[2];
1534 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1535 B43_NPHY_TXPCTL_STAT_BIDX) >>
1536 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1537 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1538 B43_NPHY_TXPCTL_STAT_BIDX) >>
1539 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1540
1541 for (i = 0; i < 2; ++i) {
1542 if (dev->phy.rev >= 3) {
1543 enum ieee80211_band band =
1544 b43_current_band(dev->wl);
1545
1546 if ((nphy->ipa2g_on &&
1547 band == IEEE80211_BAND_2GHZ) ||
1548 (nphy->ipa5g_on &&
1549 band == IEEE80211_BAND_5GHZ)) {
1550 table = b43_nphy_get_ipa_gain_table(dev);
1551 } else {
1552 if (band == IEEE80211_BAND_5GHZ) {
1553 if (dev->phy.rev == 3)
1554 table = b43_ntab_tx_gain_rev3_5ghz;
1555 else if (dev->phy.rev == 4)
1556 table = b43_ntab_tx_gain_rev4_5ghz;
1557 else
1558 table = b43_ntab_tx_gain_rev5plus_5ghz;
1559 } else {
1560 table = b43_ntab_tx_gain_rev3plus_2ghz;
1561 }
1562 }
1563
1564 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1565 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1566 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1567 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1568 } else {
1569 table = b43_ntab_tx_gain_rev0_1_2;
1570
1571 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1572 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1573 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1574 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1575 }
1576 }
1577 }
1578
1579 return target;
1580}
1581
e53de674
RM		 1582/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1583static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1584{
1585 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1586
1587 if (dev->phy.rev >= 3) {
1588 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1589 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1590 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1591 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1592 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
1593 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1594 width 16, and data from regs[5] */
1595 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1596 width 16, and data from regs[6] */
1597 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1598 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1599 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1600 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1601 b43_nphy_reset_cca(dev);
1602 } else {
1603 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1604 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1605 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1606 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1607 width 16, and data from regs[3] */
1608 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1609 width 16, and data from regs[4] */
1610 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1611 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1612 }
1613}
1614
1615/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1616static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1617{
1618 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1619 u16 tmp;
1620
1621 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1622 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1623 if (dev->phy.rev >= 3) {
1624 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1625 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1626
1627 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1628 regs[2] = tmp;
1629 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1630
1631 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1632 regs[3] = tmp;
1633 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1634
1635 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
1636 b43_phy_mask(dev, B43_NPHY_BBCFG, ~B43_NPHY_BBCFG_RSTRX);
1637
1638 /* TODO: Read an N PHY Table with ID 8, length 1, offset 3,
1639 width 16, and data pointing to tmp */
1640 regs[5] = tmp;
1641
1642 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1643 width 16, and data 0 */
1644 /* TODO: Read an N PHY Table with ID 8, length 1, offset 19,
1645 width 16, and data pointing to tmp */
1646 regs[6] = tmp;
1647
1648 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1649 width 16, and data 0 */
1650 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1651 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1652
1653 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1654 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1655 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1656
1657 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1658 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1659 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1660 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1661 } else {
1662 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1663 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1664 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1665 regs[2] = tmp;
1666 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
1667 /* TODO: Read an N PHY Table with ID 8, length 1, offset 2,
1668 width 16, and data pointing to tmp */
1669 regs[3] = tmp;
1670 tmp |= 0x2000;
1671 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1672 width 16, and data pointer tmp */
1673 /* TODO: Read an N PHY Table with ID 8, length 1, offset 18,
1674 width 16, and data pointer tmp */
1675 regs[4] = tmp;
1676 tmp |= 0x2000;
1677 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1678 width 16, and data pointer tmp */
1679 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1680 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1681 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1682 tmp = 0x0180;
1683 else
1684 tmp = 0x0120;
1685 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1686 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1687 }
1688}
1689
2f258b74
RM		 1690/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1691static void b43_nphy_restore_cal(struct b43_wldev *dev)
1692{
1693 struct b43_phy_n *nphy = dev->phy.n;
1694
1695 u16 coef[4];
1696 u16 *loft = NULL;
1697 u16 *table = NULL;
1698
1699 int i;
1700 u16 *txcal_radio_regs = NULL;
1701 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1702
1703 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1704 if (nphy->iqcal_chanspec_2G == 0)
1705 return;
1706 table = nphy->cal_cache.txcal_coeffs_2G;
1707 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1708 } else {
1709 if (nphy->iqcal_chanspec_5G == 0)
1710 return;
1711 table = nphy->cal_cache.txcal_coeffs_5G;
1712 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1713 }
1714
1715 /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1716 width 16, and data from table */
1717
1718 for (i = 0; i < 4; i++) {
1719 if (dev->phy.rev >= 3)
1720 table[i] = coef[i];
1721 else
1722 coef[i] = 0;
1723 }
1724
1725 /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1726 width 16, and data from coef */
1727 /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1728 width 16 and data from loft */
1729 /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1730 width 16 and data from loft */
1731
1732 if (dev->phy.rev < 2)
1733 b43_nphy_tx_iq_workaround(dev);
1734
1735 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1736 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1737 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1738 } else {
1739 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1740 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1741 }
1742
1743 /* TODO use some definitions */
1744 if (dev->phy.rev >= 3) {
1745 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1746 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1747 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1748 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1749 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1750 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1751 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1752 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1753 } else {
1754 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1755 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1756 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1757 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1758 }
1759 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1760}
1761
fb43b8e2
RM		 1762/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1763static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1764 struct nphy_txgains target,
1765 bool full, bool mphase)
1766{
1767 struct b43_phy_n *nphy = dev->phy.n;
1768 int i;
1769 int error = 0;
1770 int freq;
1771 bool avoid = false;
1772 u8 length;
1773 u16 tmp, core, type, count, max, numb, last, cmd;
1774 const u16 *table;
1775 bool phy6or5x;
1776
1777 u16 buffer[11];
1778 u16 diq_start = 0;
1779 u16 save[2];
1780 u16 gain[2];
1781 struct nphy_iqcal_params params[2];
1782 bool updated[2] = { };
1783
1784 b43_nphy_stay_in_carrier_search(dev, true);
1785
1786 if (dev->phy.rev >= 4) {
1787 avoid = nphy->hang_avoid;
1788 nphy->hang_avoid = 0;
1789 }
1790
1791 /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1792 width 16, and data pointer save */
1793
1794 for (i = 0; i < 2; i++) {
1795 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
1796 gain[i] = params[i].cal_gain;
1797 }
1798 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1799 width 16, and data pointer gain */
1800
1801 b43_nphy_tx_cal_radio_setup(dev);
e53de674 1802 b43_nphy_tx_cal_phy_setup(dev);
fb43b8e2
RM		 1803
1804 phy6or5x = dev->phy.rev >= 6 ||
1805 (dev->phy.rev == 5 && nphy->ipa2g_on &&
1806 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
1807 if (phy6or5x) {
1808 /* TODO */
1809 }
1810
1811 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
1812
1813 if (1 /* FIXME: the band width is 20 MHz */)
1814 freq = 2500;
1815 else
1816 freq = 5000;
1817
1818 if (nphy->mphase_cal_phase_id > 2)
1819 ;/* TODO: Call N PHY Run Samples with (band width * 8),
1820 0xFFFF, 0, 1, 0 as arguments */
1821 else
1822 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1823 and save result as error */
1824
1825 if (error == 0) {
1826 if (nphy->mphase_cal_phase_id > 2) {
1827 table = nphy->mphase_txcal_bestcoeffs;
1828 length = 11;
1829 if (dev->phy.rev < 3)
1830 length -= 2;
1831 } else {
1832 if (!full && nphy->txiqlocal_coeffsvalid) {
1833 table = nphy->txiqlocal_bestc;
1834 length = 11;
1835 if (dev->phy.rev < 3)
1836 length -= 2;
1837 } else {
1838 full = true;
1839 if (dev->phy.rev >= 3) {
1840 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
1841 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
1842 } else {
1843 table = tbl_tx_iqlo_cal_startcoefs;
1844 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
1845 }
1846 }
1847 }
1848
1849 /* TODO: Write an N PHY Table with ID 15, length from above,
1850 offset 64, width 16, and the data pointer from above */
1851
1852 if (full) {
1853 if (dev->phy.rev >= 3)
1854 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
1855 else
1856 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
1857 } else {
1858 if (dev->phy.rev >= 3)
1859 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
1860 else
1861 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
1862 }
1863
1864 if (mphase) {
1865 count = nphy->mphase_txcal_cmdidx;
1866 numb = min(max,
1867 (u16)(count + nphy->mphase_txcal_numcmds));
1868 } else {
1869 count = 0;
1870 numb = max;
1871 }
1872
1873 for (; count < numb; count++) {
1874 if (full) {
1875 if (dev->phy.rev >= 3)
1876 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
1877 else
1878 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
1879 } else {
1880 if (dev->phy.rev >= 3)
1881 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
1882 else
1883 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
1884 }
1885
1886 core = (cmd & 0x3000) >> 12;
1887 type = (cmd & 0x0F00) >> 8;
1888
1889 if (phy6or5x && updated[core] == 0) {
1890 b43_nphy_update_tx_cal_ladder(dev, core);
1891 updated[core] = 1;
1892 }
1893
1894 tmp = (params[core].ncorr[type] << 8) | 0x66;
1895 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
1896
1897 if (type == 1 || type == 3 || type == 4) {
1898 /* TODO: Read an N PHY Table with ID 15,
1899 length 1, offset 69 + core,
1900 width 16, and data pointer buffer */
1901 diq_start = buffer[0];
1902 buffer[0] = 0;
1903 /* TODO: Write an N PHY Table with ID 15,
1904 length 1, offset 69 + core, width 16,
1905 and data of 0 */
1906 }
1907
1908 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
1909 for (i = 0; i < 2000; i++) {
1910 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
1911 if (tmp & 0xC000)
1912 break;
1913 udelay(10);
1914 }
1915
1916 /* TODO: Read an N PHY Table with ID 15,
1917 length table_length, offset 96, width 16,
1918 and data pointer buffer */
1919 /* TODO: Write an N PHY Table with ID 15,
1920 length table_length, offset 64, width 16,
1921 and data pointer buffer */
1922
1923 if (type == 1 || type == 3 || type == 4)
1924 buffer[0] = diq_start;
1925 }
1926
1927 if (mphase)
1928 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
1929
1930 last = (dev->phy.rev < 3) ? 6 : 7;
1931
1932 if (!mphase || nphy->mphase_cal_phase_id == last) {
1933 /* TODO: Write an N PHY Table with ID 15, length 4,
1934 offset 96, width 16, and data pointer buffer */
1935 /* TODO: Read an N PHY Table with ID 15, length 4,
1936 offset 80, width 16, and data pointer buffer */
1937 if (dev->phy.rev < 3) {
1938 buffer[0] = 0;
1939 buffer[1] = 0;
1940 buffer[2] = 0;
1941 buffer[3] = 0;
1942 }
1943 /* TODO: Write an N PHY Table with ID 15, length 4,
1944 offset 88, width 16, and data pointer buffer */
1945 /* TODO: Read an N PHY Table with ID 15, length 2,
1946 offset 101, width 16, and data pointer buffer*/
1947 /* TODO: Write an N PHY Table with ID 15, length 2,
1948 offset 85, width 16, and data pointer buffer */
1949 /* TODO: Write an N PHY Table with ID 15, length 2,
1950 offset 93, width 16, and data pointer buffer */
1951 length = 11;
1952 if (dev->phy.rev < 3)
1953 length -= 2;
1954 /* TODO: Read an N PHY Table with ID 15, length length,
1955 offset 96, width 16, and data pointer
1956 nphy->txiqlocal_bestc */
1957 nphy->txiqlocal_coeffsvalid = true;
1958 /* TODO: Set nphy->txiqlocal_chanspec to
1959 the current channel */
1960 } else {
1961 length = 11;
1962 if (dev->phy.rev < 3)
1963 length -= 2;
1964 /* TODO: Read an N PHY Table with ID 5, length length,
1965 offset 96, width 16, and data pointer
1966 nphy->mphase_txcal_bestcoeffs */
1967 }
1968
53ae8e8c 1969 b43_nphy_stop_playback(dev);
fb43b8e2
RM		 1970 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
1971 }
1972
e53de674 1973 b43_nphy_tx_cal_phy_cleanup(dev);
fb43b8e2
RM		 1974 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1975 width 16, and data from save */
1976
1977 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
1978 b43_nphy_tx_iq_workaround(dev);
1979
1980 if (dev->phy.rev >= 4)
1981 nphy->hang_avoid = avoid;
1982
1983 b43_nphy_stay_in_carrier_search(dev, false);
1984
1985 return error;
1986}
1987
15931e31
RM		 1988/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
1989static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
1990 struct nphy_txgains target, u8 type, bool debug)
1991{
1992 struct b43_phy_n *nphy = dev->phy.n;
1993 int i, j, index;
1994 u8 rfctl[2];
1995 u8 afectl_core;
1996 u16 tmp[6];
1997 u16 cur_hpf1, cur_hpf2, cur_lna;
1998 u32 real, imag;
1999 enum ieee80211_band band;
2000
2001 u8 use;
2002 u16 cur_hpf;
2003 u16 lna[3] = { 3, 3, 1 };
2004 u16 hpf1[3] = { 7, 2, 0 };
2005 u16 hpf2[3] = { 2, 0, 0 };
2006 u32 power[3];
2007 u16 gain_save[2];
2008 u16 cal_gain[2];
2009 struct nphy_iqcal_params cal_params[2];
2010 struct nphy_iq_est est;
2011 int ret = 0;
2012 bool playtone = true;
2013 int desired = 13;
2014
2015 b43_nphy_stay_in_carrier_search(dev, 1);
2016
2017 if (dev->phy.rev < 2)
2018 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
2019 /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
2020 width 16, and data gain_save */
2021 for (i = 0; i < 2; i++) {
2022 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2023 cal_gain[i] = cal_params[i].cal_gain;
2024 }
2025 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2026 width 16, and data from cal_gain */
2027
2028 for (i = 0; i < 2; i++) {
2029 if (i == 0) {
2030 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2031 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2032 afectl_core = B43_NPHY_AFECTL_C1;
2033 } else {
2034 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2035 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2036 afectl_core = B43_NPHY_AFECTL_C2;
2037 }
2038
2039 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2040 tmp[2] = b43_phy_read(dev, afectl_core);
2041 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2042 tmp[4] = b43_phy_read(dev, rfctl[0]);
2043 tmp[5] = b43_phy_read(dev, rfctl[1]);
2044
2045 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2046 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2047 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2048 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2049 (1 - i));
2050 b43_phy_set(dev, afectl_core, 0x0006);
2051 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2052
2053 band = b43_current_band(dev->wl);
2054
2055 if (nphy->rxcalparams & 0xFF000000) {
2056 if (band == IEEE80211_BAND_5GHZ)
2057 b43_phy_write(dev, rfctl[0], 0x140);
2058 else
2059 b43_phy_write(dev, rfctl[0], 0x110);
2060 } else {
2061 if (band == IEEE80211_BAND_5GHZ)
2062 b43_phy_write(dev, rfctl[0], 0x180);
2063 else
2064 b43_phy_write(dev, rfctl[0], 0x120);
2065 }
2066
2067 if (band == IEEE80211_BAND_5GHZ)
2068 b43_phy_write(dev, rfctl[1], 0x148);
2069 else
2070 b43_phy_write(dev, rfctl[1], 0x114);
2071
2072 if (nphy->rxcalparams & 0x10000) {
2073 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2074 (i + 1));
2075 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2076 (2 - i));
2077 }
2078
2079 for (j = 0; i < 4; j++) {
2080 if (j < 3) {
2081 cur_lna = lna[j];
2082 cur_hpf1 = hpf1[j];
2083 cur_hpf2 = hpf2[j];
2084 } else {
2085 if (power[1] > 10000) {
2086 use = 1;
2087 cur_hpf = cur_hpf1;
2088 index = 2;
2089 } else {
2090 if (power[0] > 10000) {
2091 use = 1;
2092 cur_hpf = cur_hpf1;
2093 index = 1;
2094 } else {
2095 index = 0;
2096 use = 2;
2097 cur_hpf = cur_hpf2;
2098 }
2099 }
2100 cur_lna = lna[index];
2101 cur_hpf1 = hpf1[index];
2102 cur_hpf2 = hpf2[index];
2103 cur_hpf += desired - hweight32(power[index]);
2104 cur_hpf = clamp_val(cur_hpf, 0, 10);
2105 if (use == 1)
2106 cur_hpf1 = cur_hpf;
2107 else
2108 cur_hpf2 = cur_hpf;
2109 }
2110
2111 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2112 (cur_lna << 2));
2113 /* TODO:Call N PHY RF Ctrl Override with 0x400, tmp[0],
2114 3, 0 as arguments */
2115 /* TODO: Call N PHY Force RF Seq with 2 as argument */
53ae8e8c 2116 b43_nphy_stop_playback(dev);
15931e31
RM		 2117
2118 if (playtone) {
2119 /* TODO: Call N PHY TX Tone with 4000,
2120 (nphy_rxcalparams & 0xffff), 0, 0
2121 as arguments and save result as ret */
2122 playtone = false;
2123 } else {
2124 /* TODO: Call N PHY Run Samples with 160,
2125 0xFFFF, 0, 0, 0 as arguments */
2126 }
2127
2128 if (ret == 0) {
2129 if (j < 3) {
2130 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2131 false);
2132 if (i == 0) {
2133 real = est.i0_pwr;
2134 imag = est.q0_pwr;
2135 } else {
2136 real = est.i1_pwr;
2137 imag = est.q1_pwr;
2138 }
2139 power[i] = ((real + imag) / 1024) + 1;
2140 } else {
2141 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2142 }
53ae8e8c 2143 b43_nphy_stop_playback(dev);
15931e31
RM		 2144 }
2145
2146 if (ret != 0)
2147 break;
2148 }
2149
2150 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2151 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2152 b43_phy_write(dev, rfctl[1], tmp[5]);
2153 b43_phy_write(dev, rfctl[0], tmp[4]);
2154 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2155 b43_phy_write(dev, afectl_core, tmp[2]);
2156 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2157
2158 if (ret != 0)
2159 break;
2160 }
2161
2162 /* TODO: Call N PHY RF Ctrl Override with 0x400, 0, 3, 1 as arguments*/
67c0d6e2 2163 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
15931e31
RM		 2164 /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2165 width 16, and data from gain_save */
2166
2167 b43_nphy_stay_in_carrier_search(dev, 0);
2168
2169 return ret;
2170}
2171
2172static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2173 struct nphy_txgains target, u8 type, bool debug)
2174{
2175 return -1;
2176}
2177
2178/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2179static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2180 struct nphy_txgains target, u8 type, bool debug)
2181{
2182 if (dev->phy.rev >= 3)
2183 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2184 else
2185 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2186}
2187
0988a7a1
RM		 2188/*
2189 * Init N-PHY
2190 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2191 */
424047e6
MB		 2192int b43_phy_initn(struct b43_wldev *dev)
2193{
0988a7a1 2194 struct ssb_bus *bus = dev->dev->bus;
95b66bad 2195 struct b43_phy *phy = &dev->phy;
0988a7a1
RM		 2196 struct b43_phy_n *nphy = phy->n;
2197 u8 tx_pwr_state;
2198 struct nphy_txgains target;
95b66bad 2199 u16 tmp;
0988a7a1
RM		 2200 enum ieee80211_band tmp2;
2201 bool do_rssi_cal;
2202
2203 u16 clip[2];
2204 bool do_cal = false;
95b66bad 2205
0988a7a1
RM		 2206 if ((dev->phy.rev >= 3) &&
2207 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2208 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2209 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2210 }
2211 nphy->deaf_count = 0;
95b66bad 2212 b43_nphy_tables_init(dev);
0988a7a1
RM		 2213 nphy->crsminpwr_adjusted = false;
2214 nphy->noisevars_adjusted = false;
95b66bad
MB		 2215
2216 /* Clear all overrides */
0988a7a1
RM		 2217 if (dev->phy.rev >= 3) {
2218 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2219 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2220 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2221 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2222 } else {
2223 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2224 }
95b66bad
MB		 2225 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2226 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
0988a7a1
RM		 2227 if (dev->phy.rev < 6) {
2228 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2229 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2230 }
95b66bad
MB		 2231 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2232 ~(B43_NPHY_RFSEQMODE_CAOVER |
2233 B43_NPHY_RFSEQMODE_TROVER));
0988a7a1
RM		 2234 if (dev->phy.rev >= 3)
2235 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
95b66bad
MB		 2236 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2237
0988a7a1
RM		 2238 if (dev->phy.rev <= 2) {
2239 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2240 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2241 ~B43_NPHY_BPHY_CTL3_SCALE,
2242 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2243 }
95b66bad
MB		 2244 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2245 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2246
0988a7a1
RM		 2247 if (bus->sprom.boardflags2_lo & 0x100 ||
2248 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2249 bus->boardinfo.type == 0x8B))
2250 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2251 else
2252 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2253 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2254 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2255 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
424047e6 2256
ad9716e8 2257 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
4f4ab6cd 2258 b43_nphy_update_txrx_chain(dev);
95b66bad
MB		 2259
2260 if (phy->rev < 2) {
2261 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2262 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2263 }
0988a7a1
RM		 2264
2265 tmp2 = b43_current_band(dev->wl);
2266 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2267 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2268 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2269 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2270 nphy->papd_epsilon_offset[0] << 7);
2271 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2272 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2273 nphy->papd_epsilon_offset[1] << 7);
2274 /* TODO N PHY IPA Set TX Dig Filters */
2275 } else if (phy->rev >= 5) {
2276 /* TODO N PHY Ext PA Set TX Dig Filters */
2277 }
2278
95b66bad 2279 b43_nphy_workarounds(dev);
95b66bad 2280
0988a7a1 2281 /* Reset CCA, in init code it differs a little from standard way */
730dd705 2282 b43_nphy_bmac_clock_fgc(dev, 1);
0988a7a1
RM		 2283 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2284 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2285 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
730dd705 2286 b43_nphy_bmac_clock_fgc(dev, 0);
0988a7a1
RM		 2287
2288 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2289
e50cbcf6 2290 b43_nphy_pa_override(dev, false);
95b66bad
MB		 2291 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2292 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
e50cbcf6 2293 b43_nphy_pa_override(dev, true);
0988a7a1 2294
bbec398c
RM		 2295 b43_nphy_classifier(dev, 0, 0);
2296 b43_nphy_read_clip_detection(dev, clip);
0988a7a1
RM		 2297 tx_pwr_state = nphy->txpwrctrl;
2298 /* TODO N PHY TX power control with argument 0
2299 (turning off power control) */
2300 /* TODO Fix the TX Power Settings */
2301 /* TODO N PHY TX Power Control Idle TSSI */
2302 /* TODO N PHY TX Power Control Setup */
2303
2304 if (phy->rev >= 3) {
2305 /* TODO */
2306 } else {
2307 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2308 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2309 }
95b66bad 2310
0988a7a1
RM		 2311 if (nphy->phyrxchain != 3)
2312 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2313 if (nphy->mphase_cal_phase_id > 0)
2314 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2315
2316 do_rssi_cal = false;
2317 if (phy->rev >= 3) {
2318 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2319 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2320 else
2321 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2322
2323 if (do_rssi_cal)
4cb99775 2324 b43_nphy_rssi_cal(dev);
0988a7a1 2325 else
42e1547e 2326 b43_nphy_restore_rssi_cal(dev);
0988a7a1 2327 } else {
4cb99775 2328 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 2329 }
2330
2331 if (!((nphy->measure_hold & 0x6) != 0)) {
2332 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2333 do_cal = (nphy->iqcal_chanspec_2G == 0);
2334 else
2335 do_cal = (nphy->iqcal_chanspec_5G == 0);
2336
2337 if (nphy->mute)
2338 do_cal = false;
2339
2340 if (do_cal) {
b0022e15 2341 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 2342
2343 if (nphy->antsel_type == 2)
2344 ;/*TODO NPHY Superswitch Init with argument 1*/
2345 if (nphy->perical != 2) {
90b9738d 2346 b43_nphy_rssi_cal(dev);
0988a7a1
RM		 2347 if (phy->rev >= 3) {
2348 nphy->cal_orig_pwr_idx[0] =
2349 nphy->txpwrindex[0].index_internal;
2350 nphy->cal_orig_pwr_idx[1] =
2351 nphy->txpwrindex[1].index_internal;
2352 /* TODO N PHY Pre Calibrate TX Gain */
b0022e15 2353 target = b43_nphy_get_tx_gains(dev);
0988a7a1
RM		 2354 }
2355 }
2356 }
2357 }
2358
0988a7a1
RM		 2359 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2360 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
15931e31 2361 ;/* Call N PHY Save Cal */
0988a7a1 2362 else if (nphy->mphase_cal_phase_id == 0)
15931e31 2363 ;/* N PHY Periodic Calibration with argument 3 */
0988a7a1
RM		 2364 } else {
2365 b43_nphy_restore_cal(dev);
2366 }
0988a7a1 2367
6dcd9d91 2368 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
0988a7a1
RM		 2369 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2370 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2371 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2372 if (phy->rev >= 3 && phy->rev <= 6)
2373 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
fe3e46e8 2374 b43_nphy_tx_lp_fbw(dev);
0988a7a1 2375 /* TODO N PHY Spur Workaround */
95b66bad
MB		 2376
2377 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
53a6e234 2378 return 0;
424047e6 2379}
ef1a628d
MB		 2380
2381static int b43_nphy_op_allocate(struct b43_wldev *dev)
2382{
2383 struct b43_phy_n *nphy;
2384
2385 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2386 if (!nphy)
2387 return -ENOMEM;
2388 dev->phy.n = nphy;
2389
ef1a628d
MB		 2390 return 0;
2391}
2392
fb11137a 2393static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
ef1a628d 2394{
fb11137a
MB		 2395 struct b43_phy *phy = &dev->phy;
2396 struct b43_phy_n *nphy = phy->n;
ef1a628d 2397
fb11137a 2398 memset(nphy, 0, sizeof(*nphy));
ef1a628d 2399
fb11137a 2400 //TODO init struct b43_phy_n
ef1a628d
MB		 2401}
2402
fb11137a 2403static void b43_nphy_op_free(struct b43_wldev *dev)
ef1a628d 2404{
fb11137a
MB		 2405 struct b43_phy *phy = &dev->phy;
2406 struct b43_phy_n *nphy = phy->n;
ef1a628d 2407
ef1a628d 2408 kfree(nphy);
fb11137a
MB		 2409 phy->n = NULL;
2410}
2411
2412static int b43_nphy_op_init(struct b43_wldev *dev)
2413{
2414 return b43_phy_initn(dev);
ef1a628d
MB		 2415}
2416
2417static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2418{
2419#if B43_DEBUG
2420 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2421 /* OFDM registers are onnly available on A/G-PHYs */
2422 b43err(dev->wl, "Invalid OFDM PHY access at "
2423 "0x%04X on N-PHY\n", offset);
2424 dump_stack();
2425 }
2426 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2427 /* Ext-G registers are only available on G-PHYs */
2428 b43err(dev->wl, "Invalid EXT-G PHY access at "
2429 "0x%04X on N-PHY\n", offset);
2430 dump_stack();
2431 }
2432#endif /* B43_DEBUG */
2433}
2434
2435static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2436{
2437 check_phyreg(dev, reg);
2438 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2439 return b43_read16(dev, B43_MMIO_PHY_DATA);
2440}
2441
2442static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2443{
2444 check_phyreg(dev, reg);
2445 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2446 b43_write16(dev, B43_MMIO_PHY_DATA, value);
2447}
2448
2449static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2450{
2451 /* Register 1 is a 32-bit register. */
2452 B43_WARN_ON(reg == 1);
2453 /* N-PHY needs 0x100 for read access */
2454 reg |= 0x100;
2455
2456 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2457 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2458}
2459
2460static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2461{
2462 /* Register 1 is a 32-bit register. */
2463 B43_WARN_ON(reg == 1);
2464
2465 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2466 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2467}
2468
2469static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
19d337df 2470 bool blocked)
ef1a628d
MB		 2471{//TODO
2472}
2473
cb24f57f
MB		 2474static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2475{
2476 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2477 on ? 0 : 0x7FFF);
2478}
2479
ef1a628d
MB		 2480static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2481 unsigned int new_channel)
2482{
2483 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2484 if ((new_channel < 1) || (new_channel > 14))
2485 return -EINVAL;
2486 } else {
2487 if (new_channel > 200)
2488 return -EINVAL;
2489 }
2490
2491 return nphy_channel_switch(dev, new_channel);
2492}
2493
2494static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2495{
2496 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2497 return 1;
2498 return 36;
2499}
2500
ef1a628d
MB		 2501const struct b43_phy_operations b43_phyops_n = {
2502 .allocate = b43_nphy_op_allocate,
fb11137a
MB		 2503 .free = b43_nphy_op_free,
2504 .prepare_structs = b43_nphy_op_prepare_structs,
ef1a628d 2505 .init = b43_nphy_op_init,
ef1a628d
MB		 2506 .phy_read = b43_nphy_op_read,
2507 .phy_write = b43_nphy_op_write,
2508 .radio_read = b43_nphy_op_radio_read,
2509 .radio_write = b43_nphy_op_radio_write,
2510 .software_rfkill = b43_nphy_op_software_rfkill,
cb24f57f 2511 .switch_analog = b43_nphy_op_switch_analog,
ef1a628d
MB		 2512 .switch_channel = b43_nphy_op_switch_channel,
2513 .get_default_chan = b43_nphy_op_get_default_chan,
18c8adeb
MB		 2514 .recalc_txpower = b43_nphy_op_recalc_txpower,
2515 .adjust_txpower = b43_nphy_op_adjust_txpower,
ef1a628d 2516};
Clone of davem's net-next-2.6 tree