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ath: move more setup code into ath_regd_init
[net-next-2.6.git] / drivers / net / wireless / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e
BC		 63static int modparam_nohwcrypt;
64module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd
BC		 67static int modparam_all_channels;
68module_param_named(all_channels, modparam_all_channels, int, 0444);
69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 221static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
222static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 223static int ath5k_start(struct ieee80211_hw *hw);
224static void ath5k_stop(struct ieee80211_hw *hw);
225static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
e8975581 229static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
32bfd35d
JB		 230static int ath5k_config_interface(struct ieee80211_hw *hw,
231 struct ieee80211_vif *vif,
fa1c114f
JS		 232 struct ieee80211_if_conf *conf);
233static void ath5k_configure_filter(struct ieee80211_hw *hw,
234 unsigned int changed_flags,
235 unsigned int *new_flags,
236 int mc_count, struct dev_mc_list *mclist);
237static int ath5k_set_key(struct ieee80211_hw *hw,
238 enum set_key_cmd cmd,
dc822b5d 239 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 240 struct ieee80211_key_conf *key);
241static int ath5k_get_stats(struct ieee80211_hw *hw,
242 struct ieee80211_low_level_stats *stats);
243static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
244 struct ieee80211_tx_queue_stats *stats);
245static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 246static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 247static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 248static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 249 struct sk_buff *skb);
02969b38
MX		 250static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
251 struct ieee80211_vif *vif,
252 struct ieee80211_bss_conf *bss_conf,
253 u32 changes);
fa1c114f 254
2c91108c 255static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 256 .tx = ath5k_tx,
257 .start = ath5k_start,
258 .stop = ath5k_stop,
259 .add_interface = ath5k_add_interface,
260 .remove_interface = ath5k_remove_interface,
261 .config = ath5k_config,
262 .config_interface = ath5k_config_interface,
263 .configure_filter = ath5k_configure_filter,
264 .set_key = ath5k_set_key,
265 .get_stats = ath5k_get_stats,
266 .conf_tx = NULL,
267 .get_tx_stats = ath5k_get_tx_stats,
268 .get_tsf = ath5k_get_tsf,
3b5d665b 269 .set_tsf = ath5k_set_tsf,
fa1c114f 270 .reset_tsf = ath5k_reset_tsf,
02969b38 271 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 272};
273
274/*
275 * Prototypes - Internal functions
276 */
277/* Attach detach */
278static int ath5k_attach(struct pci_dev *pdev,
279 struct ieee80211_hw *hw);
280static void ath5k_detach(struct pci_dev *pdev,
281 struct ieee80211_hw *hw);
282/* Channel/mode setup */
283static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 284static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
285 struct ieee80211_channel *channels,
286 unsigned int mode,
287 unsigned int max);
63266a65 288static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 289static int ath5k_chan_set(struct ath5k_softc *sc,
290 struct ieee80211_channel *chan);
291static void ath5k_setcurmode(struct ath5k_softc *sc,
292 unsigned int mode);
293static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 294
fa1c114f
JS		 295/* Descriptor setup */
296static int ath5k_desc_alloc(struct ath5k_softc *sc,
297 struct pci_dev *pdev);
298static void ath5k_desc_free(struct ath5k_softc *sc,
299 struct pci_dev *pdev);
300/* Buffers setup */
301static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
302 struct ath5k_buf *bf);
303static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 304 struct ath5k_buf *bf);
fa1c114f
JS		 305static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
306 struct ath5k_buf *bf)
307{
308 BUG_ON(!bf);
309 if (!bf->skb)
310 return;
311 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
312 PCI_DMA_TODEVICE);
00482973 313 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 314 bf->skb = NULL;
315}
316
a6c8d375
FF		 317static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
318 struct ath5k_buf *bf)
319{
320 BUG_ON(!bf);
321 if (!bf->skb)
322 return;
323 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
324 PCI_DMA_FROMDEVICE);
325 dev_kfree_skb_any(bf->skb);
326 bf->skb = NULL;
327}
328
329
fa1c114f
JS		 330/* Queues setup */
331static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
332 int qtype, int subtype);
333static int ath5k_beaconq_setup(struct ath5k_hw *ah);
334static int ath5k_beaconq_config(struct ath5k_softc *sc);
335static void ath5k_txq_drainq(struct ath5k_softc *sc,
336 struct ath5k_txq *txq);
337static void ath5k_txq_cleanup(struct ath5k_softc *sc);
338static void ath5k_txq_release(struct ath5k_softc *sc);
339/* Rx handling */
340static int ath5k_rx_start(struct ath5k_softc *sc);
341static void ath5k_rx_stop(struct ath5k_softc *sc);
342static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
343 struct ath5k_desc *ds,
b47f407b
BR		 344 struct sk_buff *skb,
345 struct ath5k_rx_status *rs);
fa1c114f
JS		 346static void ath5k_tasklet_rx(unsigned long data);
347/* Tx handling */
348static void ath5k_tx_processq(struct ath5k_softc *sc,
349 struct ath5k_txq *txq);
350static void ath5k_tasklet_tx(unsigned long data);
351/* Beacon handling */
352static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 353 struct ath5k_buf *bf);
fa1c114f
JS		 354static void ath5k_beacon_send(struct ath5k_softc *sc);
355static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 356static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 357static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 358
359static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
360{
361 u64 tsf = ath5k_hw_get_tsf64(ah);
362
363 if ((tsf & 0x7fff) < rstamp)
364 tsf -= 0x8000;
365
366 return (tsf & ~0x7fff) | rstamp;
367}
368
369/* Interrupt handling */
bb2becac 370static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 371static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 372static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 373static irqreturn_t ath5k_intr(int irq, void *dev_id);
374static void ath5k_tasklet_reset(unsigned long data);
375
376static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 377
378/*
379 * Module init/exit functions
380 */
381static int __init
382init_ath5k_pci(void)
383{
384 int ret;
385
386 ath5k_debug_init();
387
04a9e451 388 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 389 if (ret) {
390 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
391 return ret;
392 }
393
394 return 0;
395}
396
397static void __exit
398exit_ath5k_pci(void)
399{
04a9e451 400 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 401
402 ath5k_debug_finish();
403}
404
405module_init(init_ath5k_pci);
406module_exit(exit_ath5k_pci);
407
408
409/********************\
410* PCI Initialization *
411\********************/
412
413static const char *
414ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
415{
416 const char *name = "xxxxx";
417 unsigned int i;
418
419 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
420 if (srev_names[i].sr_type != type)
421 continue;
75d0edb8
NK		 422
423 if ((val & 0xf0) == srev_names[i].sr_val)
424 name = srev_names[i].sr_name;
425
426 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 427 name = srev_names[i].sr_name;
428 break;
429 }
430 }
431
432 return name;
433}
434
435static int __devinit
436ath5k_pci_probe(struct pci_dev *pdev,
437 const struct pci_device_id *id)
438{
439 void __iomem *mem;
440 struct ath5k_softc *sc;
441 struct ieee80211_hw *hw;
442 int ret;
443 u8 csz;
444
445 ret = pci_enable_device(pdev);
446 if (ret) {
447 dev_err(&pdev->dev, "can't enable device\n");
448 goto err;
449 }
450
451 /* XXX 32-bit addressing only */
284901a9 452 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 453 if (ret) {
454 dev_err(&pdev->dev, "32-bit DMA not available\n");
455 goto err_dis;
456 }
457
458 /*
459 * Cache line size is used to size and align various
460 * structures used to communicate with the hardware.
461 */
462 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
463 if (csz == 0) {
464 /*
465 * Linux 2.4.18 (at least) writes the cache line size
466 * register as a 16-bit wide register which is wrong.
467 * We must have this setup properly for rx buffer
468 * DMA to work so force a reasonable value here if it
469 * comes up zero.
470 */
471 csz = L1_CACHE_BYTES / sizeof(u32);
472 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
473 }
474 /*
475 * The default setting of latency timer yields poor results,
476 * set it to the value used by other systems. It may be worth
477 * tweaking this setting more.
478 */
479 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
480
481 /* Enable bus mastering */
482 pci_set_master(pdev);
483
484 /*
485 * Disable the RETRY_TIMEOUT register (0x41) to keep
486 * PCI Tx retries from interfering with C3 CPU state.
487 */
488 pci_write_config_byte(pdev, 0x41, 0);
489
490 ret = pci_request_region(pdev, 0, "ath5k");
491 if (ret) {
492 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
493 goto err_dis;
494 }
495
496 mem = pci_iomap(pdev, 0, 0);
497 if (!mem) {
498 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
499 ret = -EIO;
500 goto err_reg;
501 }
502
503 /*
504 * Allocate hw (mac80211 main struct)
505 * and hw->priv (driver private data)
506 */
507 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
508 if (hw == NULL) {
509 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
510 ret = -ENOMEM;
511 goto err_map;
512 }
513
514 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
515
516 /* Initialize driver private data */
517 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 518 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
519 IEEE80211_HW_SIGNAL_DBM |
520 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 521
522 hw->wiphy->interface_modes =
523 BIT(NL80211_IFTYPE_STATION) |
524 BIT(NL80211_IFTYPE_ADHOC) |
525 BIT(NL80211_IFTYPE_MESH_POINT);
526
fa1c114f
JS		 527 hw->extra_tx_headroom = 2;
528 hw->channel_change_time = 5000;
fa1c114f
JS		 529 sc = hw->priv;
530 sc->hw = hw;
531 sc->pdev = pdev;
532
533 ath5k_debug_init_device(sc);
534
535 /*
536 * Mark the device as detached to avoid processing
537 * interrupts until setup is complete.
538 */
539 __set_bit(ATH_STAT_INVALID, sc->status);
540
541 sc->iobase = mem; /* So we can unmap it on detach */
542 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 543 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 544 mutex_init(&sc->lock);
545 spin_lock_init(&sc->rxbuflock);
546 spin_lock_init(&sc->txbuflock);
00482973 547 spin_lock_init(&sc->block);
fa1c114f
JS		 548
549 /* Set private data */
550 pci_set_drvdata(pdev, hw);
551
fa1c114f
JS		 552 /* Setup interrupt handler */
553 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
554 if (ret) {
555 ATH5K_ERR(sc, "request_irq failed\n");
556 goto err_free;
557 }
558
559 /* Initialize device */
560 sc->ah = ath5k_hw_attach(sc, id->driver_data);
561 if (IS_ERR(sc->ah)) {
562 ret = PTR_ERR(sc->ah);
563 goto err_irq;
564 }
565
2f7fe870
FF		 566 /* set up multi-rate retry capabilities */
567 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 568 hw->max_rates = 4;
569 hw->max_rate_tries = 11;
2f7fe870
FF		 570 }
571
fa1c114f
JS		 572 /* Finish private driver data initialization */
573 ret = ath5k_attach(pdev, hw);
574 if (ret)
575 goto err_ah;
576
577 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 578 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 579 sc->ah->ah_mac_srev,
580 sc->ah->ah_phy_revision);
581
400ec45a 582 if (!sc->ah->ah_single_chip) {
fa1c114f 583 /* Single chip radio (!RF5111) */
400ec45a
LR		 584 if (sc->ah->ah_radio_5ghz_revision &&
585 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 586 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 587 if (!test_bit(AR5K_MODE_11A,
588 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 589 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 590 ath5k_chip_name(AR5K_VERSION_RAD,
591 sc->ah->ah_radio_5ghz_revision),
592 sc->ah->ah_radio_5ghz_revision);
593 /* No 2GHz support (5110 and some
594 * 5Ghz only cards) -> report 5Ghz radio */
595 } else if (!test_bit(AR5K_MODE_11B,
596 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 597 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 598 ath5k_chip_name(AR5K_VERSION_RAD,
599 sc->ah->ah_radio_5ghz_revision),
600 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 601 /* Multiband radio */
602 } else {
603 ATH5K_INFO(sc, "RF%s multiband radio found"
604 " (0x%x)\n",
400ec45a
LR		 605 ath5k_chip_name(AR5K_VERSION_RAD,
606 sc->ah->ah_radio_5ghz_revision),
607 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 608 }
609 }
400ec45a
LR		 610 /* Multi chip radio (RF5111 - RF2111) ->
611 * report both 2GHz/5GHz radios */
612 else if (sc->ah->ah_radio_5ghz_revision &&
613 sc->ah->ah_radio_2ghz_revision){
fa1c114f 614 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_5ghz_revision),
617 sc->ah->ah_radio_5ghz_revision);
fa1c114f 618 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 619 ath5k_chip_name(AR5K_VERSION_RAD,
620 sc->ah->ah_radio_2ghz_revision),
621 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 622 }
623 }
624
625
626 /* ready to process interrupts */
627 __clear_bit(ATH_STAT_INVALID, sc->status);
628
629 return 0;
630err_ah:
631 ath5k_hw_detach(sc->ah);
632err_irq:
633 free_irq(pdev->irq, sc);
634err_free:
fa1c114f
JS		 635 ieee80211_free_hw(hw);
636err_map:
637 pci_iounmap(pdev, mem);
638err_reg:
639 pci_release_region(pdev, 0);
640err_dis:
641 pci_disable_device(pdev);
642err:
643 return ret;
644}
645
646static void __devexit
647ath5k_pci_remove(struct pci_dev *pdev)
648{
649 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
650 struct ath5k_softc *sc = hw->priv;
651
652 ath5k_debug_finish_device(sc);
653 ath5k_detach(pdev, hw);
654 ath5k_hw_detach(sc->ah);
655 free_irq(pdev->irq, sc);
fa1c114f
JS		 656 pci_iounmap(pdev, sc->iobase);
657 pci_release_region(pdev, 0);
658 pci_disable_device(pdev);
659 ieee80211_free_hw(hw);
660}
661
662#ifdef CONFIG_PM
663static int
664ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
665{
666 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
667 struct ath5k_softc *sc = hw->priv;
668
3a078876 669 ath5k_led_off(sc);
fa1c114f 670
3e4242b9 671 free_irq(pdev->irq, sc);
fa1c114f
JS		 672 pci_save_state(pdev);
673 pci_disable_device(pdev);
674 pci_set_power_state(pdev, PCI_D3hot);
675
676 return 0;
677}
678
679static int
680ath5k_pci_resume(struct pci_dev *pdev)
681{
682 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
683 struct ath5k_softc *sc = hw->priv;
bc1b32d6 684 int err;
fa1c114f 685
3e4242b9 686 pci_restore_state(pdev);
fa1c114f
JS		 687
688 err = pci_enable_device(pdev);
689 if (err)
690 return err;
691
3e4242b9
JS		 692 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
693 if (err) {
694 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 695 goto err_no_irq;
3e4242b9
JS		 696 }
697
3a078876 698 ath5k_led_enable(sc);
fa1c114f 699 return 0;
bb2becac 700
37465c8a 701err_no_irq:
3e4242b9
JS		 702 pci_disable_device(pdev);
703 return err;
fa1c114f
JS		 704}
705#endif /* CONFIG_PM */
706
707
fa1c114f
JS		 708/***********************\
709* Driver Initialization *
710\***********************/
711
712static int
713ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
714{
715 struct ath5k_softc *sc = hw->priv;
716 struct ath5k_hw *ah = sc->ah;
0e149cf5 717 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 718 int ret;
719
720 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
721
722 /*
723 * Check if the MAC has multi-rate retry support.
724 * We do this by trying to setup a fake extended
725 * descriptor. MAC's that don't have support will
726 * return false w/o doing anything. MAC's that do
727 * support it will return true w/o doing anything.
728 */
c6e387a2 729 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 730 if (ret < 0)
731 goto err;
732 if (ret > 0)
fa1c114f
JS		 733 __set_bit(ATH_STAT_MRRETRY, sc->status);
734
fa1c114f
JS		 735 /*
736 * Collect the channel list. The 802.11 layer
737 * is resposible for filtering this list based
738 * on settings like the phy mode and regulatory
739 * domain restrictions.
740 */
63266a65 741 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 742 if (ret) {
743 ATH5K_ERR(sc, "can't get channels\n");
744 goto err;
745 }
746
747 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 748 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
749 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 750 else
d8ee398d 751 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 752
753 /*
754 * Allocate tx+rx descriptors and populate the lists.
755 */
756 ret = ath5k_desc_alloc(sc, pdev);
757 if (ret) {
758 ATH5K_ERR(sc, "can't allocate descriptors\n");
759 goto err;
760 }
761
762 /*
763 * Allocate hardware transmit queues: one queue for
764 * beacon frames and one data queue for each QoS
765 * priority. Note that hw functions handle reseting
766 * these queues at the needed time.
767 */
768 ret = ath5k_beaconq_setup(ah);
769 if (ret < 0) {
770 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
771 goto err_desc;
772 }
773 sc->bhalq = ret;
774
775 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
776 if (IS_ERR(sc->txq)) {
777 ATH5K_ERR(sc, "can't setup xmit queue\n");
778 ret = PTR_ERR(sc->txq);
779 goto err_bhal;
780 }
781
782 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
783 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
784 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 785 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 786 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 787
0e149cf5
BC		 788 ret = ath5k_eeprom_read_mac(ah, mac);
789 if (ret) {
790 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
791 sc->pdev->device);
792 goto err_queues;
793 }
794
fa1c114f
JS		 795 SET_IEEE80211_PERM_ADDR(hw, mac);
796 /* All MAC address bits matter for ACKs */
797 memset(sc->bssidmask, 0xff, ETH_ALEN);
798 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
799
800 ret = ieee80211_register_hw(hw);
801 if (ret) {
802 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
803 goto err_queues;
804 }
805
3a078876
BC		 806 ath5k_init_leds(sc);
807
fa1c114f
JS		 808 return 0;
809err_queues:
810 ath5k_txq_release(sc);
811err_bhal:
812 ath5k_hw_release_tx_queue(ah, sc->bhalq);
813err_desc:
814 ath5k_desc_free(sc, pdev);
815err:
816 return ret;
817}
818
819static void
820ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
821{
822 struct ath5k_softc *sc = hw->priv;
823
824 /*
825 * NB: the order of these is important:
826 * o call the 802.11 layer before detaching ath5k_hw to
827 * insure callbacks into the driver to delete global
828 * key cache entries can be handled
829 * o reclaim the tx queue data structures after calling
830 * the 802.11 layer as we'll get called back to reclaim
831 * node state and potentially want to use them
832 * o to cleanup the tx queues the hal is called, so detach
833 * it last
834 * XXX: ??? detach ath5k_hw ???
835 * Other than that, it's straightforward...
836 */
837 ieee80211_unregister_hw(hw);
838 ath5k_desc_free(sc, pdev);
839 ath5k_txq_release(sc);
840 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 841 ath5k_unregister_leds(sc);
fa1c114f
JS		 842
843 /*
844 * NB: can't reclaim these until after ieee80211_ifdetach
845 * returns because we'll get called back to reclaim node
846 * state and potentially want to use them.
847 */
848}
849
850
851
852
853/********************\
854* Channel/mode setup *
855\********************/
856
857/*
858 * Convert IEEE channel number to MHz frequency.
859 */
860static inline short
861ath5k_ieee2mhz(short chan)
862{
863 if (chan <= 14 || chan >= 27)
864 return ieee80211chan2mhz(chan);
865 else
866 return 2212 + chan * 20;
867}
868
42639fcd
BC		 869/*
870 * Returns true for the channel numbers used without all_channels modparam.
871 */
872static bool ath5k_is_standard_channel(short chan)
873{
874 return ((chan <= 14) ||
875 /* UNII 1,2 */
876 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
877 /* midband */
878 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
879 /* UNII-3 */
880 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
881}
882
fa1c114f
JS		 883static unsigned int
884ath5k_copy_channels(struct ath5k_hw *ah,
885 struct ieee80211_channel *channels,
886 unsigned int mode,
887 unsigned int max)
888{
d8ee398d 889 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 890
891 if (!test_bit(mode, ah->ah_modes))
892 return 0;
893
fa1c114f 894 switch (mode) {
d8ee398d
LR		 895 case AR5K_MODE_11A:
896 case AR5K_MODE_11A_TURBO:
fa1c114f 897 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 898 size = 220 ;
fa1c114f
JS		 899 chfreq = CHANNEL_5GHZ;
900 break;
d8ee398d
LR		 901 case AR5K_MODE_11B:
902 case AR5K_MODE_11G:
903 case AR5K_MODE_11G_TURBO:
904 size = 26;
fa1c114f
JS		 905 chfreq = CHANNEL_2GHZ;
906 break;
907 default:
908 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
909 return 0;
910 }
911
912 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 913 ch = i + 1 ;
914 freq = ath5k_ieee2mhz(ch);
fa1c114f 915
d8ee398d
LR		 916 /* Check if channel is supported by the chipset */
917 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 918 continue;
919
42639fcd
BC		 920 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
921 continue;
922
d8ee398d
LR		 923 /* Write channel info and increment counter */
924 channels[count].center_freq = freq;
a3f4b914
LR		 925 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
926 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 927 switch (mode) {
928 case AR5K_MODE_11A:
929 case AR5K_MODE_11G:
930 channels[count].hw_value = chfreq | CHANNEL_OFDM;
931 break;
932 case AR5K_MODE_11A_TURBO:
933 case AR5K_MODE_11G_TURBO:
934 channels[count].hw_value = chfreq |
935 CHANNEL_OFDM | CHANNEL_TURBO;
936 break;
937 case AR5K_MODE_11B:
d8ee398d
LR		 938 channels[count].hw_value = CHANNEL_B;
939 }
fa1c114f 940
fa1c114f
JS		 941 count++;
942 max--;
943 }
944
945 return count;
946}
947
63266a65
BR		 948static void
949ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
950{
951 u8 i;
952
953 for (i = 0; i < AR5K_MAX_RATES; i++)
954 sc->rate_idx[b->band][i] = -1;
955
956 for (i = 0; i < b->n_bitrates; i++) {
957 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
958 if (b->bitrates[i].hw_value_short)
959 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
960 }
961}
962
d8ee398d 963static int
63266a65 964ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 965{
966 struct ath5k_softc *sc = hw->priv;
d8ee398d 967 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 968 struct ieee80211_supported_band *sband;
969 int max_c, count_c = 0;
970 int i;
fa1c114f 971
d8ee398d 972 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 973 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 974
975 /* 2GHz band */
63266a65
BR		 976 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
977 sband->band = IEEE80211_BAND_2GHZ;
978 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 979
63266a65
BR		 980 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
981 /* G mode */
982 memcpy(sband->bitrates, &ath5k_rates[0],
983 sizeof(struct ieee80211_rate) * 12);
984 sband->n_bitrates = 12;
fa1c114f 985
d8ee398d 986 sband->channels = sc->channels;
d8ee398d 987 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 988 AR5K_MODE_11G, max_c);
fa1c114f 989
63266a65 990 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 991 count_c = sband->n_channels;
63266a65
BR		 992 max_c -= count_c;
993 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
994 /* B mode */
995 memcpy(sband->bitrates, &ath5k_rates[0],
996 sizeof(struct ieee80211_rate) * 4);
997 sband->n_bitrates = 4;
998
999 /* 5211 only supports B rates and uses 4bit rate codes
1000 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1001 * fix them up here:
1002 */
1003 if (ah->ah_version == AR5K_AR5211) {
1004 for (i = 0; i < 4; i++) {
1005 sband->bitrates[i].hw_value =
1006 sband->bitrates[i].hw_value & 0xF;
1007 sband->bitrates[i].hw_value_short =
1008 sband->bitrates[i].hw_value_short & 0xF;
1009 }
1010 }
fa1c114f 1011
63266a65
BR		 1012 sband->channels = sc->channels;
1013 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1014 AR5K_MODE_11B, max_c);
d8ee398d 1015
63266a65
BR		 1016 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1017 count_c = sband->n_channels;
d8ee398d 1018 max_c -= count_c;
fa1c114f 1019 }
63266a65 1020 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1021
63266a65 1022 /* 5GHz band, A mode */
400ec45a 1023 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1024 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1025 sband->band = IEEE80211_BAND_5GHZ;
1026 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1027
63266a65
BR		 1028 memcpy(sband->bitrates, &ath5k_rates[4],
1029 sizeof(struct ieee80211_rate) * 8);
1030 sband->n_bitrates = 8;
fa1c114f 1031
63266a65 1032 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1033 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1034 AR5K_MODE_11A, max_c);
1035
d8ee398d
LR		 1036 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1037 }
63266a65 1038 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1039
b446197c 1040 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1041
1042 return 0;
fa1c114f
JS		 1043}
1044
1045/*
1046 * Set/change channels. If the channel is really being changed,
1047 * it's done by reseting the chip. To accomplish this we must
1048 * first cleanup any pending DMA, then restart stuff after a la
1049 * ath5k_init.
be009370
BC		 1050 *
1051 * Called with sc->lock.
fa1c114f
JS		 1052 */
1053static int
1054ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1055{
d8ee398d
LR		 1056 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1057 sc->curchan->center_freq, chan->center_freq);
1058
1059 if (chan->center_freq != sc->curchan->center_freq ||
1060 chan->hw_value != sc->curchan->hw_value) {
1061
1062 sc->curchan = chan;
1063 sc->curband = &sc->sbands[chan->band];
fa1c114f 1064
fa1c114f
JS		 1065 /*
1066 * To switch channels clear any pending DMA operations;
1067 * wait long enough for the RX fifo to drain, reset the
1068 * hardware at the new frequency, and then re-enable
1069 * the relevant bits of the h/w.
1070 */
d7dc1003 1071 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1072 }
1073
1074 return 0;
1075}
1076
1077static void
1078ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1079{
fa1c114f 1080 sc->curmode = mode;
d8ee398d 1081
400ec45a 1082 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1083 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1084 } else {
1085 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1086 }
fa1c114f
JS		 1087}
1088
1089static void
1090ath5k_mode_setup(struct ath5k_softc *sc)
1091{
1092 struct ath5k_hw *ah = sc->ah;
1093 u32 rfilt;
1094
1095 /* configure rx filter */
1096 rfilt = sc->filter_flags;
1097 ath5k_hw_set_rx_filter(ah, rfilt);
1098
1099 if (ath5k_hw_hasbssidmask(ah))
1100 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1101
1102 /* configure operational mode */
1103 ath5k_hw_set_opmode(ah);
1104
1105 ath5k_hw_set_mcast_filter(ah, 0, 0);
1106 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1107}
1108
d8ee398d 1109static inline int
63266a65
BR		 1110ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1111{
b7266047
BC		 1112 int rix;
1113
1114 /* return base rate on errors */
1115 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1116 "hw_rix out of bounds: %x\n", hw_rix))
1117 return 0;
1118
1119 rix = sc->rate_idx[sc->curband->band][hw_rix];
1120 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1121 rix = 0;
1122
1123 return rix;
d8ee398d
LR		 1124}
1125
fa1c114f
JS		 1126/***************\
1127* Buffers setup *
1128\***************/
1129
b6ea0356
BC		 1130static
1131struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1132{
1133 struct sk_buff *skb;
1134 unsigned int off;
1135
1136 /*
1137 * Allocate buffer with headroom_needed space for the
1138 * fake physical layer header at the start.
1139 */
1140 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1141
1142 if (!skb) {
1143 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1144 sc->rxbufsize + sc->cachelsz - 1);
1145 return NULL;
1146 }
1147 /*
1148 * Cache-line-align. This is important (for the
1149 * 5210 at least) as not doing so causes bogus data
1150 * in rx'd frames.
1151 */
1152 off = ((unsigned long)skb->data) % sc->cachelsz;
1153 if (off != 0)
1154 skb_reserve(skb, sc->cachelsz - off);
1155
1156 *skb_addr = pci_map_single(sc->pdev,
1157 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1158 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1159 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1160 dev_kfree_skb(skb);
1161 return NULL;
1162 }
1163 return skb;
1164}
1165
fa1c114f
JS		 1166static int
1167ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1168{
1169 struct ath5k_hw *ah = sc->ah;
1170 struct sk_buff *skb = bf->skb;
1171 struct ath5k_desc *ds;
1172
b6ea0356
BC		 1173 if (!skb) {
1174 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1175 if (!skb)
fa1c114f 1176 return -ENOMEM;
fa1c114f 1177 bf->skb = skb;
fa1c114f
JS		 1178 }
1179
1180 /*
1181 * Setup descriptors. For receive we always terminate
1182 * the descriptor list with a self-linked entry so we'll
1183 * not get overrun under high load (as can happen with a
1184 * 5212 when ANI processing enables PHY error frames).
1185 *
1186 * To insure the last descriptor is self-linked we create
1187 * each descriptor as self-linked and add it to the end. As
1188 * each additional descriptor is added the previous self-linked
1189 * entry is ``fixed'' naturally. This should be safe even
1190 * if DMA is happening. When processing RX interrupts we
1191 * never remove/process the last, self-linked, entry on the
1192 * descriptor list. This insures the hardware always has
1193 * someplace to write a new frame.
1194 */
1195 ds = bf->desc;
1196 ds->ds_link = bf->daddr; /* link to self */
1197 ds->ds_data = bf->skbaddr;
c6e387a2 1198 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1199 skb_tailroom(skb), /* buffer size */
1200 0);
1201
1202 if (sc->rxlink != NULL)
1203 *sc->rxlink = bf->daddr;
1204 sc->rxlink = &ds->ds_link;
1205 return 0;
1206}
1207
1208static int
e039fa4a 1209ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1210{
1211 struct ath5k_hw *ah = sc->ah;
1212 struct ath5k_txq *txq = sc->txq;
1213 struct ath5k_desc *ds = bf->desc;
1214 struct sk_buff *skb = bf->skb;
a888d52d 1215 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1216 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1217 struct ieee80211_rate *rate;
1218 unsigned int mrr_rate[3], mrr_tries[3];
1219 int i, ret;
8902ff4e 1220 u16 hw_rate;
07c1e852
BC		 1221 u16 cts_rate = 0;
1222 u16 duration = 0;
8902ff4e 1223 u8 rc_flags;
fa1c114f
JS		 1224
1225 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1226
fa1c114f
JS		 1227 /* XXX endianness */
1228 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1229 PCI_DMA_TODEVICE);
1230
8902ff4e
BC		 1231 rate = ieee80211_get_tx_rate(sc->hw, info);
1232
e039fa4a 1233 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1234 flags |= AR5K_TXDESC_NOACK;
1235
8902ff4e
BC		 1236 rc_flags = info->control.rates[0].flags;
1237 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1238 rate->hw_value_short : rate->hw_value;
1239
281c56dd 1240 pktlen = skb->len;
fa1c114f 1241
8f655dde
NK		 1242 /* FIXME: If we are in g mode and rate is a CCK rate
1243 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1244 * from tx power (value is in dB units already) */
362695e1
BC		 1245 if (info->control.hw_key) {
1246 keyidx = info->control.hw_key->hw_key_idx;
1247 pktlen += info->control.hw_key->icv_len;
1248 }
07c1e852
BC		 1249 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1250 flags |= AR5K_TXDESC_RTSENA;
1251 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1252 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1253 sc->vif, pktlen, info));
1254 }
1255 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1256 flags |= AR5K_TXDESC_CTSENA;
1257 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1258 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1259 sc->vif, pktlen, info));
1260 }
fa1c114f
JS		 1261 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1262 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1263 (sc->power_level * 2),
8902ff4e 1264 hw_rate,
07c1e852
BC		 1265 info->control.rates[0].count, keyidx, 0, flags,
1266 cts_rate, duration);
fa1c114f
JS		 1267 if (ret)
1268 goto err_unmap;
1269
2f7fe870
FF		 1270 memset(mrr_rate, 0, sizeof(mrr_rate));
1271 memset(mrr_tries, 0, sizeof(mrr_tries));
1272 for (i = 0; i < 3; i++) {
1273 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1274 if (!rate)
1275 break;
1276
1277 mrr_rate[i] = rate->hw_value;
e6a9854b 1278 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1279 }
1280
1281 ah->ah_setup_mrr_tx_desc(ah, ds,
1282 mrr_rate[0], mrr_tries[0],
1283 mrr_rate[1], mrr_tries[1],
1284 mrr_rate[2], mrr_tries[2]);
1285
fa1c114f
JS		 1286 ds->ds_link = 0;
1287 ds->ds_data = bf->skbaddr;
1288
1289 spin_lock_bh(&txq->lock);
1290 list_add_tail(&bf->list, &txq->q);
57ffc589 1291 sc->tx_stats[txq->qnum].len++;
fa1c114f 1292 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1293 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1294 else /* no, so only link it */
1295 *txq->link = bf->daddr;
1296
1297 txq->link = &ds->ds_link;
c6e387a2 1298 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1299 mmiowb();
fa1c114f
JS		 1300 spin_unlock_bh(&txq->lock);
1301
1302 return 0;
1303err_unmap:
1304 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1305 return ret;
1306}
1307
1308/*******************\
1309* Descriptors setup *
1310\*******************/
1311
1312static int
1313ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1314{
1315 struct ath5k_desc *ds;
1316 struct ath5k_buf *bf;
1317 dma_addr_t da;
1318 unsigned int i;
1319 int ret;
1320
1321 /* allocate descriptors */
1322 sc->desc_len = sizeof(struct ath5k_desc) *
1323 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1324 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1325 if (sc->desc == NULL) {
1326 ATH5K_ERR(sc, "can't allocate descriptors\n");
1327 ret = -ENOMEM;
1328 goto err;
1329 }
1330 ds = sc->desc;
1331 da = sc->desc_daddr;
1332 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1333 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1334
1335 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1336 sizeof(struct ath5k_buf), GFP_KERNEL);
1337 if (bf == NULL) {
1338 ATH5K_ERR(sc, "can't allocate bufptr\n");
1339 ret = -ENOMEM;
1340 goto err_free;
1341 }
1342 sc->bufptr = bf;
1343
1344 INIT_LIST_HEAD(&sc->rxbuf);
1345 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1346 bf->desc = ds;
1347 bf->daddr = da;
1348 list_add_tail(&bf->list, &sc->rxbuf);
1349 }
1350
1351 INIT_LIST_HEAD(&sc->txbuf);
1352 sc->txbuf_len = ATH_TXBUF;
1353 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1354 da += sizeof(*ds)) {
1355 bf->desc = ds;
1356 bf->daddr = da;
1357 list_add_tail(&bf->list, &sc->txbuf);
1358 }
1359
1360 /* beacon buffer */
1361 bf->desc = ds;
1362 bf->daddr = da;
1363 sc->bbuf = bf;
1364
1365 return 0;
1366err_free:
1367 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1368err:
1369 sc->desc = NULL;
1370 return ret;
1371}
1372
1373static void
1374ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1375{
1376 struct ath5k_buf *bf;
1377
1378 ath5k_txbuf_free(sc, sc->bbuf);
1379 list_for_each_entry(bf, &sc->txbuf, list)
1380 ath5k_txbuf_free(sc, bf);
1381 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1382 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1383
1384 /* Free memory associated with all descriptors */
1385 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1386
1387 kfree(sc->bufptr);
1388 sc->bufptr = NULL;
1389}
1390
1391
1392
1393
1394
1395/**************\
1396* Queues setup *
1397\**************/
1398
1399static struct ath5k_txq *
1400ath5k_txq_setup(struct ath5k_softc *sc,
1401 int qtype, int subtype)
1402{
1403 struct ath5k_hw *ah = sc->ah;
1404 struct ath5k_txq *txq;
1405 struct ath5k_txq_info qi = {
1406 .tqi_subtype = subtype,
1407 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1408 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1409 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1410 };
1411 int qnum;
1412
1413 /*
1414 * Enable interrupts only for EOL and DESC conditions.
1415 * We mark tx descriptors to receive a DESC interrupt
1416 * when a tx queue gets deep; otherwise waiting for the
1417 * EOL to reap descriptors. Note that this is done to
1418 * reduce interrupt load and this only defers reaping
1419 * descriptors, never transmitting frames. Aside from
1420 * reducing interrupts this also permits more concurrency.
1421 * The only potential downside is if the tx queue backs
1422 * up in which case the top half of the kernel may backup
1423 * due to a lack of tx descriptors.
1424 */
1425 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1426 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1427 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1428 if (qnum < 0) {
1429 /*
1430 * NB: don't print a message, this happens
1431 * normally on parts with too few tx queues
1432 */
1433 return ERR_PTR(qnum);
1434 }
1435 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1436 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1437 qnum, ARRAY_SIZE(sc->txqs));
1438 ath5k_hw_release_tx_queue(ah, qnum);
1439 return ERR_PTR(-EINVAL);
1440 }
1441 txq = &sc->txqs[qnum];
1442 if (!txq->setup) {
1443 txq->qnum = qnum;
1444 txq->link = NULL;
1445 INIT_LIST_HEAD(&txq->q);
1446 spin_lock_init(&txq->lock);
1447 txq->setup = true;
1448 }
1449 return &sc->txqs[qnum];
1450}
1451
1452static int
1453ath5k_beaconq_setup(struct ath5k_hw *ah)
1454{
1455 struct ath5k_txq_info qi = {
1456 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1457 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1458 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1459 /* NB: for dynamic turbo, don't enable any other interrupts */
1460 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1461 };
1462
1463 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1464}
1465
1466static int
1467ath5k_beaconq_config(struct ath5k_softc *sc)
1468{
1469 struct ath5k_hw *ah = sc->ah;
1470 struct ath5k_txq_info qi;
1471 int ret;
1472
1473 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1474 if (ret)
1475 return ret;
05c914fe
JB		 1476 if (sc->opmode == NL80211_IFTYPE_AP ||
1477 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1478 /*
1479 * Always burst out beacon and CAB traffic
1480 * (aifs = cwmin = cwmax = 0)
1481 */
1482 qi.tqi_aifs = 0;
1483 qi.tqi_cw_min = 0;
1484 qi.tqi_cw_max = 0;
05c914fe 1485 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1486 /*
1487 * Adhoc mode; backoff between 0 and (2 * cw_min).
1488 */
1489 qi.tqi_aifs = 0;
1490 qi.tqi_cw_min = 0;
1491 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1492 }
1493
6d91e1d8
BR		 1494 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1495 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1496 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1497
c6e387a2 1498 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1499 if (ret) {
1500 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1501 "hardware queue!\n", __func__);
1502 return ret;
1503 }
1504
1505 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1506}
1507
1508static void
1509ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1510{
1511 struct ath5k_buf *bf, *bf0;
1512
1513 /*
1514 * NB: this assumes output has been stopped and
1515 * we do not need to block ath5k_tx_tasklet
1516 */
1517 spin_lock_bh(&txq->lock);
1518 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1519 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1520
1521 ath5k_txbuf_free(sc, bf);
1522
1523 spin_lock_bh(&sc->txbuflock);
57ffc589 1524 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1525 list_move_tail(&bf->list, &sc->txbuf);
1526 sc->txbuf_len++;
1527 spin_unlock_bh(&sc->txbuflock);
1528 }
1529 txq->link = NULL;
1530 spin_unlock_bh(&txq->lock);
1531}
1532
1533/*
1534 * Drain the transmit queues and reclaim resources.
1535 */
1536static void
1537ath5k_txq_cleanup(struct ath5k_softc *sc)
1538{
1539 struct ath5k_hw *ah = sc->ah;
1540 unsigned int i;
1541
1542 /* XXX return value */
1543 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1544 /* don't touch the hardware if marked invalid */
1545 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1546 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1547 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1548 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1549 if (sc->txqs[i].setup) {
1550 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1551 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1552 "link %p\n",
1553 sc->txqs[i].qnum,
c6e387a2 1554 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1555 sc->txqs[i].qnum),
1556 sc->txqs[i].link);
1557 }
1558 }
36d6825b 1559 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1560
1561 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1562 if (sc->txqs[i].setup)
1563 ath5k_txq_drainq(sc, &sc->txqs[i]);
1564}
1565
1566static void
1567ath5k_txq_release(struct ath5k_softc *sc)
1568{
1569 struct ath5k_txq *txq = sc->txqs;
1570 unsigned int i;
1571
1572 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1573 if (txq->setup) {
1574 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1575 txq->setup = false;
1576 }
1577}
1578
1579
1580
1581
1582/*************\
1583* RX Handling *
1584\*************/
1585
1586/*
1587 * Enable the receive h/w following a reset.
1588 */
1589static int
1590ath5k_rx_start(struct ath5k_softc *sc)
1591{
1592 struct ath5k_hw *ah = sc->ah;
1593 struct ath5k_buf *bf;
1594 int ret;
1595
1596 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1597
1598 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1599 sc->cachelsz, sc->rxbufsize);
1600
1601 sc->rxlink = NULL;
1602
1603 spin_lock_bh(&sc->rxbuflock);
1604 list_for_each_entry(bf, &sc->rxbuf, list) {
1605 ret = ath5k_rxbuf_setup(sc, bf);
1606 if (ret != 0) {
1607 spin_unlock_bh(&sc->rxbuflock);
1608 goto err;
1609 }
1610 }
1611 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1612 spin_unlock_bh(&sc->rxbuflock);
1613
c6e387a2
NK		 1614 ath5k_hw_set_rxdp(ah, bf->daddr);
1615 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1616 ath5k_mode_setup(sc); /* set filters, etc. */
1617 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1618
1619 return 0;
1620err:
1621 return ret;
1622}
1623
1624/*
1625 * Disable the receive h/w in preparation for a reset.
1626 */
1627static void
1628ath5k_rx_stop(struct ath5k_softc *sc)
1629{
1630 struct ath5k_hw *ah = sc->ah;
1631
c6e387a2 1632 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1633 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1634 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1635
1636 ath5k_debug_printrxbuffs(sc, ah);
1637
1638 sc->rxlink = NULL; /* just in case */
1639}
1640
1641static unsigned int
1642ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1643 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1644{
1645 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1646 unsigned int keyix, hlen;
fa1c114f 1647
b47f407b
BR		 1648 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1649 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1650 return RX_FLAG_DECRYPTED;
1651
1652 /* Apparently when a default key is used to decrypt the packet
1653 the hw does not set the index used to decrypt. In such cases
1654 get the index from the packet. */
798ee985 1655 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1656 if (ieee80211_has_protected(hdr->frame_control) &&
1657 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1658 skb->len >= hlen + 4) {
fa1c114f
JS		 1659 keyix = skb->data[hlen + 3] >> 6;
1660
1661 if (test_bit(keyix, sc->keymap))
1662 return RX_FLAG_DECRYPTED;
1663 }
1664
1665 return 0;
1666}
1667
036cd1ec
BR		 1668
1669static void
6ba81c2c
BR		 1670ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1671 struct ieee80211_rx_status *rxs)
036cd1ec 1672{
6ba81c2c 1673 u64 tsf, bc_tstamp;
036cd1ec
BR		 1674 u32 hw_tu;
1675 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1676
24b56e70 1677 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1678 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1679 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1680 /*
6ba81c2c
BR		 1681 * Received an IBSS beacon with the same BSSID. Hardware *must*
1682 * have updated the local TSF. We have to work around various
1683 * hardware bugs, though...
036cd1ec 1684 */
6ba81c2c
BR		 1685 tsf = ath5k_hw_get_tsf64(sc->ah);
1686 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1687 hw_tu = TSF_TO_TU(tsf);
1688
1689 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1690 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1691 (unsigned long long)bc_tstamp,
1692 (unsigned long long)rxs->mactime,
1693 (unsigned long long)(rxs->mactime - bc_tstamp),
1694 (unsigned long long)tsf);
6ba81c2c
BR		 1695
1696 /*
1697 * Sometimes the HW will give us a wrong tstamp in the rx
1698 * status, causing the timestamp extension to go wrong.
1699 * (This seems to happen especially with beacon frames bigger
1700 * than 78 byte (incl. FCS))
1701 * But we know that the receive timestamp must be later than the
1702 * timestamp of the beacon since HW must have synced to that.
1703 *
1704 * NOTE: here we assume mactime to be after the frame was
1705 * received, not like mac80211 which defines it at the start.
1706 */
1707 if (bc_tstamp > rxs->mactime) {
036cd1ec 1708 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1709 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1710 (unsigned long long)rxs->mactime,
1711 (unsigned long long)tsf);
6ba81c2c 1712 rxs->mactime = tsf;
036cd1ec 1713 }
6ba81c2c
BR		 1714
1715 /*
1716 * Local TSF might have moved higher than our beacon timers,
1717 * in that case we have to update them to continue sending
1718 * beacons. This also takes care of synchronizing beacon sending
1719 * times with other stations.
1720 */
1721 if (hw_tu >= sc->nexttbtt)
1722 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1723 }
1724}
1725
acf3c1a5
BC		 1726static void ath5k_tasklet_beacon(unsigned long data)
1727{
1728 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1729
1730 /*
1731 * Software beacon alert--time to send a beacon.
1732 *
1733 * In IBSS mode we use this interrupt just to
1734 * keep track of the next TBTT (target beacon
1735 * transmission time) in order to detect wether
1736 * automatic TSF updates happened.
1737 */
1738 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1739 /* XXX: only if VEOL suppported */
1740 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1741 sc->nexttbtt += sc->bintval;
1742 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1743 "SWBA nexttbtt: %x hw_tu: %x "
1744 "TSF: %llx\n",
1745 sc->nexttbtt,
1746 TSF_TO_TU(tsf),
1747 (unsigned long long) tsf);
1748 } else {
1749 spin_lock(&sc->block);
1750 ath5k_beacon_send(sc);
1751 spin_unlock(&sc->block);
1752 }
1753}
1754
fa1c114f
JS		 1755static void
1756ath5k_tasklet_rx(unsigned long data)
1757{
1758 struct ieee80211_rx_status rxs = {};
b47f407b 1759 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1760 struct sk_buff *skb, *next_skb;
1761 dma_addr_t next_skb_addr;
fa1c114f 1762 struct ath5k_softc *sc = (void *)data;
3a0f2c87 1763 struct ath5k_buf *bf, *bf_last;
fa1c114f 1764 struct ath5k_desc *ds;
fa1c114f
JS		 1765 int ret;
1766 int hdrlen;
0fe45b1d 1767 int padsize;
fa1c114f
JS		 1768
1769 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1770 if (list_empty(&sc->rxbuf)) {
1771 ATH5K_WARN(sc, "empty rx buf pool\n");
1772 goto unlock;
1773 }
1774 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
fa1c114f 1775 do {
d6894b5b
BC		 1776 rxs.flag = 0;
1777
fa1c114f
JS		 1778 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1779 BUG_ON(bf->skb == NULL);
1780 skb = bf->skb;
1781 ds = bf->desc;
1782
3a0f2c87
JS		 1783 /*
1784 * last buffer must not be freed to ensure proper hardware
1785 * function. When the hardware finishes also a packet next to
1786 * it, we are sure, it doesn't use it anymore and we can go on.
1787 */
1788 if (bf_last == bf)
1789 bf->flags |= 1;
1790 if (bf->flags) {
1791 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1792 struct ath5k_buf, list);
1793 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1794 &rs);
1795 if (ret)
1796 break;
1797 bf->flags &= ~1;
1798 /* skip the overwritten one (even status is martian) */
1799 goto next;
1800 }
fa1c114f 1801
b47f407b 1802 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1803 if (unlikely(ret == -EINPROGRESS))
1804 break;
1805 else if (unlikely(ret)) {
1806 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1807 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1808 return;
1809 }
1810
b47f407b 1811 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1812 ATH5K_WARN(sc, "unsupported jumbo\n");
1813 goto next;
1814 }
1815
b47f407b
BR		 1816 if (unlikely(rs.rs_status)) {
1817 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1818 goto next;
b47f407b 1819 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1820 /*
1821 * Decrypt error. If the error occurred
1822 * because there was no hardware key, then
1823 * let the frame through so the upper layers
1824 * can process it. This is necessary for 5210
1825 * parts which have no way to setup a ``clear''
1826 * key cache entry.
1827 *
1828 * XXX do key cache faulting
1829 */
b47f407b
BR		 1830 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1831 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1832 goto accept;
1833 }
b47f407b 1834 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1835 rxs.flag |= RX_FLAG_MMIC_ERROR;
1836 goto accept;
1837 }
1838
1839 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1840 if ((rs.rs_status &
1841 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1842 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1843 goto next;
1844 }
1845accept:
b6ea0356
BC		 1846 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1847
1848 /*
1849 * If we can't replace bf->skb with a new skb under memory
1850 * pressure, just skip this packet
1851 */
1852 if (!next_skb)
1853 goto next;
1854
fa1c114f
JS		 1855 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1856 PCI_DMA_FROMDEVICE);
b47f407b 1857 skb_put(skb, rs.rs_datalen);
fa1c114f 1858
0fe45b1d
BP		 1859 /* The MAC header is padded to have 32-bit boundary if the
1860 * packet payload is non-zero. The general calculation for
1861 * padsize would take into account odd header lengths:
1862 * padsize = (4 - hdrlen % 4) % 4; However, since only
1863 * even-length headers are used, padding can only be 0 or 2
1864 * bytes and we can optimize this a bit. In addition, we must
1865 * not try to remove padding from short control frames that do
1866 * not have payload. */
fa1c114f 1867 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1868 padsize = ath5k_pad_size(hdrlen);
1869 if (padsize) {
0fe45b1d
BP		 1870 memmove(skb->data + padsize, skb->data, hdrlen);
1871 skb_pull(skb, padsize);
fa1c114f
JS		 1872 }
1873
c0e1899b
BR		 1874 /*
1875 * always extend the mac timestamp, since this information is
1876 * also needed for proper IBSS merging.
1877 *
1878 * XXX: it might be too late to do it here, since rs_tstamp is
1879 * 15bit only. that means TSF extension has to be done within
1880 * 32768usec (about 32ms). it might be necessary to move this to
1881 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1882 *
1883 * Unfortunately we don't know when the hardware takes the rx
1884 * timestamp (beginning of phy frame, data frame, end of rx?).
1885 * The only thing we know is that it is hardware specific...
1886 * On AR5213 it seems the rx timestamp is at the end of the
1887 * frame, but i'm not sure.
1888 *
1889 * NOTE: mac80211 defines mactime at the beginning of the first
1890 * data symbol. Since we don't have any time references it's
1891 * impossible to comply to that. This affects IBSS merge only
1892 * right now, so it's not too bad...
c0e1899b 1893 */
b47f407b 1894 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1895 rxs.flag |= RX_FLAG_TSFT;
1896
d8ee398d
LR		 1897 rxs.freq = sc->curchan->center_freq;
1898 rxs.band = sc->curband->band;
fa1c114f 1899
fa1c114f 1900 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1901 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1902
1903 /* An rssi of 35 indicates you should be able use
1904 * 54 Mbps reliably. A more elaborate scheme can be used
1905 * here but it requires a map of SNR/throughput for each
1906 * possible mode used */
1907 rxs.qual = rs.rs_rssi * 100 / 35;
1908
1909 /* rssi can be more than 35 though, anything above that
1910 * should be considered at 100% */
1911 if (rxs.qual > 100)
1912 rxs.qual = 100;
fa1c114f 1913
b47f407b
BR		 1914 rxs.antenna = rs.rs_antenna;
1915 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1916 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1917
06303352
BR		 1918 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1919 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1920 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1921
fa1c114f
JS		 1922 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1923
036cd1ec 1924 /* check beacons in IBSS mode */
05c914fe 1925 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1926 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1927
fa1c114f 1928 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1929
1930 bf->skb = next_skb;
1931 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1932next:
1933 list_move_tail(&bf->list, &sc->rxbuf);
1934 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1935unlock:
fa1c114f
JS		 1936 spin_unlock(&sc->rxbuflock);
1937}
1938
1939
1940
1941
1942/*************\
1943* TX Handling *
1944\*************/
1945
1946static void
1947ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1948{
b47f407b 1949 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1950 struct ath5k_buf *bf, *bf0;
1951 struct ath5k_desc *ds;
1952 struct sk_buff *skb;
e039fa4a 1953 struct ieee80211_tx_info *info;
2f7fe870 1954 int i, ret;
fa1c114f
JS		 1955
1956 spin_lock(&txq->lock);
1957 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1958 ds = bf->desc;
1959
b47f407b 1960 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1961 if (unlikely(ret == -EINPROGRESS))
1962 break;
1963 else if (unlikely(ret)) {
1964 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1965 ret, txq->qnum);
1966 break;
1967 }
1968
1969 skb = bf->skb;
a888d52d 1970 info = IEEE80211_SKB_CB(skb);
fa1c114f 1971 bf->skb = NULL;
e039fa4a 1972
fa1c114f
JS		 1973 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1974 PCI_DMA_TODEVICE);
1975
e6a9854b 1976 ieee80211_tx_info_clear_status(info);
2f7fe870 1977 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1978 struct ieee80211_tx_rate *r =
1979 &info->status.rates[i];
2f7fe870
FF		 1980
1981 if (ts.ts_rate[i]) {
e6a9854b
JB		 1982 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1983 r->count = ts.ts_retry[i];
2f7fe870 1984 } else {
e6a9854b
JB		 1985 r->idx = -1;
1986 r->count = 0;
2f7fe870
FF		 1987 }
1988 }
1989
e6a9854b
JB		 1990 /* count the successful attempt as well */
1991 info->status.rates[ts.ts_final_idx].count++;
1992
b47f407b 1993 if (unlikely(ts.ts_status)) {
fa1c114f 1994 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1995 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1996 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1997 } else {
e039fa4a
JB		 1998 info->flags |= IEEE80211_TX_STAT_ACK;
1999 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 2000 }
2001
e039fa4a 2002 ieee80211_tx_status(sc->hw, skb);
57ffc589 2003 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 2004
2005 spin_lock(&sc->txbuflock);
57ffc589 2006 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 2007 list_move_tail(&bf->list, &sc->txbuf);
2008 sc->txbuf_len++;
2009 spin_unlock(&sc->txbuflock);
2010 }
2011 if (likely(list_empty(&txq->q)))
2012 txq->link = NULL;
2013 spin_unlock(&txq->lock);
2014 if (sc->txbuf_len > ATH_TXBUF / 5)
2015 ieee80211_wake_queues(sc->hw);
2016}
2017
2018static void
2019ath5k_tasklet_tx(unsigned long data)
2020{
2021 struct ath5k_softc *sc = (void *)data;
2022
2023 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 2024}
2025
2026
fa1c114f
JS		 2027/*****************\
2028* Beacon handling *
2029\*****************/
2030
2031/*
2032 * Setup the beacon frame for transmit.
2033 */
2034static int
e039fa4a 2035ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2036{
2037 struct sk_buff *skb = bf->skb;
a888d52d 2038 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2039 struct ath5k_hw *ah = sc->ah;
2040 struct ath5k_desc *ds;
2041 int ret, antenna = 0;
2042 u32 flags;
2043
2044 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2045 PCI_DMA_TODEVICE);
2046 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2047 "skbaddr %llx\n", skb, skb->data, skb->len,
2048 (unsigned long long)bf->skbaddr);
8d8bb39b 2049 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2050 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2051 return -EIO;
2052 }
2053
2054 ds = bf->desc;
2055
2056 flags = AR5K_TXDESC_NOACK;
05c914fe 2057 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2058 ds->ds_link = bf->daddr; /* self-linked */
2059 flags |= AR5K_TXDESC_VEOL;
2060 /*
2061 * Let hardware handle antenna switching if txantenna is not set
2062 */
2063 } else {
2064 ds->ds_link = 0;
2065 /*
2066 * Switch antenna every 4 beacons if txantenna is not set
2067 * XXX assumes two antennas
2068 */
2069 if (antenna == 0)
2070 antenna = sc->bsent & 4 ? 2 : 1;
2071 }
2072
8f655dde
NK		 2073 /* FIXME: If we are in g mode and rate is a CCK rate
2074 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2075 * from tx power (value is in dB units already) */
fa1c114f 2076 ds->ds_data = bf->skbaddr;
281c56dd 2077 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2078 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2079 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2080 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2081 1, AR5K_TXKEYIX_INVALID,
400ec45a 2082 antenna, flags, 0, 0);
fa1c114f
JS		 2083 if (ret)
2084 goto err_unmap;
2085
2086 return 0;
2087err_unmap:
2088 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2089 return ret;
2090}
2091
2092/*
2093 * Transmit a beacon frame at SWBA. Dynamic updates to the
2094 * frame contents are done as needed and the slot time is
2095 * also adjusted based on current state.
2096 *
acf3c1a5
BC		 2097 * This is called from software irq context (beacontq or restq
2098 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2099 */
2100static void
2101ath5k_beacon_send(struct ath5k_softc *sc)
2102{
2103 struct ath5k_buf *bf = sc->bbuf;
2104 struct ath5k_hw *ah = sc->ah;
2105
be9b7259 2106 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2107
05c914fe
JB		 2108 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2109 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2110 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2111 return;
2112 }
2113 /*
2114 * Check if the previous beacon has gone out. If
2115 * not don't don't try to post another, skip this
2116 * period and wait for the next. Missed beacons
2117 * indicate a problem and should not occur. If we
2118 * miss too many consecutive beacons reset the device.
2119 */
2120 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2121 sc->bmisscount++;
be9b7259 2122 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2123 "missed %u consecutive beacons\n", sc->bmisscount);
2124 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
be9b7259 2125 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2126 "stuck beacon time (%u missed)\n",
2127 sc->bmisscount);
2128 tasklet_schedule(&sc->restq);
2129 }
2130 return;
2131 }
2132 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2133 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2134 "resume beacon xmit after %u misses\n",
2135 sc->bmisscount);
2136 sc->bmisscount = 0;
2137 }
2138
2139 /*
2140 * Stop any current dma and put the new frame on the queue.
2141 * This should never fail since we check above that no frames
2142 * are still pending on the queue.
2143 */
2144 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2145 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2146 /* NB: hw still stops DMA, so proceed */
2147 }
fa1c114f 2148
c6e387a2
NK		 2149 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2150 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2151 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2152 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2153
2154 sc->bsent++;
2155}
2156
2157
9804b98d
BR		 2158/**
2159 * ath5k_beacon_update_timers - update beacon timers
2160 *
2161 * @sc: struct ath5k_softc pointer we are operating on
2162 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2163 * beacon timer update based on the current HW TSF.
2164 *
2165 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2166 * of a received beacon or the current local hardware TSF and write it to the
2167 * beacon timer registers.
2168 *
2169 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2170 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2171 * when we otherwise know we have to update the timers, but we keep it in this
2172 * function to have it all together in one place.
2173 */
fa1c114f 2174static void
9804b98d 2175ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2176{
2177 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2178 u32 nexttbtt, intval, hw_tu, bc_tu;
2179 u64 hw_tsf;
fa1c114f
JS		 2180
2181 intval = sc->bintval & AR5K_BEACON_PERIOD;
2182 if (WARN_ON(!intval))
2183 return;
2184
9804b98d
BR		 2185 /* beacon TSF converted to TU */
2186 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2187
9804b98d
BR		 2188 /* current TSF converted to TU */
2189 hw_tsf = ath5k_hw_get_tsf64(ah);
2190 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2191
9804b98d
BR		 2192#define FUDGE 3
2193 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2194 if (bc_tsf == -1) {
2195 /*
2196 * no beacons received, called internally.
2197 * just need to refresh timers based on HW TSF.
2198 */
2199 nexttbtt = roundup(hw_tu + FUDGE, intval);
2200 } else if (bc_tsf == 0) {
2201 /*
2202 * no beacon received, probably called by ath5k_reset_tsf().
2203 * reset TSF to start with 0.
2204 */
2205 nexttbtt = intval;
2206 intval |= AR5K_BEACON_RESET_TSF;
2207 } else if (bc_tsf > hw_tsf) {
2208 /*
2209 * beacon received, SW merge happend but HW TSF not yet updated.
2210 * not possible to reconfigure timers yet, but next time we
2211 * receive a beacon with the same BSSID, the hardware will
2212 * automatically update the TSF and then we need to reconfigure
2213 * the timers.
2214 */
2215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2216 "need to wait for HW TSF sync\n");
2217 return;
2218 } else {
2219 /*
2220 * most important case for beacon synchronization between STA.
2221 *
2222 * beacon received and HW TSF has been already updated by HW.
2223 * update next TBTT based on the TSF of the beacon, but make
2224 * sure it is ahead of our local TSF timer.
2225 */
2226 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2227 }
2228#undef FUDGE
fa1c114f 2229
036cd1ec
BR		 2230 sc->nexttbtt = nexttbtt;
2231
fa1c114f 2232 intval |= AR5K_BEACON_ENA;
fa1c114f 2233 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2234
2235 /*
2236 * debugging output last in order to preserve the time critical aspect
2237 * of this function
2238 */
2239 if (bc_tsf == -1)
2240 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2241 "reconfigured timers based on HW TSF\n");
2242 else if (bc_tsf == 0)
2243 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2244 "reset HW TSF and timers\n");
2245 else
2246 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2247 "updated timers based on beacon TSF\n");
2248
2249 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2250 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2251 (unsigned long long) bc_tsf,
2252 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2254 intval & AR5K_BEACON_PERIOD,
2255 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2256 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2257}
2258
2259
036cd1ec
BR		 2260/**
2261 * ath5k_beacon_config - Configure the beacon queues and interrupts
2262 *
2263 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2264 *
036cd1ec 2265 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2266 * interrupts to detect TSF updates only.
fa1c114f
JS		 2267 */
2268static void
2269ath5k_beacon_config(struct ath5k_softc *sc)
2270{
2271 struct ath5k_hw *ah = sc->ah;
b5f03956 2272 unsigned long flags;
fa1c114f 2273
c6e387a2 2274 ath5k_hw_set_imr(ah, 0);
fa1c114f 2275 sc->bmisscount = 0;
dc1968e7 2276 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2277
1e3e6e8f 2278 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2279 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2280 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2281 /*
036cd1ec
BR		 2282 * In IBSS mode we use a self-linked tx descriptor and let the
2283 * hardware send the beacons automatically. We have to load it
fa1c114f 2284 * only once here.
036cd1ec 2285 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2286 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2287 */
2288 ath5k_beaconq_config(sc);
fa1c114f 2289
036cd1ec
BR		 2290 sc->imask |= AR5K_INT_SWBA;
2291
da966bca
JS		 2292 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2293 if (ath5k_hw_hasveol(ah)) {
b5f03956 2294 spin_lock_irqsave(&sc->block, flags);
da966bca 2295 ath5k_beacon_send(sc);
b5f03956 2296 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2297 }
2298 } else
2299 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2300 }
fa1c114f 2301
c6e387a2 2302 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2303}
2304
2305
2306/********************\
2307* Interrupt handling *
2308\********************/
2309
2310static int
bb2becac 2311ath5k_init(struct ath5k_softc *sc)
fa1c114f 2312{
bc1b32d6
EO		 2313 struct ath5k_hw *ah = sc->ah;
2314 int ret, i;
fa1c114f
JS		 2315
2316 mutex_lock(&sc->lock);
2317
2318 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2319
2320 /*
2321 * Stop anything previously setup. This is safe
2322 * no matter this is the first time through or not.
2323 */
2324 ath5k_stop_locked(sc);
2325
2326 /*
2327 * The basic interface to setting the hardware in a good
2328 * state is ``reset''. On return the hardware is known to
2329 * be powered up and with interrupts disabled. This must
2330 * be followed by initialization of the appropriate bits
2331 * and then setup of the interrupt mask.
2332 */
d8ee398d
LR		 2333 sc->curchan = sc->hw->conf.channel;
2334 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2335 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2336 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2337 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
d7dc1003
JS		 2338 ret = ath5k_reset(sc, false, false);
2339 if (ret)
2340 goto done;
fa1c114f 2341
bc1b32d6
EO		 2342 /*
2343 * Reset the key cache since some parts do not reset the
2344 * contents on initial power up or resume from suspend.
2345 */
2346 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2347 ath5k_hw_reset_key(ah, i);
2348
fa1c114f 2349 /* Set ack to be sent at low bit-rates */
bc1b32d6 2350 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2351
2352 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2353 msecs_to_jiffies(ath5k_calinterval * 1000)));
2354
2355 ret = 0;
2356done:
274c7c36 2357 mmiowb();
fa1c114f
JS		 2358 mutex_unlock(&sc->lock);
2359 return ret;
2360}
2361
2362static int
2363ath5k_stop_locked(struct ath5k_softc *sc)
2364{
2365 struct ath5k_hw *ah = sc->ah;
2366
2367 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2368 test_bit(ATH_STAT_INVALID, sc->status));
2369
2370 /*
2371 * Shutdown the hardware and driver:
2372 * stop output from above
2373 * disable interrupts
2374 * turn off timers
2375 * turn off the radio
2376 * clear transmit machinery
2377 * clear receive machinery
2378 * drain and release tx queues
2379 * reclaim beacon resources
2380 * power down hardware
2381 *
2382 * Note that some of this work is not possible if the
2383 * hardware is gone (invalid).
2384 */
2385 ieee80211_stop_queues(sc->hw);
2386
2387 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2388 ath5k_led_off(sc);
c6e387a2 2389 ath5k_hw_set_imr(ah, 0);
274c7c36 2390 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2391 }
2392 ath5k_txq_cleanup(sc);
2393 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2394 ath5k_rx_stop(sc);
2395 ath5k_hw_phy_disable(ah);
2396 } else
2397 sc->rxlink = NULL;
2398
2399 return 0;
2400}
2401
2402/*
2403 * Stop the device, grabbing the top-level lock to protect
2404 * against concurrent entry through ath5k_init (which can happen
2405 * if another thread does a system call and the thread doing the
2406 * stop is preempted).
2407 */
2408static int
bb2becac 2409ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2410{
2411 int ret;
2412
2413 mutex_lock(&sc->lock);
2414 ret = ath5k_stop_locked(sc);
2415 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2416 /*
2417 * Set the chip in full sleep mode. Note that we are
2418 * careful to do this only when bringing the interface
2419 * completely to a stop. When the chip is in this state
2420 * it must be carefully woken up or references to
2421 * registers in the PCI clock domain may freeze the bus
2422 * (and system). This varies by chip and is mostly an
2423 * issue with newer parts that go to sleep more quickly.
2424 */
2425 if (sc->ah->ah_mac_srev >= 0x78) {
2426 /*
2427 * XXX
2428 * don't put newer MAC revisions > 7.8 to sleep because
2429 * of the above mentioned problems
2430 */
2431 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2432 "not putting device to sleep\n");
2433 } else {
2434 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2435 "putting device to full sleep\n");
2436 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2437 }
2438 }
2439 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2440
274c7c36 2441 mmiowb();
fa1c114f
JS		 2442 mutex_unlock(&sc->lock);
2443
2444 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2445 tasklet_kill(&sc->rxtq);
2446 tasklet_kill(&sc->txtq);
2447 tasklet_kill(&sc->restq);
acf3c1a5 2448 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2449
2450 return ret;
2451}
2452
2453static irqreturn_t
2454ath5k_intr(int irq, void *dev_id)
2455{
2456 struct ath5k_softc *sc = dev_id;
2457 struct ath5k_hw *ah = sc->ah;
2458 enum ath5k_int status;
2459 unsigned int counter = 1000;
2460
2461 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2462 !ath5k_hw_is_intr_pending(ah)))
2463 return IRQ_NONE;
2464
2465 do {
fa1c114f
JS		 2466 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2467 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2468 status, sc->imask);
fa1c114f
JS		 2469 if (unlikely(status & AR5K_INT_FATAL)) {
2470 /*
2471 * Fatal errors are unrecoverable.
2472 * Typically these are caused by DMA errors.
2473 */
2474 tasklet_schedule(&sc->restq);
2475 } else if (unlikely(status & AR5K_INT_RXORN)) {
2476 tasklet_schedule(&sc->restq);
2477 } else {
2478 if (status & AR5K_INT_SWBA) {
acf3c1a5 2479 tasklet_schedule(&sc->beacontq);
fa1c114f
JS		 2480 }
2481 if (status & AR5K_INT_RXEOL) {
2482 /*
2483 * NB: the hardware should re-read the link when
2484 * RXE bit is written, but it doesn't work at
2485 * least on older hardware revs.
2486 */
2487 sc->rxlink = NULL;
2488 }
2489 if (status & AR5K_INT_TXURN) {
2490 /* bump tx trigger level */
2491 ath5k_hw_update_tx_triglevel(ah, true);
2492 }
4c674c60 2493 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2494 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2495 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2496 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2497 tasklet_schedule(&sc->txtq);
2498 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2499 /* TODO */
fa1c114f
JS		 2500 }
2501 if (status & AR5K_INT_MIB) {
194828a2
NK		 2502 /*
2503 * These stats are also used for ANI i think
2504 * so how about updating them more often ?
2505 */
2506 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2507 }
2508 }
2509 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2510
2511 if (unlikely(!counter))
2512 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2513
2514 return IRQ_HANDLED;
2515}
2516
2517static void
2518ath5k_tasklet_reset(unsigned long data)
2519{
2520 struct ath5k_softc *sc = (void *)data;
2521
d7dc1003 2522 ath5k_reset_wake(sc);
fa1c114f
JS		 2523}
2524
2525/*
2526 * Periodically recalibrate the PHY to account
2527 * for temperature/environment changes.
2528 */
2529static void
2530ath5k_calibrate(unsigned long data)
2531{
2532 struct ath5k_softc *sc = (void *)data;
2533 struct ath5k_hw *ah = sc->ah;
2534
2535 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2536 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2537 sc->curchan->hw_value);
fa1c114f 2538
6f3b414a 2539 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2540 /*
2541 * Rfgain is out of bounds, reset the chip
2542 * to load new gain values.
2543 */
2544 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2545 ath5k_reset_wake(sc);
fa1c114f
JS		 2546 }
2547 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2548 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2549 ieee80211_frequency_to_channel(
2550 sc->curchan->center_freq));
fa1c114f
JS		 2551
2552 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2553 msecs_to_jiffies(ath5k_calinterval * 1000)));
2554}
2555
2556
fa1c114f
JS		 2557/********************\
2558* Mac80211 functions *
2559\********************/
2560
2561static int
e039fa4a 2562ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2563{
2564 struct ath5k_softc *sc = hw->priv;
2565 struct ath5k_buf *bf;
2566 unsigned long flags;
2567 int hdrlen;
0fe45b1d 2568 int padsize;
fa1c114f
JS		 2569
2570 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2571
05c914fe 2572 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2573 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2574
2575 /*
2576 * the hardware expects the header padded to 4 byte boundaries
2577 * if this is not the case we add the padding after the header
2578 */
2579 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2580 padsize = ath5k_pad_size(hdrlen);
2581 if (padsize) {
0fe45b1d
BP		 2582
2583 if (skb_headroom(skb) < padsize) {
fa1c114f 2584 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2585 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2586 goto drop_packet;
fa1c114f 2587 }
0fe45b1d
BP		 2588 skb_push(skb, padsize);
2589 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2590 }
2591
fa1c114f
JS		 2592 spin_lock_irqsave(&sc->txbuflock, flags);
2593 if (list_empty(&sc->txbuf)) {
2594 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2595 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2596 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2597 goto drop_packet;
fa1c114f
JS		 2598 }
2599 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2600 list_del(&bf->list);
2601 sc->txbuf_len--;
2602 if (list_empty(&sc->txbuf))
2603 ieee80211_stop_queues(hw);
2604 spin_unlock_irqrestore(&sc->txbuflock, flags);
2605
2606 bf->skb = skb;
2607
e039fa4a 2608 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2609 bf->skb = NULL;
2610 spin_lock_irqsave(&sc->txbuflock, flags);
2611 list_add_tail(&bf->list, &sc->txbuf);
2612 sc->txbuf_len++;
2613 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2614 goto drop_packet;
fa1c114f 2615 }
5a0fe8ac 2616 return NETDEV_TX_OK;
fa1c114f 2617
5a0fe8ac
BC		 2618drop_packet:
2619 dev_kfree_skb_any(skb);
71ef99c8 2620 return NETDEV_TX_OK;
fa1c114f
JS		 2621}
2622
2623static int
d7dc1003 2624ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2625{
fa1c114f
JS		 2626 struct ath5k_hw *ah = sc->ah;
2627 int ret;
2628
2629 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2630
d7dc1003 2631 if (stop) {
c6e387a2 2632 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2633 ath5k_txq_cleanup(sc);
2634 ath5k_rx_stop(sc);
2635 }
fa1c114f 2636 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2637 if (ret) {
fa1c114f
JS		 2638 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2639 goto err;
2640 }
d7dc1003 2641
fa1c114f 2642 ret = ath5k_rx_start(sc);
d7dc1003 2643 if (ret) {
fa1c114f
JS		 2644 ATH5K_ERR(sc, "can't start recv logic\n");
2645 goto err;
2646 }
d7dc1003 2647
fa1c114f 2648 /*
d7dc1003
JS		 2649 * Change channels and update the h/w rate map if we're switching;
2650 * e.g. 11a to 11b/g.
2651 *
2652 * We may be doing a reset in response to an ioctl that changes the
2653 * channel so update any state that might change as a result.
fa1c114f
JS		 2654 *
2655 * XXX needed?
2656 */
2657/* ath5k_chan_change(sc, c); */
fa1c114f 2658
d7dc1003
JS		 2659 ath5k_beacon_config(sc);
2660 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2661
2662 return 0;
2663err:
2664 return ret;
2665}
2666
d7dc1003
JS		 2667static int
2668ath5k_reset_wake(struct ath5k_softc *sc)
2669{
2670 int ret;
2671
2672 ret = ath5k_reset(sc, true, true);
2673 if (!ret)
2674 ieee80211_wake_queues(sc->hw);
2675
2676 return ret;
2677}
2678
fa1c114f
JS		 2679static int ath5k_start(struct ieee80211_hw *hw)
2680{
bb2becac 2681 return ath5k_init(hw->priv);
fa1c114f
JS		 2682}
2683
2684static void ath5k_stop(struct ieee80211_hw *hw)
2685{
bb2becac 2686 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2687}
2688
2689static int ath5k_add_interface(struct ieee80211_hw *hw,
2690 struct ieee80211_if_init_conf *conf)
2691{
2692 struct ath5k_softc *sc = hw->priv;
2693 int ret;
2694
2695 mutex_lock(&sc->lock);
32bfd35d 2696 if (sc->vif) {
fa1c114f
JS		 2697 ret = 0;
2698 goto end;
2699 }
2700
32bfd35d 2701 sc->vif = conf->vif;
fa1c114f
JS		 2702
2703 switch (conf->type) {
da966bca 2704 case NL80211_IFTYPE_AP:
05c914fe
JB		 2705 case NL80211_IFTYPE_STATION:
2706 case NL80211_IFTYPE_ADHOC:
b706e65b 2707 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2708 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2709 sc->opmode = conf->type;
2710 break;
2711 default:
2712 ret = -EOPNOTSUPP;
2713 goto end;
2714 }
67d2e2df
JS		 2715
2716 /* Set to a reasonable value. Note that this will
2717 * be set to mac80211's value at ath5k_config(). */
2718 sc->bintval = 1000;
0e149cf5 2719 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2720
fa1c114f
JS		 2721 ret = 0;
2722end:
2723 mutex_unlock(&sc->lock);
2724 return ret;
2725}
2726
2727static void
2728ath5k_remove_interface(struct ieee80211_hw *hw,
2729 struct ieee80211_if_init_conf *conf)
2730{
2731 struct ath5k_softc *sc = hw->priv;
0e149cf5 2732 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2733
2734 mutex_lock(&sc->lock);
32bfd35d 2735 if (sc->vif != conf->vif)
fa1c114f
JS		 2736 goto end;
2737
0e149cf5 2738 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2739 sc->vif = NULL;
fa1c114f
JS		 2740end:
2741 mutex_unlock(&sc->lock);
2742}
2743
d8ee398d
LR		 2744/*
2745 * TODO: Phy disable/diversity etc
2746 */
fa1c114f 2747static int
e8975581 2748ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2749{
2750 struct ath5k_softc *sc = hw->priv;
e8975581 2751 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2752 int ret;
2753
2754 mutex_lock(&sc->lock);
fa1c114f 2755
e535c1ac 2756 sc->bintval = conf->beacon_int;
d8ee398d 2757 sc->power_level = conf->power_level;
fa1c114f 2758
be009370
BC		 2759 ret = ath5k_chan_set(sc, conf->channel);
2760
2761 mutex_unlock(&sc->lock);
2762 return ret;
fa1c114f
JS		 2763}
2764
2765static int
32bfd35d 2766ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
fa1c114f
JS		 2767 struct ieee80211_if_conf *conf)
2768{
2769 struct ath5k_softc *sc = hw->priv;
2770 struct ath5k_hw *ah = sc->ah;
fa8419d0 2771 int ret = 0;
fa1c114f 2772
fa1c114f 2773 mutex_lock(&sc->lock);
32bfd35d 2774 if (sc->vif != vif) {
fa1c114f
JS		 2775 ret = -EIO;
2776 goto unlock;
2777 }
da966bca 2778 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
fa1c114f
JS		 2779 /* Cache for later use during resets */
2780 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2781 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2782 * a clean way of letting us retrieve this yet. */
2783 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
274c7c36 2784 mmiowb();
fa1c114f 2785 }
9d139c81 2786 if (conf->changed & IEEE80211_IFCC_BEACON &&
da966bca 2787 (vif->type == NL80211_IFTYPE_ADHOC ||
b706e65b 2788 vif->type == NL80211_IFTYPE_MESH_POINT ||
da966bca 2789 vif->type == NL80211_IFTYPE_AP)) {
9d139c81
JB		 2790 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2791 if (!beacon) {
2792 ret = -ENOMEM;
2793 goto unlock;
2794 }
da966bca 2795 ath5k_beacon_update(sc, beacon);
9d139c81 2796 }
fa1c114f 2797
fa1c114f
JS		 2798unlock:
2799 mutex_unlock(&sc->lock);
2800 return ret;
2801}
2802
2803#define SUPPORTED_FIF_FLAGS \
2804 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2805 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2806 FIF_BCN_PRBRESP_PROMISC
2807/*
2808 * o always accept unicast, broadcast, and multicast traffic
2809 * o multicast traffic for all BSSIDs will be enabled if mac80211
2810 * says it should be
2811 * o maintain current state of phy ofdm or phy cck error reception.
2812 * If the hardware detects any of these type of errors then
2813 * ath5k_hw_get_rx_filter() will pass to us the respective
2814 * hardware filters to be able to receive these type of frames.
2815 * o probe request frames are accepted only when operating in
2816 * hostap, adhoc, or monitor modes
2817 * o enable promiscuous mode according to the interface state
2818 * o accept beacons:
2819 * - when operating in adhoc mode so the 802.11 layer creates
2820 * node table entries for peers,
2821 * - when operating in station mode for collecting rssi data when
2822 * the station is otherwise quiet, or
2823 * - when scanning
2824 */
2825static void ath5k_configure_filter(struct ieee80211_hw *hw,
2826 unsigned int changed_flags,
2827 unsigned int *new_flags,
2828 int mc_count, struct dev_mc_list *mclist)
2829{
2830 struct ath5k_softc *sc = hw->priv;
2831 struct ath5k_hw *ah = sc->ah;
2832 u32 mfilt[2], val, rfilt;
2833 u8 pos;
2834 int i;
2835
2836 mfilt[0] = 0;
2837 mfilt[1] = 0;
2838
2839 /* Only deal with supported flags */
2840 changed_flags &= SUPPORTED_FIF_FLAGS;
2841 *new_flags &= SUPPORTED_FIF_FLAGS;
2842
2843 /* If HW detects any phy or radar errors, leave those filters on.
2844 * Also, always enable Unicast, Broadcasts and Multicast
2845 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2846 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2847 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2848 AR5K_RX_FILTER_MCAST);
2849
2850 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2851 if (*new_flags & FIF_PROMISC_IN_BSS) {
2852 rfilt |= AR5K_RX_FILTER_PROM;
2853 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2854 } else {
fa1c114f 2855 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2856 }
fa1c114f
JS		 2857 }
2858
2859 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2860 if (*new_flags & FIF_ALLMULTI) {
2861 mfilt[0] = ~0;
2862 mfilt[1] = ~0;
2863 } else {
2864 for (i = 0; i < mc_count; i++) {
2865 if (!mclist)
2866 break;
2867 /* calculate XOR of eight 6-bit values */
533dd1b0 2868 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2869 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2870 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2871 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2872 pos &= 0x3f;
2873 mfilt[pos / 32] |= (1 << (pos % 32));
2874 /* XXX: we might be able to just do this instead,
2875 * but not sure, needs testing, if we do use this we'd
2876 * neet to inform below to not reset the mcast */
2877 /* ath5k_hw_set_mcast_filterindex(ah,
2878 * mclist->dmi_addr[5]); */
2879 mclist = mclist->next;
2880 }
2881 }
2882
2883 /* This is the best we can do */
2884 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2885 rfilt |= AR5K_RX_FILTER_PHYERR;
2886
2887 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2888 * and probes for any BSSID, this needs testing */
2889 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2890 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2891
2892 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2893 * set we should only pass on control frames for this
2894 * station. This needs testing. I believe right now this
2895 * enables *all* control frames, which is OK.. but
2896 * but we should see if we can improve on granularity */
2897 if (*new_flags & FIF_CONTROL)
2898 rfilt |= AR5K_RX_FILTER_CONTROL;
2899
2900 /* Additional settings per mode -- this is per ath5k */
2901
2902 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2903
05c914fe 2904 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2905 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2906 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2907 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2908 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2909 if (sc->opmode != NL80211_IFTYPE_AP &&
2910 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2911 test_bit(ATH_STAT_PROMISC, sc->status))
2912 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2913 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2914 sc->opmode == NL80211_IFTYPE_ADHOC ||
2915 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2916 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2917 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2918 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2919 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2920
2921 /* Set filters */
0bbac08f 2922 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2923
2924 /* Set multicast bits */
2925 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2926 /* Set the cached hw filter flags, this will alter actually
2927 * be set in HW */
2928 sc->filter_flags = rfilt;
2929}
2930
2931static int
2932ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2933 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2934 struct ieee80211_key_conf *key)
fa1c114f
JS		 2935{
2936 struct ath5k_softc *sc = hw->priv;
2937 int ret = 0;
2938
9ad9a26e
BC		 2939 if (modparam_nohwcrypt)
2940 return -EOPNOTSUPP;
2941
0bbac08f 2942 switch (key->alg) {
fa1c114f 2943 case ALG_WEP:
fa1c114f 2944 case ALG_TKIP:
3f64b435 2945 break;
fa1c114f
JS		 2946 case ALG_CCMP:
2947 return -EOPNOTSUPP;
2948 default:
2949 WARN_ON(1);
2950 return -EINVAL;
2951 }
2952
2953 mutex_lock(&sc->lock);
2954
2955 switch (cmd) {
2956 case SET_KEY:
dc822b5d
JB		 2957 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2958 sta ? sta->addr : NULL);
fa1c114f
JS		 2959 if (ret) {
2960 ATH5K_ERR(sc, "can't set the key\n");
2961 goto unlock;
2962 }
2963 __set_bit(key->keyidx, sc->keymap);
2964 key->hw_key_idx = key->keyidx;
3f64b435
BC		 2965 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2966 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 2967 break;
2968 case DISABLE_KEY:
2969 ath5k_hw_reset_key(sc->ah, key->keyidx);
2970 __clear_bit(key->keyidx, sc->keymap);
2971 break;
2972 default:
2973 ret = -EINVAL;
2974 goto unlock;
2975 }
2976
2977unlock:
274c7c36 2978 mmiowb();
fa1c114f
JS		 2979 mutex_unlock(&sc->lock);
2980 return ret;
2981}
2982
2983static int
2984ath5k_get_stats(struct ieee80211_hw *hw,
2985 struct ieee80211_low_level_stats *stats)
2986{
2987 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2988 struct ath5k_hw *ah = sc->ah;
2989
2990 /* Force update */
2991 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2992
2993 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2994
2995 return 0;
2996}
2997
2998static int
2999ath5k_get_tx_stats(struct ieee80211_hw *hw,
3000 struct ieee80211_tx_queue_stats *stats)
3001{
3002 struct ath5k_softc *sc = hw->priv;
3003
3004 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3005
3006 return 0;
3007}
3008
3009static u64
3010ath5k_get_tsf(struct ieee80211_hw *hw)
3011{
3012 struct ath5k_softc *sc = hw->priv;
3013
3014 return ath5k_hw_get_tsf64(sc->ah);
3015}
3016
3b5d665b
AF		 3017static void
3018ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3019{
3020 struct ath5k_softc *sc = hw->priv;
3021
3022 ath5k_hw_set_tsf64(sc->ah, tsf);
3023}
3024
fa1c114f
JS		 3025static void
3026ath5k_reset_tsf(struct ieee80211_hw *hw)
3027{
3028 struct ath5k_softc *sc = hw->priv;
3029
9804b98d
BR		 3030 /*
3031 * in IBSS mode we need to update the beacon timers too.
3032 * this will also reset the TSF if we call it with 0
3033 */
05c914fe 3034 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3035 ath5k_beacon_update_timers(sc, 0);
3036 else
3037 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3038}
3039
3040static int
da966bca 3041ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3042{
00482973 3043 unsigned long flags;
fa1c114f
JS		 3044 int ret;
3045
3046 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3047
00482973 3048 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3049 ath5k_txbuf_free(sc, sc->bbuf);
3050 sc->bbuf->skb = skb;
e039fa4a 3051 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3052 if (ret)
3053 sc->bbuf->skb = NULL;
00482973
JS		 3054 spin_unlock_irqrestore(&sc->block, flags);
3055 if (!ret) {
fa1c114f 3056 ath5k_beacon_config(sc);
274c7c36
JS		 3057 mmiowb();
3058 }
fa1c114f 3059
fa1c114f
JS		 3060 return ret;
3061}
02969b38
MX		 3062static void
3063set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3064{
3065 struct ath5k_softc *sc = hw->priv;
3066 struct ath5k_hw *ah = sc->ah;
3067 u32 rfilt;
3068 rfilt = ath5k_hw_get_rx_filter(ah);
3069 if (enable)
3070 rfilt |= AR5K_RX_FILTER_BEACON;
3071 else
3072 rfilt &= ~AR5K_RX_FILTER_BEACON;
3073 ath5k_hw_set_rx_filter(ah, rfilt);
3074 sc->filter_flags = rfilt;
3075}
fa1c114f 3076
02969b38
MX		 3077static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3078 struct ieee80211_vif *vif,
3079 struct ieee80211_bss_conf *bss_conf,
3080 u32 changes)
3081{
3082 struct ath5k_softc *sc = hw->priv;
3083 if (changes & BSS_CHANGED_ASSOC) {
3084 mutex_lock(&sc->lock);
3085 sc->assoc = bss_conf->assoc;
3086 if (sc->opmode == NL80211_IFTYPE_STATION)
3087 set_beacon_filter(hw, sc->assoc);
3088 mutex_unlock(&sc->lock);
3089 }
3090}
Clone of davem's net-next-2.6 tree