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Merge branch 'fix/asoc' into for-linus
[net-next-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom.h
CommitLineData
394cf0a1 1/*
cee075a2 2 * Copyright (c) 2008-2009 Atheros Communications Inc.
394cf0a1
S		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef EEPROM_H
18#define EEPROM_H
19
5bb12791 20#include "../ath.h"
d3236553 21#include <net/cfg80211.h>
15c9ee7a 22#include "ar9003_eeprom.h"
3a702e49 23
394cf0a1
S		 24#define AH_USE_EEPROM 0x1
25
26#ifdef __BIG_ENDIAN
27#define AR5416_EEPROM_MAGIC 0x5aa5
28#else
29#define AR5416_EEPROM_MAGIC 0xa55a
30#endif
31
32#define CTRY_DEBUG 0x1ff
33#define CTRY_DEFAULT 0
34
35#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
36#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
37#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
38#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
39#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
40#define AR_EEPROM_EEPCAP_MAXQCU_S 4
41#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
42#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
43#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
44
45#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
46#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
47#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
48#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
49#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
50#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
51
52#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
53#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
54
55#define AR5416_EEPROM_MAGIC_OFFSET 0x0
56#define AR5416_EEPROM_S 2
57#define AR5416_EEPROM_OFFSET 0x2000
58#define AR5416_EEPROM_MAX 0xae0
59
60#define AR5416_EEPROM_START_ADDR \
61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
62
63#define SD_NO_CTL 0xE0
64#define NO_CTL 0xff
90487974 65#define CTL_MODE_M 0xf
394cf0a1
S		 66#define CTL_11A 0
67#define CTL_11B 1
68#define CTL_11G 2
69#define CTL_2GHT20 5
70#define CTL_5GHT20 6
71#define CTL_2GHT40 7
72#define CTL_5GHT40 8
73
74#define EXT_ADDITIVE (0x8000)
75#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
76#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
77#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
78
79#define SUB_NUM_CTL_MODES_AT_5G_40 2
80#define SUB_NUM_CTL_MODES_AT_2G_40 3
81
e421c7b3
S		 82#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
83#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
84
fec0de11
S		 85/*
86 * For AR9285 and later chipsets, the following bits are not being programmed
87 * in EEPROM and so need to be enabled always.
88 *
89 * Bit 0: en_fcc_mid
90 * Bit 1: en_jap_mid
91 * Bit 2: en_fcc_dfs_ht40
92 * Bit 3: en_jap_ht40
93 * Bit 4: en_jap_dfs_ht40
94 */
95#define AR9285_RDEXT_DEFAULT 0x1F
96
394cf0a1
S		 97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100
355363fc 101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
d9ae96d9
S		 102#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
ac88b6ec
VN		 104#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
d9ae96d9 106
394cf0a1
S		 107#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
108#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
109#define AR_EEPROM_RFSILENT_POLARITY 0x0002
110#define AR_EEPROM_RFSILENT_POLARITY_S 1
111
112#define EEP_RFSILENT_ENABLED 0x0001
113#define EEP_RFSILENT_ENABLED_S 0
114#define EEP_RFSILENT_POLARITY 0x0002
115#define EEP_RFSILENT_POLARITY_S 1
116#define EEP_RFSILENT_GPIO_SEL 0x001c
117#define EEP_RFSILENT_GPIO_SEL_S 2
118
119#define AR5416_OPFLAGS_11A 0x01
120#define AR5416_OPFLAGS_11G 0x02
121#define AR5416_OPFLAGS_N_5G_HT40 0x04
122#define AR5416_OPFLAGS_N_2G_HT40 0x08
123#define AR5416_OPFLAGS_N_5G_HT20 0x10
124#define AR5416_OPFLAGS_N_2G_HT20 0x20
125
126#define AR5416_EEP_NO_BACK_VER 0x1
127#define AR5416_EEP_VER 0xE
128#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
129#define AR5416_EEP_MINOR_VER_2 0x2
130#define AR5416_EEP_MINOR_VER_3 0x3
131#define AR5416_EEP_MINOR_VER_7 0x7
132#define AR5416_EEP_MINOR_VER_9 0x9
133#define AR5416_EEP_MINOR_VER_16 0x10
134#define AR5416_EEP_MINOR_VER_17 0x11
135#define AR5416_EEP_MINOR_VER_19 0x13
136#define AR5416_EEP_MINOR_VER_20 0x14
e41f0bfc 137#define AR5416_EEP_MINOR_VER_21 0x15
06d0f066 138#define AR5416_EEP_MINOR_VER_22 0x16
394cf0a1
S		 139
140#define AR5416_NUM_5G_CAL_PIERS 8
141#define AR5416_NUM_2G_CAL_PIERS 4
142#define AR5416_NUM_5G_20_TARGET_POWERS 8
143#define AR5416_NUM_5G_40_TARGET_POWERS 8
144#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
145#define AR5416_NUM_2G_20_TARGET_POWERS 4
146#define AR5416_NUM_2G_40_TARGET_POWERS 4
147#define AR5416_NUM_CTLS 24
148#define AR5416_NUM_BAND_EDGES 8
149#define AR5416_NUM_PD_GAINS 4
150#define AR5416_PD_GAINS_IN_MASK 4
151#define AR5416_PD_GAIN_ICEPTS 5
152#define AR5416_EEPROM_MODAL_SPURS 5
153#define AR5416_MAX_RATE_POWER 63
154#define AR5416_NUM_PDADC_VALUES 128
155#define AR5416_BCHAN_UNUSED 0xFF
156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
157#define AR5416_MAX_CHAINS 3
df23acaa 158#define AR9300_MAX_CHAINS 3
e41f0bfc 159#define AR5416_PWR_TABLE_OFFSET_DB -5
394cf0a1
S		 160
161/* Rx gain type values */
162#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
163#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
164#define AR5416_EEP_RXGAIN_ORIG 2
165
166/* Tx gain type values */
167#define AR5416_EEP_TXGAIN_ORIGINAL 0
168#define AR5416_EEP_TXGAIN_HIGH_POWER 1
169
170#define AR5416_EEP4K_START_LOC 64
171#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
172#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
173#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
174#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
175#define AR5416_EEP4K_NUM_CTLS 12
176#define AR5416_EEP4K_NUM_BAND_EDGES 4
177#define AR5416_EEP4K_NUM_PD_GAINS 2
178#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
179#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
180#define AR5416_EEP4K_MAX_CHAINS 1
181
8bd1d07f
SB		 182#define AR9280_TX_GAIN_TABLE_SIZE 22
183
ac88b6ec
VN		 184#define AR9287_EEP_VER 0xE
185#define AR9287_EEP_VER_MINOR_MASK 0xFFF
186#define AR9287_EEP_MINOR_VER_1 0x1
187#define AR9287_EEP_MINOR_VER_2 0x2
188#define AR9287_EEP_MINOR_VER_3 0x3
189#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
190#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
191#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
192
193#define AR9287_EEP_START_LOC 128
ca6cff1f 194#define AR9287_HTC_EEP_START_LOC 256
ac88b6ec
VN		 195#define AR9287_NUM_2G_CAL_PIERS 3
196#define AR9287_NUM_2G_CCK_TARGET_POWERS 3
197#define AR9287_NUM_2G_20_TARGET_POWERS 3
198#define AR9287_NUM_2G_40_TARGET_POWERS 3
199#define AR9287_NUM_CTLS 12
200#define AR9287_NUM_BAND_EDGES 4
201#define AR9287_NUM_PD_GAINS 4
202#define AR9287_PD_GAINS_IN_MASK 4
203#define AR9287_PD_GAIN_ICEPTS 1
204#define AR9287_EEPROM_MODAL_SPURS 5
205#define AR9287_MAX_RATE_POWER 63
206#define AR9287_NUM_PDADC_VALUES 128
207#define AR9287_NUM_RATES 16
208#define AR9287_BCHAN_UNUSED 0xFF
209#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
210#define AR9287_OPFLAGS_11A 0x01
211#define AR9287_OPFLAGS_11G 0x02
212#define AR9287_OPFLAGS_2G_HT40 0x08
213#define AR9287_OPFLAGS_2G_HT20 0x20
214#define AR9287_OPFLAGS_5G_HT40 0x04
215#define AR9287_OPFLAGS_5G_HT20 0x10
216#define AR9287_EEPMISC_BIG_ENDIAN 0x01
217#define AR9287_EEPMISC_WOW 0x02
218#define AR9287_MAX_CHAINS 2
219#define AR9287_ANT_16S 32
220#define AR9287_custdatasize 20
221
222#define AR9287_NUM_ANT_CHAIN_FIELDS 6
223#define AR9287_NUM_ANT_COMMON_FIELDS 4
224#define AR9287_SIZE_ANT_CHAIN_FIELD 2
225#define AR9287_SIZE_ANT_COMMON_FIELD 4
226#define AR9287_ANT_CHAIN_MASK 0x3
227#define AR9287_ANT_COMMON_MASK 0xf
228#define AR9287_CHAIN_0_IDX 0
229#define AR9287_CHAIN_1_IDX 1
230#define AR9287_DATA_SZ 32
231
232#define AR9287_PWR_TABLE_OFFSET_DB -5
233
234#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
235
394cf0a1
S		 236enum eeprom_param {
237 EEP_NFTHRESH_5,
238 EEP_NFTHRESH_2,
239 EEP_MAC_MSW,
240 EEP_MAC_MID,
241 EEP_MAC_LSW,
242 EEP_REG_0,
243 EEP_REG_1,
244 EEP_OP_CAP,
245 EEP_OP_MODE,
246 EEP_RF_SILENT,
247 EEP_OB_5,
248 EEP_DB_5,
249 EEP_OB_2,
250 EEP_DB_2,
251 EEP_MINOR_REV,
252 EEP_TX_MASK,
253 EEP_RX_MASK,
15c9ee7a 254 EEP_FSTCLK_5G,
394cf0a1 255 EEP_RXGAIN_TYPE,
8bd1d07f 256 EEP_OL_PWRCTRL,
15c9ee7a 257 EEP_TXGAIN_TYPE,
8bd1d07f 258 EEP_RC_CHAIN_MASK,
394cf0a1 259 EEP_DAC_HPWR_5G,
ac88b6ec
VN		 260 EEP_FRAC_N_5G,
261 EEP_DEV_TYPE,
262 EEP_TEMPSENSE_SLOPE,
263 EEP_TEMPSENSE_SLOPE_PAL_ON,
15c9ee7a
SB		 264 EEP_PWR_TABLE_OFFSET,
265 EEP_DRIVE_STRENGTH,
266 EEP_INTERNAL_REGULATOR,
4935250a
FF		 267 EEP_SWREG,
268 EEP_PAPRD,
394cf0a1
S		 269};
270
271enum ar5416_rates {
272 rate6mb, rate9mb, rate12mb, rate18mb,
273 rate24mb, rate36mb, rate48mb, rate54mb,
274 rate1l, rate2l, rate2s, rate5_5l,
275 rate5_5s, rate11l, rate11s, rateXr,
276 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
277 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
278 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
279 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
280 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
281 Ar5416RateSize
282};
283
284enum ath9k_hal_freq_band {
285 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
286 ATH9K_HAL_FREQ_BAND_2GHZ = 1
287};
288
289struct base_eep_header {
290 u16 length;
291 u16 checksum;
292 u16 version;
293 u8 opCapFlags;
294 u8 eepMisc;
295 u16 regDmn[2];
296 u8 macAddr[6];
297 u8 rxMask;
298 u8 txMask;
299 u16 rfSilent;
300 u16 blueToothOptions;
301 u16 deviceCap;
302 u32 binBuildNumber;
303 u8 deviceType;
304 u8 pwdclkind;
5b75d0fc
FF		 305 u8 fastClk5g;
306 u8 divChain;
394cf0a1
S		 307 u8 rxGainType;
308 u8 dacHiPwrMode_5G;
8bd1d07f 309 u8 openLoopPwrCntl;
394cf0a1
S		 310 u8 dacLpMode;
311 u8 txGainType;
312 u8 rcChainMask;
313 u8 desiredScaleCCK;
e41f0bfc 314 u8 pwr_table_offset;
06d0f066
S		 315 u8 frac_n_5g;
316 u8 futureBase_3[21];
394cf0a1
S		 317} __packed;
318
319struct base_eep_header_4k {
320 u16 length;
321 u16 checksum;
322 u16 version;
323 u8 opCapFlags;
324 u8 eepMisc;
325 u16 regDmn[2];
326 u8 macAddr[6];
327 u8 rxMask;
328 u8 txMask;
329 u16 rfSilent;
330 u16 blueToothOptions;
331 u16 deviceCap;
332 u32 binBuildNumber;
333 u8 deviceType;
4e845168 334 u8 txGainType;
394cf0a1
S		 335} __packed;
336
337
338struct spur_chan {
339 u16 spurChan;
340 u8 spurRangeLow;
341 u8 spurRangeHigh;
342} __packed;
343
344struct modal_eep_header {
345 u32 antCtrlChain[AR5416_MAX_CHAINS];
346 u32 antCtrlCommon;
347 u8 antennaGainCh[AR5416_MAX_CHAINS];
348 u8 switchSettling;
349 u8 txRxAttenCh[AR5416_MAX_CHAINS];
350 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
351 u8 adcDesiredSize;
352 u8 pgaDesiredSize;
353 u8 xlnaGainCh[AR5416_MAX_CHAINS];
354 u8 txEndToXpaOff;
355 u8 txEndToRxOn;
356 u8 txFrameToXpaOn;
357 u8 thresh62;
358 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
359 u8 xpdGain;
360 u8 xpd;
361 u8 iqCalICh[AR5416_MAX_CHAINS];
362 u8 iqCalQCh[AR5416_MAX_CHAINS];
363 u8 pdGainOverlap;
364 u8 ob;
365 u8 db;
366 u8 xpaBiasLvl;
367 u8 pwrDecreaseFor2Chain;
368 u8 pwrDecreaseFor3Chain;
369 u8 txFrameToDataStart;
370 u8 txFrameToPaOn;
371 u8 ht40PowerIncForPdadc;
372 u8 bswAtten[AR5416_MAX_CHAINS];
373 u8 bswMargin[AR5416_MAX_CHAINS];
374 u8 swSettleHt40;
375 u8 xatten2Db[AR5416_MAX_CHAINS];
376 u8 xatten2Margin[AR5416_MAX_CHAINS];
377 u8 ob_ch1;
378 u8 db_ch1;
379 u8 useAnt1:1,
380 force_xpaon:1,
381 local_bias:1,
382 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
383 u8 miscBits;
384 u16 xpaBiasLvlFreq[3];
385 u8 futureModal[6];
386
387 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
388} __packed;
389
8bd1d07f
SB		 390struct calDataPerFreqOpLoop {
391 u8 pwrPdg[2][5];
392 u8 vpdPdg[2][5];
393 u8 pcdac[2][5];
394 u8 empty[2][5];
395} __packed;
396
394cf0a1 397struct modal_eep_4k_header {
c16c9d06
S		 398 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
399 u32 antCtrlCommon;
400 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
401 u8 switchSettling;
402 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
403 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
404 u8 adcDesiredSize;
405 u8 pgaDesiredSize;
406 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
407 u8 txEndToXpaOff;
408 u8 txEndToRxOn;
409 u8 txFrameToXpaOn;
410 u8 thresh62;
411 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
412 u8 xpdGain;
413 u8 xpd;
414 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
415 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
416 u8 pdGainOverlap;
7f63845f
S		 417#ifdef __BIG_ENDIAN_BITFIELD
418 u8 ob_1:4, ob_0:4;
419 u8 db1_1:4, db1_0:4;
420#else
421 u8 ob_0:4, ob_1:4;
422 u8 db1_0:4, db1_1:4;
423#endif
c16c9d06
S		 424 u8 xpaBiasLvl;
425 u8 txFrameToDataStart;
426 u8 txFrameToPaOn;
427 u8 ht40PowerIncForPdadc;
428 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
429 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
430 u8 swSettleHt40;
431 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
432 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
7f63845f
S		 433#ifdef __BIG_ENDIAN_BITFIELD
434 u8 db2_1:4, db2_0:4;
435#else
436 u8 db2_0:4, db2_1:4;
437#endif
c16c9d06 438 u8 version;
7f63845f
S		 439#ifdef __BIG_ENDIAN_BITFIELD
440 u8 ob_3:4, ob_2:4;
441 u8 antdiv_ctl1:4, ob_4:4;
442 u8 db1_3:4, db1_2:4;
443 u8 antdiv_ctl2:4, db1_4:4;
444 u8 db2_2:4, db2_3:4;
445 u8 reserved:4, db2_4:4;
446#else
447 u8 ob_2:4, ob_3:4;
448 u8 ob_4:4, antdiv_ctl1:4;
449 u8 db1_2:4, db1_3:4;
450 u8 db1_4:4, antdiv_ctl2:4;
451 u8 db2_2:4, db2_3:4;
452 u8 db2_4:4, reserved:4;
453#endif
c16c9d06 454 u8 futureModal[4];
394cf0a1
S		 455 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
456} __packed;
457
ac88b6ec 458struct base_eep_ar9287_header {
c16c9d06
S		 459 u16 length;
460 u16 checksum;
461 u16 version;
462 u8 opCapFlags;
463 u8 eepMisc;
464 u16 regDmn[2];
465 u8 macAddr[6];
466 u8 rxMask;
467 u8 txMask;
468 u16 rfSilent;
469 u16 blueToothOptions;
470 u16 deviceCap;
471 u32 binBuildNumber;
472 u8 deviceType;
473 u8 openLoopPwrCntl;
474 int8_t pwrTableOffset;
475 int8_t tempSensSlope;
476 int8_t tempSensSlopePalOn;
477 u8 futureBase[29];
ac88b6ec
VN		 478} __packed;
479
480struct modal_eep_ar9287_header {
c16c9d06
S		 481 u32 antCtrlChain[AR9287_MAX_CHAINS];
482 u32 antCtrlCommon;
483 int8_t antennaGainCh[AR9287_MAX_CHAINS];
484 u8 switchSettling;
485 u8 txRxAttenCh[AR9287_MAX_CHAINS];
486 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
487 int8_t adcDesiredSize;
488 u8 txEndToXpaOff;
489 u8 txEndToRxOn;
490 u8 txFrameToXpaOn;
491 u8 thresh62;
492 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
493 u8 xpdGain;
494 u8 xpd;
495 int8_t iqCalICh[AR9287_MAX_CHAINS];
496 int8_t iqCalQCh[AR9287_MAX_CHAINS];
497 u8 pdGainOverlap;
498 u8 xpaBiasLvl;
499 u8 txFrameToDataStart;
500 u8 txFrameToPaOn;
501 u8 ht40PowerIncForPdadc;
502 u8 bswAtten[AR9287_MAX_CHAINS];
503 u8 bswMargin[AR9287_MAX_CHAINS];
504 u8 swSettleHt40;
505 u8 version;
506 u8 db1;
507 u8 db2;
508 u8 ob_cck;
509 u8 ob_psk;
510 u8 ob_qam;
511 u8 ob_pal_off;
512 u8 futureModal[30];
513 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
ac88b6ec
VN		 514} __packed;
515
394cf0a1
S		 516struct cal_data_per_freq {
517 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
518 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
519} __packed;
520
521struct cal_data_per_freq_4k {
522 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
523 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
524} __packed;
525
526struct cal_target_power_leg {
527 u8 bChannel;
528 u8 tPow2x[4];
529} __packed;
530
531struct cal_target_power_ht {
532 u8 bChannel;
533 u8 tPow2x[8];
534} __packed;
535
536
537#ifdef __BIG_ENDIAN_BITFIELD
538struct cal_ctl_edges {
539 u8 bChannel;
540 u8 flag:2, tPower:6;
541} __packed;
542#else
543struct cal_ctl_edges {
544 u8 bChannel;
545 u8 tPower:6, flag:2;
546} __packed;
547#endif
548
ac88b6ec
VN		 549struct cal_data_op_loop_ar9287 {
550 u8 pwrPdg[2][5];
551 u8 vpdPdg[2][5];
552 u8 pcdac[2][5];
553 u8 empty[2][5];
554} __packed;
555
ac88b6ec
VN		 556struct cal_data_per_freq_ar9287 {
557 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
558 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
559} __packed;
560
561union cal_data_per_freq_ar9287_u {
562 struct cal_data_op_loop_ar9287 calDataOpen;
563 struct cal_data_per_freq_ar9287 calDataClose;
564} __packed;
565
566struct cal_ctl_data_ar9287 {
567 struct cal_ctl_edges
568 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
569} __packed;
570
394cf0a1
S		 571struct cal_ctl_data {
572 struct cal_ctl_edges
573 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
574} __packed;
575
576struct cal_ctl_data_4k {
577 struct cal_ctl_edges
578 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
579} __packed;
580
581struct ar5416_eeprom_def {
582 struct base_eep_header baseEepHeader;
583 u8 custData[64];
584 struct modal_eep_header modalHeader[2];
585 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
586 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
587 struct cal_data_per_freq
588 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
589 struct cal_data_per_freq
590 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
591 struct cal_target_power_leg
592 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
593 struct cal_target_power_ht
594 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
595 struct cal_target_power_ht
596 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
597 struct cal_target_power_leg
598 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
599 struct cal_target_power_leg
600 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
601 struct cal_target_power_ht
602 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
603 struct cal_target_power_ht
604 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
605 u8 ctlIndex[AR5416_NUM_CTLS];
606 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
607 u8 padding;
608} __packed;
609
610struct ar5416_eeprom_4k {
611 struct base_eep_header_4k baseEepHeader;
612 u8 custData[20];
613 struct modal_eep_4k_header modalHeader;
614 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
615 struct cal_data_per_freq_4k
616 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
617 struct cal_target_power_leg
618 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
619 struct cal_target_power_leg
620 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
621 struct cal_target_power_ht
622 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
623 struct cal_target_power_ht
624 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
625 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
626 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
627 u8 padding;
628} __packed;
629
475f5989 630struct ar9287_eeprom {
c16c9d06 631 struct base_eep_ar9287_header baseEepHeader;
ac88b6ec
VN		 632 u8 custData[AR9287_DATA_SZ];
633 struct modal_eep_ar9287_header modalHeader;
634 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
635 union cal_data_per_freq_ar9287_u
c16c9d06 636 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
ac88b6ec 637 struct cal_target_power_leg
c16c9d06 638 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
ac88b6ec 639 struct cal_target_power_leg
c16c9d06 640 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
ac88b6ec 641 struct cal_target_power_ht
c16c9d06 642 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
ac88b6ec 643 struct cal_target_power_ht
c16c9d06 644 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
ac88b6ec
VN		 645 u8 ctlIndex[AR9287_NUM_CTLS];
646 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
647 u8 padding;
648} __packed;
649
394cf0a1 650enum reg_ext_bitmap {
ebb90cfc 651 REG_EXT_FCC_MIDBAND = 0,
394cf0a1
S		 652 REG_EXT_JAPAN_MIDBAND = 1,
653 REG_EXT_FCC_DFS_HT40 = 2,
654 REG_EXT_JAPAN_NONDFS_HT40 = 3,
655 REG_EXT_JAPAN_DFS_HT40 = 4
656};
657
658struct ath9k_country_entry {
659 u16 countryCode;
660 u16 regDmnEnum;
661 u16 regDmn5G;
662 u16 regDmn2G;
663 u8 isMultidomain;
664 u8 iso[3];
665};
666
e153789d
S		 667struct eeprom_ops {
668 int (*check_eeprom)(struct ath_hw *hw);
669 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
670 bool (*fill_eeprom)(struct ath_hw *hw);
671 int (*get_eeprom_ver)(struct ath_hw *hw);
672 int (*get_eeprom_rev)(struct ath_hw *hw);
673 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
601e0cb1 674 u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
e153789d 675 struct ath9k_channel *chan);
d6509151 676 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
e153789d 677 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
8fbff4b8 678 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
e153789d
S		 679 u16 cfgCtl, u8 twiceAntennaReduction,
680 u8 twiceMaxRegulatoryPower, u8 powerLimit);
681 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
682};
683
79d7f4bc 684void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
b5aec950
S		 685void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
686 u32 shift, u32 val);
687int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
688 int16_t targetLeft,
689 int16_t targetRight);
690bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
691 u16 *indexL, u16 *indexR);
5bb12791 692bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
b5aec950
S		 693void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
694 u8 *pVpdList, u16 numIntercepts,
695 u8 *pRetVpdList);
696void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
697 struct ath9k_channel *chan,
698 struct cal_target_power_leg *powInfo,
699 u16 numChannels,
700 struct cal_target_power_leg *pNewPower,
701 u16 numRates, bool isExtTarget);
702void ath9k_hw_get_target_powers(struct ath_hw *ah,
703 struct ath9k_channel *chan,
704 struct cal_target_power_ht *powInfo,
705 u16 numChannels,
706 struct cal_target_power_ht *pNewPower,
707 u16 numRates, bool isHt40Target);
708u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
709 bool is2GHz, int num_band_edges);
a55f8588 710void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
b5aec950
S		 711int ath9k_hw_eeprom_init(struct ath_hw *ah);
712
394cf0a1 713#define ar5416_get_ntxchains(_txchainmask) \
f74df6fb 714 (((_txchainmask >> 2) & 1) + \
394cf0a1
S		 715 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
716
b5aec950
S		 717extern const struct eeprom_ops eep_def_ops;
718extern const struct eeprom_ops eep_4k_ops;
0b8f6f2b 719extern const struct eeprom_ops eep_ar9287_ops;
15c9ee7a
SB		 720extern const struct eeprom_ops eep_ar9287_ops;
721extern const struct eeprom_ops eep_ar9300_ops;
394cf0a1
S		 722
723#endif /* EEPROM_H */
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