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Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / eeprom.c
CommitLineData
c6e387a2
NK		 1/*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
8e218fb2
NK		 3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
c6e387a2
NK		 5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20/*************************************\
21* EEPROM access functions and helpers *
22\*************************************/
23
5a0e3ad6
TH		 24#include <linux/slab.h>
25
c6e387a2
NK		 26#include "ath5k.h"
27#include "reg.h"
28#include "debug.h"
29#include "base.h"
30
31/*
32 * Read from eeprom
33 */
34static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
35{
36 u32 status, timeout;
37
c6e387a2
NK		 38 /*
39 * Initialize EEPROM access
40 */
41 if (ah->ah_version == AR5K_AR5210) {
42 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
43 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
44 } else {
45 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
46 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
47 AR5K_EEPROM_CMD_READ);
48 }
49
50 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
51 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
52 if (status & AR5K_EEPROM_STAT_RDDONE) {
53 if (status & AR5K_EEPROM_STAT_RDERR)
54 return -EIO;
55 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
56 0xffff);
57 return 0;
58 }
59 udelay(15);
60 }
61
62 return -ETIMEDOUT;
63}
64
65/*
66 * Translate binary channel representation in EEPROM to frequency
67 */
1048643e
FF		 68static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin,
69 unsigned int mode)
c6e387a2
NK		 70{
71 u16 val;
72
73 if (bin == AR5K_EEPROM_CHANNEL_DIS)
74 return bin;
75
76 if (mode == AR5K_EEPROM_MODE_11A) {
1048643e 77 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
c6e387a2
NK		 78 val = (5 * bin) + 4800;
79 else
80 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
81 (bin * 10) + 5100;
82 } else {
1048643e 83 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2)
c6e387a2
NK		 84 val = bin + 2300;
85 else
86 val = bin + 2400;
87 }
88
89 return val;
90}
91
1048643e
FF		 92/*
93 * Initialize eeprom & capabilities structs
94 */
95static int
96ath5k_eeprom_init_header(struct ath5k_hw *ah)
97{
98 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
99 int ret;
100 u16 val;
359207c6 101 u32 cksum, offset, eep_max = AR5K_EEPROM_INFO_MAX;
1048643e 102
1048643e
FF		 103 /*
104 * Read values from EEPROM and store them in the capability structure
105 */
106 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
107 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
108 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
109 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
110 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
111
112 /* Return if we have an old EEPROM */
113 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
114 return 0;
115
1048643e
FF		 116 /*
117 * Validate the checksum of the EEPROM date. There are some
118 * devices with invalid EEPROMs.
119 */
359207c6
LR		 120 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_UPPER, val);
121 if (val) {
122 eep_max = (val & AR5K_EEPROM_SIZE_UPPER_MASK) <<
123 AR5K_EEPROM_SIZE_ENDLOC_SHIFT;
124 AR5K_EEPROM_READ(AR5K_EEPROM_SIZE_LOWER, val);
125 eep_max = (eep_max | val) - AR5K_EEPROM_INFO_BASE;
126
127 /*
128 * Fail safe check to prevent stupid loops due
129 * to busted EEPROMs. XXX: This value is likely too
130 * big still, waiting on a better value.
131 */
132 if (eep_max > (3 * AR5K_EEPROM_INFO_MAX)) {
133 ATH5K_ERR(ah->ah_sc, "Invalid max custom EEPROM size: "
134 "%d (0x%04x) max expected: %d (0x%04x)\n",
135 eep_max, eep_max,
136 3 * AR5K_EEPROM_INFO_MAX,
137 3 * AR5K_EEPROM_INFO_MAX);
138 return -EIO;
139 }
140 }
141
142 for (cksum = 0, offset = 0; offset < eep_max; offset++) {
1048643e
FF		 143 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
144 cksum ^= val;
145 }
146 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
359207c6
LR		 147 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM "
148 "checksum: 0x%04x eep_max: 0x%04x (%s)\n",
149 cksum, eep_max,
150 eep_max == AR5K_EEPROM_INFO_MAX ?
151 "default size" : "custom size");
1048643e
FF		 152 return -EIO;
153 }
1048643e
FF		 154
155 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
156 ee_ant_gain);
157
158 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
159 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
160 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
0ea9c00c
NK		 161
162 /* XXX: Don't know which versions include these two */
163 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC2, ee_misc2);
164
165 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3)
166 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC3, ee_misc3);
167
168 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) {
169 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC4, ee_misc4);
170 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC5, ee_misc5);
171 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC6, ee_misc6);
172 }
1048643e
FF		 173 }
174
175 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
176 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
177 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
178 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
179
180 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
181 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
182 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
183 }
184
1889ba0a
NK		 185 AR5K_EEPROM_READ(AR5K_EEPROM_IS_HB63, val);
186
187 if ((ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4)) && val)
188 ee->ee_is_hb63 = true;
189 else
190 ee->ee_is_hb63 = false;
191
192 AR5K_EEPROM_READ(AR5K_EEPROM_RFKILL, val);
193 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL);
194 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false;
195
c38e7a93
NK		 196 /* Check if PCIE_OFFSET points to PCIE_SERDES_SECTION
197 * and enable serdes programming if needed.
198 *
199 * XXX: Serdes values seem to be fixed so
200 * no need to read them here, we write them
201 * during ath5k_hw_attach */
202 AR5K_EEPROM_READ(AR5K_EEPROM_PCIE_OFFSET, val);
203 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ?
204 true : false;
205
1048643e
FF		 206 return 0;
207}
208
209
c6e387a2
NK		 210/*
211 * Read antenna infos from eeprom
212 */
213static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
214 unsigned int mode)
215{
216 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
217 u32 o = *offset;
218 u16 val;
219 int ret, i = 0;
220
221 AR5K_EEPROM_READ(o++, val);
222 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1048643e 223 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f;
c6e387a2
NK		 224 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
225
226 AR5K_EEPROM_READ(o++, val);
227 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
228 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
229 ee->ee_ant_control[mode][i++] = val & 0x3f;
230
231 AR5K_EEPROM_READ(o++, val);
232 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
233 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
234 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
235
236 AR5K_EEPROM_READ(o++, val);
237 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
238 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
239 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
240 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
241
242 AR5K_EEPROM_READ(o++, val);
243 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
244 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
245 ee->ee_ant_control[mode][i++] = val & 0x3f;
246
2bed03eb
NK		 247 /* Get antenna switch tables */
248 ah->ah_ant_ctl[mode][AR5K_ANT_CTL] =
e8f055f0 249 (ee->ee_ant_control[mode][0] << 4);
2bed03eb 250 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_A] =
c6e387a2
NK		 251 ee->ee_ant_control[mode][1] |
252 (ee->ee_ant_control[mode][2] << 6) |
253 (ee->ee_ant_control[mode][3] << 12) |
254 (ee->ee_ant_control[mode][4] << 18) |
255 (ee->ee_ant_control[mode][5] << 24);
2bed03eb 256 ah->ah_ant_ctl[mode][AR5K_ANT_SWTABLE_B] =
c6e387a2
NK		 257 ee->ee_ant_control[mode][6] |
258 (ee->ee_ant_control[mode][7] << 6) |
259 (ee->ee_ant_control[mode][8] << 12) |
260 (ee->ee_ant_control[mode][9] << 18) |
261 (ee->ee_ant_control[mode][10] << 24);
262
263 /* return new offset */
264 *offset = o;
265
266 return 0;
267}
268
269/*
0ea9c00c
NK		 270 * Read supported modes and some mode-specific calibration data
271 * from eeprom
c6e387a2
NK		 272 */
273static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
274 unsigned int mode)
275{
276 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
277 u32 o = *offset;
278 u16 val;
279 int ret;
280
1048643e
FF		 281 ee->ee_n_piers[mode] = 0;
282 AR5K_EEPROM_READ(o++, val);
283 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
284 switch(mode) {
285 case AR5K_EEPROM_MODE_11A:
8e218fb2
NK		 286 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
287 ee->ee_db[mode][3] = (val >> 2) & 0x7;
288 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1048643e
FF		 289
290 AR5K_EEPROM_READ(o++, val);
8e218fb2
NK		 291 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
292 ee->ee_db[mode][2] = (val >> 12) & 0x7;
293 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
294 ee->ee_db[mode][1] = (val >> 6) & 0x7;
295 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
296 ee->ee_db[mode][0] = val & 0x7;
1048643e
FF		 297 break;
298 case AR5K_EEPROM_MODE_11G:
299 case AR5K_EEPROM_MODE_11B:
8e218fb2
NK		 300 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
301 ee->ee_db[mode][1] = val & 0x7;
1048643e
FF		 302 break;
303 }
304
c6e387a2
NK		 305 AR5K_EEPROM_READ(o++, val);
306 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
307 ee->ee_thr_62[mode] = val & 0xff;
308
309 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
310 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
311
312 AR5K_EEPROM_READ(o++, val);
313 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
314 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
315
316 AR5K_EEPROM_READ(o++, val);
317 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
318
319 if ((val & 0xff) & 0x80)
320 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
321 else
322 ee->ee_noise_floor_thr[mode] = val & 0xff;
323
324 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
325 ee->ee_noise_floor_thr[mode] =
326 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
327
328 AR5K_EEPROM_READ(o++, val);
329 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
330 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
331 ee->ee_xpd[mode] = val & 0x1;
332
687c8ff1
BR		 333 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
334 mode != AR5K_EEPROM_MODE_11B)
c6e387a2
NK		 335 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
336
337 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
338 AR5K_EEPROM_READ(o++, val);
339 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
340
341 if (mode == AR5K_EEPROM_MODE_11A)
342 ee->ee_xr_power[mode] = val & 0x3f;
343 else {
687c8ff1 344 /* b_DB_11[bg] and b_OB_11[bg] */
c6e387a2
NK		 345 ee->ee_ob[mode][0] = val & 0x7;
346 ee->ee_db[mode][0] = (val >> 3) & 0x7;
347 }
348 }
349
350 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
351 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
352 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
353 } else {
354 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
355
356 AR5K_EEPROM_READ(o++, val);
357 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
358
1048643e 359 if (mode == AR5K_EEPROM_MODE_11G) {
c6e387a2 360 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1048643e
FF		 361 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6)
362 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
363 }
c6e387a2
NK		 364 }
365
366 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
367 mode == AR5K_EEPROM_MODE_11A) {
368 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
369 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
370 }
371
1048643e
FF		 372 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_0)
373 goto done;
374
0ea9c00c
NK		 375 /* Note: >= v5 have bg freq piers on another location
376 * so these freq piers are ignored for >= v5 (should be 0xff
377 * anyway) */
1048643e
FF		 378 switch(mode) {
379 case AR5K_EEPROM_MODE_11A:
380 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_4_1)
381 break;
382
383 AR5K_EEPROM_READ(o++, val);
384 ee->ee_margin_tx_rx[mode] = val & 0x3f;
385 break;
386 case AR5K_EEPROM_MODE_11B:
387 AR5K_EEPROM_READ(o++, val);
388
389 ee->ee_pwr_cal_b[0].freq =
390 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
391 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS)
392 ee->ee_n_piers[mode]++;
393
394 ee->ee_pwr_cal_b[1].freq =
395 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
396 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS)
397 ee->ee_n_piers[mode]++;
398
399 AR5K_EEPROM_READ(o++, val);
400 ee->ee_pwr_cal_b[2].freq =
401 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
402 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS)
403 ee->ee_n_piers[mode]++;
404
405 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
406 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
407 break;
408 case AR5K_EEPROM_MODE_11G:
409 AR5K_EEPROM_READ(o++, val);
410
411 ee->ee_pwr_cal_g[0].freq =
412 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
413 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS)
414 ee->ee_n_piers[mode]++;
415
416 ee->ee_pwr_cal_g[1].freq =
417 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
418 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS)
419 ee->ee_n_piers[mode]++;
420
421 AR5K_EEPROM_READ(o++, val);
422 ee->ee_turbo_max_power[mode] = val & 0x7f;
423 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
424
425 AR5K_EEPROM_READ(o++, val);
426 ee->ee_pwr_cal_g[2].freq =
427 ath5k_eeprom_bin2freq(ee, val & 0xff, mode);
428 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS)
429 ee->ee_n_piers[mode]++;
c6e387a2 430
1048643e
FF		 431 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
432 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
433
434 AR5K_EEPROM_READ(o++, val);
5f13bfac
BR		 435 ee->ee_i_cal[mode] = (val >> 5) & 0x3f;
436 ee->ee_q_cal[mode] = val & 0x1f;
1048643e
FF		 437
438 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
439 AR5K_EEPROM_READ(o++, val);
440 ee->ee_cck_ofdm_gain_delta = val & 0xff;
441 }
442 break;
443 }
444
3b3ee43d
PR		 445 /*
446 * Read turbo mode information on newer EEPROM versions
447 */
1048643e 448 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0)
3b3ee43d 449 goto done;
c6e387a2 450
1048643e
FF		 451 switch (mode){
452 case AR5K_EEPROM_MODE_11A:
453 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f;
c6e387a2 454
1048643e
FF		 455 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7;
456 AR5K_EEPROM_READ(o++, val);
457 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3;
458 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f;
459
460 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f;
461 AR5K_EEPROM_READ(o++, val);
462 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7;
463 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff;
464
465 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >=2)
466 ee->ee_pd_gain_overlap = (val >> 9) & 0xf;
467 break;
468 case AR5K_EEPROM_MODE_11G:
469 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f;
470
471 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7;
472 AR5K_EEPROM_READ(o++, val);
473 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1;
474 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f;
475
476 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f;
477 AR5K_EEPROM_READ(o++, val);
478 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5;
479 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff;
480 break;
481 }
482
3b3ee43d 483done:
1048643e
FF		 484 /* return new offset */
485 *offset = o;
486
487 return 0;
488}
489
0ea9c00c 490/* Read mode-specific data (except power calibration data) */
1048643e
FF		 491static int
492ath5k_eeprom_init_modes(struct ath5k_hw *ah)
493{
494 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
495 u32 mode_offset[3];
496 unsigned int mode;
497 u32 offset;
498 int ret;
c6e387a2 499
c6e387a2 500 /*
1048643e 501 * Get values for all modes
c6e387a2 502 */
1048643e
FF		 503 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
504 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
505 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
506
507 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] =
508 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
509
510 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++) {
511 offset = mode_offset[mode];
512
513 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
514 if (ret)
515 return ret;
516
517 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
518 if (ret)
519 return ret;
c6e387a2 520 }
1048643e
FF		 521
522 /* override for older eeprom versions for better performance */
523 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2) {
524 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15;
525 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28;
526 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28;
c6e387a2 527 }
c6e387a2 528
1048643e
FF		 529 return 0;
530}
c6e387a2 531
0ea9c00c
NK		 532/* Read the frequency piers for each mode (mostly used on newer eeproms with 0xff
533 * frequency mask) */
1048643e
FF		 534static inline int
535ath5k_eeprom_read_freq_list(struct ath5k_hw *ah, int *offset, int max,
0ea9c00c 536 struct ath5k_chan_pcal_info *pc, unsigned int mode)
1048643e 537{
0ea9c00c 538 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1048643e
FF		 539 int o = *offset;
540 int i = 0;
0ea9c00c 541 u8 freq1, freq2;
1048643e
FF		 542 int ret;
543 u16 val;
544
8e218fb2 545 ee->ee_n_piers[mode] = 0;
1048643e
FF		 546 while(i < max) {
547 AR5K_EEPROM_READ(o++, val);
548
8e218fb2
NK		 549 freq1 = val & 0xff;
550 if (!freq1)
551 break;
1048643e 552
8e218fb2
NK		 553 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
554 freq1, mode);
555 ee->ee_n_piers[mode]++;
1048643e 556
8e218fb2
NK		 557 freq2 = (val >> 8) & 0xff;
558 if (!freq2)
1048643e 559 break;
8e218fb2
NK		 560
561 pc[i++].freq = ath5k_eeprom_bin2freq(ee,
562 freq2, mode);
563 ee->ee_n_piers[mode]++;
c6e387a2 564 }
0ea9c00c
NK		 565
566 /* return new offset */
1048643e 567 *offset = o;
c6e387a2 568
1048643e
FF		 569 return 0;
570}
571
0ea9c00c 572/* Read frequency piers for 802.11a */
1048643e
FF		 573static int
574ath5k_eeprom_init_11a_pcal_freq(struct ath5k_hw *ah, int offset)
575{
576 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
577 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a;
578 int i, ret;
579 u16 val;
580 u8 mask;
581
582 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
583 ath5k_eeprom_read_freq_list(ah, &offset,
584 AR5K_EEPROM_N_5GHZ_CHAN, pcal,
0ea9c00c 585 AR5K_EEPROM_MODE_11A);
1048643e
FF		 586 } else {
587 mask = AR5K_EEPROM_FREQ_M(ah->ah_ee_version);
c6e387a2 588
c6e387a2 589 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 590 pcal[0].freq = (val >> 9) & mask;
591 pcal[1].freq = (val >> 2) & mask;
592 pcal[2].freq = (val << 5) & mask;
593
594 AR5K_EEPROM_READ(offset++, val);
595 pcal[2].freq |= (val >> 11) & 0x1f;
596 pcal[3].freq = (val >> 4) & mask;
597 pcal[4].freq = (val << 3) & mask;
598
599 AR5K_EEPROM_READ(offset++, val);
600 pcal[4].freq |= (val >> 13) & 0x7;
601 pcal[5].freq = (val >> 6) & mask;
602 pcal[6].freq = (val << 1) & mask;
603
604 AR5K_EEPROM_READ(offset++, val);
605 pcal[6].freq |= (val >> 15) & 0x1;
606 pcal[7].freq = (val >> 8) & mask;
607 pcal[8].freq = (val >> 1) & mask;
608 pcal[9].freq = (val << 6) & mask;
609
610 AR5K_EEPROM_READ(offset++, val);
611 pcal[9].freq |= (val >> 10) & 0x3f;
0ea9c00c
NK		 612
613 /* Fixed number of piers */
1048643e 614 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10;
c6e387a2 615
0ea9c00c
NK		 616 for (i = 0; i < AR5K_EEPROM_N_5GHZ_CHAN; i++) {
617 pcal[i].freq = ath5k_eeprom_bin2freq(ee,
1048643e 618 pcal[i].freq, AR5K_EEPROM_MODE_11A);
0ea9c00c 619 }
1048643e 620 }
c6e387a2 621
1048643e
FF		 622 return 0;
623}
c6e387a2 624
0ea9c00c 625/* Read frequency piers for 802.11bg on eeprom versions >= 5 and eemap >= 2 */
1048643e
FF		 626static inline int
627ath5k_eeprom_init_11bg_2413(struct ath5k_hw *ah, unsigned int mode, int offset)
628{
629 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
630 struct ath5k_chan_pcal_info *pcal;
1048643e
FF		 631
632 switch(mode) {
633 case AR5K_EEPROM_MODE_11B:
634 pcal = ee->ee_pwr_cal_b;
635 break;
636 case AR5K_EEPROM_MODE_11G:
637 pcal = ee->ee_pwr_cal_g;
638 break;
639 default:
640 return -EINVAL;
641 }
c6e387a2 642
1048643e
FF		 643 ath5k_eeprom_read_freq_list(ah, &offset,
644 AR5K_EEPROM_N_2GHZ_CHAN_2413, pcal,
0ea9c00c 645 mode);
c6e387a2 646
1048643e
FF		 647 return 0;
648}
c6e387a2 649
8e218fb2
NK		 650/*
651 * Read power calibration for RF5111 chips
652 *
0ea9c00c 653 * For RF5111 we have an XPD -eXternal Power Detector- curve
8e218fb2
NK		 654 * for each calibrated channel. Each curve has 0,5dB Power steps
655 * on x axis and PCDAC steps (offsets) on y axis and looks like an
656 * exponential function. To recreate the curve we read 11 points
657 * here and interpolate later.
0ea9c00c 658 */
8e218fb2
NK		 659
660/* Used to match PCDAC steps with power values on RF5111 chips
661 * (eeprom versions < 4). For RF5111 we have 11 pre-defined PCDAC
662 * steps that match with the power values we read from eeprom. On
663 * older eeprom versions (< 3.2) these steps are equaly spaced at
664 * 10% of the pcdac curve -until the curve reaches it's maximum-
665 * (11 steps from 0 to 100%) but on newer eeprom versions (>= 3.2)
666 * these 11 steps are spaced in a different way. This function returns
667 * the pcdac steps based on eeprom version and curve min/max so that we
668 * can have pcdac/pwr points.
669 */
670static inline void
671ath5k_get_pcdac_intercepts(struct ath5k_hw *ah, u8 min, u8 max, u8 *vp)
672{
bbb33881 673 static const u16 intercepts3[] =
8e218fb2 674 { 0, 5, 10, 20, 30, 50, 70, 85, 90, 95, 100 };
bbb33881 675 static const u16 intercepts3_2[] =
8e218fb2
NK		 676 { 0, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100 };
677 const u16 *ip;
678 int i;
679
680 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_2)
681 ip = intercepts3_2;
682 else
683 ip = intercepts3;
684
685 for (i = 0; i < ARRAY_SIZE(intercepts3); i++)
686 vp[i] = (ip[i] * max + (100 - ip[i]) * min) / 100;
687}
688
689/* Convert RF5111 specific data to generic raw data
690 * used by interpolation code */
691static int
692ath5k_eeprom_convert_pcal_info_5111(struct ath5k_hw *ah, int mode,
693 struct ath5k_chan_pcal_info *chinfo)
694{
695 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
696 struct ath5k_chan_pcal_info_rf5111 *pcinfo;
697 struct ath5k_pdgain_info *pd;
698 u8 pier, point, idx;
699 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
700
701 /* Fill raw data for each calibration pier */
702 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
703
704 pcinfo = &chinfo[pier].rf5111_info;
705
706 /* Allocate pd_curves for this cal pier */
707 chinfo[pier].pd_curves =
708 kcalloc(AR5K_EEPROM_N_PD_CURVES,
709 sizeof(struct ath5k_pdgain_info),
710 GFP_KERNEL);
711
712 if (!chinfo[pier].pd_curves)
713 return -ENOMEM;
714
715 /* Only one curve for RF5111
716 * find out which one and place
77c2061d 717 * in pd_curves.
8e218fb2
NK		 718 * Note: ee_x_gain is reversed here */
719 for (idx = 0; idx < AR5K_EEPROM_N_PD_CURVES; idx++) {
720
721 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) {
722 pdgain_idx[0] = idx;
723 break;
724 }
725 }
726
727 ee->ee_pd_gains[mode] = 1;
728
729 pd = &chinfo[pier].pd_curves[idx];
730
731 pd->pd_points = AR5K_EEPROM_N_PWR_POINTS_5111;
732
733 /* Allocate pd points for this curve */
734 pd->pd_step = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
735 sizeof(u8), GFP_KERNEL);
736 if (!pd->pd_step)
737 return -ENOMEM;
738
739 pd->pd_pwr = kcalloc(AR5K_EEPROM_N_PWR_POINTS_5111,
740 sizeof(s16), GFP_KERNEL);
741 if (!pd->pd_pwr)
742 return -ENOMEM;
743
744 /* Fill raw dataset
745 * (convert power to 0.25dB units
746 * for RF5112 combatibility) */
747 for (point = 0; point < pd->pd_points; point++) {
748
749 /* Absolute values */
750 pd->pd_pwr[point] = 2 * pcinfo->pwr[point];
751
752 /* Already sorted */
753 pd->pd_step[point] = pcinfo->pcdac[point];
754 }
755
756 /* Set min/max pwr */
757 chinfo[pier].min_pwr = pd->pd_pwr[0];
758 chinfo[pier].max_pwr = pd->pd_pwr[10];
759
760 }
761
762 return 0;
763}
764
765/* Parse EEPROM data */
1048643e
FF		 766static int
767ath5k_eeprom_read_pcal_info_5111(struct ath5k_hw *ah, int mode)
768{
769 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
770 struct ath5k_chan_pcal_info *pcal;
771 int offset, ret;
eaee7cc2 772 int i;
1048643e
FF		 773 u16 val;
774
775 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
776 switch(mode) {
777 case AR5K_EEPROM_MODE_11A:
778 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
779 return 0;
780
781 ret = ath5k_eeprom_init_11a_pcal_freq(ah,
782 offset + AR5K_EEPROM_GROUP1_OFFSET);
783 if (ret < 0)
784 return ret;
785
786 offset += AR5K_EEPROM_GROUP2_OFFSET;
787 pcal = ee->ee_pwr_cal_a;
788 break;
789 case AR5K_EEPROM_MODE_11B:
790 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) &&
791 !AR5K_EEPROM_HDR_11G(ee->ee_header))
792 return 0;
793
794 pcal = ee->ee_pwr_cal_b;
795 offset += AR5K_EEPROM_GROUP3_OFFSET;
796
797 /* fixed piers */
798 pcal[0].freq = 2412;
799 pcal[1].freq = 2447;
800 pcal[2].freq = 2484;
801 ee->ee_n_piers[mode] = 3;
802 break;
803 case AR5K_EEPROM_MODE_11G:
804 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
805 return 0;
806
807 pcal = ee->ee_pwr_cal_g;
808 offset += AR5K_EEPROM_GROUP4_OFFSET;
809
810 /* fixed piers */
811 pcal[0].freq = 2312;
812 pcal[1].freq = 2412;
813 pcal[2].freq = 2484;
814 ee->ee_n_piers[mode] = 3;
815 break;
816 default:
817 return -EINVAL;
c6e387a2
NK		 818 }
819
1048643e
FF		 820 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
821 struct ath5k_chan_pcal_info_rf5111 *cdata =
822 &pcal[i].rf5111_info;
c6e387a2 823
1048643e
FF		 824 AR5K_EEPROM_READ(offset++, val);
825 cdata->pcdac_max = ((val >> 10) & AR5K_EEPROM_PCDAC_M);
826 cdata->pcdac_min = ((val >> 4) & AR5K_EEPROM_PCDAC_M);
827 cdata->pwr[0] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2 828
1048643e
FF		 829 AR5K_EEPROM_READ(offset++, val);
830 cdata->pwr[0] |= ((val >> 14) & 0x3);
831 cdata->pwr[1] = ((val >> 8) & AR5K_EEPROM_POWER_M);
832 cdata->pwr[2] = ((val >> 2) & AR5K_EEPROM_POWER_M);
833 cdata->pwr[3] = ((val << 4) & AR5K_EEPROM_POWER_M);
c6e387a2 834
1048643e
FF		 835 AR5K_EEPROM_READ(offset++, val);
836 cdata->pwr[3] |= ((val >> 12) & 0xf);
837 cdata->pwr[4] = ((val >> 6) & AR5K_EEPROM_POWER_M);
838 cdata->pwr[5] = (val & AR5K_EEPROM_POWER_M);
c6e387a2 839
c6e387a2 840 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 841 cdata->pwr[6] = ((val >> 10) & AR5K_EEPROM_POWER_M);
842 cdata->pwr[7] = ((val >> 4) & AR5K_EEPROM_POWER_M);
843 cdata->pwr[8] = ((val << 2) & AR5K_EEPROM_POWER_M);
c6e387a2
NK		 844
845 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 846 cdata->pwr[8] |= ((val >> 14) & 0x3);
847 cdata->pwr[9] = ((val >> 8) & AR5K_EEPROM_POWER_M);
848 cdata->pwr[10] = ((val >> 2) & AR5K_EEPROM_POWER_M);
849
850 ath5k_get_pcdac_intercepts(ah, cdata->pcdac_min,
851 cdata->pcdac_max, cdata->pcdac);
c6e387a2
NK		 852 }
853
8e218fb2 854 return ath5k_eeprom_convert_pcal_info_5111(ah, mode, pcal);
1048643e 855}
c6e387a2 856
8e218fb2
NK		 857
858/*
859 * Read power calibration for RF5112 chips
860 *
0ea9c00c
NK		 861 * For RF5112 we have 4 XPD -eXternal Power Detector- curves
862 * for each calibrated channel on 0, -6, -12 and -18dbm but we only
8e218fb2
NK		 863 * use the higher (3) and the lower (0) curves. Each curve has 0.5dB
864 * power steps on x axis and PCDAC steps on y axis and looks like a
865 * linear function. To recreate the curve and pass the power values
866 * on hw, we read 4 points for xpd 0 (lower gain -> max power)
867 * and 3 points for xpd 3 (higher gain -> lower power) here and
868 * interpolate later.
0ea9c00c
NK		 869 *
870 * Note: Many vendors just use xpd 0 so xpd 3 is zeroed.
871 */
8e218fb2
NK		 872
873/* Convert RF5112 specific data to generic raw data
874 * used by interpolation code */
875static int
876ath5k_eeprom_convert_pcal_info_5112(struct ath5k_hw *ah, int mode,
877 struct ath5k_chan_pcal_info *chinfo)
878{
879 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
880 struct ath5k_chan_pcal_info_rf5112 *pcinfo;
881 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
882 unsigned int pier, pdg, point;
883
884 /* Fill raw data for each calibration pier */
885 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
886
887 pcinfo = &chinfo[pier].rf5112_info;
888
889 /* Allocate pd_curves for this cal pier */
890 chinfo[pier].pd_curves =
891 kcalloc(AR5K_EEPROM_N_PD_CURVES,
892 sizeof(struct ath5k_pdgain_info),
893 GFP_KERNEL);
894
895 if (!chinfo[pier].pd_curves)
896 return -ENOMEM;
897
898 /* Fill pd_curves */
899 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
900
901 u8 idx = pdgain_idx[pdg];
902 struct ath5k_pdgain_info *pd =
903 &chinfo[pier].pd_curves[idx];
904
905 /* Lowest gain curve (max power) */
906 if (pdg == 0) {
907 /* One more point for better accuracy */
908 pd->pd_points = AR5K_EEPROM_N_XPD0_POINTS;
909
910 /* Allocate pd points for this curve */
911 pd->pd_step = kcalloc(pd->pd_points,
912 sizeof(u8), GFP_KERNEL);
913
914 if (!pd->pd_step)
915 return -ENOMEM;
916
917 pd->pd_pwr = kcalloc(pd->pd_points,
918 sizeof(s16), GFP_KERNEL);
919
920 if (!pd->pd_pwr)
921 return -ENOMEM;
922
923
924 /* Fill raw dataset
925 * (all power levels are in 0.25dB units) */
926 pd->pd_step[0] = pcinfo->pcdac_x0[0];
927 pd->pd_pwr[0] = pcinfo->pwr_x0[0];
928
929 for (point = 1; point < pd->pd_points;
930 point++) {
931 /* Absolute values */
932 pd->pd_pwr[point] =
933 pcinfo->pwr_x0[point];
934
935 /* Deltas */
936 pd->pd_step[point] =
937 pd->pd_step[point - 1] +
938 pcinfo->pcdac_x0[point];
939 }
940
941 /* Set min power for this frequency */
942 chinfo[pier].min_pwr = pd->pd_pwr[0];
943
944 /* Highest gain curve (min power) */
945 } else if (pdg == 1) {
946
947 pd->pd_points = AR5K_EEPROM_N_XPD3_POINTS;
948
949 /* Allocate pd points for this curve */
950 pd->pd_step = kcalloc(pd->pd_points,
951 sizeof(u8), GFP_KERNEL);
952
953 if (!pd->pd_step)
954 return -ENOMEM;
955
956 pd->pd_pwr = kcalloc(pd->pd_points,
957 sizeof(s16), GFP_KERNEL);
958
959 if (!pd->pd_pwr)
960 return -ENOMEM;
961
962 /* Fill raw dataset
963 * (all power levels are in 0.25dB units) */
964 for (point = 0; point < pd->pd_points;
965 point++) {
966 /* Absolute values */
967 pd->pd_pwr[point] =
968 pcinfo->pwr_x3[point];
969
970 /* Fixed points */
971 pd->pd_step[point] =
972 pcinfo->pcdac_x3[point];
973 }
974
975 /* Since we have a higher gain curve
976 * override min power */
977 chinfo[pier].min_pwr = pd->pd_pwr[0];
978 }
979 }
980 }
981
982 return 0;
983}
984
985/* Parse EEPROM data */
1048643e
FF		 986static int
987ath5k_eeprom_read_pcal_info_5112(struct ath5k_hw *ah, int mode)
988{
989 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
990 struct ath5k_chan_pcal_info_rf5112 *chan_pcal_info;
991 struct ath5k_chan_pcal_info *gen_chan_info;
8e218fb2 992 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 993 u32 offset;
8e218fb2 994 u8 i, c;
1048643e
FF		 995 u16 val;
996 int ret;
8e218fb2
NK		 997 u8 pd_gains = 0;
998
999 /* Count how many curves we have and
1000 * identify them (which one of the 4
1001 * available curves we have on each count).
1002 * Curves are stored from lower (x0) to
1003 * higher (x3) gain */
1004 for (i = 0; i < AR5K_EEPROM_N_PD_CURVES; i++) {
1005 /* ee_x_gain[mode] is x gain mask */
1006 if ((ee->ee_x_gain[mode] >> i) & 0x1)
1007 pdgain_idx[pd_gains++] = i;
1008 }
1009 ee->ee_pd_gains[mode] = pd_gains;
1010
1011 if (pd_gains == 0 || pd_gains > 2)
1012 return -EINVAL;
c6e387a2 1013
1048643e
FF		 1014 switch (mode) {
1015 case AR5K_EEPROM_MODE_11A:
1016 /*
1017 * Read 5GHz EEPROM channels
1018 */
1019 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1020 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1021
1022 offset += AR5K_EEPROM_GROUP2_OFFSET;
1023 gen_chan_info = ee->ee_pwr_cal_a;
1024 break;
1025 case AR5K_EEPROM_MODE_11B:
1026 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1027 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1028 offset += AR5K_EEPROM_GROUP3_OFFSET;
1029
1030 /* NB: frequency piers parsed during mode init */
1031 gen_chan_info = ee->ee_pwr_cal_b;
1032 break;
1033 case AR5K_EEPROM_MODE_11G:
1034 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version);
1035 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
1036 offset += AR5K_EEPROM_GROUP4_OFFSET;
1037 else if (AR5K_EEPROM_HDR_11B(ee->ee_header))
1038 offset += AR5K_EEPROM_GROUP2_OFFSET;
1039
1040 /* NB: frequency piers parsed during mode init */
1041 gen_chan_info = ee->ee_pwr_cal_g;
1042 break;
1043 default:
1044 return -EINVAL;
1045 }
c6e387a2 1046
1048643e
FF		 1047 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
1048 chan_pcal_info = &gen_chan_info[i].rf5112_info;
c6e387a2 1049
8e218fb2 1050 /* Power values in quarter dB
1048643e
FF		 1051 * for the lower xpd gain curve
1052 * (0 dBm -> higher output power) */
1053 for (c = 0; c < AR5K_EEPROM_N_XPD0_POINTS; c++) {
1054 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1055 chan_pcal_info->pwr_x0[c] = (s8) (val & 0xff);
1056 chan_pcal_info->pwr_x0[++c] = (s8) ((val >> 8) & 0xff);
1048643e 1057 }
c6e387a2 1058
1048643e
FF		 1059 /* PCDAC steps
1060 * corresponding to the above power
1061 * measurements */
c6e387a2 1062 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1063 chan_pcal_info->pcdac_x0[1] = (val & 0x1f);
1064 chan_pcal_info->pcdac_x0[2] = ((val >> 5) & 0x1f);
1065 chan_pcal_info->pcdac_x0[3] = ((val >> 10) & 0x1f);
c6e387a2 1066
8e218fb2 1067 /* Power values in quarter dB
1048643e
FF		 1068 * for the higher xpd gain curve
1069 * (18 dBm -> lower output power) */
c6e387a2 1070 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1071 chan_pcal_info->pwr_x3[0] = (s8) (val & 0xff);
1072 chan_pcal_info->pwr_x3[1] = (s8) ((val >> 8) & 0xff);
c6e387a2
NK		 1073
1074 AR5K_EEPROM_READ(offset++, val);
1048643e
FF		 1075 chan_pcal_info->pwr_x3[2] = (val & 0xff);
1076
1077 /* PCDAC steps
1078 * corresponding to the above power
0ea9c00c 1079 * measurements (fixed) */
1048643e
FF		 1080 chan_pcal_info->pcdac_x3[0] = 20;
1081 chan_pcal_info->pcdac_x3[1] = 35;
1082 chan_pcal_info->pcdac_x3[2] = 63;
1083
1084 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) {
8e218fb2 1085 chan_pcal_info->pcdac_x0[0] = ((val >> 8) & 0x3f);
1048643e
FF		 1086
1087 /* Last xpd0 power level is also channel maximum */
1088 gen_chan_info[i].max_pwr = chan_pcal_info->pwr_x0[3];
1089 } else {
1090 chan_pcal_info->pcdac_x0[0] = 1;
8e218fb2 1091 gen_chan_info[i].max_pwr = (s8) ((val >> 8) & 0xff);
1048643e 1092 }
c6e387a2 1093
1048643e
FF		 1094 }
1095
8e218fb2 1096 return ath5k_eeprom_convert_pcal_info_5112(ah, mode, gen_chan_info);
1048643e
FF		 1097}
1098
8e218fb2
NK		 1099
1100/*
1101 * Read power calibration for RF2413 chips
1102 *
1103 * For RF2413 we have a Power to PDDAC table (Power Detector)
1104 * instead of a PCDAC and 4 pd gain curves for each calibrated channel.
1105 * Each curve has power on x axis in 0.5 db steps and PDDADC steps on y
1106 * axis and looks like an exponential function like the RF5111 curve.
1107 *
1108 * To recreate the curves we read here the points and interpolate
1109 * later. Note that in most cases only 2 (higher and lower) curves are
1110 * used (like RF5112) but vendors have the oportunity to include all
1111 * 4 curves on eeprom. The final curve (higher power) has an extra
1112 * point for better accuracy like RF5112.
1113 */
1114
0ea9c00c
NK		 1115/* For RF2413 power calibration data doesn't start on a fixed location and
1116 * if a mode is not supported, it's section is missing -not zeroed-.
1117 * So we need to calculate the starting offset for each section by using
1118 * these two functions */
1119
1120/* Return the size of each section based on the mode and the number of pd
1121 * gains available (maximum 4). */
1048643e
FF		 1122static inline unsigned int
1123ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode)
1124{
1125 static const unsigned int pdgains_size[] = { 4, 6, 9, 12 };
1126 unsigned int sz;
1127
1128 sz = pdgains_size[ee->ee_pd_gains[mode] - 1];
1129 sz *= ee->ee_n_piers[mode];
1130
1131 return sz;
1132}
1133
0ea9c00c
NK		 1134/* Return the starting offset for a section based on the modes supported
1135 * and each section's size. */
1048643e
FF		 1136static unsigned int
1137ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode)
1138{
1139 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4);
1140
1141 switch(mode) {
1142 case AR5K_EEPROM_MODE_11G:
1143 if (AR5K_EEPROM_HDR_11B(ee->ee_header))
8e218fb2
NK		 1144 offset += ath5k_pdgains_size_2413(ee,
1145 AR5K_EEPROM_MODE_11B) +
1146 AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
1048643e
FF		 1147 /* fall through */
1148 case AR5K_EEPROM_MODE_11B:
1149 if (AR5K_EEPROM_HDR_11A(ee->ee_header))
8e218fb2
NK		 1150 offset += ath5k_pdgains_size_2413(ee,
1151 AR5K_EEPROM_MODE_11A) +
1152 AR5K_EEPROM_N_5GHZ_CHAN / 2;
1048643e
FF		 1153 /* fall through */
1154 case AR5K_EEPROM_MODE_11A:
1155 break;
1156 default:
1157 break;
1158 }
1159
1160 return offset;
1161}
1162
8e218fb2
NK		 1163/* Convert RF2413 specific data to generic raw data
1164 * used by interpolation code */
1165static int
1166ath5k_eeprom_convert_pcal_info_2413(struct ath5k_hw *ah, int mode,
1167 struct ath5k_chan_pcal_info *chinfo)
1168{
1169 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1170 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1171 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1172 unsigned int pier, pdg, point;
1173
1174 /* Fill raw data for each calibration pier */
1175 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1176
1177 pcinfo = &chinfo[pier].rf2413_info;
1178
1179 /* Allocate pd_curves for this cal pier */
1180 chinfo[pier].pd_curves =
1181 kcalloc(AR5K_EEPROM_N_PD_CURVES,
1182 sizeof(struct ath5k_pdgain_info),
1183 GFP_KERNEL);
1184
1185 if (!chinfo[pier].pd_curves)
1186 return -ENOMEM;
1187
1188 /* Fill pd_curves */
1189 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1190
1191 u8 idx = pdgain_idx[pdg];
1192 struct ath5k_pdgain_info *pd =
1193 &chinfo[pier].pd_curves[idx];
1194
1195 /* One more point for the highest power
1196 * curve (lowest gain) */
1197 if (pdg == ee->ee_pd_gains[mode] - 1)
1198 pd->pd_points = AR5K_EEPROM_N_PD_POINTS;
1199 else
1200 pd->pd_points = AR5K_EEPROM_N_PD_POINTS - 1;
1201
1202 /* Allocate pd points for this curve */
1203 pd->pd_step = kcalloc(pd->pd_points,
1204 sizeof(u8), GFP_KERNEL);
1205
1206 if (!pd->pd_step)
1207 return -ENOMEM;
1208
1209 pd->pd_pwr = kcalloc(pd->pd_points,
1210 sizeof(s16), GFP_KERNEL);
1211
1212 if (!pd->pd_pwr)
1213 return -ENOMEM;
1214
1215 /* Fill raw dataset
1216 * convert all pwr levels to
1217 * quarter dB for RF5112 combatibility */
1218 pd->pd_step[0] = pcinfo->pddac_i[pdg];
1219 pd->pd_pwr[0] = 4 * pcinfo->pwr_i[pdg];
1220
1221 for (point = 1; point < pd->pd_points; point++) {
1222
1223 pd->pd_pwr[point] = pd->pd_pwr[point - 1] +
1224 2 * pcinfo->pwr[pdg][point - 1];
1225
1226 pd->pd_step[point] = pd->pd_step[point - 1] +
1227 pcinfo->pddac[pdg][point - 1];
1228
1229 }
1230
1231 /* Highest gain curve -> min power */
1232 if (pdg == 0)
1233 chinfo[pier].min_pwr = pd->pd_pwr[0];
1234
1235 /* Lowest gain curve -> max power */
1236 if (pdg == ee->ee_pd_gains[mode] - 1)
1237 chinfo[pier].max_pwr =
1238 pd->pd_pwr[pd->pd_points - 1];
1239 }
1240 }
1241
1242 return 0;
1243}
1244
1245/* Parse EEPROM data */
1048643e
FF		 1246static int
1247ath5k_eeprom_read_pcal_info_2413(struct ath5k_hw *ah, int mode)
1248{
1249 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
8e218fb2
NK		 1250 struct ath5k_chan_pcal_info_rf2413 *pcinfo;
1251 struct ath5k_chan_pcal_info *chinfo;
1252 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode];
1048643e 1253 u32 offset;
8e218fb2 1254 int idx, i, ret;
1048643e
FF		 1255 u16 val;
1256 u8 pd_gains = 0;
1257
8e218fb2
NK		 1258 /* Count how many curves we have and
1259 * identify them (which one of the 4
1260 * available curves we have on each count).
1261 * Curves are stored from higher to
1262 * lower gain so we go backwards */
1263 for (idx = AR5K_EEPROM_N_PD_CURVES - 1; idx >= 0; idx--) {
1264 /* ee_x_gain[mode] is x gain mask */
1265 if ((ee->ee_x_gain[mode] >> idx) & 0x1)
1266 pdgain_idx[pd_gains++] = idx;
1267
1268 }
1048643e
FF		 1269 ee->ee_pd_gains[mode] = pd_gains;
1270
8e218fb2
NK		 1271 if (pd_gains == 0)
1272 return -EINVAL;
1273
1048643e
FF		 1274 offset = ath5k_cal_data_offset_2413(ee, mode);
1275 switch (mode) {
1276 case AR5K_EEPROM_MODE_11A:
1277 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1278 return 0;
1279
1280 ath5k_eeprom_init_11a_pcal_freq(ah, offset);
1281 offset += AR5K_EEPROM_N_5GHZ_CHAN / 2;
8e218fb2 1282 chinfo = ee->ee_pwr_cal_a;
1048643e
FF		 1283 break;
1284 case AR5K_EEPROM_MODE_11B:
1285 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1286 return 0;
c6e387a2 1287
1048643e
FF		 1288 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1289 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1290 chinfo = ee->ee_pwr_cal_b;
1048643e
FF		 1291 break;
1292 case AR5K_EEPROM_MODE_11G:
1293 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1294 return 0;
1295
1296 ath5k_eeprom_init_11bg_2413(ah, mode, offset);
1297 offset += AR5K_EEPROM_N_2GHZ_CHAN_2413 / 2;
8e218fb2 1298 chinfo = ee->ee_pwr_cal_g;
1048643e
FF		 1299 break;
1300 default:
1301 return -EINVAL;
1302 }
1303
1048643e 1304 for (i = 0; i < ee->ee_n_piers[mode]; i++) {
8e218fb2 1305 pcinfo = &chinfo[i].rf2413_info;
1048643e
FF		 1306
1307 /*
1308 * Read pwr_i, pddac_i and the first
1309 * 2 pd points (pwr, pddac)
1310 */
c6e387a2 1311 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1312 pcinfo->pwr_i[0] = val & 0x1f;
1313 pcinfo->pddac_i[0] = (val >> 5) & 0x7f;
1314 pcinfo->pwr[0][0] = (val >> 12) & 0xf;
c6e387a2 1315
1048643e 1316 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1317 pcinfo->pddac[0][0] = val & 0x3f;
1318 pcinfo->pwr[0][1] = (val >> 6) & 0xf;
1319 pcinfo->pddac[0][1] = (val >> 10) & 0x3f;
1048643e
FF		 1320
1321 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1322 pcinfo->pwr[0][2] = val & 0xf;
1323 pcinfo->pddac[0][2] = (val >> 4) & 0x3f;
1048643e 1324
8e218fb2
NK		 1325 pcinfo->pwr[0][3] = 0;
1326 pcinfo->pddac[0][3] = 0;
1048643e
FF		 1327
1328 if (pd_gains > 1) {
1329 /*
1330 * Pd gain 0 is not the last pd gain
1331 * so it only has 2 pd points.
1332 * Continue wih pd gain 1.
1333 */
8e218fb2 1334 pcinfo->pwr_i[1] = (val >> 10) & 0x1f;
1048643e 1335
8e218fb2 1336 pcinfo->pddac_i[1] = (val >> 15) & 0x1;
c6e387a2 1337 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1338 pcinfo->pddac_i[1] |= (val & 0x3F) << 1;
1048643e 1339
8e218fb2
NK		 1340 pcinfo->pwr[1][0] = (val >> 6) & 0xf;
1341 pcinfo->pddac[1][0] = (val >> 10) & 0x3f;
1048643e
FF		 1342
1343 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1344 pcinfo->pwr[1][1] = val & 0xf;
1345 pcinfo->pddac[1][1] = (val >> 4) & 0x3f;
1346 pcinfo->pwr[1][2] = (val >> 10) & 0xf;
1347
1348 pcinfo->pddac[1][2] = (val >> 14) & 0x3;
1048643e 1349 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1350 pcinfo->pddac[1][2] |= (val & 0xF) << 2;
1048643e 1351
8e218fb2
NK		 1352 pcinfo->pwr[1][3] = 0;
1353 pcinfo->pddac[1][3] = 0;
1048643e
FF		 1354 } else if (pd_gains == 1) {
1355 /*
1356 * Pd gain 0 is the last one so
1357 * read the extra point.
1358 */
8e218fb2 1359 pcinfo->pwr[0][3] = (val >> 10) & 0xf;
1048643e 1360
8e218fb2 1361 pcinfo->pddac[0][3] = (val >> 14) & 0x3;
1048643e 1362 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1363 pcinfo->pddac[0][3] |= (val & 0xF) << 2;
1048643e
FF		 1364 }
1365
1366 /*
1367 * Proceed with the other pd_gains
1368 * as above.
1369 */
1370 if (pd_gains > 2) {
8e218fb2
NK		 1371 pcinfo->pwr_i[2] = (val >> 4) & 0x1f;
1372 pcinfo->pddac_i[2] = (val >> 9) & 0x7f;
1048643e
FF		 1373
1374 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1375 pcinfo->pwr[2][0] = (val >> 0) & 0xf;
1376 pcinfo->pddac[2][0] = (val >> 4) & 0x3f;
1377 pcinfo->pwr[2][1] = (val >> 10) & 0xf;
1378
1379 pcinfo->pddac[2][1] = (val >> 14) & 0x3;
1048643e 1380 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1381 pcinfo->pddac[2][1] |= (val & 0xF) << 2;
1048643e 1382
8e218fb2
NK		 1383 pcinfo->pwr[2][2] = (val >> 4) & 0xf;
1384 pcinfo->pddac[2][2] = (val >> 8) & 0x3f;
1048643e 1385
8e218fb2
NK		 1386 pcinfo->pwr[2][3] = 0;
1387 pcinfo->pddac[2][3] = 0;
1048643e 1388 } else if (pd_gains == 2) {
8e218fb2
NK		 1389 pcinfo->pwr[1][3] = (val >> 4) & 0xf;
1390 pcinfo->pddac[1][3] = (val >> 8) & 0x3f;
1048643e
FF		 1391 }
1392
1393 if (pd_gains > 3) {
8e218fb2 1394 pcinfo->pwr_i[3] = (val >> 14) & 0x3;
1048643e 1395 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1396 pcinfo->pwr_i[3] |= ((val >> 0) & 0x7) << 2;
1048643e 1397
8e218fb2
NK		 1398 pcinfo->pddac_i[3] = (val >> 3) & 0x7f;
1399 pcinfo->pwr[3][0] = (val >> 10) & 0xf;
1400 pcinfo->pddac[3][0] = (val >> 14) & 0x3;
1048643e
FF		 1401
1402 AR5K_EEPROM_READ(offset++, val);
8e218fb2
NK		 1403 pcinfo->pddac[3][0] |= (val & 0xF) << 2;
1404 pcinfo->pwr[3][1] = (val >> 4) & 0xf;
1405 pcinfo->pddac[3][1] = (val >> 8) & 0x3f;
1406
1407 pcinfo->pwr[3][2] = (val >> 14) & 0x3;
1048643e 1408 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1409 pcinfo->pwr[3][2] |= ((val >> 0) & 0x3) << 2;
1048643e 1410
8e218fb2
NK		 1411 pcinfo->pddac[3][2] = (val >> 2) & 0x3f;
1412 pcinfo->pwr[3][3] = (val >> 8) & 0xf;
1048643e 1413
8e218fb2 1414 pcinfo->pddac[3][3] = (val >> 12) & 0xF;
1048643e 1415 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1416 pcinfo->pddac[3][3] |= ((val >> 0) & 0x3) << 4;
1048643e 1417 } else if (pd_gains == 3) {
8e218fb2 1418 pcinfo->pwr[2][3] = (val >> 14) & 0x3;
1048643e 1419 AR5K_EEPROM_READ(offset++, val);
8e218fb2 1420 pcinfo->pwr[2][3] |= ((val >> 0) & 0x3) << 2;
1048643e 1421
8e218fb2 1422 pcinfo->pddac[2][3] = (val >> 2) & 0x3f;
c6e387a2
NK		 1423 }
1424 }
1425
8e218fb2 1426 return ath5k_eeprom_convert_pcal_info_2413(ah, mode, chinfo);
1048643e
FF		 1427}
1428
8e218fb2 1429
1048643e
FF		 1430/*
1431 * Read per rate target power (this is the maximum tx power
1432 * supported by the card). This info is used when setting
1433 * tx power, no matter the channel.
1434 *
1435 * This also works for v5 EEPROMs.
1436 */
8e218fb2
NK		 1437static int
1438ath5k_eeprom_read_target_rate_pwr_info(struct ath5k_hw *ah, unsigned int mode)
1048643e
FF		 1439{
1440 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1441 struct ath5k_rate_pcal_info *rate_pcal_info;
8e218fb2 1442 u8 *rate_target_pwr_num;
1048643e
FF		 1443 u32 offset;
1444 u16 val;
1445 int ret, i;
1446
1447 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1);
1448 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode];
1449 switch (mode) {
1450 case AR5K_EEPROM_MODE_11A:
1451 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version);
1452 rate_pcal_info = ee->ee_rate_tpwr_a;
1453 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_CHAN;
1454 break;
1455 case AR5K_EEPROM_MODE_11B:
1456 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version);
1457 rate_pcal_info = ee->ee_rate_tpwr_b;
1458 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */
1459 break;
1460 case AR5K_EEPROM_MODE_11G:
1461 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version);
1462 rate_pcal_info = ee->ee_rate_tpwr_g;
1463 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN;
1464 break;
1465 default:
1466 return -EINVAL;
1467 }
1468
1469 /* Different freq mask for older eeproms (<= v3.2) */
1470 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) {
1471 for (i = 0; i < (*rate_target_pwr_num); i++) {
1472 AR5K_EEPROM_READ(offset++, val);
1473 rate_pcal_info[i].freq =
1474 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode);
1475
1476 rate_pcal_info[i].target_power_6to24 = ((val >> 3) & 0x3f);
1477 rate_pcal_info[i].target_power_36 = (val << 3) & 0x3f;
1478
1479 AR5K_EEPROM_READ(offset++, val);
1480
1481 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1482 val == 0) {
1483 (*rate_target_pwr_num) = i;
1484 break;
1485 }
1486
1487 rate_pcal_info[i].target_power_36 |= ((val >> 13) & 0x7);
1488 rate_pcal_info[i].target_power_48 = ((val >> 7) & 0x3f);
1489 rate_pcal_info[i].target_power_54 = ((val >> 1) & 0x3f);
1490 }
1491 } else {
1492 for (i = 0; i < (*rate_target_pwr_num); i++) {
1493 AR5K_EEPROM_READ(offset++, val);
1494 rate_pcal_info[i].freq =
1495 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode);
1496
1497 rate_pcal_info[i].target_power_6to24 = ((val >> 2) & 0x3f);
1498 rate_pcal_info[i].target_power_36 = (val << 4) & 0x3f;
1499
1500 AR5K_EEPROM_READ(offset++, val);
1501
1502 if (rate_pcal_info[i].freq == AR5K_EEPROM_CHANNEL_DIS ||
1503 val == 0) {
1504 (*rate_target_pwr_num) = i;
1505 break;
1506 }
1507
1508 rate_pcal_info[i].target_power_36 |= (val >> 12) & 0xf;
1509 rate_pcal_info[i].target_power_48 = ((val >> 6) & 0x3f);
1510 rate_pcal_info[i].target_power_54 = (val & 0x3f);
1511 }
1512 }
1513
1514 return 0;
1515}
1516
0ea9c00c
NK		 1517/*
1518 * Read per channel calibration info from EEPROM
1519 *
1520 * This info is used to calibrate the baseband power table. Imagine
1521 * that for each channel there is a power curve that's hw specific
1522 * (depends on amplifier etc) and we try to "correct" this curve using
bf48aabb 1523 * offsets we pass on to phy chip (baseband -> before amplifier) so that
0ea9c00c
NK		 1524 * it can use accurate power values when setting tx power (takes amplifier's
1525 * performance on each channel into account).
1526 *
1527 * EEPROM provides us with the offsets for some pre-calibrated channels
1528 * and we have to interpolate to create the full table for these channels and
1529 * also the table for any channel.
1530 */
1048643e
FF		 1531static int
1532ath5k_eeprom_read_pcal_info(struct ath5k_hw *ah)
1533{
1534 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1535 int (*read_pcal)(struct ath5k_hw *hw, int mode);
1536 int mode;
1537 int err;
1538
1539 if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) &&
1540 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1))
1541 read_pcal = ath5k_eeprom_read_pcal_info_5112;
1542 else if ((ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0) &&
1543 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2))
1544 read_pcal = ath5k_eeprom_read_pcal_info_2413;
1545 else
1546 read_pcal = ath5k_eeprom_read_pcal_info_5111;
1547
8e218fb2
NK		 1548
1549 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G;
1550 mode++) {
1048643e
FF		 1551 err = read_pcal(ah, mode);
1552 if (err)
1553 return err;
1554
1555 err = ath5k_eeprom_read_target_rate_pwr_info(ah, mode);
1556 if (err < 0)
1557 return err;
1558 }
1559
1560 return 0;
1561}
1562
8e218fb2
NK		 1563static int
1564ath5k_eeprom_free_pcal_info(struct ath5k_hw *ah, int mode)
1565{
1566 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1567 struct ath5k_chan_pcal_info *chinfo;
1568 u8 pier, pdg;
1569
1570 switch (mode) {
1571 case AR5K_EEPROM_MODE_11A:
1572 if (!AR5K_EEPROM_HDR_11A(ee->ee_header))
1573 return 0;
1574 chinfo = ee->ee_pwr_cal_a;
1575 break;
1576 case AR5K_EEPROM_MODE_11B:
1577 if (!AR5K_EEPROM_HDR_11B(ee->ee_header))
1578 return 0;
1579 chinfo = ee->ee_pwr_cal_b;
1580 break;
1581 case AR5K_EEPROM_MODE_11G:
1582 if (!AR5K_EEPROM_HDR_11G(ee->ee_header))
1583 return 0;
1584 chinfo = ee->ee_pwr_cal_g;
1585 break;
1586 default:
1587 return -EINVAL;
1588 }
1589
1590 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) {
1591 if (!chinfo[pier].pd_curves)
1592 continue;
1593
1594 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) {
1595 struct ath5k_pdgain_info *pd =
1596 &chinfo[pier].pd_curves[pdg];
1597
1598 if (pd != NULL) {
1599 kfree(pd->pd_step);
1600 kfree(pd->pd_pwr);
1601 }
1602 }
1603
1604 kfree(chinfo[pier].pd_curves);
1605 }
1606
1607 return 0;
1608}
1609
1610void
1611ath5k_eeprom_detach(struct ath5k_hw *ah)
1612{
1613 u8 mode;
1614
1615 for (mode = AR5K_EEPROM_MODE_11A; mode <= AR5K_EEPROM_MODE_11G; mode++)
1616 ath5k_eeprom_free_pcal_info(ah, mode);
1617}
1618
0ea9c00c 1619/* Read conformance test limits used for regulatory control */
1048643e
FF		 1620static int
1621ath5k_eeprom_read_ctl_info(struct ath5k_hw *ah)
1622{
1623 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1624 struct ath5k_edge_power *rep;
1625 unsigned int fmask, pmask;
1626 unsigned int ctl_mode;
1627 int ret, i, j;
1628 u32 offset;
1629 u16 val;
1630
1631 pmask = AR5K_EEPROM_POWER_M;
1632 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version);
1633 offset = AR5K_EEPROM_CTL(ee->ee_version);
1634 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version);
1635 for (i = 0; i < ee->ee_ctls; i += 2) {
1636 AR5K_EEPROM_READ(offset++, val);
1637 ee->ee_ctl[i] = (val >> 8) & 0xff;
1638 ee->ee_ctl[i + 1] = val & 0xff;
1639 }
1640
1641 offset = AR5K_EEPROM_GROUP8_OFFSET;
1642 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0)
1643 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) -
1644 AR5K_EEPROM_GROUP5_OFFSET;
1645 else
1646 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version);
1647
1648 rep = ee->ee_ctl_pwr;
1649 for(i = 0; i < ee->ee_ctls; i++) {
1650 switch(ee->ee_ctl[i] & AR5K_CTL_MODE_M) {
1651 case AR5K_CTL_11A:
1652 case AR5K_CTL_TURBO:
1653 ctl_mode = AR5K_EEPROM_MODE_11A;
1654 break;
1655 default:
1656 ctl_mode = AR5K_EEPROM_MODE_11G;
1657 break;
1658 }
1659 if (ee->ee_ctl[i] == 0) {
1660 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3)
1661 offset += 8;
1662 else
1663 offset += 7;
1664 rep += AR5K_EEPROM_N_EDGES;
1665 continue;
1666 }
1667 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) {
1668 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1669 AR5K_EEPROM_READ(offset++, val);
1670 rep[j].freq = (val >> 8) & fmask;
1671 rep[j + 1].freq = val & fmask;
1672 }
1673 for (j = 0; j < AR5K_EEPROM_N_EDGES; j += 2) {
1674 AR5K_EEPROM_READ(offset++, val);
1675 rep[j].edge = (val >> 8) & pmask;
1676 rep[j].flag = (val >> 14) & 1;
1677 rep[j + 1].edge = val & pmask;
1678 rep[j + 1].flag = (val >> 6) & 1;
1679 }
1680 } else {
1681 AR5K_EEPROM_READ(offset++, val);
1682 rep[0].freq = (val >> 9) & fmask;
1683 rep[1].freq = (val >> 2) & fmask;
1684 rep[2].freq = (val << 5) & fmask;
1685
1686 AR5K_EEPROM_READ(offset++, val);
1687 rep[2].freq |= (val >> 11) & 0x1f;
1688 rep[3].freq = (val >> 4) & fmask;
1689 rep[4].freq = (val << 3) & fmask;
1690
1691 AR5K_EEPROM_READ(offset++, val);
1692 rep[4].freq |= (val >> 13) & 0x7;
1693 rep[5].freq = (val >> 6) & fmask;
1694 rep[6].freq = (val << 1) & fmask;
1695
1696 AR5K_EEPROM_READ(offset++, val);
1697 rep[6].freq |= (val >> 15) & 0x1;
1698 rep[7].freq = (val >> 8) & fmask;
1699
1700 rep[0].edge = (val >> 2) & pmask;
1701 rep[1].edge = (val << 4) & pmask;
1702
1703 AR5K_EEPROM_READ(offset++, val);
1704 rep[1].edge |= (val >> 12) & 0xf;
1705 rep[2].edge = (val >> 6) & pmask;
1706 rep[3].edge = val & pmask;
1707
1708 AR5K_EEPROM_READ(offset++, val);
1709 rep[4].edge = (val >> 10) & pmask;
1710 rep[5].edge = (val >> 4) & pmask;
1711 rep[6].edge = (val << 2) & pmask;
1712
1713 AR5K_EEPROM_READ(offset++, val);
1714 rep[6].edge |= (val >> 14) & 0x3;
1715 rep[7].edge = (val >> 8) & pmask;
1716 }
1717 for (j = 0; j < AR5K_EEPROM_N_EDGES; j++) {
1718 rep[j].freq = ath5k_eeprom_bin2freq(ee,
1719 rep[j].freq, ctl_mode);
1720 }
1721 rep += AR5K_EEPROM_N_EDGES;
1722 }
c6e387a2
NK		 1723
1724 return 0;
1725}
1726
cd417519
NK		 1727static int
1728ath5k_eeprom_read_spur_chans(struct ath5k_hw *ah)
1729{
1730 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1731 u32 offset;
1732 u16 val;
1733 int ret = 0, i;
1734
1735 offset = AR5K_EEPROM_CTL(ee->ee_version) +
1736 AR5K_EEPROM_N_CTLS(ee->ee_version);
1737
1738 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) {
1739 /* No spur info for 5GHz */
1740 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR;
1741 /* 2 channels for 2GHz (2464/2420) */
1742 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1;
1743 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2;
1744 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR;
1745 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) {
1746 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1747 AR5K_EEPROM_READ(offset, val);
1748 ee->ee_spur_chans[i][0] = val;
1749 AR5K_EEPROM_READ(offset + AR5K_EEPROM_N_SPUR_CHANS,
1750 val);
1751 ee->ee_spur_chans[i][1] = val;
1752 offset++;
1753 }
1754 }
1755
1756 return ret;
1757}
1048643e
FF		 1758
1759/*
cd417519 1760 * Initialize eeprom data structure
1048643e
FF		 1761 */
1762int
1763ath5k_eeprom_init(struct ath5k_hw *ah)
1764{
1765 int err;
1766
1767 err = ath5k_eeprom_init_header(ah);
1768 if (err < 0)
1769 return err;
1770
1771 err = ath5k_eeprom_init_modes(ah);
1772 if (err < 0)
1773 return err;
1774
1775 err = ath5k_eeprom_read_pcal_info(ah);
1776 if (err < 0)
1777 return err;
1778
1779 err = ath5k_eeprom_read_ctl_info(ah);
1780 if (err < 0)
1781 return err;
1782
cd417519
NK		 1783 err = ath5k_eeprom_read_spur_chans(ah);
1784 if (err < 0)
1785 return err;
1786
1048643e
FF		 1787 return 0;
1788}
e8f055f0 1789
c6e387a2
NK		 1790/*
1791 * Read the MAC address from eeprom
1792 */
1793int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
1794{
8d6c39ef 1795 u8 mac_d[ETH_ALEN] = {};
c6e387a2
NK		 1796 u32 total, offset;
1797 u16 data;
1798 int octet, ret;
1799
c6e387a2
NK		 1800 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
1801 if (ret)
1802 return ret;
1803
1804 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
1805 ret = ath5k_hw_eeprom_read(ah, offset, &data);
1806 if (ret)
1807 return ret;
1808
1809 total += data;
1810 mac_d[octet + 1] = data & 0xff;
1811 mac_d[octet] = data >> 8;
1812 octet += 2;
1813 }
1814
c6e387a2
NK		 1815 if (!total || total == 3 * 0xffff)
1816 return -EINVAL;
1817
8d6c39ef
JS		 1818 memcpy(mac, mac_d, ETH_ALEN);
1819
c6e387a2
NK		 1820 return 0;
1821}
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