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ath5k: Count how many times a queue got stuck
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
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fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
6ccf15a1 51#include <linux/pci-aspm.h>
fa1c114f
JS		 52#include <linux/ethtool.h>
53#include <linux/uaccess.h>
5a0e3ad6 54#include <linux/slab.h>
fa1c114f
JS		 55
56#include <net/ieee80211_radiotap.h>
57
58#include <asm/unaligned.h>
59
60#include "base.h"
61#include "reg.h"
62#include "debug.h"
2111ac0d 63#include "ani.h"
fa1c114f 64
9ad9a26e 65static int modparam_nohwcrypt;
46802a4f 66module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 67MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 68
42639fcd 69static int modparam_all_channels;
46802a4f 70module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 71MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
72
fa1c114f
JS		 73/* Module info */
74MODULE_AUTHOR("Jiri Slaby");
75MODULE_AUTHOR("Nick Kossifidis");
76MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
77MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
78MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 79MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f 80
8a63facc
BC		 81static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
82static int ath5k_beacon_update(struct ieee80211_hw *hw,
83 struct ieee80211_vif *vif);
84static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f
JS		 85
86/* Known PCI ids */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
97a81f5c
PR		 88 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
89 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
90 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
91 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
92 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
93 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
94 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
96 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
103 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
104 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
105 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
fa1c114f
JS		 106 { 0 }
107};
108MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
109
110/* Known SREVs */
2c91108c 111static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 112 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
113 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
114 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
115 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
116 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
117 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
118 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
119 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
120 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
121 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
122 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
123 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
124 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
125 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
126 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
127 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
128 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
129 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
143 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
144 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
145 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 146 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
147 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
148};
149
2c91108c 150static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 151 { .bitrate = 10,
152 .hw_value = ATH5K_RATE_CODE_1M, },
153 { .bitrate = 20,
154 .hw_value = ATH5K_RATE_CODE_2M,
155 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
156 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 { .bitrate = 55,
158 .hw_value = ATH5K_RATE_CODE_5_5M,
159 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
160 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 { .bitrate = 110,
162 .hw_value = ATH5K_RATE_CODE_11M,
163 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
164 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 { .bitrate = 60,
166 .hw_value = ATH5K_RATE_CODE_6M,
167 .flags = 0 },
168 { .bitrate = 90,
169 .hw_value = ATH5K_RATE_CODE_9M,
170 .flags = 0 },
171 { .bitrate = 120,
172 .hw_value = ATH5K_RATE_CODE_12M,
173 .flags = 0 },
174 { .bitrate = 180,
175 .hw_value = ATH5K_RATE_CODE_18M,
176 .flags = 0 },
177 { .bitrate = 240,
178 .hw_value = ATH5K_RATE_CODE_24M,
179 .flags = 0 },
180 { .bitrate = 360,
181 .hw_value = ATH5K_RATE_CODE_36M,
182 .flags = 0 },
183 { .bitrate = 480,
184 .hw_value = ATH5K_RATE_CODE_48M,
185 .flags = 0 },
186 { .bitrate = 540,
187 .hw_value = ATH5K_RATE_CODE_54M,
188 .flags = 0 },
189 /* XR missing */
190};
191
9e4e43f2 192static inline void ath5k_txbuf_free_skb(struct ath5k_softc *sc,
fa1c114f
JS		 193 struct ath5k_buf *bf)
194{
195 BUG_ON(!bf);
196 if (!bf->skb)
197 return;
198 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
199 PCI_DMA_TODEVICE);
00482973 200 dev_kfree_skb_any(bf->skb);
fa1c114f 201 bf->skb = NULL;
39d63f2a
BR		 202 bf->skbaddr = 0;
203 bf->desc->ds_data = 0;
fa1c114f
JS		 204}
205
9e4e43f2 206static inline void ath5k_rxbuf_free_skb(struct ath5k_softc *sc,
a6c8d375
FF		 207 struct ath5k_buf *bf)
208{
cc861f74
LR		 209 struct ath5k_hw *ah = sc->ah;
210 struct ath_common *common = ath5k_hw_common(ah);
211
a6c8d375
FF		 212 BUG_ON(!bf);
213 if (!bf->skb)
214 return;
cc861f74 215 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
a6c8d375
FF		 216 PCI_DMA_FROMDEVICE);
217 dev_kfree_skb_any(bf->skb);
218 bf->skb = NULL;
39d63f2a
BR		 219 bf->skbaddr = 0;
220 bf->desc->ds_data = 0;
a6c8d375
FF		 221}
222
223
fa1c114f
JS		 224static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
225{
226 u64 tsf = ath5k_hw_get_tsf64(ah);
227
228 if ((tsf & 0x7fff) < rstamp)
229 tsf -= 0x8000;
230
231 return (tsf & ~0x7fff) | rstamp;
232}
233
fa1c114f
JS		 234static const char *
235ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
236{
237 const char *name = "xxxxx";
238 unsigned int i;
239
240 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
241 if (srev_names[i].sr_type != type)
242 continue;
75d0edb8
NK		 243
244 if ((val & 0xf0) == srev_names[i].sr_val)
245 name = srev_names[i].sr_name;
246
247 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 248 name = srev_names[i].sr_name;
249 break;
250 }
251 }
252
253 return name;
254}
e5aa8474
LR		 255static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
256{
257 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
258 return ath5k_hw_reg_read(ah, reg_offset);
259}
260
261static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
262{
263 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
264 ath5k_hw_reg_write(ah, val, reg_offset);
265}
266
267static const struct ath_ops ath5k_common_ops = {
268 .read = ath5k_ioread32,
269 .write = ath5k_iowrite32,
270};
fa1c114f 271
8a63facc
BC		 272/***********************\
273* Driver Initialization *
274\***********************/
275
276static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 277{
8a63facc
BC		 278 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
279 struct ath5k_softc *sc = hw->priv;
280 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 281
8a63facc
BC		 282 return ath_reg_notifier_apply(wiphy, request, regulatory);
283}
6ccf15a1 284
8a63facc
BC		 285/********************\
286* Channel/mode setup *
287\********************/
fa1c114f 288
8a63facc
BC		 289/*
290 * Convert IEEE channel number to MHz frequency.
291 */
292static inline short
293ath5k_ieee2mhz(short chan)
294{
295 if (chan <= 14 || chan >= 27)
296 return ieee80211chan2mhz(chan);
297 else
298 return 2212 + chan * 20;
299}
fa1c114f 300
8a63facc
BC		 301/*
302 * Returns true for the channel numbers used without all_channels modparam.
303 */
304static bool ath5k_is_standard_channel(short chan)
305{
306 return ((chan <= 14) ||
307 /* UNII 1,2 */
308 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
309 /* midband */
310 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
311 /* UNII-3 */
312 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
313}
fa1c114f 314
8a63facc
BC		 315static unsigned int
316ath5k_copy_channels(struct ath5k_hw *ah,
317 struct ieee80211_channel *channels,
318 unsigned int mode,
319 unsigned int max)
320{
321 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f 322
8a63facc
BC		 323 if (!test_bit(mode, ah->ah_modes))
324 return 0;
fa1c114f 325
8a63facc
BC		 326 switch (mode) {
327 case AR5K_MODE_11A:
328 case AR5K_MODE_11A_TURBO:
329 /* 1..220, but 2GHz frequencies are filtered by check_channel */
330 size = 220 ;
331 chfreq = CHANNEL_5GHZ;
332 break;
333 case AR5K_MODE_11B:
334 case AR5K_MODE_11G:
335 case AR5K_MODE_11G_TURBO:
336 size = 26;
337 chfreq = CHANNEL_2GHZ;
338 break;
339 default:
340 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
341 return 0;
fa1c114f
JS		 342 }
343
8a63facc
BC		 344 for (i = 0, count = 0; i < size && max > 0; i++) {
345 ch = i + 1 ;
346 freq = ath5k_ieee2mhz(ch);
fa1c114f 347
8a63facc
BC		 348 /* Check if channel is supported by the chipset */
349 if (!ath5k_channel_ok(ah, freq, chfreq))
350 continue;
f59ac048 351
8a63facc
BC		 352 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
353 continue;
f59ac048 354
8a63facc
BC		 355 /* Write channel info and increment counter */
356 channels[count].center_freq = freq;
357 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
358 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
359 switch (mode) {
360 case AR5K_MODE_11A:
361 case AR5K_MODE_11G:
362 channels[count].hw_value = chfreq | CHANNEL_OFDM;
363 break;
364 case AR5K_MODE_11A_TURBO:
365 case AR5K_MODE_11G_TURBO:
366 channels[count].hw_value = chfreq |
367 CHANNEL_OFDM | CHANNEL_TURBO;
368 break;
369 case AR5K_MODE_11B:
370 channels[count].hw_value = CHANNEL_B;
371 }
fa1c114f 372
8a63facc
BC		 373 count++;
374 max--;
375 }
fa1c114f 376
8a63facc
BC		 377 return count;
378}
fa1c114f 379
8a63facc
BC		 380static void
381ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
382{
383 u8 i;
fa1c114f 384
8a63facc
BC		 385 for (i = 0; i < AR5K_MAX_RATES; i++)
386 sc->rate_idx[b->band][i] = -1;
fa1c114f 387
8a63facc
BC		 388 for (i = 0; i < b->n_bitrates; i++) {
389 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
390 if (b->bitrates[i].hw_value_short)
391 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 392 }
8a63facc 393}
fa1c114f 394
8a63facc
BC		 395static int
396ath5k_setup_bands(struct ieee80211_hw *hw)
397{
398 struct ath5k_softc *sc = hw->priv;
399 struct ath5k_hw *ah = sc->ah;
400 struct ieee80211_supported_band *sband;
401 int max_c, count_c = 0;
402 int i;
fa1c114f 403
8a63facc
BC		 404 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
405 max_c = ARRAY_SIZE(sc->channels);
db719718 406
8a63facc
BC		 407 /* 2GHz band */
408 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
409 sband->band = IEEE80211_BAND_2GHZ;
410 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 411
8a63facc
BC		 412 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
413 /* G mode */
414 memcpy(sband->bitrates, &ath5k_rates[0],
415 sizeof(struct ieee80211_rate) * 12);
416 sband->n_bitrates = 12;
2f7fe870 417
8a63facc
BC		 418 sband->channels = sc->channels;
419 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
420 AR5K_MODE_11G, max_c);
fa1c114f 421
8a63facc
BC		 422 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
423 count_c = sband->n_channels;
424 max_c -= count_c;
425 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
426 /* B mode */
427 memcpy(sband->bitrates, &ath5k_rates[0],
428 sizeof(struct ieee80211_rate) * 4);
429 sband->n_bitrates = 4;
fa1c114f 430
8a63facc
BC		 431 /* 5211 only supports B rates and uses 4bit rate codes
432 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
433 * fix them up here:
434 */
435 if (ah->ah_version == AR5K_AR5211) {
436 for (i = 0; i < 4; i++) {
437 sband->bitrates[i].hw_value =
438 sband->bitrates[i].hw_value & 0xF;
439 sband->bitrates[i].hw_value_short =
440 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 441 }
442 }
fa1c114f 443
8a63facc
BC		 444 sband->channels = sc->channels;
445 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
446 AR5K_MODE_11B, max_c);
fa1c114f 447
8a63facc
BC		 448 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
449 count_c = sband->n_channels;
450 max_c -= count_c;
451 }
452 ath5k_setup_rate_idx(sc, sband);
fa1c114f 453
8a63facc
BC		 454 /* 5GHz band, A mode */
455 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
456 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
457 sband->band = IEEE80211_BAND_5GHZ;
458 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 459
8a63facc
BC		 460 memcpy(sband->bitrates, &ath5k_rates[4],
461 sizeof(struct ieee80211_rate) * 8);
462 sband->n_bitrates = 8;
fa1c114f 463
8a63facc
BC		 464 sband->channels = &sc->channels[count_c];
465 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
466 AR5K_MODE_11A, max_c);
fa1c114f 467
8a63facc
BC		 468 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
469 }
470 ath5k_setup_rate_idx(sc, sband);
471
472 ath5k_debug_dump_bands(sc);
fa1c114f 473
fa1c114f
JS		 474 return 0;
475}
476
8a63facc
BC		 477/*
478 * Set/change channels. We always reset the chip.
479 * To accomplish this we must first cleanup any pending DMA,
480 * then restart stuff after a la ath5k_init.
481 *
482 * Called with sc->lock.
483 */
484static int
485ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
486{
487 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
488 "channel set, resetting (%u -> %u MHz)\n",
489 sc->curchan->center_freq, chan->center_freq);
490
8451d22d 491 /*
8a63facc
BC		 492 * To switch channels clear any pending DMA operations;
493 * wait long enough for the RX fifo to drain, reset the
494 * hardware at the new frequency, and then re-enable
495 * the relevant bits of the h/w.
8451d22d 496 */
8a63facc 497 return ath5k_reset(sc, chan);
fa1c114f 498}
fa1c114f 499
8a63facc
BC		 500static void
501ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
f769c36b 502{
8a63facc 503 sc->curmode = mode;
f769c36b 504
8a63facc
BC		 505 if (mode == AR5K_MODE_11A) {
506 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
507 } else {
508 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
509 }
f769c36b
BC		 510}
511
8a63facc
BC		 512static void
513ath5k_mode_setup(struct ath5k_softc *sc)
fa1c114f 514{
fa1c114f 515 struct ath5k_hw *ah = sc->ah;
8a63facc 516 u32 rfilt;
fa1c114f 517
8a63facc
BC		 518 /* configure rx filter */
519 rfilt = sc->filter_flags;
520 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f 521
8a63facc
BC		 522 if (ath5k_hw_hasbssidmask(ah))
523 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
a6668193 524
8a63facc
BC		 525 /* configure operational mode */
526 ath5k_hw_set_opmode(ah, sc->opmode);
fa1c114f 527
8a63facc
BC		 528 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d\n", sc->opmode);
529 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
530}
fa1c114f 531
8a63facc
BC		 532static inline int
533ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
534{
535 int rix;
fa1c114f 536
8a63facc
BC		 537 /* return base rate on errors */
538 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
539 "hw_rix out of bounds: %x\n", hw_rix))
540 return 0;
541
542 rix = sc->rate_idx[sc->curband->band][hw_rix];
543 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
544 rix = 0;
545
546 return rix;
547}
548
549/***************\
550* Buffers setup *
551\***************/
552
553static
554struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
555{
556 struct ath_common *common = ath5k_hw_common(sc->ah);
557 struct sk_buff *skb;
fa1c114f
JS		 558
559 /*
8a63facc
BC		 560 * Allocate buffer with headroom_needed space for the
561 * fake physical layer header at the start.
fa1c114f 562 */
8a63facc
BC		 563 skb = ath_rxbuf_alloc(common,
564 common->rx_bufsize,
565 GFP_ATOMIC);
fa1c114f 566
8a63facc
BC		 567 if (!skb) {
568 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
569 common->rx_bufsize);
570 return NULL;
fa1c114f
JS		 571 }
572
8a63facc
BC		 573 *skb_addr = pci_map_single(sc->pdev,
574 skb->data, common->rx_bufsize,
575 PCI_DMA_FROMDEVICE);
576 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
577 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
578 dev_kfree_skb(skb);
579 return NULL;
0e149cf5 580 }
8a63facc
BC		 581 return skb;
582}
0e149cf5 583
8a63facc
BC		 584static int
585ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
586{
587 struct ath5k_hw *ah = sc->ah;
588 struct sk_buff *skb = bf->skb;
589 struct ath5k_desc *ds;
590 int ret;
fa1c114f 591
8a63facc
BC		 592 if (!skb) {
593 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
594 if (!skb)
595 return -ENOMEM;
596 bf->skb = skb;
f769c36b
BC		 597 }
598
8a63facc
BC		 599 /*
600 * Setup descriptors. For receive we always terminate
601 * the descriptor list with a self-linked entry so we'll
602 * not get overrun under high load (as can happen with a
603 * 5212 when ANI processing enables PHY error frames).
604 *
605 * To ensure the last descriptor is self-linked we create
606 * each descriptor as self-linked and add it to the end. As
607 * each additional descriptor is added the previous self-linked
608 * entry is "fixed" naturally. This should be safe even
609 * if DMA is happening. When processing RX interrupts we
610 * never remove/process the last, self-linked, entry on the
611 * descriptor list. This ensures the hardware always has
612 * someplace to write a new frame.
613 */
614 ds = bf->desc;
615 ds->ds_link = bf->daddr; /* link to self */
616 ds->ds_data = bf->skbaddr;
617 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 618 if (ret) {
8a63facc
BC		 619 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
620 return ret;
fa1c114f
JS		 621 }
622
8a63facc
BC		 623 if (sc->rxlink != NULL)
624 *sc->rxlink = bf->daddr;
625 sc->rxlink = &ds->ds_link;
fa1c114f 626 return 0;
fa1c114f
JS		 627}
628
8a63facc 629static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 630{
8a63facc
BC		 631 struct ieee80211_hdr *hdr;
632 enum ath5k_pkt_type htype;
633 __le16 fc;
fa1c114f 634
8a63facc
BC		 635 hdr = (struct ieee80211_hdr *)skb->data;
636 fc = hdr->frame_control;
fa1c114f 637
8a63facc
BC		 638 if (ieee80211_is_beacon(fc))
639 htype = AR5K_PKT_TYPE_BEACON;
640 else if (ieee80211_is_probe_resp(fc))
641 htype = AR5K_PKT_TYPE_PROBE_RESP;
642 else if (ieee80211_is_atim(fc))
643 htype = AR5K_PKT_TYPE_ATIM;
644 else if (ieee80211_is_pspoll(fc))
645 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 646 else
8a63facc 647 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 648
8a63facc 649 return htype;
42639fcd
BC		 650}
651
8a63facc
BC		 652static int
653ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
654 struct ath5k_txq *txq, int padsize)
fa1c114f 655{
8a63facc
BC		 656 struct ath5k_hw *ah = sc->ah;
657 struct ath5k_desc *ds = bf->desc;
658 struct sk_buff *skb = bf->skb;
659 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
660 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
661 struct ieee80211_rate *rate;
662 unsigned int mrr_rate[3], mrr_tries[3];
663 int i, ret;
664 u16 hw_rate;
665 u16 cts_rate = 0;
666 u16 duration = 0;
667 u8 rc_flags;
fa1c114f 668
8a63facc 669 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 670
8a63facc
BC		 671 /* XXX endianness */
672 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
673 PCI_DMA_TODEVICE);
fa1c114f 674
8a63facc 675 rate = ieee80211_get_tx_rate(sc->hw, info);
fa1c114f 676
8a63facc
BC		 677 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
678 flags |= AR5K_TXDESC_NOACK;
fa1c114f 679
8a63facc
BC		 680 rc_flags = info->control.rates[0].flags;
681 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
682 rate->hw_value_short : rate->hw_value;
42639fcd 683
8a63facc
BC		 684 pktlen = skb->len;
685
686 /* FIXME: If we are in g mode and rate is a CCK rate
687 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
688 * from tx power (value is in dB units already) */
689 if (info->control.hw_key) {
690 keyidx = info->control.hw_key->hw_key_idx;
691 pktlen += info->control.hw_key->icv_len;
692 }
693 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
694 flags |= AR5K_TXDESC_RTSENA;
695 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
696 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
697 sc->vif, pktlen, info));
698 }
699 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
700 flags |= AR5K_TXDESC_CTSENA;
701 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
702 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
703 sc->vif, pktlen, info));
704 }
705 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
706 ieee80211_get_hdrlen_from_skb(skb), padsize,
707 get_hw_packet_type(skb),
708 (sc->power_level * 2),
709 hw_rate,
710 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
711 cts_rate, duration);
712 if (ret)
713 goto err_unmap;
714
715 memset(mrr_rate, 0, sizeof(mrr_rate));
716 memset(mrr_tries, 0, sizeof(mrr_tries));
717 for (i = 0; i < 3; i++) {
718 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
719 if (!rate)
400ec45a 720 break;
fa1c114f 721
8a63facc
BC		 722 mrr_rate[i] = rate->hw_value;
723 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 724 }
725
8a63facc
BC		 726 ath5k_hw_setup_mrr_tx_desc(ah, ds,
727 mrr_rate[0], mrr_tries[0],
728 mrr_rate[1], mrr_tries[1],
729 mrr_rate[2], mrr_tries[2]);
fa1c114f 730
8a63facc
BC		 731 ds->ds_link = 0;
732 ds->ds_data = bf->skbaddr;
63266a65 733
8a63facc
BC		 734 spin_lock_bh(&txq->lock);
735 list_add_tail(&bf->list, &txq->q);
925e0b06 736 txq->txq_len++;
8a63facc
BC		 737 if (txq->link == NULL) /* is this first packet? */
738 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
739 else /* no, so only link it */
740 *txq->link = bf->daddr;
63266a65 741
8a63facc
BC		 742 txq->link = &ds->ds_link;
743 ath5k_hw_start_tx_dma(ah, txq->qnum);
744 mmiowb();
745 spin_unlock_bh(&txq->lock);
746
747 return 0;
748err_unmap:
749 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
750 return ret;
63266a65
BR		 751}
752
8a63facc
BC		 753/*******************\
754* Descriptors setup *
755\*******************/
756
d8ee398d 757static int
8a63facc 758ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
fa1c114f 759{
8a63facc
BC		 760 struct ath5k_desc *ds;
761 struct ath5k_buf *bf;
762 dma_addr_t da;
763 unsigned int i;
764 int ret;
d8ee398d 765
8a63facc
BC		 766 /* allocate descriptors */
767 sc->desc_len = sizeof(struct ath5k_desc) *
768 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
769 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
770 if (sc->desc == NULL) {
771 ATH5K_ERR(sc, "can't allocate descriptors\n");
772 ret = -ENOMEM;
773 goto err;
774 }
775 ds = sc->desc;
776 da = sc->desc_daddr;
777 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
778 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 779
8a63facc
BC		 780 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
781 sizeof(struct ath5k_buf), GFP_KERNEL);
782 if (bf == NULL) {
783 ATH5K_ERR(sc, "can't allocate bufptr\n");
784 ret = -ENOMEM;
785 goto err_free;
786 }
787 sc->bufptr = bf;
fa1c114f 788
8a63facc
BC		 789 INIT_LIST_HEAD(&sc->rxbuf);
790 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
791 bf->desc = ds;
792 bf->daddr = da;
793 list_add_tail(&bf->list, &sc->rxbuf);
794 }
d8ee398d 795
8a63facc
BC		 796 INIT_LIST_HEAD(&sc->txbuf);
797 sc->txbuf_len = ATH_TXBUF;
798 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
799 da += sizeof(*ds)) {
800 bf->desc = ds;
801 bf->daddr = da;
802 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 803 }
804
8a63facc
BC		 805 /* beacon buffer */
806 bf->desc = ds;
807 bf->daddr = da;
808 sc->bbuf = bf;
fa1c114f 809
8a63facc
BC		 810 return 0;
811err_free:
812 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
813err:
814 sc->desc = NULL;
815 return ret;
816}
fa1c114f 817
8a63facc
BC		 818static void
819ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
820{
821 struct ath5k_buf *bf;
d8ee398d 822
8a63facc
BC		 823 ath5k_txbuf_free_skb(sc, sc->bbuf);
824 list_for_each_entry(bf, &sc->txbuf, list)
825 ath5k_txbuf_free_skb(sc, bf);
826 list_for_each_entry(bf, &sc->rxbuf, list)
827 ath5k_rxbuf_free_skb(sc, bf);
d8ee398d 828
8a63facc
BC		 829 /* Free memory associated with all descriptors */
830 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
831 sc->desc = NULL;
832 sc->desc_daddr = 0;
d8ee398d 833
8a63facc
BC		 834 kfree(sc->bufptr);
835 sc->bufptr = NULL;
836 sc->bbuf = NULL;
fa1c114f
JS		 837}
838
8a63facc
BC		 839
840/**************\
841* Queues setup *
842\**************/
843
844static struct ath5k_txq *
845ath5k_txq_setup(struct ath5k_softc *sc,
846 int qtype, int subtype)
fa1c114f 847{
8a63facc
BC		 848 struct ath5k_hw *ah = sc->ah;
849 struct ath5k_txq *txq;
850 struct ath5k_txq_info qi = {
851 .tqi_subtype = subtype,
852 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
853 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
854 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
855 };
856 int qnum;
d8ee398d 857
e30eb4ab 858 /*
8a63facc
BC		 859 * Enable interrupts only for EOL and DESC conditions.
860 * We mark tx descriptors to receive a DESC interrupt
861 * when a tx queue gets deep; otherwise we wait for the
862 * EOL to reap descriptors. Note that this is done to
863 * reduce interrupt load and this only defers reaping
864 * descriptors, never transmitting frames. Aside from
865 * reducing interrupts this also permits more concurrency.
866 * The only potential downside is if the tx queue backs
867 * up in which case the top half of the kernel may backup
868 * due to a lack of tx descriptors.
e30eb4ab 869 */
8a63facc
BC		 870 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
871 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
872 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
873 if (qnum < 0) {
874 /*
875 * NB: don't print a message, this happens
876 * normally on parts with too few tx queues
877 */
878 return ERR_PTR(qnum);
879 }
880 if (qnum >= ARRAY_SIZE(sc->txqs)) {
881 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
882 qnum, ARRAY_SIZE(sc->txqs));
883 ath5k_hw_release_tx_queue(ah, qnum);
884 return ERR_PTR(-EINVAL);
885 }
886 txq = &sc->txqs[qnum];
887 if (!txq->setup) {
888 txq->qnum = qnum;
889 txq->link = NULL;
890 INIT_LIST_HEAD(&txq->q);
891 spin_lock_init(&txq->lock);
892 txq->setup = true;
925e0b06 893 txq->txq_len = 0;
4edd761f 894 txq->txq_poll_mark = false;
923e5b3d 895 txq->txq_stuck = 0;
8a63facc
BC		 896 }
897 return &sc->txqs[qnum];
fa1c114f
JS		 898}
899
8a63facc
BC		 900static int
901ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 902{
8a63facc
BC		 903 struct ath5k_txq_info qi = {
904 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
905 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
906 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
907 /* NB: for dynamic turbo, don't enable any other interrupts */
908 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
909 };
d8ee398d 910
8a63facc 911 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 912}
913
8a63facc
BC		 914static int
915ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 916{
917 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 918 struct ath5k_txq_info qi;
919 int ret;
fa1c114f 920
8a63facc
BC		 921 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
922 if (ret)
923 goto err;
fa1c114f 924
8a63facc
BC		 925 if (sc->opmode == NL80211_IFTYPE_AP ||
926 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
927 /*
928 * Always burst out beacon and CAB traffic
929 * (aifs = cwmin = cwmax = 0)
930 */
931 qi.tqi_aifs = 0;
932 qi.tqi_cw_min = 0;
933 qi.tqi_cw_max = 0;
934 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
935 /*
936 * Adhoc mode; backoff between 0 and (2 * cw_min).
937 */
938 qi.tqi_aifs = 0;
939 qi.tqi_cw_min = 0;
940 qi.tqi_cw_max = 2 * ah->ah_cw_min;
941 }
fa1c114f 942
8a63facc
BC		 943 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
944 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
945 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 946
8a63facc
BC		 947 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
948 if (ret) {
949 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
950 "hardware queue!\n", __func__);
951 goto err;
952 }
953 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
954 if (ret)
955 goto err;
b7266047 956
8a63facc
BC		 957 /* reconfigure cabq with ready time to 80% of beacon_interval */
958 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
959 if (ret)
960 goto err;
b7266047 961
8a63facc
BC		 962 qi.tqi_ready_time = (sc->bintval * 80) / 100;
963 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
964 if (ret)
965 goto err;
b7266047 966
8a63facc
BC		 967 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
968err:
969 return ret;
d8ee398d
LR		 970}
971
8a63facc
BC		 972static void
973ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
974{
975 struct ath5k_buf *bf, *bf0;
b6ea0356
BC		 976
977 /*
8a63facc
BC		 978 * NB: this assumes output has been stopped and
979 * we do not need to block ath5k_tx_tasklet
b6ea0356 980 */
8a63facc
BC		 981 spin_lock_bh(&txq->lock);
982 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
983 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 984
8a63facc 985 ath5k_txbuf_free_skb(sc, bf);
b6ea0356 986
8a63facc
BC		 987 spin_lock_bh(&sc->txbuflock);
988 list_move_tail(&bf->list, &sc->txbuf);
989 sc->txbuf_len++;
925e0b06 990 txq->txq_len--;
8a63facc 991 spin_unlock_bh(&sc->txbuflock);
b6ea0356 992 }
8a63facc 993 txq->link = NULL;
4edd761f 994 txq->txq_poll_mark = false;
8a63facc 995 spin_unlock_bh(&txq->lock);
b6ea0356
BC		 996}
997
8a63facc
BC		 998/*
999 * Drain the transmit queues and reclaim resources.
1000 */
1001static void
1002ath5k_txq_cleanup(struct ath5k_softc *sc)
fa1c114f
JS		 1003{
1004 struct ath5k_hw *ah = sc->ah;
8a63facc 1005 unsigned int i;
fa1c114f 1006
8a63facc
BC		 1007 /* XXX return value */
1008 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1009 /* don't touch the hardware if marked invalid */
1010 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1011 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1012 ath5k_hw_get_txdp(ah, sc->bhalq));
1013 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1014 if (sc->txqs[i].setup) {
1015 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1016 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1017 "link %p\n",
1018 sc->txqs[i].qnum,
1019 ath5k_hw_get_txdp(ah,
1020 sc->txqs[i].qnum),
1021 sc->txqs[i].link);
1022 }
0452d4a5 1023 }
fa1c114f 1024
8a63facc
BC		 1025 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1026 if (sc->txqs[i].setup)
1027 ath5k_txq_drainq(sc, &sc->txqs[i]);
fa1c114f
JS		 1028}
1029
8a63facc
BC		 1030static void
1031ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1032{
8a63facc
BC		 1033 struct ath5k_txq *txq = sc->txqs;
1034 unsigned int i;
2ac2927a 1035
8a63facc
BC		 1036 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1037 if (txq->setup) {
1038 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1039 txq->setup = false;
1040 }
1041}
2ac2927a 1042
2ac2927a 1043
8a63facc
BC		 1044/*************\
1045* RX Handling *
1046\*************/
2ac2927a 1047
8a63facc
BC		 1048/*
1049 * Enable the receive h/w following a reset.
1050 */
fa1c114f 1051static int
8a63facc 1052ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1053{
1054 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1055 struct ath_common *common = ath5k_hw_common(ah);
1056 struct ath5k_buf *bf;
1057 int ret;
fa1c114f 1058
8a63facc 1059 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1060
8a63facc
BC		 1061 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1062 common->cachelsz, common->rx_bufsize);
2f7fe870 1063
8a63facc
BC		 1064 spin_lock_bh(&sc->rxbuflock);
1065 sc->rxlink = NULL;
1066 list_for_each_entry(bf, &sc->rxbuf, list) {
1067 ret = ath5k_rxbuf_setup(sc, bf);
1068 if (ret != 0) {
1069 spin_unlock_bh(&sc->rxbuflock);
1070 goto err;
1071 }
2f7fe870 1072 }
8a63facc
BC		 1073 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1074 ath5k_hw_set_rxdp(ah, bf->daddr);
1075 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1076
8a63facc
BC		 1077 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1078 ath5k_mode_setup(sc); /* set filters, etc. */
1079 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1080
1081 return 0;
8a63facc 1082err:
fa1c114f
JS		 1083 return ret;
1084}
1085
8a63facc
BC		 1086/*
1087 * Disable the receive h/w in preparation for a reset.
1088 */
1089static void
1090ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1091{
8a63facc 1092 struct ath5k_hw *ah = sc->ah;
fa1c114f 1093
8a63facc
BC		 1094 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1095 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1096 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f 1097
8a63facc
BC		 1098 ath5k_debug_printrxbuffs(sc, ah);
1099}
fa1c114f 1100
8a63facc
BC		 1101static unsigned int
1102ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1103 struct ath5k_rx_status *rs)
1104{
1105 struct ath5k_hw *ah = sc->ah;
1106 struct ath_common *common = ath5k_hw_common(ah);
1107 struct ieee80211_hdr *hdr = (void *)skb->data;
1108 unsigned int keyix, hlen;
fa1c114f 1109
8a63facc
BC		 1110 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1111 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1112 return RX_FLAG_DECRYPTED;
fa1c114f 1113
8a63facc
BC		 1114 /* Apparently when a default key is used to decrypt the packet
1115 the hw does not set the index used to decrypt. In such cases
1116 get the index from the packet. */
1117 hlen = ieee80211_hdrlen(hdr->frame_control);
1118 if (ieee80211_has_protected(hdr->frame_control) &&
1119 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1120 skb->len >= hlen + 4) {
1121 keyix = skb->data[hlen + 3] >> 6;
1122
1123 if (test_bit(keyix, common->keymap))
1124 return RX_FLAG_DECRYPTED;
1125 }
fa1c114f
JS		 1126
1127 return 0;
fa1c114f
JS		 1128}
1129
8a63facc 1130
fa1c114f 1131static void
8a63facc
BC		 1132ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1133 struct ieee80211_rx_status *rxs)
fa1c114f 1134{
8a63facc
BC		 1135 struct ath_common *common = ath5k_hw_common(sc->ah);
1136 u64 tsf, bc_tstamp;
1137 u32 hw_tu;
1138 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1139
8a63facc
BC		 1140 if (ieee80211_is_beacon(mgmt->frame_control) &&
1141 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1142 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1143 /*
1144 * Received an IBSS beacon with the same BSSID. Hardware *must*
1145 * have updated the local TSF. We have to work around various
1146 * hardware bugs, though...
1147 */
1148 tsf = ath5k_hw_get_tsf64(sc->ah);
1149 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1150 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1151
8a63facc
BC		 1152 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1153 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1154 (unsigned long long)bc_tstamp,
1155 (unsigned long long)rxs->mactime,
1156 (unsigned long long)(rxs->mactime - bc_tstamp),
1157 (unsigned long long)tsf);
fa1c114f 1158
8a63facc
BC		 1159 /*
1160 * Sometimes the HW will give us a wrong tstamp in the rx
1161 * status, causing the timestamp extension to go wrong.
1162 * (This seems to happen especially with beacon frames bigger
1163 * than 78 byte (incl. FCS))
1164 * But we know that the receive timestamp must be later than the
1165 * timestamp of the beacon since HW must have synced to that.
1166 *
1167 * NOTE: here we assume mactime to be after the frame was
1168 * received, not like mac80211 which defines it at the start.
1169 */
1170 if (bc_tstamp > rxs->mactime) {
1171 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1172 "fixing mactime from %llx to %llx\n",
1173 (unsigned long long)rxs->mactime,
1174 (unsigned long long)tsf);
1175 rxs->mactime = tsf;
1176 }
fa1c114f 1177
8a63facc
BC		 1178 /*
1179 * Local TSF might have moved higher than our beacon timers,
1180 * in that case we have to update them to continue sending
1181 * beacons. This also takes care of synchronizing beacon sending
1182 * times with other stations.
1183 */
1184 if (hw_tu >= sc->nexttbtt)
1185 ath5k_beacon_update_timers(sc, bc_tstamp);
1186 }
1187}
fa1c114f 1188
8a63facc
BC		 1189static void
1190ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1191{
1192 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1193 struct ath5k_hw *ah = sc->ah;
1194 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1195
8a63facc
BC		 1196 /* only beacons from our BSSID */
1197 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1198 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1199 return;
fa1c114f 1200
8a63facc
BC		 1201 ah->ah_beacon_rssi_avg = ath5k_moving_average(ah->ah_beacon_rssi_avg,
1202 rssi);
fa1c114f 1203
8a63facc
BC		 1204 /* in IBSS mode we should keep RSSI statistics per neighbour */
1205 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1206}
fa1c114f 1207
8a63facc
BC		 1208/*
1209 * Compute padding position. skb must contain an IEEE 802.11 frame
1210 */
1211static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1212{
8a63facc
BC		 1213 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1214 __le16 frame_control = hdr->frame_control;
1215 int padpos = 24;
fa1c114f 1216
8a63facc
BC		 1217 if (ieee80211_has_a4(frame_control)) {
1218 padpos += ETH_ALEN;
fa1c114f 1219 }
8a63facc
BC		 1220 if (ieee80211_is_data_qos(frame_control)) {
1221 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1222 }
8a63facc
BC		 1223
1224 return padpos;
fa1c114f
JS		 1225}
1226
8a63facc
BC		 1227/*
1228 * This function expects an 802.11 frame and returns the number of
1229 * bytes added, or -1 if we don't have enough header room.
1230 */
1231static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1232{
8a63facc
BC		 1233 int padpos = ath5k_common_padpos(skb);
1234 int padsize = padpos & 3;
fa1c114f 1235
8a63facc 1236 if (padsize && skb->len>padpos) {
fa1c114f 1237
8a63facc
BC		 1238 if (skb_headroom(skb) < padsize)
1239 return -1;
fa1c114f 1240
8a63facc
BC		 1241 skb_push(skb, padsize);
1242 memmove(skb->data, skb->data+padsize, padpos);
1243 return padsize;
1244 }
a951ae21 1245
8a63facc
BC		 1246 return 0;
1247}
fa1c114f 1248
8a63facc
BC		 1249/*
1250 * The MAC header is padded to have 32-bit boundary if the
1251 * packet payload is non-zero. The general calculation for
1252 * padsize would take into account odd header lengths:
1253 * padsize = 4 - (hdrlen & 3); however, since only
1254 * even-length headers are used, padding can only be 0 or 2
1255 * bytes and we can optimize this a bit. We must not try to
1256 * remove padding from short control frames that do not have a
1257 * payload.
1258 *
1259 * This function expects an 802.11 frame and returns the number of
1260 * bytes removed.
1261 */
1262static int ath5k_remove_padding(struct sk_buff *skb)
1263{
1264 int padpos = ath5k_common_padpos(skb);
1265 int padsize = padpos & 3;
6d91e1d8 1266
8a63facc
BC		 1267 if (padsize && skb->len>=padpos+padsize) {
1268 memmove(skb->data + padsize, skb->data, padpos);
1269 skb_pull(skb, padsize);
1270 return padsize;
fa1c114f 1271 }
a951ae21 1272
8a63facc 1273 return 0;
fa1c114f
JS		 1274}
1275
1276static void
8a63facc
BC		 1277ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1278 struct ath5k_rx_status *rs)
fa1c114f 1279{
8a63facc
BC		 1280 struct ieee80211_rx_status *rxs;
1281
1282 ath5k_remove_padding(skb);
1283
1284 rxs = IEEE80211_SKB_RXCB(skb);
1285
1286 rxs->flag = 0;
1287 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1288 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1289
1290 /*
8a63facc
BC		 1291 * always extend the mac timestamp, since this information is
1292 * also needed for proper IBSS merging.
1293 *
1294 * XXX: it might be too late to do it here, since rs_tstamp is
1295 * 15bit only. that means TSF extension has to be done within
1296 * 32768usec (about 32ms). it might be necessary to move this to
1297 * the interrupt handler, like it is done in madwifi.
1298 *
1299 * Unfortunately we don't know when the hardware takes the rx
1300 * timestamp (beginning of phy frame, data frame, end of rx?).
1301 * The only thing we know is that it is hardware specific...
1302 * On AR5213 it seems the rx timestamp is at the end of the
1303 * frame, but i'm not sure.
1304 *
1305 * NOTE: mac80211 defines mactime at the beginning of the first
1306 * data symbol. Since we don't have any time references it's
1307 * impossible to comply to that. This affects IBSS merge only
1308 * right now, so it's not too bad...
fa1c114f 1309 */
8a63facc
BC		 1310 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
1311 rxs->flag |= RX_FLAG_TSFT;
fa1c114f 1312
8a63facc
BC		 1313 rxs->freq = sc->curchan->center_freq;
1314 rxs->band = sc->curband->band;
fa1c114f 1315
8a63facc 1316 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1317
8a63facc 1318 rxs->antenna = rs->rs_antenna;
fa1c114f 1319
8a63facc
BC		 1320 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1321 sc->stats.antenna_rx[rs->rs_antenna]++;
1322 else
1323 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1324
8a63facc
BC		 1325 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1326 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1327
8a63facc
BC		 1328 if (rxs->rate_idx >= 0 && rs->rs_rate ==
1329 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1330 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1331
8a63facc 1332 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
fa1c114f 1333
8a63facc 1334 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1335
8a63facc
BC		 1336 /* check beacons in IBSS mode */
1337 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1338 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1339
8a63facc
BC		 1340 ieee80211_rx(sc->hw, skb);
1341}
fa1c114f 1342
8a63facc
BC		 1343/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1344 *
1345 * Check if we want to further process this frame or not. Also update
1346 * statistics. Return true if we want this frame, false if not.
fa1c114f 1347 */
8a63facc
BC		 1348static bool
1349ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1350{
8a63facc 1351 sc->stats.rx_all_count++;
fa1c114f 1352
8a63facc
BC		 1353 if (unlikely(rs->rs_status)) {
1354 if (rs->rs_status & AR5K_RXERR_CRC)
1355 sc->stats.rxerr_crc++;
1356 if (rs->rs_status & AR5K_RXERR_FIFO)
1357 sc->stats.rxerr_fifo++;
1358 if (rs->rs_status & AR5K_RXERR_PHY) {
1359 sc->stats.rxerr_phy++;
1360 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1361 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1362 return false;
1363 }
1364 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1365 /*
1366 * Decrypt error. If the error occurred
1367 * because there was no hardware key, then
1368 * let the frame through so the upper layers
1369 * can process it. This is necessary for 5210
1370 * parts which have no way to setup a ``clear''
1371 * key cache entry.
1372 *
1373 * XXX do key cache faulting
1374 */
1375 sc->stats.rxerr_decrypt++;
1376 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1377 !(rs->rs_status & AR5K_RXERR_CRC))
1378 return true;
1379 }
1380 if (rs->rs_status & AR5K_RXERR_MIC) {
1381 sc->stats.rxerr_mic++;
1382 return true;
fa1c114f 1383 }
fa1c114f 1384
8a63facc
BC		 1385 /* reject any frames with non-crypto errors */
1386 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1387 return false;
1388 }
fa1c114f 1389
8a63facc
BC		 1390 if (unlikely(rs->rs_more)) {
1391 sc->stats.rxerr_jumbo++;
1392 return false;
1393 }
1394 return true;
fa1c114f
JS		 1395}
1396
fa1c114f 1397static void
8a63facc 1398ath5k_tasklet_rx(unsigned long data)
fa1c114f 1399{
8a63facc
BC		 1400 struct ath5k_rx_status rs = {};
1401 struct sk_buff *skb, *next_skb;
1402 dma_addr_t next_skb_addr;
1403 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1404 struct ath5k_hw *ah = sc->ah;
1405 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1406 struct ath5k_buf *bf;
1407 struct ath5k_desc *ds;
1408 int ret;
fa1c114f 1409
8a63facc
BC		 1410 spin_lock(&sc->rxbuflock);
1411 if (list_empty(&sc->rxbuf)) {
1412 ATH5K_WARN(sc, "empty rx buf pool\n");
1413 goto unlock;
1414 }
1415 do {
1416 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1417 BUG_ON(bf->skb == NULL);
1418 skb = bf->skb;
1419 ds = bf->desc;
fa1c114f 1420
8a63facc
BC		 1421 /* bail if HW is still using self-linked descriptor */
1422 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1423 break;
fa1c114f 1424
8a63facc
BC		 1425 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1426 if (unlikely(ret == -EINPROGRESS))
1427 break;
1428 else if (unlikely(ret)) {
1429 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1430 sc->stats.rxerr_proc++;
1431 break;
1432 }
fa1c114f 1433
8a63facc
BC		 1434 if (ath5k_receive_frame_ok(sc, &rs)) {
1435 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1436
8a63facc
BC		 1437 /*
1438 * If we can't replace bf->skb with a new skb under
1439 * memory pressure, just skip this packet
1440 */
1441 if (!next_skb)
1442 goto next;
036cd1ec 1443
8a63facc
BC		 1444 pci_unmap_single(sc->pdev, bf->skbaddr,
1445 common->rx_bufsize,
1446 PCI_DMA_FROMDEVICE);
036cd1ec 1447
8a63facc 1448 skb_put(skb, rs.rs_datalen);
6ba81c2c 1449
8a63facc 1450 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1451
8a63facc
BC		 1452 bf->skb = next_skb;
1453 bf->skbaddr = next_skb_addr;
036cd1ec 1454 }
8a63facc
BC		 1455next:
1456 list_move_tail(&bf->list, &sc->rxbuf);
1457 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1458unlock:
1459 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1460}
1461
b4ea449d 1462
8a63facc
BC		 1463/*************\
1464* TX Handling *
1465\*************/
b4ea449d 1466
8a63facc
BC		 1467static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1468 struct ath5k_txq *txq)
1469{
1470 struct ath5k_softc *sc = hw->priv;
1471 struct ath5k_buf *bf;
1472 unsigned long flags;
1473 int padsize;
b4ea449d 1474
8a63facc 1475 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
b4ea449d 1476
8a63facc
BC		 1477 /*
1478 * The hardware expects the header padded to 4 byte boundaries.
1479 * If this is not the case, we add the padding after the header.
1480 */
1481 padsize = ath5k_add_padding(skb);
1482 if (padsize < 0) {
1483 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1484 " headroom to pad");
1485 goto drop_packet;
1486 }
8127fbdc 1487
925e0b06
BR		 1488 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1489 ieee80211_stop_queue(hw, txq->qnum);
1490
8a63facc
BC		 1491 spin_lock_irqsave(&sc->txbuflock, flags);
1492 if (list_empty(&sc->txbuf)) {
1493 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1494 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1495 ieee80211_stop_queues(hw);
8a63facc 1496 goto drop_packet;
8127fbdc 1497 }
8a63facc
BC		 1498 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1499 list_del(&bf->list);
1500 sc->txbuf_len--;
1501 if (list_empty(&sc->txbuf))
1502 ieee80211_stop_queues(hw);
1503 spin_unlock_irqrestore(&sc->txbuflock, flags);
1504
1505 bf->skb = skb;
1506
1507 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1508 bf->skb = NULL;
1509 spin_lock_irqsave(&sc->txbuflock, flags);
1510 list_add_tail(&bf->list, &sc->txbuf);
1511 sc->txbuf_len++;
1512 spin_unlock_irqrestore(&sc->txbuflock, flags);
1513 goto drop_packet;
8127fbdc 1514 }
8a63facc 1515 return NETDEV_TX_OK;
8127fbdc 1516
8a63facc
BC		 1517drop_packet:
1518 dev_kfree_skb_any(skb);
1519 return NETDEV_TX_OK;
8127fbdc
BP		 1520}
1521
1440401e
BR		 1522static void
1523ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
1524 struct ath5k_tx_status *ts)
1525{
1526 struct ieee80211_tx_info *info;
1527 int i;
1528
1529 sc->stats.tx_all_count++;
1530 info = IEEE80211_SKB_CB(skb);
1531
1532 ieee80211_tx_info_clear_status(info);
1533 for (i = 0; i < 4; i++) {
1534 struct ieee80211_tx_rate *r =
1535 &info->status.rates[i];
1536
1537 if (ts->ts_rate[i]) {
1538 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1539 r->count = ts->ts_retry[i];
1540 } else {
1541 r->idx = -1;
1542 r->count = 0;
1543 }
1544 }
1545
1546 /* count the successful attempt as well */
1547 info->status.rates[ts->ts_final_idx].count++;
1548
1549 if (unlikely(ts->ts_status)) {
1550 sc->stats.ack_fail++;
1551 if (ts->ts_status & AR5K_TXERR_FILT) {
1552 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1553 sc->stats.txerr_filt++;
1554 }
1555 if (ts->ts_status & AR5K_TXERR_XRETRY)
1556 sc->stats.txerr_retry++;
1557 if (ts->ts_status & AR5K_TXERR_FIFO)
1558 sc->stats.txerr_fifo++;
1559 } else {
1560 info->flags |= IEEE80211_TX_STAT_ACK;
1561 info->status.ack_signal = ts->ts_rssi;
1562 }
1563
1564 /*
1565 * Remove MAC header padding before giving the frame
1566 * back to mac80211.
1567 */
1568 ath5k_remove_padding(skb);
1569
1570 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1571 sc->stats.antenna_tx[ts->ts_antenna]++;
1572 else
1573 sc->stats.antenna_tx[0]++; /* invalid */
1574
1575 ieee80211_tx_status(sc->hw, skb);
1576}
8a63facc
BC		 1577
1578static void
1579ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1580{
8a63facc
BC		 1581 struct ath5k_tx_status ts = {};
1582 struct ath5k_buf *bf, *bf0;
1583 struct ath5k_desc *ds;
1584 struct sk_buff *skb;
1440401e 1585 int ret;
8127fbdc 1586
8a63facc
BC		 1587 spin_lock(&txq->lock);
1588 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1589 ds = bf->desc;
8127fbdc 1590
8a63facc
BC		 1591 /*
1592 * It's possible that the hardware can say the buffer is
1593 * completed when it hasn't yet loaded the ds_link from
1594 * host memory and moved on. If there are more TX
1595 * descriptors in the queue, wait for TXDP to change
1596 * before processing this one.
1597 */
1598 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) == bf->daddr &&
1599 !list_is_last(&bf->list, &txq->q))
1600 break;
8a63facc
BC		 1601 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1602 if (unlikely(ret == -EINPROGRESS))
1603 break;
1604 else if (unlikely(ret)) {
1605 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1606 ret, txq->qnum);
1607 break;
1608 }
8127fbdc 1609
8a63facc 1610 skb = bf->skb;
8a63facc 1611 bf->skb = NULL;
fa1c114f
JS		 1612 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1613 PCI_DMA_TODEVICE);
1614
1440401e 1615 ath5k_tx_frame_completed(sc, skb, &ts);
fa1c114f
JS		 1616
1617 spin_lock(&sc->txbuflock);
fa1c114f
JS		 1618 list_move_tail(&bf->list, &sc->txbuf);
1619 sc->txbuf_len++;
925e0b06 1620 txq->txq_len--;
fa1c114f 1621 spin_unlock(&sc->txbuflock);
4edd761f
BR		 1622
1623 txq->txq_poll_mark = false;
fa1c114f
JS		 1624 }
1625 if (likely(list_empty(&txq->q)))
1626 txq->link = NULL;
1627 spin_unlock(&txq->lock);
925e0b06
BR		 1628 if (txq->txq_len < ATH5K_TXQ_LEN_LOW)
1629 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1630}
1631
1632static void
1633ath5k_tasklet_tx(unsigned long data)
1634{
8784d2ee 1635 int i;
fa1c114f
JS		 1636 struct ath5k_softc *sc = (void *)data;
1637
8784d2ee
BC		 1638 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1639 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1640 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1641}
1642
1643
fa1c114f
JS		 1644/*****************\
1645* Beacon handling *
1646\*****************/
1647
1648/*
1649 * Setup the beacon frame for transmit.
1650 */
1651static int
e039fa4a 1652ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1653{
1654 struct sk_buff *skb = bf->skb;
a888d52d 1655 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1656 struct ath5k_hw *ah = sc->ah;
1657 struct ath5k_desc *ds;
2bed03eb
NK		 1658 int ret = 0;
1659 u8 antenna;
fa1c114f 1660 u32 flags;
8127fbdc 1661 const int padsize = 0;
fa1c114f
JS		 1662
1663 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1664 PCI_DMA_TODEVICE);
1665 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1666 "skbaddr %llx\n", skb, skb->data, skb->len,
1667 (unsigned long long)bf->skbaddr);
8d8bb39b 1668 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 1669 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1670 return -EIO;
1671 }
1672
1673 ds = bf->desc;
2bed03eb 1674 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1675
1676 flags = AR5K_TXDESC_NOACK;
05c914fe 1677 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1678 ds->ds_link = bf->daddr; /* self-linked */
1679 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1680 } else
fa1c114f 1681 ds->ds_link = 0;
2bed03eb
NK		 1682
1683 /*
1684 * If we use multiple antennas on AP and use
1685 * the Sectored AP scenario, switch antenna every
1686 * 4 beacons to make sure everybody hears our AP.
1687 * When a client tries to associate, hw will keep
1688 * track of the tx antenna to be used for this client
1689 * automaticaly, based on ACKed packets.
1690 *
1691 * Note: AP still listens and transmits RTS on the
1692 * default antenna which is supposed to be an omni.
1693 *
1694 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1695 * multiple antennas (1 omni -- the default -- and 14
1696 * sectors), so if we choose to actually support this
1697 * mode, we need to allow the user to set how many antennas
1698 * we have and tweak the code below to send beacons
1699 * on all of them.
2bed03eb
NK		 1700 */
1701 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1702 antenna = sc->bsent & 4 ? 2 : 1;
1703
fa1c114f 1704
8f655dde
NK		 1705 /* FIXME: If we are in g mode and rate is a CCK rate
1706 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1707 * from tx power (value is in dB units already) */
fa1c114f 1708 ds->ds_data = bf->skbaddr;
281c56dd 1709 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1710 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1711 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1712 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1713 1, AR5K_TXKEYIX_INVALID,
400ec45a 1714 antenna, flags, 0, 0);
fa1c114f
JS		 1715 if (ret)
1716 goto err_unmap;
1717
1718 return 0;
1719err_unmap:
1720 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1721 return ret;
1722}
1723
8a63facc
BC		 1724/*
1725 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1726 * this is called only once at config_bss time, for AP we do it every
1727 * SWBA interrupt so that the TIM will reflect buffered frames.
1728 *
1729 * Called with the beacon lock.
1730 */
1731static int
1732ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1733{
1734 int ret;
1735 struct ath5k_softc *sc = hw->priv;
1736 struct sk_buff *skb;
1737
1738 if (WARN_ON(!vif)) {
1739 ret = -EINVAL;
1740 goto out;
1741 }
1742
1743 skb = ieee80211_beacon_get(hw, vif);
1744
1745 if (!skb) {
1746 ret = -ENOMEM;
1747 goto out;
1748 }
1749
1750 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
1751
1752 ath5k_txbuf_free_skb(sc, sc->bbuf);
1753 sc->bbuf->skb = skb;
1754 ret = ath5k_beacon_setup(sc, sc->bbuf);
1755 if (ret)
1756 sc->bbuf->skb = NULL;
1757out:
1758 return ret;
1759}
1760
fa1c114f
JS		 1761/*
1762 * Transmit a beacon frame at SWBA. Dynamic updates to the
1763 * frame contents are done as needed and the slot time is
1764 * also adjusted based on current state.
1765 *
5faaff74
BC		 1766 * This is called from software irq context (beacontq tasklets)
1767 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1768 */
1769static void
1770ath5k_beacon_send(struct ath5k_softc *sc)
1771{
1772 struct ath5k_buf *bf = sc->bbuf;
1773 struct ath5k_hw *ah = sc->ah;
cec8db23 1774 struct sk_buff *skb;
fa1c114f 1775
be9b7259 1776 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1777
4afd89d9 1778 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION)) {
fa1c114f
JS		 1779 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1780 return;
1781 }
1782 /*
1783 * Check if the previous beacon has gone out. If
a180a130 1784 * not, don't don't try to post another: skip this
fa1c114f
JS		 1785 * period and wait for the next. Missed beacons
1786 * indicate a problem and should not occur. If we
1787 * miss too many consecutive beacons reset the device.
1788 */
1789 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1790 sc->bmisscount++;
be9b7259 1791 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1792 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1793 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1794 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1795 "stuck beacon time (%u missed)\n",
1796 sc->bmisscount);
8d67a031
BR		 1797 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1798 "stuck beacon, resetting\n");
5faaff74 1799 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1800 }
1801 return;
1802 }
1803 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1804 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1805 "resume beacon xmit after %u misses\n",
1806 sc->bmisscount);
1807 sc->bmisscount = 0;
1808 }
1809
1810 /*
1811 * Stop any current dma and put the new frame on the queue.
1812 * This should never fail since we check above that no frames
1813 * are still pending on the queue.
1814 */
1815 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 1816 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1817 /* NB: hw still stops DMA, so proceed */
1818 }
fa1c114f 1819
1071db86
BC		 1820 /* refresh the beacon for AP mode */
1821 if (sc->opmode == NL80211_IFTYPE_AP)
1822 ath5k_beacon_update(sc->hw, sc->vif);
1823
c6e387a2
NK		 1824 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1825 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1826 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1827 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1828
cec8db23
BC		 1829 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1830 while (skb) {
1831 ath5k_tx_queue(sc->hw, skb, sc->cabq);
1832 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
1833 }
1834
fa1c114f
JS		 1835 sc->bsent++;
1836}
1837
9804b98d
BR		 1838/**
1839 * ath5k_beacon_update_timers - update beacon timers
1840 *
1841 * @sc: struct ath5k_softc pointer we are operating on
1842 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1843 * beacon timer update based on the current HW TSF.
1844 *
1845 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1846 * of a received beacon or the current local hardware TSF and write it to the
1847 * beacon timer registers.
1848 *
1849 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1850 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1851 * when we otherwise know we have to update the timers, but we keep it in this
1852 * function to have it all together in one place.
1853 */
fa1c114f 1854static void
9804b98d 1855ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1856{
1857 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1858 u32 nexttbtt, intval, hw_tu, bc_tu;
1859 u64 hw_tsf;
fa1c114f
JS		 1860
1861 intval = sc->bintval & AR5K_BEACON_PERIOD;
1862 if (WARN_ON(!intval))
1863 return;
1864
9804b98d
BR		 1865 /* beacon TSF converted to TU */
1866 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1867
9804b98d
BR		 1868 /* current TSF converted to TU */
1869 hw_tsf = ath5k_hw_get_tsf64(ah);
1870 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1871
9804b98d
BR		 1872#define FUDGE 3
1873 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
1874 if (bc_tsf == -1) {
1875 /*
1876 * no beacons received, called internally.
1877 * just need to refresh timers based on HW TSF.
1878 */
1879 nexttbtt = roundup(hw_tu + FUDGE, intval);
1880 } else if (bc_tsf == 0) {
1881 /*
1882 * no beacon received, probably called by ath5k_reset_tsf().
1883 * reset TSF to start with 0.
1884 */
1885 nexttbtt = intval;
1886 intval |= AR5K_BEACON_RESET_TSF;
1887 } else if (bc_tsf > hw_tsf) {
1888 /*
1889 * beacon received, SW merge happend but HW TSF not yet updated.
1890 * not possible to reconfigure timers yet, but next time we
1891 * receive a beacon with the same BSSID, the hardware will
1892 * automatically update the TSF and then we need to reconfigure
1893 * the timers.
1894 */
1895 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1896 "need to wait for HW TSF sync\n");
1897 return;
1898 } else {
1899 /*
1900 * most important case for beacon synchronization between STA.
1901 *
1902 * beacon received and HW TSF has been already updated by HW.
1903 * update next TBTT based on the TSF of the beacon, but make
1904 * sure it is ahead of our local TSF timer.
1905 */
1906 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1907 }
1908#undef FUDGE
fa1c114f 1909
036cd1ec
BR		 1910 sc->nexttbtt = nexttbtt;
1911
fa1c114f 1912 intval |= AR5K_BEACON_ENA;
fa1c114f 1913 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 1914
1915 /*
1916 * debugging output last in order to preserve the time critical aspect
1917 * of this function
1918 */
1919 if (bc_tsf == -1)
1920 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1921 "reconfigured timers based on HW TSF\n");
1922 else if (bc_tsf == 0)
1923 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1924 "reset HW TSF and timers\n");
1925 else
1926 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1927 "updated timers based on beacon TSF\n");
1928
1929 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 1930 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
1931 (unsigned long long) bc_tsf,
1932 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 1933 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
1934 intval & AR5K_BEACON_PERIOD,
1935 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
1936 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 1937}
1938
036cd1ec
BR		 1939/**
1940 * ath5k_beacon_config - Configure the beacon queues and interrupts
1941 *
1942 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 1943 *
036cd1ec 1944 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 1945 * interrupts to detect TSF updates only.
fa1c114f
JS		 1946 */
1947static void
1948ath5k_beacon_config(struct ath5k_softc *sc)
1949{
1950 struct ath5k_hw *ah = sc->ah;
b5f03956 1951 unsigned long flags;
fa1c114f 1952
21800491 1953 spin_lock_irqsave(&sc->block, flags);
fa1c114f 1954 sc->bmisscount = 0;
dc1968e7 1955 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 1956
21800491 1957 if (sc->enable_beacon) {
fa1c114f 1958 /*
036cd1ec
BR		 1959 * In IBSS mode we use a self-linked tx descriptor and let the
1960 * hardware send the beacons automatically. We have to load it
fa1c114f 1961 * only once here.
036cd1ec 1962 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 1963 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 1964 */
1965 ath5k_beaconq_config(sc);
fa1c114f 1966
036cd1ec
BR		 1967 sc->imask |= AR5K_INT_SWBA;
1968
da966bca 1969 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 1970 if (ath5k_hw_hasveol(ah))
da966bca 1971 ath5k_beacon_send(sc);
da966bca
JS		 1972 } else
1973 ath5k_beacon_update_timers(sc, -1);
21800491
BC		 1974 } else {
1975 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
fa1c114f 1976 }
fa1c114f 1977
c6e387a2 1978 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 1979 mmiowb();
1980 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 1981}
1982
428cbd4f
NK		 1983static void ath5k_tasklet_beacon(unsigned long data)
1984{
1985 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1986
1987 /*
1988 * Software beacon alert--time to send a beacon.
1989 *
1990 * In IBSS mode we use this interrupt just to
1991 * keep track of the next TBTT (target beacon
1992 * transmission time) in order to detect wether
1993 * automatic TSF updates happened.
1994 */
1995 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1996 /* XXX: only if VEOL suppported */
1997 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1998 sc->nexttbtt += sc->bintval;
1999 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2000 "SWBA nexttbtt: %x hw_tu: %x "
2001 "TSF: %llx\n",
2002 sc->nexttbtt,
2003 TSF_TO_TU(tsf),
2004 (unsigned long long) tsf);
2005 } else {
2006 spin_lock(&sc->block);
2007 ath5k_beacon_send(sc);
2008 spin_unlock(&sc->block);
2009 }
2010}
2011
fa1c114f
JS		 2012
2013/********************\
2014* Interrupt handling *
2015\********************/
2016
6a8a3f6b
BR		 2017static void
2018ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2019{
2111ac0d
BR		 2020 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2021 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2022 /* run ANI only when full calibration is not active */
2023 ah->ah_cal_next_ani = jiffies +
2024 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2025 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2026
2027 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2028 ah->ah_cal_next_full = jiffies +
2029 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2030 tasklet_schedule(&ah->ah_sc->calib);
2031 }
2032 /* we could use SWI to generate enough interrupts to meet our
2033 * calibration interval requirements, if necessary:
2034 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2035}
2036
fa1c114f
JS		 2037static irqreturn_t
2038ath5k_intr(int irq, void *dev_id)
2039{
2040 struct ath5k_softc *sc = dev_id;
2041 struct ath5k_hw *ah = sc->ah;
2042 enum ath5k_int status;
2043 unsigned int counter = 1000;
2044
2045 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2046 !ath5k_hw_is_intr_pending(ah)))
2047 return IRQ_NONE;
2048
2049 do {
fa1c114f
JS		 2050 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2051 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2052 status, sc->imask);
fa1c114f
JS		 2053 if (unlikely(status & AR5K_INT_FATAL)) {
2054 /*
2055 * Fatal errors are unrecoverable.
2056 * Typically these are caused by DMA errors.
2057 */
8d67a031
BR		 2058 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2059 "fatal int, resetting\n");
5faaff74 2060 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2061 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2062 /*
2063 * Receive buffers are full. Either the bus is busy or
2064 * the CPU is not fast enough to process all received
2065 * frames.
2066 * Older chipsets need a reset to come out of this
2067 * condition, but we treat it as RX for newer chips.
2068 * We don't know exactly which versions need a reset -
2069 * this guess is copied from the HAL.
2070 */
2071 sc->stats.rxorn_intr++;
8d67a031
BR		 2072 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2073 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2074 "rx overrun, resetting\n");
5faaff74 2075 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2076 }
87d77c4e
BR		 2077 else
2078 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2079 } else {
2080 if (status & AR5K_INT_SWBA) {
56d2ac76 2081 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2082 }
2083 if (status & AR5K_INT_RXEOL) {
2084 /*
2085 * NB: the hardware should re-read the link when
2086 * RXE bit is written, but it doesn't work at
2087 * least on older hardware revs.
2088 */
b3f194e5 2089 sc->stats.rxeol_intr++;
fa1c114f
JS		 2090 }
2091 if (status & AR5K_INT_TXURN) {
2092 /* bump tx trigger level */
2093 ath5k_hw_update_tx_triglevel(ah, true);
2094 }
4c674c60 2095 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2096 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2097 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2098 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2099 tasklet_schedule(&sc->txtq);
2100 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2101 /* TODO */
fa1c114f
JS		 2102 }
2103 if (status & AR5K_INT_MIB) {
2111ac0d 2104 sc->stats.mib_intr++;
495391d7 2105 ath5k_hw_update_mib_counters(ah);
2111ac0d 2106 ath5k_ani_mib_intr(ah);
fa1c114f 2107 }
e6a3b616 2108 if (status & AR5K_INT_GPIO)
e6a3b616 2109 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2110
fa1c114f 2111 }
2516baa6 2112 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2113
2114 if (unlikely(!counter))
2115 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2116
6a8a3f6b 2117 ath5k_intr_calibration_poll(ah);
6e220662 2118
fa1c114f
JS		 2119 return IRQ_HANDLED;
2120}
2121
fa1c114f
JS		 2122/*
2123 * Periodically recalibrate the PHY to account
2124 * for temperature/environment changes.
2125 */
2126static void
6e220662 2127ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2128{
2129 struct ath5k_softc *sc = (void *)data;
2130 struct ath5k_hw *ah = sc->ah;
2131
6e220662 2132 /* Only full calibration for now */
e65e1d77 2133 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2134
fa1c114f 2135 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2136 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2137 sc->curchan->hw_value);
fa1c114f 2138
6f3b414a 2139 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2140 /*
2141 * Rfgain is out of bounds, reset the chip
2142 * to load new gain values.
2143 */
2144 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2145 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2146 }
2147 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2148 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2149 ieee80211_frequency_to_channel(
2150 sc->curchan->center_freq));
fa1c114f 2151
0e8e02dd 2152 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2153 * doesn't.
2154 * TODO: We should stop TX here, so that it doesn't interfere.
2155 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2156 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2157 ah->ah_cal_next_nf = jiffies +
2158 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2159 ath5k_hw_update_noise_floor(ah);
afe86286 2160 }
6e220662 2161
e65e1d77 2162 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2163}
2164
2165
2111ac0d
BR		 2166static void
2167ath5k_tasklet_ani(unsigned long data)
2168{
2169 struct ath5k_softc *sc = (void *)data;
2170 struct ath5k_hw *ah = sc->ah;
2171
2172 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2173 ath5k_ani_calibration(ah);
2174 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2175}
2176
2177
4edd761f
BR		 2178static void
2179ath5k_tx_complete_poll_work(struct work_struct *work)
2180{
2181 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2182 tx_complete_work.work);
2183 struct ath5k_txq *txq;
2184 int i;
2185 bool needreset = false;
2186
2187 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2188 if (sc->txqs[i].setup) {
2189 txq = &sc->txqs[i];
2190 spin_lock_bh(&txq->lock);
2191 if (txq->txq_len > 0) {
2192 if (txq->txq_poll_mark) {
2193 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2194 "TX queue stuck %d\n",
2195 txq->qnum);
2196 needreset = true;
923e5b3d 2197 txq->txq_stuck++;
4edd761f
BR		 2198 spin_unlock_bh(&txq->lock);
2199 break;
2200 } else {
2201 txq->txq_poll_mark = true;
2202 }
2203 }
2204 spin_unlock_bh(&txq->lock);
2205 }
2206 }
2207
2208 if (needreset) {
2209 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2210 "TX queues stuck, resetting\n");
2211 ath5k_reset(sc, sc->curchan);
2212 }
2213
2214 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2215 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2216}
2217
2218
8a63facc
BC		 2219/*************************\
2220* Initialization routines *
2221\*************************/
fa1c114f
JS		 2222
2223static int
8a63facc 2224ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2225{
8a63facc 2226 struct ath5k_hw *ah = sc->ah;
cec8db23 2227
8a63facc
BC		 2228 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2229 test_bit(ATH_STAT_INVALID, sc->status));
2230
2231 /*
2232 * Shutdown the hardware and driver:
2233 * stop output from above
2234 * disable interrupts
2235 * turn off timers
2236 * turn off the radio
2237 * clear transmit machinery
2238 * clear receive machinery
2239 * drain and release tx queues
2240 * reclaim beacon resources
2241 * power down hardware
2242 *
2243 * Note that some of this work is not possible if the
2244 * hardware is gone (invalid).
2245 */
2246 ieee80211_stop_queues(sc->hw);
2247
2248 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2249 ath5k_led_off(sc);
2250 ath5k_hw_set_imr(ah, 0);
2251 synchronize_irq(sc->pdev->irq);
2252 }
2253 ath5k_txq_cleanup(sc);
2254 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2255 ath5k_rx_stop(sc);
2256 ath5k_hw_phy_disable(ah);
2257 }
2258
2259 return 0;
cec8db23
BC		 2260}
2261
8a63facc
BC		 2262static int
2263ath5k_init(struct ath5k_softc *sc)
fa1c114f 2264{
8a63facc
BC		 2265 struct ath5k_hw *ah = sc->ah;
2266 struct ath_common *common = ath5k_hw_common(ah);
2267 int ret, i;
fa1c114f 2268
8a63facc
BC		 2269 mutex_lock(&sc->lock);
2270
2271 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2272
fa1c114f 2273 /*
8a63facc
BC		 2274 * Stop anything previously setup. This is safe
2275 * no matter this is the first time through or not.
fa1c114f 2276 */
8a63facc 2277 ath5k_stop_locked(sc);
fa1c114f 2278
8a63facc
BC		 2279 /*
2280 * The basic interface to setting the hardware in a good
2281 * state is ``reset''. On return the hardware is known to
2282 * be powered up and with interrupts disabled. This must
2283 * be followed by initialization of the appropriate bits
2284 * and then setup of the interrupt mask.
2285 */
2286 sc->curchan = sc->hw->conf.channel;
2287 sc->curband = &sc->sbands[sc->curchan->band];
2288 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2289 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2290 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2291
8a63facc
BC		 2292 ret = ath5k_reset(sc, NULL);
2293 if (ret)
2294 goto done;
fa1c114f 2295
8a63facc
BC		 2296 ath5k_rfkill_hw_start(ah);
2297
2298 /*
2299 * Reset the key cache since some parts do not reset the
2300 * contents on initial power up or resume from suspend.
2301 */
2302 for (i = 0; i < common->keymax; i++)
2303 ath_hw_keyreset(common, (u16) i);
2304
2305 ath5k_hw_set_ack_bitrate_high(ah, true);
2306 ret = 0;
2307done:
2308 mmiowb();
2309 mutex_unlock(&sc->lock);
4edd761f
BR		 2310
2311 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2312 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2313
8a63facc
BC		 2314 return ret;
2315}
2316
2317static void stop_tasklets(struct ath5k_softc *sc)
2318{
2319 tasklet_kill(&sc->rxtq);
2320 tasklet_kill(&sc->txtq);
2321 tasklet_kill(&sc->calib);
2322 tasklet_kill(&sc->beacontq);
2323 tasklet_kill(&sc->ani_tasklet);
2324}
2325
2326/*
2327 * Stop the device, grabbing the top-level lock to protect
2328 * against concurrent entry through ath5k_init (which can happen
2329 * if another thread does a system call and the thread doing the
2330 * stop is preempted).
2331 */
2332static int
2333ath5k_stop_hw(struct ath5k_softc *sc)
2334{
2335 int ret;
2336
2337 mutex_lock(&sc->lock);
2338 ret = ath5k_stop_locked(sc);
2339 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2340 /*
2341 * Don't set the card in full sleep mode!
2342 *
2343 * a) When the device is in this state it must be carefully
2344 * woken up or references to registers in the PCI clock
2345 * domain may freeze the bus (and system). This varies
2346 * by chip and is mostly an issue with newer parts
2347 * (madwifi sources mentioned srev >= 0x78) that go to
2348 * sleep more quickly.
2349 *
2350 * b) On older chips full sleep results a weird behaviour
2351 * during wakeup. I tested various cards with srev < 0x78
2352 * and they don't wake up after module reload, a second
2353 * module reload is needed to bring the card up again.
2354 *
2355 * Until we figure out what's going on don't enable
2356 * full chip reset on any chip (this is what Legacy HAL
2357 * and Sam's HAL do anyway). Instead Perform a full reset
2358 * on the device (same as initial state after attach) and
2359 * leave it idle (keep MAC/BB on warm reset) */
2360 ret = ath5k_hw_on_hold(sc->ah);
2361
2362 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2363 "putting device to sleep\n");
fa1c114f 2364 }
8a63facc 2365 ath5k_txbuf_free_skb(sc, sc->bbuf);
fa1c114f 2366
8a63facc
BC		 2367 mmiowb();
2368 mutex_unlock(&sc->lock);
2369
2370 stop_tasklets(sc);
2371
4edd761f
BR		 2372 cancel_delayed_work_sync(&sc->tx_complete_work);
2373
8a63facc
BC		 2374 ath5k_rfkill_hw_stop(sc->ah);
2375
2376 return ret;
fa1c114f
JS		 2377}
2378
209d889b
BC		 2379/*
2380 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2381 * and change to the given channel.
5faaff74
BC		 2382 *
2383 * This should be called with sc->lock.
209d889b 2384 */
fa1c114f 2385static int
209d889b 2386ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2387{
fa1c114f
JS		 2388 struct ath5k_hw *ah = sc->ah;
2389 int ret;
2390
2391 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2392
450464de
BC		 2393 ath5k_hw_set_imr(ah, 0);
2394 synchronize_irq(sc->pdev->irq);
2395 stop_tasklets(sc);
2396
209d889b 2397 if (chan) {
d7dc1003
JS		 2398 ath5k_txq_cleanup(sc);
2399 ath5k_rx_stop(sc);
209d889b
BC		 2400
2401 sc->curchan = chan;
2402 sc->curband = &sc->sbands[chan->band];
d7dc1003 2403 }
3355443a 2404 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
d7dc1003 2405 if (ret) {
fa1c114f
JS		 2406 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2407 goto err;
2408 }
d7dc1003 2409
fa1c114f 2410 ret = ath5k_rx_start(sc);
d7dc1003 2411 if (ret) {
fa1c114f
JS		 2412 ATH5K_ERR(sc, "can't start recv logic\n");
2413 goto err;
2414 }
d7dc1003 2415
2111ac0d
BR		 2416 ath5k_ani_init(ah, ah->ah_sc->ani_state.ani_mode);
2417
ac559526
BR		 2418 ah->ah_cal_next_full = jiffies;
2419 ah->ah_cal_next_ani = jiffies;
afe86286
BR		 2420 ah->ah_cal_next_nf = jiffies;
2421
fa1c114f 2422 /*
d7dc1003
JS		 2423 * Change channels and update the h/w rate map if we're switching;
2424 * e.g. 11a to 11b/g.
2425 *
2426 * We may be doing a reset in response to an ioctl that changes the
2427 * channel so update any state that might change as a result.
fa1c114f
JS		 2428 *
2429 * XXX needed?
2430 */
2431/* ath5k_chan_change(sc, c); */
fa1c114f 2432
d7dc1003
JS		 2433 ath5k_beacon_config(sc);
2434 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2435
397f385b
BR		 2436 ieee80211_wake_queues(sc->hw);
2437
fa1c114f
JS		 2438 return 0;
2439err:
2440 return ret;
2441}
2442
5faaff74
BC		 2443static void ath5k_reset_work(struct work_struct *work)
2444{
2445 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2446 reset_work);
2447
2448 mutex_lock(&sc->lock);
2449 ath5k_reset(sc, sc->curchan);
2450 mutex_unlock(&sc->lock);
2451}
2452
8a63facc
BC		 2453static int
2454ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
fa1c114f
JS		 2455{
2456 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2457 struct ath5k_hw *ah = sc->ah;
2458 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2459 struct ath5k_txq *txq;
8a63facc 2460 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2461 int ret;
2462
8a63facc 2463 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
fa1c114f 2464
8a63facc
BC		 2465 /*
2466 * Check if the MAC has multi-rate retry support.
2467 * We do this by trying to setup a fake extended
2468 * descriptor. MACs that don't have support will
2469 * return false w/o doing anything. MACs that do
2470 * support it will return true w/o doing anything.
2471 */
2472 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2473
8a63facc
BC		 2474 if (ret < 0)
2475 goto err;
2476 if (ret > 0)
2477 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2478
8a63facc
BC		 2479 /*
2480 * Collect the channel list. The 802.11 layer
2481 * is resposible for filtering this list based
2482 * on settings like the phy mode and regulatory
2483 * domain restrictions.
2484 */
2485 ret = ath5k_setup_bands(hw);
2486 if (ret) {
2487 ATH5K_ERR(sc, "can't get channels\n");
2488 goto err;
2489 }
67d2e2df 2490
8a63facc
BC		 2491 /* NB: setup here so ath5k_rate_update is happy */
2492 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
2493 ath5k_setcurmode(sc, AR5K_MODE_11A);
2494 else
2495 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f 2496
8a63facc
BC		 2497 /*
2498 * Allocate tx+rx descriptors and populate the lists.
2499 */
2500 ret = ath5k_desc_alloc(sc, pdev);
2501 if (ret) {
2502 ATH5K_ERR(sc, "can't allocate descriptors\n");
2503 goto err;
2504 }
fa1c114f 2505
8a63facc
BC		 2506 /*
2507 * Allocate hardware transmit queues: one queue for
2508 * beacon frames and one data queue for each QoS
2509 * priority. Note that hw functions handle resetting
2510 * these queues at the needed time.
2511 */
2512 ret = ath5k_beaconq_setup(ah);
2513 if (ret < 0) {
2514 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2515 goto err_desc;
2516 }
2517 sc->bhalq = ret;
2518 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2519 if (IS_ERR(sc->cabq)) {
2520 ATH5K_ERR(sc, "can't setup cab queue\n");
2521 ret = PTR_ERR(sc->cabq);
2522 goto err_bhal;
2523 }
fa1c114f 2524
925e0b06
BR		 2525 /* This order matches mac80211's queue priority, so we can
2526 * directly use the mac80211 queue number without any mapping */
2527 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2528 if (IS_ERR(txq)) {
2529 ATH5K_ERR(sc, "can't setup xmit queue\n");
2530 ret = PTR_ERR(txq);
2531 goto err_queues;
2532 }
2533 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2534 if (IS_ERR(txq)) {
8a63facc 2535 ATH5K_ERR(sc, "can't setup xmit queue\n");
925e0b06 2536 ret = PTR_ERR(txq);
8a63facc
BC		 2537 goto err_queues;
2538 }
925e0b06
BR		 2539 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2540 if (IS_ERR(txq)) {
2541 ATH5K_ERR(sc, "can't setup xmit queue\n");
2542 ret = PTR_ERR(txq);
2543 goto err_queues;
2544 }
2545 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2546 if (IS_ERR(txq)) {
2547 ATH5K_ERR(sc, "can't setup xmit queue\n");
2548 ret = PTR_ERR(txq);
2549 goto err_queues;
2550 }
2551 hw->queues = 4;
fa1c114f 2552
8a63facc
BC		 2553 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2554 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2555 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2556 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2557 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2558
8a63facc 2559 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2560 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2561
8a63facc
BC		 2562 ret = ath5k_eeprom_read_mac(ah, mac);
2563 if (ret) {
2564 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
2565 sc->pdev->device);
2566 goto err_queues;
e30eb4ab 2567 }
2bed03eb 2568
8a63facc
BC		 2569 SET_IEEE80211_PERM_ADDR(hw, mac);
2570 /* All MAC address bits matter for ACKs */
2571 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
2572 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
2573
2574 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2575 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2576 if (ret) {
2577 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2578 goto err_queues;
2579 }
2580
2581 ret = ieee80211_register_hw(hw);
2582 if (ret) {
2583 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2584 goto err_queues;
2585 }
2586
2587 if (!ath_is_world_regd(regulatory))
2588 regulatory_hint(hw->wiphy, regulatory->alpha2);
2589
2590 ath5k_init_leds(sc);
2591
2592 ath5k_sysfs_register(sc);
2593
2594 return 0;
2595err_queues:
2596 ath5k_txq_release(sc);
2597err_bhal:
2598 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2599err_desc:
2600 ath5k_desc_free(sc, pdev);
2601err:
2602 return ret;
2603}
2604
2605static void
2606ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
2607{
2608 struct ath5k_softc *sc = hw->priv;
2609
2610 /*
2611 * NB: the order of these is important:
2612 * o call the 802.11 layer before detaching ath5k_hw to
2613 * ensure callbacks into the driver to delete global
2614 * key cache entries can be handled
2615 * o reclaim the tx queue data structures after calling
2616 * the 802.11 layer as we'll get called back to reclaim
2617 * node state and potentially want to use them
2618 * o to cleanup the tx queues the hal is called, so detach
2619 * it last
2620 * XXX: ??? detach ath5k_hw ???
2621 * Other than that, it's straightforward...
2622 */
2623 ieee80211_unregister_hw(hw);
2624 ath5k_desc_free(sc, pdev);
2625 ath5k_txq_release(sc);
2626 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2627 ath5k_unregister_leds(sc);
2628
2629 ath5k_sysfs_unregister(sc);
2630 /*
2631 * NB: can't reclaim these until after ieee80211_ifdetach
2632 * returns because we'll get called back to reclaim node
2633 * state and potentially want to use them.
2634 */
2635}
2636
2637/********************\
2638* Mac80211 functions *
2639\********************/
2640
2641static int
2642ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2643{
2644 struct ath5k_softc *sc = hw->priv;
925e0b06
BR		 2645 u16 qnum = skb_get_queue_mapping(skb);
2646
2647 if (WARN_ON(qnum >= sc->ah->ah_capabilities.cap_queues.q_tx_num)) {
2648 dev_kfree_skb_any(skb);
2649 return 0;
2650 }
8a63facc 2651
925e0b06 2652 return ath5k_tx_queue(hw, skb, &sc->txqs[qnum]);
8a63facc
BC		 2653}
2654
2655static int ath5k_start(struct ieee80211_hw *hw)
2656{
2657 return ath5k_init(hw->priv);
2658}
2659
2660static void ath5k_stop(struct ieee80211_hw *hw)
2661{
2662 ath5k_stop_hw(hw->priv);
2663}
2664
2665static int ath5k_add_interface(struct ieee80211_hw *hw,
2666 struct ieee80211_vif *vif)
2667{
2668 struct ath5k_softc *sc = hw->priv;
2669 int ret;
2670
2671 mutex_lock(&sc->lock);
2672 if (sc->vif) {
2673 ret = 0;
2674 goto end;
2675 }
2676
2677 sc->vif = vif;
2678
2679 switch (vif->type) {
2680 case NL80211_IFTYPE_AP:
2681 case NL80211_IFTYPE_STATION:
2682 case NL80211_IFTYPE_ADHOC:
2683 case NL80211_IFTYPE_MESH_POINT:
2684 sc->opmode = vif->type;
2685 break;
2686 default:
2687 ret = -EOPNOTSUPP;
2688 goto end;
2689 }
2690
2691 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "add interface mode %d\n", sc->opmode);
2692
2693 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2694 ath5k_mode_setup(sc);
2695
2696 ret = 0;
2697end:
2698 mutex_unlock(&sc->lock);
2699 return ret;
2700}
2701
2702static void
2703ath5k_remove_interface(struct ieee80211_hw *hw,
2704 struct ieee80211_vif *vif)
2705{
2706 struct ath5k_softc *sc = hw->priv;
2707 u8 mac[ETH_ALEN] = {};
2708
2709 mutex_lock(&sc->lock);
2710 if (sc->vif != vif)
2711 goto end;
2712
2713 ath5k_hw_set_lladdr(sc->ah, mac);
2714 sc->vif = NULL;
2715end:
2716 mutex_unlock(&sc->lock);
2717}
2718
2719/*
2720 * TODO: Phy disable/diversity etc
2721 */
2722static int
2723ath5k_config(struct ieee80211_hw *hw, u32 changed)
2724{
2725 struct ath5k_softc *sc = hw->priv;
2726 struct ath5k_hw *ah = sc->ah;
2727 struct ieee80211_conf *conf = &hw->conf;
2728 int ret = 0;
2729
2730 mutex_lock(&sc->lock);
2731
2732 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2733 ret = ath5k_chan_set(sc, conf->channel);
2734 if (ret < 0)
2735 goto unlock;
2736 }
2737
2738 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2739 (sc->power_level != conf->power_level)) {
a0823810
NK		 2740 sc->power_level = conf->power_level;
2741
2742 /* Half dB steps */
2743 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2744 }
fa1c114f 2745
2bed03eb
NK		 2746 /* TODO:
2747 * 1) Move this on config_interface and handle each case
2748 * separately eg. when we have only one STA vif, use
2749 * AR5K_ANTMODE_SINGLE_AP
2750 *
2751 * 2) Allow the user to change antenna mode eg. when only
2752 * one antenna is present
2753 *
2754 * 3) Allow the user to set default/tx antenna when possible
2755 *
2756 * 4) Default mode should handle 90% of the cases, together
2757 * with fixed a/b and single AP modes we should be able to
2758 * handle 99%. Sectored modes are extreme cases and i still
2759 * haven't found a usage for them. If we decide to support them,
2760 * then we must allow the user to set how many tx antennas we
2761 * have available
2762 */
caec9112 2763 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
be009370 2764
55aa4e0f 2765unlock:
be009370 2766 mutex_unlock(&sc->lock);
55aa4e0f 2767 return ret;
fa1c114f
JS		 2768}
2769
3ac64bee 2770static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
22bedad3 2771 struct netdev_hw_addr_list *mc_list)
3ac64bee
JB		 2772{
2773 u32 mfilt[2], val;
3ac64bee 2774 u8 pos;
22bedad3 2775 struct netdev_hw_addr *ha;
3ac64bee
JB		 2776
2777 mfilt[0] = 0;
2778 mfilt[1] = 1;
2779
22bedad3 2780 netdev_hw_addr_list_for_each(ha, mc_list) {
3ac64bee 2781 /* calculate XOR of eight 6-bit values */
22bedad3 2782 val = get_unaligned_le32(ha->addr + 0);
3ac64bee 2783 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
22bedad3 2784 val = get_unaligned_le32(ha->addr + 3);
3ac64bee
JB		 2785 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2786 pos &= 0x3f;
2787 mfilt[pos / 32] |= (1 << (pos % 32));
2788 /* XXX: we might be able to just do this instead,
2789 * but not sure, needs testing, if we do use this we'd
2790 * neet to inform below to not reset the mcast */
2791 /* ath5k_hw_set_mcast_filterindex(ah,
22bedad3 2792 * ha->addr[5]); */
3ac64bee
JB		 2793 }
2794
2795 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2796}
2797
fa1c114f
JS		 2798#define SUPPORTED_FIF_FLAGS \
2799 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2800 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2801 FIF_BCN_PRBRESP_PROMISC
2802/*
2803 * o always accept unicast, broadcast, and multicast traffic
2804 * o multicast traffic for all BSSIDs will be enabled if mac80211
2805 * says it should be
2806 * o maintain current state of phy ofdm or phy cck error reception.
2807 * If the hardware detects any of these type of errors then
2808 * ath5k_hw_get_rx_filter() will pass to us the respective
2809 * hardware filters to be able to receive these type of frames.
2810 * o probe request frames are accepted only when operating in
2811 * hostap, adhoc, or monitor modes
2812 * o enable promiscuous mode according to the interface state
2813 * o accept beacons:
2814 * - when operating in adhoc mode so the 802.11 layer creates
2815 * node table entries for peers,
2816 * - when operating in station mode for collecting rssi data when
2817 * the station is otherwise quiet, or
2818 * - when scanning
2819 */
2820static void ath5k_configure_filter(struct ieee80211_hw *hw,
2821 unsigned int changed_flags,
2822 unsigned int *new_flags,
3ac64bee 2823 u64 multicast)
fa1c114f
JS		 2824{
2825 struct ath5k_softc *sc = hw->priv;
2826 struct ath5k_hw *ah = sc->ah;
3ac64bee 2827 u32 mfilt[2], rfilt;
fa1c114f 2828
56d1de0a
BC		 2829 mutex_lock(&sc->lock);
2830
3ac64bee
JB		 2831 mfilt[0] = multicast;
2832 mfilt[1] = multicast >> 32;
fa1c114f
JS		 2833
2834 /* Only deal with supported flags */
2835 changed_flags &= SUPPORTED_FIF_FLAGS;
2836 *new_flags &= SUPPORTED_FIF_FLAGS;
2837
2838 /* If HW detects any phy or radar errors, leave those filters on.
2839 * Also, always enable Unicast, Broadcasts and Multicast
2840 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2841 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2842 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2843 AR5K_RX_FILTER_MCAST);
2844
2845 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2846 if (*new_flags & FIF_PROMISC_IN_BSS) {
fa1c114f 2847 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2848 } else {
fa1c114f 2849 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2850 }
fa1c114f
JS		 2851 }
2852
6b5dcccb
BC		 2853 if (test_bit(ATH_STAT_PROMISC, sc->status))
2854 rfilt |= AR5K_RX_FILTER_PROM;
2855
fa1c114f
JS		 2856 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2857 if (*new_flags & FIF_ALLMULTI) {
2858 mfilt[0] = ~0;
2859 mfilt[1] = ~0;
fa1c114f
JS		 2860 }
2861
2862 /* This is the best we can do */
2863 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2864 rfilt |= AR5K_RX_FILTER_PHYERR;
2865
2866 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
30bf4169 2867 * and probes for any BSSID */
fa1c114f 2868 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
30bf4169 2869 rfilt |= AR5K_RX_FILTER_BEACON;
fa1c114f
JS		 2870
2871 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2872 * set we should only pass on control frames for this
2873 * station. This needs testing. I believe right now this
2874 * enables *all* control frames, which is OK.. but
2875 * but we should see if we can improve on granularity */
2876 if (*new_flags & FIF_CONTROL)
2877 rfilt |= AR5K_RX_FILTER_CONTROL;
2878
2879 /* Additional settings per mode -- this is per ath5k */
2880
2881 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2882
56d1de0a
BC		 2883 switch (sc->opmode) {
2884 case NL80211_IFTYPE_MESH_POINT:
56d1de0a
BC		 2885 rfilt |= AR5K_RX_FILTER_CONTROL |
2886 AR5K_RX_FILTER_BEACON |
2887 AR5K_RX_FILTER_PROBEREQ |
2888 AR5K_RX_FILTER_PROM;
2889 break;
2890 case NL80211_IFTYPE_AP:
2891 case NL80211_IFTYPE_ADHOC:
2892 rfilt |= AR5K_RX_FILTER_PROBEREQ |
2893 AR5K_RX_FILTER_BEACON;
2894 break;
2895 case NL80211_IFTYPE_STATION:
2896 if (sc->assoc)
2897 rfilt |= AR5K_RX_FILTER_BEACON;
2898 default:
2899 break;
2900 }
fa1c114f
JS		 2901
2902 /* Set filters */
0bbac08f 2903 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2904
2905 /* Set multicast bits */
2906 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
a180a130 2907 /* Set the cached hw filter flags, this will later actually
fa1c114f
JS		 2908 * be set in HW */
2909 sc->filter_flags = rfilt;
56d1de0a
BC		 2910
2911 mutex_unlock(&sc->lock);
fa1c114f
JS		 2912}
2913
2914static int
2915ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2916 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2917 struct ieee80211_key_conf *key)
fa1c114f
JS		 2918{
2919 struct ath5k_softc *sc = hw->priv;
dc1e001b
LR		 2920 struct ath5k_hw *ah = sc->ah;
2921 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f
JS		 2922 int ret = 0;
2923
9ad9a26e
BC		 2924 if (modparam_nohwcrypt)
2925 return -EOPNOTSUPP;
2926
97359d12
JB		 2927 switch (key->cipher) {
2928 case WLAN_CIPHER_SUITE_WEP40:
2929 case WLAN_CIPHER_SUITE_WEP104:
2930 case WLAN_CIPHER_SUITE_TKIP:
3f64b435 2931 break;
97359d12 2932 case WLAN_CIPHER_SUITE_CCMP:
781f3136 2933 if (common->crypt_caps & ATH_CRYPT_CAP_CIPHER_AESCCM)
1c818740 2934 break;
fa1c114f
JS		 2935 return -EOPNOTSUPP;
2936 default:
2937 WARN_ON(1);
2938 return -EINVAL;
2939 }
2940
2941 mutex_lock(&sc->lock);
2942
2943 switch (cmd) {
2944 case SET_KEY:
e0f8c2a9
BR		 2945 ret = ath_key_config(common, vif, sta, key);
2946 if (ret >= 0) {
2947 key->hw_key_idx = ret;
2948 /* push IV and Michael MIC generation to stack */
2949 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2950 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
2951 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2952 if (key->cipher == WLAN_CIPHER_SUITE_CCMP)
2953 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2954 ret = 0;
fa1c114f 2955 }
fa1c114f
JS		 2956 break;
2957 case DISABLE_KEY:
e0f8c2a9 2958 ath_key_delete(common, key);
fa1c114f
JS		 2959 break;
2960 default:
2961 ret = -EINVAL;
fa1c114f
JS		 2962 }
2963
8a63facc
BC		 2964 mmiowb();
2965 mutex_unlock(&sc->lock);
2966 return ret;
2967}
2968
2969static int
2970ath5k_get_stats(struct ieee80211_hw *hw,
2971 struct ieee80211_low_level_stats *stats)
2972{
2973 struct ath5k_softc *sc = hw->priv;
2974
2975 /* Force update */
2976 ath5k_hw_update_mib_counters(sc->ah);
2977
2978 stats->dot11ACKFailureCount = sc->stats.ack_fail;
2979 stats->dot11RTSFailureCount = sc->stats.rts_fail;
2980 stats->dot11RTSSuccessCount = sc->stats.rts_ok;
2981 stats->dot11FCSErrorCount = sc->stats.fcs_error;
2982
2983 return 0;
2984}
2985
2986static int ath5k_get_survey(struct ieee80211_hw *hw, int idx,
2987 struct survey_info *survey)
2988{
2989 struct ath5k_softc *sc = hw->priv;
2990 struct ieee80211_conf *conf = &hw->conf;
2991
2992 if (idx != 0)
2993 return -ENOENT;
2994
2995 survey->channel = conf->channel;
2996 survey->filled = SURVEY_INFO_NOISE_DBM;
2997 survey->noise = sc->ah->ah_noise_floor;
2998
2999 return 0;
3000}
3001
3002static u64
3003ath5k_get_tsf(struct ieee80211_hw *hw)
3004{
3005 struct ath5k_softc *sc = hw->priv;
3006
3007 return ath5k_hw_get_tsf64(sc->ah);
3008}
3009
3010static void
3011ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3012{
3013 struct ath5k_softc *sc = hw->priv;
3014
3015 ath5k_hw_set_tsf64(sc->ah, tsf);
3016}
3017
3018static void
3019ath5k_reset_tsf(struct ieee80211_hw *hw)
3020{
3021 struct ath5k_softc *sc = hw->priv;
3022
3023 /*
3024 * in IBSS mode we need to update the beacon timers too.
3025 * this will also reset the TSF if we call it with 0
3026 */
3027 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3028 ath5k_beacon_update_timers(sc, 0);
3029 else
3030 ath5k_hw_reset_tsf(sc->ah);
3031}
3032
3033static void
3034set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3035{
3036 struct ath5k_softc *sc = hw->priv;
3037 struct ath5k_hw *ah = sc->ah;
3038 u32 rfilt;
3039 rfilt = ath5k_hw_get_rx_filter(ah);
3040 if (enable)
3041 rfilt |= AR5K_RX_FILTER_BEACON;
3042 else
3043 rfilt &= ~AR5K_RX_FILTER_BEACON;
3044 ath5k_hw_set_rx_filter(ah, rfilt);
3045 sc->filter_flags = rfilt;
3046}
3047
3048static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3049 struct ieee80211_vif *vif,
3050 struct ieee80211_bss_conf *bss_conf,
3051 u32 changes)
3052{
3053 struct ath5k_softc *sc = hw->priv;
3054 struct ath5k_hw *ah = sc->ah;
3055 struct ath_common *common = ath5k_hw_common(ah);
3056 unsigned long flags;
3057
3058 mutex_lock(&sc->lock);
3059 if (WARN_ON(sc->vif != vif))
3060 goto unlock;
3061
3062 if (changes & BSS_CHANGED_BSSID) {
3063 /* Cache for later use during resets */
3064 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3065 common->curaid = 0;
3066 ath5k_hw_set_bssid(ah);
3067 mmiowb();
3068 }
3069
3070 if (changes & BSS_CHANGED_BEACON_INT)
3071 sc->bintval = bss_conf->beacon_int;
3072
3073 if (changes & BSS_CHANGED_ASSOC) {
3074 sc->assoc = bss_conf->assoc;
3075 if (sc->opmode == NL80211_IFTYPE_STATION)
3076 set_beacon_filter(hw, sc->assoc);
3077 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3078 AR5K_LED_ASSOC : AR5K_LED_INIT);
3079 if (bss_conf->assoc) {
3080 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3081 "Bss Info ASSOC %d, bssid: %pM\n",
3082 bss_conf->aid, common->curbssid);
3083 common->curaid = bss_conf->aid;
3084 ath5k_hw_set_bssid(ah);
3085 /* Once ANI is available you would start it here */
3086 }
3087 }
3088
3089 if (changes & BSS_CHANGED_BEACON) {
3090 spin_lock_irqsave(&sc->block, flags);
3091 ath5k_beacon_update(hw, vif);
3092 spin_unlock_irqrestore(&sc->block, flags);
3093 }
3094
3095 if (changes & BSS_CHANGED_BEACON_ENABLED)
3096 sc->enable_beacon = bss_conf->enable_beacon;
3097
3098 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3099 BSS_CHANGED_BEACON_INT))
3100 ath5k_beacon_config(sc);
3101
3102 unlock:
3103 mutex_unlock(&sc->lock);
3104}
3105
3106static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3107{
3108 struct ath5k_softc *sc = hw->priv;
3109 if (!sc->assoc)
3110 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3111}
3112
3113static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3114{
3115 struct ath5k_softc *sc = hw->priv;
3116 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3117 AR5K_LED_ASSOC : AR5K_LED_INIT);
3118}
3119
3120/**
3121 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3122 *
3123 * @hw: struct ieee80211_hw pointer
3124 * @coverage_class: IEEE 802.11 coverage class number
3125 *
3126 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3127 * coverage class. The values are persistent, they are restored after device
3128 * reset.
3129 */
3130static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3131{
3132 struct ath5k_softc *sc = hw->priv;
3133
3134 mutex_lock(&sc->lock);
3135 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3136 mutex_unlock(&sc->lock);
3137}
3138
3139static const struct ieee80211_ops ath5k_hw_ops = {
3140 .tx = ath5k_tx,
3141 .start = ath5k_start,
3142 .stop = ath5k_stop,
3143 .add_interface = ath5k_add_interface,
3144 .remove_interface = ath5k_remove_interface,
3145 .config = ath5k_config,
3146 .prepare_multicast = ath5k_prepare_multicast,
3147 .configure_filter = ath5k_configure_filter,
3148 .set_key = ath5k_set_key,
3149 .get_stats = ath5k_get_stats,
3150 .get_survey = ath5k_get_survey,
3151 .conf_tx = NULL,
3152 .get_tsf = ath5k_get_tsf,
3153 .set_tsf = ath5k_set_tsf,
3154 .reset_tsf = ath5k_reset_tsf,
3155 .bss_info_changed = ath5k_bss_info_changed,
3156 .sw_scan_start = ath5k_sw_scan_start,
3157 .sw_scan_complete = ath5k_sw_scan_complete,
3158 .set_coverage_class = ath5k_set_coverage_class,
3159};
3160
3161/********************\
3162* PCI Initialization *
3163\********************/
3164
3165static int __devinit
3166ath5k_pci_probe(struct pci_dev *pdev,
3167 const struct pci_device_id *id)
3168{
3169 void __iomem *mem;
3170 struct ath5k_softc *sc;
3171 struct ath_common *common;
3172 struct ieee80211_hw *hw;
3173 int ret;
3174 u8 csz;
3175
3176 /*
3177 * L0s needs to be disabled on all ath5k cards.
3178 *
3179 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
3180 * by default in the future in 2.6.36) this will also mean both L1 and
3181 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
3182 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
3183 * though but cannot currently undue the effect of a blacklist, for
3184 * details you can read pcie_aspm_sanity_check() and see how it adjusts
3185 * the device link capability.
3186 *
3187 * It may be possible in the future to implement some PCI API to allow
3188 * drivers to override blacklists for pre 1.1 PCIe but for now it is
3189 * best to accept that both L0s and L1 will be disabled completely for
3190 * distributions shipping with CONFIG_PCIEASPM rather than having this
3191 * issue present. Motivation for adding this new API will be to help
3192 * with power consumption for some of these devices.
3193 */
3194 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S);
3195
3196 ret = pci_enable_device(pdev);
3197 if (ret) {
3198 dev_err(&pdev->dev, "can't enable device\n");
3199 goto err;
3200 }
3201
3202 /* XXX 32-bit addressing only */
3203 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3204 if (ret) {
3205 dev_err(&pdev->dev, "32-bit DMA not available\n");
3206 goto err_dis;
3207 }
3208
3209 /*
3210 * Cache line size is used to size and align various
3211 * structures used to communicate with the hardware.
3212 */
3213 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
3214 if (csz == 0) {
3215 /*
3216 * Linux 2.4.18 (at least) writes the cache line size
3217 * register as a 16-bit wide register which is wrong.
3218 * We must have this setup properly for rx buffer
3219 * DMA to work so force a reasonable value here if it
3220 * comes up zero.
3221 */
3222 csz = L1_CACHE_BYTES >> 2;
3223 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
3224 }
3225 /*
3226 * The default setting of latency timer yields poor results,
3227 * set it to the value used by other systems. It may be worth
3228 * tweaking this setting more.
3229 */
3230 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
3231
3232 /* Enable bus mastering */
3233 pci_set_master(pdev);
3234
3235 /*
3236 * Disable the RETRY_TIMEOUT register (0x41) to keep
3237 * PCI Tx retries from interfering with C3 CPU state.
3238 */
3239 pci_write_config_byte(pdev, 0x41, 0);
3240
3241 ret = pci_request_region(pdev, 0, "ath5k");
3242 if (ret) {
3243 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
3244 goto err_dis;
3245 }
3246
3247 mem = pci_iomap(pdev, 0, 0);
3248 if (!mem) {
3249 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
3250 ret = -EIO;
3251 goto err_reg;
3252 }
3253
3254 /*
3255 * Allocate hw (mac80211 main struct)
3256 * and hw->priv (driver private data)
3257 */
3258 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
3259 if (hw == NULL) {
3260 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
3261 ret = -ENOMEM;
3262 goto err_map;
3263 }
3264
3265 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
3266
3267 /* Initialize driver private data */
3268 SET_IEEE80211_DEV(hw, &pdev->dev);
3269 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3270 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
3271 IEEE80211_HW_SIGNAL_DBM;
3272
3273 hw->wiphy->interface_modes =
3274 BIT(NL80211_IFTYPE_AP) |
3275 BIT(NL80211_IFTYPE_STATION) |
3276 BIT(NL80211_IFTYPE_ADHOC) |
3277 BIT(NL80211_IFTYPE_MESH_POINT);
3278
3279 hw->extra_tx_headroom = 2;
3280 hw->channel_change_time = 5000;
3281 sc = hw->priv;
3282 sc->hw = hw;
3283 sc->pdev = pdev;
3284
3285 ath5k_debug_init_device(sc);
3286
3287 /*
3288 * Mark the device as detached to avoid processing
3289 * interrupts until setup is complete.
3290 */
3291 __set_bit(ATH_STAT_INVALID, sc->status);
3292
3293 sc->iobase = mem; /* So we can unmap it on detach */
3294 sc->opmode = NL80211_IFTYPE_STATION;
3295 sc->bintval = 1000;
3296 mutex_init(&sc->lock);
3297 spin_lock_init(&sc->rxbuflock);
3298 spin_lock_init(&sc->txbuflock);
3299 spin_lock_init(&sc->block);
3300
3301 /* Set private data */
3302 pci_set_drvdata(pdev, sc);
3303
3304 /* Setup interrupt handler */
3305 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
3306 if (ret) {
3307 ATH5K_ERR(sc, "request_irq failed\n");
3308 goto err_free;
3309 }
3310
3311 /* If we passed the test, malloc an ath5k_hw struct */
3312 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
3313 if (!sc->ah) {
3314 ret = -ENOMEM;
3315 ATH5K_ERR(sc, "out of memory\n");
3316 goto err_irq;
3317 }
3318
3319 sc->ah->ah_sc = sc;
3320 sc->ah->ah_iobase = sc->iobase;
3321 common = ath5k_hw_common(sc->ah);
3322 common->ops = &ath5k_common_ops;
3323 common->ah = sc->ah;
3324 common->hw = hw;
3325 common->cachelsz = csz << 2; /* convert to bytes */
3326
3327 /* Initialize device */
3328 ret = ath5k_hw_attach(sc);
3329 if (ret) {
3330 goto err_free_ah;
3331 }
3332
3333 /* set up multi-rate retry capabilities */
3334 if (sc->ah->ah_version == AR5K_AR5212) {
3335 hw->max_rates = 4;
3336 hw->max_rate_tries = 11;
3337 }
3338
3339 /* Finish private driver data initialization */
3340 ret = ath5k_attach(pdev, hw);
3341 if (ret)
3342 goto err_ah;
3343
3344 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
3345 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
3346 sc->ah->ah_mac_srev,
3347 sc->ah->ah_phy_revision);
3348
3349 if (!sc->ah->ah_single_chip) {
3350 /* Single chip radio (!RF5111) */
3351 if (sc->ah->ah_radio_5ghz_revision &&
3352 !sc->ah->ah_radio_2ghz_revision) {
3353 /* No 5GHz support -> report 2GHz radio */
3354 if (!test_bit(AR5K_MODE_11A,
3355 sc->ah->ah_capabilities.cap_mode)) {
3356 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3357 ath5k_chip_name(AR5K_VERSION_RAD,
3358 sc->ah->ah_radio_5ghz_revision),
3359 sc->ah->ah_radio_5ghz_revision);
3360 /* No 2GHz support (5110 and some
3361 * 5Ghz only cards) -> report 5Ghz radio */
3362 } else if (!test_bit(AR5K_MODE_11B,
3363 sc->ah->ah_capabilities.cap_mode)) {
3364 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3365 ath5k_chip_name(AR5K_VERSION_RAD,
3366 sc->ah->ah_radio_5ghz_revision),
3367 sc->ah->ah_radio_5ghz_revision);
3368 /* Multiband radio */
3369 } else {
3370 ATH5K_INFO(sc, "RF%s multiband radio found"
3371 " (0x%x)\n",
3372 ath5k_chip_name(AR5K_VERSION_RAD,
3373 sc->ah->ah_radio_5ghz_revision),
3374 sc->ah->ah_radio_5ghz_revision);
3375 }
3376 }
3377 /* Multi chip radio (RF5111 - RF2111) ->
3378 * report both 2GHz/5GHz radios */
3379 else if (sc->ah->ah_radio_5ghz_revision &&
3380 sc->ah->ah_radio_2ghz_revision){
3381 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
3382 ath5k_chip_name(AR5K_VERSION_RAD,
3383 sc->ah->ah_radio_5ghz_revision),
3384 sc->ah->ah_radio_5ghz_revision);
3385 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
3386 ath5k_chip_name(AR5K_VERSION_RAD,
3387 sc->ah->ah_radio_2ghz_revision),
3388 sc->ah->ah_radio_2ghz_revision);
3389 }
3390 }
3391
55ee82b5 3392
8a63facc
BC		 3393 /* ready to process interrupts */
3394 __clear_bit(ATH_STAT_INVALID, sc->status);
55ee82b5
HS		 3395
3396 return 0;
8a63facc
BC		 3397err_ah:
3398 ath5k_hw_detach(sc->ah);
3399err_free_ah:
3400 kfree(sc->ah);
3401err_irq:
3402 free_irq(pdev->irq, sc);
3403err_free:
3404 ieee80211_free_hw(hw);
3405err_map:
3406 pci_iounmap(pdev, mem);
3407err_reg:
3408 pci_release_region(pdev, 0);
3409err_dis:
3410 pci_disable_device(pdev);
3411err:
3412 return ret;
55ee82b5
HS		 3413}
3414
8a63facc
BC		 3415static void __devexit
3416ath5k_pci_remove(struct pci_dev *pdev)
fa1c114f 3417{
8a63facc 3418 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3419
8a63facc
BC		 3420 ath5k_debug_finish_device(sc);
3421 ath5k_detach(pdev, sc->hw);
3422 ath5k_hw_detach(sc->ah);
3423 kfree(sc->ah);
3424 free_irq(pdev->irq, sc);
3425 pci_iounmap(pdev, sc->iobase);
3426 pci_release_region(pdev, 0);
3427 pci_disable_device(pdev);
3428 ieee80211_free_hw(sc->hw);
fa1c114f
JS		 3429}
3430
8a63facc
BC		 3431#ifdef CONFIG_PM_SLEEP
3432static int ath5k_pci_suspend(struct device *dev)
3b5d665b 3433{
8a63facc 3434 struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev));
3b5d665b 3435
8a63facc
BC		 3436 ath5k_led_off(sc);
3437 return 0;
3b5d665b
AF		 3438}
3439
8a63facc 3440static int ath5k_pci_resume(struct device *dev)
fa1c114f 3441{
8a63facc
BC		 3442 struct pci_dev *pdev = to_pci_dev(dev);
3443 struct ath5k_softc *sc = pci_get_drvdata(pdev);
fa1c114f 3444
9804b98d 3445 /*
8a63facc
BC		 3446 * Suspend/Resume resets the PCI configuration space, so we have to
3447 * re-disable the RETRY_TIMEOUT register (0x41) to keep
3448 * PCI Tx retries from interfering with C3 CPU state
9804b98d 3449 */
8a63facc
BC		 3450 pci_write_config_byte(pdev, 0x41, 0);
3451
3452 ath5k_led_enable(sc);
3453 return 0;
fa1c114f
JS		 3454}
3455
8a63facc
BC		 3456static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
3457#define ATH5K_PM_OPS (&ath5k_pm_ops)
3458#else
3459#define ATH5K_PM_OPS NULL
3460#endif /* CONFIG_PM_SLEEP */
3461
3462static struct pci_driver ath5k_pci_driver = {
3463 .name = KBUILD_MODNAME,
3464 .id_table = ath5k_pci_id_table,
3465 .probe = ath5k_pci_probe,
3466 .remove = __devexit_p(ath5k_pci_remove),
3467 .driver.pm = ATH5K_PM_OPS,
3468};
3469
1071db86 3470/*
8a63facc 3471 * Module init/exit functions
1071db86 3472 */
8a63facc
BC		 3473static int __init
3474init_ath5k_pci(void)
fa1c114f 3475{
fa1c114f 3476 int ret;
57c4d7b4 3477
8a63facc 3478 ath5k_debug_init();
2d0ddec5 3479
8a63facc
BC		 3480 ret = pci_register_driver(&ath5k_pci_driver);
3481 if (ret) {
3482 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
3483 return ret;
2d0ddec5
JB		 3484 }
3485
8a63facc 3486 return 0;
02969b38 3487}
f0f3d388 3488
8a63facc
BC		 3489static void __exit
3490exit_ath5k_pci(void)
f0f3d388 3491{
8a63facc 3492 pci_unregister_driver(&ath5k_pci_driver);
f0f3d388 3493
8a63facc 3494 ath5k_debug_finish();
f0f3d388 3495}
6e08d228 3496
8a63facc
BC		 3497module_init(init_ath5k_pci);
3498module_exit(exit_ath5k_pci);
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