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net/ucc_geth: Add SGMII support for UEC GETH driver
[net-next-2.6.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
209d889b 221static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
d7dc1003 222static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 223static int ath5k_start(struct ieee80211_hw *hw);
224static void ath5k_stop(struct ieee80211_hw *hw);
225static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
e8975581 229static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
fa1c114f
JS		 230static void ath5k_configure_filter(struct ieee80211_hw *hw,
231 unsigned int changed_flags,
232 unsigned int *new_flags,
233 int mc_count, struct dev_mc_list *mclist);
234static int ath5k_set_key(struct ieee80211_hw *hw,
235 enum set_key_cmd cmd,
dc822b5d 236 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 237 struct ieee80211_key_conf *key);
238static int ath5k_get_stats(struct ieee80211_hw *hw,
239 struct ieee80211_low_level_stats *stats);
240static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
241 struct ieee80211_tx_queue_stats *stats);
242static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 243static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 244static void ath5k_reset_tsf(struct ieee80211_hw *hw);
1071db86
BC		 245static int ath5k_beacon_update(struct ieee80211_hw *hw,
246 struct ieee80211_vif *vif);
02969b38
MX		 247static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif,
249 struct ieee80211_bss_conf *bss_conf,
250 u32 changes);
fa1c114f 251
2c91108c 252static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 253 .tx = ath5k_tx,
254 .start = ath5k_start,
255 .stop = ath5k_stop,
256 .add_interface = ath5k_add_interface,
257 .remove_interface = ath5k_remove_interface,
258 .config = ath5k_config,
fa1c114f
JS		 259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 353static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 354
355static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356{
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363}
364
365/* Interrupt handling */
bb2becac 366static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 367static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 368static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 369static irqreturn_t ath5k_intr(int irq, void *dev_id);
370static void ath5k_tasklet_reset(unsigned long data);
371
372static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 373
374/*
375 * Module init/exit functions
376 */
377static int __init
378init_ath5k_pci(void)
379{
380 int ret;
381
382 ath5k_debug_init();
383
04a9e451 384 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391}
392
393static void __exit
394exit_ath5k_pci(void)
395{
04a9e451 396 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 397
398 ath5k_debug_finish();
399}
400
401module_init(init_ath5k_pci);
402module_exit(exit_ath5k_pci);
403
404
405/********************\
406* PCI Initialization *
407\********************/
408
409static const char *
410ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411{
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
75d0edb8
NK		 418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429}
430
431static int __devinit
432ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434{
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
284901a9 448 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 517
518 hw->wiphy->interface_modes =
6f5f39c9 519 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 520 BIT(NL80211_IFTYPE_STATION) |
521 BIT(NL80211_IFTYPE_ADHOC) |
522 BIT(NL80211_IFTYPE_MESH_POINT);
523
fa1c114f
JS		 524 hw->extra_tx_headroom = 2;
525 hw->channel_change_time = 5000;
fa1c114f
JS		 526 sc = hw->priv;
527 sc->hw = hw;
528 sc->pdev = pdev;
529
530 ath5k_debug_init_device(sc);
531
532 /*
533 * Mark the device as detached to avoid processing
534 * interrupts until setup is complete.
535 */
536 __set_bit(ATH_STAT_INVALID, sc->status);
537
538 sc->iobase = mem; /* So we can unmap it on detach */
539 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 540 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 541 mutex_init(&sc->lock);
542 spin_lock_init(&sc->rxbuflock);
543 spin_lock_init(&sc->txbuflock);
00482973 544 spin_lock_init(&sc->block);
fa1c114f
JS		 545
546 /* Set private data */
547 pci_set_drvdata(pdev, hw);
548
fa1c114f
JS		 549 /* Setup interrupt handler */
550 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
551 if (ret) {
552 ATH5K_ERR(sc, "request_irq failed\n");
553 goto err_free;
554 }
555
556 /* Initialize device */
557 sc->ah = ath5k_hw_attach(sc, id->driver_data);
558 if (IS_ERR(sc->ah)) {
559 ret = PTR_ERR(sc->ah);
560 goto err_irq;
561 }
562
2f7fe870
FF		 563 /* set up multi-rate retry capabilities */
564 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 565 hw->max_rates = 4;
566 hw->max_rate_tries = 11;
2f7fe870
FF		 567 }
568
fa1c114f
JS		 569 /* Finish private driver data initialization */
570 ret = ath5k_attach(pdev, hw);
571 if (ret)
572 goto err_ah;
573
574 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 575 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 576 sc->ah->ah_mac_srev,
577 sc->ah->ah_phy_revision);
578
400ec45a 579 if (!sc->ah->ah_single_chip) {
fa1c114f 580 /* Single chip radio (!RF5111) */
400ec45a
LR		 581 if (sc->ah->ah_radio_5ghz_revision &&
582 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 583 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 584 if (!test_bit(AR5K_MODE_11A,
585 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 586 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 587 ath5k_chip_name(AR5K_VERSION_RAD,
588 sc->ah->ah_radio_5ghz_revision),
589 sc->ah->ah_radio_5ghz_revision);
590 /* No 2GHz support (5110 and some
591 * 5Ghz only cards) -> report 5Ghz radio */
592 } else if (!test_bit(AR5K_MODE_11B,
593 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 594 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 595 ath5k_chip_name(AR5K_VERSION_RAD,
596 sc->ah->ah_radio_5ghz_revision),
597 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 598 /* Multiband radio */
599 } else {
600 ATH5K_INFO(sc, "RF%s multiband radio found"
601 " (0x%x)\n",
400ec45a
LR		 602 ath5k_chip_name(AR5K_VERSION_RAD,
603 sc->ah->ah_radio_5ghz_revision),
604 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 605 }
606 }
400ec45a
LR		 607 /* Multi chip radio (RF5111 - RF2111) ->
608 * report both 2GHz/5GHz radios */
609 else if (sc->ah->ah_radio_5ghz_revision &&
610 sc->ah->ah_radio_2ghz_revision){
fa1c114f 611 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 612 ath5k_chip_name(AR5K_VERSION_RAD,
613 sc->ah->ah_radio_5ghz_revision),
614 sc->ah->ah_radio_5ghz_revision);
fa1c114f 615 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 616 ath5k_chip_name(AR5K_VERSION_RAD,
617 sc->ah->ah_radio_2ghz_revision),
618 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 619 }
620 }
621
622
623 /* ready to process interrupts */
624 __clear_bit(ATH_STAT_INVALID, sc->status);
625
626 return 0;
627err_ah:
628 ath5k_hw_detach(sc->ah);
629err_irq:
630 free_irq(pdev->irq, sc);
631err_free:
fa1c114f
JS		 632 ieee80211_free_hw(hw);
633err_map:
634 pci_iounmap(pdev, mem);
635err_reg:
636 pci_release_region(pdev, 0);
637err_dis:
638 pci_disable_device(pdev);
639err:
640 return ret;
641}
642
643static void __devexit
644ath5k_pci_remove(struct pci_dev *pdev)
645{
646 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
647 struct ath5k_softc *sc = hw->priv;
648
649 ath5k_debug_finish_device(sc);
650 ath5k_detach(pdev, hw);
651 ath5k_hw_detach(sc->ah);
652 free_irq(pdev->irq, sc);
fa1c114f
JS		 653 pci_iounmap(pdev, sc->iobase);
654 pci_release_region(pdev, 0);
655 pci_disable_device(pdev);
656 ieee80211_free_hw(hw);
657}
658
659#ifdef CONFIG_PM
660static int
661ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
662{
663 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
664 struct ath5k_softc *sc = hw->priv;
665
3a078876 666 ath5k_led_off(sc);
fa1c114f 667
3e4242b9 668 free_irq(pdev->irq, sc);
fa1c114f
JS		 669 pci_save_state(pdev);
670 pci_disable_device(pdev);
671 pci_set_power_state(pdev, PCI_D3hot);
672
673 return 0;
674}
675
676static int
677ath5k_pci_resume(struct pci_dev *pdev)
678{
679 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
680 struct ath5k_softc *sc = hw->priv;
bc1b32d6 681 int err;
fa1c114f 682
3e4242b9 683 pci_restore_state(pdev);
fa1c114f
JS		 684
685 err = pci_enable_device(pdev);
686 if (err)
687 return err;
688
3e4242b9
JS		 689 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
690 if (err) {
691 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 692 goto err_no_irq;
3e4242b9
JS		 693 }
694
3a078876 695 ath5k_led_enable(sc);
fa1c114f 696 return 0;
bb2becac 697
37465c8a 698err_no_irq:
3e4242b9
JS		 699 pci_disable_device(pdev);
700 return err;
fa1c114f
JS		 701}
702#endif /* CONFIG_PM */
703
704
fa1c114f
JS		 705/***********************\
706* Driver Initialization *
707\***********************/
708
f769c36b
BC		 709static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
710{
711 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
712 struct ath5k_softc *sc = hw->priv;
713 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
714
715 return ath_reg_notifier_apply(wiphy, request, reg);
716}
717
fa1c114f
JS		 718static int
719ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
720{
721 struct ath5k_softc *sc = hw->priv;
722 struct ath5k_hw *ah = sc->ah;
0e149cf5 723 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 724 int ret;
725
726 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
727
728 /*
729 * Check if the MAC has multi-rate retry support.
730 * We do this by trying to setup a fake extended
731 * descriptor. MAC's that don't have support will
732 * return false w/o doing anything. MAC's that do
733 * support it will return true w/o doing anything.
734 */
c6e387a2 735 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 736 if (ret < 0)
737 goto err;
738 if (ret > 0)
fa1c114f
JS		 739 __set_bit(ATH_STAT_MRRETRY, sc->status);
740
fa1c114f
JS		 741 /*
742 * Collect the channel list. The 802.11 layer
743 * is resposible for filtering this list based
744 * on settings like the phy mode and regulatory
745 * domain restrictions.
746 */
63266a65 747 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 748 if (ret) {
749 ATH5K_ERR(sc, "can't get channels\n");
750 goto err;
751 }
752
753 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 754 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
755 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 756 else
d8ee398d 757 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 758
759 /*
760 * Allocate tx+rx descriptors and populate the lists.
761 */
762 ret = ath5k_desc_alloc(sc, pdev);
763 if (ret) {
764 ATH5K_ERR(sc, "can't allocate descriptors\n");
765 goto err;
766 }
767
768 /*
769 * Allocate hardware transmit queues: one queue for
770 * beacon frames and one data queue for each QoS
771 * priority. Note that hw functions handle reseting
772 * these queues at the needed time.
773 */
774 ret = ath5k_beaconq_setup(ah);
775 if (ret < 0) {
776 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
777 goto err_desc;
778 }
779 sc->bhalq = ret;
780
781 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
782 if (IS_ERR(sc->txq)) {
783 ATH5K_ERR(sc, "can't setup xmit queue\n");
784 ret = PTR_ERR(sc->txq);
785 goto err_bhal;
786 }
787
788 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
789 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
790 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 791 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 792 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 793
0e149cf5
BC		 794 ret = ath5k_eeprom_read_mac(ah, mac);
795 if (ret) {
796 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
797 sc->pdev->device);
798 goto err_queues;
799 }
800
fa1c114f
JS		 801 SET_IEEE80211_PERM_ADDR(hw, mac);
802 /* All MAC address bits matter for ACKs */
803 memset(sc->bssidmask, 0xff, ETH_ALEN);
804 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
805
f769c36b
BC		 806 ah->ah_regulatory.current_rd =
807 ah->ah_capabilities.cap_eeprom.ee_regdomain;
808 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
809 if (ret) {
810 ATH5K_ERR(sc, "can't initialize regulatory system\n");
811 goto err_queues;
812 }
813
fa1c114f
JS		 814 ret = ieee80211_register_hw(hw);
815 if (ret) {
816 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
817 goto err_queues;
818 }
819
f769c36b
BC		 820 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
821 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
822
3a078876
BC		 823 ath5k_init_leds(sc);
824
fa1c114f
JS		 825 return 0;
826err_queues:
827 ath5k_txq_release(sc);
828err_bhal:
829 ath5k_hw_release_tx_queue(ah, sc->bhalq);
830err_desc:
831 ath5k_desc_free(sc, pdev);
832err:
833 return ret;
834}
835
836static void
837ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
838{
839 struct ath5k_softc *sc = hw->priv;
840
841 /*
842 * NB: the order of these is important:
843 * o call the 802.11 layer before detaching ath5k_hw to
844 * insure callbacks into the driver to delete global
845 * key cache entries can be handled
846 * o reclaim the tx queue data structures after calling
847 * the 802.11 layer as we'll get called back to reclaim
848 * node state and potentially want to use them
849 * o to cleanup the tx queues the hal is called, so detach
850 * it last
851 * XXX: ??? detach ath5k_hw ???
852 * Other than that, it's straightforward...
853 */
854 ieee80211_unregister_hw(hw);
855 ath5k_desc_free(sc, pdev);
856 ath5k_txq_release(sc);
857 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 858 ath5k_unregister_leds(sc);
fa1c114f
JS		 859
860 /*
861 * NB: can't reclaim these until after ieee80211_ifdetach
862 * returns because we'll get called back to reclaim node
863 * state and potentially want to use them.
864 */
865}
866
867
868
869
870/********************\
871* Channel/mode setup *
872\********************/
873
874/*
875 * Convert IEEE channel number to MHz frequency.
876 */
877static inline short
878ath5k_ieee2mhz(short chan)
879{
880 if (chan <= 14 || chan >= 27)
881 return ieee80211chan2mhz(chan);
882 else
883 return 2212 + chan * 20;
884}
885
42639fcd
BC		 886/*
887 * Returns true for the channel numbers used without all_channels modparam.
888 */
889static bool ath5k_is_standard_channel(short chan)
890{
891 return ((chan <= 14) ||
892 /* UNII 1,2 */
893 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
894 /* midband */
895 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
896 /* UNII-3 */
897 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
898}
899
fa1c114f
JS		 900static unsigned int
901ath5k_copy_channels(struct ath5k_hw *ah,
902 struct ieee80211_channel *channels,
903 unsigned int mode,
904 unsigned int max)
905{
d8ee398d 906 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 907
908 if (!test_bit(mode, ah->ah_modes))
909 return 0;
910
fa1c114f 911 switch (mode) {
d8ee398d
LR		 912 case AR5K_MODE_11A:
913 case AR5K_MODE_11A_TURBO:
fa1c114f 914 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 915 size = 220 ;
fa1c114f
JS		 916 chfreq = CHANNEL_5GHZ;
917 break;
d8ee398d
LR		 918 case AR5K_MODE_11B:
919 case AR5K_MODE_11G:
920 case AR5K_MODE_11G_TURBO:
921 size = 26;
fa1c114f
JS		 922 chfreq = CHANNEL_2GHZ;
923 break;
924 default:
925 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
926 return 0;
927 }
928
929 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 930 ch = i + 1 ;
931 freq = ath5k_ieee2mhz(ch);
fa1c114f 932
d8ee398d
LR		 933 /* Check if channel is supported by the chipset */
934 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 935 continue;
936
42639fcd
BC		 937 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
938 continue;
939
d8ee398d
LR		 940 /* Write channel info and increment counter */
941 channels[count].center_freq = freq;
a3f4b914
LR		 942 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
943 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 944 switch (mode) {
945 case AR5K_MODE_11A:
946 case AR5K_MODE_11G:
947 channels[count].hw_value = chfreq | CHANNEL_OFDM;
948 break;
949 case AR5K_MODE_11A_TURBO:
950 case AR5K_MODE_11G_TURBO:
951 channels[count].hw_value = chfreq |
952 CHANNEL_OFDM | CHANNEL_TURBO;
953 break;
954 case AR5K_MODE_11B:
d8ee398d
LR		 955 channels[count].hw_value = CHANNEL_B;
956 }
fa1c114f 957
fa1c114f
JS		 958 count++;
959 max--;
960 }
961
962 return count;
963}
964
63266a65
BR		 965static void
966ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
967{
968 u8 i;
969
970 for (i = 0; i < AR5K_MAX_RATES; i++)
971 sc->rate_idx[b->band][i] = -1;
972
973 for (i = 0; i < b->n_bitrates; i++) {
974 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
975 if (b->bitrates[i].hw_value_short)
976 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
977 }
978}
979
d8ee398d 980static int
63266a65 981ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 982{
983 struct ath5k_softc *sc = hw->priv;
d8ee398d 984 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 985 struct ieee80211_supported_band *sband;
986 int max_c, count_c = 0;
987 int i;
fa1c114f 988
d8ee398d 989 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 990 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 991
992 /* 2GHz band */
63266a65
BR		 993 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
994 sband->band = IEEE80211_BAND_2GHZ;
995 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 996
63266a65
BR		 997 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
998 /* G mode */
999 memcpy(sband->bitrates, &ath5k_rates[0],
1000 sizeof(struct ieee80211_rate) * 12);
1001 sband->n_bitrates = 12;
fa1c114f 1002
d8ee398d 1003 sband->channels = sc->channels;
d8ee398d 1004 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1005 AR5K_MODE_11G, max_c);
fa1c114f 1006
63266a65 1007 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1008 count_c = sband->n_channels;
63266a65
BR		 1009 max_c -= count_c;
1010 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1011 /* B mode */
1012 memcpy(sband->bitrates, &ath5k_rates[0],
1013 sizeof(struct ieee80211_rate) * 4);
1014 sband->n_bitrates = 4;
1015
1016 /* 5211 only supports B rates and uses 4bit rate codes
1017 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1018 * fix them up here:
1019 */
1020 if (ah->ah_version == AR5K_AR5211) {
1021 for (i = 0; i < 4; i++) {
1022 sband->bitrates[i].hw_value =
1023 sband->bitrates[i].hw_value & 0xF;
1024 sband->bitrates[i].hw_value_short =
1025 sband->bitrates[i].hw_value_short & 0xF;
1026 }
1027 }
fa1c114f 1028
63266a65
BR		 1029 sband->channels = sc->channels;
1030 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1031 AR5K_MODE_11B, max_c);
d8ee398d 1032
63266a65
BR		 1033 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1034 count_c = sband->n_channels;
d8ee398d 1035 max_c -= count_c;
fa1c114f 1036 }
63266a65 1037 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1038
63266a65 1039 /* 5GHz band, A mode */
400ec45a 1040 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1041 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1042 sband->band = IEEE80211_BAND_5GHZ;
1043 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1044
63266a65
BR		 1045 memcpy(sband->bitrates, &ath5k_rates[4],
1046 sizeof(struct ieee80211_rate) * 8);
1047 sband->n_bitrates = 8;
fa1c114f 1048
63266a65 1049 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1050 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1051 AR5K_MODE_11A, max_c);
1052
d8ee398d
LR		 1053 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1054 }
63266a65 1055 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1056
b446197c 1057 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1058
1059 return 0;
fa1c114f
JS		 1060}
1061
1062/*
1063 * Set/change channels. If the channel is really being changed,
1064 * it's done by reseting the chip. To accomplish this we must
1065 * first cleanup any pending DMA, then restart stuff after a la
1066 * ath5k_init.
be009370
BC		 1067 *
1068 * Called with sc->lock.
fa1c114f
JS		 1069 */
1070static int
1071ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1072{
d8ee398d
LR		 1073 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1074 sc->curchan->center_freq, chan->center_freq);
1075
1076 if (chan->center_freq != sc->curchan->center_freq ||
1077 chan->hw_value != sc->curchan->hw_value) {
1078
fa1c114f
JS		 1079 /*
1080 * To switch channels clear any pending DMA operations;
1081 * wait long enough for the RX fifo to drain, reset the
1082 * hardware at the new frequency, and then re-enable
1083 * the relevant bits of the h/w.
1084 */
209d889b 1085 return ath5k_reset(sc, chan);
fa1c114f
JS		 1086 }
1087
1088 return 0;
1089}
1090
1091static void
1092ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1093{
fa1c114f 1094 sc->curmode = mode;
d8ee398d 1095
400ec45a 1096 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1097 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1098 } else {
1099 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1100 }
fa1c114f
JS		 1101}
1102
1103static void
1104ath5k_mode_setup(struct ath5k_softc *sc)
1105{
1106 struct ath5k_hw *ah = sc->ah;
1107 u32 rfilt;
1108
1109 /* configure rx filter */
1110 rfilt = sc->filter_flags;
1111 ath5k_hw_set_rx_filter(ah, rfilt);
1112
1113 if (ath5k_hw_hasbssidmask(ah))
1114 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1115
1116 /* configure operational mode */
1117 ath5k_hw_set_opmode(ah);
1118
1119 ath5k_hw_set_mcast_filter(ah, 0, 0);
1120 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1121}
1122
d8ee398d 1123static inline int
63266a65
BR		 1124ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1125{
b7266047
BC		 1126 int rix;
1127
1128 /* return base rate on errors */
1129 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1130 "hw_rix out of bounds: %x\n", hw_rix))
1131 return 0;
1132
1133 rix = sc->rate_idx[sc->curband->band][hw_rix];
1134 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1135 rix = 0;
1136
1137 return rix;
d8ee398d
LR		 1138}
1139
fa1c114f
JS		 1140/***************\
1141* Buffers setup *
1142\***************/
1143
b6ea0356
BC		 1144static
1145struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1146{
1147 struct sk_buff *skb;
1148 unsigned int off;
1149
1150 /*
1151 * Allocate buffer with headroom_needed space for the
1152 * fake physical layer header at the start.
1153 */
1154 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1155
1156 if (!skb) {
1157 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1158 sc->rxbufsize + sc->cachelsz - 1);
1159 return NULL;
1160 }
1161 /*
1162 * Cache-line-align. This is important (for the
1163 * 5210 at least) as not doing so causes bogus data
1164 * in rx'd frames.
1165 */
1166 off = ((unsigned long)skb->data) % sc->cachelsz;
1167 if (off != 0)
1168 skb_reserve(skb, sc->cachelsz - off);
1169
1170 *skb_addr = pci_map_single(sc->pdev,
1171 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1172 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1173 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1174 dev_kfree_skb(skb);
1175 return NULL;
1176 }
1177 return skb;
1178}
1179
fa1c114f
JS		 1180static int
1181ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1182{
1183 struct ath5k_hw *ah = sc->ah;
1184 struct sk_buff *skb = bf->skb;
1185 struct ath5k_desc *ds;
1186
b6ea0356
BC		 1187 if (!skb) {
1188 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1189 if (!skb)
fa1c114f 1190 return -ENOMEM;
fa1c114f 1191 bf->skb = skb;
fa1c114f
JS		 1192 }
1193
1194 /*
1195 * Setup descriptors. For receive we always terminate
1196 * the descriptor list with a self-linked entry so we'll
1197 * not get overrun under high load (as can happen with a
1198 * 5212 when ANI processing enables PHY error frames).
1199 *
1200 * To insure the last descriptor is self-linked we create
1201 * each descriptor as self-linked and add it to the end. As
1202 * each additional descriptor is added the previous self-linked
1203 * entry is ``fixed'' naturally. This should be safe even
1204 * if DMA is happening. When processing RX interrupts we
1205 * never remove/process the last, self-linked, entry on the
1206 * descriptor list. This insures the hardware always has
1207 * someplace to write a new frame.
1208 */
1209 ds = bf->desc;
1210 ds->ds_link = bf->daddr; /* link to self */
1211 ds->ds_data = bf->skbaddr;
c6e387a2 1212 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1213 skb_tailroom(skb), /* buffer size */
1214 0);
1215
1216 if (sc->rxlink != NULL)
1217 *sc->rxlink = bf->daddr;
1218 sc->rxlink = &ds->ds_link;
1219 return 0;
1220}
1221
1222static int
e039fa4a 1223ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1224{
1225 struct ath5k_hw *ah = sc->ah;
1226 struct ath5k_txq *txq = sc->txq;
1227 struct ath5k_desc *ds = bf->desc;
1228 struct sk_buff *skb = bf->skb;
a888d52d 1229 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1230 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1231 struct ieee80211_rate *rate;
1232 unsigned int mrr_rate[3], mrr_tries[3];
1233 int i, ret;
8902ff4e 1234 u16 hw_rate;
07c1e852
BC		 1235 u16 cts_rate = 0;
1236 u16 duration = 0;
8902ff4e 1237 u8 rc_flags;
fa1c114f
JS		 1238
1239 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1240
fa1c114f
JS		 1241 /* XXX endianness */
1242 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1243 PCI_DMA_TODEVICE);
1244
8902ff4e
BC		 1245 rate = ieee80211_get_tx_rate(sc->hw, info);
1246
e039fa4a 1247 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1248 flags |= AR5K_TXDESC_NOACK;
1249
8902ff4e
BC		 1250 rc_flags = info->control.rates[0].flags;
1251 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1252 rate->hw_value_short : rate->hw_value;
1253
281c56dd 1254 pktlen = skb->len;
fa1c114f 1255
8f655dde
NK		 1256 /* FIXME: If we are in g mode and rate is a CCK rate
1257 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1258 * from tx power (value is in dB units already) */
362695e1
BC		 1259 if (info->control.hw_key) {
1260 keyidx = info->control.hw_key->hw_key_idx;
1261 pktlen += info->control.hw_key->icv_len;
1262 }
07c1e852
BC		 1263 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1264 flags |= AR5K_TXDESC_RTSENA;
1265 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1266 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1267 sc->vif, pktlen, info));
1268 }
1269 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1270 flags |= AR5K_TXDESC_CTSENA;
1271 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1272 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1273 sc->vif, pktlen, info));
1274 }
fa1c114f
JS		 1275 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1276 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1277 (sc->power_level * 2),
8902ff4e 1278 hw_rate,
2bed03eb 1279 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
07c1e852 1280 cts_rate, duration);
fa1c114f
JS		 1281 if (ret)
1282 goto err_unmap;
1283
2f7fe870
FF		 1284 memset(mrr_rate, 0, sizeof(mrr_rate));
1285 memset(mrr_tries, 0, sizeof(mrr_tries));
1286 for (i = 0; i < 3; i++) {
1287 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1288 if (!rate)
1289 break;
1290
1291 mrr_rate[i] = rate->hw_value;
e6a9854b 1292 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1293 }
1294
1295 ah->ah_setup_mrr_tx_desc(ah, ds,
1296 mrr_rate[0], mrr_tries[0],
1297 mrr_rate[1], mrr_tries[1],
1298 mrr_rate[2], mrr_tries[2]);
1299
fa1c114f
JS		 1300 ds->ds_link = 0;
1301 ds->ds_data = bf->skbaddr;
1302
1303 spin_lock_bh(&txq->lock);
1304 list_add_tail(&bf->list, &txq->q);
57ffc589 1305 sc->tx_stats[txq->qnum].len++;
fa1c114f 1306 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1307 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1308 else /* no, so only link it */
1309 *txq->link = bf->daddr;
1310
1311 txq->link = &ds->ds_link;
c6e387a2 1312 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1313 mmiowb();
fa1c114f
JS		 1314 spin_unlock_bh(&txq->lock);
1315
1316 return 0;
1317err_unmap:
1318 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1319 return ret;
1320}
1321
1322/*******************\
1323* Descriptors setup *
1324\*******************/
1325
1326static int
1327ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1328{
1329 struct ath5k_desc *ds;
1330 struct ath5k_buf *bf;
1331 dma_addr_t da;
1332 unsigned int i;
1333 int ret;
1334
1335 /* allocate descriptors */
1336 sc->desc_len = sizeof(struct ath5k_desc) *
1337 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1338 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1339 if (sc->desc == NULL) {
1340 ATH5K_ERR(sc, "can't allocate descriptors\n");
1341 ret = -ENOMEM;
1342 goto err;
1343 }
1344 ds = sc->desc;
1345 da = sc->desc_daddr;
1346 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1347 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1348
1349 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1350 sizeof(struct ath5k_buf), GFP_KERNEL);
1351 if (bf == NULL) {
1352 ATH5K_ERR(sc, "can't allocate bufptr\n");
1353 ret = -ENOMEM;
1354 goto err_free;
1355 }
1356 sc->bufptr = bf;
1357
1358 INIT_LIST_HEAD(&sc->rxbuf);
1359 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1360 bf->desc = ds;
1361 bf->daddr = da;
1362 list_add_tail(&bf->list, &sc->rxbuf);
1363 }
1364
1365 INIT_LIST_HEAD(&sc->txbuf);
1366 sc->txbuf_len = ATH_TXBUF;
1367 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1368 da += sizeof(*ds)) {
1369 bf->desc = ds;
1370 bf->daddr = da;
1371 list_add_tail(&bf->list, &sc->txbuf);
1372 }
1373
1374 /* beacon buffer */
1375 bf->desc = ds;
1376 bf->daddr = da;
1377 sc->bbuf = bf;
1378
1379 return 0;
1380err_free:
1381 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1382err:
1383 sc->desc = NULL;
1384 return ret;
1385}
1386
1387static void
1388ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1389{
1390 struct ath5k_buf *bf;
1391
1392 ath5k_txbuf_free(sc, sc->bbuf);
1393 list_for_each_entry(bf, &sc->txbuf, list)
1394 ath5k_txbuf_free(sc, bf);
1395 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1396 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1397
1398 /* Free memory associated with all descriptors */
1399 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1400
1401 kfree(sc->bufptr);
1402 sc->bufptr = NULL;
1403}
1404
1405
1406
1407
1408
1409/**************\
1410* Queues setup *
1411\**************/
1412
1413static struct ath5k_txq *
1414ath5k_txq_setup(struct ath5k_softc *sc,
1415 int qtype, int subtype)
1416{
1417 struct ath5k_hw *ah = sc->ah;
1418 struct ath5k_txq *txq;
1419 struct ath5k_txq_info qi = {
1420 .tqi_subtype = subtype,
1421 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1422 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1423 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1424 };
1425 int qnum;
1426
1427 /*
1428 * Enable interrupts only for EOL and DESC conditions.
1429 * We mark tx descriptors to receive a DESC interrupt
1430 * when a tx queue gets deep; otherwise waiting for the
1431 * EOL to reap descriptors. Note that this is done to
1432 * reduce interrupt load and this only defers reaping
1433 * descriptors, never transmitting frames. Aside from
1434 * reducing interrupts this also permits more concurrency.
1435 * The only potential downside is if the tx queue backs
1436 * up in which case the top half of the kernel may backup
1437 * due to a lack of tx descriptors.
1438 */
1439 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1440 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1441 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1442 if (qnum < 0) {
1443 /*
1444 * NB: don't print a message, this happens
1445 * normally on parts with too few tx queues
1446 */
1447 return ERR_PTR(qnum);
1448 }
1449 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1450 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1451 qnum, ARRAY_SIZE(sc->txqs));
1452 ath5k_hw_release_tx_queue(ah, qnum);
1453 return ERR_PTR(-EINVAL);
1454 }
1455 txq = &sc->txqs[qnum];
1456 if (!txq->setup) {
1457 txq->qnum = qnum;
1458 txq->link = NULL;
1459 INIT_LIST_HEAD(&txq->q);
1460 spin_lock_init(&txq->lock);
1461 txq->setup = true;
1462 }
1463 return &sc->txqs[qnum];
1464}
1465
1466static int
1467ath5k_beaconq_setup(struct ath5k_hw *ah)
1468{
1469 struct ath5k_txq_info qi = {
1470 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1471 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1472 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1473 /* NB: for dynamic turbo, don't enable any other interrupts */
1474 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1475 };
1476
1477 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1478}
1479
1480static int
1481ath5k_beaconq_config(struct ath5k_softc *sc)
1482{
1483 struct ath5k_hw *ah = sc->ah;
1484 struct ath5k_txq_info qi;
1485 int ret;
1486
1487 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1488 if (ret)
1489 return ret;
05c914fe
JB		 1490 if (sc->opmode == NL80211_IFTYPE_AP ||
1491 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1492 /*
1493 * Always burst out beacon and CAB traffic
1494 * (aifs = cwmin = cwmax = 0)
1495 */
1496 qi.tqi_aifs = 0;
1497 qi.tqi_cw_min = 0;
1498 qi.tqi_cw_max = 0;
05c914fe 1499 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1500 /*
1501 * Adhoc mode; backoff between 0 and (2 * cw_min).
1502 */
1503 qi.tqi_aifs = 0;
1504 qi.tqi_cw_min = 0;
1505 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1506 }
1507
6d91e1d8
BR		 1508 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1509 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1510 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1511
c6e387a2 1512 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1513 if (ret) {
1514 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1515 "hardware queue!\n", __func__);
1516 return ret;
1517 }
1518
1519 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1520}
1521
1522static void
1523ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1524{
1525 struct ath5k_buf *bf, *bf0;
1526
1527 /*
1528 * NB: this assumes output has been stopped and
1529 * we do not need to block ath5k_tx_tasklet
1530 */
1531 spin_lock_bh(&txq->lock);
1532 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1533 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1534
1535 ath5k_txbuf_free(sc, bf);
1536
1537 spin_lock_bh(&sc->txbuflock);
57ffc589 1538 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1539 list_move_tail(&bf->list, &sc->txbuf);
1540 sc->txbuf_len++;
1541 spin_unlock_bh(&sc->txbuflock);
1542 }
1543 txq->link = NULL;
1544 spin_unlock_bh(&txq->lock);
1545}
1546
1547/*
1548 * Drain the transmit queues and reclaim resources.
1549 */
1550static void
1551ath5k_txq_cleanup(struct ath5k_softc *sc)
1552{
1553 struct ath5k_hw *ah = sc->ah;
1554 unsigned int i;
1555
1556 /* XXX return value */
1557 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1558 /* don't touch the hardware if marked invalid */
1559 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1560 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1561 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1562 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1563 if (sc->txqs[i].setup) {
1564 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1565 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1566 "link %p\n",
1567 sc->txqs[i].qnum,
c6e387a2 1568 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1569 sc->txqs[i].qnum),
1570 sc->txqs[i].link);
1571 }
1572 }
36d6825b 1573 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1574
1575 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1576 if (sc->txqs[i].setup)
1577 ath5k_txq_drainq(sc, &sc->txqs[i]);
1578}
1579
1580static void
1581ath5k_txq_release(struct ath5k_softc *sc)
1582{
1583 struct ath5k_txq *txq = sc->txqs;
1584 unsigned int i;
1585
1586 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1587 if (txq->setup) {
1588 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1589 txq->setup = false;
1590 }
1591}
1592
1593
1594
1595
1596/*************\
1597* RX Handling *
1598\*************/
1599
1600/*
1601 * Enable the receive h/w following a reset.
1602 */
1603static int
1604ath5k_rx_start(struct ath5k_softc *sc)
1605{
1606 struct ath5k_hw *ah = sc->ah;
1607 struct ath5k_buf *bf;
1608 int ret;
1609
1610 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1611
1612 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1613 sc->cachelsz, sc->rxbufsize);
1614
fa1c114f 1615 spin_lock_bh(&sc->rxbuflock);
26925042 1616 sc->rxlink = NULL;
fa1c114f
JS		 1617 list_for_each_entry(bf, &sc->rxbuf, list) {
1618 ret = ath5k_rxbuf_setup(sc, bf);
1619 if (ret != 0) {
1620 spin_unlock_bh(&sc->rxbuflock);
1621 goto err;
1622 }
1623 }
1624 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1625 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1626 spin_unlock_bh(&sc->rxbuflock);
1627
c6e387a2 1628 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1629 ath5k_mode_setup(sc); /* set filters, etc. */
1630 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1631
1632 return 0;
1633err:
1634 return ret;
1635}
1636
1637/*
1638 * Disable the receive h/w in preparation for a reset.
1639 */
1640static void
1641ath5k_rx_stop(struct ath5k_softc *sc)
1642{
1643 struct ath5k_hw *ah = sc->ah;
1644
c6e387a2 1645 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1646 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1647 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1648
1649 ath5k_debug_printrxbuffs(sc, ah);
1650
1651 sc->rxlink = NULL; /* just in case */
1652}
1653
1654static unsigned int
1655ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1656 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1657{
1658 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1659 unsigned int keyix, hlen;
fa1c114f 1660
b47f407b
BR		 1661 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1662 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1663 return RX_FLAG_DECRYPTED;
1664
1665 /* Apparently when a default key is used to decrypt the packet
1666 the hw does not set the index used to decrypt. In such cases
1667 get the index from the packet. */
798ee985 1668 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1669 if (ieee80211_has_protected(hdr->frame_control) &&
1670 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1671 skb->len >= hlen + 4) {
fa1c114f
JS		 1672 keyix = skb->data[hlen + 3] >> 6;
1673
1674 if (test_bit(keyix, sc->keymap))
1675 return RX_FLAG_DECRYPTED;
1676 }
1677
1678 return 0;
1679}
1680
036cd1ec
BR		 1681
1682static void
6ba81c2c
BR		 1683ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1684 struct ieee80211_rx_status *rxs)
036cd1ec 1685{
6ba81c2c 1686 u64 tsf, bc_tstamp;
036cd1ec
BR		 1687 u32 hw_tu;
1688 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1689
24b56e70 1690 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1691 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1692 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1693 /*
6ba81c2c
BR		 1694 * Received an IBSS beacon with the same BSSID. Hardware *must*
1695 * have updated the local TSF. We have to work around various
1696 * hardware bugs, though...
036cd1ec 1697 */
6ba81c2c
BR		 1698 tsf = ath5k_hw_get_tsf64(sc->ah);
1699 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1700 hw_tu = TSF_TO_TU(tsf);
1701
1702 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1703 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1704 (unsigned long long)bc_tstamp,
1705 (unsigned long long)rxs->mactime,
1706 (unsigned long long)(rxs->mactime - bc_tstamp),
1707 (unsigned long long)tsf);
6ba81c2c
BR		 1708
1709 /*
1710 * Sometimes the HW will give us a wrong tstamp in the rx
1711 * status, causing the timestamp extension to go wrong.
1712 * (This seems to happen especially with beacon frames bigger
1713 * than 78 byte (incl. FCS))
1714 * But we know that the receive timestamp must be later than the
1715 * timestamp of the beacon since HW must have synced to that.
1716 *
1717 * NOTE: here we assume mactime to be after the frame was
1718 * received, not like mac80211 which defines it at the start.
1719 */
1720 if (bc_tstamp > rxs->mactime) {
036cd1ec 1721 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1722 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1723 (unsigned long long)rxs->mactime,
1724 (unsigned long long)tsf);
6ba81c2c 1725 rxs->mactime = tsf;
036cd1ec 1726 }
6ba81c2c
BR		 1727
1728 /*
1729 * Local TSF might have moved higher than our beacon timers,
1730 * in that case we have to update them to continue sending
1731 * beacons. This also takes care of synchronizing beacon sending
1732 * times with other stations.
1733 */
1734 if (hw_tu >= sc->nexttbtt)
1735 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1736 }
1737}
1738
fa1c114f
JS		 1739static void
1740ath5k_tasklet_rx(unsigned long data)
1741{
1742 struct ieee80211_rx_status rxs = {};
b47f407b 1743 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1744 struct sk_buff *skb, *next_skb;
1745 dma_addr_t next_skb_addr;
fa1c114f 1746 struct ath5k_softc *sc = (void *)data;
c57ca815 1747 struct ath5k_buf *bf;
fa1c114f 1748 struct ath5k_desc *ds;
fa1c114f
JS		 1749 int ret;
1750 int hdrlen;
0fe45b1d 1751 int padsize;
fa1c114f
JS		 1752
1753 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1754 if (list_empty(&sc->rxbuf)) {
1755 ATH5K_WARN(sc, "empty rx buf pool\n");
1756 goto unlock;
1757 }
fa1c114f 1758 do {
d6894b5b
BC		 1759 rxs.flag = 0;
1760
fa1c114f
JS		 1761 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1762 BUG_ON(bf->skb == NULL);
1763 skb = bf->skb;
1764 ds = bf->desc;
1765
c57ca815
BC		 1766 /* bail if HW is still using self-linked descriptor */
1767 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1768 break;
fa1c114f 1769
b47f407b 1770 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1771 if (unlikely(ret == -EINPROGRESS))
1772 break;
1773 else if (unlikely(ret)) {
1774 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1775 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1776 return;
1777 }
1778
b47f407b 1779 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1780 ATH5K_WARN(sc, "unsupported jumbo\n");
1781 goto next;
1782 }
1783
b47f407b
BR		 1784 if (unlikely(rs.rs_status)) {
1785 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1786 goto next;
b47f407b 1787 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1788 /*
1789 * Decrypt error. If the error occurred
1790 * because there was no hardware key, then
1791 * let the frame through so the upper layers
1792 * can process it. This is necessary for 5210
1793 * parts which have no way to setup a ``clear''
1794 * key cache entry.
1795 *
1796 * XXX do key cache faulting
1797 */
b47f407b
BR		 1798 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1799 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1800 goto accept;
1801 }
b47f407b 1802 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1803 rxs.flag |= RX_FLAG_MMIC_ERROR;
1804 goto accept;
1805 }
1806
1807 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1808 if ((rs.rs_status &
1809 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1810 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1811 goto next;
1812 }
1813accept:
b6ea0356
BC		 1814 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1815
1816 /*
1817 * If we can't replace bf->skb with a new skb under memory
1818 * pressure, just skip this packet
1819 */
1820 if (!next_skb)
1821 goto next;
1822
fa1c114f
JS		 1823 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1824 PCI_DMA_FROMDEVICE);
b47f407b 1825 skb_put(skb, rs.rs_datalen);
fa1c114f 1826
0fe45b1d
BP		 1827 /* The MAC header is padded to have 32-bit boundary if the
1828 * packet payload is non-zero. The general calculation for
1829 * padsize would take into account odd header lengths:
1830 * padsize = (4 - hdrlen % 4) % 4; However, since only
1831 * even-length headers are used, padding can only be 0 or 2
1832 * bytes and we can optimize this a bit. In addition, we must
1833 * not try to remove padding from short control frames that do
1834 * not have payload. */
fa1c114f 1835 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1836 padsize = ath5k_pad_size(hdrlen);
1837 if (padsize) {
0fe45b1d
BP		 1838 memmove(skb->data + padsize, skb->data, hdrlen);
1839 skb_pull(skb, padsize);
fa1c114f
JS		 1840 }
1841
c0e1899b
BR		 1842 /*
1843 * always extend the mac timestamp, since this information is
1844 * also needed for proper IBSS merging.
1845 *
1846 * XXX: it might be too late to do it here, since rs_tstamp is
1847 * 15bit only. that means TSF extension has to be done within
1848 * 32768usec (about 32ms). it might be necessary to move this to
1849 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1850 *
1851 * Unfortunately we don't know when the hardware takes the rx
1852 * timestamp (beginning of phy frame, data frame, end of rx?).
1853 * The only thing we know is that it is hardware specific...
1854 * On AR5213 it seems the rx timestamp is at the end of the
1855 * frame, but i'm not sure.
1856 *
1857 * NOTE: mac80211 defines mactime at the beginning of the first
1858 * data symbol. Since we don't have any time references it's
1859 * impossible to comply to that. This affects IBSS merge only
1860 * right now, so it's not too bad...
c0e1899b 1861 */
b47f407b 1862 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1863 rxs.flag |= RX_FLAG_TSFT;
1864
d8ee398d
LR		 1865 rxs.freq = sc->curchan->center_freq;
1866 rxs.band = sc->curband->band;
fa1c114f 1867
fa1c114f 1868 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1869 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1870
1871 /* An rssi of 35 indicates you should be able use
1872 * 54 Mbps reliably. A more elaborate scheme can be used
1873 * here but it requires a map of SNR/throughput for each
1874 * possible mode used */
1875 rxs.qual = rs.rs_rssi * 100 / 35;
1876
1877 /* rssi can be more than 35 though, anything above that
1878 * should be considered at 100% */
1879 if (rxs.qual > 100)
1880 rxs.qual = 100;
fa1c114f 1881
b47f407b
BR		 1882 rxs.antenna = rs.rs_antenna;
1883 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1884 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1885
06303352
BR		 1886 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1887 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1888 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1889
fa1c114f
JS		 1890 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1891
036cd1ec 1892 /* check beacons in IBSS mode */
05c914fe 1893 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1894 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1895
fa1c114f 1896 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1897
1898 bf->skb = next_skb;
1899 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1900next:
1901 list_move_tail(&bf->list, &sc->rxbuf);
1902 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1903unlock:
fa1c114f
JS		 1904 spin_unlock(&sc->rxbuflock);
1905}
1906
1907
1908
1909
1910/*************\
1911* TX Handling *
1912\*************/
1913
1914static void
1915ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1916{
b47f407b 1917 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1918 struct ath5k_buf *bf, *bf0;
1919 struct ath5k_desc *ds;
1920 struct sk_buff *skb;
e039fa4a 1921 struct ieee80211_tx_info *info;
2f7fe870 1922 int i, ret;
fa1c114f
JS		 1923
1924 spin_lock(&txq->lock);
1925 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1926 ds = bf->desc;
1927
b47f407b 1928 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1929 if (unlikely(ret == -EINPROGRESS))
1930 break;
1931 else if (unlikely(ret)) {
1932 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1933 ret, txq->qnum);
1934 break;
1935 }
1936
1937 skb = bf->skb;
a888d52d 1938 info = IEEE80211_SKB_CB(skb);
fa1c114f 1939 bf->skb = NULL;
e039fa4a 1940
fa1c114f
JS		 1941 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1942 PCI_DMA_TODEVICE);
1943
e6a9854b 1944 ieee80211_tx_info_clear_status(info);
2f7fe870 1945 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1946 struct ieee80211_tx_rate *r =
1947 &info->status.rates[i];
2f7fe870
FF		 1948
1949 if (ts.ts_rate[i]) {
e6a9854b
JB		 1950 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1951 r->count = ts.ts_retry[i];
2f7fe870 1952 } else {
e6a9854b
JB		 1953 r->idx = -1;
1954 r->count = 0;
2f7fe870
FF		 1955 }
1956 }
1957
e6a9854b
JB		 1958 /* count the successful attempt as well */
1959 info->status.rates[ts.ts_final_idx].count++;
1960
b47f407b 1961 if (unlikely(ts.ts_status)) {
fa1c114f 1962 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1963 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1964 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1965 } else {
e039fa4a
JB		 1966 info->flags |= IEEE80211_TX_STAT_ACK;
1967 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1968 }
1969
e039fa4a 1970 ieee80211_tx_status(sc->hw, skb);
57ffc589 1971 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1972
1973 spin_lock(&sc->txbuflock);
57ffc589 1974 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1975 list_move_tail(&bf->list, &sc->txbuf);
1976 sc->txbuf_len++;
1977 spin_unlock(&sc->txbuflock);
1978 }
1979 if (likely(list_empty(&txq->q)))
1980 txq->link = NULL;
1981 spin_unlock(&txq->lock);
1982 if (sc->txbuf_len > ATH_TXBUF / 5)
1983 ieee80211_wake_queues(sc->hw);
1984}
1985
1986static void
1987ath5k_tasklet_tx(unsigned long data)
1988{
1989 struct ath5k_softc *sc = (void *)data;
1990
1991 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1992}
1993
1994
fa1c114f
JS		 1995/*****************\
1996* Beacon handling *
1997\*****************/
1998
1999/*
2000 * Setup the beacon frame for transmit.
2001 */
2002static int
e039fa4a 2003ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2004{
2005 struct sk_buff *skb = bf->skb;
a888d52d 2006 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2007 struct ath5k_hw *ah = sc->ah;
2008 struct ath5k_desc *ds;
2bed03eb
NK		 2009 int ret = 0;
2010 u8 antenna;
fa1c114f
JS		 2011 u32 flags;
2012
2013 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2014 PCI_DMA_TODEVICE);
2015 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2016 "skbaddr %llx\n", skb, skb->data, skb->len,
2017 (unsigned long long)bf->skbaddr);
8d8bb39b 2018 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2019 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2020 return -EIO;
2021 }
2022
2023 ds = bf->desc;
2bed03eb 2024 antenna = ah->ah_tx_ant;
fa1c114f
JS		 2025
2026 flags = AR5K_TXDESC_NOACK;
05c914fe 2027 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2028 ds->ds_link = bf->daddr; /* self-linked */
2029 flags |= AR5K_TXDESC_VEOL;
2bed03eb 2030 } else
fa1c114f 2031 ds->ds_link = 0;
2bed03eb
NK		 2032
2033 /*
2034 * If we use multiple antennas on AP and use
2035 * the Sectored AP scenario, switch antenna every
2036 * 4 beacons to make sure everybody hears our AP.
2037 * When a client tries to associate, hw will keep
2038 * track of the tx antenna to be used for this client
2039 * automaticaly, based on ACKed packets.
2040 *
2041 * Note: AP still listens and transmits RTS on the
2042 * default antenna which is supposed to be an omni.
2043 *
2044 * Note2: On sectored scenarios it's possible to have
2045 * multiple antennas (1omni -the default- and 14 sectors)
2046 * so if we choose to actually support this mode we need
2047 * to allow user to set how many antennas we have and tweak
2048 * the code below to send beacons on all of them.
2049 */
2050 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2051 antenna = sc->bsent & 4 ? 2 : 1;
2052
fa1c114f 2053
8f655dde
NK		 2054 /* FIXME: If we are in g mode and rate is a CCK rate
2055 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2056 * from tx power (value is in dB units already) */
fa1c114f 2057 ds->ds_data = bf->skbaddr;
281c56dd 2058 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2059 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2060 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2061 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2062 1, AR5K_TXKEYIX_INVALID,
400ec45a 2063 antenna, flags, 0, 0);
fa1c114f
JS		 2064 if (ret)
2065 goto err_unmap;
2066
2067 return 0;
2068err_unmap:
2069 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2070 return ret;
2071}
2072
2073/*
2074 * Transmit a beacon frame at SWBA. Dynamic updates to the
2075 * frame contents are done as needed and the slot time is
2076 * also adjusted based on current state.
2077 *
acf3c1a5
BC		 2078 * This is called from software irq context (beacontq or restq
2079 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2080 */
2081static void
2082ath5k_beacon_send(struct ath5k_softc *sc)
2083{
2084 struct ath5k_buf *bf = sc->bbuf;
2085 struct ath5k_hw *ah = sc->ah;
2086
be9b7259 2087 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2088
05c914fe
JB		 2089 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2090 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2091 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2092 return;
2093 }
2094 /*
2095 * Check if the previous beacon has gone out. If
2096 * not don't don't try to post another, skip this
2097 * period and wait for the next. Missed beacons
2098 * indicate a problem and should not occur. If we
2099 * miss too many consecutive beacons reset the device.
2100 */
2101 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2102 sc->bmisscount++;
be9b7259 2103 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2104 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2105 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2106 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2107 "stuck beacon time (%u missed)\n",
2108 sc->bmisscount);
2109 tasklet_schedule(&sc->restq);
2110 }
2111 return;
2112 }
2113 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2114 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2115 "resume beacon xmit after %u misses\n",
2116 sc->bmisscount);
2117 sc->bmisscount = 0;
2118 }
2119
2120 /*
2121 * Stop any current dma and put the new frame on the queue.
2122 * This should never fail since we check above that no frames
2123 * are still pending on the queue.
2124 */
2125 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2126 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2127 /* NB: hw still stops DMA, so proceed */
2128 }
fa1c114f 2129
1071db86
BC		 2130 /* refresh the beacon for AP mode */
2131 if (sc->opmode == NL80211_IFTYPE_AP)
2132 ath5k_beacon_update(sc->hw, sc->vif);
2133
c6e387a2
NK		 2134 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2135 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2136 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2137 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2138
2139 sc->bsent++;
2140}
2141
2142
9804b98d
BR		 2143/**
2144 * ath5k_beacon_update_timers - update beacon timers
2145 *
2146 * @sc: struct ath5k_softc pointer we are operating on
2147 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2148 * beacon timer update based on the current HW TSF.
2149 *
2150 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2151 * of a received beacon or the current local hardware TSF and write it to the
2152 * beacon timer registers.
2153 *
2154 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2155 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2156 * when we otherwise know we have to update the timers, but we keep it in this
2157 * function to have it all together in one place.
2158 */
fa1c114f 2159static void
9804b98d 2160ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2161{
2162 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2163 u32 nexttbtt, intval, hw_tu, bc_tu;
2164 u64 hw_tsf;
fa1c114f
JS		 2165
2166 intval = sc->bintval & AR5K_BEACON_PERIOD;
2167 if (WARN_ON(!intval))
2168 return;
2169
9804b98d
BR		 2170 /* beacon TSF converted to TU */
2171 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2172
9804b98d
BR		 2173 /* current TSF converted to TU */
2174 hw_tsf = ath5k_hw_get_tsf64(ah);
2175 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2176
9804b98d
BR		 2177#define FUDGE 3
2178 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2179 if (bc_tsf == -1) {
2180 /*
2181 * no beacons received, called internally.
2182 * just need to refresh timers based on HW TSF.
2183 */
2184 nexttbtt = roundup(hw_tu + FUDGE, intval);
2185 } else if (bc_tsf == 0) {
2186 /*
2187 * no beacon received, probably called by ath5k_reset_tsf().
2188 * reset TSF to start with 0.
2189 */
2190 nexttbtt = intval;
2191 intval |= AR5K_BEACON_RESET_TSF;
2192 } else if (bc_tsf > hw_tsf) {
2193 /*
2194 * beacon received, SW merge happend but HW TSF not yet updated.
2195 * not possible to reconfigure timers yet, but next time we
2196 * receive a beacon with the same BSSID, the hardware will
2197 * automatically update the TSF and then we need to reconfigure
2198 * the timers.
2199 */
2200 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2201 "need to wait for HW TSF sync\n");
2202 return;
2203 } else {
2204 /*
2205 * most important case for beacon synchronization between STA.
2206 *
2207 * beacon received and HW TSF has been already updated by HW.
2208 * update next TBTT based on the TSF of the beacon, but make
2209 * sure it is ahead of our local TSF timer.
2210 */
2211 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2212 }
2213#undef FUDGE
fa1c114f 2214
036cd1ec
BR		 2215 sc->nexttbtt = nexttbtt;
2216
fa1c114f 2217 intval |= AR5K_BEACON_ENA;
fa1c114f 2218 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2219
2220 /*
2221 * debugging output last in order to preserve the time critical aspect
2222 * of this function
2223 */
2224 if (bc_tsf == -1)
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2226 "reconfigured timers based on HW TSF\n");
2227 else if (bc_tsf == 0)
2228 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2229 "reset HW TSF and timers\n");
2230 else
2231 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2232 "updated timers based on beacon TSF\n");
2233
2234 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2235 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2236 (unsigned long long) bc_tsf,
2237 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2238 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2239 intval & AR5K_BEACON_PERIOD,
2240 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2241 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2242}
2243
2244
036cd1ec
BR		 2245/**
2246 * ath5k_beacon_config - Configure the beacon queues and interrupts
2247 *
2248 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2249 *
036cd1ec 2250 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2251 * interrupts to detect TSF updates only.
fa1c114f
JS		 2252 */
2253static void
2254ath5k_beacon_config(struct ath5k_softc *sc)
2255{
2256 struct ath5k_hw *ah = sc->ah;
b5f03956 2257 unsigned long flags;
fa1c114f 2258
c6e387a2 2259 ath5k_hw_set_imr(ah, 0);
fa1c114f 2260 sc->bmisscount = 0;
dc1968e7 2261 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2262
1e3e6e8f 2263 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2264 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2265 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2266 /*
036cd1ec
BR		 2267 * In IBSS mode we use a self-linked tx descriptor and let the
2268 * hardware send the beacons automatically. We have to load it
fa1c114f 2269 * only once here.
036cd1ec 2270 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2271 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2272 */
2273 ath5k_beaconq_config(sc);
fa1c114f 2274
036cd1ec
BR		 2275 sc->imask |= AR5K_INT_SWBA;
2276
da966bca
JS		 2277 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2278 if (ath5k_hw_hasveol(ah)) {
b5f03956 2279 spin_lock_irqsave(&sc->block, flags);
da966bca 2280 ath5k_beacon_send(sc);
b5f03956 2281 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2282 }
2283 } else
2284 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2285 }
fa1c114f 2286
c6e387a2 2287 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2288}
2289
428cbd4f
NK		 2290static void ath5k_tasklet_beacon(unsigned long data)
2291{
2292 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2293
2294 /*
2295 * Software beacon alert--time to send a beacon.
2296 *
2297 * In IBSS mode we use this interrupt just to
2298 * keep track of the next TBTT (target beacon
2299 * transmission time) in order to detect wether
2300 * automatic TSF updates happened.
2301 */
2302 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2303 /* XXX: only if VEOL suppported */
2304 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2305 sc->nexttbtt += sc->bintval;
2306 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2307 "SWBA nexttbtt: %x hw_tu: %x "
2308 "TSF: %llx\n",
2309 sc->nexttbtt,
2310 TSF_TO_TU(tsf),
2311 (unsigned long long) tsf);
2312 } else {
2313 spin_lock(&sc->block);
2314 ath5k_beacon_send(sc);
2315 spin_unlock(&sc->block);
2316 }
2317}
2318
fa1c114f
JS		 2319
2320/********************\
2321* Interrupt handling *
2322\********************/
2323
2324static int
bb2becac 2325ath5k_init(struct ath5k_softc *sc)
fa1c114f 2326{
bc1b32d6
EO		 2327 struct ath5k_hw *ah = sc->ah;
2328 int ret, i;
fa1c114f
JS		 2329
2330 mutex_lock(&sc->lock);
2331
2332 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2333
2334 /*
2335 * Stop anything previously setup. This is safe
2336 * no matter this is the first time through or not.
2337 */
2338 ath5k_stop_locked(sc);
2339
2340 /*
2341 * The basic interface to setting the hardware in a good
2342 * state is ``reset''. On return the hardware is known to
2343 * be powered up and with interrupts disabled. This must
2344 * be followed by initialization of the appropriate bits
2345 * and then setup of the interrupt mask.
2346 */
d8ee398d
LR		 2347 sc->curchan = sc->hw->conf.channel;
2348 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2349 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2350 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2351 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
209d889b 2352 ret = ath5k_reset(sc, NULL);
d7dc1003
JS		 2353 if (ret)
2354 goto done;
fa1c114f 2355
bc1b32d6
EO		 2356 /*
2357 * Reset the key cache since some parts do not reset the
2358 * contents on initial power up or resume from suspend.
2359 */
2360 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2361 ath5k_hw_reset_key(ah, i);
2362
fa1c114f 2363 /* Set ack to be sent at low bit-rates */
bc1b32d6 2364 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2365
2366 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2367 msecs_to_jiffies(ath5k_calinterval * 1000)));
2368
2369 ret = 0;
2370done:
274c7c36 2371 mmiowb();
fa1c114f
JS		 2372 mutex_unlock(&sc->lock);
2373 return ret;
2374}
2375
2376static int
2377ath5k_stop_locked(struct ath5k_softc *sc)
2378{
2379 struct ath5k_hw *ah = sc->ah;
2380
2381 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2382 test_bit(ATH_STAT_INVALID, sc->status));
2383
2384 /*
2385 * Shutdown the hardware and driver:
2386 * stop output from above
2387 * disable interrupts
2388 * turn off timers
2389 * turn off the radio
2390 * clear transmit machinery
2391 * clear receive machinery
2392 * drain and release tx queues
2393 * reclaim beacon resources
2394 * power down hardware
2395 *
2396 * Note that some of this work is not possible if the
2397 * hardware is gone (invalid).
2398 */
2399 ieee80211_stop_queues(sc->hw);
2400
2401 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2402 ath5k_led_off(sc);
c6e387a2 2403 ath5k_hw_set_imr(ah, 0);
274c7c36 2404 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2405 }
2406 ath5k_txq_cleanup(sc);
2407 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2408 ath5k_rx_stop(sc);
2409 ath5k_hw_phy_disable(ah);
2410 } else
2411 sc->rxlink = NULL;
2412
2413 return 0;
2414}
2415
2416/*
2417 * Stop the device, grabbing the top-level lock to protect
2418 * against concurrent entry through ath5k_init (which can happen
2419 * if another thread does a system call and the thread doing the
2420 * stop is preempted).
2421 */
2422static int
bb2becac 2423ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2424{
2425 int ret;
2426
2427 mutex_lock(&sc->lock);
2428 ret = ath5k_stop_locked(sc);
2429 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2430 /*
2431 * Set the chip in full sleep mode. Note that we are
2432 * careful to do this only when bringing the interface
2433 * completely to a stop. When the chip is in this state
2434 * it must be carefully woken up or references to
2435 * registers in the PCI clock domain may freeze the bus
2436 * (and system). This varies by chip and is mostly an
2437 * issue with newer parts that go to sleep more quickly.
2438 */
2439 if (sc->ah->ah_mac_srev >= 0x78) {
2440 /*
2441 * XXX
2442 * don't put newer MAC revisions > 7.8 to sleep because
2443 * of the above mentioned problems
2444 */
2445 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2446 "not putting device to sleep\n");
2447 } else {
2448 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2449 "putting device to full sleep\n");
2450 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2451 }
2452 }
2453 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2454
274c7c36 2455 mmiowb();
fa1c114f
JS		 2456 mutex_unlock(&sc->lock);
2457
2458 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2459 tasklet_kill(&sc->rxtq);
2460 tasklet_kill(&sc->txtq);
2461 tasklet_kill(&sc->restq);
acf3c1a5 2462 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2463
2464 return ret;
2465}
2466
2467static irqreturn_t
2468ath5k_intr(int irq, void *dev_id)
2469{
2470 struct ath5k_softc *sc = dev_id;
2471 struct ath5k_hw *ah = sc->ah;
2472 enum ath5k_int status;
2473 unsigned int counter = 1000;
2474
2475 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2476 !ath5k_hw_is_intr_pending(ah)))
2477 return IRQ_NONE;
2478
2479 do {
fa1c114f
JS		 2480 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2481 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2482 status, sc->imask);
fa1c114f
JS		 2483 if (unlikely(status & AR5K_INT_FATAL)) {
2484 /*
2485 * Fatal errors are unrecoverable.
2486 * Typically these are caused by DMA errors.
2487 */
2488 tasklet_schedule(&sc->restq);
2489 } else if (unlikely(status & AR5K_INT_RXORN)) {
2490 tasklet_schedule(&sc->restq);
2491 } else {
2492 if (status & AR5K_INT_SWBA) {
56d2ac76 2493 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2494 }
2495 if (status & AR5K_INT_RXEOL) {
2496 /*
2497 * NB: the hardware should re-read the link when
2498 * RXE bit is written, but it doesn't work at
2499 * least on older hardware revs.
2500 */
2501 sc->rxlink = NULL;
2502 }
2503 if (status & AR5K_INT_TXURN) {
2504 /* bump tx trigger level */
2505 ath5k_hw_update_tx_triglevel(ah, true);
2506 }
4c674c60 2507 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2508 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2509 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2510 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2511 tasklet_schedule(&sc->txtq);
2512 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2513 /* TODO */
fa1c114f
JS		 2514 }
2515 if (status & AR5K_INT_MIB) {
194828a2
NK		 2516 /*
2517 * These stats are also used for ANI i think
2518 * so how about updating them more often ?
2519 */
2520 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2521 }
2522 }
2516baa6 2523 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2524
2525 if (unlikely(!counter))
2526 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2527
2528 return IRQ_HANDLED;
2529}
2530
2531static void
2532ath5k_tasklet_reset(unsigned long data)
2533{
2534 struct ath5k_softc *sc = (void *)data;
2535
d7dc1003 2536 ath5k_reset_wake(sc);
fa1c114f
JS		 2537}
2538
2539/*
2540 * Periodically recalibrate the PHY to account
2541 * for temperature/environment changes.
2542 */
2543static void
2544ath5k_calibrate(unsigned long data)
2545{
2546 struct ath5k_softc *sc = (void *)data;
2547 struct ath5k_hw *ah = sc->ah;
2548
2549 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2550 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2551 sc->curchan->hw_value);
fa1c114f 2552
6f3b414a 2553 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2554 /*
2555 * Rfgain is out of bounds, reset the chip
2556 * to load new gain values.
2557 */
2558 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2559 ath5k_reset_wake(sc);
fa1c114f
JS		 2560 }
2561 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2562 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2563 ieee80211_frequency_to_channel(
2564 sc->curchan->center_freq));
fa1c114f
JS		 2565
2566 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2567 msecs_to_jiffies(ath5k_calinterval * 1000)));
2568}
2569
2570
fa1c114f
JS		 2571/********************\
2572* Mac80211 functions *
2573\********************/
2574
2575static int
e039fa4a 2576ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2577{
2578 struct ath5k_softc *sc = hw->priv;
2579 struct ath5k_buf *bf;
2580 unsigned long flags;
2581 int hdrlen;
0fe45b1d 2582 int padsize;
fa1c114f
JS		 2583
2584 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2585
05c914fe 2586 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2587 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2588
2589 /*
2590 * the hardware expects the header padded to 4 byte boundaries
2591 * if this is not the case we add the padding after the header
2592 */
2593 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2594 padsize = ath5k_pad_size(hdrlen);
2595 if (padsize) {
0fe45b1d
BP		 2596
2597 if (skb_headroom(skb) < padsize) {
fa1c114f 2598 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2599 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2600 goto drop_packet;
fa1c114f 2601 }
0fe45b1d
BP		 2602 skb_push(skb, padsize);
2603 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2604 }
2605
fa1c114f
JS		 2606 spin_lock_irqsave(&sc->txbuflock, flags);
2607 if (list_empty(&sc->txbuf)) {
2608 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2609 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2610 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2611 goto drop_packet;
fa1c114f
JS		 2612 }
2613 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2614 list_del(&bf->list);
2615 sc->txbuf_len--;
2616 if (list_empty(&sc->txbuf))
2617 ieee80211_stop_queues(hw);
2618 spin_unlock_irqrestore(&sc->txbuflock, flags);
2619
2620 bf->skb = skb;
2621
e039fa4a 2622 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2623 bf->skb = NULL;
2624 spin_lock_irqsave(&sc->txbuflock, flags);
2625 list_add_tail(&bf->list, &sc->txbuf);
2626 sc->txbuf_len++;
2627 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2628 goto drop_packet;
fa1c114f 2629 }
5a0fe8ac 2630 return NETDEV_TX_OK;
fa1c114f 2631
5a0fe8ac
BC		 2632drop_packet:
2633 dev_kfree_skb_any(skb);
71ef99c8 2634 return NETDEV_TX_OK;
fa1c114f
JS		 2635}
2636
209d889b
BC		 2637/*
2638 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2639 * and change to the given channel.
2640 */
fa1c114f 2641static int
209d889b 2642ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
fa1c114f 2643{
fa1c114f
JS		 2644 struct ath5k_hw *ah = sc->ah;
2645 int ret;
2646
2647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2648
209d889b 2649 if (chan) {
c6e387a2 2650 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2651 ath5k_txq_cleanup(sc);
2652 ath5k_rx_stop(sc);
209d889b
BC		 2653
2654 sc->curchan = chan;
2655 sc->curband = &sc->sbands[chan->band];
d7dc1003 2656 }
fa1c114f 2657 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2658 if (ret) {
fa1c114f
JS		 2659 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2660 goto err;
2661 }
d7dc1003 2662
fa1c114f 2663 ret = ath5k_rx_start(sc);
d7dc1003 2664 if (ret) {
fa1c114f
JS		 2665 ATH5K_ERR(sc, "can't start recv logic\n");
2666 goto err;
2667 }
d7dc1003 2668
fa1c114f 2669 /*
d7dc1003
JS		 2670 * Change channels and update the h/w rate map if we're switching;
2671 * e.g. 11a to 11b/g.
2672 *
2673 * We may be doing a reset in response to an ioctl that changes the
2674 * channel so update any state that might change as a result.
fa1c114f
JS		 2675 *
2676 * XXX needed?
2677 */
2678/* ath5k_chan_change(sc, c); */
fa1c114f 2679
d7dc1003
JS		 2680 ath5k_beacon_config(sc);
2681 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2682
2683 return 0;
2684err:
2685 return ret;
2686}
2687
d7dc1003
JS		 2688static int
2689ath5k_reset_wake(struct ath5k_softc *sc)
2690{
2691 int ret;
2692
209d889b 2693 ret = ath5k_reset(sc, sc->curchan);
d7dc1003
JS		 2694 if (!ret)
2695 ieee80211_wake_queues(sc->hw);
2696
2697 return ret;
2698}
2699
fa1c114f
JS		 2700static int ath5k_start(struct ieee80211_hw *hw)
2701{
bb2becac 2702 return ath5k_init(hw->priv);
fa1c114f
JS		 2703}
2704
2705static void ath5k_stop(struct ieee80211_hw *hw)
2706{
bb2becac 2707 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2708}
2709
2710static int ath5k_add_interface(struct ieee80211_hw *hw,
2711 struct ieee80211_if_init_conf *conf)
2712{
2713 struct ath5k_softc *sc = hw->priv;
2714 int ret;
2715
2716 mutex_lock(&sc->lock);
32bfd35d 2717 if (sc->vif) {
fa1c114f
JS		 2718 ret = 0;
2719 goto end;
2720 }
2721
32bfd35d 2722 sc->vif = conf->vif;
fa1c114f
JS		 2723
2724 switch (conf->type) {
da966bca 2725 case NL80211_IFTYPE_AP:
05c914fe
JB		 2726 case NL80211_IFTYPE_STATION:
2727 case NL80211_IFTYPE_ADHOC:
b706e65b 2728 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2729 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2730 sc->opmode = conf->type;
2731 break;
2732 default:
2733 ret = -EOPNOTSUPP;
2734 goto end;
2735 }
67d2e2df
JS		 2736
2737 /* Set to a reasonable value. Note that this will
2738 * be set to mac80211's value at ath5k_config(). */
2739 sc->bintval = 1000;
0e149cf5 2740 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2741
fa1c114f
JS		 2742 ret = 0;
2743end:
2744 mutex_unlock(&sc->lock);
2745 return ret;
2746}
2747
2748static void
2749ath5k_remove_interface(struct ieee80211_hw *hw,
2750 struct ieee80211_if_init_conf *conf)
2751{
2752 struct ath5k_softc *sc = hw->priv;
0e149cf5 2753 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2754
2755 mutex_lock(&sc->lock);
32bfd35d 2756 if (sc->vif != conf->vif)
fa1c114f
JS		 2757 goto end;
2758
0e149cf5 2759 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2760 sc->vif = NULL;
fa1c114f
JS		 2761end:
2762 mutex_unlock(&sc->lock);
2763}
2764
d8ee398d
LR		 2765/*
2766 * TODO: Phy disable/diversity etc
2767 */
fa1c114f 2768static int
e8975581 2769ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2770{
2771 struct ath5k_softc *sc = hw->priv;
a0823810 2772 struct ath5k_hw *ah = sc->ah;
e8975581 2773 struct ieee80211_conf *conf = &hw->conf;
2bed03eb 2774 int ret = 0;
be009370
BC		 2775
2776 mutex_lock(&sc->lock);
fa1c114f 2777
a0823810
NK		 2778 sc->bintval = conf->beacon_int;
2779
2bed03eb
NK		 2780 ret = ath5k_chan_set(sc, conf->channel);
2781 if (ret < 0)
2782 return ret;
2783
a0823810
NK		 2784 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2785 (sc->power_level != conf->power_level)) {
2786 sc->power_level = conf->power_level;
2787
2788 /* Half dB steps */
2789 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2790 }
fa1c114f 2791
2bed03eb
NK		 2792 /* TODO:
2793 * 1) Move this on config_interface and handle each case
2794 * separately eg. when we have only one STA vif, use
2795 * AR5K_ANTMODE_SINGLE_AP
2796 *
2797 * 2) Allow the user to change antenna mode eg. when only
2798 * one antenna is present
2799 *
2800 * 3) Allow the user to set default/tx antenna when possible
2801 *
2802 * 4) Default mode should handle 90% of the cases, together
2803 * with fixed a/b and single AP modes we should be able to
2804 * handle 99%. Sectored modes are extreme cases and i still
2805 * haven't found a usage for them. If we decide to support them,
2806 * then we must allow the user to set how many tx antennas we
2807 * have available
2808 */
2809 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
be009370
BC		 2810
2811 mutex_unlock(&sc->lock);
2bed03eb 2812 return 0;
fa1c114f
JS		 2813}
2814
fa1c114f
JS		 2815#define SUPPORTED_FIF_FLAGS \
2816 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2817 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2818 FIF_BCN_PRBRESP_PROMISC
2819/*
2820 * o always accept unicast, broadcast, and multicast traffic
2821 * o multicast traffic for all BSSIDs will be enabled if mac80211
2822 * says it should be
2823 * o maintain current state of phy ofdm or phy cck error reception.
2824 * If the hardware detects any of these type of errors then
2825 * ath5k_hw_get_rx_filter() will pass to us the respective
2826 * hardware filters to be able to receive these type of frames.
2827 * o probe request frames are accepted only when operating in
2828 * hostap, adhoc, or monitor modes
2829 * o enable promiscuous mode according to the interface state
2830 * o accept beacons:
2831 * - when operating in adhoc mode so the 802.11 layer creates
2832 * node table entries for peers,
2833 * - when operating in station mode for collecting rssi data when
2834 * the station is otherwise quiet, or
2835 * - when scanning
2836 */
2837static void ath5k_configure_filter(struct ieee80211_hw *hw,
2838 unsigned int changed_flags,
2839 unsigned int *new_flags,
2840 int mc_count, struct dev_mc_list *mclist)
2841{
2842 struct ath5k_softc *sc = hw->priv;
2843 struct ath5k_hw *ah = sc->ah;
2844 u32 mfilt[2], val, rfilt;
2845 u8 pos;
2846 int i;
2847
2848 mfilt[0] = 0;
2849 mfilt[1] = 0;
2850
2851 /* Only deal with supported flags */
2852 changed_flags &= SUPPORTED_FIF_FLAGS;
2853 *new_flags &= SUPPORTED_FIF_FLAGS;
2854
2855 /* If HW detects any phy or radar errors, leave those filters on.
2856 * Also, always enable Unicast, Broadcasts and Multicast
2857 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2858 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2859 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2860 AR5K_RX_FILTER_MCAST);
2861
2862 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2863 if (*new_flags & FIF_PROMISC_IN_BSS) {
2864 rfilt |= AR5K_RX_FILTER_PROM;
2865 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2866 } else {
fa1c114f 2867 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2868 }
fa1c114f
JS		 2869 }
2870
2871 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2872 if (*new_flags & FIF_ALLMULTI) {
2873 mfilt[0] = ~0;
2874 mfilt[1] = ~0;
2875 } else {
2876 for (i = 0; i < mc_count; i++) {
2877 if (!mclist)
2878 break;
2879 /* calculate XOR of eight 6-bit values */
533dd1b0 2880 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2881 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2882 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2883 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2884 pos &= 0x3f;
2885 mfilt[pos / 32] |= (1 << (pos % 32));
2886 /* XXX: we might be able to just do this instead,
2887 * but not sure, needs testing, if we do use this we'd
2888 * neet to inform below to not reset the mcast */
2889 /* ath5k_hw_set_mcast_filterindex(ah,
2890 * mclist->dmi_addr[5]); */
2891 mclist = mclist->next;
2892 }
2893 }
2894
2895 /* This is the best we can do */
2896 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2897 rfilt |= AR5K_RX_FILTER_PHYERR;
2898
2899 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2900 * and probes for any BSSID, this needs testing */
2901 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2902 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2903
2904 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2905 * set we should only pass on control frames for this
2906 * station. This needs testing. I believe right now this
2907 * enables *all* control frames, which is OK.. but
2908 * but we should see if we can improve on granularity */
2909 if (*new_flags & FIF_CONTROL)
2910 rfilt |= AR5K_RX_FILTER_CONTROL;
2911
2912 /* Additional settings per mode -- this is per ath5k */
2913
2914 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2915
05c914fe 2916 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2917 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2918 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2919 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2920 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2921 if (sc->opmode != NL80211_IFTYPE_AP &&
2922 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2923 test_bit(ATH_STAT_PROMISC, sc->status))
2924 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2925 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2926 sc->opmode == NL80211_IFTYPE_ADHOC ||
2927 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2928 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2929 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2930 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2931 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2932
2933 /* Set filters */
0bbac08f 2934 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2935
2936 /* Set multicast bits */
2937 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2938 /* Set the cached hw filter flags, this will alter actually
2939 * be set in HW */
2940 sc->filter_flags = rfilt;
2941}
2942
2943static int
2944ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2945 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2946 struct ieee80211_key_conf *key)
fa1c114f
JS		 2947{
2948 struct ath5k_softc *sc = hw->priv;
2949 int ret = 0;
2950
9ad9a26e
BC		 2951 if (modparam_nohwcrypt)
2952 return -EOPNOTSUPP;
2953
0bbac08f 2954 switch (key->alg) {
fa1c114f 2955 case ALG_WEP:
fa1c114f 2956 case ALG_TKIP:
3f64b435 2957 break;
fa1c114f
JS		 2958 case ALG_CCMP:
2959 return -EOPNOTSUPP;
2960 default:
2961 WARN_ON(1);
2962 return -EINVAL;
2963 }
2964
2965 mutex_lock(&sc->lock);
2966
2967 switch (cmd) {
2968 case SET_KEY:
dc822b5d
JB		 2969 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2970 sta ? sta->addr : NULL);
fa1c114f
JS		 2971 if (ret) {
2972 ATH5K_ERR(sc, "can't set the key\n");
2973 goto unlock;
2974 }
2975 __set_bit(key->keyidx, sc->keymap);
2976 key->hw_key_idx = key->keyidx;
3f64b435
BC		 2977 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2978 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 2979 break;
2980 case DISABLE_KEY:
2981 ath5k_hw_reset_key(sc->ah, key->keyidx);
2982 __clear_bit(key->keyidx, sc->keymap);
2983 break;
2984 default:
2985 ret = -EINVAL;
2986 goto unlock;
2987 }
2988
2989unlock:
274c7c36 2990 mmiowb();
fa1c114f
JS		 2991 mutex_unlock(&sc->lock);
2992 return ret;
2993}
2994
2995static int
2996ath5k_get_stats(struct ieee80211_hw *hw,
2997 struct ieee80211_low_level_stats *stats)
2998{
2999 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 3000 struct ath5k_hw *ah = sc->ah;
3001
3002 /* Force update */
3003 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 3004
3005 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3006
3007 return 0;
3008}
3009
3010static int
3011ath5k_get_tx_stats(struct ieee80211_hw *hw,
3012 struct ieee80211_tx_queue_stats *stats)
3013{
3014 struct ath5k_softc *sc = hw->priv;
3015
3016 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3017
3018 return 0;
3019}
3020
3021static u64
3022ath5k_get_tsf(struct ieee80211_hw *hw)
3023{
3024 struct ath5k_softc *sc = hw->priv;
3025
3026 return ath5k_hw_get_tsf64(sc->ah);
3027}
3028
3b5d665b
AF		 3029static void
3030ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3031{
3032 struct ath5k_softc *sc = hw->priv;
3033
3034 ath5k_hw_set_tsf64(sc->ah, tsf);
3035}
3036
fa1c114f
JS		 3037static void
3038ath5k_reset_tsf(struct ieee80211_hw *hw)
3039{
3040 struct ath5k_softc *sc = hw->priv;
3041
9804b98d
BR		 3042 /*
3043 * in IBSS mode we need to update the beacon timers too.
3044 * this will also reset the TSF if we call it with 0
3045 */
05c914fe 3046 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3047 ath5k_beacon_update_timers(sc, 0);
3048 else
3049 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3050}
3051
1071db86
BC		 3052/*
3053 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3054 * this is called only once at config_bss time, for AP we do it every
3055 * SWBA interrupt so that the TIM will reflect buffered frames.
3056 *
3057 * Called with the beacon lock.
3058 */
fa1c114f 3059static int
1071db86 3060ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
fa1c114f 3061{
fa1c114f 3062 int ret;
1071db86
BC		 3063 struct ath5k_softc *sc = hw->priv;
3064 struct sk_buff *skb = ieee80211_beacon_get(hw, vif);
3065
3066 if (!skb) {
3067 ret = -ENOMEM;
3068 goto out;
3069 }
fa1c114f
JS		 3070
3071 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3072
fa1c114f
JS		 3073 ath5k_txbuf_free(sc, sc->bbuf);
3074 sc->bbuf->skb = skb;
e039fa4a 3075 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3076 if (ret)
3077 sc->bbuf->skb = NULL;
1071db86
BC		 3078out:
3079 return ret;
3080}
3081
3082/*
3083 * Update the beacon and reconfigure the beacon queues.
3084 */
3085static void
3086ath5k_beacon_reconfig(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3087{
3088 int ret;
3089 unsigned long flags;
3090 struct ath5k_softc *sc = hw->priv;
3091
3092 spin_lock_irqsave(&sc->block, flags);
3093 ret = ath5k_beacon_update(hw, vif);
00482973 3094 spin_unlock_irqrestore(&sc->block, flags);
1071db86 3095 if (ret == 0) {
fa1c114f 3096 ath5k_beacon_config(sc);
274c7c36
JS		 3097 mmiowb();
3098 }
fa1c114f 3099}
1071db86 3100
02969b38
MX		 3101static void
3102set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3103{
3104 struct ath5k_softc *sc = hw->priv;
3105 struct ath5k_hw *ah = sc->ah;
3106 u32 rfilt;
3107 rfilt = ath5k_hw_get_rx_filter(ah);
3108 if (enable)
3109 rfilt |= AR5K_RX_FILTER_BEACON;
3110 else
3111 rfilt &= ~AR5K_RX_FILTER_BEACON;
3112 ath5k_hw_set_rx_filter(ah, rfilt);
3113 sc->filter_flags = rfilt;
3114}
fa1c114f 3115
02969b38
MX		 3116static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3117 struct ieee80211_vif *vif,
3118 struct ieee80211_bss_conf *bss_conf,
3119 u32 changes)
3120{
3121 struct ath5k_softc *sc = hw->priv;
2d0ddec5
JB		 3122 struct ath5k_hw *ah = sc->ah;
3123
3124 mutex_lock(&sc->lock);
3125 if (WARN_ON(sc->vif != vif))
3126 goto unlock;
3127
3128 if (changes & BSS_CHANGED_BSSID) {
3129 /* Cache for later use during resets */
3130 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3131 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3132 * a clean way of letting us retrieve this yet. */
3133 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3134 mmiowb();
3135 }
57c4d7b4
JB		 3136
3137 if (changes & BSS_CHANGED_BEACON_INT)
3138 sc->bintval = bss_conf->beacon_int;
3139
02969b38 3140 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3141 sc->assoc = bss_conf->assoc;
3142 if (sc->opmode == NL80211_IFTYPE_STATION)
3143 set_beacon_filter(hw, sc->assoc);
02969b38 3144 }
2d0ddec5
JB		 3145
3146 if (changes & BSS_CHANGED_BEACON &&
3147 (vif->type == NL80211_IFTYPE_ADHOC ||
3148 vif->type == NL80211_IFTYPE_MESH_POINT ||
3149 vif->type == NL80211_IFTYPE_AP)) {
1071db86 3150 ath5k_beacon_reconfig(hw, vif);
2d0ddec5
JB		 3151 }
3152
3153 unlock:
3154 mutex_unlock(&sc->lock);
02969b38 3155}
Clone of davem's net-next-2.6 tree