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drivers/net: Remove deprecated use of pci_module_init()
[net-next-2.6.git] / drivers / net / wan / pc300_drv.c
CommitLineData
1da177e4
LT		 1#define USE_PCI_CLOCK
2static char rcsid[] =
3"Revision: 3.4.5 Date: 2002/03/07 ";
4
5/*
6 * pc300.c Cyclades-PC300(tm) Driver.
7 *
8 * Author: Ivan Passos <ivan@cyclades.com>
9 * Maintainer: PC300 Maintainer <pc300@cyclades.com>
10 *
11 * Copyright: (c) 1999-2003 Cyclades Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * Using tabstop = 4.
19 *
20 * $Log: pc300_drv.c,v $
21 * Revision 3.23 2002/03/20 13:58:40 henrique
22 * Fixed ortographic mistakes
23 *
24 * Revision 3.22 2002/03/13 16:56:56 henrique
25 * Take out the debug messages
26 *
27 * Revision 3.21 2002/03/07 14:17:09 henrique
28 * License data fixed
29 *
30 * Revision 3.20 2002/01/17 17:58:52 ivan
31 * Support for PC300-TE/M (PMC).
32 *
33 * Revision 3.19 2002/01/03 17:08:47 daniela
34 * Enables DMA reception when the SCA-II disables it improperly.
35 *
36 * Revision 3.18 2001/12/03 18:47:50 daniela
37 * Esthetic changes.
38 *
39 * Revision 3.17 2001/10/19 16:50:13 henrique
40 * Patch to kernel 2.4.12 and new generic hdlc.
41 *
42 * Revision 3.16 2001/10/16 15:12:31 regina
43 * clear statistics
44 *
45 * Revision 3.11 to 3.15 2001/10/11 20:26:04 daniela
46 * More DMA fixes for noisy lines.
47 * Return the size of bad frames in dma_get_rx_frame_size, so that the Rx buffer
48 * descriptors can be cleaned by dma_buf_read (called in cpc_net_rx).
49 * Renamed dma_start routine to rx_dma_start. Improved Rx statistics.
50 * Fixed BOF interrupt treatment. Created dma_start routine.
51 * Changed min and max to cpc_min and cpc_max.
52 *
53 * Revision 3.10 2001/08/06 12:01:51 regina
54 * Fixed problem in DSR_DE bit.
55 *
56 * Revision 3.9 2001/07/18 19:27:26 daniela
57 * Added some history comments.
58 *
59 * Revision 3.8 2001/07/12 13:11:19 regina
60 * bug fix - DCD-OFF in pc300 tty driver
61 *
62 * Revision 3.3 to 3.7 2001/07/06 15:00:20 daniela
63 * Removing kernel 2.4.3 and previous support.
64 * DMA transmission bug fix.
65 * MTU check in cpc_net_rx fixed.
66 * Boot messages reviewed.
67 * New configuration parameters (line code, CRC calculation and clock).
68 *
69 * Revision 3.2 2001/06/22 13:13:02 regina
70 * MLPPP implementation. Changed the header of message trace to include
71 * the device name. New format : "hdlcX[R/T]: ".
72 * Default configuration changed.
73 *
74 * Revision 3.1 2001/06/15 regina
75 * in cpc_queue_xmit, netif_stop_queue is called if don't have free descriptor
76 * upping major version number
77 *
78 * Revision 1.1.1.1 2001/06/13 20:25:04 daniela
79 * PC300 initial CVS version (3.4.0-pre1)
80 *
81 * Revision 3.0.1.2 2001/06/08 daniela
82 * Did some changes in the DMA programming implementation to avoid the
83 * occurrence of a SCA-II bug when CDA is accessed during a DMA transfer.
84 *
85 * Revision 3.0.1.1 2001/05/02 daniela
86 * Added kernel 2.4.3 support.
87 *
88 * Revision 3.0.1.0 2001/03/13 daniela, henrique
89 * Added Frame Relay Support.
90 * Driver now uses HDLC generic driver to provide protocol support.
91 *
92 * Revision 3.0.0.8 2001/03/02 daniela
93 * Fixed ram size detection.
94 * Changed SIOCGPC300CONF ioctl, to give hw information to pc300util.
95 *
96 * Revision 3.0.0.7 2001/02/23 daniela
97 * netif_stop_queue called before the SCA-II transmition commands in
98 * cpc_queue_xmit, and with interrupts disabled to avoid race conditions with
99 * transmition interrupts.
100 * Fixed falc_check_status for Unframed E1.
101 *
102 * Revision 3.0.0.6 2000/12/13 daniela
103 * Implemented pc300util support: trace, statistics, status and loopback
104 * tests for the PC300 TE boards.
105 *
106 * Revision 3.0.0.5 2000/12/12 ivan
107 * Added support for Unframed E1.
108 * Implemented monitor mode.
109 * Fixed DCD sensitivity on the second channel.
110 * Driver now complies with new PCI kernel architecture.
111 *
112 * Revision 3.0.0.4 2000/09/28 ivan
113 * Implemented DCD sensitivity.
114 * Moved hardware-specific open to the end of cpc_open, to avoid race
115 * conditions with early reception interrupts.
116 * Included code for [request|release]_mem_region().
117 * Changed location of pc300.h .
118 * Minor code revision (contrib. of Jeff Garzik).
119 *
120 * Revision 3.0.0.3 2000/07/03 ivan
121 * Previous bugfix for the framing errors with external clock made X21
122 * boards stop working. This version fixes it.
123 *
124 * Revision 3.0.0.2 2000/06/23 ivan
125 * Revisited cpc_queue_xmit to prevent race conditions on Tx DMA buffer
126 * handling when Tx timeouts occur.
127 * Revisited Rx statistics.
128 * Fixed a bug in the SCA-II programming that would cause framing errors
129 * when external clock was configured.
130 *
131 * Revision 3.0.0.1 2000/05/26 ivan
132 * Added logic in the SCA interrupt handler so that no board can monopolize
133 * the driver.
134 * Request PLX I/O region, although driver doesn't use it, to avoid
135 * problems with other drivers accessing it.
136 *
137 * Revision 3.0.0.0 2000/05/15 ivan
138 * Did some changes in the DMA programming implementation to avoid the
139 * occurrence of a SCA-II bug in the second channel.
140 * Implemented workaround for PLX9050 bug that would cause a system lockup
141 * in certain systems, depending on the MMIO addresses allocated to the
142 * board.
143 * Fixed the FALC chip programming to avoid synchronization problems in the
144 * second channel (TE only).
145 * Implemented a cleaner and faster Tx DMA descriptor cleanup procedure in
146 * cpc_queue_xmit().
147 * Changed the built-in driver implementation so that the driver can use the
148 * general 'hdlcN' naming convention instead of proprietary device names.
149 * Driver load messages are now device-centric, instead of board-centric.
150 * Dynamic allocation of net_device structures.
151 * Code is now compliant with the new module interface (module_[init|exit]).
152 * Make use of the PCI helper functions to access PCI resources.
153 *
154 * Revision 2.0.0.0 2000/04/15 ivan
155 * Added support for the PC300/TE boards (T1/FT1/E1/FE1).
156 *
157 * Revision 1.1.0.0 2000/02/28 ivan
158 * Major changes in the driver architecture.
159 * Softnet compliancy implemented.
160 * Driver now reports physical instead of virtual memory addresses.
161 * Added cpc_change_mtu function.
162 *
163 * Revision 1.0.0.0 1999/12/16 ivan
164 * First official release.
165 * Support for 1- and 2-channel boards (which use distinct PCI Device ID's).
166 * Support for monolythic installation (i.e., drv built into the kernel).
167 * X.25 additional checking when lapb_[dis]connect_request returns an error.
168 * SCA programming now covers X.21 as well.
169 *
170 * Revision 0.3.1.0 1999/11/18 ivan
171 * Made X.25 support configuration-dependent (as it depends on external
172 * modules to work).
173 * Changed X.25-specific function names to comply with adopted convention.
174 * Fixed typos in X.25 functions that would cause compile errors (Daniela).
175 * Fixed bug in ch_config that would disable interrupts on a previously
176 * enabled channel if the other channel on the same board was enabled later.
177 *
178 * Revision 0.3.0.0 1999/11/16 daniela
179 * X.25 support.
180 *
181 * Revision 0.2.3.0 1999/11/15 ivan
182 * Function cpc_ch_status now provides more detailed information.
183 * Added support for X.21 clock configuration.
184 * Changed TNR1 setting in order to prevent Tx FIFO overaccesses by the SCA.
185 * Now using PCI clock instead of internal oscillator clock for the SCA.
186 *
187 * Revision 0.2.2.0 1999/11/10 ivan
188 * Changed the *_dma_buf_check functions so that they would print only
189 * the useful info instead of the whole buffer descriptor bank.
190 * Fixed bug in cpc_queue_xmit that would eventually crash the system
191 * in case of a packet drop.
192 * Implemented TX underrun handling.
193 * Improved SCA fine tuning to boost up its performance.
194 *
195 * Revision 0.2.1.0 1999/11/03 ivan
196 * Added functions *dma_buf_pt_init to allow independent initialization
197 * of the next-descr. and DMA buffer pointers on the DMA descriptors.
198 * Kernel buffer release and tbusy clearing is now done in the interrupt
199 * handler.
200 * Fixed bug in cpc_open that would cause an interface reopen to fail.
201 * Added a protocol-specific code section in cpc_net_rx.
202 * Removed printk level defs (they might be added back after the beta phase).
203 *
204 * Revision 0.2.0.0 1999/10/28 ivan
205 * Revisited the code so that new protocols can be easily added / supported.
206 *
207 * Revision 0.1.0.1 1999/10/20 ivan
208 * Mostly "esthetic" changes.
209 *
210 * Revision 0.1.0.0 1999/10/11 ivan
211 * Initial version.
212 *
213 */
214
215#include <linux/module.h>
216#include <linux/kernel.h>
217#include <linux/mm.h>
218#include <linux/ioport.h>
219#include <linux/pci.h>
220#include <linux/errno.h>
221#include <linux/string.h>
222#include <linux/init.h>
223#include <linux/delay.h>
224#include <linux/net.h>
225#include <linux/skbuff.h>
226#include <linux/if_arp.h>
227#include <linux/netdevice.h>
228#include <linux/spinlock.h>
229#include <linux/if.h>
230
231#include <net/syncppp.h>
232#include <net/arp.h>
233
234#include <asm/io.h>
235#include <asm/uaccess.h>
236
237#include "pc300.h"
238
239#define CPC_LOCK(card,flags) \
240 do { \
241 spin_lock_irqsave(&card->card_lock, flags); \
242 } while (0)
243
244#define CPC_UNLOCK(card,flags) \
245 do { \
246 spin_unlock_irqrestore(&card->card_lock, flags); \
247 } while (0)
248
249#undef PC300_DEBUG_PCI
250#undef PC300_DEBUG_INTR
251#undef PC300_DEBUG_TX
252#undef PC300_DEBUG_RX
253#undef PC300_DEBUG_OTHER
254
255static struct pci_device_id cpc_pci_dev_id[] __devinitdata = {
256 /* PC300/RSV or PC300/X21, 2 chan */
257 {0x120e, 0x300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x300},
258 /* PC300/RSV or PC300/X21, 1 chan */
259 {0x120e, 0x301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x301},
260 /* PC300/TE, 2 chan */
261 {0x120e, 0x310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x310},
262 /* PC300/TE, 1 chan */
263 {0x120e, 0x311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x311},
264 /* PC300/TE-M, 2 chan */
265 {0x120e, 0x320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x320},
266 /* PC300/TE-M, 1 chan */
267 {0x120e, 0x321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0x321},
268 /* End of table */
269 {0,},
270};
271MODULE_DEVICE_TABLE(pci, cpc_pci_dev_id);
272
273#ifndef cpc_min
274#define cpc_min(a,b) (((a)<(b))?(a):(b))
275#endif
276#ifndef cpc_max
277#define cpc_max(a,b) (((a)>(b))?(a):(b))
278#endif
279
280/* prototypes */
281static void tx_dma_buf_pt_init(pc300_t *, int);
282static void tx_dma_buf_init(pc300_t *, int);
283static void rx_dma_buf_pt_init(pc300_t *, int);
284static void rx_dma_buf_init(pc300_t *, int);
285static void tx_dma_buf_check(pc300_t *, int);
286static void rx_dma_buf_check(pc300_t *, int);
287static irqreturn_t cpc_intr(int, void *, struct pt_regs *);
288static struct net_device_stats *cpc_get_stats(struct net_device *);
289static int clock_rate_calc(uclong, uclong, int *);
290static uclong detect_ram(pc300_t *);
291static void plx_init(pc300_t *);
292static void cpc_trace(struct net_device *, struct sk_buff *, char);
293static int cpc_attach(struct net_device *, unsigned short, unsigned short);
7665a089 294static int cpc_close(struct net_device *dev);
1da177e4
LT		 295
296#ifdef CONFIG_PC300_MLPPP
297void cpc_tty_init(pc300dev_t * dev);
298void cpc_tty_unregister_service(pc300dev_t * pc300dev);
299void cpc_tty_receive(pc300dev_t * pc300dev);
300void cpc_tty_trigger_poll(pc300dev_t * pc300dev);
301void cpc_tty_reset_var(void);
302#endif
303
304/************************/
305/*** DMA Routines ***/
306/************************/
307static void tx_dma_buf_pt_init(pc300_t * card, int ch)
308{
309 int i;
310 int ch_factor = ch * N_DMA_TX_BUF;
311 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
312 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
313
314 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
315 cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
316 (ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
317 cpc_writel(&ptdescr->ptbuf,
318 (uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
319 }
320}
321
322static void tx_dma_buf_init(pc300_t * card, int ch)
323{
324 int i;
325 int ch_factor = ch * N_DMA_TX_BUF;
326 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
327 + DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
328
329 for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
330 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
331 cpc_writew(&ptdescr->len, 0);
332 cpc_writeb(&ptdescr->status, DST_OSB);
333 }
334 tx_dma_buf_pt_init(card, ch);
335}
336
337static void rx_dma_buf_pt_init(pc300_t * card, int ch)
338{
339 int i;
340 int ch_factor = ch * N_DMA_RX_BUF;
341 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
342 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
343
344 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
345 cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
346 (ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
347 cpc_writel(&ptdescr->ptbuf,
348 (uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
349 }
350}
351
352static void rx_dma_buf_init(pc300_t * card, int ch)
353{
354 int i;
355 int ch_factor = ch * N_DMA_RX_BUF;
356 volatile pcsca_bd_t __iomem *ptdescr = (card->hw.rambase
357 + DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
358
359 for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
360 memset_io(ptdescr, 0, sizeof(pcsca_bd_t));
361 cpc_writew(&ptdescr->len, 0);
362 cpc_writeb(&ptdescr->status, 0);
363 }
364 rx_dma_buf_pt_init(card, ch);
365}
366
367static void tx_dma_buf_check(pc300_t * card, int ch)
368{
369 volatile pcsca_bd_t __iomem *ptdescr;
370 int i;
371 ucshort first_bd = card->chan[ch].tx_first_bd;
372 ucshort next_bd = card->chan[ch].tx_next_bd;
373
374 printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
375 first_bd, TX_BD_ADDR(ch, first_bd),
376 next_bd, TX_BD_ADDR(ch, next_bd));
377 for (i = first_bd,
378 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, first_bd));
379 i != ((next_bd + 1) & (N_DMA_TX_BUF - 1));
380 i = (i + 1) & (N_DMA_TX_BUF - 1),
381 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i))) {
382 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
383 ch, i, cpc_readl(&ptdescr->next),
384 cpc_readl(&ptdescr->ptbuf),
385 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
386 }
387 printk("\n");
388}
389
390#ifdef PC300_DEBUG_OTHER
391/* Show all TX buffer descriptors */
392static void tx1_dma_buf_check(pc300_t * card, int ch)
393{
394 volatile pcsca_bd_t __iomem *ptdescr;
395 int i;
396 ucshort first_bd = card->chan[ch].tx_first_bd;
397 ucshort next_bd = card->chan[ch].tx_next_bd;
398 uclong scabase = card->hw.scabase;
399
400 printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
401 printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
402 first_bd, TX_BD_ADDR(ch, first_bd),
403 next_bd, TX_BD_ADDR(ch, next_bd));
404 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
405 cpc_readl(scabase + DTX_REG(CDAL, ch)),
406 cpc_readl(scabase + DTX_REG(EDAL, ch)));
407 for (i = 0; i < N_DMA_TX_BUF; i++) {
408 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch, i));
409 printk("\n CH%d TX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
410 ch, i, cpc_readl(&ptdescr->next),
411 cpc_readl(&ptdescr->ptbuf),
412 cpc_readb(&ptdescr->status), cpc_readw(&ptdescr->len));
413 }
414 printk("\n");
415}
416#endif
417
418static void rx_dma_buf_check(pc300_t * card, int ch)
419{
420 volatile pcsca_bd_t __iomem *ptdescr;
421 int i;
422 ucshort first_bd = card->chan[ch].rx_first_bd;
423 ucshort last_bd = card->chan[ch].rx_last_bd;
424 int ch_factor;
425
426 ch_factor = ch * N_DMA_RX_BUF;
427 printk("#CH%d: f_bd = %d, l_bd = %d\n", ch, first_bd, last_bd);
428 for (i = 0, ptdescr = (card->hw.rambase +
429 DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
430 i < N_DMA_RX_BUF; i++, ptdescr++) {
431 if (cpc_readb(&ptdescr->status) & DST_OSB)
432 printk ("\n CH%d RX%d: next=0x%x, ptbuf=0x%x, ST=0x%x, len=%d",
433 ch, i, cpc_readl(&ptdescr->next),
434 cpc_readl(&ptdescr->ptbuf),
435 cpc_readb(&ptdescr->status),
436 cpc_readw(&ptdescr->len));
437 }
438 printk("\n");
439}
440
7665a089 441static int dma_get_rx_frame_size(pc300_t * card, int ch)
1da177e4
LT		 442{
443 volatile pcsca_bd_t __iomem *ptdescr;
444 ucshort first_bd = card->chan[ch].rx_first_bd;
445 int rcvd = 0;
446 volatile ucchar status;
447
448 ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
449 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
450 rcvd += cpc_readw(&ptdescr->len);
451 first_bd = (first_bd + 1) & (N_DMA_RX_BUF - 1);
452 if ((status & DST_EOM) || (first_bd == card->chan[ch].rx_last_bd)) {
453 /* Return the size of a good frame or incomplete bad frame
454 * (dma_buf_read will clean the buffer descriptors in this case). */
455 return (rcvd);
456 }
457 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
458 }
459 return (-1);
460}
461
462/*
463 * dma_buf_write: writes a frame to the Tx DMA buffers
464 * NOTE: this function writes one frame at a time.
465 */
7665a089 466static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
1da177e4
LT		 467{
468 int i, nchar;
469 volatile pcsca_bd_t __iomem *ptdescr;
470 int tosend = len;
471 ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
472
473 if (nbuf >= card->chan[ch].nfree_tx_bd) {
474 return -ENOMEM;
475 }
476
477 for (i = 0; i < nbuf; i++) {
478 ptdescr = (card->hw.rambase +
479 TX_BD_ADDR(ch, card->chan[ch].tx_next_bd));
480 nchar = cpc_min(BD_DEF_LEN, tosend);
481 if (cpc_readb(&ptdescr->status) & DST_OSB) {
482 memcpy_toio((card->hw.rambase + cpc_readl(&ptdescr->ptbuf)),
483 &ptdata[len - tosend], nchar);
484 cpc_writew(&ptdescr->len, nchar);
485 card->chan[ch].nfree_tx_bd--;
486 if ((i + 1) == nbuf) {
487 /* This must be the last BD to be used */
488 cpc_writeb(&ptdescr->status, DST_EOM);
489 } else {
490 cpc_writeb(&ptdescr->status, 0);
491 }
492 } else {
493 return -ENOMEM;
494 }
495 tosend -= nchar;
496 card->chan[ch].tx_next_bd =
497 (card->chan[ch].tx_next_bd + 1) & (N_DMA_TX_BUF - 1);
498 }
499 /* If it gets to here, it means we have sent the whole frame */
500 return 0;
501}
502
503/*
504 * dma_buf_read: reads a frame from the Rx DMA buffers
505 * NOTE: this function reads one frame at a time.
506 */
7665a089 507static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
1da177e4
LT		 508{
509 int nchar;
510 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
511 volatile pcsca_bd_t __iomem *ptdescr;
512 int rcvd = 0;
513 volatile ucchar status;
514
515 ptdescr = (card->hw.rambase +
516 RX_BD_ADDR(ch, chan->rx_first_bd));
517 while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
518 nchar = cpc_readw(&ptdescr->len);
519 if ((status & (DST_OVR | DST_CRC | DST_RBIT | DST_SHRT | DST_ABT))
520 || (nchar > BD_DEF_LEN)) {
521
522 if (nchar > BD_DEF_LEN)
523 status |= DST_RBIT;
524 rcvd = -status;
525 /* Discard remaining descriptors used by the bad frame */
526 while (chan->rx_first_bd != chan->rx_last_bd) {
527 cpc_writeb(&ptdescr->status, 0);
528 chan->rx_first_bd = (chan->rx_first_bd+1) & (N_DMA_RX_BUF-1);
529 if (status & DST_EOM)
530 break;
531 ptdescr = (card->hw.rambase +
532 cpc_readl(&ptdescr->next));
533 status = cpc_readb(&ptdescr->status);
534 }
535 break;
536 }
537 if (nchar != 0) {
538 if (skb) {
539 memcpy_fromio(skb_put(skb, nchar),
540 (card->hw.rambase+cpc_readl(&ptdescr->ptbuf)),nchar);
541 }
542 rcvd += nchar;
543 }
544 cpc_writeb(&ptdescr->status, 0);
545 cpc_writeb(&ptdescr->len, 0);
546 chan->rx_first_bd = (chan->rx_first_bd + 1) & (N_DMA_RX_BUF - 1);
547
548 if (status & DST_EOM)
549 break;
550
551 ptdescr = (card->hw.rambase + cpc_readl(&ptdescr->next));
552 }
553
554 if (rcvd != 0) {
555 /* Update pointer */
556 chan->rx_last_bd = (chan->rx_first_bd - 1) & (N_DMA_RX_BUF - 1);
557 /* Update EDA */
558 cpc_writel(card->hw.scabase + DRX_REG(EDAL, ch),
559 RX_BD_ADDR(ch, chan->rx_last_bd));
560 }
561 return (rcvd);
562}
563
7665a089 564static void tx_dma_stop(pc300_t * card, int ch)
1da177e4
LT		 565{
566 void __iomem *scabase = card->hw.scabase;
567 ucchar drr_ena_bit = 1 << (5 + 2 * ch);
568 ucchar drr_rst_bit = 1 << (1 + 2 * ch);
569
570 /* Disable DMA */
571 cpc_writeb(scabase + DRR, drr_ena_bit);
572 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
573}
574
7665a089 575static void rx_dma_stop(pc300_t * card, int ch)
1da177e4
LT		 576{
577 void __iomem *scabase = card->hw.scabase;
578 ucchar drr_ena_bit = 1 << (4 + 2 * ch);
579 ucchar drr_rst_bit = 1 << (2 * ch);
580
581 /* Disable DMA */
582 cpc_writeb(scabase + DRR, drr_ena_bit);
583 cpc_writeb(scabase + DRR, drr_rst_bit & ~drr_ena_bit);
584}
585
7665a089 586static void rx_dma_start(pc300_t * card, int ch)
1da177e4
LT		 587{
588 void __iomem *scabase = card->hw.scabase;
589 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
590
591 /* Start DMA */
592 cpc_writel(scabase + DRX_REG(CDAL, ch),
593 RX_BD_ADDR(ch, chan->rx_first_bd));
594 if (cpc_readl(scabase + DRX_REG(CDAL,ch)) !=
595 RX_BD_ADDR(ch, chan->rx_first_bd)) {
596 cpc_writel(scabase + DRX_REG(CDAL, ch),
597 RX_BD_ADDR(ch, chan->rx_first_bd));
598 }
599 cpc_writel(scabase + DRX_REG(EDAL, ch),
600 RX_BD_ADDR(ch, chan->rx_last_bd));
601 cpc_writew(scabase + DRX_REG(BFLL, ch), BD_DEF_LEN);
602 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
603 if (!(cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
604 cpc_writeb(scabase + DSR_RX(ch), DSR_DE);
605 }
606}
607
608/*************************/
609/*** FALC Routines ***/
610/*************************/
7665a089 611static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
1da177e4
LT		 612{
613 void __iomem *falcbase = card->hw.falcbase;
614 unsigned long i = 0;
615
616 while (cpc_readb(falcbase + F_REG(SIS, ch)) & SIS_CEC) {
617 if (i++ >= PC300_FALC_MAXLOOP) {
618 printk("%s: FALC command locked(cmd=0x%x).\n",
619 card->chan[ch].d.name, cmd);
620 break;
621 }
622 }
623 cpc_writeb(falcbase + F_REG(CMDR, ch), cmd);
624}
625
7665a089 626static void falc_intr_enable(pc300_t * card, int ch)
1da177e4
LT		 627{
628 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
629 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
630 falc_t *pfalc = (falc_t *) & chan->falc;
631 void __iomem *falcbase = card->hw.falcbase;
632
633 /* Interrupt pins are open-drain */
634 cpc_writeb(falcbase + F_REG(IPC, ch),
635 cpc_readb(falcbase + F_REG(IPC, ch)) & ~IPC_IC0);
636 /* Conters updated each second */
637 cpc_writeb(falcbase + F_REG(FMR1, ch),
638 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_ECM);
639 /* Enable SEC and ES interrupts */
640 cpc_writeb(falcbase + F_REG(IMR3, ch),
641 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~(IMR3_SEC | IMR3_ES));
642 if (conf->fr_mode == PC300_FR_UNFRAMED) {
643 cpc_writeb(falcbase + F_REG(IMR4, ch),
644 cpc_readb(falcbase + F_REG(IMR4, ch)) & ~(IMR4_LOS));
645 } else {
646 cpc_writeb(falcbase + F_REG(IMR4, ch),
647 cpc_readb(falcbase + F_REG(IMR4, ch)) &
648 ~(IMR4_LFA | IMR4_AIS | IMR4_LOS | IMR4_SLIP));
649 }
650 if (conf->media == IF_IFACE_T1) {
651 cpc_writeb(falcbase + F_REG(IMR3, ch),
652 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
653 } else {
654 cpc_writeb(falcbase + F_REG(IPC, ch),
655 cpc_readb(falcbase + F_REG(IPC, ch)) | IPC_SCI);
656 if (conf->fr_mode == PC300_FR_UNFRAMED) {
657 cpc_writeb(falcbase + F_REG(IMR2, ch),
658 cpc_readb(falcbase + F_REG(IMR2, ch)) & ~(IMR2_LOS));
659 } else {
660 cpc_writeb(falcbase + F_REG(IMR2, ch),
661 cpc_readb(falcbase + F_REG(IMR2, ch)) &
662 ~(IMR2_FAR | IMR2_LFA | IMR2_AIS | IMR2_LOS));
663 if (pfalc->multiframe_mode) {
664 cpc_writeb(falcbase + F_REG(IMR2, ch),
665 cpc_readb(falcbase + F_REG(IMR2, ch)) &
666 ~(IMR2_T400MS | IMR2_MFAR));
667 } else {
668 cpc_writeb(falcbase + F_REG(IMR2, ch),
669 cpc_readb(falcbase + F_REG(IMR2, ch)) |
670 IMR2_T400MS | IMR2_MFAR);
671 }
672 }
673 }
674}
675
7665a089 676static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
1da177e4
LT		 677{
678 void __iomem *falcbase = card->hw.falcbase;
679 ucchar tshf = card->chan[ch].falc.offset;
680
681 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
682 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
683 ~(0x80 >> ((timeslot - tshf) & 0x07)));
684 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
685 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) |
686 (0x80 >> (timeslot & 0x07)));
687 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
688 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) |
689 (0x80 >> (timeslot & 0x07)));
690}
691
7665a089 692static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
1da177e4
LT		 693{
694 void __iomem *falcbase = card->hw.falcbase;
695 ucchar tshf = card->chan[ch].falc.offset;
696
697 cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
698 cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
699 (0x80 >> ((timeslot - tshf) & 0x07)));
700 cpc_writeb(falcbase + F_REG((TTR1 + timeslot / 8), ch),
701 cpc_readb(falcbase + F_REG((TTR1 + timeslot / 8), ch)) &
702 ~(0x80 >> (timeslot & 0x07)));
703 cpc_writeb(falcbase + F_REG((RTR1 + timeslot / 8), ch),
704 cpc_readb(falcbase + F_REG((RTR1 + timeslot / 8), ch)) &
705 ~(0x80 >> (timeslot & 0x07)));
706}
707
7665a089 708static void falc_close_all_timeslots(pc300_t * card, int ch)
1da177e4
LT		 709{
710 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
711 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
712 void __iomem *falcbase = card->hw.falcbase;
713
714 cpc_writeb(falcbase + F_REG(ICB1, ch), 0xff);
715 cpc_writeb(falcbase + F_REG(TTR1, ch), 0);
716 cpc_writeb(falcbase + F_REG(RTR1, ch), 0);
717 cpc_writeb(falcbase + F_REG(ICB2, ch), 0xff);
718 cpc_writeb(falcbase + F_REG(TTR2, ch), 0);
719 cpc_writeb(falcbase + F_REG(RTR2, ch), 0);
720 cpc_writeb(falcbase + F_REG(ICB3, ch), 0xff);
721 cpc_writeb(falcbase + F_REG(TTR3, ch), 0);
722 cpc_writeb(falcbase + F_REG(RTR3, ch), 0);
723 if (conf->media == IF_IFACE_E1) {
724 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
725 cpc_writeb(falcbase + F_REG(TTR4, ch), 0);
726 cpc_writeb(falcbase + F_REG(RTR4, ch), 0);
727 }
728}
729
7665a089 730static void falc_open_all_timeslots(pc300_t * card, int ch)
1da177e4
LT		 731{
732 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
733 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
734 void __iomem *falcbase = card->hw.falcbase;
735
736 cpc_writeb(falcbase + F_REG(ICB1, ch), 0);
737 if (conf->fr_mode == PC300_FR_UNFRAMED) {
738 cpc_writeb(falcbase + F_REG(TTR1, ch), 0xff);
739 cpc_writeb(falcbase + F_REG(RTR1, ch), 0xff);
740 } else {
741 /* Timeslot 0 is never enabled */
742 cpc_writeb(falcbase + F_REG(TTR1, ch), 0x7f);
743 cpc_writeb(falcbase + F_REG(RTR1, ch), 0x7f);
744 }
745 cpc_writeb(falcbase + F_REG(ICB2, ch), 0);
746 cpc_writeb(falcbase + F_REG(TTR2, ch), 0xff);
747 cpc_writeb(falcbase + F_REG(RTR2, ch), 0xff);
748 cpc_writeb(falcbase + F_REG(ICB3, ch), 0);
749 cpc_writeb(falcbase + F_REG(TTR3, ch), 0xff);
750 cpc_writeb(falcbase + F_REG(RTR3, ch), 0xff);
751 if (conf->media == IF_IFACE_E1) {
752 cpc_writeb(falcbase + F_REG(ICB4, ch), 0);
753 cpc_writeb(falcbase + F_REG(TTR4, ch), 0xff);
754 cpc_writeb(falcbase + F_REG(RTR4, ch), 0xff);
755 } else {
756 cpc_writeb(falcbase + F_REG(ICB4, ch), 0xff);
757 cpc_writeb(falcbase + F_REG(TTR4, ch), 0x80);
758 cpc_writeb(falcbase + F_REG(RTR4, ch), 0x80);
759 }
760}
761
7665a089 762static void falc_init_timeslot(pc300_t * card, int ch)
1da177e4
LT		 763{
764 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
765 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
766 falc_t *pfalc = (falc_t *) & chan->falc;
767 int tslot;
768
769 for (tslot = 0; tslot < pfalc->num_channels; tslot++) {
770 if (conf->tslot_bitmap & (1 << tslot)) {
771 // Channel enabled
772 falc_open_timeslot(card, ch, tslot + 1);
773 } else {
774 // Channel disabled
775 falc_close_timeslot(card, ch, tslot + 1);
776 }
777 }
778}
779
7665a089 780static void falc_enable_comm(pc300_t * card, int ch)
1da177e4
LT		 781{
782 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
783 falc_t *pfalc = (falc_t *) & chan->falc;
784
785 if (pfalc->full_bandwidth) {
786 falc_open_all_timeslots(card, ch);
787 } else {
788 falc_init_timeslot(card, ch);
789 }
790 // CTS/DCD ON
791 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
792 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
793 ~((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
794}
795
7665a089 796static void falc_disable_comm(pc300_t * card, int ch)
1da177e4
LT		 797{
798 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
799 falc_t *pfalc = (falc_t *) & chan->falc;
800
801 if (pfalc->loop_active != 2) {
802 falc_close_all_timeslots(card, ch);
803 }
804 // CTS/DCD OFF
805 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
806 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
807 ((CPLD_REG1_FALC_DCD | CPLD_REG1_FALC_CTS) << (2 * ch)));
808}
809
7665a089 810static void falc_init_t1(pc300_t * card, int ch)
1da177e4
LT		 811{
812 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
813 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
814 falc_t *pfalc = (falc_t *) & chan->falc;
815 void __iomem *falcbase = card->hw.falcbase;
816 ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
817
818 /* Switch to T1 mode (PCM 24) */
819 cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
820
821 /* Wait 20 us for setup */
822 udelay(20);
823
824 /* Transmit Buffer Size (1 frame) */
825 cpc_writeb(falcbase + F_REG(SIC1, ch), SIC1_XBS0);
826
827 /* Clock mode */
828 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
829 cpc_writeb(falcbase + F_REG(LIM0, ch),
830 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
831 } else { /* Slave mode */
832 cpc_writeb(falcbase + F_REG(LIM0, ch),
833 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
834 cpc_writeb(falcbase + F_REG(LOOP, ch),
835 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_RTM);
836 }
837
838 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
839 cpc_writeb(falcbase + F_REG(FMR0, ch),
840 cpc_readb(falcbase + F_REG(FMR0, ch)) &
841 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
842
843 switch (conf->lcode) {
844 case PC300_LC_AMI:
845 cpc_writeb(falcbase + F_REG(FMR0, ch),
846 cpc_readb(falcbase + F_REG(FMR0, ch)) |
847 FMR0_XC1 | FMR0_RC1);
848 /* Clear Channel register to ON for all channels */
849 cpc_writeb(falcbase + F_REG(CCB1, ch), 0xff);
850 cpc_writeb(falcbase + F_REG(CCB2, ch), 0xff);
851 cpc_writeb(falcbase + F_REG(CCB3, ch), 0xff);
852 break;
853
854 case PC300_LC_B8ZS:
855 cpc_writeb(falcbase + F_REG(FMR0, ch),
856 cpc_readb(falcbase + F_REG(FMR0, ch)) |
857 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
858 break;
859
860 case PC300_LC_NRZ:
861 cpc_writeb(falcbase + F_REG(FMR0, ch),
862 cpc_readb(falcbase + F_REG(FMR0, ch)) | 0x00);
863 break;
864 }
865
866 cpc_writeb(falcbase + F_REG(LIM0, ch),
867 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_ELOS);
868 cpc_writeb(falcbase + F_REG(LIM0, ch),
869 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
870 /* Set interface mode to 2 MBPS */
871 cpc_writeb(falcbase + F_REG(FMR1, ch),
872 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
873
874 switch (conf->fr_mode) {
875 case PC300_FR_ESF:
876 pfalc->multiframe_mode = 0;
877 cpc_writeb(falcbase + F_REG(FMR4, ch),
878 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_FM1);
879 cpc_writeb(falcbase + F_REG(FMR1, ch),
880 cpc_readb(falcbase + F_REG(FMR1, ch)) |
881 FMR1_CRC | FMR1_EDL);
882 cpc_writeb(falcbase + F_REG(XDL1, ch), 0);
883 cpc_writeb(falcbase + F_REG(XDL2, ch), 0);
884 cpc_writeb(falcbase + F_REG(XDL3, ch), 0);
885 cpc_writeb(falcbase + F_REG(FMR0, ch),
886 cpc_readb(falcbase + F_REG(FMR0, ch)) & ~FMR0_SRAF);
887 cpc_writeb(falcbase + F_REG(FMR2, ch),
888 cpc_readb(falcbase + F_REG(FMR2,ch)) | FMR2_MCSP | FMR2_SSP);
889 break;
890
891 case PC300_FR_D4:
892 pfalc->multiframe_mode = 1;
893 cpc_writeb(falcbase + F_REG(FMR4, ch),
894 cpc_readb(falcbase + F_REG(FMR4, ch)) &
895 ~(FMR4_FM1 | FMR4_FM0));
896 cpc_writeb(falcbase + F_REG(FMR0, ch),
897 cpc_readb(falcbase + F_REG(FMR0, ch)) | FMR0_SRAF);
898 cpc_writeb(falcbase + F_REG(FMR2, ch),
899 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_SSP);
900 break;
901 }
902
903 /* Enable Automatic Resynchronization */
904 cpc_writeb(falcbase + F_REG(FMR4, ch),
905 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_AUTO);
906
907 /* Transmit Automatic Remote Alarm */
908 cpc_writeb(falcbase + F_REG(FMR2, ch),
909 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
910
911 /* Channel translation mode 1 : one to one */
912 cpc_writeb(falcbase + F_REG(FMR1, ch),
913 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_CTM);
914
915 /* No signaling */
916 cpc_writeb(falcbase + F_REG(FMR1, ch),
917 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_SIGM);
918 cpc_writeb(falcbase + F_REG(FMR5, ch),
919 cpc_readb(falcbase + F_REG(FMR5, ch)) &
920 ~(FMR5_EIBR | FMR5_SRS));
921 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
922
923 cpc_writeb(falcbase + F_REG(LIM1, ch),
924 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
925
926 switch (conf->lbo) {
927 /* Provides proper Line Build Out */
928 case PC300_LBO_0_DB:
929 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
930 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x5a);
931 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x8f);
932 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
933 break;
934 case PC300_LBO_7_5_DB:
935 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x40 | LIM2_LOS1 | dja));
936 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x11);
937 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x02);
938 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
939 break;
940 case PC300_LBO_15_DB:
941 cpc_writeb(falcbase + F_REG(LIM2, ch), (0x80 | LIM2_LOS1 | dja));
942 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x8e);
943 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
944 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
945 break;
946 case PC300_LBO_22_5_DB:
947 cpc_writeb(falcbase + F_REG(LIM2, ch), (0xc0 | LIM2_LOS1 | dja));
948 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x09);
949 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x01);
950 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x20);
951 break;
952 }
953
954 /* Transmit Clock-Slot Offset */
955 cpc_writeb(falcbase + F_REG(XC0, ch),
956 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
957 /* Transmit Time-slot Offset */
958 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
959 /* Receive Clock-Slot offset */
960 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
961 /* Receive Time-slot offset */
962 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
963
964 /* LOS Detection after 176 consecutive 0s */
965 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
966 /* LOS Recovery after 22 ones in the time window of PCD */
967 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
968
969 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
970
971 if (conf->fr_mode == PC300_FR_ESF_JAPAN) {
972 cpc_writeb(falcbase + F_REG(RC1, ch),
973 cpc_readb(falcbase + F_REG(RC1, ch)) | 0x80);
974 }
975
976 falc_close_all_timeslots(card, ch);
977}
978
7665a089 979static void falc_init_e1(pc300_t * card, int ch)
1da177e4
LT		 980{
981 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
982 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
983 falc_t *pfalc = (falc_t *) & chan->falc;
984 void __iomem *falcbase = card->hw.falcbase;
985 ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
986
987 /* Switch to E1 mode (PCM 30) */
988 cpc_writeb(falcbase + F_REG(FMR1, ch),
989 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_PMOD);
990
991 /* Clock mode */
992 if (conf->phys_settings.clock_type == CLOCK_INT) { /* Master mode */
993 cpc_writeb(falcbase + F_REG(LIM0, ch),
994 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_MAS);
995 } else { /* Slave mode */
996 cpc_writeb(falcbase + F_REG(LIM0, ch),
997 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_MAS);
998 }
999 cpc_writeb(falcbase + F_REG(LOOP, ch),
1000 cpc_readb(falcbase + F_REG(LOOP, ch)) & ~LOOP_SFM);
1001
1002 cpc_writeb(falcbase + F_REG(IPC, ch), IPC_SCI);
1003 cpc_writeb(falcbase + F_REG(FMR0, ch),
1004 cpc_readb(falcbase + F_REG(FMR0, ch)) &
1005 ~(FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1));
1006
1007 switch (conf->lcode) {
1008 case PC300_LC_AMI:
1009 cpc_writeb(falcbase + F_REG(FMR0, ch),
1010 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1011 FMR0_XC1 | FMR0_RC1);
1012 break;
1013
1014 case PC300_LC_HDB3:
1015 cpc_writeb(falcbase + F_REG(FMR0, ch),
1016 cpc_readb(falcbase + F_REG(FMR0, ch)) |
1017 FMR0_XC0 | FMR0_XC1 | FMR0_RC0 | FMR0_RC1);
1018 break;
1019
1020 case PC300_LC_NRZ:
1021 break;
1022 }
1023
1024 cpc_writeb(falcbase + F_REG(LIM0, ch),
1025 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~(LIM0_SCL1 | LIM0_SCL0));
1026 /* Set interface mode to 2 MBPS */
1027 cpc_writeb(falcbase + F_REG(FMR1, ch),
1028 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_IMOD);
1029
1030 cpc_writeb(falcbase + F_REG(XPM0, ch), 0x18);
1031 cpc_writeb(falcbase + F_REG(XPM1, ch), 0x03);
1032 cpc_writeb(falcbase + F_REG(XPM2, ch), 0x00);
1033
1034 switch (conf->fr_mode) {
1035 case PC300_FR_MF_CRC4:
1036 pfalc->multiframe_mode = 1;
1037 cpc_writeb(falcbase + F_REG(FMR1, ch),
1038 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_XFS);
1039 cpc_writeb(falcbase + F_REG(FMR2, ch),
1040 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_RFS1);
1041 cpc_writeb(falcbase + F_REG(FMR2, ch),
1042 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_RFS0);
1043 cpc_writeb(falcbase + F_REG(FMR3, ch),
1044 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_EXTIW);
1045
1046 /* MultiFrame Resynchronization */
1047 cpc_writeb(falcbase + F_REG(FMR1, ch),
1048 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_MFCS);
1049
1050 /* Automatic Loss of Multiframe > 914 CRC errors */
1051 cpc_writeb(falcbase + F_REG(FMR2, ch),
1052 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_ALMF);
1053
1054 /* S1 and SI1/SI2 spare Bits set to 1 */
1055 cpc_writeb(falcbase + F_REG(XSP, ch),
1056 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_AXS);
1057 cpc_writeb(falcbase + F_REG(XSP, ch),
1058 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_EBP);
1059 cpc_writeb(falcbase + F_REG(XSP, ch),
1060 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XS13 | XSP_XS15);
1061
1062 /* Automatic Force Resynchronization */
1063 cpc_writeb(falcbase + F_REG(FMR1, ch),
1064 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1065
1066 /* Transmit Automatic Remote Alarm */
1067 cpc_writeb(falcbase + F_REG(FMR2, ch),
1068 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1069
1070 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1071 cpc_writeb(falcbase + F_REG(XSW, ch),
1072 cpc_readb(falcbase + F_REG(XSW, ch)) |
1073 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1074 break;
1075
1076 case PC300_FR_MF_NON_CRC4:
1077 case PC300_FR_D4:
1078 pfalc->multiframe_mode = 0;
1079 cpc_writeb(falcbase + F_REG(FMR1, ch),
1080 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1081 cpc_writeb(falcbase + F_REG(FMR2, ch),
1082 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1083 ~(FMR2_RFS1 | FMR2_RFS0));
1084 cpc_writeb(falcbase + F_REG(XSW, ch),
1085 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XSIS);
1086 cpc_writeb(falcbase + F_REG(XSP, ch),
1087 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_XSIF);
1088
1089 /* Automatic Force Resynchronization */
1090 cpc_writeb(falcbase + F_REG(FMR1, ch),
1091 cpc_readb(falcbase + F_REG(FMR1, ch)) | FMR1_AFR);
1092
1093 /* Transmit Automatic Remote Alarm */
1094 cpc_writeb(falcbase + F_REG(FMR2, ch),
1095 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_AXRA);
1096
1097 /* Transmit Spare Bits for National Use (Y, Sn, Sa) */
1098 cpc_writeb(falcbase + F_REG(XSW, ch),
1099 cpc_readb(falcbase + F_REG(XSW, ch)) |
1100 XSW_XY0 | XSW_XY1 | XSW_XY2 | XSW_XY3 | XSW_XY4);
1101 break;
1102
1103 case PC300_FR_UNFRAMED:
1104 pfalc->multiframe_mode = 0;
1105 cpc_writeb(falcbase + F_REG(FMR1, ch),
1106 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_XFS);
1107 cpc_writeb(falcbase + F_REG(FMR2, ch),
1108 cpc_readb(falcbase + F_REG(FMR2, ch)) &
1109 ~(FMR2_RFS1 | FMR2_RFS0));
1110 cpc_writeb(falcbase + F_REG(XSP, ch),
1111 cpc_readb(falcbase + F_REG(XSP, ch)) | XSP_TT0);
1112 cpc_writeb(falcbase + F_REG(XSW, ch),
1113 cpc_readb(falcbase + F_REG(XSW, ch)) &
1114 ~(XSW_XTM|XSW_XY0|XSW_XY1|XSW_XY2|XSW_XY3|XSW_XY4));
1115 cpc_writeb(falcbase + F_REG(TSWM, ch), 0xff);
1116 cpc_writeb(falcbase + F_REG(FMR2, ch),
1117 cpc_readb(falcbase + F_REG(FMR2, ch)) |
1118 (FMR2_RTM | FMR2_DAIS));
1119 cpc_writeb(falcbase + F_REG(FMR2, ch),
1120 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_AXRA);
1121 cpc_writeb(falcbase + F_REG(FMR1, ch),
1122 cpc_readb(falcbase + F_REG(FMR1, ch)) & ~FMR1_AFR);
1123 pfalc->sync = 1;
1124 cpc_writeb(falcbase + card->hw.cpld_reg2,
1125 cpc_readb(falcbase + card->hw.cpld_reg2) |
1126 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1127 break;
1128 }
1129
1130 /* No signaling */
1131 cpc_writeb(falcbase + F_REG(XSP, ch),
1132 cpc_readb(falcbase + F_REG(XSP, ch)) & ~XSP_CASEN);
1133 cpc_writeb(falcbase + F_REG(CCR1, ch), 0);
1134
1135 cpc_writeb(falcbase + F_REG(LIM1, ch),
1136 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RIL0 | LIM1_RIL1);
1137 cpc_writeb(falcbase + F_REG(LIM2, ch), (LIM2_LOS1 | dja));
1138
1139 /* Transmit Clock-Slot Offset */
1140 cpc_writeb(falcbase + F_REG(XC0, ch),
1141 cpc_readb(falcbase + F_REG(XC0, ch)) | 0x01);
1142 /* Transmit Time-slot Offset */
1143 cpc_writeb(falcbase + F_REG(XC1, ch), 0x3e);
1144 /* Receive Clock-Slot offset */
1145 cpc_writeb(falcbase + F_REG(RC0, ch), 0x05);
1146 /* Receive Time-slot offset */
1147 cpc_writeb(falcbase + F_REG(RC1, ch), 0x00);
1148
1149 /* LOS Detection after 176 consecutive 0s */
1150 cpc_writeb(falcbase + F_REG(PCDR, ch), 0x0a);
1151 /* LOS Recovery after 22 ones in the time window of PCD */
1152 cpc_writeb(falcbase + F_REG(PCRR, ch), 0x15);
1153
1154 cpc_writeb(falcbase + F_REG(IDLE, ch), 0x7f);
1155
1156 falc_close_all_timeslots(card, ch);
1157}
1158
7665a089 1159static void falc_init_hdlc(pc300_t * card, int ch)
1da177e4
LT		 1160{
1161 void __iomem *falcbase = card->hw.falcbase;
1162 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1163 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1164
1165 /* Enable transparent data transfer */
1166 if (conf->fr_mode == PC300_FR_UNFRAMED) {
1167 cpc_writeb(falcbase + F_REG(MODE, ch), 0);
1168 } else {
1169 cpc_writeb(falcbase + F_REG(MODE, ch),
1170 cpc_readb(falcbase + F_REG(MODE, ch)) |
1171 (MODE_HRAC | MODE_MDS2));
1172 cpc_writeb(falcbase + F_REG(RAH2, ch), 0xff);
1173 cpc_writeb(falcbase + F_REG(RAH1, ch), 0xff);
1174 cpc_writeb(falcbase + F_REG(RAL2, ch), 0xff);
1175 cpc_writeb(falcbase + F_REG(RAL1, ch), 0xff);
1176 }
1177
1178 /* Tx/Rx reset */
1179 falc_issue_cmd(card, ch, CMDR_RRES | CMDR_XRES | CMDR_SRES);
1180
1181 /* Enable interrupt sources */
1182 falc_intr_enable(card, ch);
1183}
1184
7665a089 1185static void te_config(pc300_t * card, int ch)
1da177e4
LT		 1186{
1187 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1188 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1189 falc_t *pfalc = (falc_t *) & chan->falc;
1190 void __iomem *falcbase = card->hw.falcbase;
1191 ucchar dummy;
1192 unsigned long flags;
1193
1194 memset(pfalc, 0, sizeof(falc_t));
1195 switch (conf->media) {
1196 case IF_IFACE_T1:
1197 pfalc->num_channels = NUM_OF_T1_CHANNELS;
1198 pfalc->offset = 1;
1199 break;
1200 case IF_IFACE_E1:
1201 pfalc->num_channels = NUM_OF_E1_CHANNELS;
1202 pfalc->offset = 0;
1203 break;
1204 }
1205 if (conf->tslot_bitmap == 0xffffffffUL)
1206 pfalc->full_bandwidth = 1;
1207 else
1208 pfalc->full_bandwidth = 0;
1209
1210 CPC_LOCK(card, flags);
1211 /* Reset the FALC chip */
1212 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1213 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
1214 (CPLD_REG1_FALC_RESET << (2 * ch)));
1215 udelay(10000);
1216 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
1217 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
1218 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
1219
1220 if (conf->media == IF_IFACE_T1) {
1221 falc_init_t1(card, ch);
1222 } else {
1223 falc_init_e1(card, ch);
1224 }
1225 falc_init_hdlc(card, ch);
1226 if (conf->rx_sens == PC300_RX_SENS_SH) {
1227 cpc_writeb(falcbase + F_REG(LIM0, ch),
1228 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_EQON);
1229 } else {
1230 cpc_writeb(falcbase + F_REG(LIM0, ch),
1231 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_EQON);
1232 }
1233 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1234 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1235 ((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK) << (2 * ch)));
1236
1237 /* Clear all interrupt registers */
1238 dummy = cpc_readb(falcbase + F_REG(FISR0, ch)) +
1239 cpc_readb(falcbase + F_REG(FISR1, ch)) +
1240 cpc_readb(falcbase + F_REG(FISR2, ch)) +
1241 cpc_readb(falcbase + F_REG(FISR3, ch));
1242 CPC_UNLOCK(card, flags);
1243}
1244
7665a089 1245static void falc_check_status(pc300_t * card, int ch, unsigned char frs0)
1da177e4
LT		 1246{
1247 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1248 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1249 falc_t *pfalc = (falc_t *) & chan->falc;
1250 void __iomem *falcbase = card->hw.falcbase;
1251
1252 /* Verify LOS */
1253 if (frs0 & FRS0_LOS) {
1254 if (!pfalc->red_alarm) {
1255 pfalc->red_alarm = 1;
1256 pfalc->los++;
1257 if (!pfalc->blue_alarm) {
1258 // EVENT_FALC_ABNORMAL
1259 if (conf->media == IF_IFACE_T1) {
1260 /* Disable this interrupt as it may otherwise interfere
1261 * with other working boards. */
1262 cpc_writeb(falcbase + F_REG(IMR0, ch),
1263 cpc_readb(falcbase + F_REG(IMR0, ch))
1264 | IMR0_PDEN);
1265 }
1266 falc_disable_comm(card, ch);
1267 // EVENT_FALC_ABNORMAL
1268 }
1269 }
1270 } else {
1271 if (pfalc->red_alarm) {
1272 pfalc->red_alarm = 0;
1273 pfalc->losr++;
1274 }
1275 }
1276
1277 if (conf->fr_mode != PC300_FR_UNFRAMED) {
1278 /* Verify AIS alarm */
1279 if (frs0 & FRS0_AIS) {
1280 if (!pfalc->blue_alarm) {
1281 pfalc->blue_alarm = 1;
1282 pfalc->ais++;
1283 // EVENT_AIS
1284 if (conf->media == IF_IFACE_T1) {
1285 /* Disable this interrupt as it may otherwise interfere with other working boards. */
1286 cpc_writeb(falcbase + F_REG(IMR0, ch),
1287 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1288 }
1289 falc_disable_comm(card, ch);
1290 // EVENT_AIS
1291 }
1292 } else {
1293 pfalc->blue_alarm = 0;
1294 }
1295
1296 /* Verify LFA */
1297 if (frs0 & FRS0_LFA) {
1298 if (!pfalc->loss_fa) {
1299 pfalc->loss_fa = 1;
1300 pfalc->lfa++;
1301 if (!pfalc->blue_alarm && !pfalc->red_alarm) {
1302 // EVENT_FALC_ABNORMAL
1303 if (conf->media == IF_IFACE_T1) {
1304 /* Disable this interrupt as it may otherwise
1305 * interfere with other working boards. */
1306 cpc_writeb(falcbase + F_REG(IMR0, ch),
1307 cpc_readb(falcbase + F_REG(IMR0, ch))
1308 | IMR0_PDEN);
1309 }
1310 falc_disable_comm(card, ch);
1311 // EVENT_FALC_ABNORMAL
1312 }
1313 }
1314 } else {
1315 if (pfalc->loss_fa) {
1316 pfalc->loss_fa = 0;
1317 pfalc->farec++;
1318 }
1319 }
1320
1321 /* Verify LMFA */
1322 if (pfalc->multiframe_mode && (frs0 & FRS0_LMFA)) {
1323 /* D4 or CRC4 frame mode */
1324 if (!pfalc->loss_mfa) {
1325 pfalc->loss_mfa = 1;
1326 pfalc->lmfa++;
1327 if (!pfalc->blue_alarm && !pfalc->red_alarm &&
1328 !pfalc->loss_fa) {
1329 // EVENT_FALC_ABNORMAL
1330 if (conf->media == IF_IFACE_T1) {
1331 /* Disable this interrupt as it may otherwise
1332 * interfere with other working boards. */
1333 cpc_writeb(falcbase + F_REG(IMR0, ch),
1334 cpc_readb(falcbase + F_REG(IMR0, ch))
1335 | IMR0_PDEN);
1336 }
1337 falc_disable_comm(card, ch);
1338 // EVENT_FALC_ABNORMAL
1339 }
1340 }
1341 } else {
1342 pfalc->loss_mfa = 0;
1343 }
1344
1345 /* Verify Remote Alarm */
1346 if (frs0 & FRS0_RRA) {
1347 if (!pfalc->yellow_alarm) {
1348 pfalc->yellow_alarm = 1;
1349 pfalc->rai++;
1350 if (pfalc->sync) {
1351 // EVENT_RAI
1352 falc_disable_comm(card, ch);
1353 // EVENT_RAI
1354 }
1355 }
1356 } else {
1357 pfalc->yellow_alarm = 0;
1358 }
1359 } /* if !PC300_UNFRAMED */
1360
1361 if (pfalc->red_alarm || pfalc->loss_fa ||
1362 pfalc->loss_mfa || pfalc->blue_alarm) {
1363 if (pfalc->sync) {
1364 pfalc->sync = 0;
1365 chan->d.line_off++;
1366 cpc_writeb(falcbase + card->hw.cpld_reg2,
1367 cpc_readb(falcbase + card->hw.cpld_reg2) &
1368 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1369 }
1370 } else {
1371 if (!pfalc->sync) {
1372 pfalc->sync = 1;
1373 chan->d.line_on++;
1374 cpc_writeb(falcbase + card->hw.cpld_reg2,
1375 cpc_readb(falcbase + card->hw.cpld_reg2) |
1376 (CPLD_REG2_FALC_LED2 << (2 * ch)));
1377 }
1378 }
1379
1380 if (pfalc->sync && !pfalc->yellow_alarm) {
1381 if (!pfalc->active) {
1382 // EVENT_FALC_NORMAL
1383 if (pfalc->loop_active) {
1384 return;
1385 }
1386 if (conf->media == IF_IFACE_T1) {
1387 cpc_writeb(falcbase + F_REG(IMR0, ch),
1388 cpc_readb(falcbase + F_REG(IMR0, ch)) & ~IMR0_PDEN);
1389 }
1390 falc_enable_comm(card, ch);
1391 // EVENT_FALC_NORMAL
1392 pfalc->active = 1;
1393 }
1394 } else {
1395 if (pfalc->active) {
1396 pfalc->active = 0;
1397 }
1398 }
1399}
1400
7665a089 1401static void falc_update_stats(pc300_t * card, int ch)
1da177e4
LT		 1402{
1403 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1404 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1405 falc_t *pfalc = (falc_t *) & chan->falc;
1406 void __iomem *falcbase = card->hw.falcbase;
1407 ucshort counter;
1408
1409 counter = cpc_readb(falcbase + F_REG(FECL, ch));
1410 counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
1411 pfalc->fec += counter;
1412
1413 counter = cpc_readb(falcbase + F_REG(CVCL, ch));
1414 counter |= cpc_readb(falcbase + F_REG(CVCH, ch)) << 8;
1415 pfalc->cvc += counter;
1416
1417 counter = cpc_readb(falcbase + F_REG(CECL, ch));
1418 counter |= cpc_readb(falcbase + F_REG(CECH, ch)) << 8;
1419 pfalc->cec += counter;
1420
1421 counter = cpc_readb(falcbase + F_REG(EBCL, ch));
1422 counter |= cpc_readb(falcbase + F_REG(EBCH, ch)) << 8;
1423 pfalc->ebc += counter;
1424
1425 if (cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) {
1426 mdelay(10);
1427 counter = cpc_readb(falcbase + F_REG(BECL, ch));
1428 counter |= cpc_readb(falcbase + F_REG(BECH, ch)) << 8;
1429 pfalc->bec += counter;
1430
1431 if (((conf->media == IF_IFACE_T1) &&
1432 (cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_LLBAD) &&
1433 (!(cpc_readb(falcbase + F_REG(FRS1, ch)) & FRS1_PDEN)))
1434 ||
1435 ((conf->media == IF_IFACE_E1) &&
1436 (cpc_readb(falcbase + F_REG(RSP, ch)) & RSP_LLBAD))) {
1437 pfalc->prbs = 2;
1438 } else {
1439 pfalc->prbs = 1;
1440 }
1441 }
1442}
1443
1444/*----------------------------------------------------------------------------
1445 * falc_remote_loop
1446 *----------------------------------------------------------------------------
1447 * Description: In the remote loopback mode the clock and data recovered
1448 * from the line inputs RL1/2 or RDIP/RDIN are routed back
1449 * to the line outputs XL1/2 or XDOP/XDON via the analog
1450 * transmitter. As in normal mode they are processsed by
1451 * the synchronizer and then sent to the system interface.
1452 *----------------------------------------------------------------------------
1453 */
7665a089 1454static void falc_remote_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1455{
1456 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1457 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1458 falc_t *pfalc = (falc_t *) & chan->falc;
1459 void __iomem *falcbase = card->hw.falcbase;
1460
1461 if (loop_on) {
1462 // EVENT_FALC_ABNORMAL
1463 if (conf->media == IF_IFACE_T1) {
1464 /* Disable this interrupt as it may otherwise interfere with
1465 * other working boards. */
1466 cpc_writeb(falcbase + F_REG(IMR0, ch),
1467 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1468 }
1469 falc_disable_comm(card, ch);
1470 // EVENT_FALC_ABNORMAL
1471 cpc_writeb(falcbase + F_REG(LIM1, ch),
1472 cpc_readb(falcbase + F_REG(LIM1, ch)) | LIM1_RL);
1473 pfalc->loop_active = 1;
1474 } else {
1475 cpc_writeb(falcbase + F_REG(LIM1, ch),
1476 cpc_readb(falcbase + F_REG(LIM1, ch)) & ~LIM1_RL);
1477 pfalc->sync = 0;
1478 cpc_writeb(falcbase + card->hw.cpld_reg2,
1479 cpc_readb(falcbase + card->hw.cpld_reg2) &
1480 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1481 pfalc->active = 0;
1482 falc_issue_cmd(card, ch, CMDR_XRES);
1483 pfalc->loop_active = 0;
1484 }
1485}
1486
1487/*----------------------------------------------------------------------------
1488 * falc_local_loop
1489 *----------------------------------------------------------------------------
1490 * Description: The local loopback mode disconnects the receive lines
1491 * RL1/RL2 resp. RDIP/RDIN from the receiver. Instead of the
1492 * signals coming from the line the data provided by system
1493 * interface are routed through the analog receiver back to
1494 * the system interface. The unipolar bit stream will be
1495 * undisturbed transmitted on the line. Receiver and transmitter
1496 * coding must be identical.
1497 *----------------------------------------------------------------------------
1498 */
7665a089 1499static void falc_local_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1500{
1501 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1502 falc_t *pfalc = (falc_t *) & chan->falc;
1503 void __iomem *falcbase = card->hw.falcbase;
1504
1505 if (loop_on) {
1506 cpc_writeb(falcbase + F_REG(LIM0, ch),
1507 cpc_readb(falcbase + F_REG(LIM0, ch)) | LIM0_LL);
1508 pfalc->loop_active = 1;
1509 } else {
1510 cpc_writeb(falcbase + F_REG(LIM0, ch),
1511 cpc_readb(falcbase + F_REG(LIM0, ch)) & ~LIM0_LL);
1512 pfalc->loop_active = 0;
1513 }
1514}
1515
1516/*----------------------------------------------------------------------------
1517 * falc_payload_loop
1518 *----------------------------------------------------------------------------
1519 * Description: This routine allows to enable/disable payload loopback.
1520 * When the payload loop is activated, the received 192 bits
1521 * of payload data will be looped back to the transmit
1522 * direction. The framing bits, CRC6 and DL bits are not
1523 * looped. They are originated by the FALC-LH transmitter.
1524 *----------------------------------------------------------------------------
1525 */
7665a089 1526static void falc_payload_loop(pc300_t * card, int ch, int loop_on)
1da177e4
LT		 1527{
1528 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1529 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1530 falc_t *pfalc = (falc_t *) & chan->falc;
1531 void __iomem *falcbase = card->hw.falcbase;
1532
1533 if (loop_on) {
1534 // EVENT_FALC_ABNORMAL
1535 if (conf->media == IF_IFACE_T1) {
1536 /* Disable this interrupt as it may otherwise interfere with
1537 * other working boards. */
1538 cpc_writeb(falcbase + F_REG(IMR0, ch),
1539 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1540 }
1541 falc_disable_comm(card, ch);
1542 // EVENT_FALC_ABNORMAL
1543 cpc_writeb(falcbase + F_REG(FMR2, ch),
1544 cpc_readb(falcbase + F_REG(FMR2, ch)) | FMR2_PLB);
1545 if (conf->media == IF_IFACE_T1) {
1546 cpc_writeb(falcbase + F_REG(FMR4, ch),
1547 cpc_readb(falcbase + F_REG(FMR4, ch)) | FMR4_TM);
1548 } else {
1549 cpc_writeb(falcbase + F_REG(FMR5, ch),
1550 cpc_readb(falcbase + F_REG(FMR5, ch)) | XSP_TT0);
1551 }
1552 falc_open_all_timeslots(card, ch);
1553 pfalc->loop_active = 2;
1554 } else {
1555 cpc_writeb(falcbase + F_REG(FMR2, ch),
1556 cpc_readb(falcbase + F_REG(FMR2, ch)) & ~FMR2_PLB);
1557 if (conf->media == IF_IFACE_T1) {
1558 cpc_writeb(falcbase + F_REG(FMR4, ch),
1559 cpc_readb(falcbase + F_REG(FMR4, ch)) & ~FMR4_TM);
1560 } else {
1561 cpc_writeb(falcbase + F_REG(FMR5, ch),
1562 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~XSP_TT0);
1563 }
1564 pfalc->sync = 0;
1565 cpc_writeb(falcbase + card->hw.cpld_reg2,
1566 cpc_readb(falcbase + card->hw.cpld_reg2) &
1567 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1568 pfalc->active = 0;
1569 falc_issue_cmd(card, ch, CMDR_XRES);
1570 pfalc->loop_active = 0;
1571 }
1572}
1573
1574/*----------------------------------------------------------------------------
1575 * turn_off_xlu
1576 *----------------------------------------------------------------------------
1577 * Description: Turns XLU bit off in the proper register
1578 *----------------------------------------------------------------------------
1579 */
7665a089 1580static void turn_off_xlu(pc300_t * card, int ch)
1da177e4
LT		 1581{
1582 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1583 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1584 void __iomem *falcbase = card->hw.falcbase;
1585
1586 if (conf->media == IF_IFACE_T1) {
1587 cpc_writeb(falcbase + F_REG(FMR5, ch),
1588 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLU);
1589 } else {
1590 cpc_writeb(falcbase + F_REG(FMR3, ch),
1591 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLU);
1592 }
1593}
1594
1595/*----------------------------------------------------------------------------
1596 * turn_off_xld
1597 *----------------------------------------------------------------------------
1598 * Description: Turns XLD bit off in the proper register
1599 *----------------------------------------------------------------------------
1600 */
7665a089 1601static void turn_off_xld(pc300_t * card, int ch)
1da177e4
LT		 1602{
1603 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1604 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1605 void __iomem *falcbase = card->hw.falcbase;
1606
1607 if (conf->media == IF_IFACE_T1) {
1608 cpc_writeb(falcbase + F_REG(FMR5, ch),
1609 cpc_readb(falcbase + F_REG(FMR5, ch)) & ~FMR5_XLD);
1610 } else {
1611 cpc_writeb(falcbase + F_REG(FMR3, ch),
1612 cpc_readb(falcbase + F_REG(FMR3, ch)) & ~FMR3_XLD);
1613 }
1614}
1615
1616/*----------------------------------------------------------------------------
1617 * falc_generate_loop_up_code
1618 *----------------------------------------------------------------------------
1619 * Description: This routine writes the proper FALC chip register in order
1620 * to generate a LOOP activation code over a T1/E1 line.
1621 *----------------------------------------------------------------------------
1622 */
7665a089 1623static void falc_generate_loop_up_code(pc300_t * card, int ch)
1da177e4
LT		 1624{
1625 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1626 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1627 falc_t *pfalc = (falc_t *) & chan->falc;
1628 void __iomem *falcbase = card->hw.falcbase;
1629
1630 if (conf->media == IF_IFACE_T1) {
1631 cpc_writeb(falcbase + F_REG(FMR5, ch),
1632 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLU);
1633 } else {
1634 cpc_writeb(falcbase + F_REG(FMR3, ch),
1635 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLU);
1636 }
1637 // EVENT_FALC_ABNORMAL
1638 if (conf->media == IF_IFACE_T1) {
1639 /* Disable this interrupt as it may otherwise interfere with
1640 * other working boards. */
1641 cpc_writeb(falcbase + F_REG(IMR0, ch),
1642 cpc_readb(falcbase + F_REG(IMR0, ch)) | IMR0_PDEN);
1643 }
1644 falc_disable_comm(card, ch);
1645 // EVENT_FALC_ABNORMAL
1646 pfalc->loop_gen = 1;
1647}
1648
1649/*----------------------------------------------------------------------------
1650 * falc_generate_loop_down_code
1651 *----------------------------------------------------------------------------
1652 * Description: This routine writes the proper FALC chip register in order
1653 * to generate a LOOP deactivation code over a T1/E1 line.
1654 *----------------------------------------------------------------------------
1655 */
7665a089 1656static void falc_generate_loop_down_code(pc300_t * card, int ch)
1da177e4
LT		 1657{
1658 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1659 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1660 falc_t *pfalc = (falc_t *) & chan->falc;
1661 void __iomem *falcbase = card->hw.falcbase;
1662
1663 if (conf->media == IF_IFACE_T1) {
1664 cpc_writeb(falcbase + F_REG(FMR5, ch),
1665 cpc_readb(falcbase + F_REG(FMR5, ch)) | FMR5_XLD);
1666 } else {
1667 cpc_writeb(falcbase + F_REG(FMR3, ch),
1668 cpc_readb(falcbase + F_REG(FMR3, ch)) | FMR3_XLD);
1669 }
1670 pfalc->sync = 0;
1671 cpc_writeb(falcbase + card->hw.cpld_reg2,
1672 cpc_readb(falcbase + card->hw.cpld_reg2) &
1673 ~(CPLD_REG2_FALC_LED2 << (2 * ch)));
1674 pfalc->active = 0;
1675//? falc_issue_cmd(card, ch, CMDR_XRES);
1676 pfalc->loop_gen = 0;
1677}
1678
1679/*----------------------------------------------------------------------------
1680 * falc_pattern_test
1681 *----------------------------------------------------------------------------
1682 * Description: This routine generates a pattern code and checks
1683 * it on the reception side.
1684 *----------------------------------------------------------------------------
1685 */
7665a089 1686static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
1da177e4
LT		 1687{
1688 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1689 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
1690 falc_t *pfalc = (falc_t *) & chan->falc;
1691 void __iomem *falcbase = card->hw.falcbase;
1692
1693 if (activate) {
1694 pfalc->prbs = 1;
1695 pfalc->bec = 0;
1696 if (conf->media == IF_IFACE_T1) {
1697 /* Disable local loop activation/deactivation detect */
1698 cpc_writeb(falcbase + F_REG(IMR3, ch),
1699 cpc_readb(falcbase + F_REG(IMR3, ch)) | IMR3_LLBSC);
1700 } else {
1701 /* Disable local loop activation/deactivation detect */
1702 cpc_writeb(falcbase + F_REG(IMR1, ch),
1703 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_LLBSC);
1704 }
1705 /* Activates generation and monitoring of PRBS
1706 * (Pseudo Random Bit Sequence) */
1707 cpc_writeb(falcbase + F_REG(LCR1, ch),
1708 cpc_readb(falcbase + F_REG(LCR1, ch)) | LCR1_EPRM | LCR1_XPRBS);
1709 } else {
1710 pfalc->prbs = 0;
1711 /* Deactivates generation and monitoring of PRBS
1712 * (Pseudo Random Bit Sequence) */
1713 cpc_writeb(falcbase + F_REG(LCR1, ch),
1714 cpc_readb(falcbase+F_REG(LCR1,ch)) & ~(LCR1_EPRM | LCR1_XPRBS));
1715 if (conf->media == IF_IFACE_T1) {
1716 /* Enable local loop activation/deactivation detect */
1717 cpc_writeb(falcbase + F_REG(IMR3, ch),
1718 cpc_readb(falcbase + F_REG(IMR3, ch)) & ~IMR3_LLBSC);
1719 } else {
1720 /* Enable local loop activation/deactivation detect */
1721 cpc_writeb(falcbase + F_REG(IMR1, ch),
1722 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_LLBSC);
1723 }
1724 }
1725}
1726
1727/*----------------------------------------------------------------------------
1728 * falc_pattern_test_error
1729 *----------------------------------------------------------------------------
1730 * Description: This routine returns the bit error counter value
1731 *----------------------------------------------------------------------------
1732 */
7665a089 1733static ucshort falc_pattern_test_error(pc300_t * card, int ch)
1da177e4
LT		 1734{
1735 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
1736 falc_t *pfalc = (falc_t *) & chan->falc;
1737
1738 return (pfalc->bec);
1739}
1740
1741/**********************************/
1742/*** Net Interface Routines ***/
1743/**********************************/
1744
1745static void
1746cpc_trace(struct net_device *dev, struct sk_buff *skb_main, char rx_tx)
1747{
1748 struct sk_buff *skb;
1749
1750 if ((skb = dev_alloc_skb(10 + skb_main->len)) == NULL) {
1751 printk("%s: out of memory\n", dev->name);
1752 return;
1753 }
1754 skb_put(skb, 10 + skb_main->len);
1755
1756 skb->dev = dev;
1757 skb->protocol = htons(ETH_P_CUST);
1758 skb->mac.raw = skb->data;
1759 skb->pkt_type = PACKET_HOST;
1760 skb->len = 10 + skb_main->len;
1761
1762 memcpy(skb->data, dev->name, 5);
1763 skb->data[5] = '[';
1764 skb->data[6] = rx_tx;
1765 skb->data[7] = ']';
1766 skb->data[8] = ':';
1767 skb->data[9] = ' ';
1768 memcpy(&skb->data[10], skb_main->data, skb_main->len);
1769
1770 netif_rx(skb);
1771}
1772
7665a089 1773static void cpc_tx_timeout(struct net_device *dev)
1da177e4
LT		 1774{
1775 pc300dev_t *d = (pc300dev_t *) dev->priv;
1776 pc300ch_t *chan = (pc300ch_t *) d->chan;
1777 pc300_t *card = (pc300_t *) chan->card;
1778 struct net_device_stats *stats = hdlc_stats(dev);
1779 int ch = chan->channel;
1780 unsigned long flags;
1781 ucchar ilar;
1782
1783 stats->tx_errors++;
1784 stats->tx_aborted_errors++;
1785 CPC_LOCK(card, flags);
1786 if ((ilar = cpc_readb(card->hw.scabase + ILAR)) != 0) {
1787 printk("%s: ILAR=0x%x\n", dev->name, ilar);
1788 cpc_writeb(card->hw.scabase + ILAR, ilar);
1789 cpc_writeb(card->hw.scabase + DMER, 0x80);
1790 }
1791 if (card->hw.type == PC300_TE) {
1792 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1793 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1794 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1795 }
1796 dev->trans_start = jiffies;
1797 CPC_UNLOCK(card, flags);
1798 netif_wake_queue(dev);
1799}
1800
7665a089 1801static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 1802{
1803 pc300dev_t *d = (pc300dev_t *) dev->priv;
1804 pc300ch_t *chan = (pc300ch_t *) d->chan;
1805 pc300_t *card = (pc300_t *) chan->card;
1806 struct net_device_stats *stats = hdlc_stats(dev);
1807 int ch = chan->channel;
1808 unsigned long flags;
1809#ifdef PC300_DEBUG_TX
1810 int i;
1811#endif
1812
1813 if (chan->conf.monitor) {
1814 /* In monitor mode no Tx is done: ignore packet */
1815 dev_kfree_skb(skb);
1816 return 0;
1817 } else if (!netif_carrier_ok(dev)) {
1818 /* DCD must be OFF: drop packet */
1819 dev_kfree_skb(skb);
1820 stats->tx_errors++;
1821 stats->tx_carrier_errors++;
1822 return 0;
1823 } else if (cpc_readb(card->hw.scabase + M_REG(ST3, ch)) & ST3_DCD) {
1824 printk("%s: DCD is OFF. Going administrative down.\n", dev->name);
1825 stats->tx_errors++;
1826 stats->tx_carrier_errors++;
1827 dev_kfree_skb(skb);
1828 netif_carrier_off(dev);
1829 CPC_LOCK(card, flags);
1830 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_BUF_CLR);
1831 if (card->hw.type == PC300_TE) {
1832 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1833 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
1834 ~(CPLD_REG2_FALC_LED1 << (2 * ch)));
1835 }
1836 CPC_UNLOCK(card, flags);
1837 netif_wake_queue(dev);
1838 return 0;
1839 }
1840
1841 /* Write buffer to DMA buffers */
1842 if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
1843// printk("%s: write error. Dropping TX packet.\n", dev->name);
1844 netif_stop_queue(dev);
1845 dev_kfree_skb(skb);
1846 stats->tx_errors++;
1847 stats->tx_dropped++;
1848 return 0;
1849 }
1850#ifdef PC300_DEBUG_TX
1851 printk("%s T:", dev->name);
1852 for (i = 0; i < skb->len; i++)
1853 printk(" %02x", *(skb->data + i));
1854 printk("\n");
1855#endif
1856
1857 if (d->trace_on) {
1858 cpc_trace(dev, skb, 'T');
1859 }
1860 dev->trans_start = jiffies;
1861
1862 /* Start transmission */
1863 CPC_LOCK(card, flags);
1864 /* verify if it has more than one free descriptor */
1865 if (card->chan[ch].nfree_tx_bd <= 1) {
1866 /* don't have so stop the queue */
1867 netif_stop_queue(dev);
1868 }
1869 cpc_writel(card->hw.scabase + DTX_REG(EDAL, ch),
1870 TX_BD_ADDR(ch, chan->tx_next_bd));
1871 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_TX_ENA);
1872 cpc_writeb(card->hw.scabase + DSR_TX(ch), DSR_DE);
1873 if (card->hw.type == PC300_TE) {
1874 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
1875 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) |
1876 (CPLD_REG2_FALC_LED1 << (2 * ch)));
1877 }
1878 CPC_UNLOCK(card, flags);
1879 dev_kfree_skb(skb);
1880
1881 return 0;
1882}
1883
7665a089 1884static void cpc_net_rx(struct net_device *dev)
1da177e4
LT		 1885{
1886 pc300dev_t *d = (pc300dev_t *) dev->priv;
1887 pc300ch_t *chan = (pc300ch_t *) d->chan;
1888 pc300_t *card = (pc300_t *) chan->card;
1889 struct net_device_stats *stats = hdlc_stats(dev);
1890 int ch = chan->channel;
1891#ifdef PC300_DEBUG_RX
1892 int i;
1893#endif
1894 int rxb;
1895 struct sk_buff *skb;
1896
1897 while (1) {
1898 if ((rxb = dma_get_rx_frame_size(card, ch)) == -1)
1899 return;
1900
1901 if (!netif_carrier_ok(dev)) {
1902 /* DCD must be OFF: drop packet */
1903 printk("%s : DCD is OFF - drop %d rx bytes\n", dev->name, rxb);
1904 skb = NULL;
1905 } else {
1906 if (rxb > (dev->mtu + 40)) { /* add headers */
1907 printk("%s : MTU exceeded %d\n", dev->name, rxb);
1908 skb = NULL;
1909 } else {
1910 skb = dev_alloc_skb(rxb);
1911 if (skb == NULL) {
1912 printk("%s: Memory squeeze!!\n", dev->name);
1913 return;
1914 }
1915 skb->dev = dev;
1916 }
1917 }
1918
1919 if (((rxb = dma_buf_read(card, ch, skb)) <= 0) || (skb == NULL)) {
1920#ifdef PC300_DEBUG_RX
1921 printk("%s: rxb = %x\n", dev->name, rxb);
1922#endif
1923 if ((skb == NULL) && (rxb > 0)) {
1924 /* rxb > dev->mtu */
1925 stats->rx_errors++;
1926 stats->rx_length_errors++;
1927 continue;
1928 }
1929
1930 if (rxb < 0) { /* Invalid frame */
1931 rxb = -rxb;
1932 if (rxb & DST_OVR) {
1933 stats->rx_errors++;
1934 stats->rx_fifo_errors++;
1935 }
1936 if (rxb & DST_CRC) {
1937 stats->rx_errors++;
1938 stats->rx_crc_errors++;
1939 }
1940 if (rxb & (DST_RBIT | DST_SHRT | DST_ABT)) {
1941 stats->rx_errors++;
1942 stats->rx_frame_errors++;
1943 }
1944 }
1945 if (skb) {
1946 dev_kfree_skb_irq(skb);
1947 }
1948 continue;
1949 }
1950
1951 stats->rx_bytes += rxb;
1952
1953#ifdef PC300_DEBUG_RX
1954 printk("%s R:", dev->name);
1955 for (i = 0; i < skb->len; i++)
1956 printk(" %02x", *(skb->data + i));
1957 printk("\n");
1958#endif
1959 if (d->trace_on) {
1960 cpc_trace(dev, skb, 'R');
1961 }
1962 stats->rx_packets++;
1963 skb->protocol = hdlc_type_trans(skb, dev);
1964 netif_rx(skb);
1965 }
1966}
1967
1968/************************************/
1969/*** PC300 Interrupt Routines ***/
1970/************************************/
1971static void sca_tx_intr(pc300dev_t *dev)
1972{
1973 pc300ch_t *chan = (pc300ch_t *)dev->chan;
1974 pc300_t *card = (pc300_t *)chan->card;
1975 int ch = chan->channel;
1976 volatile pcsca_bd_t __iomem * ptdescr;
1977 struct net_device_stats *stats = hdlc_stats(dev->dev);
1978
1979 /* Clean up descriptors from previous transmission */
1980 ptdescr = (card->hw.rambase +
1981 TX_BD_ADDR(ch,chan->tx_first_bd));
1982 while ((cpc_readl(card->hw.scabase + DTX_REG(CDAL,ch)) !=
1983 TX_BD_ADDR(ch,chan->tx_first_bd)) &&
1984 (cpc_readb(&ptdescr->status) & DST_OSB)) {
1985 stats->tx_packets++;
1986 stats->tx_bytes += cpc_readw(&ptdescr->len);
1987 cpc_writeb(&ptdescr->status, DST_OSB);
1988 cpc_writew(&ptdescr->len, 0);
1989 chan->nfree_tx_bd++;
1990 chan->tx_first_bd = (chan->tx_first_bd + 1) & (N_DMA_TX_BUF - 1);
1991 ptdescr = (card->hw.rambase + TX_BD_ADDR(ch,chan->tx_first_bd));
1992 }
1993
1994#ifdef CONFIG_PC300_MLPPP
1995 if (chan->conf.proto == PC300_PROTO_MLPPP) {
1996 cpc_tty_trigger_poll(dev);
1997 } else {
1998#endif
1999 /* Tell the upper layer we are ready to transmit more packets */
2000 netif_wake_queue(dev->dev);
2001#ifdef CONFIG_PC300_MLPPP
2002 }
2003#endif
2004}
2005
2006static void sca_intr(pc300_t * card)
2007{
2008 void __iomem *scabase = card->hw.scabase;
2009 volatile uclong status;
2010 int ch;
2011 int intr_count = 0;
2012 unsigned char dsr_rx;
2013
2014 while ((status = cpc_readl(scabase + ISR0)) != 0) {
2015 for (ch = 0; ch < card->hw.nchan; ch++) {
2016 pc300ch_t *chan = &card->chan[ch];
2017 pc300dev_t *d = &chan->d;
2018 struct net_device *dev = d->dev;
2019 hdlc_device *hdlc = dev_to_hdlc(dev);
2020
2021 spin_lock(&card->card_lock);
2022
2023 /**** Reception ****/
2024 if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
2025 ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
2026
2027 /* Clear RX interrupts */
2028 cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
2029
2030#ifdef PC300_DEBUG_INTR
2031 printk ("sca_intr: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2032 ch, status, drx_stat);
2033#endif
2034 if (status & IR0_DRX(IR0_DMIA, ch)) {
2035 if (drx_stat & DSR_BOF) {
2036#ifdef CONFIG_PC300_MLPPP
2037 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2038 /* verify if driver is TTY */
2039 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2040 rx_dma_stop(card, ch);
2041 }
2042 cpc_tty_receive(d);
2043 rx_dma_start(card, ch);
2044 } else
2045#endif
2046 {
2047 if ((cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2048 rx_dma_stop(card, ch);
2049 }
2050 cpc_net_rx(dev);
2051 /* Discard invalid frames */
2052 hdlc->stats.rx_errors++;
2053 hdlc->stats.rx_over_errors++;
2054 chan->rx_first_bd = 0;
2055 chan->rx_last_bd = N_DMA_RX_BUF - 1;
2056 rx_dma_start(card, ch);
2057 }
2058 }
2059 }
2060 if (status & IR0_DRX(IR0_DMIB, ch)) {
2061 if (drx_stat & DSR_EOM) {
2062 if (card->hw.type == PC300_TE) {
2063 cpc_writeb(card->hw.falcbase +
2064 card->hw.cpld_reg2,
2065 cpc_readb (card->hw.falcbase +
2066 card->hw.cpld_reg2) |
2067 (CPLD_REG2_FALC_LED1 << (2 * ch)));
2068 }
2069#ifdef CONFIG_PC300_MLPPP
2070 if (chan->conf.proto == PC300_PROTO_MLPPP) {
2071 /* verify if driver is TTY */
2072 cpc_tty_receive(d);
2073 } else {
2074 cpc_net_rx(dev);
2075 }
2076#else
2077 cpc_net_rx(dev);
2078#endif
2079 if (card->hw.type == PC300_TE) {
2080 cpc_writeb(card->hw.falcbase +
2081 card->hw.cpld_reg2,
2082 cpc_readb (card->hw.falcbase +
2083 card->hw.cpld_reg2) &
2084 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2085 }
2086 }
2087 }
2088 if (!(dsr_rx = cpc_readb(scabase + DSR_RX(ch)) & DSR_DE)) {
2089#ifdef PC300_DEBUG_INTR
2090 printk("%s: RX intr chan[%d] (st=0x%08lx, dsr=0x%02x, dsr2=0x%02x)\n",
2091 dev->name, ch, status, drx_stat, dsr_rx);
2092#endif
2093 cpc_writeb(scabase + DSR_RX(ch), (dsr_rx | DSR_DE) & 0xfe);
2094 }
2095 }
2096
2097 /**** Transmission ****/
2098 if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
2099 ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
2100
2101 /* Clear TX interrupts */
2102 cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
2103
2104#ifdef PC300_DEBUG_INTR
2105 printk ("sca_intr: TX intr chan[%d] (st=0x%08lx, dsr=0x%02x)\n",
2106 ch, status, dtx_stat);
2107#endif
2108 if (status & IR0_DTX(IR0_EFT, ch)) {
2109 if (dtx_stat & DSR_UDRF) {
2110 if (cpc_readb (scabase + M_REG(TBN, ch)) != 0) {
2111 cpc_writeb(scabase + M_REG(CMD,ch), CMD_TX_BUF_CLR);
2112 }
2113 if (card->hw.type == PC300_TE) {
2114 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2115 cpc_readb (card->hw.falcbase +
2116 card->hw.cpld_reg2) &
2117 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2118 }
2119 hdlc->stats.tx_errors++;
2120 hdlc->stats.tx_fifo_errors++;
2121 sca_tx_intr(d);
2122 }
2123 }
2124 if (status & IR0_DTX(IR0_DMIA, ch)) {
2125 if (dtx_stat & DSR_BOF) {
2126 }
2127 }
2128 if (status & IR0_DTX(IR0_DMIB, ch)) {
2129 if (dtx_stat & DSR_EOM) {
2130 if (card->hw.type == PC300_TE) {
2131 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
2132 cpc_readb (card->hw.falcbase +
2133 card->hw.cpld_reg2) &
2134 ~ (CPLD_REG2_FALC_LED1 << (2 * ch)));
2135 }
2136 sca_tx_intr(d);
2137 }
2138 }
2139 }
2140
2141 /**** MSCI ****/
2142 if (status & IR0_M(IR0_RXINTA, ch)) {
2143 ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
2144
2145 /* Clear MSCI interrupts */
2146 cpc_writeb(scabase + M_REG(ST1, ch), st1);
2147
2148#ifdef PC300_DEBUG_INTR
2149 printk("sca_intr: MSCI intr chan[%d] (st=0x%08lx, st1=0x%02x)\n",
2150 ch, status, st1);
2151#endif
2152 if (st1 & ST1_CDCD) { /* DCD changed */
2153 if (cpc_readb(scabase + M_REG(ST3, ch)) & ST3_DCD) {
2154 printk ("%s: DCD is OFF. Going administrative down.\n",
2155 dev->name);
2156#ifdef CONFIG_PC300_MLPPP
2157 if (chan->conf.proto != PC300_PROTO_MLPPP) {
2158 netif_carrier_off(dev);
2159 }
2160#else
2161 netif_carrier_off(dev);
2162
2163#endif
2164 card->chan[ch].d.line_off++;
2165 } else { /* DCD = 1 */
2166 printk ("%s: DCD is ON. Going administrative up.\n",
2167 dev->name);
2168#ifdef CONFIG_PC300_MLPPP
2169 if (chan->conf.proto != PC300_PROTO_MLPPP)
2170 /* verify if driver is not TTY */
2171#endif
2172 netif_carrier_on(dev);
2173 card->chan[ch].d.line_on++;
2174 }
2175 }
2176 }
2177 spin_unlock(&card->card_lock);
2178 }
2179 if (++intr_count == 10)
2180 /* Too much work at this board. Force exit */
2181 break;
2182 }
2183}
2184
2185static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
2186{
2187 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2188 falc_t *pfalc = (falc_t *) & chan->falc;
2189 void __iomem *falcbase = card->hw.falcbase;
2190
2191 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2192 !pfalc->loop_gen) {
2193 if (frs1 & FRS1_LLBDD) {
2194 // A Line Loop Back Deactivation signal detected
2195 if (pfalc->loop_active) {
2196 falc_remote_loop(card, ch, 0);
2197 }
2198 } else {
2199 if ((frs1 & FRS1_LLBAD) &&
2200 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2201 // A Line Loop Back Activation signal detected
2202 if (!pfalc->loop_active) {
2203 falc_remote_loop(card, ch, 1);
2204 }
2205 }
2206 }
2207 }
2208}
2209
2210static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
2211{
2212 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2213 falc_t *pfalc = (falc_t *) & chan->falc;
2214 void __iomem *falcbase = card->hw.falcbase;
2215
2216 if (((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_XPRBS) == 0) &&
2217 !pfalc->loop_gen) {
2218 if (rsp & RSP_LLBDD) {
2219 // A Line Loop Back Deactivation signal detected
2220 if (pfalc->loop_active) {
2221 falc_remote_loop(card, ch, 0);
2222 }
2223 } else {
2224 if ((rsp & RSP_LLBAD) &&
2225 ((cpc_readb(falcbase + F_REG(LCR1, ch)) & LCR1_EPRM) == 0)) {
2226 // A Line Loop Back Activation signal detected
2227 if (!pfalc->loop_active) {
2228 falc_remote_loop(card, ch, 1);
2229 }
2230 }
2231 }
2232 }
2233}
2234
2235static void falc_t1_intr(pc300_t * card, int ch)
2236{
2237 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2238 falc_t *pfalc = (falc_t *) & chan->falc;
2239 void __iomem *falcbase = card->hw.falcbase;
2240 ucchar isr0, isr3, gis;
2241 ucchar dummy;
2242
2243 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2244 if (gis & GIS_ISR0) {
2245 isr0 = cpc_readb(falcbase + F_REG(FISR0, ch));
2246 if (isr0 & FISR0_PDEN) {
2247 /* Read the bit to clear the situation */
2248 if (cpc_readb(falcbase + F_REG(FRS1, ch)) &
2249 FRS1_PDEN) {
2250 pfalc->pden++;
2251 }
2252 }
2253 }
2254
2255 if (gis & GIS_ISR1) {
2256 dummy = cpc_readb(falcbase + F_REG(FISR1, ch));
2257 }
2258
2259 if (gis & GIS_ISR2) {
2260 dummy = cpc_readb(falcbase + F_REG(FISR2, ch));
2261 }
2262
2263 if (gis & GIS_ISR3) {
2264 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2265 if (isr3 & FISR3_SEC) {
2266 pfalc->sec++;
2267 falc_update_stats(card, ch);
2268 falc_check_status(card, ch,
2269 cpc_readb(falcbase + F_REG(FRS0, ch)));
2270 }
2271 if (isr3 & FISR3_ES) {
2272 pfalc->es++;
2273 }
2274 if (isr3 & FISR3_LLBSC) {
2275 falc_t1_loop_detection(card, ch,
2276 cpc_readb(falcbase + F_REG(FRS1, ch)));
2277 }
2278 }
2279 }
2280}
2281
2282static void falc_e1_intr(pc300_t * card, int ch)
2283{
2284 pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
2285 falc_t *pfalc = (falc_t *) & chan->falc;
2286 void __iomem *falcbase = card->hw.falcbase;
2287 ucchar isr1, isr2, isr3, gis, rsp;
2288 ucchar dummy;
2289
2290 while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
2291 rsp = cpc_readb(falcbase + F_REG(RSP, ch));
2292
2293 if (gis & GIS_ISR0) {
2294 dummy = cpc_readb(falcbase + F_REG(FISR0, ch));
2295 }
2296 if (gis & GIS_ISR1) {
2297 isr1 = cpc_readb(falcbase + F_REG(FISR1, ch));
2298 if (isr1 & FISR1_XMB) {
2299 if ((pfalc->xmb_cause & 2)
2300 && pfalc->multiframe_mode) {
2301 if (cpc_readb (falcbase + F_REG(FRS0, ch)) &
2302 (FRS0_LOS | FRS0_AIS | FRS0_LFA)) {
2303 cpc_writeb(falcbase + F_REG(XSP, ch),
2304 cpc_readb(falcbase + F_REG(XSP, ch))
2305 & ~XSP_AXS);
2306 } else {
2307 cpc_writeb(falcbase + F_REG(XSP, ch),
2308 cpc_readb(falcbase + F_REG(XSP, ch))
2309 | XSP_AXS);
2310 }
2311 }
2312 pfalc->xmb_cause = 0;
2313 cpc_writeb(falcbase + F_REG(IMR1, ch),
2314 cpc_readb(falcbase + F_REG(IMR1, ch)) | IMR1_XMB);
2315 }
2316 if (isr1 & FISR1_LLBSC) {
2317 falc_e1_loop_detection(card, ch, rsp);
2318 }
2319 }
2320 if (gis & GIS_ISR2) {
2321 isr2 = cpc_readb(falcbase + F_REG(FISR2, ch));
2322 if (isr2 & FISR2_T400MS) {
2323 cpc_writeb(falcbase + F_REG(XSW, ch),
2324 cpc_readb(falcbase + F_REG(XSW, ch)) | XSW_XRA);
2325 }
2326 if (isr2 & FISR2_MFAR) {
2327 cpc_writeb(falcbase + F_REG(XSW, ch),
2328 cpc_readb(falcbase + F_REG(XSW, ch)) & ~XSW_XRA);
2329 }
2330 if (isr2 & (FISR2_FAR | FISR2_LFA | FISR2_AIS | FISR2_LOS)) {
2331 pfalc->xmb_cause |= 2;
2332 cpc_writeb(falcbase + F_REG(IMR1, ch),
2333 cpc_readb(falcbase + F_REG(IMR1, ch)) & ~IMR1_XMB);
2334 }
2335 }
2336 if (gis & GIS_ISR3) {
2337 isr3 = cpc_readb(falcbase + F_REG(FISR3, ch));
2338 if (isr3 & FISR3_SEC) {
2339 pfalc->sec++;
2340 falc_update_stats(card, ch);
2341 falc_check_status(card, ch,
2342 cpc_readb(falcbase + F_REG(FRS0, ch)));
2343 }
2344 if (isr3 & FISR3_ES) {
2345 pfalc->es++;
2346 }
2347 }
2348 }
2349}
2350
2351static void falc_intr(pc300_t * card)
2352{
2353 int ch;
2354
2355 for (ch = 0; ch < card->hw.nchan; ch++) {
2356 pc300ch_t *chan = &card->chan[ch];
2357 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2358
2359 if (conf->media == IF_IFACE_T1) {
2360 falc_t1_intr(card, ch);
2361 } else {
2362 falc_e1_intr(card, ch);
2363 }
2364 }
2365}
2366
2367static irqreturn_t cpc_intr(int irq, void *dev_id, struct pt_regs *regs)
2368{
2369 pc300_t *card;
2370 volatile ucchar plx_status;
2371
2372 if ((card = (pc300_t *) dev_id) == 0) {
2373#ifdef PC300_DEBUG_INTR
2374 printk("cpc_intr: spurious intr %d\n", irq);
2375#endif
2376 return IRQ_NONE; /* spurious intr */
2377 }
2378
2379 if (card->hw.rambase == 0) {
2380#ifdef PC300_DEBUG_INTR
2381 printk("cpc_intr: spurious intr2 %d\n", irq);
2382#endif
2383 return IRQ_NONE; /* spurious intr */
2384 }
2385
2386 switch (card->hw.type) {
2387 case PC300_RSV:
2388 case PC300_X21:
2389 sca_intr(card);
2390 break;
2391
2392 case PC300_TE:
2393 while ( (plx_status = (cpc_readb(card->hw.plxbase + card->hw.intctl_reg) &
2394 (PLX_9050_LINT1_STATUS | PLX_9050_LINT2_STATUS))) != 0) {
2395 if (plx_status & PLX_9050_LINT1_STATUS) { /* SCA Interrupt */
2396 sca_intr(card);
2397 }
2398 if (plx_status & PLX_9050_LINT2_STATUS) { /* FALC Interrupt */
2399 falc_intr(card);
2400 }
2401 }
2402 break;
2403 }
2404 return IRQ_HANDLED;
2405}
2406
7665a089 2407static void cpc_sca_status(pc300_t * card, int ch)
1da177e4
LT		 2408{
2409 ucchar ilar;
2410 void __iomem *scabase = card->hw.scabase;
2411 unsigned long flags;
2412
2413 tx_dma_buf_check(card, ch);
2414 rx_dma_buf_check(card, ch);
2415 ilar = cpc_readb(scabase + ILAR);
2416 printk ("ILAR=0x%02x, WCRL=0x%02x, PCR=0x%02x, BTCR=0x%02x, BOLR=0x%02x\n",
2417 ilar, cpc_readb(scabase + WCRL), cpc_readb(scabase + PCR),
2418 cpc_readb(scabase + BTCR), cpc_readb(scabase + BOLR));
2419 printk("TX_CDA=0x%08x, TX_EDA=0x%08x\n",
2420 cpc_readl(scabase + DTX_REG(CDAL, ch)),
2421 cpc_readl(scabase + DTX_REG(EDAL, ch)));
2422 printk("RX_CDA=0x%08x, RX_EDA=0x%08x, BFL=0x%04x\n",
2423 cpc_readl(scabase + DRX_REG(CDAL, ch)),
2424 cpc_readl(scabase + DRX_REG(EDAL, ch)),
2425 cpc_readw(scabase + DRX_REG(BFLL, ch)));
2426 printk("DMER=0x%02x, DSR_TX=0x%02x, DSR_RX=0x%02x\n",
2427 cpc_readb(scabase + DMER), cpc_readb(scabase + DSR_TX(ch)),
2428 cpc_readb(scabase + DSR_RX(ch)));
2429 printk("DMR_TX=0x%02x, DMR_RX=0x%02x, DIR_TX=0x%02x, DIR_RX=0x%02x\n",
2430 cpc_readb(scabase + DMR_TX(ch)), cpc_readb(scabase + DMR_RX(ch)),
2431 cpc_readb(scabase + DIR_TX(ch)),
2432 cpc_readb(scabase + DIR_RX(ch)));
2433 printk("DCR_TX=0x%02x, DCR_RX=0x%02x, FCT_TX=0x%02x, FCT_RX=0x%02x\n",
2434 cpc_readb(scabase + DCR_TX(ch)), cpc_readb(scabase + DCR_RX(ch)),
2435 cpc_readb(scabase + FCT_TX(ch)),
2436 cpc_readb(scabase + FCT_RX(ch)));
2437 printk("MD0=0x%02x, MD1=0x%02x, MD2=0x%02x, MD3=0x%02x, IDL=0x%02x\n",
2438 cpc_readb(scabase + M_REG(MD0, ch)),
2439 cpc_readb(scabase + M_REG(MD1, ch)),
2440 cpc_readb(scabase + M_REG(MD2, ch)),
2441 cpc_readb(scabase + M_REG(MD3, ch)),
2442 cpc_readb(scabase + M_REG(IDL, ch)));
2443 printk("CMD=0x%02x, SA0=0x%02x, SA1=0x%02x, TFN=0x%02x, CTL=0x%02x\n",
2444 cpc_readb(scabase + M_REG(CMD, ch)),
2445 cpc_readb(scabase + M_REG(SA0, ch)),
2446 cpc_readb(scabase + M_REG(SA1, ch)),
2447 cpc_readb(scabase + M_REG(TFN, ch)),
2448 cpc_readb(scabase + M_REG(CTL, ch)));
2449 printk("ST0=0x%02x, ST1=0x%02x, ST2=0x%02x, ST3=0x%02x, ST4=0x%02x\n",
2450 cpc_readb(scabase + M_REG(ST0, ch)),
2451 cpc_readb(scabase + M_REG(ST1, ch)),
2452 cpc_readb(scabase + M_REG(ST2, ch)),
2453 cpc_readb(scabase + M_REG(ST3, ch)),
2454 cpc_readb(scabase + M_REG(ST4, ch)));
2455 printk ("CST0=0x%02x, CST1=0x%02x, CST2=0x%02x, CST3=0x%02x, FST=0x%02x\n",
2456 cpc_readb(scabase + M_REG(CST0, ch)),
2457 cpc_readb(scabase + M_REG(CST1, ch)),
2458 cpc_readb(scabase + M_REG(CST2, ch)),
2459 cpc_readb(scabase + M_REG(CST3, ch)),
2460 cpc_readb(scabase + M_REG(FST, ch)));
2461 printk("TRC0=0x%02x, TRC1=0x%02x, RRC=0x%02x, TBN=0x%02x, RBN=0x%02x\n",
2462 cpc_readb(scabase + M_REG(TRC0, ch)),
2463 cpc_readb(scabase + M_REG(TRC1, ch)),
2464 cpc_readb(scabase + M_REG(RRC, ch)),
2465 cpc_readb(scabase + M_REG(TBN, ch)),
2466 cpc_readb(scabase + M_REG(RBN, ch)));
2467 printk("TFS=0x%02x, TNR0=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2468 cpc_readb(scabase + M_REG(TFS, ch)),
2469 cpc_readb(scabase + M_REG(TNR0, ch)),
2470 cpc_readb(scabase + M_REG(TNR1, ch)),
2471 cpc_readb(scabase + M_REG(RNR, ch)));
2472 printk("TCR=0x%02x, RCR=0x%02x, TNR1=0x%02x, RNR=0x%02x\n",
2473 cpc_readb(scabase + M_REG(TCR, ch)),
2474 cpc_readb(scabase + M_REG(RCR, ch)),
2475 cpc_readb(scabase + M_REG(TNR1, ch)),
2476 cpc_readb(scabase + M_REG(RNR, ch)));
2477 printk("TXS=0x%02x, RXS=0x%02x, EXS=0x%02x, TMCT=0x%02x, TMCR=0x%02x\n",
2478 cpc_readb(scabase + M_REG(TXS, ch)),
2479 cpc_readb(scabase + M_REG(RXS, ch)),
2480 cpc_readb(scabase + M_REG(EXS, ch)),
2481 cpc_readb(scabase + M_REG(TMCT, ch)),
2482 cpc_readb(scabase + M_REG(TMCR, ch)));
2483 printk("IE0=0x%02x, IE1=0x%02x, IE2=0x%02x, IE4=0x%02x, FIE=0x%02x\n",
2484 cpc_readb(scabase + M_REG(IE0, ch)),
2485 cpc_readb(scabase + M_REG(IE1, ch)),
2486 cpc_readb(scabase + M_REG(IE2, ch)),
2487 cpc_readb(scabase + M_REG(IE4, ch)),
2488 cpc_readb(scabase + M_REG(FIE, ch)));
2489 printk("IER0=0x%08x\n", cpc_readl(scabase + IER0));
2490
2491 if (ilar != 0) {
2492 CPC_LOCK(card, flags);
2493 cpc_writeb(scabase + ILAR, ilar);
2494 cpc_writeb(scabase + DMER, 0x80);
2495 CPC_UNLOCK(card, flags);
2496 }
2497}
2498
7665a089 2499static void cpc_falc_status(pc300_t * card, int ch)
1da177e4
LT		 2500{
2501 pc300ch_t *chan = &card->chan[ch];
2502 falc_t *pfalc = (falc_t *) & chan->falc;
2503 unsigned long flags;
2504
2505 CPC_LOCK(card, flags);
2506 printk("CH%d: %s %s %d channels\n",
2507 ch, (pfalc->sync ? "SYNC" : ""), (pfalc->active ? "ACTIVE" : ""),
2508 pfalc->num_channels);
2509
2510 printk(" pden=%d, los=%d, losr=%d, lfa=%d, farec=%d\n",
2511 pfalc->pden, pfalc->los, pfalc->losr, pfalc->lfa, pfalc->farec);
2512 printk(" lmfa=%d, ais=%d, sec=%d, es=%d, rai=%d\n",
2513 pfalc->lmfa, pfalc->ais, pfalc->sec, pfalc->es, pfalc->rai);
2514 printk(" bec=%d, fec=%d, cvc=%d, cec=%d, ebc=%d\n",
2515 pfalc->bec, pfalc->fec, pfalc->cvc, pfalc->cec, pfalc->ebc);
2516
2517 printk("\n");
2518 printk(" STATUS: %s %s %s %s %s %s\n",
2519 (pfalc->red_alarm ? "RED" : ""),
2520 (pfalc->blue_alarm ? "BLU" : ""),
2521 (pfalc->yellow_alarm ? "YEL" : ""),
2522 (pfalc->loss_fa ? "LFA" : ""),
2523 (pfalc->loss_mfa ? "LMF" : ""), (pfalc->prbs ? "PRB" : ""));
2524 CPC_UNLOCK(card, flags);
2525}
2526
7665a089 2527static int cpc_change_mtu(struct net_device *dev, int new_mtu)
1da177e4
LT		 2528{
2529 if ((new_mtu < 128) || (new_mtu > PC300_DEF_MTU))
2530 return -EINVAL;
2531 dev->mtu = new_mtu;
2532 return 0;
2533}
2534
7665a089 2535static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4
LT		 2536{
2537 hdlc_device *hdlc = dev_to_hdlc(dev);
2538 pc300dev_t *d = (pc300dev_t *) dev->priv;
2539 pc300ch_t *chan = (pc300ch_t *) d->chan;
2540 pc300_t *card = (pc300_t *) chan->card;
2541 pc300conf_t conf_aux;
2542 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2543 int ch = chan->channel;
2544 void __user *arg = ifr->ifr_data;
2545 struct if_settings *settings = &ifr->ifr_settings;
2546 void __iomem *scabase = card->hw.scabase;
2547
2548 if (!capable(CAP_NET_ADMIN))
2549 return -EPERM;
2550
2551 switch (cmd) {
2552 case SIOCGPC300CONF:
2553#ifdef CONFIG_PC300_MLPPP
2554 if (conf->proto != PC300_PROTO_MLPPP) {
2555 conf->proto = hdlc->proto.id;
2556 }
2557#else
2558 conf->proto = hdlc->proto.id;
2559#endif
2560 memcpy(&conf_aux.conf, conf, sizeof(pc300chconf_t));
2561 memcpy(&conf_aux.hw, &card->hw, sizeof(pc300hw_t));
2562 if (!arg ||
2563 copy_to_user(arg, &conf_aux, sizeof(pc300conf_t)))
2564 return -EINVAL;
2565 return 0;
2566 case SIOCSPC300CONF:
2567 if (!capable(CAP_NET_ADMIN))
2568 return -EPERM;
2569 if (!arg ||
2570 copy_from_user(&conf_aux.conf, arg, sizeof(pc300chconf_t)))
2571 return -EINVAL;
2572 if (card->hw.cpld_id < 0x02 &&
2573 conf_aux.conf.fr_mode == PC300_FR_UNFRAMED) {
2574 /* CPLD_ID < 0x02 doesn't support Unframed E1 */
2575 return -EINVAL;
2576 }
2577#ifdef CONFIG_PC300_MLPPP
2578 if (conf_aux.conf.proto == PC300_PROTO_MLPPP) {
2579 if (conf->proto != PC300_PROTO_MLPPP) {
2580 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2581 cpc_tty_init(d); /* init TTY driver */
2582 }
2583 } else {
2584 if (conf_aux.conf.proto == 0xffff) {
2585 if (conf->proto == PC300_PROTO_MLPPP){
2586 /* ifdown interface */
2587 cpc_close(dev);
2588 }
2589 } else {
2590 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2591 hdlc->proto.id = conf->proto;
2592 }
2593 }
2594#else
2595 memcpy(conf, &conf_aux.conf, sizeof(pc300chconf_t));
2596 hdlc->proto.id = conf->proto;
2597#endif
2598 return 0;
2599 case SIOCGPC300STATUS:
2600 cpc_sca_status(card, ch);
2601 return 0;
2602 case SIOCGPC300FALCSTATUS:
2603 cpc_falc_status(card, ch);
2604 return 0;
2605
2606 case SIOCGPC300UTILSTATS:
2607 {
2608 if (!arg) { /* clear statistics */
2609 memset(&hdlc->stats, 0, sizeof(struct net_device_stats));
2610 if (card->hw.type == PC300_TE) {
2611 memset(&chan->falc, 0, sizeof(falc_t));
2612 }
2613 } else {
2614 pc300stats_t pc300stats;
2615
2616 memset(&pc300stats, 0, sizeof(pc300stats_t));
2617 pc300stats.hw_type = card->hw.type;
2618 pc300stats.line_on = card->chan[ch].d.line_on;
2619 pc300stats.line_off = card->chan[ch].d.line_off;
2620 memcpy(&pc300stats.gen_stats, &hdlc->stats,
2621 sizeof(struct net_device_stats));
2622 if (card->hw.type == PC300_TE)
2623 memcpy(&pc300stats.te_stats,&chan->falc,sizeof(falc_t));
2624 if (copy_to_user(arg, &pc300stats, sizeof(pc300stats_t)))
2625 return -EFAULT;
2626 }
2627 return 0;
2628 }
2629
2630 case SIOCGPC300UTILSTATUS:
2631 {
2632 struct pc300status pc300status;
2633
2634 pc300status.hw_type = card->hw.type;
2635 if (card->hw.type == PC300_TE) {
2636 pc300status.te_status.sync = chan->falc.sync;
2637 pc300status.te_status.red_alarm = chan->falc.red_alarm;
2638 pc300status.te_status.blue_alarm = chan->falc.blue_alarm;
2639 pc300status.te_status.loss_fa = chan->falc.loss_fa;
2640 pc300status.te_status.yellow_alarm =chan->falc.yellow_alarm;
2641 pc300status.te_status.loss_mfa = chan->falc.loss_mfa;
2642 pc300status.te_status.prbs = chan->falc.prbs;
2643 } else {
2644 pc300status.gen_status.dcd =
2645 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_DCD);
2646 pc300status.gen_status.cts =
2647 !(cpc_readb (scabase + M_REG(ST3, ch)) & ST3_CTS);
2648 pc300status.gen_status.rts =
2649 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_RTS);
2650 pc300status.gen_status.dtr =
2651 !(cpc_readb (scabase + M_REG(CTL, ch)) & CTL_DTR);
2652 /* There is no DSR in HD64572 */
2653 }
2654 if (!arg
2655 || copy_to_user(arg, &pc300status, sizeof(pc300status_t)))
2656 return -EINVAL;
2657 return 0;
2658 }
2659
2660 case SIOCSPC300TRACE:
2661 /* Sets/resets a trace_flag for the respective device */
2662 if (!arg || copy_from_user(&d->trace_on, arg,sizeof(unsigned char)))
2663 return -EINVAL;
2664 return 0;
2665
2666 case SIOCSPC300LOOPBACK:
2667 {
2668 struct pc300loopback pc300loop;
2669
2670 /* TE boards only */
2671 if (card->hw.type != PC300_TE)
2672 return -EINVAL;
2673
2674 if (!arg ||
2675 copy_from_user(&pc300loop, arg, sizeof(pc300loopback_t)))
2676 return -EINVAL;
2677 switch (pc300loop.loop_type) {
2678 case PC300LOCLOOP: /* Turn the local loop on/off */
2679 falc_local_loop(card, ch, pc300loop.loop_on);
2680 return 0;
2681
2682 case PC300REMLOOP: /* Turn the remote loop on/off */
2683 falc_remote_loop(card, ch, pc300loop.loop_on);
2684 return 0;
2685
2686 case PC300PAYLOADLOOP: /* Turn the payload loop on/off */
2687 falc_payload_loop(card, ch, pc300loop.loop_on);
2688 return 0;
2689
2690 case PC300GENLOOPUP: /* Generate loop UP */
2691 if (pc300loop.loop_on) {
2692 falc_generate_loop_up_code (card, ch);
2693 } else {
2694 turn_off_xlu(card, ch);
2695 }
2696 return 0;
2697
2698 case PC300GENLOOPDOWN: /* Generate loop DOWN */
2699 if (pc300loop.loop_on) {
2700 falc_generate_loop_down_code (card, ch);
2701 } else {
2702 turn_off_xld(card, ch);
2703 }
2704 return 0;
2705
2706 default:
2707 return -EINVAL;
2708 }
2709 }
2710
2711 case SIOCSPC300PATTERNTEST:
2712 /* Turn the pattern test on/off and show the errors counter */
2713 {
2714 struct pc300patterntst pc300patrntst;
2715
2716 /* TE boards only */
2717 if (card->hw.type != PC300_TE)
2718 return -EINVAL;
2719
2720 if (card->hw.cpld_id < 0x02) {
2721 /* CPLD_ID < 0x02 doesn't support pattern test */
2722 return -EINVAL;
2723 }
2724
2725 if (!arg ||
2726 copy_from_user(&pc300patrntst,arg,sizeof(pc300patterntst_t)))
2727 return -EINVAL;
2728 if (pc300patrntst.patrntst_on == 2) {
2729 if (chan->falc.prbs == 0) {
2730 falc_pattern_test(card, ch, 1);
2731 }
2732 pc300patrntst.num_errors =
2733 falc_pattern_test_error(card, ch);
2734 if (!arg
2735 || copy_to_user(arg, &pc300patrntst,
2736 sizeof (pc300patterntst_t)))
2737 return -EINVAL;
2738 } else {
2739 falc_pattern_test(card, ch, pc300patrntst.patrntst_on);
2740 }
2741 return 0;
2742 }
2743
2744 case SIOCWANDEV:
2745 switch (ifr->ifr_settings.type) {
2746 case IF_GET_IFACE:
2747 {
2748 const size_t size = sizeof(sync_serial_settings);
2749 ifr->ifr_settings.type = conf->media;
2750 if (ifr->ifr_settings.size < size) {
2751 /* data size wanted */
2752 ifr->ifr_settings.size = size;
2753 return -ENOBUFS;
2754 }
2755
2756 if (copy_to_user(settings->ifs_ifsu.sync,
2757 &conf->phys_settings, size)) {
2758 return -EFAULT;
2759 }
2760 return 0;
2761 }
2762
2763 case IF_IFACE_V35:
2764 case IF_IFACE_V24:
2765 case IF_IFACE_X21:
2766 {
2767 const size_t size = sizeof(sync_serial_settings);
2768
2769 if (!capable(CAP_NET_ADMIN)) {
2770 return -EPERM;
2771 }
2772 /* incorrect data len? */
2773 if (ifr->ifr_settings.size != size) {
2774 return -ENOBUFS;
2775 }
2776
2777 if (copy_from_user(&conf->phys_settings,
2778 settings->ifs_ifsu.sync, size)) {
2779 return -EFAULT;
2780 }
2781
2782 if (conf->phys_settings.loopback) {
2783 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2784 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2785 MD2_LOOP_MIR);
2786 }
2787 conf->media = ifr->ifr_settings.type;
2788 return 0;
2789 }
2790
2791 case IF_IFACE_T1:
2792 case IF_IFACE_E1:
2793 {
2794 const size_t te_size = sizeof(te1_settings);
2795 const size_t size = sizeof(sync_serial_settings);
2796
2797 if (!capable(CAP_NET_ADMIN)) {
2798 return -EPERM;
2799 }
2800
2801 /* incorrect data len? */
2802 if (ifr->ifr_settings.size != te_size) {
2803 return -ENOBUFS;
2804 }
2805
2806 if (copy_from_user(&conf->phys_settings,
2807 settings->ifs_ifsu.te1, size)) {
2808 return -EFAULT;
2809 }/* Ignoring HDLC slot_map for a while */
2810
2811 if (conf->phys_settings.loopback) {
2812 cpc_writeb(card->hw.scabase + M_REG(MD2, ch),
2813 cpc_readb(card->hw.scabase + M_REG(MD2, ch)) |
2814 MD2_LOOP_MIR);
2815 }
2816 conf->media = ifr->ifr_settings.type;
2817 return 0;
2818 }
2819 default:
2820 return hdlc_ioctl(dev, ifr, cmd);
2821 }
2822
2823 default:
2824 return hdlc_ioctl(dev, ifr, cmd);
2825 }
2826}
2827
2828static struct net_device_stats *cpc_get_stats(struct net_device *dev)
2829{
2830 return hdlc_stats(dev);
2831}
2832
2833static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
2834{
2835 int br, tc;
2836 int br_pwr, error;
2837
2838 if (rate == 0)
2839 return (0);
2840
2841 for (br = 0, br_pwr = 1; br <= 9; br++, br_pwr <<= 1) {
2842 if ((tc = clock / br_pwr / rate) <= 0xff) {
2843 *br_io = br;
2844 break;
2845 }
2846 }
2847
2848 if (tc <= 0xff) {
2849 error = ((rate - (clock / br_pwr / rate)) / rate) * 1000;
2850 /* Errors bigger than +/- 1% won't be tolerated */
2851 if (error < -10 || error > 10)
2852 return (-1);
2853 else
2854 return (tc);
2855 } else {
2856 return (-1);
2857 }
2858}
2859
7665a089 2860static int ch_config(pc300dev_t * d)
1da177e4
LT		 2861{
2862 pc300ch_t *chan = (pc300ch_t *) d->chan;
2863 pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
2864 pc300_t *card = (pc300_t *) chan->card;
2865 void __iomem *scabase = card->hw.scabase;
2866 void __iomem *plxbase = card->hw.plxbase;
2867 int ch = chan->channel;
2868 uclong clkrate = chan->conf.phys_settings.clock_rate;
2869 uclong clktype = chan->conf.phys_settings.clock_type;
2870 ucshort encoding = chan->conf.proto_settings.encoding;
2871 ucshort parity = chan->conf.proto_settings.parity;
2872 int tmc, br;
2873 ucchar md0, md2;
2874
2875 /* Reset the channel */
2876 cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
2877
2878 /* Configure the SCA registers */
2879 switch (parity) {
2880 case PARITY_NONE:
2881 md0 = MD0_BIT_SYNC;
2882 break;
2883 case PARITY_CRC16_PR0:
2884 md0 = MD0_CRC16_0|MD0_CRCC0|MD0_BIT_SYNC;
2885 break;
2886 case PARITY_CRC16_PR1:
2887 md0 = MD0_CRC16_1|MD0_CRCC0|MD0_BIT_SYNC;
2888 break;
2889 case PARITY_CRC32_PR1_CCITT:
2890 md0 = MD0_CRC32|MD0_CRCC0|MD0_BIT_SYNC;
2891 break;
2892 case PARITY_CRC16_PR1_CCITT:
2893 default:
2894 md0 = MD0_CRC_CCITT|MD0_CRCC0|MD0_BIT_SYNC;
2895 break;
2896 }
2897 switch (encoding) {
2898 case ENCODING_NRZI:
2899 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZI;
2900 break;
2901 case ENCODING_FM_MARK: /* FM1 */
2902 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM1;
2903 break;
2904 case ENCODING_FM_SPACE: /* FM0 */
2905 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_FM0;
2906 break;
2907 case ENCODING_MANCHESTER: /* It's not working... */
2908 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_FM|MD2_MANCH;
2909 break;
2910 case ENCODING_NRZ:
2911 default:
2912 md2 = MD2_F_DUPLEX|MD2_ADPLL_X8|MD2_NRZ;
2913 break;
2914 }
2915 cpc_writeb(scabase + M_REG(MD0, ch), md0);
2916 cpc_writeb(scabase + M_REG(MD1, ch), 0);
2917 cpc_writeb(scabase + M_REG(MD2, ch), md2);
2918 cpc_writeb(scabase + M_REG(IDL, ch), 0x7e);
2919 cpc_writeb(scabase + M_REG(CTL, ch), CTL_URSKP | CTL_IDLC);
2920
2921 /* Configure HW media */
2922 switch (card->hw.type) {
2923 case PC300_RSV:
2924 if (conf->media == IF_IFACE_V35) {
2925 cpc_writel((plxbase + card->hw.gpioc_reg),
2926 cpc_readl(plxbase + card->hw.gpioc_reg) | PC300_CHMEDIA_MASK(ch));
2927 } else {
2928 cpc_writel((plxbase + card->hw.gpioc_reg),
2929 cpc_readl(plxbase + card->hw.gpioc_reg) & ~PC300_CHMEDIA_MASK(ch));
2930 }
2931 break;
2932
2933 case PC300_X21:
2934 break;
2935
2936 case PC300_TE:
2937 te_config(card, ch);
2938 break;
2939 }
2940
2941 switch (card->hw.type) {
2942 case PC300_RSV:
2943 case PC300_X21:
2944 if (clktype == CLOCK_INT || clktype == CLOCK_TXINT) {
2945 /* Calculate the clkrate parameters */
2946 tmc = clock_rate_calc(clkrate, card->hw.clock, &br);
2947 cpc_writeb(scabase + M_REG(TMCT, ch), tmc);
2948 cpc_writeb(scabase + M_REG(TXS, ch),
2949 (TXS_DTRXC | TXS_IBRG | br));
2950 if (clktype == CLOCK_INT) {
2951 cpc_writeb(scabase + M_REG(TMCR, ch), tmc);
2952 cpc_writeb(scabase + M_REG(RXS, ch),
2953 (RXS_IBRG | br));
2954 } else {
2955 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2956 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2957 }
2958 if (card->hw.type == PC300_X21) {
2959 cpc_writeb(scabase + M_REG(GPO, ch), 1);
2960 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2961 } else {
2962 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2963 }
2964 } else {
2965 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2966 if (clktype == CLOCK_EXT) {
2967 cpc_writeb(scabase + M_REG(TXS, ch),
2968 TXS_DTRXC);
2969 } else {
2970 cpc_writeb(scabase + M_REG(TXS, ch),
2971 TXS_DTRXC|TXS_RCLK);
2972 }
2973 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2974 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2975 if (card->hw.type == PC300_X21) {
2976 cpc_writeb(scabase + M_REG(GPO, ch), 0);
2977 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1 | EXS_RES1);
2978 } else {
2979 cpc_writeb(scabase + M_REG(EXS, ch), EXS_TES1);
2980 }
2981 }
2982 break;
2983
2984 case PC300_TE:
2985 /* SCA always receives clock from the FALC chip */
2986 cpc_writeb(scabase + M_REG(TMCT, ch), 1);
2987 cpc_writeb(scabase + M_REG(TXS, ch), 0);
2988 cpc_writeb(scabase + M_REG(TMCR, ch), 1);
2989 cpc_writeb(scabase + M_REG(RXS, ch), 0);
2990 cpc_writeb(scabase + M_REG(EXS, ch), 0);
2991 break;
2992 }
2993
2994 /* Enable Interrupts */
2995 cpc_writel(scabase + IER0,
2996 cpc_readl(scabase + IER0) |
2997 IR0_M(IR0_RXINTA, ch) |
2998 IR0_DRX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch) |
2999 IR0_DTX(IR0_EFT | IR0_DMIA | IR0_DMIB, ch));
3000 cpc_writeb(scabase + M_REG(IE0, ch),
3001 cpc_readl(scabase + M_REG(IE0, ch)) | IE0_RXINTA);
3002 cpc_writeb(scabase + M_REG(IE1, ch),
3003 cpc_readl(scabase + M_REG(IE1, ch)) | IE1_CDCD);
3004
3005 return 0;
3006}
3007
7665a089 3008static int rx_config(pc300dev_t * d)
1da177e4
LT		 3009{
3010 pc300ch_t *chan = (pc300ch_t *) d->chan;
3011 pc300_t *card = (pc300_t *) chan->card;
3012 void __iomem *scabase = card->hw.scabase;
3013 int ch = chan->channel;
3014
3015 cpc_writeb(scabase + DSR_RX(ch), 0);
3016
3017 /* General RX settings */
3018 cpc_writeb(scabase + M_REG(RRC, ch), 0);
3019 cpc_writeb(scabase + M_REG(RNR, ch), 16);
3020
3021 /* Enable reception */
3022 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_CRC_INIT);
3023 cpc_writeb(scabase + M_REG(CMD, ch), CMD_RX_ENA);
3024
3025 /* Initialize DMA stuff */
3026 chan->rx_first_bd = 0;
3027 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3028 rx_dma_buf_init(card, ch);
3029 cpc_writeb(scabase + DCR_RX(ch), DCR_FCT_CLR);
3030 cpc_writeb(scabase + DMR_RX(ch), (DMR_TMOD | DMR_NF));
3031 cpc_writeb(scabase + DIR_RX(ch), (DIR_EOM | DIR_BOF));
3032
3033 /* Start DMA */
3034 rx_dma_start(card, ch);
3035
3036 return 0;
3037}
3038
7665a089 3039static int tx_config(pc300dev_t * d)
1da177e4
LT		 3040{
3041 pc300ch_t *chan = (pc300ch_t *) d->chan;
3042 pc300_t *card = (pc300_t *) chan->card;
3043 void __iomem *scabase = card->hw.scabase;
3044 int ch = chan->channel;
3045
3046 cpc_writeb(scabase + DSR_TX(ch), 0);
3047
3048 /* General TX settings */
3049 cpc_writeb(scabase + M_REG(TRC0, ch), 0);
3050 cpc_writeb(scabase + M_REG(TFS, ch), 32);
3051 cpc_writeb(scabase + M_REG(TNR0, ch), 20);
3052 cpc_writeb(scabase + M_REG(TNR1, ch), 48);
3053 cpc_writeb(scabase + M_REG(TCR, ch), 8);
3054
3055 /* Enable transmission */
3056 cpc_writeb(scabase + M_REG(CMD, ch), CMD_TX_CRC_INIT);
3057
3058 /* Initialize DMA stuff */
3059 chan->tx_first_bd = 0;
3060 chan->tx_next_bd = 0;
3061 tx_dma_buf_init(card, ch);
3062 cpc_writeb(scabase + DCR_TX(ch), DCR_FCT_CLR);
3063 cpc_writeb(scabase + DMR_TX(ch), (DMR_TMOD | DMR_NF));
3064 cpc_writeb(scabase + DIR_TX(ch), (DIR_EOM | DIR_BOF | DIR_UDRF));
3065 cpc_writel(scabase + DTX_REG(CDAL, ch), TX_BD_ADDR(ch, chan->tx_first_bd));
3066 cpc_writel(scabase + DTX_REG(EDAL, ch), TX_BD_ADDR(ch, chan->tx_next_bd));
3067
3068 return 0;
3069}
3070
3071static int cpc_attach(struct net_device *dev, unsigned short encoding,
3072 unsigned short parity)
3073{
3074 pc300dev_t *d = (pc300dev_t *)dev->priv;
3075 pc300ch_t *chan = (pc300ch_t *)d->chan;
3076 pc300_t *card = (pc300_t *)chan->card;
3077 pc300chconf_t *conf = (pc300chconf_t *)&chan->conf;
3078
3079 if (card->hw.type == PC300_TE) {
3080 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI) {
3081 return -EINVAL;
3082 }
3083 } else {
3084 if (encoding != ENCODING_NRZ && encoding != ENCODING_NRZI &&
3085 encoding != ENCODING_FM_MARK && encoding != ENCODING_FM_SPACE) {
3086 /* Driver doesn't support ENCODING_MANCHESTER yet */
3087 return -EINVAL;
3088 }
3089 }
3090
3091 if (parity != PARITY_NONE && parity != PARITY_CRC16_PR0 &&
3092 parity != PARITY_CRC16_PR1 && parity != PARITY_CRC32_PR1_CCITT &&
3093 parity != PARITY_CRC16_PR1_CCITT) {
3094 return -EINVAL;
3095 }
3096
3097 conf->proto_settings.encoding = encoding;
3098 conf->proto_settings.parity = parity;
3099 return 0;
3100}
3101
7665a089 3102static void cpc_opench(pc300dev_t * d)
1da177e4
LT		 3103{
3104 pc300ch_t *chan = (pc300ch_t *) d->chan;
3105 pc300_t *card = (pc300_t *) chan->card;
3106 int ch = chan->channel;
3107 void __iomem *scabase = card->hw.scabase;
3108
3109 ch_config(d);
3110
3111 rx_config(d);
3112
3113 tx_config(d);
3114
3115 /* Assert RTS and DTR */
3116 cpc_writeb(scabase + M_REG(CTL, ch),
3117 cpc_readb(scabase + M_REG(CTL, ch)) & ~(CTL_RTS | CTL_DTR));
3118}
3119
7665a089 3120static void cpc_closech(pc300dev_t * d)
1da177e4
LT		 3121{
3122 pc300ch_t *chan = (pc300ch_t *) d->chan;
3123 pc300_t *card = (pc300_t *) chan->card;
3124 falc_t *pfalc = (falc_t *) & chan->falc;
3125 int ch = chan->channel;
3126
3127 cpc_writeb(card->hw.scabase + M_REG(CMD, ch), CMD_CH_RST);
3128 rx_dma_stop(card, ch);
3129 tx_dma_stop(card, ch);
3130
3131 if (card->hw.type == PC300_TE) {
3132 memset(pfalc, 0, sizeof(falc_t));
3133 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg2,
3134 cpc_readb(card->hw.falcbase + card->hw.cpld_reg2) &
3135 ~((CPLD_REG2_FALC_TX_CLK | CPLD_REG2_FALC_RX_CLK |
3136 CPLD_REG2_FALC_LED2) << (2 * ch)));
3137 /* Reset the FALC chip */
3138 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3139 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3140 (CPLD_REG1_FALC_RESET << (2 * ch)));
3141 udelay(10000);
3142 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3143 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) &
3144 ~(CPLD_REG1_FALC_RESET << (2 * ch)));
3145 }
3146}
3147
3148int cpc_open(struct net_device *dev)
3149{
3150 hdlc_device *hdlc = dev_to_hdlc(dev);
3151 pc300dev_t *d = (pc300dev_t *) dev->priv;
3152 struct ifreq ifr;
3153 int result;
3154
3155#ifdef PC300_DEBUG_OTHER
3156 printk("pc300: cpc_open");
3157#endif
3158
3159 if (hdlc->proto.id == IF_PROTO_PPP) {
3160 d->if_ptr = &hdlc->state.ppp.pppdev;
3161 }
3162
3163 result = hdlc_open(dev);
3164 if (hdlc->proto.id == IF_PROTO_PPP) {
3165 dev->priv = d;
3166 }
3167 if (result) {
3168 return result;
3169 }
3170
3171 sprintf(ifr.ifr_name, "%s", dev->name);
3172 cpc_opench(d);
3173 netif_start_queue(dev);
3174 return 0;
3175}
3176
7665a089 3177static int cpc_close(struct net_device *dev)
1da177e4
LT		 3178{
3179 hdlc_device *hdlc = dev_to_hdlc(dev);
3180 pc300dev_t *d = (pc300dev_t *) dev->priv;
3181 pc300ch_t *chan = (pc300ch_t *) d->chan;
3182 pc300_t *card = (pc300_t *) chan->card;
3183 unsigned long flags;
3184
3185#ifdef PC300_DEBUG_OTHER
3186 printk("pc300: cpc_close");
3187#endif
3188
3189 netif_stop_queue(dev);
3190
3191 CPC_LOCK(card, flags);
3192 cpc_closech(d);
3193 CPC_UNLOCK(card, flags);
3194
3195 hdlc_close(dev);
3196 if (hdlc->proto.id == IF_PROTO_PPP) {
3197 d->if_ptr = NULL;
3198 }
3199#ifdef CONFIG_PC300_MLPPP
3200 if (chan->conf.proto == PC300_PROTO_MLPPP) {
3201 cpc_tty_unregister_service(d);
3202 chan->conf.proto = 0xffff;
3203 }
3204#endif
3205
3206 return 0;
3207}
3208
3209static uclong detect_ram(pc300_t * card)
3210{
3211 uclong i;
3212 ucchar data;
3213 void __iomem *rambase = card->hw.rambase;
3214
3215 card->hw.ramsize = PC300_RAMSIZE;
3216 /* Let's find out how much RAM is present on this board */
3217 for (i = 0; i < card->hw.ramsize; i++) {
3218 data = (ucchar) (i & 0xff);
3219 cpc_writeb(rambase + i, data);
3220 if (cpc_readb(rambase + i) != data) {
3221 break;
3222 }
3223 }
3224 return (i);
3225}
3226
3227static void plx_init(pc300_t * card)
3228{
3229 struct RUNTIME_9050 __iomem *plx_ctl = card->hw.plxbase;
3230
3231 /* Reset PLX */
3232 cpc_writel(&plx_ctl->init_ctrl,
3233 cpc_readl(&plx_ctl->init_ctrl) | 0x40000000);
3234 udelay(10000L);
3235 cpc_writel(&plx_ctl->init_ctrl,
3236 cpc_readl(&plx_ctl->init_ctrl) & ~0x40000000);
3237
3238 /* Reload Config. Registers from EEPROM */
3239 cpc_writel(&plx_ctl->init_ctrl,
3240 cpc_readl(&plx_ctl->init_ctrl) | 0x20000000);
3241 udelay(10000L);
3242 cpc_writel(&plx_ctl->init_ctrl,
3243 cpc_readl(&plx_ctl->init_ctrl) & ~0x20000000);
3244
3245}
3246
3247static inline void show_version(void)
3248{
3249 char *rcsvers, *rcsdate, *tmp;
3250
3251 rcsvers = strchr(rcsid, ' ');
3252 rcsvers++;
3253 tmp = strchr(rcsvers, ' ');
3254 *tmp++ = '\0';
3255 rcsdate = strchr(tmp, ' ');
3256 rcsdate++;
3257 tmp = strrchr(rcsdate, ' ');
3258 *tmp = '\0';
3259 printk(KERN_INFO "Cyclades-PC300 driver %s %s (built %s %s)\n",
3260 rcsvers, rcsdate, __DATE__, __TIME__);
3261} /* show_version */
3262
3263static void cpc_init_card(pc300_t * card)
3264{
3265 int i, devcount = 0;
3266 static int board_nbr = 1;
3267
3268 /* Enable interrupts on the PCI bridge */
3269 plx_init(card);
3270 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3271 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) | 0x0040);
3272
3273#ifdef USE_PCI_CLOCK
3274 /* Set board clock to PCI clock */
3275 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3276 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) | 0x00000004UL);
3277 card->hw.clock = PC300_PCI_CLOCK;
3278#else
3279 /* Set board clock to internal oscillator clock */
3280 cpc_writel(card->hw.plxbase + card->hw.gpioc_reg,
3281 cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & ~0x00000004UL);
3282 card->hw.clock = PC300_OSC_CLOCK;
3283#endif
3284
3285 /* Detect actual on-board RAM size */
3286 card->hw.ramsize = detect_ram(card);
3287
3288 /* Set Global SCA-II registers */
3289 cpc_writeb(card->hw.scabase + PCR, PCR_PR2);
3290 cpc_writeb(card->hw.scabase + BTCR, 0x10);
3291 cpc_writeb(card->hw.scabase + WCRL, 0);
3292 cpc_writeb(card->hw.scabase + DMER, 0x80);
3293
3294 if (card->hw.type == PC300_TE) {
3295 ucchar reg1;
3296
3297 /* Check CPLD version */
3298 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3299 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3300 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3301 /* New CPLD */
3302 card->hw.cpld_id = cpc_readb(card->hw.falcbase + CPLD_ID_REG);
3303 card->hw.cpld_reg1 = CPLD_V2_REG1;
3304 card->hw.cpld_reg2 = CPLD_V2_REG2;
3305 } else {
3306 /* old CPLD */
3307 card->hw.cpld_id = 0;
3308 card->hw.cpld_reg1 = CPLD_REG1;
3309 card->hw.cpld_reg2 = CPLD_REG2;
3310 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
3311 }
3312
3313 /* Enable the board's global clock */
3314 cpc_writeb(card->hw.falcbase + card->hw.cpld_reg1,
3315 cpc_readb(card->hw.falcbase + card->hw.cpld_reg1) |
3316 CPLD_REG1_GLOBAL_CLK);
3317
3318 }
3319
3320 for (i = 0; i < card->hw.nchan; i++) {
3321 pc300ch_t *chan = &card->chan[i];
3322 pc300dev_t *d = &chan->d;
3323 hdlc_device *hdlc;
3324 struct net_device *dev;
3325
3326 chan->card = card;
3327 chan->channel = i;
3328 chan->conf.phys_settings.clock_rate = 0;
3329 chan->conf.phys_settings.clock_type = CLOCK_EXT;
3330 chan->conf.proto_settings.encoding = ENCODING_NRZ;
3331 chan->conf.proto_settings.parity = PARITY_CRC16_PR1_CCITT;
3332 switch (card->hw.type) {
3333 case PC300_TE:
3334 chan->conf.media = IF_IFACE_T1;
3335 chan->conf.lcode = PC300_LC_B8ZS;
3336 chan->conf.fr_mode = PC300_FR_ESF;
3337 chan->conf.lbo = PC300_LBO_0_DB;
3338 chan->conf.rx_sens = PC300_RX_SENS_SH;
3339 chan->conf.tslot_bitmap = 0xffffffffUL;
3340 break;
3341
3342 case PC300_X21:
3343 chan->conf.media = IF_IFACE_X21;
3344 break;
3345
3346 case PC300_RSV:
3347 default:
3348 chan->conf.media = IF_IFACE_V35;
3349 break;
3350 }
3351 chan->conf.proto = IF_PROTO_PPP;
3352 chan->tx_first_bd = 0;
3353 chan->tx_next_bd = 0;
3354 chan->rx_first_bd = 0;
3355 chan->rx_last_bd = N_DMA_RX_BUF - 1;
3356 chan->nfree_tx_bd = N_DMA_TX_BUF;
3357
3358 d->chan = chan;
3359 d->tx_skb = NULL;
3360 d->trace_on = 0;
3361 d->line_on = 0;
3362 d->line_off = 0;
3363
3364 dev = alloc_hdlcdev(NULL);
3365 if (dev == NULL)
3366 continue;
3367
3368 hdlc = dev_to_hdlc(dev);
3369 hdlc->xmit = cpc_queue_xmit;
3370 hdlc->attach = cpc_attach;
3371 d->dev = dev;
3372 dev->mem_start = card->hw.ramphys;
3373 dev->mem_end = card->hw.ramphys + card->hw.ramsize - 1;
3374 dev->irq = card->hw.irq;
3375 dev->init = NULL;
3376 dev->tx_queue_len = PC300_TX_QUEUE_LEN;
3377 dev->mtu = PC300_DEF_MTU;
3378
3379 dev->open = cpc_open;
3380 dev->stop = cpc_close;
3381 dev->tx_timeout = cpc_tx_timeout;
3382 dev->watchdog_timeo = PC300_TX_TIMEOUT;
3383 dev->get_stats = cpc_get_stats;
3384 dev->set_multicast_list = NULL;
3385 dev->set_mac_address = NULL;
3386 dev->change_mtu = cpc_change_mtu;
3387 dev->do_ioctl = cpc_ioctl;
3388
3389 if (register_hdlc_device(dev) == 0) {
3390 dev->priv = d; /* We need 'priv', hdlc doesn't */
3391 printk("%s: Cyclades-PC300/", dev->name);
3392 switch (card->hw.type) {
3393 case PC300_TE:
3394 if (card->hw.bus == PC300_PMC) {
3395 printk("TE-M");
3396 } else {
3397 printk("TE ");
3398 }
3399 break;
3400
3401 case PC300_X21:
3402 printk("X21 ");
3403 break;
3404
3405 case PC300_RSV:
3406 default:
3407 printk("RSV ");
3408 break;
3409 }
3410 printk (" #%d, %dKB of RAM at 0x%08x, IRQ%d, channel %d.\n",
3411 board_nbr, card->hw.ramsize / 1024,
3412 card->hw.ramphys, card->hw.irq, i + 1);
3413 devcount++;
3414 } else {
3415 printk ("Dev%d on card(0x%08x): unable to allocate i/f name.\n",
3416 i + 1, card->hw.ramphys);
3417 free_netdev(dev);
3418 continue;
3419 }
3420 }
3421 spin_lock_init(&card->card_lock);
3422
3423 board_nbr++;
3424}
3425
3426static int __devinit
3427cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3428{
3429 static int first_time = 1;
3430 ucchar cpc_rev_id;
e8108c98 3431 int err, eeprom_outdated = 0;
1da177e4
LT		 3432 ucshort device_id;
3433 pc300_t *card;
3434
3435 if (first_time) {
3436 first_time = 0;
3437 show_version();
3438#ifdef CONFIG_PC300_MLPPP
3439 cpc_tty_reset_var();
3440#endif
3441 }
3442
e8108c98
MT		 3443 if ((err = pci_enable_device(pdev)) < 0)
3444 return err;
3445
1da177e4
LT		 3446 card = (pc300_t *) kmalloc(sizeof(pc300_t), GFP_KERNEL);
3447 if (card == NULL) {
7c7459d1 3448 printk("PC300 found at RAM 0x%016llx, "
1da177e4 3449 "but could not allocate card structure.\n",
7c7459d1 3450 (unsigned long long)pci_resource_start(pdev, 3));
e8108c98
MT		 3451 err = -ENOMEM;
3452 goto err_disable_dev;
1da177e4
LT		 3453 }
3454 memset(card, 0, sizeof(pc300_t));
3455
e8108c98
MT		 3456 err = -ENODEV;
3457
1da177e4
LT		 3458 /* read PCI configuration area */
3459 device_id = ent->device;
3460 card->hw.irq = pdev->irq;
3461 card->hw.iophys = pci_resource_start(pdev, 1);
3462 card->hw.iosize = pci_resource_len(pdev, 1);
3463 card->hw.scaphys = pci_resource_start(pdev, 2);
3464 card->hw.scasize = pci_resource_len(pdev, 2);
3465 card->hw.ramphys = pci_resource_start(pdev, 3);
3466 card->hw.alloc_ramsize = pci_resource_len(pdev, 3);
3467 card->hw.falcphys = pci_resource_start(pdev, 4);
3468 card->hw.falcsize = pci_resource_len(pdev, 4);
3469 card->hw.plxphys = pci_resource_start(pdev, 5);
3470 card->hw.plxsize = pci_resource_len(pdev, 5);
3471 pci_read_config_byte(pdev, PCI_REVISION_ID, &cpc_rev_id);
3472
3473 switch (device_id) {
3474 case PCI_DEVICE_ID_PC300_RX_1:
3475 case PCI_DEVICE_ID_PC300_TE_1:
3476 case PCI_DEVICE_ID_PC300_TE_M_1:
3477 card->hw.nchan = 1;
3478 break;
3479
3480 case PCI_DEVICE_ID_PC300_RX_2:
3481 case PCI_DEVICE_ID_PC300_TE_2:
3482 case PCI_DEVICE_ID_PC300_TE_M_2:
3483 default:
3484 card->hw.nchan = PC300_MAXCHAN;
3485 break;
3486 }
3487#ifdef PC300_DEBUG_PCI
3488 printk("cpc (bus=0x0%x,pci_id=0x%x,", pdev->bus->number, pdev->devfn);
3489 printk("rev_id=%d) IRQ%d\n", cpc_rev_id, card->hw.irq);
3490 printk("cpc:found ramaddr=0x%08lx plxaddr=0x%08lx "
3491 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3492 card->hw.ramphys, card->hw.plxphys, card->hw.scaphys,
3493 card->hw.falcphys);
3494#endif
3495 /* Although we don't use this I/O region, we should
3496 * request it from the kernel anyway, to avoid problems
3497 * with other drivers accessing it. */
3498 if (!request_region(card->hw.iophys, card->hw.iosize, "PLX Registers")) {
3499 /* In case we can't allocate it, warn user */
3500 printk("WARNING: couldn't allocate I/O region for PC300 board "
3501 "at 0x%08x!\n", card->hw.ramphys);
3502 }
3503
3504 if (card->hw.plxphys) {
3505 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, card->hw.plxphys);
3506 } else {
3507 eeprom_outdated = 1;
3508 card->hw.plxphys = pci_resource_start(pdev, 0);
3509 card->hw.plxsize = pci_resource_len(pdev, 0);
3510 }
3511
3512 if (!request_mem_region(card->hw.plxphys, card->hw.plxsize,
3513 "PLX Registers")) {
3514 printk("PC300 found at RAM 0x%08x, "
3515 "but could not allocate PLX mem region.\n",
3516 card->hw.ramphys);
1da177e4
LT		 3517 goto err_release_io;
3518 }
3519 if (!request_mem_region(card->hw.ramphys, card->hw.alloc_ramsize,
3520 "On-board RAM")) {
3521 printk("PC300 found at RAM 0x%08x, "
3522 "but could not allocate RAM mem region.\n",
3523 card->hw.ramphys);
1da177e4
LT		 3524 goto err_release_plx;
3525 }
3526 if (!request_mem_region(card->hw.scaphys, card->hw.scasize,
3527 "SCA-II Registers")) {
3528 printk("PC300 found at RAM 0x%08x, "
3529 "but could not allocate SCA mem region.\n",
3530 card->hw.ramphys);
1da177e4
LT		 3531 goto err_release_ram;
3532 }
3533
1da177e4
LT		 3534 card->hw.plxbase = ioremap(card->hw.plxphys, card->hw.plxsize);
3535 card->hw.rambase = ioremap(card->hw.ramphys, card->hw.alloc_ramsize);
3536 card->hw.scabase = ioremap(card->hw.scaphys, card->hw.scasize);
3537 switch (device_id) {
3538 case PCI_DEVICE_ID_PC300_TE_1:
3539 case PCI_DEVICE_ID_PC300_TE_2:
3540 case PCI_DEVICE_ID_PC300_TE_M_1:
3541 case PCI_DEVICE_ID_PC300_TE_M_2:
3542 request_mem_region(card->hw.falcphys, card->hw.falcsize,
3543 "FALC Registers");
3544 card->hw.falcbase = ioremap(card->hw.falcphys, card->hw.falcsize);
3545 break;
3546
3547 case PCI_DEVICE_ID_PC300_RX_1:
3548 case PCI_DEVICE_ID_PC300_RX_2:
3549 default:
3550 card->hw.falcbase = NULL;
3551 break;
3552 }
3553
3554#ifdef PC300_DEBUG_PCI
3555 printk("cpc: relocate ramaddr=0x%08lx plxaddr=0x%08lx "
3556 "ctladdr=0x%08lx falcaddr=0x%08lx\n",
3557 card->hw.rambase, card->hw.plxbase, card->hw.scabase,
3558 card->hw.falcbase);
3559#endif
3560
3561 /* Set PCI drv pointer to the card structure */
3562 pci_set_drvdata(pdev, card);
3563
3564 /* Set board type */
3565 switch (device_id) {
3566 case PCI_DEVICE_ID_PC300_TE_1:
3567 case PCI_DEVICE_ID_PC300_TE_2:
3568 case PCI_DEVICE_ID_PC300_TE_M_1:
3569 case PCI_DEVICE_ID_PC300_TE_M_2:
3570 card->hw.type = PC300_TE;
3571
3572 if ((device_id == PCI_DEVICE_ID_PC300_TE_M_1) ||
3573 (device_id == PCI_DEVICE_ID_PC300_TE_M_2)) {
3574 card->hw.bus = PC300_PMC;
3575 /* Set PLX register offsets */
3576 card->hw.gpioc_reg = 0x54;
3577 card->hw.intctl_reg = 0x4c;
3578 } else {
3579 card->hw.bus = PC300_PCI;
3580 /* Set PLX register offsets */
3581 card->hw.gpioc_reg = 0x50;
3582 card->hw.intctl_reg = 0x4c;
3583 }
3584 break;
3585
3586 case PCI_DEVICE_ID_PC300_RX_1:
3587 case PCI_DEVICE_ID_PC300_RX_2:
3588 default:
3589 card->hw.bus = PC300_PCI;
3590 /* Set PLX register offsets */
3591 card->hw.gpioc_reg = 0x50;
3592 card->hw.intctl_reg = 0x4c;
3593
3594 if ((cpc_readl(card->hw.plxbase + card->hw.gpioc_reg) & PC300_CTYPE_MASK)) {
3595 card->hw.type = PC300_X21;
3596 } else {
3597 card->hw.type = PC300_RSV;
3598 }
3599 break;
3600 }
3601
3602 /* Allocate IRQ */
1fb9df5d 3603 if (request_irq(card->hw.irq, cpc_intr, IRQF_SHARED, "Cyclades-PC300", card)) {
1da177e4
LT		 3604 printk ("PC300 found at RAM 0x%08x, but could not allocate IRQ%d.\n",
3605 card->hw.ramphys, card->hw.irq);
3606 goto err_io_unmap;
3607 }
3608
3609 cpc_init_card(card);
3610
3611 if (eeprom_outdated)
3612 printk("WARNING: PC300 with outdated EEPROM.\n");
3613 return 0;
3614
3615err_io_unmap:
3616 iounmap(card->hw.plxbase);
3617 iounmap(card->hw.scabase);
3618 iounmap(card->hw.rambase);
3619 if (card->hw.type == PC300_TE) {
3620 iounmap(card->hw.falcbase);
3621 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3622 }
1da177e4
LT		 3623 release_mem_region(card->hw.scaphys, card->hw.scasize);
3624err_release_ram:
3625 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3626err_release_plx:
3627 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3628err_release_io:
3629 release_region(card->hw.iophys, card->hw.iosize);
3630 kfree(card);
e8108c98
MT		 3631err_disable_dev:
3632 pci_disable_device(pdev);
3633 return err;
1da177e4
LT		 3634}
3635
3636static void __devexit cpc_remove_one(struct pci_dev *pdev)
3637{
3638 pc300_t *card = pci_get_drvdata(pdev);
3639
3640 if (card->hw.rambase != 0) {
3641 int i;
3642
3643 /* Disable interrupts on the PCI bridge */
3644 cpc_writew(card->hw.plxbase + card->hw.intctl_reg,
3645 cpc_readw(card->hw.plxbase + card->hw.intctl_reg) & ~(0x0040));
3646
3647 for (i = 0; i < card->hw.nchan; i++) {
3648 unregister_hdlc_device(card->chan[i].d.dev);
3649 }
3650 iounmap(card->hw.plxbase);
3651 iounmap(card->hw.scabase);
3652 iounmap(card->hw.rambase);
3653 release_mem_region(card->hw.plxphys, card->hw.plxsize);
3654 release_mem_region(card->hw.ramphys, card->hw.alloc_ramsize);
3655 release_mem_region(card->hw.scaphys, card->hw.scasize);
3656 release_region(card->hw.iophys, card->hw.iosize);
3657 if (card->hw.type == PC300_TE) {
3658 iounmap(card->hw.falcbase);
3659 release_mem_region(card->hw.falcphys, card->hw.falcsize);
3660 }
3661 for (i = 0; i < card->hw.nchan; i++)
3662 if (card->chan[i].d.dev)
3663 free_netdev(card->chan[i].d.dev);
3664 if (card->hw.irq)
3665 free_irq(card->hw.irq, card);
3666 kfree(card);
e8108c98 3667 pci_disable_device(pdev);
1da177e4
LT		 3668 }
3669}
3670
3671static struct pci_driver cpc_driver = {
3672 .name = "pc300",
3673 .id_table = cpc_pci_dev_id,
3674 .probe = cpc_init_one,
3675 .remove = __devexit_p(cpc_remove_one),
3676};
3677
3678static int __init cpc_init(void)
3679{
29917620 3680 return pci_register_driver(&cpc_driver);
1da177e4
LT		 3681}
3682
3683static void __exit cpc_cleanup_module(void)
3684{
3685 pci_unregister_driver(&cpc_driver);
3686}
3687
3688module_init(cpc_init);
3689module_exit(cpc_cleanup_module);
3690
3691MODULE_DESCRIPTION("Cyclades-PC300 cards driver");
3692MODULE_AUTHOR( "Author: Ivan Passos <ivan@cyclades.com>\r\n"
3693 "Maintainer: PC300 Maintainer <pc300@cyclades.com");
3694MODULE_LICENSE("GPL");
3695
Clone of davem's net-next-2.6 tree