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drivers/net/: use DEFINE_PCI_DEVICE_TABLE()
[net-next-2.6.git] / drivers / net / tulip / winbond-840.c
CommitLineData
1da177e4
LT		 1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
f3b197ac 41
1da177e4
LT		 42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
f3b197ac 46
1da177e4 47#define DRV_NAME "winbond-840"
d5b20697
AG		 48#define DRV_VERSION "1.01-e"
49#define DRV_RELDATE "Sep-11-2006"
1da177e4
LT		 50
51
52/* Automatically extracted configuration info:
53probe-func: winbond840_probe
54config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
55
56c-help-name: Winbond W89c840 PCI Ethernet support
57c-help-symbol: CONFIG_WINBOND_840
58c-help: This driver is for the Winbond W89c840 chip. It also works with
59c-help: the TX9882 chip on the Compex RL100-ATX board.
f3b197ac 60c-help: More specific information and updates are available from
1da177e4
LT		 61c-help: http://www.scyld.com/network/drivers.html
62*/
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
68static int max_interrupt_work = 20;
69/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The '840 uses a 64 element hash table based on the Ethernet CRC. */
71static int multicast_filter_limit = 32;
72
73/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
74 Setting to > 1518 effectively disables this feature. */
75static int rx_copybreak;
76
77/* Used to pass the media type, etc.
78 Both 'options[]' and 'full_duplex[]' should exist for driver
79 interoperability.
80 The media type is usually passed in 'options[]'.
81*/
82#define MAX_UNITS 8 /* More are supported, limit only on options */
83static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
85
86/* Operational parameters that are set at compile time. */
87
88/* Keep the ring sizes a power of two for compile efficiency.
89 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */
1da177e4
LT		 93#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
94#define TX_QUEUE_LEN_RESTART 5
1da177e4
LT		 95
96#define TX_BUFLIMIT (1024-128)
97
98/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
99 To avoid overflowing we don't queue again until we have room for a
100 full-size packet.
101 */
102#define TX_FIFO_SIZE (2048)
103#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
104
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
1da177e4
LT		 110/* Include files, designed to support most kernel versions 2.0.0 and later. */
111#include <linux/module.h>
112#include <linux/kernel.h>
113#include <linux/string.h>
114#include <linux/timer.h>
115#include <linux/errno.h>
116#include <linux/ioport.h>
117#include <linux/slab.h>
118#include <linux/interrupt.h>
119#include <linux/pci.h>
10a87fcf 120#include <linux/dma-mapping.h>
1da177e4
LT		 121#include <linux/netdevice.h>
122#include <linux/etherdevice.h>
123#include <linux/skbuff.h>
124#include <linux/init.h>
125#include <linux/delay.h>
126#include <linux/ethtool.h>
127#include <linux/mii.h>
128#include <linux/rtnetlink.h>
129#include <linux/crc32.h>
130#include <linux/bitops.h>
131#include <asm/uaccess.h>
132#include <asm/processor.h> /* Processor type for cache alignment. */
133#include <asm/io.h>
134#include <asm/irq.h>
135
42eab567
GG		 136#include "tulip.h"
137
48dd59e3
JG		 138#undef PKT_BUF_SZ /* tulip.h also defines this */
139#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
140
1da177e4 141/* These identify the driver base version and may not be removed. */
03f54b3d
SH		 142static const char version[] __initconst =
143 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) "
144 DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
ad361c98 145 " http://www.scyld.com/network/drivers.html\n";
1da177e4
LT		 146
147MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
148MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
152module_param(max_interrupt_work, int, 0);
153module_param(debug, int, 0);
154module_param(rx_copybreak, int, 0);
155module_param(multicast_filter_limit, int, 0);
156module_param_array(options, int, NULL, 0);
157module_param_array(full_duplex, int, NULL, 0);
158MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
159MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
160MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
161MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
162MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
163MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
164
165/*
166 Theory of Operation
167
168I. Board Compatibility
169
170This driver is for the Winbond w89c840 chip.
171
172II. Board-specific settings
173
174None.
175
176III. Driver operation
177
178This chip is very similar to the Digital 21*4* "Tulip" family. The first
179twelve registers and the descriptor format are nearly identical. Read a
180Tulip manual for operational details.
181
182A significant difference is that the multicast filter and station address are
183stored in registers rather than loaded through a pseudo-transmit packet.
184
185Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
186full-sized packet we must use both data buffers in a descriptor. Thus the
187driver uses ring mode where descriptors are implicitly sequential in memory,
188rather than using the second descriptor address as a chain pointer to
189subsequent descriptors.
190
191IV. Notes
192
193If you are going to almost clone a Tulip, why not go all the way and avoid
194the need for a new driver?
195
196IVb. References
197
198http://www.scyld.com/expert/100mbps.html
199http://www.scyld.com/expert/NWay.html
200http://www.winbond.com.tw/
201
202IVc. Errata
203
204A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
205correctly detect a full FIFO, and queuing more than 2048 bytes may result in
206silent data corruption.
207
208Test with 'ping -s 10000' on a fast computer.
209
210*/
211
f3b197ac 212
1da177e4
LT		 213
214/*
215 PCI probe table.
216*/
1da177e4 217enum chip_capability_flags {
1f1bd5fc
JG		 218 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
219};
220
a3aa1884 221static DEFINE_PCI_DEVICE_TABLE(w840_pci_tbl) = {
1da177e4
LT		 222 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
223 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
224 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
1f1bd5fc 225 { }
1da177e4
LT		 226};
227MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
228
c3d8e682
JG		 229enum {
230 netdev_res_size = 128, /* size of PCI BAR resource */
231};
232
1da177e4
LT		 233struct pci_id_info {
234 const char *name;
c3d8e682 235 int drv_flags; /* Driver use, intended as capability flags. */
1da177e4 236};
c3d8e682
JG		 237
238static const struct pci_id_info pci_id_tbl[] __devinitdata = {
239 { /* Sometime a Level-One switch card. */
240 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
241 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
242 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
243 { } /* terminate list. */
1da177e4
LT		 244};
245
246/* This driver was written to use PCI memory space, however some x86 systems
42eab567
GG		 247 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
248*/
1da177e4
LT		 249
250/* Offsets to the Command and Status Registers, "CSRs".
251 While similar to the Tulip, these registers are longword aligned.
252 Note: It's not useful to define symbolic names for every register bit in
253 the device. The name can only partially document the semantics and make
254 the driver longer and more difficult to read.
255*/
256enum w840_offsets {
257 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
258 RxRingPtr=0x0C, TxRingPtr=0x10,
259 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
260 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
261 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
262 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
263 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
264};
265
1da177e4
LT		 266/* Bits in the NetworkConfig register. */
267enum rx_mode_bits {
42eab567
GG		 268 AcceptErr=0x80,
269 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
270 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
1da177e4
LT		 271};
272
273enum mii_reg_bits {
274 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
275 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
276};
277
278/* The Tulip Rx and Tx buffer descriptors. */
279struct w840_rx_desc {
280 s32 status;
281 s32 length;
282 u32 buffer1;
283 u32 buffer2;
284};
285
286struct w840_tx_desc {
287 s32 status;
288 s32 length;
289 u32 buffer1, buffer2;
290};
291
1da177e4
LT		 292#define MII_CNT 1 /* winbond only supports one MII */
293struct netdev_private {
294 struct w840_rx_desc *rx_ring;
295 dma_addr_t rx_addr[RX_RING_SIZE];
296 struct w840_tx_desc *tx_ring;
297 dma_addr_t tx_addr[TX_RING_SIZE];
298 dma_addr_t ring_dma_addr;
299 /* The addresses of receive-in-place skbuffs. */
300 struct sk_buff* rx_skbuff[RX_RING_SIZE];
301 /* The saved address of a sent-in-place packet/buffer, for later free(). */
302 struct sk_buff* tx_skbuff[TX_RING_SIZE];
303 struct net_device_stats stats;
304 struct timer_list timer; /* Media monitoring timer. */
305 /* Frequently used values: keep some adjacent for cache effect. */
306 spinlock_t lock;
307 int chip_id, drv_flags;
308 struct pci_dev *pci_dev;
309 int csr6;
310 struct w840_rx_desc *rx_head_desc;
311 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
312 unsigned int rx_buf_sz; /* Based on MTU+slack. */
313 unsigned int cur_tx, dirty_tx;
314 unsigned int tx_q_bytes;
315 unsigned int tx_full; /* The Tx queue is full. */
316 /* MII transceiver section. */
317 int mii_cnt; /* MII device addresses. */
318 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
319 u32 mii;
320 struct mii_if_info mii_if;
321 void __iomem *base_addr;
322};
323
324static int eeprom_read(void __iomem *ioaddr, int location);
325static int mdio_read(struct net_device *dev, int phy_id, int location);
326static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
327static int netdev_open(struct net_device *dev);
328static int update_link(struct net_device *dev);
329static void netdev_timer(unsigned long data);
330static void init_rxtx_rings(struct net_device *dev);
331static void free_rxtx_rings(struct netdev_private *np);
332static void init_registers(struct net_device *dev);
333static void tx_timeout(struct net_device *dev);
334static int alloc_ringdesc(struct net_device *dev);
335static void free_ringdesc(struct netdev_private *np);
ad096463 336static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 337static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 338static void netdev_error(struct net_device *dev, int intr_status);
339static int netdev_rx(struct net_device *dev);
340static u32 __set_rx_mode(struct net_device *dev);
341static void set_rx_mode(struct net_device *dev);
342static struct net_device_stats *get_stats(struct net_device *dev);
343static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 344static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 345static int netdev_close(struct net_device *dev);
346
2a97e6b7
SH		 347static const struct net_device_ops netdev_ops = {
348 .ndo_open = netdev_open,
349 .ndo_stop = netdev_close,
350 .ndo_start_xmit = start_tx,
351 .ndo_get_stats = get_stats,
352 .ndo_set_multicast_list = set_rx_mode,
353 .ndo_do_ioctl = netdev_ioctl,
354 .ndo_tx_timeout = tx_timeout,
355 .ndo_change_mtu = eth_change_mtu,
356 .ndo_set_mac_address = eth_mac_addr,
357 .ndo_validate_addr = eth_validate_addr,
358};
1da177e4
LT		 359
360static int __devinit w840_probe1 (struct pci_dev *pdev,
361 const struct pci_device_id *ent)
362{
363 struct net_device *dev;
364 struct netdev_private *np;
365 static int find_cnt;
366 int chip_idx = ent->driver_data;
367 int irq;
368 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
369 void __iomem *ioaddr;
1da177e4
LT		 370
371 i = pci_enable_device(pdev);
372 if (i) return i;
373
374 pci_set_master(pdev);
375
376 irq = pdev->irq;
377
284901a9 378 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1da177e4
LT		 379 printk(KERN_WARNING "Winbond-840: Device %s disabled due to DMA limitations.\n",
380 pci_name(pdev));
381 return -EIO;
382 }
383 dev = alloc_etherdev(sizeof(*np));
384 if (!dev)
385 return -ENOMEM;
1da177e4
LT		 386 SET_NETDEV_DEV(dev, &pdev->dev);
387
388 if (pci_request_regions(pdev, DRV_NAME))
389 goto err_out_netdev;
42eab567
GG		 390
391 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
1da177e4
LT		 392 if (!ioaddr)
393 goto err_out_free_res;
394
395 for (i = 0; i < 3; i++)
c559a5bc 396 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
1da177e4
LT		 397
398 /* Reset the chip to erase previous misconfiguration.
399 No hold time required! */
400 iowrite32(0x00000001, ioaddr + PCIBusCfg);
401
402 dev->base_addr = (unsigned long)ioaddr;
403 dev->irq = irq;
404
405 np = netdev_priv(dev);
406 np->pci_dev = pdev;
407 np->chip_id = chip_idx;
408 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
409 spin_lock_init(&np->lock);
410 np->mii_if.dev = dev;
411 np->mii_if.mdio_read = mdio_read;
412 np->mii_if.mdio_write = mdio_write;
413 np->base_addr = ioaddr;
f3b197ac 414
1da177e4
LT		 415 pci_set_drvdata(pdev, dev);
416
417 if (dev->mem_start)
418 option = dev->mem_start;
419
420 /* The lower four bits are the media type. */
421 if (option > 0) {
422 if (option & 0x200)
423 np->mii_if.full_duplex = 1;
424 if (option & 15)
425 printk(KERN_INFO "%s: ignoring user supplied media type %d",
426 dev->name, option & 15);
427 }
428 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
429 np->mii_if.full_duplex = 1;
430
431 if (np->mii_if.full_duplex)
432 np->mii_if.force_media = 1;
433
434 /* The chip-specific entries in the device structure. */
2a97e6b7 435 dev->netdev_ops = &netdev_ops;
1da177e4 436 dev->ethtool_ops = &netdev_ethtool_ops;
1da177e4
LT		 437 dev->watchdog_timeo = TX_TIMEOUT;
438
439 i = register_netdev(dev);
440 if (i)
441 goto err_out_cleardev;
442
e174961c 443 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
0795af57 444 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
e174961c 445 dev->dev_addr, irq);
1da177e4
LT		 446
447 if (np->drv_flags & CanHaveMII) {
448 int phy, phy_idx = 0;
449 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
450 int mii_status = mdio_read(dev, phy, MII_BMSR);
451 if (mii_status != 0xffff && mii_status != 0x0000) {
452 np->phys[phy_idx++] = phy;
453 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
454 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
455 mdio_read(dev, phy, MII_PHYSID2);
456 printk(KERN_INFO "%s: MII PHY %8.8xh found at address %d, status "
457 "0x%4.4x advertising %4.4x.\n",
458 dev->name, np->mii, phy, mii_status, np->mii_if.advertising);
459 }
460 }
461 np->mii_cnt = phy_idx;
462 np->mii_if.phy_id = np->phys[0];
463 if (phy_idx == 0) {
464 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
465 "not operate correctly.\n", dev->name);
466 }
467 }
468
469 find_cnt++;
470 return 0;
471
472err_out_cleardev:
473 pci_set_drvdata(pdev, NULL);
474 pci_iounmap(pdev, ioaddr);
475err_out_free_res:
476 pci_release_regions(pdev);
477err_out_netdev:
478 free_netdev (dev);
479 return -ENODEV;
480}
481
f3b197ac 482
1da177e4
LT		 483/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
484 often serial bit streams generated by the host processor.
485 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
486
487/* Delay between EEPROM clock transitions.
488 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
489 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
490 made udelay() unreliable.
491 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 492 deprecated.
1da177e4
LT		 493*/
494#define eeprom_delay(ee_addr) ioread32(ee_addr)
495
496enum EEPROM_Ctrl_Bits {
497 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
498 EE_ChipSelect=0x801, EE_DataIn=0x08,
499};
500
501/* The EEPROM commands include the alway-set leading bit. */
502enum EEPROM_Cmds {
503 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
504};
505
506static int eeprom_read(void __iomem *addr, int location)
507{
508 int i;
509 int retval = 0;
510 void __iomem *ee_addr = addr + EECtrl;
511 int read_cmd = location | EE_ReadCmd;
512 iowrite32(EE_ChipSelect, ee_addr);
513
514 /* Shift the read command bits out. */
515 for (i = 10; i >= 0; i--) {
516 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
517 iowrite32(dataval, ee_addr);
518 eeprom_delay(ee_addr);
519 iowrite32(dataval | EE_ShiftClk, ee_addr);
520 eeprom_delay(ee_addr);
521 }
522 iowrite32(EE_ChipSelect, ee_addr);
523 eeprom_delay(ee_addr);
524
525 for (i = 16; i > 0; i--) {
526 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
527 eeprom_delay(ee_addr);
528 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
529 iowrite32(EE_ChipSelect, ee_addr);
530 eeprom_delay(ee_addr);
531 }
532
533 /* Terminate the EEPROM access. */
534 iowrite32(0, ee_addr);
535 return retval;
536}
537
538/* MII transceiver control section.
539 Read and write the MII registers using software-generated serial
540 MDIO protocol. See the MII specifications or DP83840A data sheet
541 for details.
542
543 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
544 met by back-to-back 33Mhz PCI cycles. */
545#define mdio_delay(mdio_addr) ioread32(mdio_addr)
546
547/* Set iff a MII transceiver on any interface requires mdio preamble.
548 This only set with older transceivers, so the extra
549 code size of a per-interface flag is not worthwhile. */
550static char mii_preamble_required = 1;
551
552#define MDIO_WRITE0 (MDIO_EnbOutput)
553#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
554
555/* Generate the preamble required for initial synchronization and
556 a few older transceivers. */
557static void mdio_sync(void __iomem *mdio_addr)
558{
559 int bits = 32;
560
561 /* Establish sync by sending at least 32 logic ones. */
562 while (--bits >= 0) {
563 iowrite32(MDIO_WRITE1, mdio_addr);
564 mdio_delay(mdio_addr);
565 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
566 mdio_delay(mdio_addr);
567 }
568}
569
570static int mdio_read(struct net_device *dev, int phy_id, int location)
571{
572 struct netdev_private *np = netdev_priv(dev);
573 void __iomem *mdio_addr = np->base_addr + MIICtrl;
574 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
575 int i, retval = 0;
576
577 if (mii_preamble_required)
578 mdio_sync(mdio_addr);
579
580 /* Shift the read command bits out. */
581 for (i = 15; i >= 0; i--) {
582 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
583
584 iowrite32(dataval, mdio_addr);
585 mdio_delay(mdio_addr);
586 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
587 mdio_delay(mdio_addr);
588 }
589 /* Read the two transition, 16 data, and wire-idle bits. */
590 for (i = 20; i > 0; i--) {
591 iowrite32(MDIO_EnbIn, mdio_addr);
592 mdio_delay(mdio_addr);
593 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
594 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
595 mdio_delay(mdio_addr);
596 }
597 return (retval>>1) & 0xffff;
598}
599
600static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
601{
602 struct netdev_private *np = netdev_priv(dev);
603 void __iomem *mdio_addr = np->base_addr + MIICtrl;
604 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
605 int i;
606
607 if (location == 4 && phy_id == np->phys[0])
608 np->mii_if.advertising = value;
609
610 if (mii_preamble_required)
611 mdio_sync(mdio_addr);
612
613 /* Shift the command bits out. */
614 for (i = 31; i >= 0; i--) {
615 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
616
617 iowrite32(dataval, mdio_addr);
618 mdio_delay(mdio_addr);
619 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
620 mdio_delay(mdio_addr);
621 }
622 /* Clear out extra bits. */
623 for (i = 2; i > 0; i--) {
624 iowrite32(MDIO_EnbIn, mdio_addr);
625 mdio_delay(mdio_addr);
626 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
627 mdio_delay(mdio_addr);
628 }
629 return;
630}
631
f3b197ac 632
1da177e4
LT		 633static int netdev_open(struct net_device *dev)
634{
635 struct netdev_private *np = netdev_priv(dev);
636 void __iomem *ioaddr = np->base_addr;
637 int i;
638
639 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
640
641 netif_device_detach(dev);
a0607fd3 642 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 643 if (i)
644 goto out_err;
645
646 if (debug > 1)
647 printk(KERN_DEBUG "%s: w89c840_open() irq %d.\n",
648 dev->name, dev->irq);
649
650 if((i=alloc_ringdesc(dev)))
651 goto out_err;
652
653 spin_lock_irq(&np->lock);
654 netif_device_attach(dev);
655 init_registers(dev);
656 spin_unlock_irq(&np->lock);
657
658 netif_start_queue(dev);
659 if (debug > 2)
660 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
661
662 /* Set the timer to check for link beat. */
663 init_timer(&np->timer);
664 np->timer.expires = jiffies + 1*HZ;
665 np->timer.data = (unsigned long)dev;
666 np->timer.function = &netdev_timer; /* timer handler */
667 add_timer(&np->timer);
668 return 0;
669out_err:
670 netif_device_attach(dev);
671 return i;
672}
673
674#define MII_DAVICOM_DM9101 0x0181b800
675
676static int update_link(struct net_device *dev)
677{
678 struct netdev_private *np = netdev_priv(dev);
679 int duplex, fasteth, result, mii_reg;
680
681 /* BSMR */
682 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
683
684 if (mii_reg == 0xffff)
685 return np->csr6;
686 /* reread: the link status bit is sticky */
687 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
688 if (!(mii_reg & 0x4)) {
689 if (netif_carrier_ok(dev)) {
690 if (debug)
691 printk(KERN_INFO "%s: MII #%d reports no link. Disabling watchdog.\n",
692 dev->name, np->phys[0]);
693 netif_carrier_off(dev);
694 }
695 return np->csr6;
696 }
697 if (!netif_carrier_ok(dev)) {
698 if (debug)
699 printk(KERN_INFO "%s: MII #%d link is back. Enabling watchdog.\n",
700 dev->name, np->phys[0]);
701 netif_carrier_on(dev);
702 }
f3b197ac 703
1da177e4
LT		 704 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
705 /* If the link partner doesn't support autonegotiation
706 * the MII detects it's abilities with the "parallel detection".
707 * Some MIIs update the LPA register to the result of the parallel
708 * detection, some don't.
709 * The Davicom PHY [at least 0181b800] doesn't.
710 * Instead bit 9 and 13 of the BMCR are updated to the result
711 * of the negotiation..
712 */
713 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
714 duplex = mii_reg & BMCR_FULLDPLX;
715 fasteth = mii_reg & BMCR_SPEED100;
716 } else {
717 int negotiated;
718 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
719 negotiated = mii_reg & np->mii_if.advertising;
720
721 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
722 fasteth = negotiated & 0x380;
723 }
724 duplex |= np->mii_if.force_media;
725 /* remove fastether and fullduplex */
726 result = np->csr6 & ~0x20000200;
727 if (duplex)
728 result |= 0x200;
729 if (fasteth)
730 result |= 0x20000000;
731 if (result != np->csr6 && debug)
732 printk(KERN_INFO "%s: Setting %dMBit-%s-duplex based on MII#%d\n",
f3b197ac 733 dev->name, fasteth ? 100 : 10,
1da177e4
LT		 734 duplex ? "full" : "half", np->phys[0]);
735 return result;
736}
737
738#define RXTX_TIMEOUT 2000
739static inline void update_csr6(struct net_device *dev, int new)
740{
741 struct netdev_private *np = netdev_priv(dev);
742 void __iomem *ioaddr = np->base_addr;
743 int limit = RXTX_TIMEOUT;
744
745 if (!netif_device_present(dev))
746 new = 0;
747 if (new==np->csr6)
748 return;
749 /* stop both Tx and Rx processes */
750 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
751 /* wait until they have really stopped */
752 for (;;) {
753 int csr5 = ioread32(ioaddr + IntrStatus);
754 int t;
755
756 t = (csr5 >> 17) & 0x07;
757 if (t==0||t==1) {
758 /* rx stopped */
759 t = (csr5 >> 20) & 0x07;
760 if (t==0||t==1)
761 break;
762 }
763
764 limit--;
765 if(!limit) {
766 printk(KERN_INFO "%s: couldn't stop rxtx, IntrStatus %xh.\n",
767 dev->name, csr5);
768 break;
769 }
770 udelay(1);
771 }
772 np->csr6 = new;
773 /* and restart them with the new configuration */
774 iowrite32(np->csr6, ioaddr + NetworkConfig);
775 if (new & 0x200)
776 np->mii_if.full_duplex = 1;
777}
778
779static void netdev_timer(unsigned long data)
780{
781 struct net_device *dev = (struct net_device *)data;
782 struct netdev_private *np = netdev_priv(dev);
783 void __iomem *ioaddr = np->base_addr;
784
785 if (debug > 2)
786 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
787 "config %8.8x.\n",
788 dev->name, ioread32(ioaddr + IntrStatus),
789 ioread32(ioaddr + NetworkConfig));
790 spin_lock_irq(&np->lock);
791 update_csr6(dev, update_link(dev));
792 spin_unlock_irq(&np->lock);
793 np->timer.expires = jiffies + 10*HZ;
794 add_timer(&np->timer);
795}
796
797static void init_rxtx_rings(struct net_device *dev)
798{
799 struct netdev_private *np = netdev_priv(dev);
800 int i;
801
802 np->rx_head_desc = &np->rx_ring[0];
803 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
804
805 /* Initial all Rx descriptors. */
806 for (i = 0; i < RX_RING_SIZE; i++) {
807 np->rx_ring[i].length = np->rx_buf_sz;
808 np->rx_ring[i].status = 0;
809 np->rx_skbuff[i] = NULL;
810 }
811 /* Mark the last entry as wrapping the ring. */
812 np->rx_ring[i-1].length |= DescEndRing;
813
814 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
815 for (i = 0; i < RX_RING_SIZE; i++) {
816 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
817 np->rx_skbuff[i] = skb;
818 if (skb == NULL)
819 break;
689be439 820 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data,
bb02aacc 821 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
1da177e4
LT		 822
823 np->rx_ring[i].buffer1 = np->rx_addr[i];
42eab567 824 np->rx_ring[i].status = DescOwned;
1da177e4
LT		 825 }
826
827 np->cur_rx = 0;
828 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
829
830 /* Initialize the Tx descriptors */
831 for (i = 0; i < TX_RING_SIZE; i++) {
832 np->tx_skbuff[i] = NULL;
833 np->tx_ring[i].status = 0;
834 }
835 np->tx_full = 0;
836 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
837
838 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
839 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
840 np->base_addr + TxRingPtr);
841
842}
843
844static void free_rxtx_rings(struct netdev_private* np)
845{
846 int i;
847 /* Free all the skbuffs in the Rx queue. */
848 for (i = 0; i < RX_RING_SIZE; i++) {
849 np->rx_ring[i].status = 0;
850 if (np->rx_skbuff[i]) {
851 pci_unmap_single(np->pci_dev,
852 np->rx_addr[i],
853 np->rx_skbuff[i]->len,
854 PCI_DMA_FROMDEVICE);
855 dev_kfree_skb(np->rx_skbuff[i]);
856 }
857 np->rx_skbuff[i] = NULL;
858 }
859 for (i = 0; i < TX_RING_SIZE; i++) {
860 if (np->tx_skbuff[i]) {
861 pci_unmap_single(np->pci_dev,
862 np->tx_addr[i],
863 np->tx_skbuff[i]->len,
864 PCI_DMA_TODEVICE);
865 dev_kfree_skb(np->tx_skbuff[i]);
866 }
867 np->tx_skbuff[i] = NULL;
868 }
869}
870
871static void init_registers(struct net_device *dev)
872{
873 struct netdev_private *np = netdev_priv(dev);
874 void __iomem *ioaddr = np->base_addr;
875 int i;
876
877 for (i = 0; i < 6; i++)
878 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
879
880 /* Initialize other registers. */
881#ifdef __BIG_ENDIAN
882 i = (1<<20); /* Big-endian descriptors */
883#else
884 i = 0;
885#endif
886 i |= (0x04<<2); /* skip length 4 u32 */
887 i |= 0x02; /* give Rx priority */
888
889 /* Configure the PCI bus bursts and FIFO thresholds.
890 486: Set 8 longword cache alignment, 8 longword burst.
891 586: Set 16 longword cache alignment, no burst limit.
892 Cache alignment bits 15:14 Burst length 13:8
893 0000 <not allowed> 0000 align to cache 0800 8 longwords
894 4000 8 longwords 0100 1 longword 1000 16 longwords
895 8000 16 longwords 0200 2 longwords 2000 32 longwords
896 C000 32 longwords 0400 4 longwords */
897
898#if defined (__i386__) && !defined(MODULE)
899 /* When not a module we can work around broken '486 PCI boards. */
900 if (boot_cpu_data.x86 <= 4) {
901 i |= 0x4800;
902 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting cache "
903 "alignment to 8 longwords.\n", dev->name);
904 } else {
905 i |= 0xE000;
906 }
907#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
908 i |= 0xE000;
49345103 909#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC)
1da177e4
LT		 910 i |= 0x4800;
911#else
912#warning Processor architecture undefined
913 i |= 0x4800;
914#endif
915 iowrite32(i, ioaddr + PCIBusCfg);
916
917 np->csr6 = 0;
f3b197ac 918 /* 128 byte Tx threshold;
1da177e4
LT		 919 Transmit on; Receive on; */
920 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
921
922 /* Clear and Enable interrupts by setting the interrupt mask. */
923 iowrite32(0x1A0F5, ioaddr + IntrStatus);
924 iowrite32(0x1A0F5, ioaddr + IntrEnable);
925
926 iowrite32(0, ioaddr + RxStartDemand);
927}
928
929static void tx_timeout(struct net_device *dev)
930{
931 struct netdev_private *np = netdev_priv(dev);
932 void __iomem *ioaddr = np->base_addr;
933
934 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
935 " resetting...\n", dev->name, ioread32(ioaddr + IntrStatus));
936
937 {
938 int i;
939 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
940 for (i = 0; i < RX_RING_SIZE; i++)
941 printk(" %8.8x", (unsigned int)np->rx_ring[i].status);
ad361c98 942 printk(KERN_DEBUG" Tx ring %p: ", np->tx_ring);
1da177e4
LT		 943 for (i = 0; i < TX_RING_SIZE; i++)
944 printk(" %8.8x", np->tx_ring[i].status);
945 printk("\n");
946 }
947 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d.\n",
948 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
949 printk(KERN_DEBUG "Tx Descriptor addr %xh.\n",ioread32(ioaddr+0x4C));
950
951 disable_irq(dev->irq);
952 spin_lock_irq(&np->lock);
953 /*
954 * Under high load dirty_tx and the internal tx descriptor pointer
955 * come out of sync, thus perform a software reset and reinitialize
956 * everything.
957 */
958
959 iowrite32(1, np->base_addr+PCIBusCfg);
960 udelay(1);
961
962 free_rxtx_rings(np);
963 init_rxtx_rings(dev);
964 init_registers(dev);
965 spin_unlock_irq(&np->lock);
966 enable_irq(dev->irq);
967
968 netif_wake_queue(dev);
969 dev->trans_start = jiffies;
970 np->stats.tx_errors++;
971 return;
972}
973
974/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
975static int alloc_ringdesc(struct net_device *dev)
976{
977 struct netdev_private *np = netdev_priv(dev);
978
979 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
980
981 np->rx_ring = pci_alloc_consistent(np->pci_dev,
982 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
983 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
984 &np->ring_dma_addr);
985 if(!np->rx_ring)
986 return -ENOMEM;
987 init_rxtx_rings(dev);
988 return 0;
989}
990
991static void free_ringdesc(struct netdev_private *np)
992{
993 pci_free_consistent(np->pci_dev,
994 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
995 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
996 np->rx_ring, np->ring_dma_addr);
997
998}
999
ad096463 1000static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 1001{
1002 struct netdev_private *np = netdev_priv(dev);
1003 unsigned entry;
1004
1005 /* Caution: the write order is important here, set the field
1006 with the "ownership" bits last. */
1007
1008 /* Calculate the next Tx descriptor entry. */
1009 entry = np->cur_tx % TX_RING_SIZE;
1010
1011 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1012 skb->data,skb->len, PCI_DMA_TODEVICE);
1013 np->tx_skbuff[entry] = skb;
1014
1015 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1016 if (skb->len < TX_BUFLIMIT) {
1017 np->tx_ring[entry].length = DescWholePkt | skb->len;
1018 } else {
1019 int len = skb->len - TX_BUFLIMIT;
1020
1021 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1022 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1023 }
1024 if(entry == TX_RING_SIZE-1)
1025 np->tx_ring[entry].length |= DescEndRing;
1026
1027 /* Now acquire the irq spinlock.
59c51591 1028 * The difficult race is the ordering between
42eab567 1029 * increasing np->cur_tx and setting DescOwned:
1da177e4
LT		 1030 * - if np->cur_tx is increased first the interrupt
1031 * handler could consider the packet as transmitted
42eab567
GG		 1032 * since DescOwned is cleared.
1033 * - If DescOwned is set first the NIC could report the
1da177e4
LT		 1034 * packet as sent, but the interrupt handler would ignore it
1035 * since the np->cur_tx was not yet increased.
1036 */
1037 spin_lock_irq(&np->lock);
1038 np->cur_tx++;
1039
1040 wmb(); /* flush length, buffer1, buffer2 */
42eab567 1041 np->tx_ring[entry].status = DescOwned;
1da177e4
LT		 1042 wmb(); /* flush status and kick the hardware */
1043 iowrite32(0, np->base_addr + TxStartDemand);
1044 np->tx_q_bytes += skb->len;
1045 /* Work around horrible bug in the chip by marking the queue as full
1046 when we do not have FIFO room for a maximum sized packet. */
1047 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1048 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1049 netif_stop_queue(dev);
1050 wmb();
1051 np->tx_full = 1;
1052 }
1053 spin_unlock_irq(&np->lock);
1054
1055 dev->trans_start = jiffies;
1056
1057 if (debug > 4) {
1058 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1059 dev->name, np->cur_tx, entry);
1060 }
6ed10654 1061 return NETDEV_TX_OK;
1da177e4
LT		 1062}
1063
1064static void netdev_tx_done(struct net_device *dev)
1065{
1066 struct netdev_private *np = netdev_priv(dev);
1067 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1068 int entry = np->dirty_tx % TX_RING_SIZE;
1069 int tx_status = np->tx_ring[entry].status;
1070
1071 if (tx_status < 0)
1072 break;
1073 if (tx_status & 0x8000) { /* There was an error, log it. */
1074#ifndef final_version
1075 if (debug > 1)
1076 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1077 dev->name, tx_status);
1078#endif
1079 np->stats.tx_errors++;
1080 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1081 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1082 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1083 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1084 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1085 np->stats.tx_heartbeat_errors++;
1086 } else {
1087#ifndef final_version
1088 if (debug > 3)
1089 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %8.8x.\n",
1090 dev->name, entry, tx_status);
1091#endif
1092 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1093 np->stats.collisions += (tx_status >> 3) & 15;
1094 np->stats.tx_packets++;
1095 }
1096 /* Free the original skb. */
1097 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1098 np->tx_skbuff[entry]->len,
1099 PCI_DMA_TODEVICE);
1100 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1101 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1102 np->tx_skbuff[entry] = NULL;
1103 }
1104 if (np->tx_full &&
1105 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1106 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1107 /* The ring is no longer full, clear tbusy. */
1108 np->tx_full = 0;
1109 wmb();
1110 netif_wake_queue(dev);
1111 }
1112}
1113
1114/* The interrupt handler does all of the Rx thread work and cleans up
1115 after the Tx thread. */
7d12e780 1116static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1117{
1118 struct net_device *dev = (struct net_device *)dev_instance;
1119 struct netdev_private *np = netdev_priv(dev);
1120 void __iomem *ioaddr = np->base_addr;
1121 int work_limit = max_interrupt_work;
1122 int handled = 0;
1123
1124 if (!netif_device_present(dev))
1125 return IRQ_NONE;
1126 do {
1127 u32 intr_status = ioread32(ioaddr + IntrStatus);
1128
1129 /* Acknowledge all of the current interrupt sources ASAP. */
1130 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1131
1132 if (debug > 4)
1133 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1134 dev->name, intr_status);
1135
1136 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1137 break;
1138
1139 handled = 1;
1140
42eab567 1141 if (intr_status & (RxIntr | RxNoBuf))
1da177e4
LT		 1142 netdev_rx(dev);
1143 if (intr_status & RxNoBuf)
1144 iowrite32(0, ioaddr + RxStartDemand);
1145
42eab567 1146 if (intr_status & (TxNoBuf | TxIntr) &&
1da177e4
LT		 1147 np->cur_tx != np->dirty_tx) {
1148 spin_lock(&np->lock);
1149 netdev_tx_done(dev);
1150 spin_unlock(&np->lock);
1151 }
1152
1153 /* Abnormal error summary/uncommon events handlers. */
1ddb9861 1154 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
42eab567 1155 TimerInt | TxDied))
1da177e4
LT		 1156 netdev_error(dev, intr_status);
1157
1158 if (--work_limit < 0) {
1159 printk(KERN_WARNING "%s: Too much work at interrupt, "
1160 "status=0x%4.4x.\n", dev->name, intr_status);
1161 /* Set the timer to re-enable the other interrupts after
1162 10*82usec ticks. */
1163 spin_lock(&np->lock);
1164 if (netif_device_present(dev)) {
1165 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1166 iowrite32(10, ioaddr + GPTimer);
1167 }
1168 spin_unlock(&np->lock);
1169 break;
1170 }
1171 } while (1);
1172
1173 if (debug > 3)
1174 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1175 dev->name, ioread32(ioaddr + IntrStatus));
1176 return IRQ_RETVAL(handled);
1177}
1178
1179/* This routine is logically part of the interrupt handler, but separated
1180 for clarity and better register allocation. */
1181static int netdev_rx(struct net_device *dev)
1182{
1183 struct netdev_private *np = netdev_priv(dev);
1184 int entry = np->cur_rx % RX_RING_SIZE;
1185 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1186
1187 if (debug > 4) {
1188 printk(KERN_DEBUG " In netdev_rx(), entry %d status %4.4x.\n",
1189 entry, np->rx_ring[entry].status);
1190 }
1191
1192 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1193 while (--work_limit >= 0) {
1194 struct w840_rx_desc *desc = np->rx_head_desc;
1195 s32 status = desc->status;
1196
1197 if (debug > 4)
1198 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1199 status);
1200 if (status < 0)
1201 break;
1202 if ((status & 0x38008300) != 0x0300) {
1203 if ((status & 0x38000300) != 0x0300) {
1204 /* Ingore earlier buffers. */
1205 if ((status & 0xffff) != 0x7fff) {
1206 printk(KERN_WARNING "%s: Oversized Ethernet frame spanned "
1207 "multiple buffers, entry %#x status %4.4x!\n",
1208 dev->name, np->cur_rx, status);
1209 np->stats.rx_length_errors++;
1210 }
1211 } else if (status & 0x8000) {
1212 /* There was a fatal error. */
1213 if (debug > 2)
1214 printk(KERN_DEBUG "%s: Receive error, Rx status %8.8x.\n",
1215 dev->name, status);
1216 np->stats.rx_errors++; /* end of a packet.*/
1217 if (status & 0x0890) np->stats.rx_length_errors++;
1218 if (status & 0x004C) np->stats.rx_frame_errors++;
1219 if (status & 0x0002) np->stats.rx_crc_errors++;
1220 }
1221 } else {
1222 struct sk_buff *skb;
1223 /* Omit the four octet CRC from the length. */
1224 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1225
1226#ifndef final_version
1227 if (debug > 4)
1228 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1229 " status %x.\n", pkt_len, status);
1230#endif
1231 /* Check if the packet is long enough to accept without copying
1232 to a minimally-sized skbuff. */
8e95a202
JP		 1233 if (pkt_len < rx_copybreak &&
1234 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1235 skb_reserve(skb, 2); /* 16 byte align the IP header */
1236 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1237 np->rx_skbuff[entry]->len,
1238 PCI_DMA_FROMDEVICE);
8c7b7faa 1239 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 1240 skb_put(skb, pkt_len);
1241 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1242 np->rx_skbuff[entry]->len,
1243 PCI_DMA_FROMDEVICE);
1244 } else {
1245 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1246 np->rx_skbuff[entry]->len,
1247 PCI_DMA_FROMDEVICE);
1248 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1249 np->rx_skbuff[entry] = NULL;
1250 }
1251#ifndef final_version /* Remove after testing. */
1252 /* You will want this info for the initial debug. */
e174961c
JB		 1253 if (debug > 5)
1254 printk(KERN_DEBUG " Rx data %pM %pM"
0795af57 1255 " %2.2x%2.2x %d.%d.%d.%d.\n",
e174961c 1256 &skb->data[0], &skb->data[6],
0795af57
JP		 1257 skb->data[12], skb->data[13],
1258 skb->data[14], skb->data[15], skb->data[16], skb->data[17]);
1da177e4
LT		 1259#endif
1260 skb->protocol = eth_type_trans(skb, dev);
1261 netif_rx(skb);
1da177e4
LT		 1262 np->stats.rx_packets++;
1263 np->stats.rx_bytes += pkt_len;
1264 }
1265 entry = (++np->cur_rx) % RX_RING_SIZE;
1266 np->rx_head_desc = &np->rx_ring[entry];
1267 }
1268
1269 /* Refill the Rx ring buffers. */
1270 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1271 struct sk_buff *skb;
1272 entry = np->dirty_rx % RX_RING_SIZE;
1273 if (np->rx_skbuff[entry] == NULL) {
1274 skb = dev_alloc_skb(np->rx_buf_sz);
1275 np->rx_skbuff[entry] = skb;
1276 if (skb == NULL)
1277 break; /* Better luck next round. */
1da177e4 1278 np->rx_addr[entry] = pci_map_single(np->pci_dev,
689be439 1279 skb->data,
bb02aacc 1280 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1281 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1282 }
1283 wmb();
42eab567 1284 np->rx_ring[entry].status = DescOwned;
1da177e4
LT		 1285 }
1286
1287 return 0;
1288}
1289
1290static void netdev_error(struct net_device *dev, int intr_status)
1291{
1292 struct netdev_private *np = netdev_priv(dev);
1293 void __iomem *ioaddr = np->base_addr;
1294
1295 if (debug > 2)
1296 printk(KERN_DEBUG "%s: Abnormal event, %8.8x.\n",
1297 dev->name, intr_status);
1298 if (intr_status == 0xffffffff)
1299 return;
1300 spin_lock(&np->lock);
1301 if (intr_status & TxFIFOUnderflow) {
1302 int new;
1303 /* Bump up the Tx threshold */
1304#if 0
1305 /* This causes lots of dropped packets,
1306 * and under high load even tx_timeouts
1307 */
1308 new = np->csr6 + 0x4000;
1309#else
1310 new = (np->csr6 >> 14)&0x7f;
1311 if (new < 64)
1312 new *= 2;
1313 else
1314 new = 127; /* load full packet before starting */
1315 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1316#endif
1317 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %8.8x.\n",
1318 dev->name, new);
1319 update_csr6(dev, new);
1320 }
42eab567 1321 if (intr_status & RxDied) { /* Missed a Rx frame. */
1da177e4
LT		 1322 np->stats.rx_errors++;
1323 }
1324 if (intr_status & TimerInt) {
1325 /* Re-enable other interrupts. */
1326 if (netif_device_present(dev))
1327 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1328 }
1329 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1330 iowrite32(0, ioaddr + RxStartDemand);
1331 spin_unlock(&np->lock);
1332}
1333
1334static struct net_device_stats *get_stats(struct net_device *dev)
1335{
1336 struct netdev_private *np = netdev_priv(dev);
1337 void __iomem *ioaddr = np->base_addr;
1338
1339 /* The chip only need report frame silently dropped. */
1340 spin_lock_irq(&np->lock);
1341 if (netif_running(dev) && netif_device_present(dev))
1342 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1343 spin_unlock_irq(&np->lock);
1344
1345 return &np->stats;
1346}
1347
1348
1349static u32 __set_rx_mode(struct net_device *dev)
1350{
1351 struct netdev_private *np = netdev_priv(dev);
1352 void __iomem *ioaddr = np->base_addr;
1353 u32 mc_filter[2]; /* Multicast hash filter */
1354 u32 rx_mode;
1355
1356 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1357 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1358 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1da177e4 1359 | AcceptMyPhys;
8e95a202
JP		 1360 } else if ((dev->mc_count > multicast_filter_limit) ||
1361 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1362 /* Too many to match, or accept all multicasts. */
1363 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1364 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4
LT		 1365 } else {
1366 struct dev_mc_list *mclist;
1367 int i;
1368 memset(mc_filter, 0, sizeof(mc_filter));
1369 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1370 i++, mclist = mclist->next) {
1371 int filterbit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1372 filterbit &= 0x3f;
1373 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1374 }
42eab567 1375 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4
LT		 1376 }
1377 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1378 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1379 return rx_mode;
1380}
1381
1382static void set_rx_mode(struct net_device *dev)
1383{
1384 struct netdev_private *np = netdev_priv(dev);
1385 u32 rx_mode = __set_rx_mode(dev);
1386 spin_lock_irq(&np->lock);
1387 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1388 spin_unlock_irq(&np->lock);
1389}
1390
1391static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1392{
1393 struct netdev_private *np = netdev_priv(dev);
1394
1395 strcpy (info->driver, DRV_NAME);
1396 strcpy (info->version, DRV_VERSION);
1397 strcpy (info->bus_info, pci_name(np->pci_dev));
1398}
1399
1400static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1401{
1402 struct netdev_private *np = netdev_priv(dev);
1403 int rc;
1404
1405 spin_lock_irq(&np->lock);
1406 rc = mii_ethtool_gset(&np->mii_if, cmd);
1407 spin_unlock_irq(&np->lock);
1408
1409 return rc;
1410}
1411
1412static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1413{
1414 struct netdev_private *np = netdev_priv(dev);
1415 int rc;
1416
1417 spin_lock_irq(&np->lock);
1418 rc = mii_ethtool_sset(&np->mii_if, cmd);
1419 spin_unlock_irq(&np->lock);
1420
1421 return rc;
1422}
1423
1424static int netdev_nway_reset(struct net_device *dev)
1425{
1426 struct netdev_private *np = netdev_priv(dev);
1427 return mii_nway_restart(&np->mii_if);
1428}
1429
1430static u32 netdev_get_link(struct net_device *dev)
1431{
1432 struct netdev_private *np = netdev_priv(dev);
1433 return mii_link_ok(&np->mii_if);
1434}
1435
1436static u32 netdev_get_msglevel(struct net_device *dev)
1437{
1438 return debug;
1439}
1440
1441static void netdev_set_msglevel(struct net_device *dev, u32 value)
1442{
1443 debug = value;
1444}
1445
7282d491 1446static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1447 .get_drvinfo = netdev_get_drvinfo,
1448 .get_settings = netdev_get_settings,
1449 .set_settings = netdev_set_settings,
1450 .nway_reset = netdev_nway_reset,
1451 .get_link = netdev_get_link,
1452 .get_msglevel = netdev_get_msglevel,
1453 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1454};
1455
1456static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1457{
1458 struct mii_ioctl_data *data = if_mii(rq);
1459 struct netdev_private *np = netdev_priv(dev);
1460
1461 switch(cmd) {
1462 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1463 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1464 /* Fall Through */
1465
1466 case SIOCGMIIREG: /* Read MII PHY register. */
1467 spin_lock_irq(&np->lock);
1468 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1469 spin_unlock_irq(&np->lock);
1470 return 0;
1471
1472 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 1473 spin_lock_irq(&np->lock);
1474 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1475 spin_unlock_irq(&np->lock);
1476 return 0;
1477 default:
1478 return -EOPNOTSUPP;
1479 }
1480}
1481
1482static int netdev_close(struct net_device *dev)
1483{
1484 struct netdev_private *np = netdev_priv(dev);
1485 void __iomem *ioaddr = np->base_addr;
1486
1487 netif_stop_queue(dev);
1488
1489 if (debug > 1) {
1490 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %8.8x "
1491 "Config %8.8x.\n", dev->name, ioread32(ioaddr + IntrStatus),
1492 ioread32(ioaddr + NetworkConfig));
1493 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1494 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1495 }
1496
1497 /* Stop the chip's Tx and Rx processes. */
1498 spin_lock_irq(&np->lock);
1499 netif_device_detach(dev);
1500 update_csr6(dev, 0);
1501 iowrite32(0x0000, ioaddr + IntrEnable);
1502 spin_unlock_irq(&np->lock);
1503
1504 free_irq(dev->irq, dev);
1505 wmb();
1506 netif_device_attach(dev);
1507
1508 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1509 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1510
1511#ifdef __i386__
1512 if (debug > 2) {
1513 int i;
1514
1515 printk(KERN_DEBUG" Tx ring at %8.8x:\n",
1516 (int)np->tx_ring);
1517 for (i = 0; i < TX_RING_SIZE; i++)
1518 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x.\n",
1519 i, np->tx_ring[i].length,
1520 np->tx_ring[i].status, np->tx_ring[i].buffer1);
ad361c98 1521 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1da177e4
LT		 1522 (int)np->rx_ring);
1523 for (i = 0; i < RX_RING_SIZE; i++) {
1524 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1525 i, np->rx_ring[i].length,
1526 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1527 }
1528 }
1529#endif /* __i386__ debugging only */
1530
1531 del_timer_sync(&np->timer);
1532
1533 free_rxtx_rings(np);
1534 free_ringdesc(np);
1535
1536 return 0;
1537}
1538
1539static void __devexit w840_remove1 (struct pci_dev *pdev)
1540{
1541 struct net_device *dev = pci_get_drvdata(pdev);
f3b197ac 1542
1da177e4
LT		 1543 if (dev) {
1544 struct netdev_private *np = netdev_priv(dev);
1545 unregister_netdev(dev);
1546 pci_release_regions(pdev);
1547 pci_iounmap(pdev, np->base_addr);
1548 free_netdev(dev);
1549 }
1550
1551 pci_set_drvdata(pdev, NULL);
1552}
1553
1554#ifdef CONFIG_PM
1555
1556/*
1557 * suspend/resume synchronization:
1558 * - open, close, do_ioctl:
1559 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1560 * - get_stats:
1561 * spin_lock_irq(np->lock), doesn't touch hw if not present
2a97e6b7 1562 * - start_xmit:
932ff279 1563 * synchronize_irq + netif_tx_disable;
1da177e4 1564 * - tx_timeout:
932ff279 1565 * netif_device_detach + netif_tx_disable;
1da177e4 1566 * - set_multicast_list
932ff279 1567 * netif_device_detach + netif_tx_disable;
1da177e4
LT		 1568 * - interrupt handler
1569 * doesn't touch hw if not present, synchronize_irq waits for
1570 * running instances of the interrupt handler.
1571 *
1572 * Disabling hw requires clearing csr6 & IntrEnable.
1573 * update_csr6 & all function that write IntrEnable check netif_device_present
1574 * before settings any bits.
1575 *
1576 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1577 * device would cause an irq storm.
1578 */
05adc3b7 1579static int w840_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1580{
1581 struct net_device *dev = pci_get_drvdata (pdev);
1582 struct netdev_private *np = netdev_priv(dev);
1583 void __iomem *ioaddr = np->base_addr;
1584
1585 rtnl_lock();
1586 if (netif_running (dev)) {
1587 del_timer_sync(&np->timer);
1588
1589 spin_lock_irq(&np->lock);
1590 netif_device_detach(dev);
1591 update_csr6(dev, 0);
1592 iowrite32(0, ioaddr + IntrEnable);
1da177e4
LT		 1593 spin_unlock_irq(&np->lock);
1594
1da177e4 1595 synchronize_irq(dev->irq);
932ff279 1596 netif_tx_disable(dev);
6aa20a22 1597
1da177e4
LT		 1598 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1599
1600 /* no more hardware accesses behind this line. */
1601
0ee904c3 1602 BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
1da177e4
LT		 1603
1604 /* pci_power_off(pdev, -1); */
1605
1606 free_rxtx_rings(np);
1607 } else {
1608 netif_device_detach(dev);
1609 }
1610 rtnl_unlock();
1611 return 0;
1612}
1613
1614static int w840_resume (struct pci_dev *pdev)
1615{
1616 struct net_device *dev = pci_get_drvdata (pdev);
1617 struct netdev_private *np = netdev_priv(dev);
9f486ae1 1618 int retval = 0;
1da177e4
LT		 1619
1620 rtnl_lock();
1621 if (netif_device_present(dev))
1622 goto out; /* device not suspended */
1623 if (netif_running(dev)) {
9f486ae1
VH		 1624 if ((retval = pci_enable_device(pdev))) {
1625 printk (KERN_ERR
1626 "%s: pci_enable_device failed in resume\n",
1627 dev->name);
1628 goto out;
1629 }
1da177e4
LT		 1630 spin_lock_irq(&np->lock);
1631 iowrite32(1, np->base_addr+PCIBusCfg);
1632 ioread32(np->base_addr+PCIBusCfg);
1633 udelay(1);
1634 netif_device_attach(dev);
1635 init_rxtx_rings(dev);
1636 init_registers(dev);
1637 spin_unlock_irq(&np->lock);
1638
1639 netif_wake_queue(dev);
1640
1641 mod_timer(&np->timer, jiffies + 1*HZ);
1642 } else {
1643 netif_device_attach(dev);
1644 }
1645out:
1646 rtnl_unlock();
9f486ae1 1647 return retval;
1da177e4
LT		 1648}
1649#endif
1650
1651static struct pci_driver w840_driver = {
1652 .name = DRV_NAME,
1653 .id_table = w840_pci_tbl,
1654 .probe = w840_probe1,
1655 .remove = __devexit_p(w840_remove1),
1656#ifdef CONFIG_PM
1657 .suspend = w840_suspend,
1658 .resume = w840_resume,
1659#endif
1660};
1661
1662static int __init w840_init(void)
1663{
1664 printk(version);
29917620 1665 return pci_register_driver(&w840_driver);
1da177e4
LT		 1666}
1667
1668static void __exit w840_exit(void)
1669{
1670 pci_unregister_driver(&w840_driver);
1671}
1672
1673module_init(w840_init);
1674module_exit(w840_exit);
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