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1da177e4
LT		 1/* winbond-840.c: A Linux PCI network adapter device driver. */
2/*
3 Written 1998-2001 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/drivers.html
19
20 Do not remove the copyright information.
21 Do not change the version information unless an improvement has been made.
22 Merely removing my name, as Compex has done in the past, does not count
23 as an improvement.
24
25 Changelog:
26 * ported to 2.4
27 ???
28 * spin lock update, memory barriers, new style dma mappings
29 limit each tx buffer to < 1024 bytes
30 remove DescIntr from Rx descriptors (that's an Tx flag)
31 remove next pointer from Tx descriptors
32 synchronize tx_q_bytes
33 software reset in tx_timeout
34 Copyright (C) 2000 Manfred Spraul
35 * further cleanups
36 power management.
37 support for big endian descriptors
38 Copyright (C) 2001 Manfred Spraul
39 * ethtool support (jgarzik)
40 * Replace some MII-related magic numbers with constants (jgarzik)
f3b197ac 41
1da177e4
LT		 42 TODO:
43 * enable pci_power_off
44 * Wake-On-LAN
45*/
f3b197ac 46
1da177e4 47#define DRV_NAME "winbond-840"
d5b20697
AG		 48#define DRV_VERSION "1.01-e"
49#define DRV_RELDATE "Sep-11-2006"
1da177e4
LT		 50
51
52/* Automatically extracted configuration info:
53probe-func: winbond840_probe
54config-in: tristate 'Winbond W89c840 Ethernet support' CONFIG_WINBOND_840
55
56c-help-name: Winbond W89c840 PCI Ethernet support
57c-help-symbol: CONFIG_WINBOND_840
58c-help: This driver is for the Winbond W89c840 chip. It also works with
59c-help: the TX9882 chip on the Compex RL100-ATX board.
f3b197ac 60c-help: More specific information and updates are available from
1da177e4
LT		 61c-help: http://www.scyld.com/network/drivers.html
62*/
63
64/* The user-configurable values.
65 These may be modified when a driver module is loaded.*/
66
67static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
68static int max_interrupt_work = 20;
69/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
70 The '840 uses a 64 element hash table based on the Ethernet CRC. */
71static int multicast_filter_limit = 32;
72
73/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
74 Setting to > 1518 effectively disables this feature. */
75static int rx_copybreak;
76
77/* Used to pass the media type, etc.
78 Both 'options[]' and 'full_duplex[]' should exist for driver
79 interoperability.
80 The media type is usually passed in 'options[]'.
81*/
82#define MAX_UNITS 8 /* More are supported, limit only on options */
83static int options[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
84static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
85
86/* Operational parameters that are set at compile time. */
87
88/* Keep the ring sizes a power of two for compile efficiency.
89 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
90 Making the Tx ring too large decreases the effectiveness of channel
91 bonding and packet priority.
92 There are no ill effects from too-large receive rings. */
1da177e4
LT		 93#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
94#define TX_QUEUE_LEN_RESTART 5
1da177e4
LT		 95
96#define TX_BUFLIMIT (1024-128)
97
98/* The presumed FIFO size for working around the Tx-FIFO-overflow bug.
99 To avoid overflowing we don't queue again until we have room for a
100 full-size packet.
101 */
102#define TX_FIFO_SIZE (2048)
103#define TX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16)
104
105
106/* Operational parameters that usually are not changed. */
107/* Time in jiffies before concluding the transmitter is hung. */
108#define TX_TIMEOUT (2*HZ)
109
1da177e4
LT		 110/* Include files, designed to support most kernel versions 2.0.0 and later. */
111#include <linux/module.h>
112#include <linux/kernel.h>
113#include <linux/string.h>
114#include <linux/timer.h>
115#include <linux/errno.h>
116#include <linux/ioport.h>
117#include <linux/slab.h>
118#include <linux/interrupt.h>
119#include <linux/pci.h>
10a87fcf 120#include <linux/dma-mapping.h>
1da177e4
LT		 121#include <linux/netdevice.h>
122#include <linux/etherdevice.h>
123#include <linux/skbuff.h>
124#include <linux/init.h>
125#include <linux/delay.h>
126#include <linux/ethtool.h>
127#include <linux/mii.h>
128#include <linux/rtnetlink.h>
129#include <linux/crc32.h>
130#include <linux/bitops.h>
131#include <asm/uaccess.h>
132#include <asm/processor.h> /* Processor type for cache alignment. */
133#include <asm/io.h>
134#include <asm/irq.h>
135
42eab567
GG		 136#include "tulip.h"
137
48dd59e3
JG		 138#undef PKT_BUF_SZ /* tulip.h also defines this */
139#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
140
1da177e4 141/* These identify the driver base version and may not be removed. */
03f54b3d
SH		 142static const char version[] __initconst =
143 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " (2.4 port) "
144 DRV_RELDATE " Donald Becker <becker@scyld.com>\n"
ad361c98 145 " http://www.scyld.com/network/drivers.html\n";
1da177e4
LT		 146
147MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
148MODULE_DESCRIPTION("Winbond W89c840 Ethernet driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
152module_param(max_interrupt_work, int, 0);
153module_param(debug, int, 0);
154module_param(rx_copybreak, int, 0);
155module_param(multicast_filter_limit, int, 0);
156module_param_array(options, int, NULL, 0);
157module_param_array(full_duplex, int, NULL, 0);
158MODULE_PARM_DESC(max_interrupt_work, "winbond-840 maximum events handled per interrupt");
159MODULE_PARM_DESC(debug, "winbond-840 debug level (0-6)");
160MODULE_PARM_DESC(rx_copybreak, "winbond-840 copy breakpoint for copy-only-tiny-frames");
161MODULE_PARM_DESC(multicast_filter_limit, "winbond-840 maximum number of filtered multicast addresses");
162MODULE_PARM_DESC(options, "winbond-840: Bits 0-3: media type, bit 17: full duplex");
163MODULE_PARM_DESC(full_duplex, "winbond-840 full duplex setting(s) (1)");
164
165/*
166 Theory of Operation
167
168I. Board Compatibility
169
170This driver is for the Winbond w89c840 chip.
171
172II. Board-specific settings
173
174None.
175
176III. Driver operation
177
178This chip is very similar to the Digital 21*4* "Tulip" family. The first
179twelve registers and the descriptor format are nearly identical. Read a
180Tulip manual for operational details.
181
182A significant difference is that the multicast filter and station address are
183stored in registers rather than loaded through a pseudo-transmit packet.
184
185Unlike the Tulip, transmit buffers are limited to 1KB. To transmit a
186full-sized packet we must use both data buffers in a descriptor. Thus the
187driver uses ring mode where descriptors are implicitly sequential in memory,
188rather than using the second descriptor address as a chain pointer to
189subsequent descriptors.
190
191IV. Notes
192
193If you are going to almost clone a Tulip, why not go all the way and avoid
194the need for a new driver?
195
196IVb. References
197
198http://www.scyld.com/expert/100mbps.html
199http://www.scyld.com/expert/NWay.html
200http://www.winbond.com.tw/
201
202IVc. Errata
203
204A horrible bug exists in the transmit FIFO. Apparently the chip doesn't
205correctly detect a full FIFO, and queuing more than 2048 bytes may result in
206silent data corruption.
207
208Test with 'ping -s 10000' on a fast computer.
209
210*/
211
f3b197ac 212
1da177e4
LT		 213
214/*
215 PCI probe table.
216*/
1da177e4 217enum chip_capability_flags {
1f1bd5fc
JG		 218 CanHaveMII=1, HasBrokenTx=2, AlwaysFDX=4, FDXOnNoMII=8,
219};
220
a3aa1884 221static DEFINE_PCI_DEVICE_TABLE(w840_pci_tbl) = {
1da177e4
LT		 222 { 0x1050, 0x0840, PCI_ANY_ID, 0x8153, 0, 0, 0 },
223 { 0x1050, 0x0840, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
224 { 0x11f6, 0x2011, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
1f1bd5fc 225 { }
1da177e4
LT		 226};
227MODULE_DEVICE_TABLE(pci, w840_pci_tbl);
228
c3d8e682
JG		 229enum {
230 netdev_res_size = 128, /* size of PCI BAR resource */
231};
232
1da177e4
LT		 233struct pci_id_info {
234 const char *name;
c3d8e682 235 int drv_flags; /* Driver use, intended as capability flags. */
1da177e4 236};
c3d8e682
JG		 237
238static const struct pci_id_info pci_id_tbl[] __devinitdata = {
239 { /* Sometime a Level-One switch card. */
240 "Winbond W89c840", CanHaveMII | HasBrokenTx | FDXOnNoMII},
241 { "Winbond W89c840", CanHaveMII | HasBrokenTx},
242 { "Compex RL100-ATX", CanHaveMII | HasBrokenTx},
243 { } /* terminate list. */
1da177e4
LT		 244};
245
246/* This driver was written to use PCI memory space, however some x86 systems
42eab567
GG		 247 work only with I/O space accesses. See CONFIG_TULIP_MMIO in .config
248*/
1da177e4
LT		 249
250/* Offsets to the Command and Status Registers, "CSRs".
251 While similar to the Tulip, these registers are longword aligned.
252 Note: It's not useful to define symbolic names for every register bit in
253 the device. The name can only partially document the semantics and make
254 the driver longer and more difficult to read.
255*/
256enum w840_offsets {
257 PCIBusCfg=0x00, TxStartDemand=0x04, RxStartDemand=0x08,
258 RxRingPtr=0x0C, TxRingPtr=0x10,
259 IntrStatus=0x14, NetworkConfig=0x18, IntrEnable=0x1C,
260 RxMissed=0x20, EECtrl=0x24, MIICtrl=0x24, BootRom=0x28, GPTimer=0x2C,
261 CurRxDescAddr=0x30, CurRxBufAddr=0x34, /* Debug use */
262 MulticastFilter0=0x38, MulticastFilter1=0x3C, StationAddr=0x40,
263 CurTxDescAddr=0x4C, CurTxBufAddr=0x50,
264};
265
1da177e4
LT		 266/* Bits in the NetworkConfig register. */
267enum rx_mode_bits {
42eab567
GG		 268 AcceptErr=0x80,
269 RxAcceptBroadcast=0x20, AcceptMulticast=0x10,
270 RxAcceptAllPhys=0x08, AcceptMyPhys=0x02,
1da177e4
LT		 271};
272
273enum mii_reg_bits {
274 MDIO_ShiftClk=0x10000, MDIO_DataIn=0x80000, MDIO_DataOut=0x20000,
275 MDIO_EnbOutput=0x40000, MDIO_EnbIn = 0x00000,
276};
277
278/* The Tulip Rx and Tx buffer descriptors. */
279struct w840_rx_desc {
280 s32 status;
281 s32 length;
282 u32 buffer1;
283 u32 buffer2;
284};
285
286struct w840_tx_desc {
287 s32 status;
288 s32 length;
289 u32 buffer1, buffer2;
290};
291
1da177e4
LT		 292#define MII_CNT 1 /* winbond only supports one MII */
293struct netdev_private {
294 struct w840_rx_desc *rx_ring;
295 dma_addr_t rx_addr[RX_RING_SIZE];
296 struct w840_tx_desc *tx_ring;
297 dma_addr_t tx_addr[TX_RING_SIZE];
298 dma_addr_t ring_dma_addr;
299 /* The addresses of receive-in-place skbuffs. */
300 struct sk_buff* rx_skbuff[RX_RING_SIZE];
301 /* The saved address of a sent-in-place packet/buffer, for later free(). */
302 struct sk_buff* tx_skbuff[TX_RING_SIZE];
303 struct net_device_stats stats;
304 struct timer_list timer; /* Media monitoring timer. */
305 /* Frequently used values: keep some adjacent for cache effect. */
306 spinlock_t lock;
307 int chip_id, drv_flags;
308 struct pci_dev *pci_dev;
309 int csr6;
310 struct w840_rx_desc *rx_head_desc;
311 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
312 unsigned int rx_buf_sz; /* Based on MTU+slack. */
313 unsigned int cur_tx, dirty_tx;
314 unsigned int tx_q_bytes;
315 unsigned int tx_full; /* The Tx queue is full. */
316 /* MII transceiver section. */
317 int mii_cnt; /* MII device addresses. */
318 unsigned char phys[MII_CNT]; /* MII device addresses, but only the first is used */
319 u32 mii;
320 struct mii_if_info mii_if;
321 void __iomem *base_addr;
322};
323
324static int eeprom_read(void __iomem *ioaddr, int location);
325static int mdio_read(struct net_device *dev, int phy_id, int location);
326static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
327static int netdev_open(struct net_device *dev);
328static int update_link(struct net_device *dev);
329static void netdev_timer(unsigned long data);
330static void init_rxtx_rings(struct net_device *dev);
331static void free_rxtx_rings(struct netdev_private *np);
332static void init_registers(struct net_device *dev);
333static void tx_timeout(struct net_device *dev);
334static int alloc_ringdesc(struct net_device *dev);
335static void free_ringdesc(struct netdev_private *np);
ad096463 336static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
7d12e780 337static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 338static void netdev_error(struct net_device *dev, int intr_status);
339static int netdev_rx(struct net_device *dev);
340static u32 __set_rx_mode(struct net_device *dev);
341static void set_rx_mode(struct net_device *dev);
342static struct net_device_stats *get_stats(struct net_device *dev);
343static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
7282d491 344static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 345static int netdev_close(struct net_device *dev);
346
2a97e6b7
SH		 347static const struct net_device_ops netdev_ops = {
348 .ndo_open = netdev_open,
349 .ndo_stop = netdev_close,
350 .ndo_start_xmit = start_tx,
351 .ndo_get_stats = get_stats,
352 .ndo_set_multicast_list = set_rx_mode,
353 .ndo_do_ioctl = netdev_ioctl,
354 .ndo_tx_timeout = tx_timeout,
355 .ndo_change_mtu = eth_change_mtu,
356 .ndo_set_mac_address = eth_mac_addr,
357 .ndo_validate_addr = eth_validate_addr,
358};
1da177e4
LT		 359
360static int __devinit w840_probe1 (struct pci_dev *pdev,
361 const struct pci_device_id *ent)
362{
363 struct net_device *dev;
364 struct netdev_private *np;
365 static int find_cnt;
366 int chip_idx = ent->driver_data;
367 int irq;
368 int i, option = find_cnt < MAX_UNITS ? options[find_cnt] : 0;
369 void __iomem *ioaddr;
1da177e4
LT		 370
371 i = pci_enable_device(pdev);
372 if (i) return i;
373
374 pci_set_master(pdev);
375
376 irq = pdev->irq;
377
284901a9 378 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
a1e37bc5
JP		 379 pr_warning("Winbond-840: Device %s disabled due to DMA limitations\n",
380 pci_name(pdev));
1da177e4
LT		 381 return -EIO;
382 }
383 dev = alloc_etherdev(sizeof(*np));
384 if (!dev)
385 return -ENOMEM;
1da177e4
LT		 386 SET_NETDEV_DEV(dev, &pdev->dev);
387
388 if (pci_request_regions(pdev, DRV_NAME))
389 goto err_out_netdev;
42eab567
GG		 390
391 ioaddr = pci_iomap(pdev, TULIP_BAR, netdev_res_size);
1da177e4
LT		 392 if (!ioaddr)
393 goto err_out_free_res;
394
395 for (i = 0; i < 3; i++)
c559a5bc 396 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(eeprom_read(ioaddr, i));
1da177e4
LT		 397
398 /* Reset the chip to erase previous misconfiguration.
399 No hold time required! */
400 iowrite32(0x00000001, ioaddr + PCIBusCfg);
401
402 dev->base_addr = (unsigned long)ioaddr;
403 dev->irq = irq;
404
405 np = netdev_priv(dev);
406 np->pci_dev = pdev;
407 np->chip_id = chip_idx;
408 np->drv_flags = pci_id_tbl[chip_idx].drv_flags;
409 spin_lock_init(&np->lock);
410 np->mii_if.dev = dev;
411 np->mii_if.mdio_read = mdio_read;
412 np->mii_if.mdio_write = mdio_write;
413 np->base_addr = ioaddr;
f3b197ac 414
1da177e4
LT		 415 pci_set_drvdata(pdev, dev);
416
417 if (dev->mem_start)
418 option = dev->mem_start;
419
420 /* The lower four bits are the media type. */
421 if (option > 0) {
422 if (option & 0x200)
423 np->mii_if.full_duplex = 1;
424 if (option & 15)
a1e37bc5
JP		 425 dev_info(&dev->dev,
426 "ignoring user supplied media type %d",
427 option & 15);
1da177e4
LT		 428 }
429 if (find_cnt < MAX_UNITS && full_duplex[find_cnt] > 0)
430 np->mii_if.full_duplex = 1;
431
432 if (np->mii_if.full_duplex)
433 np->mii_if.force_media = 1;
434
435 /* The chip-specific entries in the device structure. */
2a97e6b7 436 dev->netdev_ops = &netdev_ops;
1da177e4 437 dev->ethtool_ops = &netdev_ethtool_ops;
1da177e4
LT		 438 dev->watchdog_timeo = TX_TIMEOUT;
439
440 i = register_netdev(dev);
441 if (i)
442 goto err_out_cleardev;
443
a1e37bc5
JP		 444 dev_info(&dev->dev, "%s at %p, %pM, IRQ %d\n",
445 pci_id_tbl[chip_idx].name, ioaddr, dev->dev_addr, irq);
1da177e4
LT		 446
447 if (np->drv_flags & CanHaveMII) {
448 int phy, phy_idx = 0;
449 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
450 int mii_status = mdio_read(dev, phy, MII_BMSR);
451 if (mii_status != 0xffff && mii_status != 0x0000) {
452 np->phys[phy_idx++] = phy;
453 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
454 np->mii = (mdio_read(dev, phy, MII_PHYSID1) << 16)+
455 mdio_read(dev, phy, MII_PHYSID2);
a1e37bc5
JP		 456 dev_info(&dev->dev,
457 "MII PHY %08xh found at address %d, status 0x%04x advertising %04x\n",
458 np->mii, phy, mii_status,
459 np->mii_if.advertising);
1da177e4
LT		 460 }
461 }
462 np->mii_cnt = phy_idx;
463 np->mii_if.phy_id = np->phys[0];
464 if (phy_idx == 0) {
a1e37bc5
JP		 465 dev_warn(&dev->dev,
466 "MII PHY not found -- this device may not operate correctly\n");
1da177e4
LT		 467 }
468 }
469
470 find_cnt++;
471 return 0;
472
473err_out_cleardev:
474 pci_set_drvdata(pdev, NULL);
475 pci_iounmap(pdev, ioaddr);
476err_out_free_res:
477 pci_release_regions(pdev);
478err_out_netdev:
479 free_netdev (dev);
480 return -ENODEV;
481}
482
f3b197ac 483
1da177e4
LT		 484/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. These are
485 often serial bit streams generated by the host processor.
486 The example below is for the common 93c46 EEPROM, 64 16 bit words. */
487
488/* Delay between EEPROM clock transitions.
489 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need
490 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that
491 made udelay() unreliable.
492 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is
405bbe9f 493 deprecated.
1da177e4
LT		 494*/
495#define eeprom_delay(ee_addr) ioread32(ee_addr)
496
497enum EEPROM_Ctrl_Bits {
498 EE_ShiftClk=0x02, EE_Write0=0x801, EE_Write1=0x805,
499 EE_ChipSelect=0x801, EE_DataIn=0x08,
500};
501
502/* The EEPROM commands include the alway-set leading bit. */
503enum EEPROM_Cmds {
504 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6),
505};
506
507static int eeprom_read(void __iomem *addr, int location)
508{
509 int i;
510 int retval = 0;
511 void __iomem *ee_addr = addr + EECtrl;
512 int read_cmd = location | EE_ReadCmd;
513 iowrite32(EE_ChipSelect, ee_addr);
514
515 /* Shift the read command bits out. */
516 for (i = 10; i >= 0; i--) {
517 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0;
518 iowrite32(dataval, ee_addr);
519 eeprom_delay(ee_addr);
520 iowrite32(dataval | EE_ShiftClk, ee_addr);
521 eeprom_delay(ee_addr);
522 }
523 iowrite32(EE_ChipSelect, ee_addr);
524 eeprom_delay(ee_addr);
525
526 for (i = 16; i > 0; i--) {
527 iowrite32(EE_ChipSelect | EE_ShiftClk, ee_addr);
528 eeprom_delay(ee_addr);
529 retval = (retval << 1) | ((ioread32(ee_addr) & EE_DataIn) ? 1 : 0);
530 iowrite32(EE_ChipSelect, ee_addr);
531 eeprom_delay(ee_addr);
532 }
533
534 /* Terminate the EEPROM access. */
535 iowrite32(0, ee_addr);
536 return retval;
537}
538
539/* MII transceiver control section.
540 Read and write the MII registers using software-generated serial
541 MDIO protocol. See the MII specifications or DP83840A data sheet
542 for details.
543
544 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
545 met by back-to-back 33Mhz PCI cycles. */
546#define mdio_delay(mdio_addr) ioread32(mdio_addr)
547
548/* Set iff a MII transceiver on any interface requires mdio preamble.
549 This only set with older transceivers, so the extra
550 code size of a per-interface flag is not worthwhile. */
551static char mii_preamble_required = 1;
552
553#define MDIO_WRITE0 (MDIO_EnbOutput)
554#define MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput)
555
556/* Generate the preamble required for initial synchronization and
557 a few older transceivers. */
558static void mdio_sync(void __iomem *mdio_addr)
559{
560 int bits = 32;
561
562 /* Establish sync by sending at least 32 logic ones. */
563 while (--bits >= 0) {
564 iowrite32(MDIO_WRITE1, mdio_addr);
565 mdio_delay(mdio_addr);
566 iowrite32(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
567 mdio_delay(mdio_addr);
568 }
569}
570
571static int mdio_read(struct net_device *dev, int phy_id, int location)
572{
573 struct netdev_private *np = netdev_priv(dev);
574 void __iomem *mdio_addr = np->base_addr + MIICtrl;
575 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
576 int i, retval = 0;
577
578 if (mii_preamble_required)
579 mdio_sync(mdio_addr);
580
581 /* Shift the read command bits out. */
582 for (i = 15; i >= 0; i--) {
583 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
584
585 iowrite32(dataval, mdio_addr);
586 mdio_delay(mdio_addr);
587 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
588 mdio_delay(mdio_addr);
589 }
590 /* Read the two transition, 16 data, and wire-idle bits. */
591 for (i = 20; i > 0; i--) {
592 iowrite32(MDIO_EnbIn, mdio_addr);
593 mdio_delay(mdio_addr);
594 retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DataIn) ? 1 : 0);
595 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
596 mdio_delay(mdio_addr);
597 }
598 return (retval>>1) & 0xffff;
599}
600
601static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
602{
603 struct netdev_private *np = netdev_priv(dev);
604 void __iomem *mdio_addr = np->base_addr + MIICtrl;
605 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
606 int i;
607
608 if (location == 4 && phy_id == np->phys[0])
609 np->mii_if.advertising = value;
610
611 if (mii_preamble_required)
612 mdio_sync(mdio_addr);
613
614 /* Shift the command bits out. */
615 for (i = 31; i >= 0; i--) {
616 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
617
618 iowrite32(dataval, mdio_addr);
619 mdio_delay(mdio_addr);
620 iowrite32(dataval | MDIO_ShiftClk, mdio_addr);
621 mdio_delay(mdio_addr);
622 }
623 /* Clear out extra bits. */
624 for (i = 2; i > 0; i--) {
625 iowrite32(MDIO_EnbIn, mdio_addr);
626 mdio_delay(mdio_addr);
627 iowrite32(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
628 mdio_delay(mdio_addr);
629 }
630 return;
631}
632
f3b197ac 633
1da177e4
LT		 634static int netdev_open(struct net_device *dev)
635{
636 struct netdev_private *np = netdev_priv(dev);
637 void __iomem *ioaddr = np->base_addr;
638 int i;
639
640 iowrite32(0x00000001, ioaddr + PCIBusCfg); /* Reset */
641
642 netif_device_detach(dev);
a0607fd3 643 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 644 if (i)
645 goto out_err;
646
647 if (debug > 1)
a1e37bc5
JP		 648 printk(KERN_DEBUG "%s: w89c840_open() irq %d\n",
649 dev->name, dev->irq);
1da177e4
LT		 650
651 if((i=alloc_ringdesc(dev)))
652 goto out_err;
653
654 spin_lock_irq(&np->lock);
655 netif_device_attach(dev);
656 init_registers(dev);
657 spin_unlock_irq(&np->lock);
658
659 netif_start_queue(dev);
660 if (debug > 2)
a1e37bc5 661 printk(KERN_DEBUG "%s: Done netdev_open()\n", dev->name);
1da177e4
LT		 662
663 /* Set the timer to check for link beat. */
664 init_timer(&np->timer);
665 np->timer.expires = jiffies + 1*HZ;
666 np->timer.data = (unsigned long)dev;
667 np->timer.function = &netdev_timer; /* timer handler */
668 add_timer(&np->timer);
669 return 0;
670out_err:
671 netif_device_attach(dev);
672 return i;
673}
674
675#define MII_DAVICOM_DM9101 0x0181b800
676
677static int update_link(struct net_device *dev)
678{
679 struct netdev_private *np = netdev_priv(dev);
680 int duplex, fasteth, result, mii_reg;
681
682 /* BSMR */
683 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
684
685 if (mii_reg == 0xffff)
686 return np->csr6;
687 /* reread: the link status bit is sticky */
688 mii_reg = mdio_read(dev, np->phys[0], MII_BMSR);
689 if (!(mii_reg & 0x4)) {
690 if (netif_carrier_ok(dev)) {
691 if (debug)
a1e37bc5
JP		 692 dev_info(&dev->dev,
693 "MII #%d reports no link. Disabling watchdog\n",
694 np->phys[0]);
1da177e4
LT		 695 netif_carrier_off(dev);
696 }
697 return np->csr6;
698 }
699 if (!netif_carrier_ok(dev)) {
700 if (debug)
a1e37bc5
JP		 701 dev_info(&dev->dev,
702 "MII #%d link is back. Enabling watchdog\n",
703 np->phys[0]);
1da177e4
LT		 704 netif_carrier_on(dev);
705 }
f3b197ac 706
1da177e4
LT		 707 if ((np->mii & ~0xf) == MII_DAVICOM_DM9101) {
708 /* If the link partner doesn't support autonegotiation
709 * the MII detects it's abilities with the "parallel detection".
710 * Some MIIs update the LPA register to the result of the parallel
711 * detection, some don't.
712 * The Davicom PHY [at least 0181b800] doesn't.
713 * Instead bit 9 and 13 of the BMCR are updated to the result
714 * of the negotiation..
715 */
716 mii_reg = mdio_read(dev, np->phys[0], MII_BMCR);
717 duplex = mii_reg & BMCR_FULLDPLX;
718 fasteth = mii_reg & BMCR_SPEED100;
719 } else {
720 int negotiated;
721 mii_reg = mdio_read(dev, np->phys[0], MII_LPA);
722 negotiated = mii_reg & np->mii_if.advertising;
723
724 duplex = (negotiated & LPA_100FULL) || ((negotiated & 0x02C0) == LPA_10FULL);
725 fasteth = negotiated & 0x380;
726 }
727 duplex |= np->mii_if.force_media;
728 /* remove fastether and fullduplex */
729 result = np->csr6 & ~0x20000200;
730 if (duplex)
731 result |= 0x200;
732 if (fasteth)
733 result |= 0x20000000;
734 if (result != np->csr6 && debug)
a1e37bc5
JP		 735 dev_info(&dev->dev,
736 "Setting %dMBit-%s-duplex based on MII#%d\n",
737 fasteth ? 100 : 10, duplex ? "full" : "half",
738 np->phys[0]);
1da177e4
LT		 739 return result;
740}
741
742#define RXTX_TIMEOUT 2000
743static inline void update_csr6(struct net_device *dev, int new)
744{
745 struct netdev_private *np = netdev_priv(dev);
746 void __iomem *ioaddr = np->base_addr;
747 int limit = RXTX_TIMEOUT;
748
749 if (!netif_device_present(dev))
750 new = 0;
751 if (new==np->csr6)
752 return;
753 /* stop both Tx and Rx processes */
754 iowrite32(np->csr6 & ~0x2002, ioaddr + NetworkConfig);
755 /* wait until they have really stopped */
756 for (;;) {
757 int csr5 = ioread32(ioaddr + IntrStatus);
758 int t;
759
760 t = (csr5 >> 17) & 0x07;
761 if (t==0||t==1) {
762 /* rx stopped */
763 t = (csr5 >> 20) & 0x07;
764 if (t==0||t==1)
765 break;
766 }
767
768 limit--;
769 if(!limit) {
a1e37bc5
JP		 770 dev_info(&dev->dev,
771 "couldn't stop rxtx, IntrStatus %xh\n", csr5);
1da177e4
LT		 772 break;
773 }
774 udelay(1);
775 }
776 np->csr6 = new;
777 /* and restart them with the new configuration */
778 iowrite32(np->csr6, ioaddr + NetworkConfig);
779 if (new & 0x200)
780 np->mii_if.full_duplex = 1;
781}
782
783static void netdev_timer(unsigned long data)
784{
785 struct net_device *dev = (struct net_device *)data;
786 struct netdev_private *np = netdev_priv(dev);
787 void __iomem *ioaddr = np->base_addr;
788
789 if (debug > 2)
a1e37bc5
JP		 790 printk(KERN_DEBUG "%s: Media selection timer tick, status %08x config %08x\n",
791 dev->name, ioread32(ioaddr + IntrStatus),
792 ioread32(ioaddr + NetworkConfig));
1da177e4
LT		 793 spin_lock_irq(&np->lock);
794 update_csr6(dev, update_link(dev));
795 spin_unlock_irq(&np->lock);
796 np->timer.expires = jiffies + 10*HZ;
797 add_timer(&np->timer);
798}
799
800static void init_rxtx_rings(struct net_device *dev)
801{
802 struct netdev_private *np = netdev_priv(dev);
803 int i;
804
805 np->rx_head_desc = &np->rx_ring[0];
806 np->tx_ring = (struct w840_tx_desc*)&np->rx_ring[RX_RING_SIZE];
807
808 /* Initial all Rx descriptors. */
809 for (i = 0; i < RX_RING_SIZE; i++) {
810 np->rx_ring[i].length = np->rx_buf_sz;
811 np->rx_ring[i].status = 0;
812 np->rx_skbuff[i] = NULL;
813 }
814 /* Mark the last entry as wrapping the ring. */
815 np->rx_ring[i-1].length |= DescEndRing;
816
817 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
818 for (i = 0; i < RX_RING_SIZE; i++) {
819 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
820 np->rx_skbuff[i] = skb;
821 if (skb == NULL)
822 break;
689be439 823 np->rx_addr[i] = pci_map_single(np->pci_dev,skb->data,
bb02aacc 824 np->rx_buf_sz,PCI_DMA_FROMDEVICE);
1da177e4
LT		 825
826 np->rx_ring[i].buffer1 = np->rx_addr[i];
42eab567 827 np->rx_ring[i].status = DescOwned;
1da177e4
LT		 828 }
829
830 np->cur_rx = 0;
831 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
832
833 /* Initialize the Tx descriptors */
834 for (i = 0; i < TX_RING_SIZE; i++) {
835 np->tx_skbuff[i] = NULL;
836 np->tx_ring[i].status = 0;
837 }
838 np->tx_full = 0;
839 np->tx_q_bytes = np->dirty_tx = np->cur_tx = 0;
840
841 iowrite32(np->ring_dma_addr, np->base_addr + RxRingPtr);
842 iowrite32(np->ring_dma_addr+sizeof(struct w840_rx_desc)*RX_RING_SIZE,
843 np->base_addr + TxRingPtr);
844
845}
846
847static void free_rxtx_rings(struct netdev_private* np)
848{
849 int i;
850 /* Free all the skbuffs in the Rx queue. */
851 for (i = 0; i < RX_RING_SIZE; i++) {
852 np->rx_ring[i].status = 0;
853 if (np->rx_skbuff[i]) {
854 pci_unmap_single(np->pci_dev,
855 np->rx_addr[i],
856 np->rx_skbuff[i]->len,
857 PCI_DMA_FROMDEVICE);
858 dev_kfree_skb(np->rx_skbuff[i]);
859 }
860 np->rx_skbuff[i] = NULL;
861 }
862 for (i = 0; i < TX_RING_SIZE; i++) {
863 if (np->tx_skbuff[i]) {
864 pci_unmap_single(np->pci_dev,
865 np->tx_addr[i],
866 np->tx_skbuff[i]->len,
867 PCI_DMA_TODEVICE);
868 dev_kfree_skb(np->tx_skbuff[i]);
869 }
870 np->tx_skbuff[i] = NULL;
871 }
872}
873
874static void init_registers(struct net_device *dev)
875{
876 struct netdev_private *np = netdev_priv(dev);
877 void __iomem *ioaddr = np->base_addr;
878 int i;
879
880 for (i = 0; i < 6; i++)
881 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
882
883 /* Initialize other registers. */
884#ifdef __BIG_ENDIAN
885 i = (1<<20); /* Big-endian descriptors */
886#else
887 i = 0;
888#endif
889 i |= (0x04<<2); /* skip length 4 u32 */
890 i |= 0x02; /* give Rx priority */
891
892 /* Configure the PCI bus bursts and FIFO thresholds.
893 486: Set 8 longword cache alignment, 8 longword burst.
894 586: Set 16 longword cache alignment, no burst limit.
895 Cache alignment bits 15:14 Burst length 13:8
896 0000 <not allowed> 0000 align to cache 0800 8 longwords
897 4000 8 longwords 0100 1 longword 1000 16 longwords
898 8000 16 longwords 0200 2 longwords 2000 32 longwords
899 C000 32 longwords 0400 4 longwords */
900
901#if defined (__i386__) && !defined(MODULE)
902 /* When not a module we can work around broken '486 PCI boards. */
903 if (boot_cpu_data.x86 <= 4) {
904 i |= 0x4800;
a1e37bc5
JP		 905 dev_info(&dev->dev,
906 "This is a 386/486 PCI system, setting cache alignment to 8 longwords\n");
1da177e4
LT		 907 } else {
908 i |= 0xE000;
909 }
910#elif defined(__powerpc__) || defined(__i386__) || defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)
911 i |= 0xE000;
49345103 912#elif defined(CONFIG_SPARC) || defined (CONFIG_PARISC)
1da177e4
LT		 913 i |= 0x4800;
914#else
915#warning Processor architecture undefined
916 i |= 0x4800;
917#endif
918 iowrite32(i, ioaddr + PCIBusCfg);
919
920 np->csr6 = 0;
f3b197ac 921 /* 128 byte Tx threshold;
1da177e4
LT		 922 Transmit on; Receive on; */
923 update_csr6(dev, 0x00022002 | update_link(dev) | __set_rx_mode(dev));
924
925 /* Clear and Enable interrupts by setting the interrupt mask. */
926 iowrite32(0x1A0F5, ioaddr + IntrStatus);
927 iowrite32(0x1A0F5, ioaddr + IntrEnable);
928
929 iowrite32(0, ioaddr + RxStartDemand);
930}
931
932static void tx_timeout(struct net_device *dev)
933{
934 struct netdev_private *np = netdev_priv(dev);
935 void __iomem *ioaddr = np->base_addr;
936
a1e37bc5
JP		 937 dev_warn(&dev->dev, "Transmit timed out, status %08x, resetting...\n",
938 ioread32(ioaddr + IntrStatus));
1da177e4
LT		 939
940 {
941 int i;
942 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
943 for (i = 0; i < RX_RING_SIZE; i++)
a1e37bc5
JP		 944 printk(KERN_CONT " %08x", (unsigned int)np->rx_ring[i].status);
945 printk(KERN_CONT "\n");
946 printk(KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1da177e4 947 for (i = 0; i < TX_RING_SIZE; i++)
a1e37bc5
JP		 948 printk(KERN_CONT " %08x", np->tx_ring[i].status);
949 printk(KERN_CONT "\n");
1da177e4 950 }
a1e37bc5
JP		 951 printk(KERN_DEBUG "Tx cur %d Tx dirty %d Tx Full %d, q bytes %d\n",
952 np->cur_tx, np->dirty_tx, np->tx_full, np->tx_q_bytes);
953 printk(KERN_DEBUG "Tx Descriptor addr %xh\n", ioread32(ioaddr+0x4C));
1da177e4
LT		 954
955 disable_irq(dev->irq);
956 spin_lock_irq(&np->lock);
957 /*
958 * Under high load dirty_tx and the internal tx descriptor pointer
959 * come out of sync, thus perform a software reset and reinitialize
960 * everything.
961 */
962
963 iowrite32(1, np->base_addr+PCIBusCfg);
964 udelay(1);
965
966 free_rxtx_rings(np);
967 init_rxtx_rings(dev);
968 init_registers(dev);
969 spin_unlock_irq(&np->lock);
970 enable_irq(dev->irq);
971
972 netif_wake_queue(dev);
973 dev->trans_start = jiffies;
974 np->stats.tx_errors++;
975 return;
976}
977
978/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
979static int alloc_ringdesc(struct net_device *dev)
980{
981 struct netdev_private *np = netdev_priv(dev);
982
983 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
984
985 np->rx_ring = pci_alloc_consistent(np->pci_dev,
986 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
987 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
988 &np->ring_dma_addr);
989 if(!np->rx_ring)
990 return -ENOMEM;
991 init_rxtx_rings(dev);
992 return 0;
993}
994
995static void free_ringdesc(struct netdev_private *np)
996{
997 pci_free_consistent(np->pci_dev,
998 sizeof(struct w840_rx_desc)*RX_RING_SIZE +
999 sizeof(struct w840_tx_desc)*TX_RING_SIZE,
1000 np->rx_ring, np->ring_dma_addr);
1001
1002}
1003
ad096463 1004static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev)
1da177e4
LT		 1005{
1006 struct netdev_private *np = netdev_priv(dev);
1007 unsigned entry;
1008
1009 /* Caution: the write order is important here, set the field
1010 with the "ownership" bits last. */
1011
1012 /* Calculate the next Tx descriptor entry. */
1013 entry = np->cur_tx % TX_RING_SIZE;
1014
1015 np->tx_addr[entry] = pci_map_single(np->pci_dev,
1016 skb->data,skb->len, PCI_DMA_TODEVICE);
1017 np->tx_skbuff[entry] = skb;
1018
1019 np->tx_ring[entry].buffer1 = np->tx_addr[entry];
1020 if (skb->len < TX_BUFLIMIT) {
1021 np->tx_ring[entry].length = DescWholePkt | skb->len;
1022 } else {
1023 int len = skb->len - TX_BUFLIMIT;
1024
1025 np->tx_ring[entry].buffer2 = np->tx_addr[entry]+TX_BUFLIMIT;
1026 np->tx_ring[entry].length = DescWholePkt | (len << 11) | TX_BUFLIMIT;
1027 }
1028 if(entry == TX_RING_SIZE-1)
1029 np->tx_ring[entry].length |= DescEndRing;
1030
1031 /* Now acquire the irq spinlock.
59c51591 1032 * The difficult race is the ordering between
42eab567 1033 * increasing np->cur_tx and setting DescOwned:
1da177e4
LT		 1034 * - if np->cur_tx is increased first the interrupt
1035 * handler could consider the packet as transmitted
42eab567
GG		 1036 * since DescOwned is cleared.
1037 * - If DescOwned is set first the NIC could report the
1da177e4
LT		 1038 * packet as sent, but the interrupt handler would ignore it
1039 * since the np->cur_tx was not yet increased.
1040 */
1041 spin_lock_irq(&np->lock);
1042 np->cur_tx++;
1043
1044 wmb(); /* flush length, buffer1, buffer2 */
42eab567 1045 np->tx_ring[entry].status = DescOwned;
1da177e4
LT		 1046 wmb(); /* flush status and kick the hardware */
1047 iowrite32(0, np->base_addr + TxStartDemand);
1048 np->tx_q_bytes += skb->len;
1049 /* Work around horrible bug in the chip by marking the queue as full
1050 when we do not have FIFO room for a maximum sized packet. */
1051 if (np->cur_tx - np->dirty_tx > TX_QUEUE_LEN ||
1052 ((np->drv_flags & HasBrokenTx) && np->tx_q_bytes > TX_BUG_FIFO_LIMIT)) {
1053 netif_stop_queue(dev);
1054 wmb();
1055 np->tx_full = 1;
1056 }
1057 spin_unlock_irq(&np->lock);
1058
1059 dev->trans_start = jiffies;
1060
1061 if (debug > 4) {
a1e37bc5
JP		 1062 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d\n",
1063 dev->name, np->cur_tx, entry);
1da177e4 1064 }
6ed10654 1065 return NETDEV_TX_OK;
1da177e4
LT		 1066}
1067
1068static void netdev_tx_done(struct net_device *dev)
1069{
1070 struct netdev_private *np = netdev_priv(dev);
1071 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1072 int entry = np->dirty_tx % TX_RING_SIZE;
1073 int tx_status = np->tx_ring[entry].status;
1074
1075 if (tx_status < 0)
1076 break;
1077 if (tx_status & 0x8000) { /* There was an error, log it. */
1078#ifndef final_version
1079 if (debug > 1)
a1e37bc5
JP		 1080 printk(KERN_DEBUG "%s: Transmit error, Tx status %08x\n",
1081 dev->name, tx_status);
1da177e4
LT		 1082#endif
1083 np->stats.tx_errors++;
1084 if (tx_status & 0x0104) np->stats.tx_aborted_errors++;
1085 if (tx_status & 0x0C80) np->stats.tx_carrier_errors++;
1086 if (tx_status & 0x0200) np->stats.tx_window_errors++;
1087 if (tx_status & 0x0002) np->stats.tx_fifo_errors++;
1088 if ((tx_status & 0x0080) && np->mii_if.full_duplex == 0)
1089 np->stats.tx_heartbeat_errors++;
1090 } else {
1091#ifndef final_version
1092 if (debug > 3)
a1e37bc5
JP		 1093 printk(KERN_DEBUG "%s: Transmit slot %d ok, Tx status %08x\n",
1094 dev->name, entry, tx_status);
1da177e4
LT		 1095#endif
1096 np->stats.tx_bytes += np->tx_skbuff[entry]->len;
1097 np->stats.collisions += (tx_status >> 3) & 15;
1098 np->stats.tx_packets++;
1099 }
1100 /* Free the original skb. */
1101 pci_unmap_single(np->pci_dev,np->tx_addr[entry],
1102 np->tx_skbuff[entry]->len,
1103 PCI_DMA_TODEVICE);
1104 np->tx_q_bytes -= np->tx_skbuff[entry]->len;
1105 dev_kfree_skb_irq(np->tx_skbuff[entry]);
1106 np->tx_skbuff[entry] = NULL;
1107 }
1108 if (np->tx_full &&
1109 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN_RESTART &&
1110 np->tx_q_bytes < TX_BUG_FIFO_LIMIT) {
1111 /* The ring is no longer full, clear tbusy. */
1112 np->tx_full = 0;
1113 wmb();
1114 netif_wake_queue(dev);
1115 }
1116}
1117
1118/* The interrupt handler does all of the Rx thread work and cleans up
1119 after the Tx thread. */
7d12e780 1120static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1121{
1122 struct net_device *dev = (struct net_device *)dev_instance;
1123 struct netdev_private *np = netdev_priv(dev);
1124 void __iomem *ioaddr = np->base_addr;
1125 int work_limit = max_interrupt_work;
1126 int handled = 0;
1127
1128 if (!netif_device_present(dev))
1129 return IRQ_NONE;
1130 do {
1131 u32 intr_status = ioread32(ioaddr + IntrStatus);
1132
1133 /* Acknowledge all of the current interrupt sources ASAP. */
1134 iowrite32(intr_status & 0x001ffff, ioaddr + IntrStatus);
1135
1136 if (debug > 4)
a1e37bc5
JP		 1137 printk(KERN_DEBUG "%s: Interrupt, status %04x\n",
1138 dev->name, intr_status);
1da177e4
LT		 1139
1140 if ((intr_status & (NormalIntr|AbnormalIntr)) == 0)
1141 break;
1142
1143 handled = 1;
1144
42eab567 1145 if (intr_status & (RxIntr | RxNoBuf))
1da177e4
LT		 1146 netdev_rx(dev);
1147 if (intr_status & RxNoBuf)
1148 iowrite32(0, ioaddr + RxStartDemand);
1149
42eab567 1150 if (intr_status & (TxNoBuf | TxIntr) &&
1da177e4
LT		 1151 np->cur_tx != np->dirty_tx) {
1152 spin_lock(&np->lock);
1153 netdev_tx_done(dev);
1154 spin_unlock(&np->lock);
1155 }
1156
1157 /* Abnormal error summary/uncommon events handlers. */
1ddb9861 1158 if (intr_status & (AbnormalIntr | TxFIFOUnderflow | SystemError |
42eab567 1159 TimerInt | TxDied))
1da177e4
LT		 1160 netdev_error(dev, intr_status);
1161
1162 if (--work_limit < 0) {
a1e37bc5
JP		 1163 dev_warn(&dev->dev,
1164 "Too much work at interrupt, status=0x%04x\n",
1165 intr_status);
1da177e4
LT		 1166 /* Set the timer to re-enable the other interrupts after
1167 10*82usec ticks. */
1168 spin_lock(&np->lock);
1169 if (netif_device_present(dev)) {
1170 iowrite32(AbnormalIntr | TimerInt, ioaddr + IntrEnable);
1171 iowrite32(10, ioaddr + GPTimer);
1172 }
1173 spin_unlock(&np->lock);
1174 break;
1175 }
1176 } while (1);
1177
1178 if (debug > 3)
a1e37bc5
JP		 1179 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x\n",
1180 dev->name, ioread32(ioaddr + IntrStatus));
1da177e4
LT		 1181 return IRQ_RETVAL(handled);
1182}
1183
1184/* This routine is logically part of the interrupt handler, but separated
1185 for clarity and better register allocation. */
1186static int netdev_rx(struct net_device *dev)
1187{
1188 struct netdev_private *np = netdev_priv(dev);
1189 int entry = np->cur_rx % RX_RING_SIZE;
1190 int work_limit = np->dirty_rx + RX_RING_SIZE - np->cur_rx;
1191
1192 if (debug > 4) {
a1e37bc5
JP		 1193 printk(KERN_DEBUG " In netdev_rx(), entry %d status %04x\n",
1194 entry, np->rx_ring[entry].status);
1da177e4
LT		 1195 }
1196
1197 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1198 while (--work_limit >= 0) {
1199 struct w840_rx_desc *desc = np->rx_head_desc;
1200 s32 status = desc->status;
1201
1202 if (debug > 4)
a1e37bc5
JP		 1203 printk(KERN_DEBUG " netdev_rx() status was %08x\n",
1204 status);
1da177e4
LT		 1205 if (status < 0)
1206 break;
1207 if ((status & 0x38008300) != 0x0300) {
1208 if ((status & 0x38000300) != 0x0300) {
1209 /* Ingore earlier buffers. */
1210 if ((status & 0xffff) != 0x7fff) {
a1e37bc5
JP		 1211 dev_warn(&dev->dev,
1212 "Oversized Ethernet frame spanned multiple buffers, entry %#x status %04x!\n",
1213 np->cur_rx, status);
1da177e4
LT		 1214 np->stats.rx_length_errors++;
1215 }
1216 } else if (status & 0x8000) {
1217 /* There was a fatal error. */
1218 if (debug > 2)
a1e37bc5
JP		 1219 printk(KERN_DEBUG "%s: Receive error, Rx status %08x\n",
1220 dev->name, status);
1da177e4
LT		 1221 np->stats.rx_errors++; /* end of a packet.*/
1222 if (status & 0x0890) np->stats.rx_length_errors++;
1223 if (status & 0x004C) np->stats.rx_frame_errors++;
1224 if (status & 0x0002) np->stats.rx_crc_errors++;
1225 }
1226 } else {
1227 struct sk_buff *skb;
1228 /* Omit the four octet CRC from the length. */
1229 int pkt_len = ((status >> 16) & 0x7ff) - 4;
1230
1231#ifndef final_version
1232 if (debug > 4)
a1e37bc5
JP		 1233 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d status %x\n",
1234 pkt_len, status);
1da177e4
LT		 1235#endif
1236 /* Check if the packet is long enough to accept without copying
1237 to a minimally-sized skbuff. */
8e95a202
JP		 1238 if (pkt_len < rx_copybreak &&
1239 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4
LT		 1240 skb_reserve(skb, 2); /* 16 byte align the IP header */
1241 pci_dma_sync_single_for_cpu(np->pci_dev,np->rx_addr[entry],
1242 np->rx_skbuff[entry]->len,
1243 PCI_DMA_FROMDEVICE);
8c7b7faa 1244 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1da177e4
LT		 1245 skb_put(skb, pkt_len);
1246 pci_dma_sync_single_for_device(np->pci_dev,np->rx_addr[entry],
1247 np->rx_skbuff[entry]->len,
1248 PCI_DMA_FROMDEVICE);
1249 } else {
1250 pci_unmap_single(np->pci_dev,np->rx_addr[entry],
1251 np->rx_skbuff[entry]->len,
1252 PCI_DMA_FROMDEVICE);
1253 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1254 np->rx_skbuff[entry] = NULL;
1255 }
1256#ifndef final_version /* Remove after testing. */
1257 /* You will want this info for the initial debug. */
e174961c 1258 if (debug > 5)
a1e37bc5 1259 printk(KERN_DEBUG " Rx data %pM %pM %02x%02x %pI4\n",
e174961c 1260 &skb->data[0], &skb->data[6],
0795af57 1261 skb->data[12], skb->data[13],
a1e37bc5 1262 &skb->data[14]);
1da177e4
LT		 1263#endif
1264 skb->protocol = eth_type_trans(skb, dev);
1265 netif_rx(skb);
1da177e4
LT		 1266 np->stats.rx_packets++;
1267 np->stats.rx_bytes += pkt_len;
1268 }
1269 entry = (++np->cur_rx) % RX_RING_SIZE;
1270 np->rx_head_desc = &np->rx_ring[entry];
1271 }
1272
1273 /* Refill the Rx ring buffers. */
1274 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1275 struct sk_buff *skb;
1276 entry = np->dirty_rx % RX_RING_SIZE;
1277 if (np->rx_skbuff[entry] == NULL) {
1278 skb = dev_alloc_skb(np->rx_buf_sz);
1279 np->rx_skbuff[entry] = skb;
1280 if (skb == NULL)
1281 break; /* Better luck next round. */
1da177e4 1282 np->rx_addr[entry] = pci_map_single(np->pci_dev,
689be439 1283 skb->data,
bb02aacc 1284 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1da177e4
LT		 1285 np->rx_ring[entry].buffer1 = np->rx_addr[entry];
1286 }
1287 wmb();
42eab567 1288 np->rx_ring[entry].status = DescOwned;
1da177e4
LT		 1289 }
1290
1291 return 0;
1292}
1293
1294static void netdev_error(struct net_device *dev, int intr_status)
1295{
1296 struct netdev_private *np = netdev_priv(dev);
1297 void __iomem *ioaddr = np->base_addr;
1298
1299 if (debug > 2)
a1e37bc5
JP		 1300 printk(KERN_DEBUG "%s: Abnormal event, %08x\n",
1301 dev->name, intr_status);
1da177e4
LT		 1302 if (intr_status == 0xffffffff)
1303 return;
1304 spin_lock(&np->lock);
1305 if (intr_status & TxFIFOUnderflow) {
1306 int new;
1307 /* Bump up the Tx threshold */
1308#if 0
1309 /* This causes lots of dropped packets,
1310 * and under high load even tx_timeouts
1311 */
1312 new = np->csr6 + 0x4000;
1313#else
1314 new = (np->csr6 >> 14)&0x7f;
1315 if (new < 64)
1316 new *= 2;
1317 else
1318 new = 127; /* load full packet before starting */
1319 new = (np->csr6 & ~(0x7F << 14)) | (new<<14);
1320#endif
a1e37bc5
JP		 1321 printk(KERN_DEBUG "%s: Tx underflow, new csr6 %08x\n",
1322 dev->name, new);
1da177e4
LT		 1323 update_csr6(dev, new);
1324 }
42eab567 1325 if (intr_status & RxDied) { /* Missed a Rx frame. */
1da177e4
LT		 1326 np->stats.rx_errors++;
1327 }
1328 if (intr_status & TimerInt) {
1329 /* Re-enable other interrupts. */
1330 if (netif_device_present(dev))
1331 iowrite32(0x1A0F5, ioaddr + IntrEnable);
1332 }
1333 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1334 iowrite32(0, ioaddr + RxStartDemand);
1335 spin_unlock(&np->lock);
1336}
1337
1338static struct net_device_stats *get_stats(struct net_device *dev)
1339{
1340 struct netdev_private *np = netdev_priv(dev);
1341 void __iomem *ioaddr = np->base_addr;
1342
1343 /* The chip only need report frame silently dropped. */
1344 spin_lock_irq(&np->lock);
1345 if (netif_running(dev) && netif_device_present(dev))
1346 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1347 spin_unlock_irq(&np->lock);
1348
1349 return &np->stats;
1350}
1351
1352
1353static u32 __set_rx_mode(struct net_device *dev)
1354{
1355 struct netdev_private *np = netdev_priv(dev);
1356 void __iomem *ioaddr = np->base_addr;
1357 u32 mc_filter[2]; /* Multicast hash filter */
1358 u32 rx_mode;
1359
1360 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4 1361 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1362 rx_mode = RxAcceptBroadcast | AcceptMulticast | RxAcceptAllPhys
1da177e4 1363 | AcceptMyPhys;
4cd24eaf 1364 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 1365 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1366 /* Too many to match, or accept all multicasts. */
1367 memset(mc_filter, 0xff, sizeof(mc_filter));
42eab567 1368 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4 1369 } else {
22bedad3 1370 struct netdev_hw_addr *ha;
4302b67e 1371
1da177e4 1372 memset(mc_filter, 0, sizeof(mc_filter));
22bedad3
JP		 1373 netdev_for_each_mc_addr(ha, dev) {
1374 int filbit;
1375
1376 filbit = (ether_crc(ETH_ALEN, ha->addr) >> 26) ^ 0x3F;
1377 filbit &= 0x3f;
1378 mc_filter[filbit >> 5] |= 1 << (filbit & 31);
1da177e4 1379 }
42eab567 1380 rx_mode = RxAcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1da177e4
LT		 1381 }
1382 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1383 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1384 return rx_mode;
1385}
1386
1387static void set_rx_mode(struct net_device *dev)
1388{
1389 struct netdev_private *np = netdev_priv(dev);
1390 u32 rx_mode = __set_rx_mode(dev);
1391 spin_lock_irq(&np->lock);
1392 update_csr6(dev, (np->csr6 & ~0x00F8) | rx_mode);
1393 spin_unlock_irq(&np->lock);
1394}
1395
1396static void netdev_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1397{
1398 struct netdev_private *np = netdev_priv(dev);
1399
1400 strcpy (info->driver, DRV_NAME);
1401 strcpy (info->version, DRV_VERSION);
1402 strcpy (info->bus_info, pci_name(np->pci_dev));
1403}
1404
1405static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1406{
1407 struct netdev_private *np = netdev_priv(dev);
1408 int rc;
1409
1410 spin_lock_irq(&np->lock);
1411 rc = mii_ethtool_gset(&np->mii_if, cmd);
1412 spin_unlock_irq(&np->lock);
1413
1414 return rc;
1415}
1416
1417static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1418{
1419 struct netdev_private *np = netdev_priv(dev);
1420 int rc;
1421
1422 spin_lock_irq(&np->lock);
1423 rc = mii_ethtool_sset(&np->mii_if, cmd);
1424 spin_unlock_irq(&np->lock);
1425
1426 return rc;
1427}
1428
1429static int netdev_nway_reset(struct net_device *dev)
1430{
1431 struct netdev_private *np = netdev_priv(dev);
1432 return mii_nway_restart(&np->mii_if);
1433}
1434
1435static u32 netdev_get_link(struct net_device *dev)
1436{
1437 struct netdev_private *np = netdev_priv(dev);
1438 return mii_link_ok(&np->mii_if);
1439}
1440
1441static u32 netdev_get_msglevel(struct net_device *dev)
1442{
1443 return debug;
1444}
1445
1446static void netdev_set_msglevel(struct net_device *dev, u32 value)
1447{
1448 debug = value;
1449}
1450
7282d491 1451static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 1452 .get_drvinfo = netdev_get_drvinfo,
1453 .get_settings = netdev_get_settings,
1454 .set_settings = netdev_set_settings,
1455 .nway_reset = netdev_nway_reset,
1456 .get_link = netdev_get_link,
1457 .get_msglevel = netdev_get_msglevel,
1458 .set_msglevel = netdev_set_msglevel,
1da177e4
LT		 1459};
1460
1461static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1462{
1463 struct mii_ioctl_data *data = if_mii(rq);
1464 struct netdev_private *np = netdev_priv(dev);
1465
1466 switch(cmd) {
1467 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1468 data->phy_id = ((struct netdev_private *)netdev_priv(dev))->phys[0] & 0x1f;
1469 /* Fall Through */
1470
1471 case SIOCGMIIREG: /* Read MII PHY register. */
1472 spin_lock_irq(&np->lock);
1473 data->val_out = mdio_read(dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
1474 spin_unlock_irq(&np->lock);
1475 return 0;
1476
1477 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT		 1478 spin_lock_irq(&np->lock);
1479 mdio_write(dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
1480 spin_unlock_irq(&np->lock);
1481 return 0;
1482 default:
1483 return -EOPNOTSUPP;
1484 }
1485}
1486
1487static int netdev_close(struct net_device *dev)
1488{
1489 struct netdev_private *np = netdev_priv(dev);
1490 void __iomem *ioaddr = np->base_addr;
1491
1492 netif_stop_queue(dev);
1493
1494 if (debug > 1) {
a1e37bc5
JP		 1495 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %08x Config %08x\n",
1496 dev->name, ioread32(ioaddr + IntrStatus),
1497 ioread32(ioaddr + NetworkConfig));
1498 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d\n",
1499 dev->name,
1500 np->cur_tx, np->dirty_tx,
1501 np->cur_rx, np->dirty_rx);
1da177e4
LT		 1502 }
1503
1504 /* Stop the chip's Tx and Rx processes. */
1505 spin_lock_irq(&np->lock);
1506 netif_device_detach(dev);
1507 update_csr6(dev, 0);
1508 iowrite32(0x0000, ioaddr + IntrEnable);
1509 spin_unlock_irq(&np->lock);
1510
1511 free_irq(dev->irq, dev);
1512 wmb();
1513 netif_device_attach(dev);
1514
1515 if (ioread32(ioaddr + NetworkConfig) != 0xffffffff)
1516 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1517
1518#ifdef __i386__
1519 if (debug > 2) {
1520 int i;
1521
a1e37bc5 1522 printk(KERN_DEBUG" Tx ring at %08x:\n", (int)np->tx_ring);
1da177e4 1523 for (i = 0; i < TX_RING_SIZE; i++)
a1e37bc5
JP		 1524 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1525 i, np->tx_ring[i].length,
1526 np->tx_ring[i].status, np->tx_ring[i].buffer1);
1527 printk(KERN_DEBUG " Rx ring %08x:\n", (int)np->rx_ring);
1da177e4 1528 for (i = 0; i < RX_RING_SIZE; i++) {
a1e37bc5
JP		 1529 printk(KERN_DEBUG " #%d desc. %04x %04x %08x\n",
1530 i, np->rx_ring[i].length,
1531 np->rx_ring[i].status, np->rx_ring[i].buffer1);
1da177e4
LT		 1532 }
1533 }
1534#endif /* __i386__ debugging only */
1535
1536 del_timer_sync(&np->timer);
1537
1538 free_rxtx_rings(np);
1539 free_ringdesc(np);
1540
1541 return 0;
1542}
1543
1544static void __devexit w840_remove1 (struct pci_dev *pdev)
1545{
1546 struct net_device *dev = pci_get_drvdata(pdev);
f3b197ac 1547
1da177e4
LT		 1548 if (dev) {
1549 struct netdev_private *np = netdev_priv(dev);
1550 unregister_netdev(dev);
1551 pci_release_regions(pdev);
1552 pci_iounmap(pdev, np->base_addr);
1553 free_netdev(dev);
1554 }
1555
1556 pci_set_drvdata(pdev, NULL);
1557}
1558
1559#ifdef CONFIG_PM
1560
1561/*
1562 * suspend/resume synchronization:
1563 * - open, close, do_ioctl:
1564 * rtnl_lock, & netif_device_detach after the rtnl_unlock.
1565 * - get_stats:
1566 * spin_lock_irq(np->lock), doesn't touch hw if not present
2a97e6b7 1567 * - start_xmit:
932ff279 1568 * synchronize_irq + netif_tx_disable;
1da177e4 1569 * - tx_timeout:
932ff279 1570 * netif_device_detach + netif_tx_disable;
1da177e4 1571 * - set_multicast_list
932ff279 1572 * netif_device_detach + netif_tx_disable;
1da177e4
LT		 1573 * - interrupt handler
1574 * doesn't touch hw if not present, synchronize_irq waits for
1575 * running instances of the interrupt handler.
1576 *
1577 * Disabling hw requires clearing csr6 & IntrEnable.
1578 * update_csr6 & all function that write IntrEnable check netif_device_present
1579 * before settings any bits.
1580 *
1581 * Detach must occur under spin_unlock_irq(), interrupts from a detached
1582 * device would cause an irq storm.
1583 */
05adc3b7 1584static int w840_suspend (struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1585{
1586 struct net_device *dev = pci_get_drvdata (pdev);
1587 struct netdev_private *np = netdev_priv(dev);
1588 void __iomem *ioaddr = np->base_addr;
1589
1590 rtnl_lock();
1591 if (netif_running (dev)) {
1592 del_timer_sync(&np->timer);
1593
1594 spin_lock_irq(&np->lock);
1595 netif_device_detach(dev);
1596 update_csr6(dev, 0);
1597 iowrite32(0, ioaddr + IntrEnable);
1da177e4
LT		 1598 spin_unlock_irq(&np->lock);
1599
1da177e4 1600 synchronize_irq(dev->irq);
932ff279 1601 netif_tx_disable(dev);
6aa20a22 1602
1da177e4
LT		 1603 np->stats.rx_missed_errors += ioread32(ioaddr + RxMissed) & 0xffff;
1604
1605 /* no more hardware accesses behind this line. */
1606
0ee904c3 1607 BUG_ON(np->csr6 || ioread32(ioaddr + IntrEnable));
1da177e4
LT		 1608
1609 /* pci_power_off(pdev, -1); */
1610
1611 free_rxtx_rings(np);
1612 } else {
1613 netif_device_detach(dev);
1614 }
1615 rtnl_unlock();
1616 return 0;
1617}
1618
1619static int w840_resume (struct pci_dev *pdev)
1620{
1621 struct net_device *dev = pci_get_drvdata (pdev);
1622 struct netdev_private *np = netdev_priv(dev);
9f486ae1 1623 int retval = 0;
1da177e4
LT		 1624
1625 rtnl_lock();
1626 if (netif_device_present(dev))
1627 goto out; /* device not suspended */
1628 if (netif_running(dev)) {
9f486ae1 1629 if ((retval = pci_enable_device(pdev))) {
a1e37bc5
JP		 1630 dev_err(&dev->dev,
1631 "pci_enable_device failed in resume\n");
9f486ae1
VH		 1632 goto out;
1633 }
1da177e4
LT		 1634 spin_lock_irq(&np->lock);
1635 iowrite32(1, np->base_addr+PCIBusCfg);
1636 ioread32(np->base_addr+PCIBusCfg);
1637 udelay(1);
1638 netif_device_attach(dev);
1639 init_rxtx_rings(dev);
1640 init_registers(dev);
1641 spin_unlock_irq(&np->lock);
1642
1643 netif_wake_queue(dev);
1644
1645 mod_timer(&np->timer, jiffies + 1*HZ);
1646 } else {
1647 netif_device_attach(dev);
1648 }
1649out:
1650 rtnl_unlock();
9f486ae1 1651 return retval;
1da177e4
LT		 1652}
1653#endif
1654
1655static struct pci_driver w840_driver = {
1656 .name = DRV_NAME,
1657 .id_table = w840_pci_tbl,
1658 .probe = w840_probe1,
1659 .remove = __devexit_p(w840_remove1),
1660#ifdef CONFIG_PM
1661 .suspend = w840_suspend,
1662 .resume = w840_resume,
1663#endif
1664};
1665
1666static int __init w840_init(void)
1667{
1668 printk(version);
29917620 1669 return pci_register_driver(&w840_driver);
1da177e4
LT		 1670}
1671
1672static void __exit w840_exit(void)
1673{
1674 pci_unregister_driver(&w840_driver);
1675}
1676
1677module_init(w840_init);
1678module_exit(w840_exit);
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