[net-next-2.6.git] / drivers / net / tulip / tulip.h

/*
	drivers/net/tulip/tulip.h

	Copyright 2000,2001  The Linux Kernel Team
	Written/copyright 1994-2001 by Donald Becker.

	This software may be used and distributed according to the terms
	of the GNU General Public License, incorporated herein by reference.

	Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
	for more information on this driver, or visit the project
	Web page at http://sourceforge.net/projects/tulip/

*/

#ifndef __NET_TULIP_H__
#define __NET_TULIP_H__

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/netdevice.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/io.h>
#include <asm/irq.h>


/* undefine, or define to various debugging levels (>4 == obscene levels) */
#define TULIP_DEBUG 1

#ifdef CONFIG_TULIP_MMIO
#define TULIP_BAR	1	/* CBMA */
#else
#define TULIP_BAR	0	/* CBIO */
#endif


struct tulip_chip_table {
	char *chip_name;
	int io_size;
	int valid_intrs;	/* CSR7 interrupt enable settings */
	int flags;
	void (*media_timer) (unsigned long);
	work_func_t media_task;
};


enum tbl_flag {
	HAS_MII			= 0x0001,
	HAS_MEDIA_TABLE		= 0x0002,
	CSR12_IN_SROM		= 0x0004,
	ALWAYS_CHECK_MII	= 0x0008,
	HAS_ACPI		= 0x0010,
	MC_HASH_ONLY		= 0x0020, /* Hash-only multicast filter. */
	HAS_PNICNWAY		= 0x0080,
	HAS_NWAY		= 0x0040, /* Uses internal NWay xcvr. */
	HAS_INTR_MITIGATION	= 0x0100,
	IS_ASIX			= 0x0200,
	HAS_8023X		= 0x0400,
	COMET_MAC_ADDR		= 0x0800,
	HAS_PCI_MWI		= 0x1000,
	HAS_PHY_IRQ		= 0x2000,
	HAS_SWAPPED_SEEPROM	= 0x4000,
	NEEDS_FAKE_MEDIA_TABLE	= 0x8000,
};


/* chip types.  careful!  order is VERY IMPORTANT here, as these
 * are used throughout the driver as indices into arrays */
/* Note 21142 == 21143. */
enum chips {
	DC21040 = 0,
	DC21041 = 1,
	DC21140 = 2,
	DC21142 = 3, DC21143 = 3,
	LC82C168,
	MX98713,
	MX98715,
	MX98725,
	AX88140,
	PNIC2,
	COMET,
	COMPEX9881,
	I21145,
	DM910X,
	CONEXANT,
};


enum MediaIs {
	MediaIsFD = 1,
	MediaAlwaysFD = 2,
	MediaIsMII = 4,
	MediaIsFx = 8,
	MediaIs100 = 16
};


/* Offsets to the Command and Status Registers, "CSRs".  All accesses
   must be longword instructions and quadword aligned. */
enum tulip_offsets {
	CSR0 = 0,
	CSR1 = 0x08,
	CSR2 = 0x10,
	CSR3 = 0x18,
	CSR4 = 0x20,
	CSR5 = 0x28,
	CSR6 = 0x30,
	CSR7 = 0x38,
	CSR8 = 0x40,
	CSR9 = 0x48,
	CSR10 = 0x50,
	CSR11 = 0x58,
	CSR12 = 0x60,
	CSR13 = 0x68,
	CSR14 = 0x70,
	CSR15 = 0x78,
};

/* register offset and bits for CFDD PCI config reg */
enum pci_cfg_driver_reg {
	CFDD = 0x40,
	CFDD_Sleep = (1 << 31),
	CFDD_Snooze = (1 << 30),
};

#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)

/* The bits in the CSR5 status registers, mostly interrupt sources. */
enum status_bits {
	TimerInt = 0x800,
	SystemError = 0x2000,
	TPLnkFail = 0x1000,
	TPLnkPass = 0x10,
	NormalIntr = 0x10000,
	AbnormalIntr = 0x8000,
	RxJabber = 0x200,
	RxDied = 0x100,
	RxNoBuf = 0x80,
	RxIntr = 0x40,
	TxFIFOUnderflow = 0x20,
	RxErrIntr = 0x10,
	TxJabber = 0x08,
	TxNoBuf = 0x04,
	TxDied = 0x02,
	TxIntr = 0x01,
};

/* bit mask for CSR5 TX/RX process state */
#define CSR5_TS	0x00700000
#define CSR5_RS	0x000e0000

enum tulip_mode_bits {
	TxThreshold		= (1 << 22),
	FullDuplex		= (1 << 9),
	TxOn			= 0x2000,
	AcceptBroadcast		= 0x0100,
	AcceptAllMulticast	= 0x0080,
	AcceptAllPhys		= 0x0040,
	AcceptRunt		= 0x0008,
	RxOn			= 0x0002,
	RxTx			= (TxOn | RxOn),
};


enum tulip_busconfig_bits {
	MWI			= (1 << 24),
	MRL			= (1 << 23),
	MRM			= (1 << 21),
	CALShift		= 14,
	BurstLenShift		= 8,
};


/* The Tulip Rx and Tx buffer descriptors. */
struct tulip_rx_desc {
	s32 status;
	s32 length;
	u32 buffer1;
	u32 buffer2;
};


struct tulip_tx_desc {
	s32 status;
	s32 length;
	u32 buffer1;
	u32 buffer2;		/* We use only buffer 1.  */
};


enum desc_status_bits {
	DescOwned    = 0x80000000,
	DescWholePkt = 0x60000000,
	DescEndPkt   = 0x40000000,
	DescStartPkt = 0x20000000,
	DescEndRing  = 0x02000000,
	DescUseLink  = 0x01000000,
	RxDescFatalErr = 0x008000,
	RxWholePkt   = 0x00000300,
};


enum t21143_csr6_bits {
	csr6_sc = (1<<31),
	csr6_ra = (1<<30),
	csr6_ign_dest_msb = (1<<26),
	csr6_mbo = (1<<25),
	csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
	csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
	csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
	csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
	csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
	csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
	csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
	csr6_trh = (1<<15),  /* Transmit Threshold high bit */
	csr6_trl = (1<<14),  /* Transmit Threshold low bit */

	/***************************************************************
	 * This table shows transmit threshold values based on media   *
	 * and these two registers (from PNIC1 & 2 docs) Note: this is *
	 * all meaningless if sf is set.                               *
	 ***************************************************************/

	/***********************************
	 * (trh,trl) * 100BaseTX * 10BaseT *
	 ***********************************
	 *   (0,0)   *     128   *    72   *
	 *   (0,1)   *     256   *    96   *
	 *   (1,0)   *     512   *   128   *
	 *   (1,1)   *    1024   *   160   *
	 ***********************************/

	csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
	csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
	csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
	/* set both and you get (PHY) loopback */
	csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
	csr6_pm = (1<<7),    /* Pass All Multicast */
	csr6_pr = (1<<6),    /* Promiscuous mode */
	csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
	csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
	csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
	csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
	csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */

	csr6_mask_capture = (csr6_sc | csr6_ca),
	csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
	csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
	csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
	csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
	csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
	csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
	csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
};


/* Keep the ring sizes a power of two for efficiency.
   Making the Tx ring too large decreases the effectiveness of channel
   bonding and packet priority.
   There are no ill effects from too-large receive rings. */

#define TX_RING_SIZE	32
#define RX_RING_SIZE	128
#define MEDIA_MASK     31

#define PKT_BUF_SZ		1536	/* Size of each temporary Rx buffer. */

#define TULIP_MIN_CACHE_LINE	8	/* in units of 32-bit words */

#if defined(__sparc__) || defined(__hppa__)
/* The UltraSparc PCI controllers will disconnect at every 64-byte
 * crossing anyways so it makes no sense to tell Tulip to burst
 * any more than that.
 */
#define TULIP_MAX_CACHE_LINE	16	/* in units of 32-bit words */
#else
#define TULIP_MAX_CACHE_LINE	32	/* in units of 32-bit words */
#endif


/* Ring-wrap flag in length field, use for last ring entry.
	0x01000000 means chain on buffer2 address,
	0x02000000 means use the ring start address in CSR2/3.
   Note: Some work-alike chips do not function correctly in chained mode.
   The ASIX chip works only in chained mode.
   Thus we indicates ring mode, but always write the 'next' field for
   chained mode as well.
*/
#define DESC_RING_WRAP 0x02000000


#define EEPROM_SIZE 512 	/* 2 << EEPROM_ADDRLEN */


#define RUN_AT(x) (jiffies + (x))

#if defined(__i386__)			/* AKA get_unaligned() */
#define get_u16(ptr) (*(u16 *)(ptr))
#else
#define get_u16(ptr) (((u8*)(ptr))[0] + (((u8*)(ptr))[1]<<8))
#endif

struct medialeaf {
	u8 type;
	u8 media;
	unsigned char *leafdata;
};


struct mediatable {
	u16 defaultmedia;
	u8 leafcount;
	u8 csr12dir;		/* General purpose pin directions. */
	unsigned has_mii:1;
	unsigned has_nonmii:1;
	unsigned has_reset:6;
	u32 csr15dir;
	u32 csr15val;		/* 21143 NWay setting. */
	struct medialeaf mleaf[0];
};


struct mediainfo {
	struct mediainfo *next;
	int info_type;
	int index;
	unsigned char *info;
};

struct ring_info {
	struct sk_buff	*skb;
	dma_addr_t	mapping;
};


struct tulip_private {
	const char *product_name;
	struct net_device *next_module;
	struct tulip_rx_desc *rx_ring;
	struct tulip_tx_desc *tx_ring;
	dma_addr_t rx_ring_dma;
	dma_addr_t tx_ring_dma;
	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
	struct ring_info tx_buffers[TX_RING_SIZE];
	/* The addresses of receive-in-place skbuffs. */
	struct ring_info rx_buffers[RX_RING_SIZE];
	u16 setup_frame[96];	/* Pseudo-Tx frame to init address table. */
	int chip_id;
	int revision;
	int flags;
	struct napi_struct napi;
	struct net_device_stats stats;
	struct timer_list timer;	/* Media selection timer. */
	struct timer_list oom_timer;    /* Out of memory timer. */
	u32 mc_filter[2];
	spinlock_t lock;
	spinlock_t mii_lock;
	unsigned int cur_rx, cur_tx;	/* The next free ring entry */
	unsigned int dirty_rx, dirty_tx;	/* The ring entries to be free()ed. */

#ifdef 	CONFIG_TULIP_NAPI_HW_MITIGATION
        int mit_on;
#endif
	unsigned int full_duplex:1;	/* Full-duplex operation requested. */
	unsigned int full_duplex_lock:1;
	unsigned int fake_addr:1;	/* Multiport board faked address. */
	unsigned int default_port:4;	/* Last dev->if_port value. */
	unsigned int media2:4;	/* Secondary monitored media port. */
	unsigned int medialock:1;	/* Don't sense media type. */
	unsigned int mediasense:1;	/* Media sensing in progress. */
	unsigned int nway:1, nwayset:1;		/* 21143 internal NWay. */
	unsigned int timeout_recovery:1;
	unsigned int csr0;	/* CSR0 setting. */
	unsigned int csr6;	/* Current CSR6 control settings. */
	unsigned char eeprom[EEPROM_SIZE];	/* Serial EEPROM contents. */
	void (*link_change) (struct net_device * dev, int csr5);
	u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
	u16 lpar;		/* 21143 Link partner ability. */
	u16 advertising[4];
	signed char phys[4], mii_cnt;	/* MII device addresses. */
	struct mediatable *mtable;
	int cur_index;		/* Current media index. */
	int saved_if_port;
	struct pci_dev *pdev;
	int ttimer;
	int susp_rx;
	unsigned long nir;
	void __iomem *base_addr;
	int csr12_shadow;
	int pad0;		/* Used for 8-byte alignment */
	struct work_struct media_work;
	struct net_device *dev;
};


struct eeprom_fixup {
	char *name;
	unsigned char addr0;
	unsigned char addr1;
	unsigned char addr2;
	u16 newtable[32];	/* Max length below. */
};


/* 21142.c */
extern u16 t21142_csr14[];
void t21142_media_task(struct work_struct *work);
void t21142_start_nway(struct net_device *dev);
void t21142_lnk_change(struct net_device *dev, int csr5);


/* PNIC2.c */
void pnic2_lnk_change(struct net_device *dev, int csr5);
void pnic2_timer(unsigned long data);
void pnic2_start_nway(struct net_device *dev);
void pnic2_lnk_change(struct net_device *dev, int csr5);

/* eeprom.c */
void tulip_parse_eeprom(struct net_device *dev);
int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);

/* interrupt.c */
extern unsigned int tulip_max_interrupt_work;
extern int tulip_rx_copybreak;
irqreturn_t tulip_interrupt(int irq, void *dev_instance);
int tulip_refill_rx(struct net_device *dev);
#ifdef CONFIG_TULIP_NAPI
int tulip_poll(struct napi_struct *napi, int budget);
#endif


/* media.c */
int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
void tulip_select_media(struct net_device *dev, int startup);
int tulip_check_duplex(struct net_device *dev);
void tulip_find_mii (struct net_device *dev, int board_idx);

/* pnic.c */
void pnic_do_nway(struct net_device *dev);
void pnic_lnk_change(struct net_device *dev, int csr5);
void pnic_timer(unsigned long data);

/* timer.c */
void tulip_media_task(struct work_struct *work);
void mxic_timer(unsigned long data);
void comet_timer(unsigned long data);

/* tulip_core.c */
extern int tulip_debug;
extern const char * const medianame[];
extern const char tulip_media_cap[];
extern struct tulip_chip_table tulip_tbl[];
void oom_timer(unsigned long data);
extern u8 t21040_csr13[];

static inline void tulip_start_rxtx(struct tulip_private *tp)
{
	void __iomem *ioaddr = tp->base_addr;
	iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
	barrier();
	(void) ioread32(ioaddr + CSR6); /* mmio sync */
}

static inline void tulip_stop_rxtx(struct tulip_private *tp)
{
	void __iomem *ioaddr = tp->base_addr;
	u32 csr6 = ioread32(ioaddr + CSR6);

	if (csr6 & RxTx) {
		unsigned i=1300/10;
		iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
		barrier();
		/* wait until in-flight frame completes.
		 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
		 * Typically expect this loop to end in < 50 us on 100BT.
		 */
		while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
			udelay(10);

		if (!i)
			printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
					" (CSR5 0x%x CSR6 0x%x)\n",
					pci_name(tp->pdev),
					ioread32(ioaddr + CSR5),
					ioread32(ioaddr + CSR6));
	}
}

static inline void tulip_restart_rxtx(struct tulip_private *tp)
{
	tulip_stop_rxtx(tp);
	udelay(5);
	tulip_start_rxtx(tp);
}

static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
{
	/* Stop and restart the chip's Tx processes. */
	tulip_restart_rxtx(tp);
	/* Trigger an immediate transmit demand. */
	iowrite32(0, ioaddr + CSR1);

	tp->stats.tx_errors++;
}

#endif /* __NET_TULIP_H__ */
Commit	Line	Data
1da177e4 LT	1	/*
	2	drivers/net/tulip/tulip.h
	3
	4	Copyright 2000,2001 The Linux Kernel Team
	5	Written/copyright 1994-2001 by Donald Becker.
	6
	7	This software may be used and distributed according to the terms
	8	of the GNU General Public License, incorporated herein by reference.
	9
	10	Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
	11	for more information on this driver, or visit the project
	12	Web page at http://sourceforge.net/projects/tulip/
	13
	14	*/
	15
	16	#ifndef __NET_TULIP_H__
	17	#define __NET_TULIP_H__
	18
1da177e4 LT	19	#include <linux/kernel.h>
	20	#include <linux/types.h>
	21	#include <linux/spinlock.h>
	22	#include <linux/netdevice.h>
	23	#include <linux/timer.h>
	24	#include <linux/delay.h>
6473d160	25	#include <linux/pci.h>
1da177e4 LT	26	#include <asm/io.h>
	27	#include <asm/irq.h>
	28
	29
	30
	31	/* undefine, or define to various debugging levels (>4 == obscene levels) */
	32	#define TULIP_DEBUG 1
	33
1da177e4	34	#ifdef CONFIG_TULIP_MMIO
7f2b1248	35	#define TULIP_BAR 1 /* CBMA */
1da177e4	36	#else
7f2b1248	37	#define TULIP_BAR 0 /* CBIO */
1da177e4 LT	38	#endif
	39
	40
	41
	42	struct tulip_chip_table {
	43	char *chip_name;
	44	int io_size;
	45	int valid_intrs; /* CSR7 interrupt enable settings */
	46	int flags;
0bb3cf72	47	void (*media_timer) (unsigned long);
c4028958	48	work_func_t media_task;
1da177e4 LT	49	};
	50
	51
	52	enum tbl_flag {
	53	HAS_MII = 0x0001,
	54	HAS_MEDIA_TABLE = 0x0002,
	55	CSR12_IN_SROM = 0x0004,
	56	ALWAYS_CHECK_MII = 0x0008,
	57	HAS_ACPI = 0x0010,
	58	MC_HASH_ONLY = 0x0020, /* Hash-only multicast filter. */
	59	HAS_PNICNWAY = 0x0080,
	60	HAS_NWAY = 0x0040, /* Uses internal NWay xcvr. */
	61	HAS_INTR_MITIGATION = 0x0100,
	62	IS_ASIX = 0x0200,
	63	HAS_8023X = 0x0400,
	64	COMET_MAC_ADDR = 0x0800,
	65	HAS_PCI_MWI = 0x1000,
	66	HAS_PHY_IRQ = 0x2000,
	67	HAS_SWAPPED_SEEPROM = 0x4000,
	68	NEEDS_FAKE_MEDIA_TABLE = 0x8000,
	69	};
	70
	71
	72	/* chip types. careful! order is VERY IMPORTANT here, as these
	73	* are used throughout the driver as indices into arrays */
	74	/* Note 21142 == 21143. */
	75	enum chips {
	76	DC21040 = 0,
	77	DC21041 = 1,
	78	DC21140 = 2,
	79	DC21142 = 3, DC21143 = 3,
	80	LC82C168,
	81	MX98713,
	82	MX98715,
	83	MX98725,
	84	AX88140,
	85	PNIC2,
	86	COMET,
	87	COMPEX9881,
	88	I21145,
	89	DM910X,
	90	CONEXANT,
1da177e4 LT	91	};
	92
	93
	94	enum MediaIs {
	95	MediaIsFD = 1,
	96	MediaAlwaysFD = 2,
	97	MediaIsMII = 4,
	98	MediaIsFx = 8,
	99	MediaIs100 = 16
	100	};
	101
	102
	103	/* Offsets to the Command and Status Registers, "CSRs". All accesses
	104	must be longword instructions and quadword aligned. */
	105	enum tulip_offsets {
	106	CSR0 = 0,
	107	CSR1 = 0x08,
	108	CSR2 = 0x10,
	109	CSR3 = 0x18,
	110	CSR4 = 0x20,
	111	CSR5 = 0x28,
	112	CSR6 = 0x30,
	113	CSR7 = 0x38,
	114	CSR8 = 0x40,
	115	CSR9 = 0x48,
	116	CSR10 = 0x50,
	117	CSR11 = 0x58,
	118	CSR12 = 0x60,
	119	CSR13 = 0x68,
	120	CSR14 = 0x70,
	121	CSR15 = 0x78,
	122	};
	123
	124	/* register offset and bits for CFDD PCI config reg */
	125	enum pci_cfg_driver_reg {
	126	CFDD = 0x40,
	127	CFDD_Sleep = (1 << 31),
	128	CFDD_Snooze = (1 << 30),
	129	};
	130
	131	#define RxPollInt (RxIntr\|RxNoBuf\|RxDied\|RxJabber)
	132
	133	/* The bits in the CSR5 status registers, mostly interrupt sources. */
	134	enum status_bits {
	135	TimerInt = 0x800,
1ddb9861	136	SystemError = 0x2000,
1da177e4 LT	137	TPLnkFail = 0x1000,
	138	TPLnkPass = 0x10,
	139	NormalIntr = 0x10000,
	140	AbnormalIntr = 0x8000,
	141	RxJabber = 0x200,
	142	RxDied = 0x100,
	143	RxNoBuf = 0x80,
	144	RxIntr = 0x40,
	145	TxFIFOUnderflow = 0x20,
7f2b1248	146	RxErrIntr = 0x10,
1da177e4 LT	147	TxJabber = 0x08,
	148	TxNoBuf = 0x04,
	149	TxDied = 0x02,
	150	TxIntr = 0x01,
	151	};
	152
	153	/* bit mask for CSR5 TX/RX process state */
	154	#define CSR5_TS 0x00700000
	155	#define CSR5_RS 0x000e0000
	156
	157	enum tulip_mode_bits {
	158	TxThreshold = (1 << 22),
	159	FullDuplex = (1 << 9),
	160	TxOn = 0x2000,
	161	AcceptBroadcast = 0x0100,
	162	AcceptAllMulticast = 0x0080,
	163	AcceptAllPhys = 0x0040,
	164	AcceptRunt = 0x0008,
	165	RxOn = 0x0002,
	166	RxTx = (TxOn \| RxOn),
	167	};
	168
	169
	170	enum tulip_busconfig_bits {
	171	MWI = (1 << 24),
	172	MRL = (1 << 23),
	173	MRM = (1 << 21),
	174	CALShift = 14,
	175	BurstLenShift = 8,
	176	};
	177
	178
	179	/* The Tulip Rx and Tx buffer descriptors. */
	180	struct tulip_rx_desc {
	181	s32 status;
	182	s32 length;
	183	u32 buffer1;
	184	u32 buffer2;
	185	};
	186
	187
	188	struct tulip_tx_desc {
	189	s32 status;
	190	s32 length;
	191	u32 buffer1;
	192	u32 buffer2; /* We use only buffer 1. */
	193	};
	194
	195
	196	enum desc_status_bits {
7f2b1248 GG	197	DescOwned = 0x80000000,
	198	DescWholePkt = 0x60000000,
	199	DescEndPkt = 0x40000000,
	200	DescStartPkt = 0x20000000,
	201	DescEndRing = 0x02000000,
	202	DescUseLink = 0x01000000,
	203	RxDescFatalErr = 0x008000,
	204	RxWholePkt = 0x00000300,
1da177e4 LT	205	};
	206
	207
	208	enum t21143_csr6_bits {
	209	csr6_sc = (1<<31),
	210	csr6_ra = (1<<30),
	211	csr6_ign_dest_msb = (1<<26),
	212	csr6_mbo = (1<<25),
	213	csr6_scr = (1<<24), /* scramble mode flag: can't be set */
	214	csr6_pcs = (1<<23), /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
	215	csr6_ttm = (1<<22), /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
	216	csr6_sf = (1<<21), /* Store and forward. If set ignores TR bits */
	217	csr6_hbd = (1<<19), /* Heart beat disable. Disables SQE function in 10baseT */
	218	csr6_ps = (1<<18), /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
	219	csr6_ca = (1<<17), /* Collision Offset Enable. If set uses special algorithm in low collision situations */
	220	csr6_trh = (1<<15), /* Transmit Threshold high bit */
	221	csr6_trl = (1<<14), /* Transmit Threshold low bit */
	222
	223	/***************************************************************
	224	* This table shows transmit threshold values based on media *
	225	* and these two registers (from PNIC1 & 2 docs) Note: this is *
	226	* all meaningless if sf is set. *
	227	***************************************************************/
	228
	229	/***********************************
	230	* (trh,trl) * 100BaseTX * 10BaseT *
	231	***********************************
	232	* (0,0) * 128 * 72 *
	233	* (0,1) * 256 * 96 *
	234	* (1,0) * 512 * 128 *
	235	* (1,1) * 1024 * 160 *
	236	***********************************/
	237
	238	csr6_fc = (1<<12), /* Forces a collision in next transmission (for testing in loopback mode) */
	239	csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
	240	csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
	241	/* set both and you get (PHY) loopback */
	242	csr6_fd = (1<<9), /* Full duplex mode, disables hearbeat, no loopback */
	243	csr6_pm = (1<<7), /* Pass All Multicast */
	244	csr6_pr = (1<<6), /* Promiscuous mode */
	245	csr6_sb = (1<<5), /* Start(1)/Stop(0) backoff counter */
	246	csr6_if = (1<<4), /* Inverse Filtering, rejects only addresses in address table: can't be set */
	247	csr6_pb = (1<<3), /* Pass Bad Frames, (1) causes even bad frames to be passed on */
	248	csr6_ho = (1<<2), /* Hash-only filtering mode: can't be set */
	249	csr6_hp = (1<<0), /* Hash/Perfect Receive Filtering Mode: can't be set */
	250
	251	csr6_mask_capture = (csr6_sc \| csr6_ca),
	252	csr6_mask_defstate = (csr6_mask_capture \| csr6_mbo),
	253	csr6_mask_hdcap = (csr6_mask_defstate \| csr6_hbd \| csr6_ps),
	254	csr6_mask_hdcaptt = (csr6_mask_hdcap \| csr6_trh \| csr6_trl),
	255	csr6_mask_fullcap = (csr6_mask_hdcaptt \| csr6_fd),
	256	csr6_mask_fullpromisc = (csr6_pr \| csr6_pm),
	257	csr6_mask_filters = (csr6_hp \| csr6_ho \| csr6_if),
	258	csr6_mask_100bt = (csr6_scr \| csr6_pcs \| csr6_hbd),
	259	};
	260
	261
	262	/* Keep the ring sizes a power of two for efficiency.
	263	Making the Tx ring too large decreases the effectiveness of channel
	264	bonding and packet priority.
	265	There are no ill effects from too-large receive rings. */
	266
	267	#define TX_RING_SIZE 32
f3b197ac	268	#define RX_RING_SIZE 128
1da177e4 LT	269	#define MEDIA_MASK 31
	270
	271	#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
	272
	273	#define TULIP_MIN_CACHE_LINE 8 /* in units of 32-bit words */
	274
	275	#if defined(__sparc__) \|\| defined(__hppa__)
	276	/* The UltraSparc PCI controllers will disconnect at every 64-byte
	277	* crossing anyways so it makes no sense to tell Tulip to burst
	278	* any more than that.
	279	*/
	280	#define TULIP_MAX_CACHE_LINE 16 /* in units of 32-bit words */
	281	#else
	282	#define TULIP_MAX_CACHE_LINE 32 /* in units of 32-bit words */
	283	#endif
	284
	285
	286	/* Ring-wrap flag in length field, use for last ring entry.
	287	0x01000000 means chain on buffer2 address,
	288	0x02000000 means use the ring start address in CSR2/3.
	289	Note: Some work-alike chips do not function correctly in chained mode.
	290	The ASIX chip works only in chained mode.
	291	Thus we indicates ring mode, but always write the 'next' field for
	292	chained mode as well.
	293	*/
	294	#define DESC_RING_WRAP 0x02000000
	295
	296
	297	#define EEPROM_SIZE 512 /* 2 << EEPROM_ADDRLEN */
	298
	299
	300	#define RUN_AT(x) (jiffies + (x))
	301
	302	#if defined(__i386__) /* AKA get_unaligned() */
	303	#define get_u16(ptr) ((u16 )(ptr))
	304	#else
	305	#define get_u16(ptr) (((u8)(ptr))[0] + (((u8)(ptr))[1]<<8))
	306	#endif
	307
	308	struct medialeaf {
	309	u8 type;
	310	u8 media;
	311	unsigned char *leafdata;
	312	};
	313
	314
	315	struct mediatable {
	316	u16 defaultmedia;
	317	u8 leafcount;
	318	u8 csr12dir; /* General purpose pin directions. */
	319	unsigned has_mii:1;
	320	unsigned has_nonmii:1;
	321	unsigned has_reset:6;
	322	u32 csr15dir;
	323	u32 csr15val; /* 21143 NWay setting. */
	324	struct medialeaf mleaf[0];
	325	};
	326
	327
	328	struct mediainfo {
	329	struct mediainfo *next;
	330	int info_type;
	331	int index;
	332	unsigned char *info;
333	};
334
335	struct ring_info {
336	struct sk_buff *skb;
337	dma_addr_t mapping;
338	};
339
340
341	struct tulip_private {
342	const char *product_name;
343	struct net_device *next_module;
344	struct tulip_rx_desc *rx_ring;
345	struct tulip_tx_desc *tx_ring;
346	dma_addr_t rx_ring_dma;
347	dma_addr_t tx_ring_dma;
348	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
349	struct ring_info tx_buffers[TX_RING_SIZE];
350	/* The addresses of receive-in-place skbuffs. */
351	struct ring_info rx_buffers[RX_RING_SIZE];
352	u16 setup_frame[96]; /* Pseudo-Tx frame to init address table. */
353	int chip_id;
354	int revision;
355	int flags;
bea3348e	356	struct napi_struct napi;
1da177e4 LT	357	struct net_device_stats stats;
	358	struct timer_list timer; /* Media selection timer. */
	359	struct timer_list oom_timer; /* Out of memory timer. */
	360	u32 mc_filter[2];
	361	spinlock_t lock;
	362	spinlock_t mii_lock;
	363	unsigned int cur_rx, cur_tx; /* The next free ring entry */
	364	unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
	365
	366	#ifdef CONFIG_TULIP_NAPI_HW_MITIGATION
	367	int mit_on;
	368	#endif
	369	unsigned int full_duplex:1; /* Full-duplex operation requested. */
	370	unsigned int full_duplex_lock:1;
	371	unsigned int fake_addr:1; /* Multiport board faked address. */
	372	unsigned int default_port:4; /* Last dev->if_port value. */
	373	unsigned int media2:4; /* Secondary monitored media port. */
	374	unsigned int medialock:1; /* Don't sense media type. */
	375	unsigned int mediasense:1; /* Media sensing in progress. */
	376	unsigned int nway:1, nwayset:1; /* 21143 internal NWay. */
0bb3cf72	377	unsigned int timeout_recovery:1;
1da177e4 LT	378	unsigned int csr0; /* CSR0 setting. */
	379	unsigned int csr6; /* Current CSR6 control settings. */
	380	unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
	381	void (link_change) (struct net_device dev, int csr5);
	382	u16 sym_advertise, mii_advertise; /* NWay capabilities advertised. */
	383	u16 lpar; /* 21143 Link partner ability. */
	384	u16 advertising[4];
	385	signed char phys[4], mii_cnt; /* MII device addresses. */
	386	struct mediatable *mtable;
	387	int cur_index; /* Current media index. */
	388	int saved_if_port;
	389	struct pci_dev *pdev;
	390	int ttimer;
	391	int susp_rx;
	392	unsigned long nir;
	393	void __iomem *base_addr;
	394	int csr12_shadow;
	395	int pad0; /* Used for 8-byte alignment */
0bb3cf72	396	struct work_struct media_work;
c4028958	397	struct net_device *dev;
1da177e4 LT	398	};
	399
	400
	401	struct eeprom_fixup {
	402	char *name;
	403	unsigned char addr0;
	404	unsigned char addr1;
	405	unsigned char addr2;
	406	u16 newtable[32]; /* Max length below. */
	407	};
	408
	409
	410	/* 21142.c */
	411	extern u16 t21142_csr14[];
c4028958	412	void t21142_media_task(struct work_struct *work);
1da177e4 LT	413	void t21142_start_nway(struct net_device *dev);
	414	void t21142_lnk_change(struct net_device *dev, int csr5);
	415
	416
	417	/* PNIC2.c */
	418	void pnic2_lnk_change(struct net_device *dev, int csr5);
	419	void pnic2_timer(unsigned long data);
	420	void pnic2_start_nway(struct net_device *dev);
	421	void pnic2_lnk_change(struct net_device *dev, int csr5);
	422
	423	/* eeprom.c */
	424	void tulip_parse_eeprom(struct net_device *dev);
	425	int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
	426
	427	/* interrupt.c */
	428	extern unsigned int tulip_max_interrupt_work;
	429	extern int tulip_rx_copybreak;
7d12e780	430	irqreturn_t tulip_interrupt(int irq, void *dev_instance);
1da177e4 LT	431	int tulip_refill_rx(struct net_device *dev);
1da177e4 LT	432	#ifdef CONFIG_TULIP_NAPI
bea3348e	433	int tulip_poll(struct napi_struct *napi, int budget);
1da177e4 LT	434	#endif
	435
	436
	437	/* media.c */
	438	int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
	439	void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
	440	void tulip_select_media(struct net_device *dev, int startup);
	441	int tulip_check_duplex(struct net_device *dev);
	442	void tulip_find_mii (struct net_device *dev, int board_idx);
	443
	444	/* pnic.c */
	445	void pnic_do_nway(struct net_device *dev);
	446	void pnic_lnk_change(struct net_device *dev, int csr5);
	447	void pnic_timer(unsigned long data);
	448
	449	/* timer.c */
c4028958	450	void tulip_media_task(struct work_struct *work);
1da177e4 LT	451	void mxic_timer(unsigned long data);
	452	void comet_timer(unsigned long data);
	453
	454	/* tulip_core.c */
	455	extern int tulip_debug;
	456	extern const char * const medianame[];
	457	extern const char tulip_media_cap[];
	458	extern struct tulip_chip_table tulip_tbl[];
	459	void oom_timer(unsigned long data);
	460	extern u8 t21040_csr13[];
	461
	462	static inline void tulip_start_rxtx(struct tulip_private *tp)
	463	{
	464	void __iomem *ioaddr = tp->base_addr;
	465	iowrite32(tp->csr6 \| RxTx, ioaddr + CSR6);
	466	barrier();
	467	(void) ioread32(ioaddr + CSR6); /* mmio sync */
	468	}
	469
	470	static inline void tulip_stop_rxtx(struct tulip_private *tp)
	471	{
	472	void __iomem *ioaddr = tp->base_addr;
	473	u32 csr6 = ioread32(ioaddr + CSR6);
	474
	475	if (csr6 & RxTx) {
	476	unsigned i=1300/10;
	477	iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
	478	barrier();
	479	/* wait until in-flight frame completes.
	480	* Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
	481	* Typically expect this loop to end in < 50 us on 100BT.
	482	*/
	483	while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS\|CSR5_RS)))
	484	udelay(10);
	485
	486	if (!i)
b3bff39a VH	487	printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
	488	" (CSR5 0x%x CSR6 0x%x)\n",
	489	pci_name(tp->pdev),
	490	ioread32(ioaddr + CSR5),
	491	ioread32(ioaddr + CSR6));
1da177e4 LT	492	}
	493	}
	494
	495	static inline void tulip_restart_rxtx(struct tulip_private *tp)
	496	{
ea8f400c PC	497	tulip_stop_rxtx(tp);
ea8f400c PC	498	udelay(5);
1da177e4 LT	499	tulip_start_rxtx(tp);
	500	}
	501
0bb3cf72 FR	502	static inline void tulip_tx_timeout_complete(struct tulip_private tp, void __iomem ioaddr)
	503	{
	504	/* Stop and restart the chip's Tx processes. */
	505	tulip_restart_rxtx(tp);
	506	/* Trigger an immediate transmit demand. */
	507	iowrite32(0, ioaddr + CSR1);
	508
	509	tp->stats.tx_errors++;
	510	}
	511
1da177e4	512	#endif /* __NET_TULIP_H__ */