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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | drivers/net/tulip/media.c | |
3 | ||
1da177e4 LT |
4 | Copyright 2000,2001 The Linux Kernel Team |
5 | Written/copyright 1994-2001 by Donald Becker. | |
6 | ||
7 | This software may be used and distributed according to the terms | |
8 | of the GNU General Public License, incorporated herein by reference. | |
9 | ||
10 | Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html} | |
78a65518 | 11 | for more information on this driver. |
1da177e4 | 12 | |
78a65518 | 13 | Please submit bugs to http://bugzilla.kernel.org/ . |
1da177e4 LT |
14 | */ |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/mii.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/pci.h> | |
21 | #include "tulip.h" | |
22 | ||
23 | ||
24 | /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually | |
25 | met by back-to-back PCI I/O cycles, but we insert a delay to avoid | |
26 | "overclocking" issues or future 66Mhz PCI. */ | |
27 | #define mdio_delay() ioread32(mdio_addr) | |
28 | ||
29 | /* Read and write the MII registers using software-generated serial | |
30 | MDIO protocol. It is just different enough from the EEPROM protocol | |
31 | to not share code. The maxium data clock rate is 2.5 Mhz. */ | |
32 | #define MDIO_SHIFT_CLK 0x10000 | |
33 | #define MDIO_DATA_WRITE0 0x00000 | |
34 | #define MDIO_DATA_WRITE1 0x20000 | |
35 | #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */ | |
36 | #define MDIO_ENB_IN 0x40000 | |
37 | #define MDIO_DATA_READ 0x80000 | |
38 | ||
39 | static const unsigned char comet_miireg2offset[32] = { | |
40 | 0xB4, 0xB8, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC, 0, 0,0,0,0, 0,0,0,0, | |
41 | 0,0xD0,0,0, 0,0,0,0, 0,0,0,0, 0, 0xD4, 0xD8, 0xDC, }; | |
42 | ||
43 | ||
44 | /* MII transceiver control section. | |
45 | Read and write the MII registers using software-generated serial | |
b3bff39a VH |
46 | MDIO protocol. |
47 | See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions") | |
48 | or DP83840A data sheet for more details. | |
49 | */ | |
1da177e4 LT |
50 | |
51 | int tulip_mdio_read(struct net_device *dev, int phy_id, int location) | |
52 | { | |
53 | struct tulip_private *tp = netdev_priv(dev); | |
54 | int i; | |
55 | int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location; | |
56 | int retval = 0; | |
57 | void __iomem *ioaddr = tp->base_addr; | |
58 | void __iomem *mdio_addr = ioaddr + CSR9; | |
59 | unsigned long flags; | |
60 | ||
61 | if (location & ~0x1f) | |
62 | return 0xffff; | |
63 | ||
64 | if (tp->chip_id == COMET && phy_id == 30) { | |
65 | if (comet_miireg2offset[location]) | |
66 | return ioread32(ioaddr + comet_miireg2offset[location]); | |
67 | return 0xffff; | |
68 | } | |
69 | ||
70 | spin_lock_irqsave(&tp->mii_lock, flags); | |
71 | if (tp->chip_id == LC82C168) { | |
1da177e4 LT |
72 | iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0); |
73 | ioread32(ioaddr + 0xA0); | |
74 | ioread32(ioaddr + 0xA0); | |
de2f19da | 75 | for (i = 1000; i >= 0; --i) { |
1da177e4 LT |
76 | barrier(); |
77 | if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000)) | |
78 | break; | |
79 | } | |
80 | spin_unlock_irqrestore(&tp->mii_lock, flags); | |
81 | return retval & 0xffff; | |
82 | } | |
83 | ||
1da177e4 LT |
84 | /* Establish sync by sending at least 32 logic ones. */ |
85 | for (i = 32; i >= 0; i--) { | |
86 | iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); | |
87 | mdio_delay(); | |
88 | iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); | |
89 | mdio_delay(); | |
90 | } | |
91 | /* Shift the read command bits out. */ | |
92 | for (i = 15; i >= 0; i--) { | |
93 | int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; | |
94 | ||
95 | iowrite32(MDIO_ENB | dataval, mdio_addr); | |
96 | mdio_delay(); | |
97 | iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); | |
98 | mdio_delay(); | |
99 | } | |
100 | /* Read the two transition, 16 data, and wire-idle bits. */ | |
101 | for (i = 19; i > 0; i--) { | |
102 | iowrite32(MDIO_ENB_IN, mdio_addr); | |
103 | mdio_delay(); | |
104 | retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); | |
105 | iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); | |
106 | mdio_delay(); | |
107 | } | |
108 | ||
109 | spin_unlock_irqrestore(&tp->mii_lock, flags); | |
110 | return (retval>>1) & 0xffff; | |
111 | } | |
112 | ||
113 | void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val) | |
114 | { | |
115 | struct tulip_private *tp = netdev_priv(dev); | |
116 | int i; | |
117 | int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff); | |
118 | void __iomem *ioaddr = tp->base_addr; | |
119 | void __iomem *mdio_addr = ioaddr + CSR9; | |
120 | unsigned long flags; | |
121 | ||
122 | if (location & ~0x1f) | |
123 | return; | |
124 | ||
125 | if (tp->chip_id == COMET && phy_id == 30) { | |
126 | if (comet_miireg2offset[location]) | |
127 | iowrite32(val, ioaddr + comet_miireg2offset[location]); | |
128 | return; | |
129 | } | |
130 | ||
131 | spin_lock_irqsave(&tp->mii_lock, flags); | |
132 | if (tp->chip_id == LC82C168) { | |
1da177e4 | 133 | iowrite32(cmd, ioaddr + 0xA0); |
de2f19da | 134 | for (i = 1000; i >= 0; --i) { |
1da177e4 LT |
135 | barrier(); |
136 | if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000)) | |
137 | break; | |
de2f19da | 138 | } |
1da177e4 LT |
139 | spin_unlock_irqrestore(&tp->mii_lock, flags); |
140 | return; | |
141 | } | |
f3b197ac | 142 | |
1da177e4 LT |
143 | /* Establish sync by sending 32 logic ones. */ |
144 | for (i = 32; i >= 0; i--) { | |
145 | iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr); | |
146 | mdio_delay(); | |
147 | iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); | |
148 | mdio_delay(); | |
149 | } | |
150 | /* Shift the command bits out. */ | |
151 | for (i = 31; i >= 0; i--) { | |
152 | int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0; | |
153 | iowrite32(MDIO_ENB | dataval, mdio_addr); | |
154 | mdio_delay(); | |
155 | iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr); | |
156 | mdio_delay(); | |
157 | } | |
158 | /* Clear out extra bits. */ | |
159 | for (i = 2; i > 0; i--) { | |
160 | iowrite32(MDIO_ENB_IN, mdio_addr); | |
161 | mdio_delay(); | |
162 | iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); | |
163 | mdio_delay(); | |
164 | } | |
165 | ||
166 | spin_unlock_irqrestore(&tp->mii_lock, flags); | |
167 | } | |
168 | ||
169 | ||
170 | /* Set up the transceiver control registers for the selected media type. */ | |
171 | void tulip_select_media(struct net_device *dev, int startup) | |
172 | { | |
173 | struct tulip_private *tp = netdev_priv(dev); | |
174 | void __iomem *ioaddr = tp->base_addr; | |
175 | struct mediatable *mtable = tp->mtable; | |
176 | u32 new_csr6; | |
177 | int i; | |
178 | ||
179 | if (mtable) { | |
180 | struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index]; | |
181 | unsigned char *p = mleaf->leafdata; | |
182 | switch (mleaf->type) { | |
183 | case 0: /* 21140 non-MII xcvr. */ | |
184 | if (tulip_debug > 1) | |
fa0b9a4c JP |
185 | printk(KERN_DEBUG "%s: Using a 21140 non-MII transceiver with control setting %02x\n", |
186 | dev->name, p[1]); | |
1da177e4 LT |
187 | dev->if_port = p[0]; |
188 | if (startup) | |
189 | iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12); | |
190 | iowrite32(p[1], ioaddr + CSR12); | |
191 | new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18); | |
192 | break; | |
193 | case 2: case 4: { | |
194 | u16 setup[5]; | |
195 | u32 csr13val, csr14val, csr15dir, csr15val; | |
196 | for (i = 0; i < 5; i++) | |
197 | setup[i] = get_u16(&p[i*2 + 1]); | |
198 | ||
199 | dev->if_port = p[0] & MEDIA_MASK; | |
200 | if (tulip_media_cap[dev->if_port] & MediaAlwaysFD) | |
201 | tp->full_duplex = 1; | |
202 | ||
203 | if (startup && mtable->has_reset) { | |
204 | struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset]; | |
205 | unsigned char *rst = rleaf->leafdata; | |
206 | if (tulip_debug > 1) | |
fa0b9a4c JP |
207 | printk(KERN_DEBUG "%s: Resetting the transceiver\n", |
208 | dev->name); | |
1da177e4 LT |
209 | for (i = 0; i < rst[0]; i++) |
210 | iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); | |
211 | } | |
212 | if (tulip_debug > 1) | |
fa0b9a4c JP |
213 | printk(KERN_DEBUG "%s: 21143 non-MII %s transceiver control %04x/%04x\n", |
214 | dev->name, medianame[dev->if_port], | |
215 | setup[0], setup[1]); | |
1da177e4 LT |
216 | if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */ |
217 | csr13val = setup[0]; | |
218 | csr14val = setup[1]; | |
219 | csr15dir = (setup[3]<<16) | setup[2]; | |
220 | csr15val = (setup[4]<<16) | setup[2]; | |
221 | iowrite32(0, ioaddr + CSR13); | |
222 | iowrite32(csr14val, ioaddr + CSR14); | |
223 | iowrite32(csr15dir, ioaddr + CSR15); /* Direction */ | |
224 | iowrite32(csr15val, ioaddr + CSR15); /* Data */ | |
225 | iowrite32(csr13val, ioaddr + CSR13); | |
226 | } else { | |
227 | csr13val = 1; | |
228 | csr14val = 0; | |
229 | csr15dir = (setup[0]<<16) | 0x0008; | |
230 | csr15val = (setup[1]<<16) | 0x0008; | |
231 | if (dev->if_port <= 4) | |
232 | csr14val = t21142_csr14[dev->if_port]; | |
233 | if (startup) { | |
234 | iowrite32(0, ioaddr + CSR13); | |
235 | iowrite32(csr14val, ioaddr + CSR14); | |
236 | } | |
237 | iowrite32(csr15dir, ioaddr + CSR15); /* Direction */ | |
238 | iowrite32(csr15val, ioaddr + CSR15); /* Data */ | |
239 | if (startup) iowrite32(csr13val, ioaddr + CSR13); | |
240 | } | |
241 | if (tulip_debug > 1) | |
fa0b9a4c JP |
242 | printk(KERN_DEBUG "%s: Setting CSR15 to %08x/%08x\n", |
243 | dev->name, csr15dir, csr15val); | |
1da177e4 LT |
244 | if (mleaf->type == 4) |
245 | new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18); | |
246 | else | |
247 | new_csr6 = 0x82420000; | |
248 | break; | |
249 | } | |
250 | case 1: case 3: { | |
251 | int phy_num = p[0]; | |
252 | int init_length = p[1]; | |
253 | u16 *misc_info, tmp_info; | |
254 | ||
255 | dev->if_port = 11; | |
256 | new_csr6 = 0x020E0000; | |
257 | if (mleaf->type == 3) { /* 21142 */ | |
258 | u16 *init_sequence = (u16*)(p+2); | |
259 | u16 *reset_sequence = &((u16*)(p+3))[init_length]; | |
260 | int reset_length = p[2 + init_length*2]; | |
261 | misc_info = reset_sequence + reset_length; | |
eb117b17 TV |
262 | if (startup) { |
263 | int timeout = 10; /* max 1 ms */ | |
1da177e4 LT |
264 | for (i = 0; i < reset_length; i++) |
265 | iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15); | |
eb117b17 TV |
266 | |
267 | /* flush posted writes */ | |
268 | ioread32(ioaddr + CSR15); | |
269 | ||
270 | /* Sect 3.10.3 in DP83840A.pdf (p39) */ | |
271 | udelay(500); | |
272 | ||
273 | /* Section 4.2 in DP83840A.pdf (p43) */ | |
274 | /* and IEEE 802.3 "22.2.4.1.1 Reset" */ | |
275 | while (timeout-- && | |
276 | (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) | |
277 | udelay(100); | |
278 | } | |
1da177e4 LT |
279 | for (i = 0; i < init_length; i++) |
280 | iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15); | |
eb117b17 TV |
281 | |
282 | ioread32(ioaddr + CSR15); /* flush posted writes */ | |
1da177e4 LT |
283 | } else { |
284 | u8 *init_sequence = p + 2; | |
285 | u8 *reset_sequence = p + 3 + init_length; | |
286 | int reset_length = p[2 + init_length]; | |
287 | misc_info = (u16*)(reset_sequence + reset_length); | |
288 | if (startup) { | |
b3bff39a | 289 | int timeout = 10; /* max 1 ms */ |
1da177e4 LT |
290 | iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12); |
291 | for (i = 0; i < reset_length; i++) | |
292 | iowrite32(reset_sequence[i], ioaddr + CSR12); | |
b3bff39a VH |
293 | |
294 | /* flush posted writes */ | |
295 | ioread32(ioaddr + CSR12); | |
296 | ||
297 | /* Sect 3.10.3 in DP83840A.pdf (p39) */ | |
298 | udelay(500); | |
299 | ||
300 | /* Section 4.2 in DP83840A.pdf (p43) */ | |
301 | /* and IEEE 802.3 "22.2.4.1.1 Reset" */ | |
302 | while (timeout-- && | |
303 | (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET)) | |
304 | udelay(100); | |
1da177e4 LT |
305 | } |
306 | for (i = 0; i < init_length; i++) | |
307 | iowrite32(init_sequence[i], ioaddr + CSR12); | |
b3bff39a VH |
308 | |
309 | ioread32(ioaddr + CSR12); /* flush posted writes */ | |
1da177e4 | 310 | } |
b3bff39a | 311 | |
1da177e4 LT |
312 | tmp_info = get_u16(&misc_info[1]); |
313 | if (tmp_info) | |
314 | tp->advertising[phy_num] = tmp_info | 1; | |
315 | if (tmp_info && startup < 2) { | |
316 | if (tp->mii_advertise == 0) | |
317 | tp->mii_advertise = tp->advertising[phy_num]; | |
318 | if (tulip_debug > 1) | |
fa0b9a4c JP |
319 | printk(KERN_DEBUG "%s: Advertising %04x on MII %d\n", |
320 | dev->name, tp->mii_advertise, | |
321 | tp->phys[phy_num]); | |
1da177e4 LT |
322 | tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise); |
323 | } | |
324 | break; | |
325 | } | |
326 | case 5: case 6: { | |
327 | u16 setup[5]; | |
328 | ||
329 | new_csr6 = 0; /* FIXME */ | |
330 | ||
331 | for (i = 0; i < 5; i++) | |
332 | setup[i] = get_u16(&p[i*2 + 1]); | |
333 | ||
334 | if (startup && mtable->has_reset) { | |
335 | struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset]; | |
336 | unsigned char *rst = rleaf->leafdata; | |
337 | if (tulip_debug > 1) | |
fa0b9a4c JP |
338 | printk(KERN_DEBUG "%s: Resetting the transceiver\n", |
339 | dev->name); | |
1da177e4 LT |
340 | for (i = 0; i < rst[0]; i++) |
341 | iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15); | |
342 | } | |
343 | ||
344 | break; | |
345 | } | |
346 | default: | |
fa0b9a4c JP |
347 | printk(KERN_DEBUG "%s: Invalid media table selection %d\n", |
348 | dev->name, mleaf->type); | |
1da177e4 LT |
349 | new_csr6 = 0x020E0000; |
350 | } | |
351 | if (tulip_debug > 1) | |
fa0b9a4c JP |
352 | printk(KERN_DEBUG "%s: Using media type %s, CSR12 is %02x\n", |
353 | dev->name, medianame[dev->if_port], | |
1da177e4 LT |
354 | ioread32(ioaddr + CSR12) & 0xff); |
355 | } else if (tp->chip_id == LC82C168) { | |
356 | if (startup && ! tp->medialock) | |
357 | dev->if_port = tp->mii_cnt ? 11 : 0; | |
358 | if (tulip_debug > 1) | |
fa0b9a4c JP |
359 | printk(KERN_DEBUG "%s: PNIC PHY status is %3.3x, media %s\n", |
360 | dev->name, ioread32(ioaddr + 0xB8), medianame[dev->if_port]); | |
1da177e4 LT |
361 | if (tp->mii_cnt) { |
362 | new_csr6 = 0x810C0000; | |
363 | iowrite32(0x0001, ioaddr + CSR15); | |
364 | iowrite32(0x0201B07A, ioaddr + 0xB8); | |
365 | } else if (startup) { | |
366 | /* Start with 10mbps to do autonegotiation. */ | |
367 | iowrite32(0x32, ioaddr + CSR12); | |
368 | new_csr6 = 0x00420000; | |
369 | iowrite32(0x0001B078, ioaddr + 0xB8); | |
370 | iowrite32(0x0201B078, ioaddr + 0xB8); | |
371 | } else if (dev->if_port == 3 || dev->if_port == 5) { | |
372 | iowrite32(0x33, ioaddr + CSR12); | |
373 | new_csr6 = 0x01860000; | |
374 | /* Trigger autonegotiation. */ | |
375 | iowrite32(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8); | |
376 | } else { | |
377 | iowrite32(0x32, ioaddr + CSR12); | |
378 | new_csr6 = 0x00420000; | |
379 | iowrite32(0x1F078, ioaddr + 0xB8); | |
380 | } | |
381 | } else { /* Unknown chip type with no media table. */ | |
382 | if (tp->default_port == 0) | |
383 | dev->if_port = tp->mii_cnt ? 11 : 3; | |
384 | if (tulip_media_cap[dev->if_port] & MediaIsMII) { | |
385 | new_csr6 = 0x020E0000; | |
386 | } else if (tulip_media_cap[dev->if_port] & MediaIsFx) { | |
387 | new_csr6 = 0x02860000; | |
388 | } else | |
389 | new_csr6 = 0x03860000; | |
390 | if (tulip_debug > 1) | |
fa0b9a4c JP |
391 | printk(KERN_DEBUG "%s: No media description table, assuming %s transceiver, CSR12 %02x\n", |
392 | dev->name, medianame[dev->if_port], | |
393 | ioread32(ioaddr + CSR12)); | |
1da177e4 LT |
394 | } |
395 | ||
396 | tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0); | |
12755c16 RB |
397 | |
398 | mdelay(1); | |
1da177e4 LT |
399 | } |
400 | ||
401 | /* | |
402 | Check the MII negotiated duplex and change the CSR6 setting if | |
403 | required. | |
404 | Return 0 if everything is OK. | |
405 | Return < 0 if the transceiver is missing or has no link beat. | |
406 | */ | |
407 | int tulip_check_duplex(struct net_device *dev) | |
408 | { | |
409 | struct tulip_private *tp = netdev_priv(dev); | |
410 | unsigned int bmsr, lpa, negotiated, new_csr6; | |
411 | ||
412 | bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR); | |
413 | lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA); | |
414 | if (tulip_debug > 1) | |
fa0b9a4c JP |
415 | dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n", |
416 | bmsr, lpa); | |
1da177e4 LT |
417 | if (bmsr == 0xffff) |
418 | return -2; | |
419 | if ((bmsr & BMSR_LSTATUS) == 0) { | |
420 | int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR); | |
421 | if ((new_bmsr & BMSR_LSTATUS) == 0) { | |
422 | if (tulip_debug > 1) | |
fa0b9a4c JP |
423 | dev_info(&dev->dev, |
424 | "No link beat on the MII interface, status %04x\n", | |
425 | new_bmsr); | |
1da177e4 LT |
426 | return -1; |
427 | } | |
428 | } | |
429 | negotiated = lpa & tp->advertising[0]; | |
430 | tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated); | |
431 | ||
432 | new_csr6 = tp->csr6; | |
433 | ||
434 | if (negotiated & LPA_100) new_csr6 &= ~TxThreshold; | |
435 | else new_csr6 |= TxThreshold; | |
436 | if (tp->full_duplex) new_csr6 |= FullDuplex; | |
437 | else new_csr6 &= ~FullDuplex; | |
438 | ||
439 | if (new_csr6 != tp->csr6) { | |
440 | tp->csr6 = new_csr6; | |
441 | tulip_restart_rxtx(tp); | |
442 | ||
443 | if (tulip_debug > 0) | |
fa0b9a4c JP |
444 | dev_info(&dev->dev, |
445 | "Setting %s-duplex based on MII#%d link partner capability of %04x\n", | |
446 | tp->full_duplex ? "full" : "half", | |
447 | tp->phys[0], lpa); | |
1da177e4 LT |
448 | return 1; |
449 | } | |
450 | ||
451 | return 0; | |
452 | } | |
453 | ||
454 | void __devinit tulip_find_mii (struct net_device *dev, int board_idx) | |
455 | { | |
456 | struct tulip_private *tp = netdev_priv(dev); | |
457 | int phyn, phy_idx = 0; | |
458 | int mii_reg0; | |
459 | int mii_advert; | |
460 | unsigned int to_advert, new_bmcr, ane_switch; | |
461 | ||
462 | /* Find the connected MII xcvrs. | |
463 | Doing this in open() would allow detecting external xcvrs later, | |
464 | but takes much time. */ | |
465 | for (phyn = 1; phyn <= 32 && phy_idx < sizeof (tp->phys); phyn++) { | |
466 | int phy = phyn & 0x1f; | |
467 | int mii_status = tulip_mdio_read (dev, phy, MII_BMSR); | |
468 | if ((mii_status & 0x8301) == 0x8001 || | |
8e95a202 JP |
469 | ((mii_status & BMSR_100BASE4) == 0 && |
470 | (mii_status & 0x7800) != 0)) { | |
1da177e4 LT |
471 | /* preserve Becker logic, gain indentation level */ |
472 | } else { | |
473 | continue; | |
474 | } | |
475 | ||
476 | mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR); | |
477 | mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE); | |
478 | ane_switch = 0; | |
479 | ||
480 | /* if not advertising at all, gen an | |
481 | * advertising value from the capability | |
482 | * bits in BMSR | |
483 | */ | |
484 | if ((mii_advert & ADVERTISE_ALL) == 0) { | |
485 | unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR); | |
486 | mii_advert = ((tmpadv >> 6) & 0x3e0) | 1; | |
487 | } | |
488 | ||
489 | if (tp->mii_advertise) { | |
490 | tp->advertising[phy_idx] = | |
491 | to_advert = tp->mii_advertise; | |
492 | } else if (tp->advertising[phy_idx]) { | |
493 | to_advert = tp->advertising[phy_idx]; | |
494 | } else { | |
495 | tp->advertising[phy_idx] = | |
496 | tp->mii_advertise = | |
497 | to_advert = mii_advert; | |
498 | } | |
499 | ||
500 | tp->phys[phy_idx++] = phy; | |
501 | ||
fa0b9a4c | 502 | pr_info("tulip%d: MII transceiver #%d config %04x status %04x advertising %04x\n", |
1da177e4 LT |
503 | board_idx, phy, mii_reg0, mii_status, mii_advert); |
504 | ||
505 | /* Fixup for DLink with miswired PHY. */ | |
506 | if (mii_advert != to_advert) { | |
fa0b9a4c JP |
507 | printk(KERN_DEBUG "tulip%d: Advertising %04x on PHY %d, previously advertising %04x\n", |
508 | board_idx, to_advert, phy, mii_advert); | |
1da177e4 LT |
509 | tulip_mdio_write (dev, phy, 4, to_advert); |
510 | } | |
511 | ||
512 | /* Enable autonegotiation: some boards default to off. */ | |
513 | if (tp->default_port == 0) { | |
514 | new_bmcr = mii_reg0 | BMCR_ANENABLE; | |
515 | if (new_bmcr != mii_reg0) { | |
516 | new_bmcr |= BMCR_ANRESTART; | |
517 | ane_switch = 1; | |
518 | } | |
519 | } | |
520 | /* ...or disable nway, if forcing media */ | |
521 | else { | |
522 | new_bmcr = mii_reg0 & ~BMCR_ANENABLE; | |
523 | if (new_bmcr != mii_reg0) | |
524 | ane_switch = 1; | |
525 | } | |
526 | ||
527 | /* clear out bits we never want at this point */ | |
528 | new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE | | |
529 | BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK | | |
530 | BMCR_RESET); | |
531 | ||
532 | if (tp->full_duplex) | |
533 | new_bmcr |= BMCR_FULLDPLX; | |
534 | if (tulip_media_cap[tp->default_port] & MediaIs100) | |
535 | new_bmcr |= BMCR_SPEED100; | |
536 | ||
537 | if (new_bmcr != mii_reg0) { | |
538 | /* some phys need the ANE switch to | |
539 | * happen before forced media settings | |
540 | * will "take." However, we write the | |
541 | * same value twice in order not to | |
542 | * confuse the sane phys. | |
543 | */ | |
544 | if (ane_switch) { | |
545 | tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr); | |
546 | udelay (10); | |
547 | } | |
548 | tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr); | |
549 | } | |
550 | } | |
551 | tp->mii_cnt = phy_idx; | |
552 | if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) { | |
fa0b9a4c | 553 | pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n", |
1da177e4 LT |
554 | board_idx); |
555 | tp->phys[0] = 1; | |
556 | } | |
557 | } |