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dmfe/tulip: Let dmfe handle DM910x except for SPARC on-board chips
[net-next-2.6.git] / drivers / net / tulip / dmfe.c
CommitLineData
1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
64#define DRV_NAME "dmfe"
65#define DRV_VERSION "1.36.4"
66#define DRV_RELDATE "2002-01-17"
67
68#include <linux/module.h>
69#include <linux/kernel.h>
70#include <linux/string.h>
71#include <linux/timer.h>
72#include <linux/ptrace.h>
73#include <linux/errno.h>
74#include <linux/ioport.h>
75#include <linux/slab.h>
76#include <linux/interrupt.h>
77#include <linux/pci.h>
cb199d42 78#include <linux/dma-mapping.h>
1da177e4
LT		 79#include <linux/init.h>
80#include <linux/netdevice.h>
81#include <linux/etherdevice.h>
82#include <linux/ethtool.h>
83#include <linux/skbuff.h>
84#include <linux/delay.h>
85#include <linux/spinlock.h>
86#include <linux/crc32.h>
87#include <linux/bitops.h>
88
89#include <asm/processor.h>
90#include <asm/io.h>
91#include <asm/dma.h>
92#include <asm/uaccess.h>
93#include <asm/irq.h>
94
4d907069
BH		 95#ifdef CONFIG_TULIP_DM910X
96#include <linux/of.h>
97#endif
98
1da177e4
LT		 99
100/* Board/System/Debug information/definition ---------------- */
101#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
102#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
103#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
104#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
105
106#define DM9102_IO_SIZE 0x80
107#define DM9102A_IO_SIZE 0x100
108#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
109#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
110#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
111#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
112#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
113#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
114#define TX_BUF_ALLOC 0x600
115#define RX_ALLOC_SIZE 0x620
116#define DM910X_RESET 1
117#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
118#define CR6_DEFAULT 0x00080000 /* HD */
119#define CR7_DEFAULT 0x180c1
120#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
121#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
122#define MAX_PACKET_SIZE 1514
123#define DMFE_MAX_MULTICAST 14
124#define RX_COPY_SIZE 100
125#define MAX_CHECK_PACKET 0x8000
126#define DM9801_NOISE_FLOOR 8
127#define DM9802_NOISE_FLOOR 5
128
f1069046
ML		 129#define DMFE_WOL_LINKCHANGE 0x20000000
130#define DMFE_WOL_SAMPLEPACKET 0x10000000
131#define DMFE_WOL_MAGICPACKET 0x08000000
132
133
1da177e4
LT		 134#define DMFE_10MHF 0
135#define DMFE_100MHF 1
136#define DMFE_10MFD 4
137#define DMFE_100MFD 5
138#define DMFE_AUTO 8
139#define DMFE_1M_HPNA 0x10
140
141#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
142#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
143#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
144#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
145#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
146#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
147
148#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
149#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
150#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
151
f67ba792
ML		 152#define DMFE_DBUG(dbug_now, msg, value) \
153 do { \
154 if (dmfe_debug || (dbug_now)) \
155 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
156 (msg), (long) (value)); \
157 } while (0)
1da177e4 158
f67ba792
ML		 159#define SHOW_MEDIA_TYPE(mode) \
160 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
161 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
1da177e4
LT		 162
163
164/* CR9 definition: SROM/MII */
165#define CR9_SROM_READ 0x4800
166#define CR9_SRCS 0x1
167#define CR9_SRCLK 0x2
168#define CR9_CRDOUT 0x8
169#define SROM_DATA_0 0x0
170#define SROM_DATA_1 0x4
171#define PHY_DATA_1 0x20000
172#define PHY_DATA_0 0x00000
173#define MDCLKH 0x10000
174
175#define PHY_POWER_DOWN 0x800
176
177#define SROM_V41_CODE 0x14
178
f67ba792
ML		 179#define SROM_CLK_WRITE(data, ioaddr) \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
181 udelay(5); \
182 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
183 udelay(5); \
184 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
185 udelay(5);
186
187#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 188 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 189 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 190
44c10138
AK		 191#define CHK_IO_SIZE(pci_dev) \
192 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
193 (pci_dev)->revision))
1da177e4
LT		 194
195/* Sten Check */
196#define DEVICE net_device
197
198/* Structure/enum declaration ------------------------------- */
199struct tx_desc {
a31e40f6 200 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 201 char *tx_buf_ptr; /* Data for us */
202 struct tx_desc *next_tx_desc;
203} __attribute__(( aligned(32) ));
204
205struct rx_desc {
a31e40f6 206 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 207 struct sk_buff *rx_skb_ptr; /* Data for us */
208 struct rx_desc *next_rx_desc;
209} __attribute__(( aligned(32) ));
210
211struct dmfe_board_info {
212 u32 chip_id; /* Chip vendor/Device ID */
44c10138 213 u8 chip_revision; /* Chip revision */
ead9bffb 214 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 215 struct pci_dev *pdev; /* PCI device */
216 spinlock_t lock;
217
218 long ioaddr; /* I/O base address */
219 u32 cr0_data;
220 u32 cr5_data;
221 u32 cr6_data;
222 u32 cr7_data;
223 u32 cr15_data;
224
225 /* pointer for memory physical address */
226 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
227 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
228 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
229 dma_addr_t first_tx_desc_dma;
230 dma_addr_t first_rx_desc_dma;
231
232 /* descriptor pointer */
233 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
234 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
235 unsigned char *desc_pool_ptr; /* descriptor pool memory */
236 struct tx_desc *first_tx_desc;
237 struct tx_desc *tx_insert_ptr;
238 struct tx_desc *tx_remove_ptr;
239 struct rx_desc *first_rx_desc;
240 struct rx_desc *rx_insert_ptr;
241 struct rx_desc *rx_ready_ptr; /* packet come pointer */
242 unsigned long tx_packet_cnt; /* transmitted packet count */
243 unsigned long tx_queue_cnt; /* wait to send packet count */
244 unsigned long rx_avail_cnt; /* available rx descriptor count */
245 unsigned long interval_rx_cnt; /* rx packet count a callback time */
246
247 u16 HPNA_command; /* For HPNA register 16 */
248 u16 HPNA_timer; /* For HPNA remote device check */
249 u16 dbug_cnt;
250 u16 NIC_capability; /* NIC media capability */
251 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
252
253 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
254 u8 chip_type; /* Keep DM9102A chip type */
255 u8 media_mode; /* user specify media mode */
256 u8 op_mode; /* real work media mode */
257 u8 phy_addr;
1da177e4
LT		 258 u8 wait_reset; /* Hardware failed, need to reset */
259 u8 dm910x_chk_mode; /* Operating mode check */
260 u8 first_in_callback; /* Flag to record state */
f1069046 261 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 262 struct timer_list timer;
263
1da177e4
LT		 264 /* Driver defined statistic counter */
265 unsigned long tx_fifo_underrun;
266 unsigned long tx_loss_carrier;
267 unsigned long tx_no_carrier;
268 unsigned long tx_late_collision;
269 unsigned long tx_excessive_collision;
270 unsigned long tx_jabber_timeout;
271 unsigned long reset_count;
272 unsigned long reset_cr8;
273 unsigned long reset_fatal;
274 unsigned long reset_TXtimeout;
275
276 /* NIC SROM data */
277 unsigned char srom[128];
278};
279
280enum dmfe_offsets {
281 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
282 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
283 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
284 DCR15 = 0x78
285};
286
287enum dmfe_CR6_bits {
288 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
289 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
290 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
291};
292
293/* Global variable declaration ----------------------------- */
294static int __devinitdata printed_version;
03f54b3d 295static const char version[] __devinitconst =
1da177e4
LT		 296 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
297 DRV_VERSION " (" DRV_RELDATE ")\n";
298
299static int dmfe_debug;
300static unsigned char dmfe_media_mode = DMFE_AUTO;
301static u32 dmfe_cr6_user_set;
302
303/* For module input parameter */
304static int debug;
305static u32 cr6set;
306static unsigned char mode = 8;
307static u8 chkmode = 1;
308static u8 HPNA_mode; /* Default: Low Power/High Speed */
309static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
310static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
311static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
312static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
313 4: TX pause packet */
314
315
316/* function declaration ------------------------------------- */
317static int dmfe_open(struct DEVICE *);
ad096463 318static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 319static int dmfe_stop(struct DEVICE *);
1da177e4 320static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 321static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 322static u16 read_srom_word(long ,int);
7d12e780 323static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 324#ifdef CONFIG_NET_POLL_CONTROLLER
325static void poll_dmfe (struct net_device *dev);
326#endif
327static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
328static void allocate_rx_buffer(struct dmfe_board_info *);
329static void update_cr6(u32, unsigned long);
330static void send_filter_frame(struct DEVICE * ,int);
331static void dm9132_id_table(struct DEVICE * ,int);
332static u16 phy_read(unsigned long, u8, u8, u32);
333static void phy_write(unsigned long, u8, u8, u16, u32);
334static void phy_write_1bit(unsigned long, u32);
335static u16 phy_read_1bit(unsigned long);
336static u8 dmfe_sense_speed(struct dmfe_board_info *);
337static void dmfe_process_mode(struct dmfe_board_info *);
338static void dmfe_timer(unsigned long);
339static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
340static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
341static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
342static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
343static void dmfe_dynamic_reset(struct DEVICE *);
344static void dmfe_free_rxbuffer(struct dmfe_board_info *);
345static void dmfe_init_dm910x(struct DEVICE *);
346static void dmfe_parse_srom(struct dmfe_board_info *);
347static void dmfe_program_DM9801(struct dmfe_board_info *, int);
348static void dmfe_program_DM9802(struct dmfe_board_info *);
349static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
350static void dmfe_set_phyxcer(struct dmfe_board_info *);
351
f67ba792 352/* DM910X network board routine ---------------------------- */
1da177e4 353
2765df58
SH		 354static const struct net_device_ops netdev_ops = {
355 .ndo_open = dmfe_open,
356 .ndo_stop = dmfe_stop,
357 .ndo_start_xmit = dmfe_start_xmit,
358 .ndo_set_multicast_list = dmfe_set_filter_mode,
359 .ndo_change_mtu = eth_change_mtu,
360 .ndo_set_mac_address = eth_mac_addr,
361 .ndo_validate_addr = eth_validate_addr,
362#ifdef CONFIG_NET_POLL_CONTROLLER
363 .ndo_poll_controller = poll_dmfe,
364#endif
365};
366
1da177e4
LT		 367/*
368 * Search DM910X board ,allocate space and register it
369 */
370
371static int __devinit dmfe_init_one (struct pci_dev *pdev,
372 const struct pci_device_id *ent)
373{
374 struct dmfe_board_info *db; /* board information structure */
375 struct net_device *dev;
44c10138 376 u32 pci_pmr;
1da177e4
LT		 377 int i, err;
378
379 DMFE_DBUG(0, "dmfe_init_one()", 0);
380
381 if (!printed_version++)
382 printk(version);
383
4d907069
BH		 384 /*
385 * SPARC on-board DM910x chips should be handled by the main
386 * tulip driver, except for early DM9100s.
387 */
388#ifdef CONFIG_TULIP_DM910X
389 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
390 ent->driver_data == PCI_DM9102_ID) {
391 struct device_node *dp = pci_device_to_OF_node(pdev);
392
393 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
394 printk(KERN_INFO DRV_NAME
395 ": skipping on-board DM910x (use tulip)\n");
396 return -ENODEV;
397 }
398 }
399#endif
400
1da177e4
LT		 401 /* Init network device */
402 dev = alloc_etherdev(sizeof(*db));
403 if (dev == NULL)
404 return -ENOMEM;
1da177e4
LT		 405 SET_NETDEV_DEV(dev, &pdev->dev);
406
284901a9 407 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
f67ba792
ML		 408 printk(KERN_WARNING DRV_NAME
409 ": 32-bit PCI DMA not available.\n");
1da177e4
LT		 410 err = -ENODEV;
411 goto err_out_free;
412 }
413
414 /* Enable Master/IO access, Disable memory access */
415 err = pci_enable_device(pdev);
416 if (err)
417 goto err_out_free;
418
419 if (!pci_resource_start(pdev, 0)) {
420 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
421 err = -ENODEV;
422 goto err_out_disable;
423 }
424
44c10138 425 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
1da177e4
LT		 426 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
427 err = -ENODEV;
428 goto err_out_disable;
429 }
430
431#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
432
433 /* Set Latency Timer 80h */
434 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
435 Need a PCI quirk.. */
436
437 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
438#endif
439
440 if (pci_request_regions(pdev, DRV_NAME)) {
441 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
442 err = -ENODEV;
443 goto err_out_disable;
444 }
445
446 /* Init system & device */
447 db = netdev_priv(dev);
448
449 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 450 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
451 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 452 if (!db->desc_pool_ptr)
453 goto err_out_res;
f67ba792
ML		 454
455 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
456 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 457 if (!db->buf_pool_ptr)
458 goto err_out_free_desc;
1da177e4
LT		 459
460 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
461 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
462 db->buf_pool_start = db->buf_pool_ptr;
463 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
464
465 db->chip_id = ent->driver_data;
466 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 467 db->chip_revision = pdev->revision;
f1069046 468 db->wol_mode = 0;
1da177e4
LT		 469
470 db->pdev = pdev;
471
472 dev->base_addr = db->ioaddr;
473 dev->irq = pdev->irq;
474 pci_set_drvdata(pdev, dev);
2765df58 475 dev->netdev_ops = &netdev_ops;
1da177e4 476 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 477 netif_carrier_off(dev);
1da177e4
LT		 478 spin_lock_init(&db->lock);
479
480 pci_read_config_dword(pdev, 0x50, &pci_pmr);
481 pci_pmr &= 0x70000;
44c10138 482 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 483 db->chip_type = 1; /* DM9102A E3 */
484 else
485 db->chip_type = 0;
486
487 /* read 64 word srom data */
488 for (i = 0; i < 64; i++)
a31e40f6 489 ((__le16 *) db->srom)[i] =
f67ba792 490 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 491
492 /* Set Node address */
493 for (i = 0; i < 6; i++)
494 dev->dev_addr[i] = db->srom[20 + i];
495
496 err = register_netdev (dev);
497 if (err)
74d5e8ac 498 goto err_out_free_buf;
1da177e4 499
e174961c 500 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s, %pM, irq %d.\n",
0795af57
JP		 501 dev->name,
502 ent->driver_data >> 16,
503 pci_name(pdev),
e174961c 504 dev->dev_addr,
0795af57 505 dev->irq);
1da177e4
LT		 506
507 pci_set_master(pdev);
508
509 return 0;
510
74d5e8ac
FT		 511err_out_free_buf:
512 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
513 db->buf_pool_ptr, db->buf_pool_dma_ptr);
514err_out_free_desc:
515 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
516 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 517err_out_res:
518 pci_release_regions(pdev);
519err_out_disable:
520 pci_disable_device(pdev);
521err_out_free:
522 pci_set_drvdata(pdev, NULL);
523 free_netdev(dev);
524
525 return err;
526}
527
528
529static void __devexit dmfe_remove_one (struct pci_dev *pdev)
530{
531 struct net_device *dev = pci_get_drvdata(pdev);
532 struct dmfe_board_info *db = netdev_priv(dev);
533
534 DMFE_DBUG(0, "dmfe_remove_one()", 0);
535
536 if (dev) {
4dc68f3d
ML		 537
538 unregister_netdev(dev);
539
1da177e4
LT		 540 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
541 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
542 db->desc_pool_dma_ptr);
543 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
544 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 545 pci_release_regions(pdev);
546 free_netdev(dev); /* free board information */
4dc68f3d 547
1da177e4
LT		 548 pci_set_drvdata(pdev, NULL);
549 }
550
551 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
552}
553
554
555/*
556 * Open the interface.
557 * The interface is opened whenever "ifconfig" actives it.
558 */
559
560static int dmfe_open(struct DEVICE *dev)
561{
562 int ret;
563 struct dmfe_board_info *db = netdev_priv(dev);
564
565 DMFE_DBUG(0, "dmfe_open", 0);
566
a0607fd3 567 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 568 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 569 if (ret)
570 return ret;
571
572 /* system variable init */
573 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
574 db->tx_packet_cnt = 0;
575 db->tx_queue_cnt = 0;
576 db->rx_avail_cnt = 0;
1da177e4
LT		 577 db->wait_reset = 0;
578
579 db->first_in_callback = 0;
580 db->NIC_capability = 0xf; /* All capability*/
581 db->PHY_reg4 = 0x1e0;
582
583 /* CR6 operation mode decision */
584 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 585 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 586 db->cr6_data |= DMFE_TXTH_256;
587 db->cr0_data = CR0_DEFAULT;
588 db->dm910x_chk_mode=4; /* Enter the normal mode */
589 } else {
590 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
591 db->cr0_data = 0;
592 db->dm910x_chk_mode = 1; /* Enter the check mode */
593 }
594
595 /* Initilize DM910X board */
596 dmfe_init_dm910x(dev);
597
598 /* Active System Interface */
599 netif_wake_queue(dev);
600
601 /* set and active a timer process */
602 init_timer(&db->timer);
603 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
604 db->timer.data = (unsigned long)dev;
605 db->timer.function = &dmfe_timer;
606 add_timer(&db->timer);
607
608 return 0;
609}
610
611
612/* Initilize DM910X board
613 * Reset DM910X board
614 * Initilize TX/Rx descriptor chain structure
615 * Send the set-up frame
616 * Enable Tx/Rx machine
617 */
618
619static void dmfe_init_dm910x(struct DEVICE *dev)
620{
621 struct dmfe_board_info *db = netdev_priv(dev);
622 unsigned long ioaddr = db->ioaddr;
623
624 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
625
626 /* Reset DM910x MAC controller */
627 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
628 udelay(100);
629 outl(db->cr0_data, ioaddr + DCR0);
630 udelay(5);
631
632 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
633 db->phy_addr = 1;
634
635 /* Parser SROM and media mode */
636 dmfe_parse_srom(db);
637 db->media_mode = dmfe_media_mode;
638
639 /* RESET Phyxcer Chip by GPR port bit 7 */
640 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
641 if (db->chip_id == PCI_DM9009_ID) {
642 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
643 mdelay(300); /* Delay 300 ms */
644 }
645 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
646
647 /* Process Phyxcer Media Mode */
648 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
649 dmfe_set_phyxcer(db);
650
651 /* Media Mode Process */
652 if ( !(db->media_mode & DMFE_AUTO) )
653 db->op_mode = db->media_mode; /* Force Mode */
654
655 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
656 dmfe_descriptor_init(db, ioaddr);
657
658 /* Init CR6 to program DM910x operation */
659 update_cr6(db->cr6_data, ioaddr);
660
661 /* Send setup frame */
662 if (db->chip_id == PCI_DM9132_ID)
663 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
664 else
665 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
666
667 /* Init CR7, interrupt active bit */
668 db->cr7_data = CR7_DEFAULT;
669 outl(db->cr7_data, ioaddr + DCR7);
670
671 /* Init CR15, Tx jabber and Rx watchdog timer */
672 outl(db->cr15_data, ioaddr + DCR15);
673
674 /* Enable DM910X Tx/Rx function */
675 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
676 update_cr6(db->cr6_data, ioaddr);
677}
678
679
680/*
681 * Hardware start transmission.
682 * Send a packet to media from the upper layer.
683 */
684
ad096463
SH		 685static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
686 struct DEVICE *dev)
1da177e4
LT		 687{
688 struct dmfe_board_info *db = netdev_priv(dev);
689 struct tx_desc *txptr;
690 unsigned long flags;
691
692 DMFE_DBUG(0, "dmfe_start_xmit", 0);
693
694 /* Resource flag check */
695 netif_stop_queue(dev);
696
697 /* Too large packet check */
698 if (skb->len > MAX_PACKET_SIZE) {
699 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
700 dev_kfree_skb(skb);
ec634fe3 701 return NETDEV_TX_OK;
1da177e4
LT		 702 }
703
704 spin_lock_irqsave(&db->lock, flags);
705
706 /* No Tx resource check, it never happen nromally */
707 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
708 spin_unlock_irqrestore(&db->lock, flags);
f67ba792
ML		 709 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
710 db->tx_queue_cnt);
5b548140 711 return NETDEV_TX_BUSY;
1da177e4
LT		 712 }
713
714 /* Disable NIC interrupt */
715 outl(0, dev->base_addr + DCR7);
716
717 /* transmit this packet */
718 txptr = db->tx_insert_ptr;
d626f62b 719 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 720 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
721
722 /* Point to next transmit free descriptor */
723 db->tx_insert_ptr = txptr->next_tx_desc;
724
725 /* Transmit Packet Process */
726 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
727 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
728 db->tx_packet_cnt++; /* Ready to send */
729 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
730 dev->trans_start = jiffies; /* saved time stamp */
731 } else {
732 db->tx_queue_cnt++; /* queue TX packet */
733 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
734 }
735
736 /* Tx resource check */
737 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
738 netif_wake_queue(dev);
739
740 /* Restore CR7 to enable interrupt */
741 spin_unlock_irqrestore(&db->lock, flags);
742 outl(db->cr7_data, dev->base_addr + DCR7);
743
744 /* free this SKB */
745 dev_kfree_skb(skb);
746
ec634fe3 747 return NETDEV_TX_OK;
1da177e4
LT		 748}
749
750
751/*
752 * Stop the interface.
753 * The interface is stopped when it is brought.
754 */
755
756static int dmfe_stop(struct DEVICE *dev)
757{
758 struct dmfe_board_info *db = netdev_priv(dev);
759 unsigned long ioaddr = dev->base_addr;
760
761 DMFE_DBUG(0, "dmfe_stop", 0);
762
763 /* disable system */
764 netif_stop_queue(dev);
765
766 /* deleted timer */
767 del_timer_sync(&db->timer);
768
769 /* Reset & stop DM910X board */
770 outl(DM910X_RESET, ioaddr + DCR0);
771 udelay(5);
772 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
773
774 /* free interrupt */
775 free_irq(dev->irq, dev);
776
777 /* free allocated rx buffer */
778 dmfe_free_rxbuffer(db);
779
780#if 0
781 /* show statistic counter */
f67ba792
ML		 782 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
783 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
1da177e4
LT		 784 db->tx_fifo_underrun, db->tx_excessive_collision,
785 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
786 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
787 db->reset_fatal, db->reset_TXtimeout);
788#endif
789
790 return 0;
791}
792
793
794/*
795 * DM9102 insterrupt handler
796 * receive the packet to upper layer, free the transmitted packet
797 */
798
7d12e780 799static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 800{
801 struct DEVICE *dev = dev_id;
802 struct dmfe_board_info *db = netdev_priv(dev);
803 unsigned long ioaddr = dev->base_addr;
804 unsigned long flags;
805
806 DMFE_DBUG(0, "dmfe_interrupt()", 0);
807
1da177e4
LT		 808 spin_lock_irqsave(&db->lock, flags);
809
810 /* Got DM910X status */
811 db->cr5_data = inl(ioaddr + DCR5);
812 outl(db->cr5_data, ioaddr + DCR5);
813 if ( !(db->cr5_data & 0xc1) ) {
814 spin_unlock_irqrestore(&db->lock, flags);
815 return IRQ_HANDLED;
816 }
817
818 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
819 outl(0, ioaddr + DCR7);
820
821 /* Check system status */
822 if (db->cr5_data & 0x2000) {
823 /* system bus error happen */
824 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
825 db->reset_fatal++;
826 db->wait_reset = 1; /* Need to RESET */
827 spin_unlock_irqrestore(&db->lock, flags);
828 return IRQ_HANDLED;
829 }
830
831 /* Received the coming packet */
832 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
833 dmfe_rx_packet(dev, db);
834
835 /* reallocate rx descriptor buffer */
836 if (db->rx_avail_cnt<RX_DESC_CNT)
837 allocate_rx_buffer(db);
838
839 /* Free the transmitted descriptor */
840 if ( db->cr5_data & 0x01)
841 dmfe_free_tx_pkt(dev, db);
842
843 /* Mode Check */
844 if (db->dm910x_chk_mode & 0x2) {
845 db->dm910x_chk_mode = 0x4;
846 db->cr6_data |= 0x100;
847 update_cr6(db->cr6_data, db->ioaddr);
848 }
849
850 /* Restore CR7 to enable interrupt mask */
851 outl(db->cr7_data, ioaddr + DCR7);
852
853 spin_unlock_irqrestore(&db->lock, flags);
854 return IRQ_HANDLED;
855}
856
857
858#ifdef CONFIG_NET_POLL_CONTROLLER
859/*
860 * Polling 'interrupt' - used by things like netconsole to send skbs
861 * without having to re-enable interrupts. It's not called while
862 * the interrupt routine is executing.
863 */
864
865static void poll_dmfe (struct net_device *dev)
866{
867 /* disable_irq here is not very nice, but with the lockless
868 interrupt handler we have no other choice. */
869 disable_irq(dev->irq);
7d12e780 870 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 871 enable_irq(dev->irq);
872}
873#endif
874
875/*
876 * Free TX resource after TX complete
877 */
878
879static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
880{
881 struct tx_desc *txptr;
882 unsigned long ioaddr = dev->base_addr;
883 u32 tdes0;
884
885 txptr = db->tx_remove_ptr;
886 while(db->tx_packet_cnt) {
887 tdes0 = le32_to_cpu(txptr->tdes0);
888 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
889 if (tdes0 & 0x80000000)
890 break;
891
892 /* A packet sent completed */
893 db->tx_packet_cnt--;
2765df58 894 dev->stats.tx_packets++;
1da177e4
LT		 895
896 /* Transmit statistic counter */
897 if ( tdes0 != 0x7fffffff ) {
898 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
2765df58
SH		 899 dev->stats.collisions += (tdes0 >> 3) & 0xf;
900 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 901 if (tdes0 & TDES0_ERR_MASK) {
2765df58 902 dev->stats.tx_errors++;
1da177e4
LT		 903
904 if (tdes0 & 0x0002) { /* UnderRun */
905 db->tx_fifo_underrun++;
906 if ( !(db->cr6_data & CR6_SFT) ) {
907 db->cr6_data = db->cr6_data | CR6_SFT;
908 update_cr6(db->cr6_data, db->ioaddr);
909 }
910 }
911 if (tdes0 & 0x0100)
912 db->tx_excessive_collision++;
913 if (tdes0 & 0x0200)
914 db->tx_late_collision++;
915 if (tdes0 & 0x0400)
916 db->tx_no_carrier++;
917 if (tdes0 & 0x0800)
918 db->tx_loss_carrier++;
919 if (tdes0 & 0x4000)
920 db->tx_jabber_timeout++;
921 }
922 }
923
924 txptr = txptr->next_tx_desc;
925 }/* End of while */
926
927 /* Update TX remove pointer to next */
928 db->tx_remove_ptr = txptr;
929
930 /* Send the Tx packet in queue */
931 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
932 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
933 db->tx_packet_cnt++; /* Ready to send */
934 db->tx_queue_cnt--;
935 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
936 dev->trans_start = jiffies; /* saved time stamp */
937 }
938
939 /* Resource available check */
940 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
941 netif_wake_queue(dev); /* Active upper layer, send again */
942}
943
944
945/*
946 * Calculate the CRC valude of the Rx packet
947 * flag = 1 : return the reverse CRC (for the received packet CRC)
948 * 0 : return the normal CRC (for Hash Table index)
949 */
950
951static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
952{
953 u32 crc = crc32(~0, Data, Len);
954 if (flag) crc = ~crc;
955 return crc;
956}
957
958
959/*
960 * Receive the come packet and pass to upper layer
961 */
962
963static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
964{
965 struct rx_desc *rxptr;
4dc68f3d 966 struct sk_buff *skb, *newskb;
1da177e4
LT		 967 int rxlen;
968 u32 rdes0;
969
970 rxptr = db->rx_ready_ptr;
971
972 while(db->rx_avail_cnt) {
973 rdes0 = le32_to_cpu(rxptr->rdes0);
974 if (rdes0 & 0x80000000) /* packet owner check */
975 break;
976
977 db->rx_avail_cnt--;
978 db->interval_rx_cnt++;
979
f67ba792
ML		 980 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
981 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
982
1da177e4
LT		 983 if ( (rdes0 & 0x300) != 0x300) {
984 /* A packet without First/Last flag */
985 /* reuse this SKB */
986 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
987 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
988 } else {
989 /* A packet with First/Last flag */
990 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
991
992 /* error summary bit check */
993 if (rdes0 & 0x8000) {
994 /* This is a error packet */
995 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
2765df58 996 dev->stats.rx_errors++;
1da177e4 997 if (rdes0 & 1)
2765df58 998 dev->stats.rx_fifo_errors++;
1da177e4 999 if (rdes0 & 2)
2765df58 1000 dev->stats.rx_crc_errors++;
1da177e4 1001 if (rdes0 & 0x80)
2765df58 1002 dev->stats.rx_length_errors++;
1da177e4
LT		 1003 }
1004
1005 if ( !(rdes0 & 0x8000) ||
1006 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1007 skb = rxptr->rx_skb_ptr;
1008
1009 /* Received Packet CRC check need or not */
1010 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 1011 (cal_CRC(skb->data, rxlen, 1) !=
1012 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 1013 /* Found a error received packet */
1014 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1015 db->dm910x_chk_mode = 3;
1016 } else {
1017 /* Good packet, send to upper layer */
1018 /* Shorst packet used new SKB */
4dc68f3d
ML		 1019 if ((rxlen < RX_COPY_SIZE) &&
1020 ((newskb = dev_alloc_skb(rxlen + 2))
1021 != NULL)) {
1022
1023 skb = newskb;
1da177e4 1024 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1025 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1026 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1027 skb_put(skb, rxlen),
1028 rxlen);
1da177e4 1029 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1030 } else
1da177e4 1031 skb_put(skb, rxlen);
4c13eb66 1032
1da177e4
LT		 1033 skb->protocol = eth_type_trans(skb, dev);
1034 netif_rx(skb);
2765df58
SH		 1035 dev->stats.rx_packets++;
1036 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1037 }
1038 } else {
1039 /* Reuse SKB buffer when the packet is error */
1040 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1041 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1042 }
1043 }
1044
1045 rxptr = rxptr->next_rx_desc;
1046 }
1047
1048 db->rx_ready_ptr = rxptr;
1049}
1050
1da177e4
LT		 1051/*
1052 * Set DM910X multicast address
1053 */
1054
1055static void dmfe_set_filter_mode(struct DEVICE * dev)
1056{
1057 struct dmfe_board_info *db = netdev_priv(dev);
1058 unsigned long flags;
1059
1060 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1061 spin_lock_irqsave(&db->lock, flags);
1062
1063 if (dev->flags & IFF_PROMISC) {
1064 DMFE_DBUG(0, "Enable PROM Mode", 0);
1065 db->cr6_data |= CR6_PM | CR6_PBF;
1066 update_cr6(db->cr6_data, db->ioaddr);
1067 spin_unlock_irqrestore(&db->lock, flags);
1068 return;
1069 }
1070
1071 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1072 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1073 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1074 db->cr6_data |= CR6_PAM;
1075 spin_unlock_irqrestore(&db->lock, flags);
1076 return;
1077 }
1078
1079 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1080 if (db->chip_id == PCI_DM9132_ID)
1081 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1082 else
1083 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1084 spin_unlock_irqrestore(&db->lock, flags);
1085}
1086
f1069046
ML		 1087/*
1088 * Ethtool interace
1089 */
1090
1091static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1092 struct ethtool_drvinfo *info)
1093{
1094 struct dmfe_board_info *np = netdev_priv(dev);
1095
1096 strcpy(info->driver, DRV_NAME);
1097 strcpy(info->version, DRV_VERSION);
1098 if (np->pdev)
1099 strcpy(info->bus_info, pci_name(np->pdev));
1100 else
1101 sprintf(info->bus_info, "EISA 0x%lx %d",
1102 dev->base_addr, dev->irq);
1103}
1104
f1069046
ML		 1105static int dmfe_ethtool_set_wol(struct net_device *dev,
1106 struct ethtool_wolinfo *wolinfo)
1107{
1108 struct dmfe_board_info *db = netdev_priv(dev);
1109
1110 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1111 WAKE_ARP | WAKE_MAGICSECURE))
1112 return -EOPNOTSUPP;
1113
1114 db->wol_mode = wolinfo->wolopts;
1115 return 0;
1116}
1117
1118static void dmfe_ethtool_get_wol(struct net_device *dev,
1119 struct ethtool_wolinfo *wolinfo)
1120{
1121 struct dmfe_board_info *db = netdev_priv(dev);
1122
1123 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1124 wolinfo->wolopts = db->wol_mode;
1125 return;
1126}
1127
1128
7282d491 1129static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1130 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1131 .get_link = ethtool_op_get_link,
f1069046
ML		 1132 .set_wol = dmfe_ethtool_set_wol,
1133 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1134};
1135
1136/*
1137 * A periodic timer routine
1138 * Dynamic media sense, allocate Rx buffer...
1139 */
1140
1141static void dmfe_timer(unsigned long data)
1142{
1143 u32 tmp_cr8;
1144 unsigned char tmp_cr12;
1145 struct DEVICE *dev = (struct DEVICE *) data;
1146 struct dmfe_board_info *db = netdev_priv(dev);
1147 unsigned long flags;
1148
cfa51b9d
ML		 1149 int link_ok, link_ok_phy;
1150
1da177e4
LT		 1151 DMFE_DBUG(0, "dmfe_timer()", 0);
1152 spin_lock_irqsave(&db->lock, flags);
1153
1154 /* Media mode process when Link OK before enter this route */
1155 if (db->first_in_callback == 0) {
1156 db->first_in_callback = 1;
1157 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1158 db->cr6_data &= ~0x40000;
1159 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1160 phy_write(db->ioaddr,
1161 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1162 db->cr6_data |= 0x40000;
1163 update_cr6(db->cr6_data, db->ioaddr);
1164 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1165 add_timer(&db->timer);
1166 spin_unlock_irqrestore(&db->lock, flags);
1167 return;
1168 }
1169 }
1170
1171
1172 /* Operating Mode Check */
1173 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1174 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1175 db->dm910x_chk_mode = 0x4;
1176
1177 /* Dynamic reset DM910X : system error or transmit time-out */
1178 tmp_cr8 = inl(db->ioaddr + DCR8);
1179 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1180 db->reset_cr8++;
1181 db->wait_reset = 1;
1182 }
1183 db->interval_rx_cnt = 0;
1184
1185 /* TX polling kick monitor */
1186 if ( db->tx_packet_cnt &&
1187 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1188 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1189
1190 /* TX Timeout */
1191 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1192 db->reset_TXtimeout++;
1193 db->wait_reset = 1;
1194 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1195 dev->name);
1196 }
1197 }
1198
1199 if (db->wait_reset) {
1200 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1201 db->reset_count++;
1202 dmfe_dynamic_reset(dev);
1203 db->first_in_callback = 0;
1204 db->timer.expires = DMFE_TIMER_WUT;
1205 add_timer(&db->timer);
1206 spin_unlock_irqrestore(&db->lock, flags);
1207 return;
1208 }
1209
1210 /* Link status check, Dynamic media type change */
1211 if (db->chip_id == PCI_DM9132_ID)
1212 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1213 else
1214 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1215
1216 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1217 (db->chip_revision == 0x30)) ||
1da177e4 1218 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1219 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1220 /* DM9102A Chip */
1221 if (tmp_cr12 & 2)
cfa51b9d 1222 link_ok = 0;
1da177e4 1223 else
cfa51b9d 1224 link_ok = 1;
1da177e4 1225 }
cfa51b9d
ML		 1226 else
1227 /*0x43 is used instead of 0x3 because bit 6 should represent
1228 link status of external PHY */
1229 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1230
1231
1232 /* If chip reports that link is failed it could be because external
1233 PHY link status pin is not conected correctly to chip
1234 To be sure ask PHY too.
1235 */
1236
1237 /* need a dummy read because of PHY's register latch*/
1238 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1239 link_ok_phy = (phy_read (db->ioaddr,
1240 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1241
cfa51b9d
ML		 1242 if (link_ok_phy != link_ok) {
1243 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1244 link_ok = link_ok | link_ok_phy;
1245 }
1246
1247 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1248 /* Link Failed */
1249 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1250 netif_carrier_off(dev);
1da177e4
LT		 1251
1252 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1253 /* AUTO or force 1M Homerun/Longrun don't need */
1254 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1255 phy_write(db->ioaddr, db->phy_addr,
1256 0, 0x1000, db->chip_id);
1da177e4
LT		 1257
1258 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1259 if (db->media_mode & DMFE_AUTO) {
1260 /* 10/100M link failed, used 1M Home-Net */
1261 db->cr6_data|=0x00040000; /* bit18=1, MII */
1262 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1263 update_cr6(db->cr6_data, db->ioaddr);
1264 }
cfa51b9d
ML		 1265 } else if (!netif_carrier_ok(dev)) {
1266
1267 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1268
1269 /* Auto Sense Speed */
1270 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1271 netif_carrier_on(dev);
1272 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1273 }
1274
cfa51b9d
ML		 1275 dmfe_process_mode(db);
1276 }
1277
1da177e4
LT		 1278 /* HPNA remote command check */
1279 if (db->HPNA_command & 0xf00) {
1280 db->HPNA_timer--;
1281 if (!db->HPNA_timer)
1282 dmfe_HPNA_remote_cmd_chk(db);
1283 }
1284
1285 /* Timer active again */
1286 db->timer.expires = DMFE_TIMER_WUT;
1287 add_timer(&db->timer);
1288 spin_unlock_irqrestore(&db->lock, flags);
1289}
1290
1291
1292/*
1293 * Dynamic reset the DM910X board
1294 * Stop DM910X board
1295 * Free Tx/Rx allocated memory
1296 * Reset DM910X board
1297 * Re-initilize DM910X board
1298 */
1299
1300static void dmfe_dynamic_reset(struct DEVICE *dev)
1301{
1302 struct dmfe_board_info *db = netdev_priv(dev);
1303
1304 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1305
1306 /* Sopt MAC controller */
1307 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1308 update_cr6(db->cr6_data, dev->base_addr);
1309 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1310 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1311
1312 /* Disable upper layer interface */
1313 netif_stop_queue(dev);
1314
1315 /* Free Rx Allocate buffer */
1316 dmfe_free_rxbuffer(db);
1317
1318 /* system variable init */
1319 db->tx_packet_cnt = 0;
1320 db->tx_queue_cnt = 0;
1321 db->rx_avail_cnt = 0;
cfa51b9d 1322 netif_carrier_off(dev);
1da177e4
LT		 1323 db->wait_reset = 0;
1324
1325 /* Re-initilize DM910X board */
1326 dmfe_init_dm910x(dev);
1327
1328 /* Restart upper layer interface */
1329 netif_wake_queue(dev);
1330}
1331
1332
1333/*
1334 * free all allocated rx buffer
1335 */
1336
1337static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1338{
1339 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1340
1341 /* free allocated rx buffer */
1342 while (db->rx_avail_cnt) {
1343 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1344 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1345 db->rx_avail_cnt--;
1346 }
1347}
1348
1349
1350/*
1351 * Reuse the SK buffer
1352 */
1353
1354static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1355{
1356 struct rx_desc *rxptr = db->rx_insert_ptr;
1357
1358 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1359 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1360 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1361 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1362 wmb();
1363 rxptr->rdes0 = cpu_to_le32(0x80000000);
1364 db->rx_avail_cnt++;
1365 db->rx_insert_ptr = rxptr->next_rx_desc;
1366 } else
1367 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1368}
1369
1370
1371/*
1372 * Initialize transmit/Receive descriptor
1373 * Using Chain structure, and allocate Tx/Rx buffer
1374 */
1375
1376static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1377{
1378 struct tx_desc *tmp_tx;
1379 struct rx_desc *tmp_rx;
1380 unsigned char *tmp_buf;
1381 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1382 dma_addr_t tmp_buf_dma;
1383 int i;
1384
1385 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1386
1387 /* tx descriptor start pointer */
1388 db->tx_insert_ptr = db->first_tx_desc;
1389 db->tx_remove_ptr = db->first_tx_desc;
1390 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1391
1392 /* rx descriptor start pointer */
f67ba792
ML		 1393 db->first_rx_desc = (void *)db->first_tx_desc +
1394 sizeof(struct tx_desc) * TX_DESC_CNT;
1395
1396 db->first_rx_desc_dma = db->first_tx_desc_dma +
1397 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1398 db->rx_insert_ptr = db->first_rx_desc;
1399 db->rx_ready_ptr = db->first_rx_desc;
1400 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1401
1402 /* Init Transmit chain */
1403 tmp_buf = db->buf_pool_start;
1404 tmp_buf_dma = db->buf_pool_dma_start;
1405 tmp_tx_dma = db->first_tx_desc_dma;
1406 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1407 tmp_tx->tx_buf_ptr = tmp_buf;
1408 tmp_tx->tdes0 = cpu_to_le32(0);
1409 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1410 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1411 tmp_tx_dma += sizeof(struct tx_desc);
1412 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1413 tmp_tx->next_tx_desc = tmp_tx + 1;
1414 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1415 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1416 }
1417 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1418 tmp_tx->next_tx_desc = db->first_tx_desc;
1419
1420 /* Init Receive descriptor chain */
1421 tmp_rx_dma=db->first_rx_desc_dma;
1422 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1423 tmp_rx->rdes0 = cpu_to_le32(0);
1424 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1425 tmp_rx_dma += sizeof(struct rx_desc);
1426 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1427 tmp_rx->next_rx_desc = tmp_rx + 1;
1428 }
1429 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1430 tmp_rx->next_rx_desc = db->first_rx_desc;
1431
1432 /* pre-allocate Rx buffer */
1433 allocate_rx_buffer(db);
1434}
1435
1436
1437/*
1438 * Update CR6 value
1439 * Firstly stop DM910X , then written value and start
1440 */
1441
1442static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1443{
1444 u32 cr6_tmp;
1445
1446 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1447 outl(cr6_tmp, ioaddr + DCR6);
1448 udelay(5);
1449 outl(cr6_data, ioaddr + DCR6);
1450 udelay(5);
1451}
1452
1453
1454/*
1455 * Send a setup frame for DM9132
1456 * This setup frame initilize DM910X address filter mode
1457*/
1458
1459static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1460{
1461 struct dev_mc_list *mcptr;
1462 u16 * addrptr;
1463 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1464 u32 hash_val;
1465 u16 i, hash_table[4];
1466
1467 DMFE_DBUG(0, "dm9132_id_table()", 0);
1468
1469 /* Node address */
1470 addrptr = (u16 *) dev->dev_addr;
1471 outw(addrptr[0], ioaddr);
1472 ioaddr += 4;
1473 outw(addrptr[1], ioaddr);
1474 ioaddr += 4;
1475 outw(addrptr[2], ioaddr);
1476 ioaddr += 4;
1477
1478 /* Clear Hash Table */
1479 for (i = 0; i < 4; i++)
1480 hash_table[i] = 0x0;
1481
1482 /* broadcast address */
1483 hash_table[3] = 0x8000;
1484
1485 /* the multicast address in Hash Table : 64 bits */
1486 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1487 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1488 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1489 }
1490
1491 /* Write the hash table to MAC MD table */
1492 for (i = 0; i < 4; i++, ioaddr += 4)
1493 outw(hash_table[i], ioaddr);
1494}
1495
1496
1497/*
1498 * Send a setup frame for DM9102/DM9102A
1499 * This setup frame initilize DM910X address filter mode
1500 */
1501
1502static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1503{
1504 struct dmfe_board_info *db = netdev_priv(dev);
1505 struct dev_mc_list *mcptr;
1506 struct tx_desc *txptr;
1507 u16 * addrptr;
1508 u32 * suptr;
1509 int i;
1510
1511 DMFE_DBUG(0, "send_filter_frame()", 0);
1512
1513 txptr = db->tx_insert_ptr;
1514 suptr = (u32 *) txptr->tx_buf_ptr;
1515
1516 /* Node address */
1517 addrptr = (u16 *) dev->dev_addr;
1518 *suptr++ = addrptr[0];
1519 *suptr++ = addrptr[1];
1520 *suptr++ = addrptr[2];
1521
1522 /* broadcast address */
1523 *suptr++ = 0xffff;
1524 *suptr++ = 0xffff;
1525 *suptr++ = 0xffff;
1526
1527 /* fit the multicast address */
1528 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1529 addrptr = (u16 *) mcptr->dmi_addr;
1530 *suptr++ = addrptr[0];
1531 *suptr++ = addrptr[1];
1532 *suptr++ = addrptr[2];
1533 }
1534
1535 for (; i<14; i++) {
1536 *suptr++ = 0xffff;
1537 *suptr++ = 0xffff;
1538 *suptr++ = 0xffff;
1539 }
1540
1541 /* prepare the setup frame */
1542 db->tx_insert_ptr = txptr->next_tx_desc;
1543 txptr->tdes1 = cpu_to_le32(0x890000c0);
1544
1545 /* Resource Check and Send the setup packet */
1546 if (!db->tx_packet_cnt) {
1547 /* Resource Empty */
1548 db->tx_packet_cnt++;
1549 txptr->tdes0 = cpu_to_le32(0x80000000);
1550 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1551 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1552 update_cr6(db->cr6_data, dev->base_addr);
1553 dev->trans_start = jiffies;
1554 } else
1555 db->tx_queue_cnt++; /* Put in TX queue */
1556}
1557
1558
1559/*
1560 * Allocate rx buffer,
1561 * As possible as allocate maxiumn Rx buffer
1562 */
1563
1564static void allocate_rx_buffer(struct dmfe_board_info *db)
1565{
1566 struct rx_desc *rxptr;
1567 struct sk_buff *skb;
1568
1569 rxptr = db->rx_insert_ptr;
1570
1571 while(db->rx_avail_cnt < RX_DESC_CNT) {
1572 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1573 break;
1574 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1575 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1576 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1577 wmb();
1578 rxptr->rdes0 = cpu_to_le32(0x80000000);
1579 rxptr = rxptr->next_rx_desc;
1580 db->rx_avail_cnt++;
1581 }
1582
1583 db->rx_insert_ptr = rxptr;
1584}
1585
1586
1587/*
1588 * Read one word data from the serial ROM
1589 */
1590
1591static u16 read_srom_word(long ioaddr, int offset)
1592{
1593 int i;
1594 u16 srom_data = 0;
1595 long cr9_ioaddr = ioaddr + DCR9;
1596
1597 outl(CR9_SROM_READ, cr9_ioaddr);
1598 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1599
1600 /* Send the Read Command 110b */
1601 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1602 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1603 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1604
1605 /* Send the offset */
1606 for (i = 5; i >= 0; i--) {
1607 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1608 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1609 }
1610
1611 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1612
1613 for (i = 16; i > 0; i--) {
1614 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1615 udelay(5);
f67ba792
ML		 1616 srom_data = (srom_data << 1) |
1617 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1618 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1619 udelay(5);
1620 }
1621
1622 outl(CR9_SROM_READ, cr9_ioaddr);
1623 return srom_data;
1624}
1625
1626
1627/*
1628 * Auto sense the media mode
1629 */
1630
1631static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1632{
1633 u8 ErrFlag = 0;
1634 u16 phy_mode;
1635
1636 /* CR6 bit18=0, select 10/100M */
1637 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1638
1639 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1640 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1641
1642 if ( (phy_mode & 0x24) == 0x24 ) {
1643 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1644 phy_mode = phy_read(db->ioaddr,
1645 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1646 else /* DM9102/DM9102A */
f67ba792
ML		 1647 phy_mode = phy_read(db->ioaddr,
1648 db->phy_addr, 17, db->chip_id) & 0xf000;
1da177e4
LT		 1649 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1650 switch (phy_mode) {
1651 case 0x1000: db->op_mode = DMFE_10MHF; break;
1652 case 0x2000: db->op_mode = DMFE_10MFD; break;
1653 case 0x4000: db->op_mode = DMFE_100MHF; break;
1654 case 0x8000: db->op_mode = DMFE_100MFD; break;
1655 default: db->op_mode = DMFE_10MHF;
1656 ErrFlag = 1;
1657 break;
1658 }
1659 } else {
1660 db->op_mode = DMFE_10MHF;
1661 DMFE_DBUG(0, "Link Failed :", phy_mode);
1662 ErrFlag = 1;
1663 }
1664
1665 return ErrFlag;
1666}
1667
1668
1669/*
1670 * Set 10/100 phyxcer capability
1671 * AUTO mode : phyxcer register4 is NIC capability
1672 * Force mode: phyxcer register4 is the force media
1673 */
1674
1675static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1676{
1677 u16 phy_reg;
1678
1679 /* Select 10/100M phyxcer */
1680 db->cr6_data &= ~0x40000;
1681 update_cr6(db->cr6_data, db->ioaddr);
1682
1683 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1684 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1685 phy_reg = phy_read(db->ioaddr,
1686 db->phy_addr, 18, db->chip_id) & ~0x1000;
1687
1688 phy_write(db->ioaddr,
1689 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1690 }
1691
1692 /* Phyxcer capability setting */
1693 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1694
1695 if (db->media_mode & DMFE_AUTO) {
1696 /* AUTO Mode */
1697 phy_reg |= db->PHY_reg4;
1698 } else {
1699 /* Force Mode */
1700 switch(db->media_mode) {
1701 case DMFE_10MHF: phy_reg |= 0x20; break;
1702 case DMFE_10MFD: phy_reg |= 0x40; break;
1703 case DMFE_100MHF: phy_reg |= 0x80; break;
1704 case DMFE_100MFD: phy_reg |= 0x100; break;
1705 }
1706 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1707 }
1708
1709 /* Write new capability to Phyxcer Reg4 */
1710 if ( !(phy_reg & 0x01e0)) {
1711 phy_reg|=db->PHY_reg4;
1712 db->media_mode|=DMFE_AUTO;
1713 }
1714 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1715
1716 /* Restart Auto-Negotiation */
1717 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1718 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1719 if ( !db->chip_type )
1720 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1721}
1722
1723
1724/*
1725 * Process op-mode
1726 * AUTO mode : PHY controller in Auto-negotiation Mode
1727 * Force mode: PHY controller in force mode with HUB
1728 * N-way force capability with SWITCH
1729 */
1730
1731static void dmfe_process_mode(struct dmfe_board_info *db)
1732{
1733 u16 phy_reg;
1734
1735 /* Full Duplex Mode Check */
1736 if (db->op_mode & 0x4)
1737 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1738 else
1739 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1740
1741 /* Transciver Selection */
1742 if (db->op_mode & 0x10) /* 1M HomePNA */
1743 db->cr6_data |= 0x40000;/* External MII select */
1744 else
1745 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1746
1747 update_cr6(db->cr6_data, db->ioaddr);
1748
1749 /* 10/100M phyxcer force mode need */
1750 if ( !(db->media_mode & 0x18)) {
1751 /* Forece Mode */
1752 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1753 if ( !(phy_reg & 0x1) ) {
1754 /* parter without N-Way capability */
1755 phy_reg = 0x0;
1756 switch(db->op_mode) {
1757 case DMFE_10MHF: phy_reg = 0x0; break;
1758 case DMFE_10MFD: phy_reg = 0x100; break;
1759 case DMFE_100MHF: phy_reg = 0x2000; break;
1760 case DMFE_100MFD: phy_reg = 0x2100; break;
1761 }
f67ba792
ML		 1762 phy_write(db->ioaddr,
1763 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1764 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1765 mdelay(20);
f67ba792
ML		 1766 phy_write(db->ioaddr,
1767 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1768 }
1769 }
1770}
1771
1772
1773/*
1774 * Write a word to Phy register
1775 */
1776
f67ba792
ML		 1777static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1778 u16 phy_data, u32 chip_id)
1da177e4
LT		 1779{
1780 u16 i;
1781 unsigned long ioaddr;
1782
1783 if (chip_id == PCI_DM9132_ID) {
1784 ioaddr = iobase + 0x80 + offset * 4;
1785 outw(phy_data, ioaddr);
1786 } else {
1787 /* DM9102/DM9102A Chip */
1788 ioaddr = iobase + DCR9;
1789
1790 /* Send 33 synchronization clock to Phy controller */
1791 for (i = 0; i < 35; i++)
1792 phy_write_1bit(ioaddr, PHY_DATA_1);
1793
1794 /* Send start command(01) to Phy */
1795 phy_write_1bit(ioaddr, PHY_DATA_0);
1796 phy_write_1bit(ioaddr, PHY_DATA_1);
1797
1798 /* Send write command(01) to Phy */
1799 phy_write_1bit(ioaddr, PHY_DATA_0);
1800 phy_write_1bit(ioaddr, PHY_DATA_1);
1801
1802 /* Send Phy address */
1803 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1804 phy_write_1bit(ioaddr,
1805 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1806
1807 /* Send register address */
1808 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1809 phy_write_1bit(ioaddr,
1810 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1811
1812 /* written trasnition */
1813 phy_write_1bit(ioaddr, PHY_DATA_1);
1814 phy_write_1bit(ioaddr, PHY_DATA_0);
1815
1816 /* Write a word data to PHY controller */
1817 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1818 phy_write_1bit(ioaddr,
1819 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1820 }
1821}
1822
1823
1824/*
1825 * Read a word data from phy register
1826 */
1827
1828static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1829{
1830 int i;
1831 u16 phy_data;
1832 unsigned long ioaddr;
1833
1834 if (chip_id == PCI_DM9132_ID) {
1835 /* DM9132 Chip */
1836 ioaddr = iobase + 0x80 + offset * 4;
1837 phy_data = inw(ioaddr);
1838 } else {
1839 /* DM9102/DM9102A Chip */
1840 ioaddr = iobase + DCR9;
1841
1842 /* Send 33 synchronization clock to Phy controller */
1843 for (i = 0; i < 35; i++)
1844 phy_write_1bit(ioaddr, PHY_DATA_1);
1845
1846 /* Send start command(01) to Phy */
1847 phy_write_1bit(ioaddr, PHY_DATA_0);
1848 phy_write_1bit(ioaddr, PHY_DATA_1);
1849
1850 /* Send read command(10) to Phy */
1851 phy_write_1bit(ioaddr, PHY_DATA_1);
1852 phy_write_1bit(ioaddr, PHY_DATA_0);
1853
1854 /* Send Phy address */
1855 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1856 phy_write_1bit(ioaddr,
1857 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1858
1859 /* Send register address */
1860 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1861 phy_write_1bit(ioaddr,
1862 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1863
1864 /* Skip transition state */
1865 phy_read_1bit(ioaddr);
1866
1867 /* read 16bit data */
1868 for (phy_data = 0, i = 0; i < 16; i++) {
1869 phy_data <<= 1;
1870 phy_data |= phy_read_1bit(ioaddr);
1871 }
1872 }
1873
1874 return phy_data;
1875}
1876
1877
1878/*
1879 * Write one bit data to Phy Controller
1880 */
1881
1882static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1883{
1884 outl(phy_data, ioaddr); /* MII Clock Low */
1885 udelay(1);
1886 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1887 udelay(1);
1888 outl(phy_data, ioaddr); /* MII Clock Low */
1889 udelay(1);
1890}
1891
1892
1893/*
1894 * Read one bit phy data from PHY controller
1895 */
1896
1897static u16 phy_read_1bit(unsigned long ioaddr)
1898{
1899 u16 phy_data;
1900
1901 outl(0x50000, ioaddr);
1902 udelay(1);
1903 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1904 outl(0x40000, ioaddr);
1905 udelay(1);
1906
1907 return phy_data;
1908}
1909
1910
1911/*
1912 * Parser SROM and media mode
1913 */
1914
1915static void dmfe_parse_srom(struct dmfe_board_info * db)
1916{
1917 char * srom = db->srom;
1918 int dmfe_mode, tmp_reg;
1919
1920 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1921
1922 /* Init CR15 */
1923 db->cr15_data = CR15_DEFAULT;
1924
1925 /* Check SROM Version */
1926 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1927 /* SROM V4.01 */
1928 /* Get NIC support media mode */
4c93566e 1929 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1930 db->PHY_reg4 = 0;
1931 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1932 switch( db->NIC_capability & tmp_reg ) {
1933 case 0x1: db->PHY_reg4 |= 0x0020; break;
1934 case 0x2: db->PHY_reg4 |= 0x0040; break;
1935 case 0x4: db->PHY_reg4 |= 0x0080; break;
1936 case 0x8: db->PHY_reg4 |= 0x0100; break;
1937 }
1938 }
1939
1940 /* Media Mode Force or not check */
4c93566e
DM		 1941 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1942 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1943 switch(dmfe_mode) {
1944 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1945 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1946 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1947 case 0x100:
1948 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1949 }
1950
1951 /* Special Function setting */
1952 /* VLAN function */
1953 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1954 db->cr15_data |= 0x40;
1955
1956 /* Flow Control */
1957 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1958 db->cr15_data |= 0x400;
1959
1960 /* TX pause packet */
1961 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1962 db->cr15_data |= 0x9800;
1963 }
1964
1965 /* Parse HPNA parameter */
1966 db->HPNA_command = 1;
1967
1968 /* Accept remote command or not */
1969 if (HPNA_rx_cmd == 0)
1970 db->HPNA_command |= 0x8000;
1971
1972 /* Issue remote command & operation mode */
1973 if (HPNA_tx_cmd == 1)
1974 switch(HPNA_mode) { /* Issue Remote Command */
1975 case 0: db->HPNA_command |= 0x0904; break;
1976 case 1: db->HPNA_command |= 0x0a00; break;
1977 case 2: db->HPNA_command |= 0x0506; break;
1978 case 3: db->HPNA_command |= 0x0602; break;
1979 }
1980 else
1981 switch(HPNA_mode) { /* Don't Issue */
1982 case 0: db->HPNA_command |= 0x0004; break;
1983 case 1: db->HPNA_command |= 0x0000; break;
1984 case 2: db->HPNA_command |= 0x0006; break;
1985 case 3: db->HPNA_command |= 0x0002; break;
1986 }
1987
1988 /* Check DM9801 or DM9802 present or not */
1989 db->HPNA_present = 0;
1990 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1991 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1992 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1993 /* DM9801 or DM9802 present */
1994 db->HPNA_timer = 8;
1995 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1996 /* DM9801 HomeRun */
1997 db->HPNA_present = 1;
1998 dmfe_program_DM9801(db, tmp_reg);
1999 } else {
2000 /* DM9802 LongRun */
2001 db->HPNA_present = 2;
2002 dmfe_program_DM9802(db);
2003 }
2004 }
2005
2006}
2007
2008
2009/*
2010 * Init HomeRun DM9801
2011 */
2012
2013static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2014{
2015 uint reg17, reg25;
2016
2017 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2018 switch(HPNA_rev) {
2019 case 0xb900: /* DM9801 E3 */
2020 db->HPNA_command |= 0x1000;
2021 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2022 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2023 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2024 break;
2025 case 0xb901: /* DM9801 E4 */
2026 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2027 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2028 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2029 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2030 break;
2031 case 0xb902: /* DM9801 E5 */
2032 case 0xb903: /* DM9801 E6 */
2033 default:
2034 db->HPNA_command |= 0x1000;
2035 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2036 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2037 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2038 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2039 break;
2040 }
2041 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2042 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2043 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2044}
2045
2046
2047/*
2048 * Init HomeRun DM9802
2049 */
2050
2051static void dmfe_program_DM9802(struct dmfe_board_info * db)
2052{
2053 uint phy_reg;
2054
2055 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2056 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2057 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2058 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2059 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2060}
2061
2062
2063/*
2064 * Check remote HPNA power and speed status. If not correct,
2065 * issue command again.
2066*/
2067
2068static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2069{
2070 uint phy_reg;
2071
2072 /* Got remote device status */
2073 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2074 switch(phy_reg) {
2075 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2076 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2077 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2078 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2079 }
2080
2081 /* Check remote device status match our setting ot not */
2082 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2083 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2084 db->chip_id);
1da177e4
LT		 2085 db->HPNA_timer=8;
2086 } else
2087 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2088}
2089
2090
2091
2092static struct pci_device_id dmfe_pci_tbl[] = {
2093 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2094 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2095 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2096 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2097 { 0, }
2098};
2099MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2100
2101
bc8a8387
ML		 2102#ifdef CONFIG_PM
2103static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2104{
2105 struct net_device *dev = pci_get_drvdata(pci_dev);
2106 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2107 u32 tmp;
bc8a8387
ML		 2108
2109 /* Disable upper layer interface */
2110 netif_device_detach(dev);
2111
2112 /* Disable Tx/Rx */
2113 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2114 update_cr6(db->cr6_data, dev->base_addr);
2115
2116 /* Disable Interrupt */
2117 outl(0, dev->base_addr + DCR7);
2118 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2119
2120 /* Fre RX buffers */
2121 dmfe_free_rxbuffer(db);
2122
f1069046
ML		 2123 /* Enable WOL */
2124 pci_read_config_dword(pci_dev, 0x40, &tmp);
2125 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2126
2127 if (db->wol_mode & WAKE_PHY)
2128 tmp |= DMFE_WOL_LINKCHANGE;
2129 if (db->wol_mode & WAKE_MAGIC)
2130 tmp |= DMFE_WOL_MAGICPACKET;
2131
2132 pci_write_config_dword(pci_dev, 0x40, tmp);
2133
2134 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2135 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2136
bc8a8387 2137 /* Power down device*/
bc8a8387 2138 pci_save_state(pci_dev);
a31e23e1 2139 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2140
2141 return 0;
2142}
2143
2144static int dmfe_resume(struct pci_dev *pci_dev)
2145{
2146 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2147 u32 tmp;
bc8a8387 2148
bc8a8387 2149 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2150 pci_restore_state(pci_dev);
bc8a8387
ML		 2151
2152 /* Re-initilize DM910X board */
2153 dmfe_init_dm910x(dev);
2154
f1069046
ML		 2155 /* Disable WOL */
2156 pci_read_config_dword(pci_dev, 0x40, &tmp);
2157
2158 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2159 pci_write_config_dword(pci_dev, 0x40, tmp);
2160
2161 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2162 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2163
bc8a8387
ML		 2164 /* Restart upper layer interface */
2165 netif_device_attach(dev);
2166
2167 return 0;
2168}
2169#else
2170#define dmfe_suspend NULL
2171#define dmfe_resume NULL
2172#endif
2173
1da177e4
LT		 2174static struct pci_driver dmfe_driver = {
2175 .name = "dmfe",
2176 .id_table = dmfe_pci_tbl,
2177 .probe = dmfe_init_one,
2178 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2179 .suspend = dmfe_suspend,
2180 .resume = dmfe_resume
1da177e4
LT		 2181};
2182
2183MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2184MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2185MODULE_LICENSE("GPL");
2186MODULE_VERSION(DRV_VERSION);
2187
2188module_param(debug, int, 0);
2189module_param(mode, byte, 0);
2190module_param(cr6set, int, 0);
2191module_param(chkmode, byte, 0);
2192module_param(HPNA_mode, byte, 0);
2193module_param(HPNA_rx_cmd, byte, 0);
2194module_param(HPNA_tx_cmd, byte, 0);
2195module_param(HPNA_NoiseFloor, byte, 0);
2196module_param(SF_mode, byte, 0);
2197MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2198MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2199 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2200
2201MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2202 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2203
2204/* Description:
2205 * when user used insmod to add module, system invoked init_module()
2206 * to initilize and register.
2207 */
2208
2209static int __init dmfe_init_module(void)
2210{
2211 int rc;
2212
2213 printk(version);
2214 printed_version = 1;
2215
2216 DMFE_DBUG(0, "init_module() ", debug);
2217
2218 if (debug)
2219 dmfe_debug = debug; /* set debug flag */
2220 if (cr6set)
2221 dmfe_cr6_user_set = cr6set;
2222
2223 switch(mode) {
2224 case DMFE_10MHF:
2225 case DMFE_100MHF:
2226 case DMFE_10MFD:
2227 case DMFE_100MFD:
2228 case DMFE_1M_HPNA:
2229 dmfe_media_mode = mode;
2230 break;
2231 default:dmfe_media_mode = DMFE_AUTO;
2232 break;
2233 }
2234
2235 if (HPNA_mode > 4)
2236 HPNA_mode = 0; /* Default: LP/HS */
2237 if (HPNA_rx_cmd > 1)
2238 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2239 if (HPNA_tx_cmd > 1)
2240 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2241 if (HPNA_NoiseFloor > 15)
2242 HPNA_NoiseFloor = 0;
2243
29917620 2244 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2245 if (rc < 0)
2246 return rc;
2247
2248 return 0;
2249}
2250
2251
2252/*
2253 * Description:
2254 * when user used rmmod to delete module, system invoked clean_module()
2255 * to un-register all registered services.
2256 */
2257
2258static void __exit dmfe_cleanup_module(void)
2259{
2260 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2261 pci_unregister_driver(&dmfe_driver);
2262}
2263
2264module_init(dmfe_init_module);
2265module_exit(dmfe_cleanup_module);
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