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1da177e4
LT		 1/*
2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
5
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 DAVICOM Web-Site: www.davicom.com.tw
17
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
20
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
22
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
25
113aa838 26 Alan Cox <alan@lxorguk.ukuu.org.uk> :
1da177e4
LT		 27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
31
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
36
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
40
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
46
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
51
113aa838 52 Alan Cox <alan@lxorguk.ukuu.org.uk>
f3b197ac 53 Added new PCI identifiers provided by Clear Zhang at ALi
1da177e4
LT		 54 for their 1563 ethernet device.
55
56 TODO
57
1da177e4
LT		 58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
60
61 Test and make sure PCI latency is now correct for all cases.
62*/
63
dde7c8ef
JP		 64#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
65
1da177e4
LT		 66#define DRV_NAME "dmfe"
67#define DRV_VERSION "1.36.4"
68#define DRV_RELDATE "2002-01-17"
69
70#include <linux/module.h>
71#include <linux/kernel.h>
72#include <linux/string.h>
73#include <linux/timer.h>
74#include <linux/ptrace.h>
75#include <linux/errno.h>
76#include <linux/ioport.h>
77#include <linux/slab.h>
78#include <linux/interrupt.h>
79#include <linux/pci.h>
cb199d42 80#include <linux/dma-mapping.h>
1da177e4
LT		 81#include <linux/init.h>
82#include <linux/netdevice.h>
83#include <linux/etherdevice.h>
84#include <linux/ethtool.h>
85#include <linux/skbuff.h>
86#include <linux/delay.h>
87#include <linux/spinlock.h>
88#include <linux/crc32.h>
89#include <linux/bitops.h>
90
91#include <asm/processor.h>
92#include <asm/io.h>
93#include <asm/dma.h>
94#include <asm/uaccess.h>
95#include <asm/irq.h>
96
4d907069
BH		 97#ifdef CONFIG_TULIP_DM910X
98#include <linux/of.h>
99#endif
100
1da177e4
LT		 101
102/* Board/System/Debug information/definition ---------------- */
103#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
104#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
105#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
106#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
107
108#define DM9102_IO_SIZE 0x80
109#define DM9102A_IO_SIZE 0x100
110#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
111#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
112#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
113#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
114#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
115#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
116#define TX_BUF_ALLOC 0x600
117#define RX_ALLOC_SIZE 0x620
118#define DM910X_RESET 1
119#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
120#define CR6_DEFAULT 0x00080000 /* HD */
121#define CR7_DEFAULT 0x180c1
122#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
123#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
124#define MAX_PACKET_SIZE 1514
125#define DMFE_MAX_MULTICAST 14
126#define RX_COPY_SIZE 100
127#define MAX_CHECK_PACKET 0x8000
128#define DM9801_NOISE_FLOOR 8
129#define DM9802_NOISE_FLOOR 5
130
f1069046
ML		 131#define DMFE_WOL_LINKCHANGE 0x20000000
132#define DMFE_WOL_SAMPLEPACKET 0x10000000
133#define DMFE_WOL_MAGICPACKET 0x08000000
134
135
1da177e4
LT		 136#define DMFE_10MHF 0
137#define DMFE_100MHF 1
138#define DMFE_10MFD 4
139#define DMFE_100MFD 5
140#define DMFE_AUTO 8
141#define DMFE_1M_HPNA 0x10
142
143#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
144#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
145#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
146#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
147#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
148#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
149
150#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
151#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
152#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
153
dde7c8ef
JP		 154#define DMFE_DBUG(dbug_now, msg, value) \
155 do { \
156 if (dmfe_debug || (dbug_now)) \
157 pr_err("%s %lx\n", \
158 (msg), (long) (value)); \
f67ba792 159 } while (0)
1da177e4 160
dde7c8ef
JP		 161#define SHOW_MEDIA_TYPE(mode) \
162 pr_info("Change Speed to %sMhz %s duplex\n" , \
163 (mode & 1) ? "100":"10", \
164 (mode & 4) ? "full":"half");
1da177e4
LT		 165
166
167/* CR9 definition: SROM/MII */
168#define CR9_SROM_READ 0x4800
169#define CR9_SRCS 0x1
170#define CR9_SRCLK 0x2
171#define CR9_CRDOUT 0x8
172#define SROM_DATA_0 0x0
173#define SROM_DATA_1 0x4
174#define PHY_DATA_1 0x20000
175#define PHY_DATA_0 0x00000
176#define MDCLKH 0x10000
177
178#define PHY_POWER_DOWN 0x800
179
180#define SROM_V41_CODE 0x14
181
f67ba792
ML		 182#define SROM_CLK_WRITE(data, ioaddr) \
183 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
184 udelay(5); \
185 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
186 udelay(5); \
187 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
188 udelay(5);
189
190#define __CHK_IO_SIZE(pci_id, dev_rev) \
44c10138 191 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
f67ba792 192 DM9102A_IO_SIZE: DM9102_IO_SIZE)
1da177e4 193
44c10138
AK		 194#define CHK_IO_SIZE(pci_dev) \
195 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
196 (pci_dev)->revision))
1da177e4
LT		 197
198/* Sten Check */
199#define DEVICE net_device
200
201/* Structure/enum declaration ------------------------------- */
202struct tx_desc {
a31e40f6 203 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
1da177e4
LT		 204 char *tx_buf_ptr; /* Data for us */
205 struct tx_desc *next_tx_desc;
206} __attribute__(( aligned(32) ));
207
208struct rx_desc {
a31e40f6 209 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
1da177e4
LT		 210 struct sk_buff *rx_skb_ptr; /* Data for us */
211 struct rx_desc *next_rx_desc;
212} __attribute__(( aligned(32) ));
213
214struct dmfe_board_info {
215 u32 chip_id; /* Chip vendor/Device ID */
44c10138 216 u8 chip_revision; /* Chip revision */
ead9bffb 217 struct DEVICE *next_dev; /* next device */
1da177e4
LT		 218 struct pci_dev *pdev; /* PCI device */
219 spinlock_t lock;
220
221 long ioaddr; /* I/O base address */
222 u32 cr0_data;
223 u32 cr5_data;
224 u32 cr6_data;
225 u32 cr7_data;
226 u32 cr15_data;
227
228 /* pointer for memory physical address */
229 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
230 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
231 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
232 dma_addr_t first_tx_desc_dma;
233 dma_addr_t first_rx_desc_dma;
234
235 /* descriptor pointer */
236 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
237 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
238 unsigned char *desc_pool_ptr; /* descriptor pool memory */
239 struct tx_desc *first_tx_desc;
240 struct tx_desc *tx_insert_ptr;
241 struct tx_desc *tx_remove_ptr;
242 struct rx_desc *first_rx_desc;
243 struct rx_desc *rx_insert_ptr;
244 struct rx_desc *rx_ready_ptr; /* packet come pointer */
245 unsigned long tx_packet_cnt; /* transmitted packet count */
246 unsigned long tx_queue_cnt; /* wait to send packet count */
247 unsigned long rx_avail_cnt; /* available rx descriptor count */
248 unsigned long interval_rx_cnt; /* rx packet count a callback time */
249
250 u16 HPNA_command; /* For HPNA register 16 */
251 u16 HPNA_timer; /* For HPNA remote device check */
252 u16 dbug_cnt;
253 u16 NIC_capability; /* NIC media capability */
254 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
255
256 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
257 u8 chip_type; /* Keep DM9102A chip type */
258 u8 media_mode; /* user specify media mode */
259 u8 op_mode; /* real work media mode */
260 u8 phy_addr;
1da177e4
LT		 261 u8 wait_reset; /* Hardware failed, need to reset */
262 u8 dm910x_chk_mode; /* Operating mode check */
263 u8 first_in_callback; /* Flag to record state */
f1069046 264 u8 wol_mode; /* user WOL settings */
1da177e4
LT		 265 struct timer_list timer;
266
1da177e4
LT		 267 /* Driver defined statistic counter */
268 unsigned long tx_fifo_underrun;
269 unsigned long tx_loss_carrier;
270 unsigned long tx_no_carrier;
271 unsigned long tx_late_collision;
272 unsigned long tx_excessive_collision;
273 unsigned long tx_jabber_timeout;
274 unsigned long reset_count;
275 unsigned long reset_cr8;
276 unsigned long reset_fatal;
277 unsigned long reset_TXtimeout;
278
279 /* NIC SROM data */
280 unsigned char srom[128];
281};
282
283enum dmfe_offsets {
284 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
285 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
286 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
287 DCR15 = 0x78
288};
289
290enum dmfe_CR6_bits {
291 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
292 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
293 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
294};
295
296/* Global variable declaration ----------------------------- */
297static int __devinitdata printed_version;
03f54b3d 298static const char version[] __devinitconst =
1da177e4
LT		 299 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
300 DRV_VERSION " (" DRV_RELDATE ")\n";
301
302static int dmfe_debug;
303static unsigned char dmfe_media_mode = DMFE_AUTO;
304static u32 dmfe_cr6_user_set;
305
306/* For module input parameter */
307static int debug;
308static u32 cr6set;
309static unsigned char mode = 8;
310static u8 chkmode = 1;
311static u8 HPNA_mode; /* Default: Low Power/High Speed */
312static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
313static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
314static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
315static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
316 4: TX pause packet */
317
318
319/* function declaration ------------------------------------- */
320static int dmfe_open(struct DEVICE *);
ad096463 321static netdev_tx_t dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
1da177e4 322static int dmfe_stop(struct DEVICE *);
1da177e4 323static void dmfe_set_filter_mode(struct DEVICE *);
7282d491 324static const struct ethtool_ops netdev_ethtool_ops;
1da177e4 325static u16 read_srom_word(long ,int);
7d12e780 326static irqreturn_t dmfe_interrupt(int , void *);
1da177e4
LT		 327#ifdef CONFIG_NET_POLL_CONTROLLER
328static void poll_dmfe (struct net_device *dev);
329#endif
330static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
331static void allocate_rx_buffer(struct dmfe_board_info *);
332static void update_cr6(u32, unsigned long);
4302b67e
JP		 333static void send_filter_frame(struct DEVICE *);
334static void dm9132_id_table(struct DEVICE *);
1da177e4
LT		 335static u16 phy_read(unsigned long, u8, u8, u32);
336static void phy_write(unsigned long, u8, u8, u16, u32);
337static void phy_write_1bit(unsigned long, u32);
338static u16 phy_read_1bit(unsigned long);
339static u8 dmfe_sense_speed(struct dmfe_board_info *);
340static void dmfe_process_mode(struct dmfe_board_info *);
341static void dmfe_timer(unsigned long);
342static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
343static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
344static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
345static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
346static void dmfe_dynamic_reset(struct DEVICE *);
347static void dmfe_free_rxbuffer(struct dmfe_board_info *);
348static void dmfe_init_dm910x(struct DEVICE *);
349static void dmfe_parse_srom(struct dmfe_board_info *);
350static void dmfe_program_DM9801(struct dmfe_board_info *, int);
351static void dmfe_program_DM9802(struct dmfe_board_info *);
352static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
353static void dmfe_set_phyxcer(struct dmfe_board_info *);
354
f67ba792 355/* DM910X network board routine ---------------------------- */
1da177e4 356
2765df58
SH		 357static const struct net_device_ops netdev_ops = {
358 .ndo_open = dmfe_open,
359 .ndo_stop = dmfe_stop,
360 .ndo_start_xmit = dmfe_start_xmit,
361 .ndo_set_multicast_list = dmfe_set_filter_mode,
362 .ndo_change_mtu = eth_change_mtu,
363 .ndo_set_mac_address = eth_mac_addr,
364 .ndo_validate_addr = eth_validate_addr,
365#ifdef CONFIG_NET_POLL_CONTROLLER
366 .ndo_poll_controller = poll_dmfe,
367#endif
368};
369
1da177e4
LT		 370/*
371 * Search DM910X board ,allocate space and register it
372 */
373
374static int __devinit dmfe_init_one (struct pci_dev *pdev,
375 const struct pci_device_id *ent)
376{
377 struct dmfe_board_info *db; /* board information structure */
378 struct net_device *dev;
44c10138 379 u32 pci_pmr;
1da177e4
LT		 380 int i, err;
381
382 DMFE_DBUG(0, "dmfe_init_one()", 0);
383
384 if (!printed_version++)
385 printk(version);
386
4d907069
BH		 387 /*
388 * SPARC on-board DM910x chips should be handled by the main
389 * tulip driver, except for early DM9100s.
390 */
391#ifdef CONFIG_TULIP_DM910X
392 if ((ent->driver_data == PCI_DM9100_ID && pdev->revision >= 0x30) ||
393 ent->driver_data == PCI_DM9102_ID) {
394 struct device_node *dp = pci_device_to_OF_node(pdev);
395
396 if (dp && of_get_property(dp, "local-mac-address", NULL)) {
dde7c8ef 397 pr_info("skipping on-board DM910x (use tulip)\n");
4d907069
BH		 398 return -ENODEV;
399 }
400 }
401#endif
402
1da177e4
LT		 403 /* Init network device */
404 dev = alloc_etherdev(sizeof(*db));
405 if (dev == NULL)
406 return -ENOMEM;
1da177e4
LT		 407 SET_NETDEV_DEV(dev, &pdev->dev);
408
284901a9 409 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
dde7c8ef 410 pr_warning("32-bit PCI DMA not available\n");
1da177e4
LT		 411 err = -ENODEV;
412 goto err_out_free;
413 }
414
415 /* Enable Master/IO access, Disable memory access */
416 err = pci_enable_device(pdev);
417 if (err)
418 goto err_out_free;
419
420 if (!pci_resource_start(pdev, 0)) {
dde7c8ef 421 pr_err("I/O base is zero\n");
1da177e4
LT		 422 err = -ENODEV;
423 goto err_out_disable;
424 }
425
44c10138 426 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
dde7c8ef 427 pr_err("Allocated I/O size too small\n");
1da177e4
LT		 428 err = -ENODEV;
429 goto err_out_disable;
430 }
431
432#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
433
434 /* Set Latency Timer 80h */
435 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
436 Need a PCI quirk.. */
437
438 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
439#endif
440
441 if (pci_request_regions(pdev, DRV_NAME)) {
dde7c8ef 442 pr_err("Failed to request PCI regions\n");
1da177e4
LT		 443 err = -ENODEV;
444 goto err_out_disable;
445 }
446
447 /* Init system & device */
448 db = netdev_priv(dev);
449
450 /* Allocate Tx/Rx descriptor memory */
f67ba792
ML		 451 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
452 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
74d5e8ac
FT		 453 if (!db->desc_pool_ptr)
454 goto err_out_res;
f67ba792
ML		 455
456 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
457 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
74d5e8ac
FT		 458 if (!db->buf_pool_ptr)
459 goto err_out_free_desc;
1da177e4
LT		 460
461 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
462 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
463 db->buf_pool_start = db->buf_pool_ptr;
464 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
465
466 db->chip_id = ent->driver_data;
467 db->ioaddr = pci_resource_start(pdev, 0);
44c10138 468 db->chip_revision = pdev->revision;
f1069046 469 db->wol_mode = 0;
1da177e4
LT		 470
471 db->pdev = pdev;
472
473 dev->base_addr = db->ioaddr;
474 dev->irq = pdev->irq;
475 pci_set_drvdata(pdev, dev);
2765df58 476 dev->netdev_ops = &netdev_ops;
1da177e4 477 dev->ethtool_ops = &netdev_ethtool_ops;
cfa51b9d 478 netif_carrier_off(dev);
1da177e4
LT		 479 spin_lock_init(&db->lock);
480
481 pci_read_config_dword(pdev, 0x50, &pci_pmr);
482 pci_pmr &= 0x70000;
44c10138 483 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
1da177e4
LT		 484 db->chip_type = 1; /* DM9102A E3 */
485 else
486 db->chip_type = 0;
487
488 /* read 64 word srom data */
489 for (i = 0; i < 64; i++)
a31e40f6 490 ((__le16 *) db->srom)[i] =
f67ba792 491 cpu_to_le16(read_srom_word(db->ioaddr, i));
1da177e4
LT		 492
493 /* Set Node address */
494 for (i = 0; i < 6; i++)
495 dev->dev_addr[i] = db->srom[20 + i];
496
497 err = register_netdev (dev);
498 if (err)
74d5e8ac 499 goto err_out_free_buf;
1da177e4 500
dde7c8ef
JP		 501 dev_info(&dev->dev, "Davicom DM%04lx at pci%s, %pM, irq %d\n",
502 ent->driver_data >> 16,
503 pci_name(pdev), dev->dev_addr, dev->irq);
1da177e4
LT		 504
505 pci_set_master(pdev);
506
507 return 0;
508
74d5e8ac
FT		 509err_out_free_buf:
510 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
511 db->buf_pool_ptr, db->buf_pool_dma_ptr);
512err_out_free_desc:
513 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
514 db->desc_pool_ptr, db->desc_pool_dma_ptr);
1da177e4
LT		 515err_out_res:
516 pci_release_regions(pdev);
517err_out_disable:
518 pci_disable_device(pdev);
519err_out_free:
520 pci_set_drvdata(pdev, NULL);
521 free_netdev(dev);
522
523 return err;
524}
525
526
527static void __devexit dmfe_remove_one (struct pci_dev *pdev)
528{
529 struct net_device *dev = pci_get_drvdata(pdev);
530 struct dmfe_board_info *db = netdev_priv(dev);
531
532 DMFE_DBUG(0, "dmfe_remove_one()", 0);
533
534 if (dev) {
4dc68f3d
ML		 535
536 unregister_netdev(dev);
537
1da177e4
LT		 538 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
539 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
540 db->desc_pool_dma_ptr);
541 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
542 db->buf_pool_ptr, db->buf_pool_dma_ptr);
1da177e4
LT		 543 pci_release_regions(pdev);
544 free_netdev(dev); /* free board information */
4dc68f3d 545
1da177e4
LT		 546 pci_set_drvdata(pdev, NULL);
547 }
548
549 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
550}
551
552
553/*
554 * Open the interface.
555 * The interface is opened whenever "ifconfig" actives it.
556 */
557
558static int dmfe_open(struct DEVICE *dev)
559{
560 int ret;
561 struct dmfe_board_info *db = netdev_priv(dev);
562
563 DMFE_DBUG(0, "dmfe_open", 0);
564
a0607fd3 565 ret = request_irq(dev->irq, dmfe_interrupt,
f67ba792 566 IRQF_SHARED, dev->name, dev);
1da177e4
LT		 567 if (ret)
568 return ret;
569
570 /* system variable init */
571 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
572 db->tx_packet_cnt = 0;
573 db->tx_queue_cnt = 0;
574 db->rx_avail_cnt = 0;
1da177e4
LT		 575 db->wait_reset = 0;
576
577 db->first_in_callback = 0;
578 db->NIC_capability = 0xf; /* All capability*/
579 db->PHY_reg4 = 0x1e0;
580
581 /* CR6 operation mode decision */
582 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
44c10138 583 (db->chip_revision >= 0x30) ) {
1da177e4
LT		 584 db->cr6_data |= DMFE_TXTH_256;
585 db->cr0_data = CR0_DEFAULT;
586 db->dm910x_chk_mode=4; /* Enter the normal mode */
587 } else {
588 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
589 db->cr0_data = 0;
590 db->dm910x_chk_mode = 1; /* Enter the check mode */
591 }
592
593 /* Initilize DM910X board */
594 dmfe_init_dm910x(dev);
595
596 /* Active System Interface */
597 netif_wake_queue(dev);
598
599 /* set and active a timer process */
600 init_timer(&db->timer);
601 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
602 db->timer.data = (unsigned long)dev;
603 db->timer.function = &dmfe_timer;
604 add_timer(&db->timer);
605
606 return 0;
607}
608
609
610/* Initilize DM910X board
611 * Reset DM910X board
612 * Initilize TX/Rx descriptor chain structure
613 * Send the set-up frame
614 * Enable Tx/Rx machine
615 */
616
617static void dmfe_init_dm910x(struct DEVICE *dev)
618{
619 struct dmfe_board_info *db = netdev_priv(dev);
620 unsigned long ioaddr = db->ioaddr;
621
622 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
623
624 /* Reset DM910x MAC controller */
625 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
626 udelay(100);
627 outl(db->cr0_data, ioaddr + DCR0);
628 udelay(5);
629
630 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
631 db->phy_addr = 1;
632
633 /* Parser SROM and media mode */
634 dmfe_parse_srom(db);
635 db->media_mode = dmfe_media_mode;
636
637 /* RESET Phyxcer Chip by GPR port bit 7 */
638 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
639 if (db->chip_id == PCI_DM9009_ID) {
640 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
641 mdelay(300); /* Delay 300 ms */
642 }
643 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
644
645 /* Process Phyxcer Media Mode */
646 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
647 dmfe_set_phyxcer(db);
648
649 /* Media Mode Process */
650 if ( !(db->media_mode & DMFE_AUTO) )
651 db->op_mode = db->media_mode; /* Force Mode */
652
653 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
654 dmfe_descriptor_init(db, ioaddr);
655
656 /* Init CR6 to program DM910x operation */
657 update_cr6(db->cr6_data, ioaddr);
658
659 /* Send setup frame */
660 if (db->chip_id == PCI_DM9132_ID)
4302b67e 661 dm9132_id_table(dev); /* DM9132 */
1da177e4 662 else
4302b67e 663 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 664
665 /* Init CR7, interrupt active bit */
666 db->cr7_data = CR7_DEFAULT;
667 outl(db->cr7_data, ioaddr + DCR7);
668
669 /* Init CR15, Tx jabber and Rx watchdog timer */
670 outl(db->cr15_data, ioaddr + DCR15);
671
672 /* Enable DM910X Tx/Rx function */
673 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
674 update_cr6(db->cr6_data, ioaddr);
675}
676
677
678/*
679 * Hardware start transmission.
680 * Send a packet to media from the upper layer.
681 */
682
ad096463
SH		 683static netdev_tx_t dmfe_start_xmit(struct sk_buff *skb,
684 struct DEVICE *dev)
1da177e4
LT		 685{
686 struct dmfe_board_info *db = netdev_priv(dev);
687 struct tx_desc *txptr;
688 unsigned long flags;
689
690 DMFE_DBUG(0, "dmfe_start_xmit", 0);
691
692 /* Resource flag check */
693 netif_stop_queue(dev);
694
695 /* Too large packet check */
696 if (skb->len > MAX_PACKET_SIZE) {
dde7c8ef 697 pr_err("big packet = %d\n", (u16)skb->len);
1da177e4 698 dev_kfree_skb(skb);
ec634fe3 699 return NETDEV_TX_OK;
1da177e4
LT		 700 }
701
702 spin_lock_irqsave(&db->lock, flags);
703
704 /* No Tx resource check, it never happen nromally */
705 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
706 spin_unlock_irqrestore(&db->lock, flags);
dde7c8ef 707 pr_err("No Tx resource %ld\n", db->tx_queue_cnt);
5b548140 708 return NETDEV_TX_BUSY;
1da177e4
LT		 709 }
710
711 /* Disable NIC interrupt */
712 outl(0, dev->base_addr + DCR7);
713
714 /* transmit this packet */
715 txptr = db->tx_insert_ptr;
d626f62b 716 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
1da177e4
LT		 717 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
718
719 /* Point to next transmit free descriptor */
720 db->tx_insert_ptr = txptr->next_tx_desc;
721
722 /* Transmit Packet Process */
723 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
724 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
725 db->tx_packet_cnt++; /* Ready to send */
726 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
727 dev->trans_start = jiffies; /* saved time stamp */
728 } else {
729 db->tx_queue_cnt++; /* queue TX packet */
730 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
731 }
732
733 /* Tx resource check */
734 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
735 netif_wake_queue(dev);
736
737 /* Restore CR7 to enable interrupt */
738 spin_unlock_irqrestore(&db->lock, flags);
739 outl(db->cr7_data, dev->base_addr + DCR7);
740
741 /* free this SKB */
742 dev_kfree_skb(skb);
743
ec634fe3 744 return NETDEV_TX_OK;
1da177e4
LT		 745}
746
747
748/*
749 * Stop the interface.
750 * The interface is stopped when it is brought.
751 */
752
753static int dmfe_stop(struct DEVICE *dev)
754{
755 struct dmfe_board_info *db = netdev_priv(dev);
756 unsigned long ioaddr = dev->base_addr;
757
758 DMFE_DBUG(0, "dmfe_stop", 0);
759
760 /* disable system */
761 netif_stop_queue(dev);
762
763 /* deleted timer */
764 del_timer_sync(&db->timer);
765
766 /* Reset & stop DM910X board */
767 outl(DM910X_RESET, ioaddr + DCR0);
768 udelay(5);
769 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
770
771 /* free interrupt */
772 free_irq(dev->irq, dev);
773
774 /* free allocated rx buffer */
775 dmfe_free_rxbuffer(db);
776
777#if 0
778 /* show statistic counter */
dde7c8ef
JP		 779 printk("FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
780 db->tx_fifo_underrun, db->tx_excessive_collision,
781 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
782 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
783 db->reset_fatal, db->reset_TXtimeout);
1da177e4
LT		 784#endif
785
786 return 0;
787}
788
789
790/*
791 * DM9102 insterrupt handler
792 * receive the packet to upper layer, free the transmitted packet
793 */
794
7d12e780 795static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
1da177e4
LT		 796{
797 struct DEVICE *dev = dev_id;
798 struct dmfe_board_info *db = netdev_priv(dev);
799 unsigned long ioaddr = dev->base_addr;
800 unsigned long flags;
801
802 DMFE_DBUG(0, "dmfe_interrupt()", 0);
803
1da177e4
LT		 804 spin_lock_irqsave(&db->lock, flags);
805
806 /* Got DM910X status */
807 db->cr5_data = inl(ioaddr + DCR5);
808 outl(db->cr5_data, ioaddr + DCR5);
809 if ( !(db->cr5_data & 0xc1) ) {
810 spin_unlock_irqrestore(&db->lock, flags);
811 return IRQ_HANDLED;
812 }
813
814 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
815 outl(0, ioaddr + DCR7);
816
817 /* Check system status */
818 if (db->cr5_data & 0x2000) {
819 /* system bus error happen */
820 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
821 db->reset_fatal++;
822 db->wait_reset = 1; /* Need to RESET */
823 spin_unlock_irqrestore(&db->lock, flags);
824 return IRQ_HANDLED;
825 }
826
827 /* Received the coming packet */
828 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
829 dmfe_rx_packet(dev, db);
830
831 /* reallocate rx descriptor buffer */
832 if (db->rx_avail_cnt<RX_DESC_CNT)
833 allocate_rx_buffer(db);
834
835 /* Free the transmitted descriptor */
836 if ( db->cr5_data & 0x01)
837 dmfe_free_tx_pkt(dev, db);
838
839 /* Mode Check */
840 if (db->dm910x_chk_mode & 0x2) {
841 db->dm910x_chk_mode = 0x4;
842 db->cr6_data |= 0x100;
843 update_cr6(db->cr6_data, db->ioaddr);
844 }
845
846 /* Restore CR7 to enable interrupt mask */
847 outl(db->cr7_data, ioaddr + DCR7);
848
849 spin_unlock_irqrestore(&db->lock, flags);
850 return IRQ_HANDLED;
851}
852
853
854#ifdef CONFIG_NET_POLL_CONTROLLER
855/*
856 * Polling 'interrupt' - used by things like netconsole to send skbs
857 * without having to re-enable interrupts. It's not called while
858 * the interrupt routine is executing.
859 */
860
861static void poll_dmfe (struct net_device *dev)
862{
863 /* disable_irq here is not very nice, but with the lockless
864 interrupt handler we have no other choice. */
865 disable_irq(dev->irq);
7d12e780 866 dmfe_interrupt (dev->irq, dev);
1da177e4
LT		 867 enable_irq(dev->irq);
868}
869#endif
870
871/*
872 * Free TX resource after TX complete
873 */
874
875static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
876{
877 struct tx_desc *txptr;
878 unsigned long ioaddr = dev->base_addr;
879 u32 tdes0;
880
881 txptr = db->tx_remove_ptr;
882 while(db->tx_packet_cnt) {
883 tdes0 = le32_to_cpu(txptr->tdes0);
dde7c8ef 884 pr_debug("tdes0=%x\n", tdes0);
1da177e4
LT		 885 if (tdes0 & 0x80000000)
886 break;
887
888 /* A packet sent completed */
889 db->tx_packet_cnt--;
2765df58 890 dev->stats.tx_packets++;
1da177e4
LT		 891
892 /* Transmit statistic counter */
893 if ( tdes0 != 0x7fffffff ) {
dde7c8ef 894 pr_debug("tdes0=%x\n", tdes0);
2765df58
SH		 895 dev->stats.collisions += (tdes0 >> 3) & 0xf;
896 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
1da177e4 897 if (tdes0 & TDES0_ERR_MASK) {
2765df58 898 dev->stats.tx_errors++;
1da177e4
LT		 899
900 if (tdes0 & 0x0002) { /* UnderRun */
901 db->tx_fifo_underrun++;
902 if ( !(db->cr6_data & CR6_SFT) ) {
903 db->cr6_data = db->cr6_data | CR6_SFT;
904 update_cr6(db->cr6_data, db->ioaddr);
905 }
906 }
907 if (tdes0 & 0x0100)
908 db->tx_excessive_collision++;
909 if (tdes0 & 0x0200)
910 db->tx_late_collision++;
911 if (tdes0 & 0x0400)
912 db->tx_no_carrier++;
913 if (tdes0 & 0x0800)
914 db->tx_loss_carrier++;
915 if (tdes0 & 0x4000)
916 db->tx_jabber_timeout++;
917 }
918 }
919
920 txptr = txptr->next_tx_desc;
921 }/* End of while */
922
923 /* Update TX remove pointer to next */
924 db->tx_remove_ptr = txptr;
925
926 /* Send the Tx packet in queue */
927 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
928 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
929 db->tx_packet_cnt++; /* Ready to send */
930 db->tx_queue_cnt--;
931 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
932 dev->trans_start = jiffies; /* saved time stamp */
933 }
934
935 /* Resource available check */
936 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
937 netif_wake_queue(dev); /* Active upper layer, send again */
938}
939
940
941/*
942 * Calculate the CRC valude of the Rx packet
943 * flag = 1 : return the reverse CRC (for the received packet CRC)
944 * 0 : return the normal CRC (for Hash Table index)
945 */
946
947static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
948{
949 u32 crc = crc32(~0, Data, Len);
950 if (flag) crc = ~crc;
951 return crc;
952}
953
954
955/*
956 * Receive the come packet and pass to upper layer
957 */
958
959static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
960{
961 struct rx_desc *rxptr;
4dc68f3d 962 struct sk_buff *skb, *newskb;
1da177e4
LT		 963 int rxlen;
964 u32 rdes0;
965
966 rxptr = db->rx_ready_ptr;
967
968 while(db->rx_avail_cnt) {
969 rdes0 = le32_to_cpu(rxptr->rdes0);
970 if (rdes0 & 0x80000000) /* packet owner check */
971 break;
972
973 db->rx_avail_cnt--;
974 db->interval_rx_cnt++;
975
f67ba792
ML		 976 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
977 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
978
1da177e4
LT		 979 if ( (rdes0 & 0x300) != 0x300) {
980 /* A packet without First/Last flag */
981 /* reuse this SKB */
982 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
983 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
984 } else {
985 /* A packet with First/Last flag */
986 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
987
988 /* error summary bit check */
989 if (rdes0 & 0x8000) {
990 /* This is a error packet */
dde7c8ef 991 pr_debug("rdes0: %x\n", rdes0);
2765df58 992 dev->stats.rx_errors++;
1da177e4 993 if (rdes0 & 1)
2765df58 994 dev->stats.rx_fifo_errors++;
1da177e4 995 if (rdes0 & 2)
2765df58 996 dev->stats.rx_crc_errors++;
1da177e4 997 if (rdes0 & 0x80)
2765df58 998 dev->stats.rx_length_errors++;
1da177e4
LT		 999 }
1000
1001 if ( !(rdes0 & 0x8000) ||
1002 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
1003 skb = rxptr->rx_skb_ptr;
1004
1005 /* Received Packet CRC check need or not */
1006 if ( (db->dm910x_chk_mode & 1) &&
689be439
DM		 1007 (cal_CRC(skb->data, rxlen, 1) !=
1008 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
1da177e4
LT		 1009 /* Found a error received packet */
1010 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1011 db->dm910x_chk_mode = 3;
1012 } else {
1013 /* Good packet, send to upper layer */
1014 /* Shorst packet used new SKB */
4dc68f3d
ML		 1015 if ((rxlen < RX_COPY_SIZE) &&
1016 ((newskb = dev_alloc_skb(rxlen + 2))
1017 != NULL)) {
1018
1019 skb = newskb;
1da177e4 1020 /* size less than COPY_SIZE, allocate a rxlen SKB */
1da177e4 1021 skb_reserve(skb, 2); /* 16byte align */
d626f62b
ACM		 1022 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
1023 skb_put(skb, rxlen),
1024 rxlen);
1da177e4 1025 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 1026 } else
1da177e4 1027 skb_put(skb, rxlen);
4c13eb66 1028
1da177e4
LT		 1029 skb->protocol = eth_type_trans(skb, dev);
1030 netif_rx(skb);
2765df58
SH		 1031 dev->stats.rx_packets++;
1032 dev->stats.rx_bytes += rxlen;
1da177e4
LT		 1033 }
1034 } else {
1035 /* Reuse SKB buffer when the packet is error */
1036 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1037 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1038 }
1039 }
1040
1041 rxptr = rxptr->next_rx_desc;
1042 }
1043
1044 db->rx_ready_ptr = rxptr;
1045}
1046
1da177e4
LT		 1047/*
1048 * Set DM910X multicast address
1049 */
1050
1051static void dmfe_set_filter_mode(struct DEVICE * dev)
1052{
1053 struct dmfe_board_info *db = netdev_priv(dev);
1054 unsigned long flags;
4cd24eaf 1055 int mc_count = netdev_mc_count(dev);
1da177e4
LT		 1056
1057 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1058 spin_lock_irqsave(&db->lock, flags);
1059
1060 if (dev->flags & IFF_PROMISC) {
1061 DMFE_DBUG(0, "Enable PROM Mode", 0);
1062 db->cr6_data |= CR6_PM | CR6_PBF;
1063 update_cr6(db->cr6_data, db->ioaddr);
1064 spin_unlock_irqrestore(&db->lock, flags);
1065 return;
1066 }
1067
4cd24eaf
JP		 1068 if (dev->flags & IFF_ALLMULTI || mc_count > DMFE_MAX_MULTICAST) {
1069 DMFE_DBUG(0, "Pass all multicast address", mc_count);
1da177e4
LT		 1070 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1071 db->cr6_data |= CR6_PAM;
1072 spin_unlock_irqrestore(&db->lock, flags);
1073 return;
1074 }
1075
4cd24eaf 1076 DMFE_DBUG(0, "Set multicast address", mc_count);
1da177e4 1077 if (db->chip_id == PCI_DM9132_ID)
4302b67e 1078 dm9132_id_table(dev); /* DM9132 */
1da177e4 1079 else
4302b67e 1080 send_filter_frame(dev); /* DM9102/DM9102A */
1da177e4
LT		 1081 spin_unlock_irqrestore(&db->lock, flags);
1082}
1083
f1069046
ML		 1084/*
1085 * Ethtool interace
1086 */
1087
1088static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1da177e4
LT		 1089 struct ethtool_drvinfo *info)
1090{
1091 struct dmfe_board_info *np = netdev_priv(dev);
1092
1093 strcpy(info->driver, DRV_NAME);
1094 strcpy(info->version, DRV_VERSION);
1095 if (np->pdev)
1096 strcpy(info->bus_info, pci_name(np->pdev));
1097 else
1098 sprintf(info->bus_info, "EISA 0x%lx %d",
1099 dev->base_addr, dev->irq);
1100}
1101
f1069046
ML		 1102static int dmfe_ethtool_set_wol(struct net_device *dev,
1103 struct ethtool_wolinfo *wolinfo)
1104{
1105 struct dmfe_board_info *db = netdev_priv(dev);
1106
1107 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1108 WAKE_ARP | WAKE_MAGICSECURE))
1109 return -EOPNOTSUPP;
1110
1111 db->wol_mode = wolinfo->wolopts;
1112 return 0;
1113}
1114
1115static void dmfe_ethtool_get_wol(struct net_device *dev,
1116 struct ethtool_wolinfo *wolinfo)
1117{
1118 struct dmfe_board_info *db = netdev_priv(dev);
1119
1120 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1121 wolinfo->wolopts = db->wol_mode;
1122 return;
1123}
1124
1125
7282d491 1126static const struct ethtool_ops netdev_ethtool_ops = {
f1069046 1127 .get_drvinfo = dmfe_ethtool_get_drvinfo,
cfa51b9d 1128 .get_link = ethtool_op_get_link,
f1069046
ML		 1129 .set_wol = dmfe_ethtool_set_wol,
1130 .get_wol = dmfe_ethtool_get_wol,
1da177e4
LT		 1131};
1132
1133/*
1134 * A periodic timer routine
1135 * Dynamic media sense, allocate Rx buffer...
1136 */
1137
1138static void dmfe_timer(unsigned long data)
1139{
1140 u32 tmp_cr8;
1141 unsigned char tmp_cr12;
1142 struct DEVICE *dev = (struct DEVICE *) data;
1143 struct dmfe_board_info *db = netdev_priv(dev);
1144 unsigned long flags;
1145
cfa51b9d
ML		 1146 int link_ok, link_ok_phy;
1147
1da177e4
LT		 1148 DMFE_DBUG(0, "dmfe_timer()", 0);
1149 spin_lock_irqsave(&db->lock, flags);
1150
1151 /* Media mode process when Link OK before enter this route */
1152 if (db->first_in_callback == 0) {
1153 db->first_in_callback = 1;
1154 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1155 db->cr6_data &= ~0x40000;
1156 update_cr6(db->cr6_data, db->ioaddr);
f67ba792
ML		 1157 phy_write(db->ioaddr,
1158 db->phy_addr, 0, 0x1000, db->chip_id);
1da177e4
LT		 1159 db->cr6_data |= 0x40000;
1160 update_cr6(db->cr6_data, db->ioaddr);
1161 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1162 add_timer(&db->timer);
1163 spin_unlock_irqrestore(&db->lock, flags);
1164 return;
1165 }
1166 }
1167
1168
1169 /* Operating Mode Check */
1170 if ( (db->dm910x_chk_mode & 0x1) &&
2765df58 1171 (dev->stats.rx_packets > MAX_CHECK_PACKET) )
1da177e4
LT		 1172 db->dm910x_chk_mode = 0x4;
1173
1174 /* Dynamic reset DM910X : system error or transmit time-out */
1175 tmp_cr8 = inl(db->ioaddr + DCR8);
1176 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1177 db->reset_cr8++;
1178 db->wait_reset = 1;
1179 }
1180 db->interval_rx_cnt = 0;
1181
1182 /* TX polling kick monitor */
1183 if ( db->tx_packet_cnt &&
1184 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1185 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1186
1187 /* TX Timeout */
1188 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1189 db->reset_TXtimeout++;
1190 db->wait_reset = 1;
dde7c8ef 1191 dev_warn(&dev->dev, "Tx timeout - resetting\n");
1da177e4
LT		 1192 }
1193 }
1194
1195 if (db->wait_reset) {
1196 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1197 db->reset_count++;
1198 dmfe_dynamic_reset(dev);
1199 db->first_in_callback = 0;
1200 db->timer.expires = DMFE_TIMER_WUT;
1201 add_timer(&db->timer);
1202 spin_unlock_irqrestore(&db->lock, flags);
1203 return;
1204 }
1205
1206 /* Link status check, Dynamic media type change */
1207 if (db->chip_id == PCI_DM9132_ID)
1208 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1209 else
1210 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1211
1212 if ( ((db->chip_id == PCI_DM9102_ID) &&
44c10138 1213 (db->chip_revision == 0x30)) ||
1da177e4 1214 ((db->chip_id == PCI_DM9132_ID) &&
44c10138 1215 (db->chip_revision == 0x10)) ) {
1da177e4
LT		 1216 /* DM9102A Chip */
1217 if (tmp_cr12 & 2)
cfa51b9d 1218 link_ok = 0;
1da177e4 1219 else
cfa51b9d 1220 link_ok = 1;
1da177e4 1221 }
cfa51b9d
ML		 1222 else
1223 /*0x43 is used instead of 0x3 because bit 6 should represent
1224 link status of external PHY */
1225 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1226
1227
1228 /* If chip reports that link is failed it could be because external
1229 PHY link status pin is not conected correctly to chip
1230 To be sure ask PHY too.
1231 */
1232
1233 /* need a dummy read because of PHY's register latch*/
1234 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1235 link_ok_phy = (phy_read (db->ioaddr,
1236 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1da177e4 1237
cfa51b9d
ML		 1238 if (link_ok_phy != link_ok) {
1239 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1240 link_ok = link_ok | link_ok_phy;
1241 }
1242
1243 if ( !link_ok && netif_carrier_ok(dev)) {
1da177e4
LT		 1244 /* Link Failed */
1245 DMFE_DBUG(0, "Link Failed", tmp_cr12);
cfa51b9d 1246 netif_carrier_off(dev);
1da177e4
LT		 1247
1248 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1249 /* AUTO or force 1M Homerun/Longrun don't need */
1250 if ( !(db->media_mode & 0x38) )
f67ba792
ML		 1251 phy_write(db->ioaddr, db->phy_addr,
1252 0, 0x1000, db->chip_id);
1da177e4
LT		 1253
1254 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1255 if (db->media_mode & DMFE_AUTO) {
1256 /* 10/100M link failed, used 1M Home-Net */
1257 db->cr6_data|=0x00040000; /* bit18=1, MII */
1258 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1259 update_cr6(db->cr6_data, db->ioaddr);
1260 }
cfa51b9d
ML		 1261 } else if (!netif_carrier_ok(dev)) {
1262
1263 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1264
1265 /* Auto Sense Speed */
1266 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1267 netif_carrier_on(dev);
1268 SHOW_MEDIA_TYPE(db->op_mode);
1da177e4
LT		 1269 }
1270
cfa51b9d
ML		 1271 dmfe_process_mode(db);
1272 }
1273
1da177e4
LT		 1274 /* HPNA remote command check */
1275 if (db->HPNA_command & 0xf00) {
1276 db->HPNA_timer--;
1277 if (!db->HPNA_timer)
1278 dmfe_HPNA_remote_cmd_chk(db);
1279 }
1280
1281 /* Timer active again */
1282 db->timer.expires = DMFE_TIMER_WUT;
1283 add_timer(&db->timer);
1284 spin_unlock_irqrestore(&db->lock, flags);
1285}
1286
1287
1288/*
1289 * Dynamic reset the DM910X board
1290 * Stop DM910X board
1291 * Free Tx/Rx allocated memory
1292 * Reset DM910X board
1293 * Re-initilize DM910X board
1294 */
1295
1296static void dmfe_dynamic_reset(struct DEVICE *dev)
1297{
1298 struct dmfe_board_info *db = netdev_priv(dev);
1299
1300 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1301
1302 /* Sopt MAC controller */
1303 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1304 update_cr6(db->cr6_data, dev->base_addr);
1305 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1306 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1307
1308 /* Disable upper layer interface */
1309 netif_stop_queue(dev);
1310
1311 /* Free Rx Allocate buffer */
1312 dmfe_free_rxbuffer(db);
1313
1314 /* system variable init */
1315 db->tx_packet_cnt = 0;
1316 db->tx_queue_cnt = 0;
1317 db->rx_avail_cnt = 0;
cfa51b9d 1318 netif_carrier_off(dev);
1da177e4
LT		 1319 db->wait_reset = 0;
1320
1321 /* Re-initilize DM910X board */
1322 dmfe_init_dm910x(dev);
1323
1324 /* Restart upper layer interface */
1325 netif_wake_queue(dev);
1326}
1327
1328
1329/*
1330 * free all allocated rx buffer
1331 */
1332
1333static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1334{
1335 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1336
1337 /* free allocated rx buffer */
1338 while (db->rx_avail_cnt) {
1339 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1340 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1341 db->rx_avail_cnt--;
1342 }
1343}
1344
1345
1346/*
1347 * Reuse the SK buffer
1348 */
1349
1350static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1351{
1352 struct rx_desc *rxptr = db->rx_insert_ptr;
1353
1354 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1355 rxptr->rx_skb_ptr = skb;
f67ba792
ML		 1356 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1357 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1358 wmb();
1359 rxptr->rdes0 = cpu_to_le32(0x80000000);
1360 db->rx_avail_cnt++;
1361 db->rx_insert_ptr = rxptr->next_rx_desc;
1362 } else
1363 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1364}
1365
1366
1367/*
1368 * Initialize transmit/Receive descriptor
1369 * Using Chain structure, and allocate Tx/Rx buffer
1370 */
1371
1372static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1373{
1374 struct tx_desc *tmp_tx;
1375 struct rx_desc *tmp_rx;
1376 unsigned char *tmp_buf;
1377 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1378 dma_addr_t tmp_buf_dma;
1379 int i;
1380
1381 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1382
1383 /* tx descriptor start pointer */
1384 db->tx_insert_ptr = db->first_tx_desc;
1385 db->tx_remove_ptr = db->first_tx_desc;
1386 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1387
1388 /* rx descriptor start pointer */
f67ba792
ML		 1389 db->first_rx_desc = (void *)db->first_tx_desc +
1390 sizeof(struct tx_desc) * TX_DESC_CNT;
1391
1392 db->first_rx_desc_dma = db->first_tx_desc_dma +
1393 sizeof(struct tx_desc) * TX_DESC_CNT;
1da177e4
LT		 1394 db->rx_insert_ptr = db->first_rx_desc;
1395 db->rx_ready_ptr = db->first_rx_desc;
1396 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1397
1398 /* Init Transmit chain */
1399 tmp_buf = db->buf_pool_start;
1400 tmp_buf_dma = db->buf_pool_dma_start;
1401 tmp_tx_dma = db->first_tx_desc_dma;
1402 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1403 tmp_tx->tx_buf_ptr = tmp_buf;
1404 tmp_tx->tdes0 = cpu_to_le32(0);
1405 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1406 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1407 tmp_tx_dma += sizeof(struct tx_desc);
1408 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1409 tmp_tx->next_tx_desc = tmp_tx + 1;
1410 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1411 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1412 }
1413 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1414 tmp_tx->next_tx_desc = db->first_tx_desc;
1415
1416 /* Init Receive descriptor chain */
1417 tmp_rx_dma=db->first_rx_desc_dma;
1418 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1419 tmp_rx->rdes0 = cpu_to_le32(0);
1420 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1421 tmp_rx_dma += sizeof(struct rx_desc);
1422 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1423 tmp_rx->next_rx_desc = tmp_rx + 1;
1424 }
1425 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1426 tmp_rx->next_rx_desc = db->first_rx_desc;
1427
1428 /* pre-allocate Rx buffer */
1429 allocate_rx_buffer(db);
1430}
1431
1432
1433/*
1434 * Update CR6 value
1435 * Firstly stop DM910X , then written value and start
1436 */
1437
1438static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1439{
1440 u32 cr6_tmp;
1441
1442 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1443 outl(cr6_tmp, ioaddr + DCR6);
1444 udelay(5);
1445 outl(cr6_data, ioaddr + DCR6);
1446 udelay(5);
1447}
1448
1449
1450/*
1451 * Send a setup frame for DM9132
1452 * This setup frame initilize DM910X address filter mode
1453*/
1454
4302b67e 1455static void dm9132_id_table(struct DEVICE *dev)
1da177e4 1456{
22bedad3 1457 struct netdev_hw_addr *ha;
1da177e4
LT		 1458 u16 * addrptr;
1459 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1460 u32 hash_val;
1461 u16 i, hash_table[4];
1462
1463 DMFE_DBUG(0, "dm9132_id_table()", 0);
1464
1465 /* Node address */
1466 addrptr = (u16 *) dev->dev_addr;
1467 outw(addrptr[0], ioaddr);
1468 ioaddr += 4;
1469 outw(addrptr[1], ioaddr);
1470 ioaddr += 4;
1471 outw(addrptr[2], ioaddr);
1472 ioaddr += 4;
1473
1474 /* Clear Hash Table */
4302b67e 1475 memset(hash_table, 0, sizeof(hash_table));
1da177e4
LT		 1476
1477 /* broadcast address */
1478 hash_table[3] = 0x8000;
1479
1480 /* the multicast address in Hash Table : 64 bits */
22bedad3
JP		 1481 netdev_for_each_mc_addr(ha, dev) {
1482 hash_val = cal_CRC((char *) ha->addr, 6, 0) & 0x3f;
1da177e4
LT		 1483 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1484 }
1485
1486 /* Write the hash table to MAC MD table */
1487 for (i = 0; i < 4; i++, ioaddr += 4)
1488 outw(hash_table[i], ioaddr);
1489}
1490
1491
1492/*
1493 * Send a setup frame for DM9102/DM9102A
1494 * This setup frame initilize DM910X address filter mode
1495 */
1496
4302b67e 1497static void send_filter_frame(struct DEVICE *dev)
1da177e4
LT		 1498{
1499 struct dmfe_board_info *db = netdev_priv(dev);
22bedad3 1500 struct netdev_hw_addr *ha;
1da177e4
LT		 1501 struct tx_desc *txptr;
1502 u16 * addrptr;
1503 u32 * suptr;
1504 int i;
1505
1506 DMFE_DBUG(0, "send_filter_frame()", 0);
1507
1508 txptr = db->tx_insert_ptr;
1509 suptr = (u32 *) txptr->tx_buf_ptr;
1510
1511 /* Node address */
1512 addrptr = (u16 *) dev->dev_addr;
1513 *suptr++ = addrptr[0];
1514 *suptr++ = addrptr[1];
1515 *suptr++ = addrptr[2];
1516
1517 /* broadcast address */
1518 *suptr++ = 0xffff;
1519 *suptr++ = 0xffff;
1520 *suptr++ = 0xffff;
1521
1522 /* fit the multicast address */
22bedad3
JP		 1523 netdev_for_each_mc_addr(ha, dev) {
1524 addrptr = (u16 *) ha->addr;
1da177e4
LT		 1525 *suptr++ = addrptr[0];
1526 *suptr++ = addrptr[1];
1527 *suptr++ = addrptr[2];
1528 }
1529
4302b67e 1530 for (i = netdev_mc_count(dev); i < 14; i++) {
1da177e4
LT		 1531 *suptr++ = 0xffff;
1532 *suptr++ = 0xffff;
1533 *suptr++ = 0xffff;
1534 }
1535
1536 /* prepare the setup frame */
1537 db->tx_insert_ptr = txptr->next_tx_desc;
1538 txptr->tdes1 = cpu_to_le32(0x890000c0);
1539
1540 /* Resource Check and Send the setup packet */
1541 if (!db->tx_packet_cnt) {
1542 /* Resource Empty */
1543 db->tx_packet_cnt++;
1544 txptr->tdes0 = cpu_to_le32(0x80000000);
1545 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1546 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1547 update_cr6(db->cr6_data, dev->base_addr);
1548 dev->trans_start = jiffies;
1549 } else
1550 db->tx_queue_cnt++; /* Put in TX queue */
1551}
1552
1553
1554/*
1555 * Allocate rx buffer,
1556 * As possible as allocate maxiumn Rx buffer
1557 */
1558
1559static void allocate_rx_buffer(struct dmfe_board_info *db)
1560{
1561 struct rx_desc *rxptr;
1562 struct sk_buff *skb;
1563
1564 rxptr = db->rx_insert_ptr;
1565
1566 while(db->rx_avail_cnt < RX_DESC_CNT) {
1567 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1568 break;
1569 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
f67ba792
ML		 1570 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1571 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1da177e4
LT		 1572 wmb();
1573 rxptr->rdes0 = cpu_to_le32(0x80000000);
1574 rxptr = rxptr->next_rx_desc;
1575 db->rx_avail_cnt++;
1576 }
1577
1578 db->rx_insert_ptr = rxptr;
1579}
1580
1581
1582/*
1583 * Read one word data from the serial ROM
1584 */
1585
1586static u16 read_srom_word(long ioaddr, int offset)
1587{
1588 int i;
1589 u16 srom_data = 0;
1590 long cr9_ioaddr = ioaddr + DCR9;
1591
1592 outl(CR9_SROM_READ, cr9_ioaddr);
1593 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1594
1595 /* Send the Read Command 110b */
1596 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1597 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1598 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1599
1600 /* Send the offset */
1601 for (i = 5; i >= 0; i--) {
1602 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1603 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1604 }
1605
1606 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1607
1608 for (i = 16; i > 0; i--) {
1609 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1610 udelay(5);
f67ba792
ML		 1611 srom_data = (srom_data << 1) |
1612 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1da177e4
LT		 1613 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1614 udelay(5);
1615 }
1616
1617 outl(CR9_SROM_READ, cr9_ioaddr);
1618 return srom_data;
1619}
1620
1621
1622/*
1623 * Auto sense the media mode
1624 */
1625
1626static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1627{
1628 u8 ErrFlag = 0;
1629 u16 phy_mode;
1630
1631 /* CR6 bit18=0, select 10/100M */
1632 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1633
1634 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1635 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1636
1637 if ( (phy_mode & 0x24) == 0x24 ) {
1638 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
f67ba792
ML		 1639 phy_mode = phy_read(db->ioaddr,
1640 db->phy_addr, 7, db->chip_id) & 0xf000;
1da177e4 1641 else /* DM9102/DM9102A */
f67ba792
ML		 1642 phy_mode = phy_read(db->ioaddr,
1643 db->phy_addr, 17, db->chip_id) & 0xf000;
dde7c8ef 1644 pr_debug("Phy_mode %x\n", phy_mode);
1da177e4
LT		 1645 switch (phy_mode) {
1646 case 0x1000: db->op_mode = DMFE_10MHF; break;
1647 case 0x2000: db->op_mode = DMFE_10MFD; break;
1648 case 0x4000: db->op_mode = DMFE_100MHF; break;
1649 case 0x8000: db->op_mode = DMFE_100MFD; break;
1650 default: db->op_mode = DMFE_10MHF;
1651 ErrFlag = 1;
1652 break;
1653 }
1654 } else {
1655 db->op_mode = DMFE_10MHF;
1656 DMFE_DBUG(0, "Link Failed :", phy_mode);
1657 ErrFlag = 1;
1658 }
1659
1660 return ErrFlag;
1661}
1662
1663
1664/*
1665 * Set 10/100 phyxcer capability
1666 * AUTO mode : phyxcer register4 is NIC capability
1667 * Force mode: phyxcer register4 is the force media
1668 */
1669
1670static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1671{
1672 u16 phy_reg;
1673
1674 /* Select 10/100M phyxcer */
1675 db->cr6_data &= ~0x40000;
1676 update_cr6(db->cr6_data, db->ioaddr);
1677
1678 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1679 if (db->chip_id == PCI_DM9009_ID) {
f67ba792
ML		 1680 phy_reg = phy_read(db->ioaddr,
1681 db->phy_addr, 18, db->chip_id) & ~0x1000;
1682
1683 phy_write(db->ioaddr,
1684 db->phy_addr, 18, phy_reg, db->chip_id);
1da177e4
LT		 1685 }
1686
1687 /* Phyxcer capability setting */
1688 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1689
1690 if (db->media_mode & DMFE_AUTO) {
1691 /* AUTO Mode */
1692 phy_reg |= db->PHY_reg4;
1693 } else {
1694 /* Force Mode */
1695 switch(db->media_mode) {
1696 case DMFE_10MHF: phy_reg |= 0x20; break;
1697 case DMFE_10MFD: phy_reg |= 0x40; break;
1698 case DMFE_100MHF: phy_reg |= 0x80; break;
1699 case DMFE_100MFD: phy_reg |= 0x100; break;
1700 }
1701 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1702 }
1703
1704 /* Write new capability to Phyxcer Reg4 */
1705 if ( !(phy_reg & 0x01e0)) {
1706 phy_reg|=db->PHY_reg4;
1707 db->media_mode|=DMFE_AUTO;
1708 }
1709 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1710
1711 /* Restart Auto-Negotiation */
1712 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1713 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1714 if ( !db->chip_type )
1715 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1716}
1717
1718
1719/*
1720 * Process op-mode
1721 * AUTO mode : PHY controller in Auto-negotiation Mode
1722 * Force mode: PHY controller in force mode with HUB
1723 * N-way force capability with SWITCH
1724 */
1725
1726static void dmfe_process_mode(struct dmfe_board_info *db)
1727{
1728 u16 phy_reg;
1729
1730 /* Full Duplex Mode Check */
1731 if (db->op_mode & 0x4)
1732 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1733 else
1734 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1735
1736 /* Transciver Selection */
1737 if (db->op_mode & 0x10) /* 1M HomePNA */
1738 db->cr6_data |= 0x40000;/* External MII select */
1739 else
1740 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1741
1742 update_cr6(db->cr6_data, db->ioaddr);
1743
1744 /* 10/100M phyxcer force mode need */
1745 if ( !(db->media_mode & 0x18)) {
1746 /* Forece Mode */
1747 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1748 if ( !(phy_reg & 0x1) ) {
1749 /* parter without N-Way capability */
1750 phy_reg = 0x0;
1751 switch(db->op_mode) {
1752 case DMFE_10MHF: phy_reg = 0x0; break;
1753 case DMFE_10MFD: phy_reg = 0x100; break;
1754 case DMFE_100MHF: phy_reg = 0x2000; break;
1755 case DMFE_100MFD: phy_reg = 0x2100; break;
1756 }
f67ba792
ML		 1757 phy_write(db->ioaddr,
1758 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1759 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1760 mdelay(20);
f67ba792
ML		 1761 phy_write(db->ioaddr,
1762 db->phy_addr, 0, phy_reg, db->chip_id);
1da177e4
LT		 1763 }
1764 }
1765}
1766
1767
1768/*
1769 * Write a word to Phy register
1770 */
1771
f67ba792
ML		 1772static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1773 u16 phy_data, u32 chip_id)
1da177e4
LT		 1774{
1775 u16 i;
1776 unsigned long ioaddr;
1777
1778 if (chip_id == PCI_DM9132_ID) {
1779 ioaddr = iobase + 0x80 + offset * 4;
1780 outw(phy_data, ioaddr);
1781 } else {
1782 /* DM9102/DM9102A Chip */
1783 ioaddr = iobase + DCR9;
1784
1785 /* Send 33 synchronization clock to Phy controller */
1786 for (i = 0; i < 35; i++)
1787 phy_write_1bit(ioaddr, PHY_DATA_1);
1788
1789 /* Send start command(01) to Phy */
1790 phy_write_1bit(ioaddr, PHY_DATA_0);
1791 phy_write_1bit(ioaddr, PHY_DATA_1);
1792
1793 /* Send write command(01) to Phy */
1794 phy_write_1bit(ioaddr, PHY_DATA_0);
1795 phy_write_1bit(ioaddr, PHY_DATA_1);
1796
1797 /* Send Phy address */
1798 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1799 phy_write_1bit(ioaddr,
1800 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1801
1802 /* Send register address */
1803 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1804 phy_write_1bit(ioaddr,
1805 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1806
1807 /* written trasnition */
1808 phy_write_1bit(ioaddr, PHY_DATA_1);
1809 phy_write_1bit(ioaddr, PHY_DATA_0);
1810
1811 /* Write a word data to PHY controller */
1812 for ( i = 0x8000; i > 0; i >>= 1)
f67ba792
ML		 1813 phy_write_1bit(ioaddr,
1814 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1815 }
1816}
1817
1818
1819/*
1820 * Read a word data from phy register
1821 */
1822
1823static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1824{
1825 int i;
1826 u16 phy_data;
1827 unsigned long ioaddr;
1828
1829 if (chip_id == PCI_DM9132_ID) {
1830 /* DM9132 Chip */
1831 ioaddr = iobase + 0x80 + offset * 4;
1832 phy_data = inw(ioaddr);
1833 } else {
1834 /* DM9102/DM9102A Chip */
1835 ioaddr = iobase + DCR9;
1836
1837 /* Send 33 synchronization clock to Phy controller */
1838 for (i = 0; i < 35; i++)
1839 phy_write_1bit(ioaddr, PHY_DATA_1);
1840
1841 /* Send start command(01) to Phy */
1842 phy_write_1bit(ioaddr, PHY_DATA_0);
1843 phy_write_1bit(ioaddr, PHY_DATA_1);
1844
1845 /* Send read command(10) to Phy */
1846 phy_write_1bit(ioaddr, PHY_DATA_1);
1847 phy_write_1bit(ioaddr, PHY_DATA_0);
1848
1849 /* Send Phy address */
1850 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1851 phy_write_1bit(ioaddr,
1852 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1853
1854 /* Send register address */
1855 for (i = 0x10; i > 0; i = i >> 1)
f67ba792
ML		 1856 phy_write_1bit(ioaddr,
1857 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1da177e4
LT		 1858
1859 /* Skip transition state */
1860 phy_read_1bit(ioaddr);
1861
1862 /* read 16bit data */
1863 for (phy_data = 0, i = 0; i < 16; i++) {
1864 phy_data <<= 1;
1865 phy_data |= phy_read_1bit(ioaddr);
1866 }
1867 }
1868
1869 return phy_data;
1870}
1871
1872
1873/*
1874 * Write one bit data to Phy Controller
1875 */
1876
1877static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1878{
1879 outl(phy_data, ioaddr); /* MII Clock Low */
1880 udelay(1);
1881 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1882 udelay(1);
1883 outl(phy_data, ioaddr); /* MII Clock Low */
1884 udelay(1);
1885}
1886
1887
1888/*
1889 * Read one bit phy data from PHY controller
1890 */
1891
1892static u16 phy_read_1bit(unsigned long ioaddr)
1893{
1894 u16 phy_data;
1895
1896 outl(0x50000, ioaddr);
1897 udelay(1);
1898 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1899 outl(0x40000, ioaddr);
1900 udelay(1);
1901
1902 return phy_data;
1903}
1904
1905
1906/*
1907 * Parser SROM and media mode
1908 */
1909
1910static void dmfe_parse_srom(struct dmfe_board_info * db)
1911{
1912 char * srom = db->srom;
1913 int dmfe_mode, tmp_reg;
1914
1915 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1916
1917 /* Init CR15 */
1918 db->cr15_data = CR15_DEFAULT;
1919
1920 /* Check SROM Version */
1921 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1922 /* SROM V4.01 */
1923 /* Get NIC support media mode */
4c93566e 1924 db->NIC_capability = le16_to_cpup((__le16 *) (srom + 34));
1da177e4
LT		 1925 db->PHY_reg4 = 0;
1926 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1927 switch( db->NIC_capability & tmp_reg ) {
1928 case 0x1: db->PHY_reg4 |= 0x0020; break;
1929 case 0x2: db->PHY_reg4 |= 0x0040; break;
1930 case 0x4: db->PHY_reg4 |= 0x0080; break;
1931 case 0x8: db->PHY_reg4 |= 0x0100; break;
1932 }
1933 }
1934
1935 /* Media Mode Force or not check */
4c93566e
DM		 1936 dmfe_mode = (le32_to_cpup((__le32 *) (srom + 34)) &
1937 le32_to_cpup((__le32 *) (srom + 36)));
1da177e4
LT		 1938 switch(dmfe_mode) {
1939 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1940 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1941 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1942 case 0x100:
1943 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1944 }
1945
1946 /* Special Function setting */
1947 /* VLAN function */
1948 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1949 db->cr15_data |= 0x40;
1950
1951 /* Flow Control */
1952 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1953 db->cr15_data |= 0x400;
1954
1955 /* TX pause packet */
1956 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1957 db->cr15_data |= 0x9800;
1958 }
1959
1960 /* Parse HPNA parameter */
1961 db->HPNA_command = 1;
1962
1963 /* Accept remote command or not */
1964 if (HPNA_rx_cmd == 0)
1965 db->HPNA_command |= 0x8000;
1966
1967 /* Issue remote command & operation mode */
1968 if (HPNA_tx_cmd == 1)
1969 switch(HPNA_mode) { /* Issue Remote Command */
1970 case 0: db->HPNA_command |= 0x0904; break;
1971 case 1: db->HPNA_command |= 0x0a00; break;
1972 case 2: db->HPNA_command |= 0x0506; break;
1973 case 3: db->HPNA_command |= 0x0602; break;
1974 }
1975 else
1976 switch(HPNA_mode) { /* Don't Issue */
1977 case 0: db->HPNA_command |= 0x0004; break;
1978 case 1: db->HPNA_command |= 0x0000; break;
1979 case 2: db->HPNA_command |= 0x0006; break;
1980 case 3: db->HPNA_command |= 0x0002; break;
1981 }
1982
1983 /* Check DM9801 or DM9802 present or not */
1984 db->HPNA_present = 0;
1985 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1986 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1987 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1988 /* DM9801 or DM9802 present */
1989 db->HPNA_timer = 8;
1990 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1991 /* DM9801 HomeRun */
1992 db->HPNA_present = 1;
1993 dmfe_program_DM9801(db, tmp_reg);
1994 } else {
1995 /* DM9802 LongRun */
1996 db->HPNA_present = 2;
1997 dmfe_program_DM9802(db);
1998 }
1999 }
2000
2001}
2002
2003
2004/*
2005 * Init HomeRun DM9801
2006 */
2007
2008static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
2009{
2010 uint reg17, reg25;
2011
2012 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2013 switch(HPNA_rev) {
2014 case 0xb900: /* DM9801 E3 */
2015 db->HPNA_command |= 0x1000;
2016 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2017 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2018 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2019 break;
2020 case 0xb901: /* DM9801 E4 */
2021 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2022 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2023 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2024 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2025 break;
2026 case 0xb902: /* DM9801 E5 */
2027 case 0xb903: /* DM9801 E6 */
2028 default:
2029 db->HPNA_command |= 0x1000;
2030 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2031 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2032 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2033 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2034 break;
2035 }
2036 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2037 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2038 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2039}
2040
2041
2042/*
2043 * Init HomeRun DM9802
2044 */
2045
2046static void dmfe_program_DM9802(struct dmfe_board_info * db)
2047{
2048 uint phy_reg;
2049
2050 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2051 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2052 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2053 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2054 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2055}
2056
2057
2058/*
2059 * Check remote HPNA power and speed status. If not correct,
2060 * issue command again.
2061*/
2062
2063static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2064{
2065 uint phy_reg;
2066
2067 /* Got remote device status */
2068 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2069 switch(phy_reg) {
2070 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2071 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2072 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2073 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2074 }
2075
2076 /* Check remote device status match our setting ot not */
2077 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
f67ba792
ML		 2078 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2079 db->chip_id);
1da177e4
LT		 2080 db->HPNA_timer=8;
2081 } else
2082 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2083}
2084
2085
2086
a3aa1884 2087static DEFINE_PCI_DEVICE_TABLE(dmfe_pci_tbl) = {
1da177e4
LT		 2088 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2089 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2090 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2091 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2092 { 0, }
2093};
2094MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2095
2096
bc8a8387
ML		 2097#ifdef CONFIG_PM
2098static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2099{
2100 struct net_device *dev = pci_get_drvdata(pci_dev);
2101 struct dmfe_board_info *db = netdev_priv(dev);
f1069046 2102 u32 tmp;
bc8a8387
ML		 2103
2104 /* Disable upper layer interface */
2105 netif_device_detach(dev);
2106
2107 /* Disable Tx/Rx */
2108 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2109 update_cr6(db->cr6_data, dev->base_addr);
2110
2111 /* Disable Interrupt */
2112 outl(0, dev->base_addr + DCR7);
2113 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2114
2115 /* Fre RX buffers */
2116 dmfe_free_rxbuffer(db);
2117
f1069046
ML		 2118 /* Enable WOL */
2119 pci_read_config_dword(pci_dev, 0x40, &tmp);
2120 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2121
2122 if (db->wol_mode & WAKE_PHY)
2123 tmp |= DMFE_WOL_LINKCHANGE;
2124 if (db->wol_mode & WAKE_MAGIC)
2125 tmp |= DMFE_WOL_MAGICPACKET;
2126
2127 pci_write_config_dword(pci_dev, 0x40, tmp);
2128
2129 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2130 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2131
bc8a8387 2132 /* Power down device*/
bc8a8387 2133 pci_save_state(pci_dev);
a31e23e1 2134 pci_set_power_state(pci_dev, pci_choose_state (pci_dev, state));
bc8a8387
ML		 2135
2136 return 0;
2137}
2138
2139static int dmfe_resume(struct pci_dev *pci_dev)
2140{
2141 struct net_device *dev = pci_get_drvdata(pci_dev);
f1069046 2142 u32 tmp;
bc8a8387 2143
bc8a8387 2144 pci_set_power_state(pci_dev, PCI_D0);
65809b51 2145 pci_restore_state(pci_dev);
bc8a8387
ML		 2146
2147 /* Re-initilize DM910X board */
2148 dmfe_init_dm910x(dev);
2149
f1069046
ML		 2150 /* Disable WOL */
2151 pci_read_config_dword(pci_dev, 0x40, &tmp);
2152
2153 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2154 pci_write_config_dword(pci_dev, 0x40, tmp);
2155
2156 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2157 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2158
bc8a8387
ML		 2159 /* Restart upper layer interface */
2160 netif_device_attach(dev);
2161
2162 return 0;
2163}
2164#else
2165#define dmfe_suspend NULL
2166#define dmfe_resume NULL
2167#endif
2168
1da177e4
LT		 2169static struct pci_driver dmfe_driver = {
2170 .name = "dmfe",
2171 .id_table = dmfe_pci_tbl,
2172 .probe = dmfe_init_one,
2173 .remove = __devexit_p(dmfe_remove_one),
bc8a8387
ML		 2174 .suspend = dmfe_suspend,
2175 .resume = dmfe_resume
1da177e4
LT		 2176};
2177
2178MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2179MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2180MODULE_LICENSE("GPL");
2181MODULE_VERSION(DRV_VERSION);
2182
2183module_param(debug, int, 0);
2184module_param(mode, byte, 0);
2185module_param(cr6set, int, 0);
2186module_param(chkmode, byte, 0);
2187module_param(HPNA_mode, byte, 0);
2188module_param(HPNA_rx_cmd, byte, 0);
2189module_param(HPNA_tx_cmd, byte, 0);
2190module_param(HPNA_NoiseFloor, byte, 0);
2191module_param(SF_mode, byte, 0);
2192MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
f67ba792
ML		 2193MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2194 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2195
2196MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2197 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
1da177e4
LT		 2198
2199/* Description:
2200 * when user used insmod to add module, system invoked init_module()
2201 * to initilize and register.
2202 */
2203
2204static int __init dmfe_init_module(void)
2205{
2206 int rc;
2207
2208 printk(version);
2209 printed_version = 1;
2210
2211 DMFE_DBUG(0, "init_module() ", debug);
2212
2213 if (debug)
2214 dmfe_debug = debug; /* set debug flag */
2215 if (cr6set)
2216 dmfe_cr6_user_set = cr6set;
2217
2218 switch(mode) {
2219 case DMFE_10MHF:
2220 case DMFE_100MHF:
2221 case DMFE_10MFD:
2222 case DMFE_100MFD:
2223 case DMFE_1M_HPNA:
2224 dmfe_media_mode = mode;
2225 break;
2226 default:dmfe_media_mode = DMFE_AUTO;
2227 break;
2228 }
2229
2230 if (HPNA_mode > 4)
2231 HPNA_mode = 0; /* Default: LP/HS */
2232 if (HPNA_rx_cmd > 1)
2233 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2234 if (HPNA_tx_cmd > 1)
2235 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2236 if (HPNA_NoiseFloor > 15)
2237 HPNA_NoiseFloor = 0;
2238
29917620 2239 rc = pci_register_driver(&dmfe_driver);
1da177e4
LT		 2240 if (rc < 0)
2241 return rc;
2242
2243 return 0;
2244}
2245
2246
2247/*
2248 * Description:
2249 * when user used rmmod to delete module, system invoked clean_module()
2250 * to un-register all registered services.
2251 */
2252
2253static void __exit dmfe_cleanup_module(void)
2254{
2255 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2256 pci_unregister_driver(&dmfe_driver);
2257}
2258
2259module_init(dmfe_init_module);
2260module_exit(dmfe_cleanup_module);
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