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1da177e4 LT |
1 | /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500 |
2 | ethernet driver for Linux. | |
3 | ||
4 | Copyright 1994, 1995 Digital Equipment Corporation. | |
5 | ||
6 | Testing resources for this driver have been made available | |
7 | in part by NASA Ames Research Center (mjacob@nas.nasa.gov). | |
8 | ||
9 | The author may be reached at davies@maniac.ultranet.com. | |
10 | ||
11 | This program is free software; you can redistribute it and/or modify it | |
12 | under the terms of the GNU General Public License as published by the | |
13 | Free Software Foundation; either version 2 of the License, or (at your | |
14 | option) any later version. | |
15 | ||
16 | THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
17 | WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
18 | MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
19 | NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
20 | INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
21 | NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
22 | USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
23 | ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
25 | THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | ||
27 | You should have received a copy of the GNU General Public License along | |
28 | with this program; if not, write to the Free Software Foundation, Inc., | |
29 | 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | ||
31 | Originally, this driver was written for the Digital Equipment | |
32 | Corporation series of EtherWORKS ethernet cards: | |
33 | ||
34 | DE425 TP/COAX EISA | |
35 | DE434 TP PCI | |
36 | DE435 TP/COAX/AUI PCI | |
37 | DE450 TP/COAX/AUI PCI | |
38 | DE500 10/100 PCI Fasternet | |
39 | ||
40 | but it will now attempt to support all cards which conform to the | |
41 | Digital Semiconductor SROM Specification. The driver currently | |
42 | recognises the following chips: | |
43 | ||
f3b197ac JG |
44 | DC21040 (no SROM) |
45 | DC21041[A] | |
46 | DC21140[A] | |
47 | DC21142 | |
48 | DC21143 | |
1da177e4 LT |
49 | |
50 | So far the driver is known to work with the following cards: | |
51 | ||
52 | KINGSTON | |
53 | Linksys | |
54 | ZNYX342 | |
55 | SMC8432 | |
56 | SMC9332 (w/new SROM) | |
57 | ZNYX31[45] | |
f3b197ac | 58 | ZNYX346 10/100 4 port (can act as a 10/100 bridge!) |
1da177e4 LT |
59 | |
60 | The driver has been tested on a relatively busy network using the DE425, | |
61 | DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred | |
62 | 16M of data to a DECstation 5000/200 as follows: | |
63 | ||
64 | TCP UDP | |
65 | TX RX TX RX | |
66 | DE425 1030k 997k 1170k 1128k | |
67 | DE434 1063k 995k 1170k 1125k | |
68 | DE435 1063k 995k 1170k 1125k | |
69 | DE500 1063k 998k 1170k 1125k in 10Mb/s mode | |
70 | ||
71 | All values are typical (in kBytes/sec) from a sample of 4 for each | |
72 | measurement. Their error is +/-20k on a quiet (private) network and also | |
73 | depend on what load the CPU has. | |
74 | ||
75 | ========================================================================= | |
76 | This driver has been written substantially from scratch, although its | |
77 | inheritance of style and stack interface from 'ewrk3.c' and in turn from | |
78 | Donald Becker's 'lance.c' should be obvious. With the module autoload of | |
79 | every usable DECchip board, I pinched Donald's 'next_module' field to | |
80 | link my modules together. | |
81 | ||
82 | Upto 15 EISA cards can be supported under this driver, limited primarily | |
83 | by the available IRQ lines. I have checked different configurations of | |
84 | multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a | |
85 | problem yet (provided you have at least depca.c v0.38) ... | |
86 | ||
87 | PCI support has been added to allow the driver to work with the DE434, | |
88 | DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due | |
89 | to the differences in the EISA and PCI CSR address offsets from the base | |
90 | address. | |
91 | ||
92 | The ability to load this driver as a loadable module has been included | |
93 | and used extensively during the driver development (to save those long | |
94 | reboot sequences). Loadable module support under PCI and EISA has been | |
95 | achieved by letting the driver autoprobe as if it were compiled into the | |
96 | kernel. Do make sure you're not sharing interrupts with anything that | |
97 | cannot accommodate interrupt sharing! | |
98 | ||
99 | To utilise this ability, you have to do 8 things: | |
100 | ||
101 | 0) have a copy of the loadable modules code installed on your system. | |
102 | 1) copy de4x5.c from the /linux/drivers/net directory to your favourite | |
103 | temporary directory. | |
104 | 2) for fixed autoprobes (not recommended), edit the source code near | |
105 | line 5594 to reflect the I/O address you're using, or assign these when | |
106 | loading by: | |
107 | ||
108 | insmod de4x5 io=0xghh where g = bus number | |
f3b197ac | 109 | hh = device number |
1da177e4 LT |
110 | |
111 | NB: autoprobing for modules is now supported by default. You may just | |
112 | use: | |
113 | ||
114 | insmod de4x5 | |
115 | ||
116 | to load all available boards. For a specific board, still use | |
117 | the 'io=?' above. | |
118 | 3) compile de4x5.c, but include -DMODULE in the command line to ensure | |
119 | that the correct bits are compiled (see end of source code). | |
120 | 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a | |
121 | kernel with the de4x5 configuration turned off and reboot. | |
122 | 5) insmod de4x5 [io=0xghh] | |
f3b197ac JG |
123 | 6) run the net startup bits for your new eth?? interface(s) manually |
124 | (usually /etc/rc.inet[12] at boot time). | |
1da177e4 LT |
125 | 7) enjoy! |
126 | ||
f3b197ac | 127 | To unload a module, turn off the associated interface(s) |
1da177e4 LT |
128 | 'ifconfig eth?? down' then 'rmmod de4x5'. |
129 | ||
130 | Automedia detection is included so that in principal you can disconnect | |
131 | from, e.g. TP, reconnect to BNC and things will still work (after a | |
132 | pause whilst the driver figures out where its media went). My tests | |
133 | using ping showed that it appears to work.... | |
134 | ||
135 | By default, the driver will now autodetect any DECchip based card. | |
136 | Should you have a need to restrict the driver to DIGITAL only cards, you | |
137 | can compile with a DEC_ONLY define, or if loading as a module, use the | |
f3b197ac | 138 | 'dec_only=1' parameter. |
1da177e4 LT |
139 | |
140 | I've changed the timing routines to use the kernel timer and scheduling | |
141 | functions so that the hangs and other assorted problems that occurred | |
142 | while autosensing the media should be gone. A bonus for the DC21040 | |
143 | auto media sense algorithm is that it can now use one that is more in | |
144 | line with the rest (the DC21040 chip doesn't have a hardware timer). | |
145 | The downside is the 1 'jiffies' (10ms) resolution. | |
146 | ||
147 | IEEE 802.3u MII interface code has been added in anticipation that some | |
148 | products may use it in the future. | |
149 | ||
150 | The SMC9332 card has a non-compliant SROM which needs fixing - I have | |
151 | patched this driver to detect it because the SROM format used complies | |
152 | to a previous DEC-STD format. | |
153 | ||
154 | I have removed the buffer copies needed for receive on Intels. I cannot | |
155 | remove them for Alphas since the Tulip hardware only does longword | |
156 | aligned DMA transfers and the Alphas get alignment traps with non | |
157 | longword aligned data copies (which makes them really slow). No comment. | |
158 | ||
159 | I have added SROM decoding routines to make this driver work with any | |
160 | card that supports the Digital Semiconductor SROM spec. This will help | |
161 | all cards running the dc2114x series chips in particular. Cards using | |
162 | the dc2104x chips should run correctly with the basic driver. I'm in | |
163 | debt to <mjacob@feral.com> for the testing and feedback that helped get | |
164 | this feature working. So far we have tested KINGSTON, SMC8432, SMC9332 | |
165 | (with the latest SROM complying with the SROM spec V3: their first was | |
166 | broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315 | |
167 | (quad 21041 MAC) cards also appear to work despite their incorrectly | |
168 | wired IRQs. | |
169 | ||
170 | I have added a temporary fix for interrupt problems when some SCSI cards | |
171 | share the same interrupt as the DECchip based cards. The problem occurs | |
172 | because the SCSI card wants to grab the interrupt as a fast interrupt | |
173 | (runs the service routine with interrupts turned off) vs. this card | |
174 | which really needs to run the service routine with interrupts turned on. | |
175 | This driver will now add the interrupt service routine as a fast | |
176 | interrupt if it is bounced from the slow interrupt. THIS IS NOT A | |
177 | RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time | |
178 | until people sort out their compatibility issues and the kernel | |
179 | interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST | |
180 | INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not | |
181 | run on the same interrupt. PCMCIA/CardBus is another can of worms... | |
182 | ||
183 | Finally, I think I have really fixed the module loading problem with | |
184 | more than one DECchip based card. As a side effect, I don't mess with | |
185 | the device structure any more which means that if more than 1 card in | |
186 | 2.0.x is installed (4 in 2.1.x), the user will have to edit | |
187 | linux/drivers/net/Space.c to make room for them. Hence, module loading | |
188 | is the preferred way to use this driver, since it doesn't have this | |
189 | limitation. | |
190 | ||
191 | Where SROM media detection is used and full duplex is specified in the | |
192 | SROM, the feature is ignored unless lp->params.fdx is set at compile | |
193 | time OR during a module load (insmod de4x5 args='eth??:fdx' [see | |
194 | below]). This is because there is no way to automatically detect full | |
195 | duplex links except through autonegotiation. When I include the | |
196 | autonegotiation feature in the SROM autoconf code, this detection will | |
197 | occur automatically for that case. | |
198 | ||
199 | Command line arguments are now allowed, similar to passing arguments | |
200 | through LILO. This will allow a per adapter board set up of full duplex | |
201 | and media. The only lexical constraints are: the board name (dev->name) | |
202 | appears in the list before its parameters. The list of parameters ends | |
203 | either at the end of the parameter list or with another board name. The | |
204 | following parameters are allowed: | |
205 | ||
206 | fdx for full duplex | |
f3b197ac | 207 | autosense to set the media/speed; with the following |
1da177e4 LT |
208 | sub-parameters: |
209 | TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO | |
210 | ||
211 | Case sensitivity is important for the sub-parameters. They *must* be | |
212 | upper case. Examples: | |
213 | ||
214 | insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'. | |
215 | ||
216 | For a compiled in driver, at or above line 548, place e.g. | |
217 | #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP" | |
218 | ||
219 | Yes, I know full duplex isn't permissible on BNC or AUI; they're just | |
220 | examples. By default, full duplex is turned off and AUTO is the default | |
221 | autosense setting. In reality, I expect only the full duplex option to | |
222 | be used. Note the use of single quotes in the two examples above and the | |
223 | lack of commas to separate items. ALSO, you must get the requested media | |
224 | correct in relation to what the adapter SROM says it has. There's no way | |
225 | to determine this in advance other than by trial and error and common | |
226 | sense, e.g. call a BNC connectored port 'BNC', not '10Mb'. | |
227 | ||
228 | Changed the bus probing. EISA used to be done first, followed by PCI. | |
229 | Most people probably don't even know what a de425 is today and the EISA | |
230 | probe has messed up some SCSI cards in the past, so now PCI is always | |
231 | probed first followed by EISA if a) the architecture allows EISA and | |
232 | either b) there have been no PCI cards detected or c) an EISA probe is | |
233 | forced by the user. To force a probe include "force_eisa" in your | |
234 | insmod "args" line; for built-in kernels either change the driver to do | |
235 | this automatically or include #define DE4X5_FORCE_EISA on or before | |
236 | line 1040 in the driver. | |
237 | ||
f3b197ac | 238 | TO DO: |
1da177e4 LT |
239 | ------ |
240 | ||
241 | Revision History | |
242 | ---------------- | |
243 | ||
244 | Version Date Description | |
f3b197ac | 245 | |
1da177e4 LT |
246 | 0.1 17-Nov-94 Initial writing. ALPHA code release. |
247 | 0.2 13-Jan-95 Added PCI support for DE435's. | |
248 | 0.21 19-Jan-95 Added auto media detection. | |
249 | 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>. | |
250 | Fix recognition bug reported by <bkm@star.rl.ac.uk>. | |
251 | Add request/release_region code. | |
252 | Add loadable modules support for PCI. | |
253 | Clean up loadable modules support. | |
f3b197ac | 254 | 0.23 28-Feb-95 Added DC21041 and DC21140 support. |
1da177e4 LT |
255 | Fix missed frame counter value and initialisation. |
256 | Fixed EISA probe. | |
257 | 0.24 11-Apr-95 Change delay routine to use <linux/udelay>. | |
258 | Change TX_BUFFS_AVAIL macro. | |
259 | Change media autodetection to allow manual setting. | |
260 | Completed DE500 (DC21140) support. | |
261 | 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm. | |
262 | 0.242 10-May-95 Minor changes. | |
263 | 0.30 12-Jun-95 Timer fix for DC21140. | |
264 | Portability changes. | |
265 | Add ALPHA changes from <jestabro@ant.tay1.dec.com>. | |
266 | Add DE500 semi automatic autosense. | |
267 | Add Link Fail interrupt TP failure detection. | |
268 | Add timer based link change detection. | |
269 | Plugged a memory leak in de4x5_queue_pkt(). | |
270 | 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1. | |
271 | 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a | |
272 | suggestion by <heiko@colossus.escape.de>. | |
273 | 0.33 8-Aug-95 Add shared interrupt support (not released yet). | |
274 | 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs. | |
275 | Fix de4x5_interrupt(). | |
276 | Fix dc21140_autoconf() mess. | |
277 | No shared interrupt support. | |
278 | 0.332 11-Sep-95 Added MII management interface routines. | |
279 | 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>. | |
280 | Add kernel timer code (h/w is too flaky). | |
281 | Add MII based PHY autosense. | |
282 | Add new multicasting code. | |
f3b197ac | 283 | Add new autosense algorithms for media/mode |
1da177e4 LT |
284 | selection using kernel scheduling/timing. |
285 | Re-formatted. | |
286 | Made changes suggested by <jeff@router.patch.net>: | |
287 | Change driver to detect all DECchip based cards | |
288 | with DEC_ONLY restriction a special case. | |
289 | Changed driver to autoprobe as a module. No irq | |
290 | checking is done now - assume BIOS is good! | |
291 | Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp> | |
292 | 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card | |
293 | only <niles@axp745gsfc.nasa.gov> | |
294 | Fix for multiple PCI cards reported by <jos@xos.nl> | |
1fb9df5d | 295 | Duh, put the IRQF_SHARED flag into request_interrupt(). |
1da177e4 LT |
296 | Fix SMC ethernet address in enet_det[]. |
297 | Print chip name instead of "UNKNOWN" during boot. | |
298 | 0.42 26-Apr-96 Fix MII write TA bit error. | |
299 | Fix bug in dc21040 and dc21041 autosense code. | |
300 | Remove buffer copies on receive for Intels. | |
301 | Change sk_buff handling during media disconnects to | |
302 | eliminate DUP packets. | |
303 | Add dynamic TX thresholding. | |
304 | Change all chips to use perfect multicast filtering. | |
305 | Fix alloc_device() bug <jari@markkus2.fimr.fi> | |
306 | 0.43 21-Jun-96 Fix unconnected media TX retry bug. | |
307 | Add Accton to the list of broken cards. | |
308 | Fix TX under-run bug for non DC21140 chips. | |
309 | Fix boot command probe bug in alloc_device() as | |
f3b197ac | 310 | reported by <koen.gadeyne@barco.com> and |
1da177e4 LT |
311 | <orava@nether.tky.hut.fi>. |
312 | Add cache locks to prevent a race condition as | |
f3b197ac | 313 | reported by <csd@microplex.com> and |
1da177e4 LT |
314 | <baba@beckman.uiuc.edu>. |
315 | Upgraded alloc_device() code. | |
316 | 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion | |
317 | with <csd@microplex.com> | |
318 | 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips. | |
319 | Fix EISA probe bugs reported by <os2@kpi.kharkov.ua> | |
320 | and <michael@compurex.com>. | |
321 | 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media | |
322 | with a loopback packet. | |
323 | 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported | |
324 | by <bhat@mundook.cs.mu.OZ.AU> | |
f3b197ac | 325 | 0.45 8-Dec-96 Include endian functions for PPC use, from work |
1da177e4 LT |
326 | by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>. |
327 | 0.451 28-Dec-96 Added fix to allow autoprobe for modules after | |
328 | suggestion from <mjacob@feral.com>. | |
329 | 0.5 30-Jan-97 Added SROM decoding functions. | |
330 | Updated debug flags. | |
331 | Fix sleep/wakeup calls for PCI cards, bug reported | |
332 | by <cross@gweep.lkg.dec.com>. | |
333 | Added multi-MAC, one SROM feature from discussion | |
334 | with <mjacob@feral.com>. | |
335 | Added full module autoprobe capability. | |
336 | Added attempt to use an SMC9332 with broken SROM. | |
337 | Added fix for ZYNX multi-mac cards that didn't | |
338 | get their IRQs wired correctly. | |
339 | 0.51 13-Feb-97 Added endian fixes for the SROM accesses from | |
340 | <paubert@iram.es> | |
341 | Fix init_connection() to remove extra device reset. | |
342 | Fix MAC/PHY reset ordering in dc21140m_autoconf(). | |
343 | Fix initialisation problem with lp->timeout in | |
344 | typeX_infoblock() from <paubert@iram.es>. | |
345 | Fix MII PHY reset problem from work done by | |
346 | <paubert@iram.es>. | |
347 | 0.52 26-Apr-97 Some changes may not credit the right people - | |
348 | a disk crash meant I lost some mail. | |
f3b197ac JG |
349 | Change RX interrupt routine to drop rather than |
350 | defer packets to avoid hang reported by | |
1da177e4 LT |
351 | <g.thomas@opengroup.org>. |
352 | Fix srom_exec() to return for COMPACT and type 1 | |
353 | infoblocks. | |
354 | Added DC21142 and DC21143 functions. | |
355 | Added byte counters from <phil@tazenda.demon.co.uk> | |
1fb9df5d | 356 | Added IRQF_DISABLED temporary fix from |
1da177e4 LT |
357 | <mjacob@feral.com>. |
358 | 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during | |
359 | module load: bug reported by | |
360 | <Piete.Brooks@cl.cam.ac.uk> | |
361 | Fix multi-MAC, one SROM, to work with 2114x chips: | |
362 | bug reported by <cmetz@inner.net>. | |
363 | Make above search independent of BIOS device scan | |
364 | direction. | |
365 | Completed DC2114[23] autosense functions. | |
f3b197ac | 366 | 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by |
1da177e4 LT |
367 | <robin@intercore.com |
368 | Fix type1_infoblock() bug introduced in 0.53, from | |
f3b197ac | 369 | problem reports by |
1da177e4 LT |
370 | <parmee@postecss.ncrfran.france.ncr.com> and |
371 | <jo@ice.dillingen.baynet.de>. | |
372 | Added argument list to set up each board from either | |
373 | a module's command line or a compiled in #define. | |
374 | Added generic MII PHY functionality to deal with | |
375 | newer PHY chips. | |
376 | Fix the mess in 2.1.67. | |
f3b197ac | 377 | 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by |
1da177e4 LT |
378 | <redhat@cococo.net>. |
379 | Fix bug in pci_probe() for 64 bit systems reported | |
380 | by <belliott@accessone.com>. | |
381 | 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>. | |
382 | 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org> | |
383 | 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040. | |
384 | 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure. | |
385 | **Incompatible with 2.0.x from here.** | |
386 | 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP | |
387 | from <lma@varesearch.com> | |
388 | Add TP, AUI and BNC cases to 21140m_autoconf() for | |
389 | case where a 21140 under SROM control uses, e.g. AUI | |
390 | from problem report by <delchini@lpnp09.in2p3.fr> | |
391 | Add MII parallel detection to 2114x_autoconf() for | |
392 | case where no autonegotiation partner exists from | |
393 | problem report by <mlapsley@ndirect.co.uk>. | |
394 | Add ability to force connection type directly even | |
395 | when using SROM control from problem report by | |
396 | <earl@exis.net>. | |
397 | Updated the PCI interface to conform with the latest | |
398 | version. I hope nothing is broken... | |
399 | Add TX done interrupt modification from suggestion | |
400 | by <Austin.Donnelly@cl.cam.ac.uk>. | |
f3b197ac | 401 | Fix is_anc_capable() bug reported by |
1da177e4 LT |
402 | <Austin.Donnelly@cl.cam.ac.uk>. |
403 | Fix type[13]_infoblock() bug: during MII search, PHY | |
404 | lp->rst not run because lp->ibn not initialised - | |
405 | from report & fix by <paubert@iram.es>. | |
406 | Fix probe bug with EISA & PCI cards present from | |
407 | report by <eirik@netcom.com>. | |
408 | 0.541 24-Aug-98 Fix compiler problems associated with i386-string | |
409 | ops from multiple bug reports and temporary fix | |
410 | from <paubert@iram.es>. | |
411 | Fix pci_probe() to correctly emulate the old | |
412 | pcibios_find_class() function. | |
413 | Add an_exception() for old ZYNX346 and fix compile | |
414 | warning on PPC & SPARC, from <ecd@skynet.be>. | |
415 | Fix lastPCI to correctly work with compiled in | |
f3b197ac | 416 | kernels and modules from bug report by |
1da177e4 LT |
417 | <Zlatko.Calusic@CARNet.hr> et al. |
418 | 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages | |
419 | when media is unconnected. | |
420 | Change dev->interrupt to lp->interrupt to ensure | |
421 | alignment for Alpha's and avoid their unaligned | |
422 | access traps. This flag is merely for log messages: | |
423 | should do something more definitive though... | |
424 | 0.543 30-Dec-98 Add SMP spin locking. | |
425 | 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using | |
426 | a 21143 by <mmporter@home.com>. | |
427 | Change PCI/EISA bus probing order. | |
f3b197ac | 428 | 0.545 28-Nov-99 Further Moto SROM bug fix from |
1da177e4 LT |
429 | <mporter@eng.mcd.mot.com> |
430 | Remove double checking for DEBUG_RX in de4x5_dbg_rx() | |
431 | from report by <geert@linux-m68k.org> | |
432 | 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function | |
433 | was causing a page fault when initializing the | |
434 | variable 'pb', on a non de4x5 PCI device, in this | |
435 | case a PCI bridge (DEC chip 21152). The value of | |
436 | 'pb' is now only initialized if a de4x5 chip is | |
f3b197ac JG |
437 | present. |
438 | <france@handhelds.org> | |
1da177e4 LT |
439 | 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com> |
440 | 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and | |
441 | generic DMA APIs. Fixed DE425 support on Alpha. | |
442 | <maz@wild-wind.fr.eu.org> | |
443 | ========================================================================= | |
444 | */ | |
445 | ||
1da177e4 LT |
446 | #include <linux/module.h> |
447 | #include <linux/kernel.h> | |
448 | #include <linux/string.h> | |
449 | #include <linux/interrupt.h> | |
450 | #include <linux/ptrace.h> | |
451 | #include <linux/errno.h> | |
452 | #include <linux/ioport.h> | |
453 | #include <linux/slab.h> | |
454 | #include <linux/pci.h> | |
455 | #include <linux/eisa.h> | |
456 | #include <linux/delay.h> | |
457 | #include <linux/init.h> | |
458 | #include <linux/spinlock.h> | |
459 | #include <linux/crc32.h> | |
460 | #include <linux/netdevice.h> | |
461 | #include <linux/etherdevice.h> | |
462 | #include <linux/skbuff.h> | |
463 | #include <linux/time.h> | |
464 | #include <linux/types.h> | |
465 | #include <linux/unistd.h> | |
466 | #include <linux/ctype.h> | |
467 | #include <linux/dma-mapping.h> | |
468 | #include <linux/moduleparam.h> | |
469 | #include <linux/bitops.h> | |
470 | ||
471 | #include <asm/io.h> | |
472 | #include <asm/dma.h> | |
473 | #include <asm/byteorder.h> | |
474 | #include <asm/unaligned.h> | |
475 | #include <asm/uaccess.h> | |
bfaadcad | 476 | #ifdef CONFIG_PPC_PMAC |
1da177e4 | 477 | #include <asm/machdep.h> |
bfaadcad | 478 | #endif /* CONFIG_PPC_PMAC */ |
1da177e4 LT |
479 | |
480 | #include "de4x5.h" | |
481 | ||
482 | static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n"; | |
483 | ||
484 | #define c_char const char | |
c559a5bc | 485 | #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((__le16 *)(a))) |
1da177e4 LT |
486 | |
487 | /* | |
488 | ** MII Information | |
489 | */ | |
490 | struct phy_table { | |
491 | int reset; /* Hard reset required? */ | |
492 | int id; /* IEEE OUI */ | |
493 | int ta; /* One cycle TA time - 802.3u is confusing here */ | |
494 | struct { /* Non autonegotiation (parallel) speed det. */ | |
495 | int reg; | |
496 | int mask; | |
497 | int value; | |
498 | } spd; | |
499 | }; | |
500 | ||
501 | struct mii_phy { | |
502 | int reset; /* Hard reset required? */ | |
503 | int id; /* IEEE OUI */ | |
504 | int ta; /* One cycle TA time */ | |
505 | struct { /* Non autonegotiation (parallel) speed det. */ | |
506 | int reg; | |
507 | int mask; | |
508 | int value; | |
509 | } spd; | |
510 | int addr; /* MII address for the PHY */ | |
511 | u_char *gep; /* Start of GEP sequence block in SROM */ | |
512 | u_char *rst; /* Start of reset sequence in SROM */ | |
513 | u_int mc; /* Media Capabilities */ | |
514 | u_int ana; /* NWay Advertisement */ | |
7f927fcc | 515 | u_int fdx; /* Full DupleX capabilities for each media */ |
1da177e4 LT |
516 | u_int ttm; /* Transmit Threshold Mode for each media */ |
517 | u_int mci; /* 21142 MII Connector Interrupt info */ | |
518 | }; | |
519 | ||
520 | #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */ | |
521 | ||
522 | struct sia_phy { | |
523 | u_char mc; /* Media Code */ | |
524 | u_char ext; /* csr13-15 valid when set */ | |
525 | int csr13; /* SIA Connectivity Register */ | |
526 | int csr14; /* SIA TX/RX Register */ | |
527 | int csr15; /* SIA General Register */ | |
528 | int gepc; /* SIA GEP Control Information */ | |
529 | int gep; /* SIA GEP Data */ | |
530 | }; | |
531 | ||
532 | /* | |
533 | ** Define the know universe of PHY devices that can be | |
534 | ** recognised by this driver. | |
535 | */ | |
536 | static struct phy_table phy_info[] = { | |
537 | {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */ | |
538 | {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */ | |
539 | {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */ | |
540 | {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */ | |
541 | {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */ | |
542 | }; | |
543 | ||
544 | /* | |
545 | ** These GENERIC values assumes that the PHY devices follow 802.3u and | |
546 | ** allow parallel detection to set the link partner ability register. | |
547 | ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported. | |
548 | */ | |
549 | #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */ | |
550 | #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */ | |
551 | #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */ | |
552 | ||
553 | /* | |
554 | ** Define special SROM detection cases | |
555 | */ | |
556 | static c_char enet_det[][ETH_ALEN] = { | |
557 | {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00}, | |
558 | {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00} | |
559 | }; | |
560 | ||
561 | #define SMC 1 | |
562 | #define ACCTON 2 | |
563 | ||
564 | /* | |
565 | ** SROM Repair definitions. If a broken SROM is detected a card may | |
566 | ** use this information to help figure out what to do. This is a | |
567 | ** "stab in the dark" and so far for SMC9332's only. | |
568 | */ | |
569 | static c_char srom_repair_info[][100] = { | |
570 | {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */ | |
571 | 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02, | |
572 | 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50, | |
573 | 0x00,0x18,} | |
574 | }; | |
575 | ||
576 | ||
577 | #ifdef DE4X5_DEBUG | |
578 | static int de4x5_debug = DE4X5_DEBUG; | |
579 | #else | |
580 | /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/ | |
581 | static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION); | |
582 | #endif | |
583 | ||
584 | /* | |
585 | ** Allow per adapter set up. For modules this is simply a command line | |
f3b197ac | 586 | ** parameter, e.g.: |
1da177e4 LT |
587 | ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'. |
588 | ** | |
589 | ** For a compiled in driver, place e.g. | |
590 | ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP" | |
591 | ** here | |
592 | */ | |
593 | #ifdef DE4X5_PARM | |
594 | static char *args = DE4X5_PARM; | |
595 | #else | |
596 | static char *args; | |
597 | #endif | |
598 | ||
599 | struct parameters { | |
eb034a79 | 600 | bool fdx; |
1da177e4 LT |
601 | int autosense; |
602 | }; | |
603 | ||
604 | #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */ | |
605 | ||
606 | #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */ | |
607 | ||
608 | /* | |
609 | ** Ethernet PROM defines | |
610 | */ | |
611 | #define PROBE_LENGTH 32 | |
612 | #define ETH_PROM_SIG 0xAA5500FFUL | |
613 | ||
614 | /* | |
615 | ** Ethernet Info | |
616 | */ | |
617 | #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */ | |
618 | #define IEEE802_3_SZ 1518 /* Packet + CRC */ | |
619 | #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */ | |
620 | #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */ | |
621 | #define MIN_DAT_SZ 1 /* Minimum ethernet data length */ | |
622 | #define PKT_HDR_LEN 14 /* Addresses and data length info */ | |
623 | #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1) | |
624 | #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */ | |
625 | ||
626 | ||
627 | /* | |
628 | ** EISA bus defines | |
629 | */ | |
630 | #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */ | |
631 | #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */ | |
632 | ||
633 | #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11} | |
634 | ||
635 | #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"} | |
636 | #define DE4X5_NAME_LENGTH 8 | |
637 | ||
638 | static c_char *de4x5_signatures[] = DE4X5_SIGNATURE; | |
639 | ||
640 | /* | |
641 | ** Ethernet PROM defines for DC21040 | |
642 | */ | |
643 | #define PROBE_LENGTH 32 | |
644 | #define ETH_PROM_SIG 0xAA5500FFUL | |
645 | ||
646 | /* | |
647 | ** PCI Bus defines | |
648 | */ | |
649 | #define PCI_MAX_BUS_NUM 8 | |
650 | #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */ | |
651 | #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */ | |
652 | ||
653 | /* | |
654 | ** Memory Alignment. Each descriptor is 4 longwords long. To force a | |
655 | ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and | |
656 | ** DESC_ALIGN. ALIGN aligns the start address of the private memory area | |
f3b197ac | 657 | ** and hence the RX descriptor ring's first entry. |
1da177e4 LT |
658 | */ |
659 | #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */ | |
660 | #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */ | |
661 | #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */ | |
662 | #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */ | |
663 | #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */ | |
664 | #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */ | |
665 | ||
666 | #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */ | |
667 | #define DE4X5_CACHE_ALIGN CAL_16LONG | |
668 | #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */ | |
669 | /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */ | |
670 | #define DESC_ALIGN | |
671 | ||
672 | #ifndef DEC_ONLY /* See README.de4x5 for using this */ | |
673 | static int dec_only; | |
674 | #else | |
675 | static int dec_only = 1; | |
676 | #endif | |
677 | ||
678 | /* | |
679 | ** DE4X5 IRQ ENABLE/DISABLE | |
680 | */ | |
681 | #define ENABLE_IRQs { \ | |
682 | imr |= lp->irq_en;\ | |
683 | outl(imr, DE4X5_IMR); /* Enable the IRQs */\ | |
684 | } | |
685 | ||
686 | #define DISABLE_IRQs {\ | |
687 | imr = inl(DE4X5_IMR);\ | |
688 | imr &= ~lp->irq_en;\ | |
689 | outl(imr, DE4X5_IMR); /* Disable the IRQs */\ | |
690 | } | |
691 | ||
692 | #define UNMASK_IRQs {\ | |
693 | imr |= lp->irq_mask;\ | |
694 | outl(imr, DE4X5_IMR); /* Unmask the IRQs */\ | |
695 | } | |
696 | ||
697 | #define MASK_IRQs {\ | |
698 | imr = inl(DE4X5_IMR);\ | |
699 | imr &= ~lp->irq_mask;\ | |
700 | outl(imr, DE4X5_IMR); /* Mask the IRQs */\ | |
701 | } | |
702 | ||
703 | /* | |
704 | ** DE4X5 START/STOP | |
705 | */ | |
706 | #define START_DE4X5 {\ | |
707 | omr = inl(DE4X5_OMR);\ | |
708 | omr |= OMR_ST | OMR_SR;\ | |
709 | outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\ | |
710 | } | |
711 | ||
712 | #define STOP_DE4X5 {\ | |
713 | omr = inl(DE4X5_OMR);\ | |
714 | omr &= ~(OMR_ST|OMR_SR);\ | |
715 | outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \ | |
716 | } | |
717 | ||
718 | /* | |
719 | ** DE4X5 SIA RESET | |
720 | */ | |
721 | #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */ | |
722 | ||
723 | /* | |
724 | ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS) | |
725 | */ | |
726 | #define DE4X5_AUTOSENSE_MS 250 | |
727 | ||
728 | /* | |
729 | ** SROM Structure | |
730 | */ | |
731 | struct de4x5_srom { | |
732 | char sub_vendor_id[2]; | |
733 | char sub_system_id[2]; | |
734 | char reserved[12]; | |
735 | char id_block_crc; | |
736 | char reserved2; | |
737 | char version; | |
738 | char num_controllers; | |
739 | char ieee_addr[6]; | |
740 | char info[100]; | |
741 | short chksum; | |
742 | }; | |
743 | #define SUB_VENDOR_ID 0x500a | |
744 | ||
745 | /* | |
746 | ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous | |
747 | ** and have sizes of both a power of 2 and a multiple of 4. | |
748 | ** A size of 256 bytes for each buffer could be chosen because over 90% of | |
749 | ** all packets in our network are <256 bytes long and 64 longword alignment | |
750 | ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX | |
751 | ** descriptors are needed for machines with an ALPHA CPU. | |
752 | */ | |
753 | #define NUM_RX_DESC 8 /* Number of RX descriptors */ | |
754 | #define NUM_TX_DESC 32 /* Number of TX descriptors */ | |
755 | #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */ | |
756 | /* Multiple of 4 for DC21040 */ | |
757 | /* Allows 512 byte alignment */ | |
758 | struct de4x5_desc { | |
c559a5bc AV |
759 | volatile __le32 status; |
760 | __le32 des1; | |
761 | __le32 buf; | |
762 | __le32 next; | |
1da177e4 LT |
763 | DESC_ALIGN |
764 | }; | |
765 | ||
766 | /* | |
767 | ** The DE4X5 private structure | |
768 | */ | |
769 | #define DE4X5_PKT_STAT_SZ 16 | |
770 | #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you | |
771 | increase DE4X5_PKT_STAT_SZ */ | |
772 | ||
773 | struct pkt_stats { | |
774 | u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */ | |
775 | u_int unicast; | |
776 | u_int multicast; | |
777 | u_int broadcast; | |
778 | u_int excessive_collisions; | |
779 | u_int tx_underruns; | |
780 | u_int excessive_underruns; | |
781 | u_int rx_runt_frames; | |
782 | u_int rx_collision; | |
783 | u_int rx_dribble; | |
784 | u_int rx_overflow; | |
785 | }; | |
786 | ||
787 | struct de4x5_private { | |
788 | char adapter_name[80]; /* Adapter name */ | |
789 | u_long interrupt; /* Aligned ISR flag */ | |
790 | struct de4x5_desc *rx_ring; /* RX descriptor ring */ | |
791 | struct de4x5_desc *tx_ring; /* TX descriptor ring */ | |
792 | struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */ | |
793 | struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */ | |
794 | int rx_new, rx_old; /* RX descriptor ring pointers */ | |
795 | int tx_new, tx_old; /* TX descriptor ring pointers */ | |
796 | char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */ | |
797 | char frame[64]; /* Min sized packet for loopback*/ | |
798 | spinlock_t lock; /* Adapter specific spinlock */ | |
799 | struct net_device_stats stats; /* Public stats */ | |
800 | struct pkt_stats pktStats; /* Private stats counters */ | |
801 | char rxRingSize; | |
802 | char txRingSize; | |
803 | int bus; /* EISA or PCI */ | |
804 | int bus_num; /* PCI Bus number */ | |
805 | int device; /* Device number on PCI bus */ | |
806 | int state; /* Adapter OPENED or CLOSED */ | |
807 | int chipset; /* DC21040, DC21041 or DC21140 */ | |
808 | s32 irq_mask; /* Interrupt Mask (Enable) bits */ | |
809 | s32 irq_en; /* Summary interrupt bits */ | |
810 | int media; /* Media (eg TP), mode (eg 100B)*/ | |
811 | int c_media; /* Remember the last media conn */ | |
eb034a79 | 812 | bool fdx; /* media full duplex flag */ |
1da177e4 LT |
813 | int linkOK; /* Link is OK */ |
814 | int autosense; /* Allow/disallow autosensing */ | |
eb034a79 | 815 | bool tx_enable; /* Enable descriptor polling */ |
1da177e4 LT |
816 | int setup_f; /* Setup frame filtering type */ |
817 | int local_state; /* State within a 'media' state */ | |
818 | struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */ | |
819 | struct sia_phy sia; /* SIA PHY Information */ | |
820 | int active; /* Index to active PHY device */ | |
821 | int mii_cnt; /* Number of attached PHY's */ | |
822 | int timeout; /* Scheduling counter */ | |
823 | struct timer_list timer; /* Timer info for kernel */ | |
824 | int tmp; /* Temporary global per card */ | |
825 | struct { | |
826 | u_long lock; /* Lock the cache accesses */ | |
827 | s32 csr0; /* Saved Bus Mode Register */ | |
828 | s32 csr6; /* Saved Operating Mode Reg. */ | |
829 | s32 csr7; /* Saved IRQ Mask Register */ | |
830 | s32 gep; /* Saved General Purpose Reg. */ | |
831 | s32 gepc; /* Control info for GEP */ | |
832 | s32 csr13; /* Saved SIA Connectivity Reg. */ | |
833 | s32 csr14; /* Saved SIA TX/RX Register */ | |
834 | s32 csr15; /* Saved SIA General Register */ | |
835 | int save_cnt; /* Flag if state already saved */ | |
836 | struct sk_buff *skb; /* Save the (re-ordered) skb's */ | |
837 | } cache; | |
838 | struct de4x5_srom srom; /* A copy of the SROM */ | |
839 | int cfrv; /* Card CFRV copy */ | |
840 | int rx_ovf; /* Check for 'RX overflow' tag */ | |
eb034a79 RK |
841 | bool useSROM; /* For non-DEC card use SROM */ |
842 | bool useMII; /* Infoblock using the MII */ | |
1da177e4 LT |
843 | int asBitValid; /* Autosense bits in GEP? */ |
844 | int asPolarity; /* 0 => asserted high */ | |
845 | int asBit; /* Autosense bit number in GEP */ | |
846 | int defMedium; /* SROM default medium */ | |
847 | int tcount; /* Last infoblock number */ | |
848 | int infoblock_init; /* Initialised this infoblock? */ | |
849 | int infoleaf_offset; /* SROM infoleaf for controller */ | |
850 | s32 infoblock_csr6; /* csr6 value in SROM infoblock */ | |
851 | int infoblock_media; /* infoblock media */ | |
852 | int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */ | |
853 | u_char *rst; /* Pointer to Type 5 reset info */ | |
854 | u_char ibn; /* Infoblock number */ | |
855 | struct parameters params; /* Command line/ #defined params */ | |
856 | struct device *gendev; /* Generic device */ | |
857 | dma_addr_t dma_rings; /* DMA handle for rings */ | |
858 | int dma_size; /* Size of the DMA area */ | |
859 | char *rx_bufs; /* rx bufs on alpha, sparc, ... */ | |
860 | }; | |
861 | ||
862 | /* | |
863 | ** To get around certain poxy cards that don't provide an SROM | |
864 | ** for the second and more DECchip, I have to key off the first | |
865 | ** chip's address. I'll assume there's not a bad SROM iff: | |
866 | ** | |
867 | ** o the chipset is the same | |
868 | ** o the bus number is the same and > 0 | |
869 | ** o the sum of all the returned hw address bytes is 0 or 0x5fa | |
870 | ** | |
871 | ** Also have to save the irq for those cards whose hardware designers | |
872 | ** can't follow the PCI to PCI Bridge Architecture spec. | |
873 | */ | |
874 | static struct { | |
875 | int chipset; | |
876 | int bus; | |
877 | int irq; | |
878 | u_char addr[ETH_ALEN]; | |
879 | } last = {0,}; | |
880 | ||
881 | /* | |
882 | ** The transmit ring full condition is described by the tx_old and tx_new | |
883 | ** pointers by: | |
884 | ** tx_old = tx_new Empty ring | |
885 | ** tx_old = tx_new+1 Full ring | |
886 | ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition) | |
887 | */ | |
888 | #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\ | |
889 | lp->tx_old+lp->txRingSize-lp->tx_new-1:\ | |
890 | lp->tx_old -lp->tx_new-1) | |
891 | ||
892 | #define TX_PKT_PENDING (lp->tx_old != lp->tx_new) | |
893 | ||
894 | /* | |
895 | ** Public Functions | |
896 | */ | |
897 | static int de4x5_open(struct net_device *dev); | |
898 | static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 899 | static irqreturn_t de4x5_interrupt(int irq, void *dev_id); |
1da177e4 LT |
900 | static int de4x5_close(struct net_device *dev); |
901 | static struct net_device_stats *de4x5_get_stats(struct net_device *dev); | |
902 | static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len); | |
903 | static void set_multicast_list(struct net_device *dev); | |
904 | static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
905 | ||
906 | /* | |
907 | ** Private functions | |
908 | */ | |
909 | static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev); | |
910 | static int de4x5_init(struct net_device *dev); | |
911 | static int de4x5_sw_reset(struct net_device *dev); | |
912 | static int de4x5_rx(struct net_device *dev); | |
913 | static int de4x5_tx(struct net_device *dev); | |
914 | static int de4x5_ast(struct net_device *dev); | |
915 | static int de4x5_txur(struct net_device *dev); | |
916 | static int de4x5_rx_ovfc(struct net_device *dev); | |
917 | ||
918 | static int autoconf_media(struct net_device *dev); | |
919 | static void create_packet(struct net_device *dev, char *frame, int len); | |
920 | static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb); | |
921 | static int dc21040_autoconf(struct net_device *dev); | |
922 | static int dc21041_autoconf(struct net_device *dev); | |
923 | static int dc21140m_autoconf(struct net_device *dev); | |
924 | static int dc2114x_autoconf(struct net_device *dev); | |
925 | static int srom_autoconf(struct net_device *dev); | |
926 | static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *)); | |
927 | static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int)); | |
928 | static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec); | |
929 | static int test_for_100Mb(struct net_device *dev, int msec); | |
930 | static int wait_for_link(struct net_device *dev); | |
eb034a79 | 931 | static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec); |
1da177e4 LT |
932 | static int is_spd_100(struct net_device *dev); |
933 | static int is_100_up(struct net_device *dev); | |
934 | static int is_10_up(struct net_device *dev); | |
935 | static int is_anc_capable(struct net_device *dev); | |
936 | static int ping_media(struct net_device *dev, int msec); | |
937 | static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len); | |
938 | static void de4x5_free_rx_buffs(struct net_device *dev); | |
939 | static void de4x5_free_tx_buffs(struct net_device *dev); | |
940 | static void de4x5_save_skbs(struct net_device *dev); | |
941 | static void de4x5_rst_desc_ring(struct net_device *dev); | |
942 | static void de4x5_cache_state(struct net_device *dev, int flag); | |
943 | static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb); | |
944 | static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb); | |
945 | static struct sk_buff *de4x5_get_cache(struct net_device *dev); | |
946 | static void de4x5_setup_intr(struct net_device *dev); | |
947 | static void de4x5_init_connection(struct net_device *dev); | |
948 | static int de4x5_reset_phy(struct net_device *dev); | |
949 | static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr); | |
950 | static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec); | |
951 | static int test_tp(struct net_device *dev, s32 msec); | |
952 | static int EISA_signature(char *name, struct device *device); | |
953 | static int PCI_signature(char *name, struct de4x5_private *lp); | |
954 | static void DevicePresent(struct net_device *dev, u_long iobase); | |
955 | static void enet_addr_rst(u_long aprom_addr); | |
956 | static int de4x5_bad_srom(struct de4x5_private *lp); | |
957 | static short srom_rd(u_long address, u_char offset); | |
958 | static void srom_latch(u_int command, u_long address); | |
959 | static void srom_command(u_int command, u_long address); | |
960 | static void srom_address(u_int command, u_long address, u_char offset); | |
961 | static short srom_data(u_int command, u_long address); | |
962 | /*static void srom_busy(u_int command, u_long address);*/ | |
963 | static void sendto_srom(u_int command, u_long addr); | |
964 | static int getfrom_srom(u_long addr); | |
965 | static int srom_map_media(struct net_device *dev); | |
966 | static int srom_infoleaf_info(struct net_device *dev); | |
967 | static void srom_init(struct net_device *dev); | |
968 | static void srom_exec(struct net_device *dev, u_char *p); | |
969 | static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr); | |
970 | static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr); | |
971 | static int mii_rdata(u_long ioaddr); | |
972 | static void mii_wdata(int data, int len, u_long ioaddr); | |
973 | static void mii_ta(u_long rw, u_long ioaddr); | |
974 | static int mii_swap(int data, int len); | |
975 | static void mii_address(u_char addr, u_long ioaddr); | |
976 | static void sendto_mii(u32 command, int data, u_long ioaddr); | |
977 | static int getfrom_mii(u32 command, u_long ioaddr); | |
978 | static int mii_get_oui(u_char phyaddr, u_long ioaddr); | |
979 | static int mii_get_phy(struct net_device *dev); | |
980 | static void SetMulticastFilter(struct net_device *dev); | |
981 | static int get_hw_addr(struct net_device *dev); | |
982 | static void srom_repair(struct net_device *dev, int card); | |
983 | static int test_bad_enet(struct net_device *dev, int status); | |
984 | static int an_exception(struct de4x5_private *lp); | |
985 | static char *build_setup_frame(struct net_device *dev, int mode); | |
986 | static void disable_ast(struct net_device *dev); | |
987 | static void enable_ast(struct net_device *dev, u32 time_out); | |
988 | static long de4x5_switch_mac_port(struct net_device *dev); | |
989 | static int gep_rd(struct net_device *dev); | |
990 | static void gep_wr(s32 data, struct net_device *dev); | |
991 | static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec); | |
992 | static void yawn(struct net_device *dev, int state); | |
993 | static void de4x5_parse_params(struct net_device *dev); | |
994 | static void de4x5_dbg_open(struct net_device *dev); | |
995 | static void de4x5_dbg_mii(struct net_device *dev, int k); | |
996 | static void de4x5_dbg_media(struct net_device *dev); | |
997 | static void de4x5_dbg_srom(struct de4x5_srom *p); | |
998 | static void de4x5_dbg_rx(struct sk_buff *skb, int len); | |
999 | static int de4x5_strncmp(char *a, char *b, int n); | |
1000 | static int dc21041_infoleaf(struct net_device *dev); | |
1001 | static int dc21140_infoleaf(struct net_device *dev); | |
1002 | static int dc21142_infoleaf(struct net_device *dev); | |
1003 | static int dc21143_infoleaf(struct net_device *dev); | |
1004 | static int type0_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1005 | static int type1_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1006 | static int type2_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1007 | static int type3_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1008 | static int type4_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1009 | static int type5_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1010 | static int compact_infoblock(struct net_device *dev, u_char count, u_char *p); | |
1011 | ||
1012 | /* | |
1013 | ** Note now that module autoprobing is allowed under EISA and PCI. The | |
1014 | ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes | |
1015 | ** to "do the right thing". | |
1016 | */ | |
1017 | ||
1018 | static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */ | |
1019 | ||
1020 | module_param(io, int, 0); | |
1021 | module_param(de4x5_debug, int, 0); | |
1022 | module_param(dec_only, int, 0); | |
1023 | module_param(args, charp, 0); | |
1024 | ||
1025 | MODULE_PARM_DESC(io, "de4x5 I/O base address"); | |
1026 | MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask"); | |
1027 | MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)"); | |
1028 | MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details"); | |
1029 | MODULE_LICENSE("GPL"); | |
1030 | ||
1031 | /* | |
1032 | ** List the SROM infoleaf functions and chipsets | |
1033 | */ | |
1034 | struct InfoLeaf { | |
1035 | int chipset; | |
1036 | int (*fn)(struct net_device *); | |
1037 | }; | |
1038 | static struct InfoLeaf infoleaf_array[] = { | |
1039 | {DC21041, dc21041_infoleaf}, | |
1040 | {DC21140, dc21140_infoleaf}, | |
1041 | {DC21142, dc21142_infoleaf}, | |
1042 | {DC21143, dc21143_infoleaf} | |
1043 | }; | |
e9edda69 | 1044 | #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array) |
1da177e4 LT |
1045 | |
1046 | /* | |
1047 | ** List the SROM info block functions | |
1048 | */ | |
1049 | static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = { | |
1050 | type0_infoblock, | |
1051 | type1_infoblock, | |
1052 | type2_infoblock, | |
1053 | type3_infoblock, | |
1054 | type4_infoblock, | |
1055 | type5_infoblock, | |
1056 | compact_infoblock | |
1057 | }; | |
1058 | ||
e9edda69 | 1059 | #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1) |
1da177e4 LT |
1060 | |
1061 | /* | |
1062 | ** Miscellaneous defines... | |
1063 | */ | |
1064 | #define RESET_DE4X5 {\ | |
1065 | int i;\ | |
1066 | i=inl(DE4X5_BMR);\ | |
1067 | mdelay(1);\ | |
1068 | outl(i | BMR_SWR, DE4X5_BMR);\ | |
1069 | mdelay(1);\ | |
1070 | outl(i, DE4X5_BMR);\ | |
1071 | mdelay(1);\ | |
1072 | for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\ | |
1073 | mdelay(1);\ | |
1074 | } | |
1075 | ||
1076 | #define PHY_HARD_RESET {\ | |
1077 | outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\ | |
1078 | mdelay(1); /* Assert for 1ms */\ | |
1079 | outl(0x00, DE4X5_GEP);\ | |
1080 | mdelay(2); /* Wait for 2ms */\ | |
1081 | } | |
1082 | ||
f3b197ac JG |
1083 | |
1084 | static int __devinit | |
1da177e4 LT |
1085 | de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev) |
1086 | { | |
1087 | char name[DE4X5_NAME_LENGTH + 1]; | |
1088 | struct de4x5_private *lp = netdev_priv(dev); | |
1089 | struct pci_dev *pdev = NULL; | |
1090 | int i, status=0; | |
0795af57 | 1091 | DECLARE_MAC_BUF(mac); |
1da177e4 LT |
1092 | |
1093 | gendev->driver_data = dev; | |
1094 | ||
1095 | /* Ensure we're not sleeping */ | |
1096 | if (lp->bus == EISA) { | |
1097 | outb(WAKEUP, PCI_CFPM); | |
1098 | } else { | |
1099 | pdev = to_pci_dev (gendev); | |
1100 | pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP); | |
1101 | } | |
1102 | mdelay(10); | |
1103 | ||
1104 | RESET_DE4X5; | |
f3b197ac | 1105 | |
1da177e4 LT |
1106 | if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) { |
1107 | return -ENXIO; /* Hardware could not reset */ | |
1108 | } | |
f3b197ac JG |
1109 | |
1110 | /* | |
1da177e4 LT |
1111 | ** Now find out what kind of DC21040/DC21041/DC21140 board we have. |
1112 | */ | |
eb034a79 | 1113 | lp->useSROM = false; |
1da177e4 LT |
1114 | if (lp->bus == PCI) { |
1115 | PCI_signature(name, lp); | |
1116 | } else { | |
1117 | EISA_signature(name, gendev); | |
1118 | } | |
f3b197ac | 1119 | |
1da177e4 LT |
1120 | if (*name == '\0') { /* Not found a board signature */ |
1121 | return -ENXIO; | |
1122 | } | |
f3b197ac | 1123 | |
1da177e4 LT |
1124 | dev->base_addr = iobase; |
1125 | printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase); | |
f3b197ac | 1126 | |
1da177e4 | 1127 | status = get_hw_addr(dev); |
0795af57 | 1128 | printk(", h/w address %s\n", print_mac(mac, dev->dev_addr)); |
f3b197ac | 1129 | |
1da177e4 LT |
1130 | if (status != 0) { |
1131 | printk(" which has an Ethernet PROM CRC error.\n"); | |
1132 | return -ENXIO; | |
1133 | } else { | |
1134 | lp->cache.gepc = GEP_INIT; | |
1135 | lp->asBit = GEP_SLNK; | |
1136 | lp->asPolarity = GEP_SLNK; | |
eb034a79 | 1137 | lp->asBitValid = ~0; |
1da177e4 LT |
1138 | lp->timeout = -1; |
1139 | lp->gendev = gendev; | |
1140 | spin_lock_init(&lp->lock); | |
1141 | init_timer(&lp->timer); | |
1142 | de4x5_parse_params(dev); | |
1143 | ||
1144 | /* | |
1145 | ** Choose correct autosensing in case someone messed up | |
1146 | */ | |
1147 | lp->autosense = lp->params.autosense; | |
1148 | if (lp->chipset != DC21140) { | |
1149 | if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) { | |
1150 | lp->params.autosense = TP; | |
1151 | } | |
1152 | if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) { | |
1153 | lp->params.autosense = BNC; | |
1154 | } | |
1155 | } | |
1156 | lp->fdx = lp->params.fdx; | |
1157 | sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id); | |
1158 | ||
1159 | lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc); | |
49345103 | 1160 | #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY) |
1da177e4 LT |
1161 | lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN; |
1162 | #endif | |
1163 | lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size, | |
1164 | &lp->dma_rings, GFP_ATOMIC); | |
1165 | if (lp->rx_ring == NULL) { | |
1166 | return -ENOMEM; | |
1167 | } | |
1168 | ||
1169 | lp->tx_ring = lp->rx_ring + NUM_RX_DESC; | |
f3b197ac | 1170 | |
1da177e4 LT |
1171 | /* |
1172 | ** Set up the RX descriptor ring (Intels) | |
f3b197ac | 1173 | ** Allocate contiguous receive buffers, long word aligned (Alphas) |
1da177e4 | 1174 | */ |
49345103 | 1175 | #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY) |
1da177e4 LT |
1176 | for (i=0; i<NUM_RX_DESC; i++) { |
1177 | lp->rx_ring[i].status = 0; | |
1178 | lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); | |
1179 | lp->rx_ring[i].buf = 0; | |
1180 | lp->rx_ring[i].next = 0; | |
1181 | lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ | |
1182 | } | |
1183 | ||
1184 | #else | |
1185 | { | |
1186 | dma_addr_t dma_rx_bufs; | |
1187 | ||
1188 | dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC) | |
1189 | * sizeof(struct de4x5_desc); | |
1190 | dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN; | |
1191 | lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC | |
1192 | + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN); | |
1193 | for (i=0; i<NUM_RX_DESC; i++) { | |
1194 | lp->rx_ring[i].status = 0; | |
1195 | lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ); | |
1196 | lp->rx_ring[i].buf = | |
1197 | cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ); | |
1198 | lp->rx_ring[i].next = 0; | |
1199 | lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */ | |
1200 | } | |
1201 | ||
1202 | } | |
1203 | #endif | |
1204 | ||
1205 | barrier(); | |
1206 | ||
1207 | lp->rxRingSize = NUM_RX_DESC; | |
1208 | lp->txRingSize = NUM_TX_DESC; | |
f3b197ac | 1209 | |
1da177e4 LT |
1210 | /* Write the end of list marker to the descriptor lists */ |
1211 | lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER); | |
1212 | lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER); | |
1213 | ||
1214 | /* Tell the adapter where the TX/RX rings are located. */ | |
1215 | outl(lp->dma_rings, DE4X5_RRBA); | |
1216 | outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), | |
1217 | DE4X5_TRBA); | |
f3b197ac | 1218 | |
1da177e4 LT |
1219 | /* Initialise the IRQ mask and Enable/Disable */ |
1220 | lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM; | |
1221 | lp->irq_en = IMR_NIM | IMR_AIM; | |
1222 | ||
1223 | /* Create a loopback packet frame for later media probing */ | |
1224 | create_packet(dev, lp->frame, sizeof(lp->frame)); | |
1225 | ||
1226 | /* Check if the RX overflow bug needs testing for */ | |
1227 | i = lp->cfrv & 0x000000fe; | |
1228 | if ((lp->chipset == DC21140) && (i == 0x20)) { | |
1229 | lp->rx_ovf = 1; | |
1230 | } | |
1231 | ||
1232 | /* Initialise the SROM pointers if possible */ | |
1233 | if (lp->useSROM) { | |
1234 | lp->state = INITIALISED; | |
1235 | if (srom_infoleaf_info(dev)) { | |
1236 | dma_free_coherent (gendev, lp->dma_size, | |
1237 | lp->rx_ring, lp->dma_rings); | |
1238 | return -ENXIO; | |
1239 | } | |
1240 | srom_init(dev); | |
1241 | } | |
1242 | ||
1243 | lp->state = CLOSED; | |
1244 | ||
1245 | /* | |
1246 | ** Check for an MII interface | |
1247 | */ | |
1248 | if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) { | |
1249 | mii_get_phy(dev); | |
1250 | } | |
f3b197ac | 1251 | |
1da177e4 | 1252 | printk(" and requires IRQ%d (provided by %s).\n", dev->irq, |
1da177e4 LT |
1253 | ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG")); |
1254 | } | |
f3b197ac | 1255 | |
1da177e4 LT |
1256 | if (de4x5_debug & DEBUG_VERSION) { |
1257 | printk(version); | |
1258 | } | |
f3b197ac | 1259 | |
1da177e4 | 1260 | /* The DE4X5-specific entries in the device structure. */ |
1da177e4 LT |
1261 | SET_NETDEV_DEV(dev, gendev); |
1262 | dev->open = &de4x5_open; | |
1263 | dev->hard_start_xmit = &de4x5_queue_pkt; | |
1264 | dev->stop = &de4x5_close; | |
1265 | dev->get_stats = &de4x5_get_stats; | |
1266 | dev->set_multicast_list = &set_multicast_list; | |
1267 | dev->do_ioctl = &de4x5_ioctl; | |
f3b197ac | 1268 | |
1da177e4 | 1269 | dev->mem_start = 0; |
f3b197ac | 1270 | |
1da177e4 LT |
1271 | /* Fill in the generic fields of the device structure. */ |
1272 | if ((status = register_netdev (dev))) { | |
1273 | dma_free_coherent (gendev, lp->dma_size, | |
1274 | lp->rx_ring, lp->dma_rings); | |
1275 | return status; | |
1276 | } | |
f3b197ac | 1277 | |
1da177e4 LT |
1278 | /* Let the adapter sleep to save power */ |
1279 | yawn(dev, SLEEP); | |
f3b197ac | 1280 | |
1da177e4 LT |
1281 | return status; |
1282 | } | |
1283 | ||
f3b197ac | 1284 | |
1da177e4 LT |
1285 | static int |
1286 | de4x5_open(struct net_device *dev) | |
1287 | { | |
1288 | struct de4x5_private *lp = netdev_priv(dev); | |
1289 | u_long iobase = dev->base_addr; | |
1290 | int i, status = 0; | |
1291 | s32 omr; | |
1292 | ||
1293 | /* Allocate the RX buffers */ | |
1294 | for (i=0; i<lp->rxRingSize; i++) { | |
1295 | if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) { | |
1296 | de4x5_free_rx_buffs(dev); | |
1297 | return -EAGAIN; | |
1298 | } | |
1299 | } | |
1300 | ||
1301 | /* | |
1302 | ** Wake up the adapter | |
1303 | */ | |
1304 | yawn(dev, WAKEUP); | |
1305 | ||
f3b197ac JG |
1306 | /* |
1307 | ** Re-initialize the DE4X5... | |
1da177e4 LT |
1308 | */ |
1309 | status = de4x5_init(dev); | |
1310 | spin_lock_init(&lp->lock); | |
1311 | lp->state = OPEN; | |
1312 | de4x5_dbg_open(dev); | |
f3b197ac | 1313 | |
1fb9df5d | 1314 | if (request_irq(dev->irq, (void *)de4x5_interrupt, IRQF_SHARED, |
1da177e4 LT |
1315 | lp->adapter_name, dev)) { |
1316 | printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq); | |
1fb9df5d | 1317 | if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED, |
1da177e4 LT |
1318 | lp->adapter_name, dev)) { |
1319 | printk("\n Cannot get IRQ- reconfigure your hardware.\n"); | |
1320 | disable_ast(dev); | |
1321 | de4x5_free_rx_buffs(dev); | |
1322 | de4x5_free_tx_buffs(dev); | |
1323 | yawn(dev, SLEEP); | |
1324 | lp->state = CLOSED; | |
1325 | return -EAGAIN; | |
1326 | } else { | |
1327 | printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n"); | |
1328 | printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n"); | |
1329 | } | |
1330 | } | |
1331 | ||
1332 | lp->interrupt = UNMASK_INTERRUPTS; | |
1333 | dev->trans_start = jiffies; | |
f3b197ac | 1334 | |
1da177e4 | 1335 | START_DE4X5; |
f3b197ac | 1336 | |
1da177e4 | 1337 | de4x5_setup_intr(dev); |
f3b197ac | 1338 | |
1da177e4 LT |
1339 | if (de4x5_debug & DEBUG_OPEN) { |
1340 | printk("\tsts: 0x%08x\n", inl(DE4X5_STS)); | |
1341 | printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR)); | |
1342 | printk("\timr: 0x%08x\n", inl(DE4X5_IMR)); | |
1343 | printk("\tomr: 0x%08x\n", inl(DE4X5_OMR)); | |
1344 | printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR)); | |
1345 | printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR)); | |
1346 | printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR)); | |
1347 | printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR)); | |
1348 | } | |
f3b197ac | 1349 | |
1da177e4 LT |
1350 | return status; |
1351 | } | |
1352 | ||
1353 | /* | |
1354 | ** Initialize the DE4X5 operating conditions. NB: a chip problem with the | |
1355 | ** DC21140 requires using perfect filtering mode for that chip. Since I can't | |
1356 | ** see why I'd want > 14 multicast addresses, I have changed all chips to use | |
1357 | ** the perfect filtering mode. Keep the DMA burst length at 8: there seems | |
1358 | ** to be data corruption problems if it is larger (UDP errors seen from a | |
1359 | ** ttcp source). | |
1360 | */ | |
1361 | static int | |
1362 | de4x5_init(struct net_device *dev) | |
f3b197ac | 1363 | { |
1da177e4 LT |
1364 | /* Lock out other processes whilst setting up the hardware */ |
1365 | netif_stop_queue(dev); | |
f3b197ac | 1366 | |
1da177e4 | 1367 | de4x5_sw_reset(dev); |
f3b197ac | 1368 | |
1da177e4 LT |
1369 | /* Autoconfigure the connected port */ |
1370 | autoconf_media(dev); | |
f3b197ac | 1371 | |
1da177e4 LT |
1372 | return 0; |
1373 | } | |
1374 | ||
1375 | static int | |
1376 | de4x5_sw_reset(struct net_device *dev) | |
1377 | { | |
1378 | struct de4x5_private *lp = netdev_priv(dev); | |
1379 | u_long iobase = dev->base_addr; | |
1380 | int i, j, status = 0; | |
1381 | s32 bmr, omr; | |
f3b197ac | 1382 | |
1da177e4 LT |
1383 | /* Select the MII or SRL port now and RESET the MAC */ |
1384 | if (!lp->useSROM) { | |
1385 | if (lp->phy[lp->active].id != 0) { | |
1386 | lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD; | |
1387 | } else { | |
1388 | lp->infoblock_csr6 = OMR_SDP | OMR_TTM; | |
1389 | } | |
1390 | de4x5_switch_mac_port(dev); | |
1391 | } | |
1392 | ||
f3b197ac | 1393 | /* |
1da177e4 LT |
1394 | ** Set the programmable burst length to 8 longwords for all the DC21140 |
1395 | ** Fasternet chips and 4 longwords for all others: DMA errors result | |
1396 | ** without these values. Cache align 16 long. | |
1397 | */ | |
1398 | bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN; | |
1399 | bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0); | |
1400 | outl(bmr, DE4X5_BMR); | |
1401 | ||
1402 | omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */ | |
1403 | if (lp->chipset == DC21140) { | |
1404 | omr |= (OMR_SDP | OMR_SB); | |
1405 | } | |
1406 | lp->setup_f = PERFECT; | |
1407 | outl(lp->dma_rings, DE4X5_RRBA); | |
1408 | outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), | |
1409 | DE4X5_TRBA); | |
f3b197ac | 1410 | |
1da177e4 LT |
1411 | lp->rx_new = lp->rx_old = 0; |
1412 | lp->tx_new = lp->tx_old = 0; | |
f3b197ac | 1413 | |
1da177e4 LT |
1414 | for (i = 0; i < lp->rxRingSize; i++) { |
1415 | lp->rx_ring[i].status = cpu_to_le32(R_OWN); | |
1416 | } | |
f3b197ac | 1417 | |
1da177e4 LT |
1418 | for (i = 0; i < lp->txRingSize; i++) { |
1419 | lp->tx_ring[i].status = cpu_to_le32(0); | |
1420 | } | |
f3b197ac | 1421 | |
1da177e4 LT |
1422 | barrier(); |
1423 | ||
1424 | /* Build the setup frame depending on filtering mode */ | |
1425 | SetMulticastFilter(dev); | |
f3b197ac | 1426 | |
1da177e4 LT |
1427 | load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1); |
1428 | outl(omr|OMR_ST, DE4X5_OMR); | |
1429 | ||
1430 | /* Poll for setup frame completion (adapter interrupts are disabled now) */ | |
1431 | ||
1432 | for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */ | |
1433 | mdelay(1); | |
1434 | if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1; | |
1435 | } | |
1436 | outl(omr, DE4X5_OMR); /* Stop everything! */ | |
1437 | ||
1438 | if (j == 0) { | |
f3b197ac | 1439 | printk("%s: Setup frame timed out, status %08x\n", dev->name, |
1da177e4 LT |
1440 | inl(DE4X5_STS)); |
1441 | status = -EIO; | |
1442 | } | |
f3b197ac | 1443 | |
1da177e4 LT |
1444 | lp->tx_new = (++lp->tx_new) % lp->txRingSize; |
1445 | lp->tx_old = lp->tx_new; | |
1446 | ||
1447 | return status; | |
1448 | } | |
1449 | ||
f3b197ac | 1450 | /* |
1da177e4 LT |
1451 | ** Writes a socket buffer address to the next available transmit descriptor. |
1452 | */ | |
1453 | static int | |
1454 | de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev) | |
1455 | { | |
1456 | struct de4x5_private *lp = netdev_priv(dev); | |
1457 | u_long iobase = dev->base_addr; | |
1458 | int status = 0; | |
1459 | u_long flags = 0; | |
1460 | ||
1461 | netif_stop_queue(dev); | |
eb034a79 | 1462 | if (!lp->tx_enable) { /* Cannot send for now */ |
f3b197ac | 1463 | return -1; |
1da177e4 | 1464 | } |
f3b197ac | 1465 | |
1da177e4 LT |
1466 | /* |
1467 | ** Clean out the TX ring asynchronously to interrupts - sometimes the | |
1468 | ** interrupts are lost by delayed descriptor status updates relative to | |
1469 | ** the irq assertion, especially with a busy PCI bus. | |
1470 | */ | |
1471 | spin_lock_irqsave(&lp->lock, flags); | |
1472 | de4x5_tx(dev); | |
1473 | spin_unlock_irqrestore(&lp->lock, flags); | |
1474 | ||
1475 | /* Test if cache is already locked - requeue skb if so */ | |
f3b197ac | 1476 | if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt) |
1da177e4 LT |
1477 | return -1; |
1478 | ||
1479 | /* Transmit descriptor ring full or stale skb */ | |
1480 | if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) { | |
1481 | if (lp->interrupt) { | |
1482 | de4x5_putb_cache(dev, skb); /* Requeue the buffer */ | |
1483 | } else { | |
1484 | de4x5_put_cache(dev, skb); | |
1485 | } | |
1486 | if (de4x5_debug & DEBUG_TX) { | |
1487 | printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO"); | |
1488 | } | |
1489 | } else if (skb->len > 0) { | |
1490 | /* If we already have stuff queued locally, use that first */ | |
1491 | if (lp->cache.skb && !lp->interrupt) { | |
1492 | de4x5_put_cache(dev, skb); | |
1493 | skb = de4x5_get_cache(dev); | |
1494 | } | |
1495 | ||
1496 | while (skb && !netif_queue_stopped(dev) && | |
1497 | (u_long) lp->tx_skb[lp->tx_new] <= 1) { | |
1498 | spin_lock_irqsave(&lp->lock, flags); | |
1499 | netif_stop_queue(dev); | |
1500 | load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb); | |
1501 | lp->stats.tx_bytes += skb->len; | |
1502 | outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */ | |
f3b197ac | 1503 | |
1da177e4 LT |
1504 | lp->tx_new = (++lp->tx_new) % lp->txRingSize; |
1505 | dev->trans_start = jiffies; | |
f3b197ac | 1506 | |
1da177e4 LT |
1507 | if (TX_BUFFS_AVAIL) { |
1508 | netif_start_queue(dev); /* Another pkt may be queued */ | |
1509 | } | |
1510 | skb = de4x5_get_cache(dev); | |
1511 | spin_unlock_irqrestore(&lp->lock, flags); | |
1512 | } | |
1513 | if (skb) de4x5_putb_cache(dev, skb); | |
1514 | } | |
f3b197ac | 1515 | |
1da177e4 LT |
1516 | lp->cache.lock = 0; |
1517 | ||
1518 | return status; | |
1519 | } | |
1520 | ||
1521 | /* | |
f3b197ac JG |
1522 | ** The DE4X5 interrupt handler. |
1523 | ** | |
1da177e4 LT |
1524 | ** I/O Read/Writes through intermediate PCI bridges are never 'posted', |
1525 | ** so that the asserted interrupt always has some real data to work with - | |
1526 | ** if these I/O accesses are ever changed to memory accesses, ensure the | |
1527 | ** STS write is read immediately to complete the transaction if the adapter | |
1528 | ** is not on bus 0. Lost interrupts can still occur when the PCI bus load | |
1529 | ** is high and descriptor status bits cannot be set before the associated | |
1530 | ** interrupt is asserted and this routine entered. | |
1531 | */ | |
1532 | static irqreturn_t | |
7d12e780 | 1533 | de4x5_interrupt(int irq, void *dev_id) |
1da177e4 | 1534 | { |
c31f28e7 | 1535 | struct net_device *dev = dev_id; |
1da177e4 LT |
1536 | struct de4x5_private *lp; |
1537 | s32 imr, omr, sts, limit; | |
1538 | u_long iobase; | |
1539 | unsigned int handled = 0; | |
f3b197ac | 1540 | |
1da177e4 LT |
1541 | lp = netdev_priv(dev); |
1542 | spin_lock(&lp->lock); | |
1543 | iobase = dev->base_addr; | |
f3b197ac | 1544 | |
1da177e4 LT |
1545 | DISABLE_IRQs; /* Ensure non re-entrancy */ |
1546 | ||
1547 | if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt)) | |
1548 | printk("%s: Re-entering the interrupt handler.\n", dev->name); | |
1549 | ||
1550 | synchronize_irq(dev->irq); | |
f3b197ac | 1551 | |
1da177e4 LT |
1552 | for (limit=0; limit<8; limit++) { |
1553 | sts = inl(DE4X5_STS); /* Read IRQ status */ | |
1554 | outl(sts, DE4X5_STS); /* Reset the board interrupts */ | |
f3b197ac | 1555 | |
1da177e4 LT |
1556 | if (!(sts & lp->irq_mask)) break;/* All done */ |
1557 | handled = 1; | |
f3b197ac | 1558 | |
1da177e4 LT |
1559 | if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */ |
1560 | de4x5_rx(dev); | |
f3b197ac | 1561 | |
1da177e4 | 1562 | if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */ |
f3b197ac JG |
1563 | de4x5_tx(dev); |
1564 | ||
1da177e4 LT |
1565 | if (sts & STS_LNF) { /* TP Link has failed */ |
1566 | lp->irq_mask &= ~IMR_LFM; | |
1567 | } | |
f3b197ac | 1568 | |
1da177e4 LT |
1569 | if (sts & STS_UNF) { /* Transmit underrun */ |
1570 | de4x5_txur(dev); | |
1571 | } | |
f3b197ac | 1572 | |
1da177e4 LT |
1573 | if (sts & STS_SE) { /* Bus Error */ |
1574 | STOP_DE4X5; | |
1575 | printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n", | |
1576 | dev->name, sts); | |
1577 | spin_unlock(&lp->lock); | |
1578 | return IRQ_HANDLED; | |
1579 | } | |
1580 | } | |
1581 | ||
1582 | /* Load the TX ring with any locally stored packets */ | |
1583 | if (!test_and_set_bit(0, (void *)&lp->cache.lock)) { | |
1584 | while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) { | |
1585 | de4x5_queue_pkt(de4x5_get_cache(dev), dev); | |
1586 | } | |
1587 | lp->cache.lock = 0; | |
1588 | } | |
1589 | ||
1590 | lp->interrupt = UNMASK_INTERRUPTS; | |
1591 | ENABLE_IRQs; | |
1592 | spin_unlock(&lp->lock); | |
f3b197ac | 1593 | |
1da177e4 LT |
1594 | return IRQ_RETVAL(handled); |
1595 | } | |
1596 | ||
1597 | static int | |
1598 | de4x5_rx(struct net_device *dev) | |
1599 | { | |
1600 | struct de4x5_private *lp = netdev_priv(dev); | |
1601 | u_long iobase = dev->base_addr; | |
1602 | int entry; | |
1603 | s32 status; | |
f3b197ac | 1604 | |
1da177e4 LT |
1605 | for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0; |
1606 | entry=lp->rx_new) { | |
1607 | status = (s32)le32_to_cpu(lp->rx_ring[entry].status); | |
f3b197ac | 1608 | |
1da177e4 LT |
1609 | if (lp->rx_ovf) { |
1610 | if (inl(DE4X5_MFC) & MFC_FOCM) { | |
1611 | de4x5_rx_ovfc(dev); | |
1612 | break; | |
1613 | } | |
1614 | } | |
1615 | ||
1616 | if (status & RD_FS) { /* Remember the start of frame */ | |
1617 | lp->rx_old = entry; | |
1618 | } | |
f3b197ac | 1619 | |
1da177e4 LT |
1620 | if (status & RD_LS) { /* Valid frame status */ |
1621 | if (lp->tx_enable) lp->linkOK++; | |
1622 | if (status & RD_ES) { /* There was an error. */ | |
1623 | lp->stats.rx_errors++; /* Update the error stats. */ | |
1624 | if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++; | |
1625 | if (status & RD_CE) lp->stats.rx_crc_errors++; | |
1626 | if (status & RD_OF) lp->stats.rx_fifo_errors++; | |
1627 | if (status & RD_TL) lp->stats.rx_length_errors++; | |
1628 | if (status & RD_RF) lp->pktStats.rx_runt_frames++; | |
1629 | if (status & RD_CS) lp->pktStats.rx_collision++; | |
1630 | if (status & RD_DB) lp->pktStats.rx_dribble++; | |
1631 | if (status & RD_OF) lp->pktStats.rx_overflow++; | |
1632 | } else { /* A valid frame received */ | |
1633 | struct sk_buff *skb; | |
1634 | short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status) | |
1635 | >> 16) - 4; | |
f3b197ac | 1636 | |
1da177e4 | 1637 | if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) { |
f3b197ac | 1638 | printk("%s: Insufficient memory; nuking packet.\n", |
1da177e4 LT |
1639 | dev->name); |
1640 | lp->stats.rx_dropped++; | |
1641 | } else { | |
1642 | de4x5_dbg_rx(skb, pkt_len); | |
1643 | ||
1644 | /* Push up the protocol stack */ | |
1645 | skb->protocol=eth_type_trans(skb,dev); | |
1646 | de4x5_local_stats(dev, skb->data, pkt_len); | |
1647 | netif_rx(skb); | |
f3b197ac | 1648 | |
1da177e4 LT |
1649 | /* Update stats */ |
1650 | dev->last_rx = jiffies; | |
1651 | lp->stats.rx_packets++; | |
1652 | lp->stats.rx_bytes += pkt_len; | |
1653 | } | |
1654 | } | |
f3b197ac | 1655 | |
1da177e4 LT |
1656 | /* Change buffer ownership for this frame, back to the adapter */ |
1657 | for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) { | |
1658 | lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN); | |
1659 | barrier(); | |
1660 | } | |
1661 | lp->rx_ring[entry].status = cpu_to_le32(R_OWN); | |
1662 | barrier(); | |
1663 | } | |
f3b197ac | 1664 | |
1da177e4 LT |
1665 | /* |
1666 | ** Update entry information | |
1667 | */ | |
1668 | lp->rx_new = (++lp->rx_new) % lp->rxRingSize; | |
1669 | } | |
f3b197ac | 1670 | |
1da177e4 LT |
1671 | return 0; |
1672 | } | |
1673 | ||
1674 | static inline void | |
1675 | de4x5_free_tx_buff(struct de4x5_private *lp, int entry) | |
1676 | { | |
1677 | dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf), | |
1678 | le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1, | |
1679 | DMA_TO_DEVICE); | |
1680 | if ((u_long) lp->tx_skb[entry] > 1) | |
1681 | dev_kfree_skb_irq(lp->tx_skb[entry]); | |
1682 | lp->tx_skb[entry] = NULL; | |
1683 | } | |
1684 | ||
1685 | /* | |
1686 | ** Buffer sent - check for TX buffer errors. | |
1687 | */ | |
1688 | static int | |
1689 | de4x5_tx(struct net_device *dev) | |
1690 | { | |
1691 | struct de4x5_private *lp = netdev_priv(dev); | |
1692 | u_long iobase = dev->base_addr; | |
1693 | int entry; | |
1694 | s32 status; | |
f3b197ac | 1695 | |
1da177e4 LT |
1696 | for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) { |
1697 | status = (s32)le32_to_cpu(lp->tx_ring[entry].status); | |
1698 | if (status < 0) { /* Buffer not sent yet */ | |
1699 | break; | |
1700 | } else if (status != 0x7fffffff) { /* Not setup frame */ | |
1701 | if (status & TD_ES) { /* An error happened */ | |
f3b197ac | 1702 | lp->stats.tx_errors++; |
1da177e4 LT |
1703 | if (status & TD_NC) lp->stats.tx_carrier_errors++; |
1704 | if (status & TD_LC) lp->stats.tx_window_errors++; | |
1705 | if (status & TD_UF) lp->stats.tx_fifo_errors++; | |
1706 | if (status & TD_EC) lp->pktStats.excessive_collisions++; | |
1707 | if (status & TD_DE) lp->stats.tx_aborted_errors++; | |
f3b197ac | 1708 | |
1da177e4 LT |
1709 | if (TX_PKT_PENDING) { |
1710 | outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */ | |
1711 | } | |
1712 | } else { /* Packet sent */ | |
1713 | lp->stats.tx_packets++; | |
1714 | if (lp->tx_enable) lp->linkOK++; | |
1715 | } | |
1716 | /* Update the collision counter */ | |
f3b197ac | 1717 | lp->stats.collisions += ((status & TD_EC) ? 16 : |
1da177e4 LT |
1718 | ((status & TD_CC) >> 3)); |
1719 | ||
1720 | /* Free the buffer. */ | |
1721 | if (lp->tx_skb[entry] != NULL) | |
1722 | de4x5_free_tx_buff(lp, entry); | |
1723 | } | |
f3b197ac | 1724 | |
1da177e4 LT |
1725 | /* Update all the pointers */ |
1726 | lp->tx_old = (++lp->tx_old) % lp->txRingSize; | |
1727 | } | |
1728 | ||
1729 | /* Any resources available? */ | |
1730 | if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) { | |
1731 | if (lp->interrupt) | |
1732 | netif_wake_queue(dev); | |
1733 | else | |
1734 | netif_start_queue(dev); | |
1735 | } | |
f3b197ac | 1736 | |
1da177e4 LT |
1737 | return 0; |
1738 | } | |
1739 | ||
1740 | static int | |
1741 | de4x5_ast(struct net_device *dev) | |
1742 | { | |
1743 | struct de4x5_private *lp = netdev_priv(dev); | |
1744 | int next_tick = DE4X5_AUTOSENSE_MS; | |
f3b197ac | 1745 | |
1da177e4 | 1746 | disable_ast(dev); |
f3b197ac | 1747 | |
1da177e4 LT |
1748 | if (lp->useSROM) { |
1749 | next_tick = srom_autoconf(dev); | |
1750 | } else if (lp->chipset == DC21140) { | |
1751 | next_tick = dc21140m_autoconf(dev); | |
1752 | } else if (lp->chipset == DC21041) { | |
1753 | next_tick = dc21041_autoconf(dev); | |
1754 | } else if (lp->chipset == DC21040) { | |
1755 | next_tick = dc21040_autoconf(dev); | |
1756 | } | |
1757 | lp->linkOK = 0; | |
1758 | enable_ast(dev, next_tick); | |
f3b197ac | 1759 | |
1da177e4 LT |
1760 | return 0; |
1761 | } | |
1762 | ||
1763 | static int | |
1764 | de4x5_txur(struct net_device *dev) | |
1765 | { | |
1766 | struct de4x5_private *lp = netdev_priv(dev); | |
1767 | u_long iobase = dev->base_addr; | |
1768 | int omr; | |
1769 | ||
1770 | omr = inl(DE4X5_OMR); | |
1771 | if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) { | |
1772 | omr &= ~(OMR_ST|OMR_SR); | |
1773 | outl(omr, DE4X5_OMR); | |
1774 | while (inl(DE4X5_STS) & STS_TS); | |
1775 | if ((omr & OMR_TR) < OMR_TR) { | |
1776 | omr += 0x4000; | |
1777 | } else { | |
1778 | omr |= OMR_SF; | |
1779 | } | |
1780 | outl(omr | OMR_ST | OMR_SR, DE4X5_OMR); | |
1781 | } | |
f3b197ac | 1782 | |
1da177e4 LT |
1783 | return 0; |
1784 | } | |
1785 | ||
f3b197ac | 1786 | static int |
1da177e4 LT |
1787 | de4x5_rx_ovfc(struct net_device *dev) |
1788 | { | |
1789 | struct de4x5_private *lp = netdev_priv(dev); | |
1790 | u_long iobase = dev->base_addr; | |
1791 | int omr; | |
1792 | ||
1793 | omr = inl(DE4X5_OMR); | |
1794 | outl(omr & ~OMR_SR, DE4X5_OMR); | |
1795 | while (inl(DE4X5_STS) & STS_RS); | |
1796 | ||
1797 | for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) { | |
1798 | lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN); | |
1799 | lp->rx_new = (++lp->rx_new % lp->rxRingSize); | |
1800 | } | |
1801 | ||
1802 | outl(omr, DE4X5_OMR); | |
f3b197ac | 1803 | |
1da177e4 LT |
1804 | return 0; |
1805 | } | |
1806 | ||
1807 | static int | |
1808 | de4x5_close(struct net_device *dev) | |
1809 | { | |
1810 | struct de4x5_private *lp = netdev_priv(dev); | |
1811 | u_long iobase = dev->base_addr; | |
1812 | s32 imr, omr; | |
f3b197ac | 1813 | |
1da177e4 LT |
1814 | disable_ast(dev); |
1815 | ||
1816 | netif_stop_queue(dev); | |
f3b197ac | 1817 | |
1da177e4 LT |
1818 | if (de4x5_debug & DEBUG_CLOSE) { |
1819 | printk("%s: Shutting down ethercard, status was %8.8x.\n", | |
1820 | dev->name, inl(DE4X5_STS)); | |
1821 | } | |
f3b197ac JG |
1822 | |
1823 | /* | |
1da177e4 LT |
1824 | ** We stop the DE4X5 here... mask interrupts and stop TX & RX |
1825 | */ | |
1826 | DISABLE_IRQs; | |
1827 | STOP_DE4X5; | |
f3b197ac | 1828 | |
1da177e4 LT |
1829 | /* Free the associated irq */ |
1830 | free_irq(dev->irq, dev); | |
1831 | lp->state = CLOSED; | |
1832 | ||
1833 | /* Free any socket buffers */ | |
1834 | de4x5_free_rx_buffs(dev); | |
1835 | de4x5_free_tx_buffs(dev); | |
f3b197ac | 1836 | |
1da177e4 LT |
1837 | /* Put the adapter to sleep to save power */ |
1838 | yawn(dev, SLEEP); | |
f3b197ac | 1839 | |
1da177e4 LT |
1840 | return 0; |
1841 | } | |
1842 | ||
1843 | static struct net_device_stats * | |
1844 | de4x5_get_stats(struct net_device *dev) | |
1845 | { | |
1846 | struct de4x5_private *lp = netdev_priv(dev); | |
1847 | u_long iobase = dev->base_addr; | |
f3b197ac | 1848 | |
1da177e4 | 1849 | lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR)); |
f3b197ac | 1850 | |
1da177e4 LT |
1851 | return &lp->stats; |
1852 | } | |
1853 | ||
1854 | static void | |
1855 | de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len) | |
1856 | { | |
1857 | struct de4x5_private *lp = netdev_priv(dev); | |
1858 | int i; | |
1859 | ||
1860 | for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) { | |
1861 | if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) { | |
1862 | lp->pktStats.bins[i]++; | |
1863 | i = DE4X5_PKT_STAT_SZ; | |
1864 | } | |
1865 | } | |
1866 | if (buf[0] & 0x01) { /* Multicast/Broadcast */ | |
1867 | if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) { | |
1868 | lp->pktStats.broadcast++; | |
1869 | } else { | |
1870 | lp->pktStats.multicast++; | |
1871 | } | |
1872 | } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) && | |
1873 | (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) { | |
1874 | lp->pktStats.unicast++; | |
1875 | } | |
f3b197ac | 1876 | |
1da177e4 LT |
1877 | lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */ |
1878 | if (lp->pktStats.bins[0] == 0) { /* Reset counters */ | |
1879 | memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats)); | |
1880 | } | |
1881 | ||
1882 | return; | |
1883 | } | |
1884 | ||
1885 | /* | |
1886 | ** Removes the TD_IC flag from previous descriptor to improve TX performance. | |
1887 | ** If the flag is changed on a descriptor that is being read by the hardware, | |
1888 | ** I assume PCI transaction ordering will mean you are either successful or | |
1889 | ** just miss asserting the change to the hardware. Anyway you're messing with | |
1890 | ** a descriptor you don't own, but this shouldn't kill the chip provided | |
1891 | ** the descriptor register is read only to the hardware. | |
1892 | */ | |
1893 | static void | |
1894 | load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb) | |
1895 | { | |
1896 | struct de4x5_private *lp = netdev_priv(dev); | |
1897 | int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1); | |
1898 | dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE); | |
1899 | ||
1900 | lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma); | |
1901 | lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER); | |
1902 | lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags); | |
1903 | lp->tx_skb[lp->tx_new] = skb; | |
1904 | lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC); | |
1905 | barrier(); | |
1906 | ||
1907 | lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN); | |
1908 | barrier(); | |
1909 | } | |
1910 | ||
1911 | /* | |
1912 | ** Set or clear the multicast filter for this adaptor. | |
1913 | */ | |
1914 | static void | |
1915 | set_multicast_list(struct net_device *dev) | |
1916 | { | |
1917 | struct de4x5_private *lp = netdev_priv(dev); | |
1918 | u_long iobase = dev->base_addr; | |
1919 | ||
1920 | /* First, double check that the adapter is open */ | |
1921 | if (lp->state == OPEN) { | |
1922 | if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */ | |
1923 | u32 omr; | |
1924 | omr = inl(DE4X5_OMR); | |
1925 | omr |= OMR_PR; | |
1926 | outl(omr, DE4X5_OMR); | |
f3b197ac | 1927 | } else { |
1da177e4 | 1928 | SetMulticastFilter(dev); |
f3b197ac | 1929 | load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | |
1da177e4 | 1930 | SETUP_FRAME_LEN, (struct sk_buff *)1); |
f3b197ac | 1931 | |
1da177e4 LT |
1932 | lp->tx_new = (++lp->tx_new) % lp->txRingSize; |
1933 | outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ | |
1934 | dev->trans_start = jiffies; | |
1935 | } | |
1936 | } | |
1937 | } | |
1938 | ||
1939 | /* | |
1940 | ** Calculate the hash code and update the logical address filter | |
1941 | ** from a list of ethernet multicast addresses. | |
1942 | ** Little endian crc one liner from Matt Thomas, DEC. | |
1943 | */ | |
1944 | static void | |
1945 | SetMulticastFilter(struct net_device *dev) | |
1946 | { | |
1947 | struct de4x5_private *lp = netdev_priv(dev); | |
1948 | struct dev_mc_list *dmi=dev->mc_list; | |
1949 | u_long iobase = dev->base_addr; | |
1950 | int i, j, bit, byte; | |
1951 | u16 hashcode; | |
1952 | u32 omr, crc; | |
1953 | char *pa; | |
1954 | unsigned char *addrs; | |
1955 | ||
1956 | omr = inl(DE4X5_OMR); | |
1957 | omr &= ~(OMR_PR | OMR_PM); | |
1958 | pa = build_setup_frame(dev, ALL); /* Build the basic frame */ | |
f3b197ac | 1959 | |
1da177e4 LT |
1960 | if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) { |
1961 | omr |= OMR_PM; /* Pass all multicasts */ | |
1962 | } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */ | |
1963 | for (i=0;i<dev->mc_count;i++) { /* for each address in the list */ | |
1964 | addrs=dmi->dmi_addr; | |
1965 | dmi=dmi->next; | |
f3b197ac | 1966 | if ((*addrs & 0x01) == 1) { /* multicast address? */ |
1da177e4 LT |
1967 | crc = ether_crc_le(ETH_ALEN, addrs); |
1968 | hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */ | |
f3b197ac | 1969 | |
1da177e4 LT |
1970 | byte = hashcode >> 3; /* bit[3-8] -> byte in filter */ |
1971 | bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */ | |
f3b197ac | 1972 | |
1da177e4 LT |
1973 | byte <<= 1; /* calc offset into setup frame */ |
1974 | if (byte & 0x02) { | |
1975 | byte -= 1; | |
1976 | } | |
1977 | lp->setup_frame[byte] |= bit; | |
1978 | } | |
1979 | } | |
1980 | } else { /* Perfect filtering */ | |
1981 | for (j=0; j<dev->mc_count; j++) { | |
1982 | addrs=dmi->dmi_addr; | |
1983 | dmi=dmi->next; | |
f3b197ac | 1984 | for (i=0; i<ETH_ALEN; i++) { |
1da177e4 LT |
1985 | *(pa + (i&1)) = *addrs++; |
1986 | if (i & 0x01) pa += 4; | |
1987 | } | |
1988 | } | |
1989 | } | |
1990 | outl(omr, DE4X5_OMR); | |
f3b197ac | 1991 | |
1da177e4 LT |
1992 | return; |
1993 | } | |
1994 | ||
1995 | #ifdef CONFIG_EISA | |
1996 | ||
1997 | static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST; | |
1998 | ||
1999 | static int __init de4x5_eisa_probe (struct device *gendev) | |
2000 | { | |
2001 | struct eisa_device *edev; | |
2002 | u_long iobase; | |
2003 | u_char irq, regval; | |
2004 | u_short vendor; | |
2005 | u32 cfid; | |
2006 | int status, device; | |
2007 | struct net_device *dev; | |
2008 | struct de4x5_private *lp; | |
2009 | ||
2010 | edev = to_eisa_device (gendev); | |
2011 | iobase = edev->base_addr; | |
2012 | ||
2013 | if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5")) | |
2014 | return -EBUSY; | |
2015 | ||
2016 | if (!request_region (iobase + DE4X5_EISA_IO_PORTS, | |
2017 | DE4X5_EISA_TOTAL_SIZE, "de4x5")) { | |
2018 | status = -EBUSY; | |
2019 | goto release_reg_1; | |
2020 | } | |
f3b197ac | 2021 | |
1da177e4 LT |
2022 | if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) { |
2023 | status = -ENOMEM; | |
2024 | goto release_reg_2; | |
2025 | } | |
2026 | lp = netdev_priv(dev); | |
f3b197ac | 2027 | |
1da177e4 LT |
2028 | cfid = (u32) inl(PCI_CFID); |
2029 | lp->cfrv = (u_short) inl(PCI_CFRV); | |
2030 | device = (cfid >> 8) & 0x00ffff00; | |
2031 | vendor = (u_short) cfid; | |
f3b197ac | 2032 | |
1da177e4 LT |
2033 | /* Read the EISA Configuration Registers */ |
2034 | regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT); | |
2035 | #ifdef CONFIG_ALPHA | |
2036 | /* Looks like the Jensen firmware (rev 2.2) doesn't really | |
2037 | * care about the EISA configuration, and thus doesn't | |
2038 | * configure the PLX bridge properly. Oh well... Simply mimic | |
2039 | * the EISA config file to sort it out. */ | |
f3b197ac | 2040 | |
1da177e4 LT |
2041 | /* EISA REG1: Assert DecChip 21040 HW Reset */ |
2042 | outb (ER1_IAM | 1, EISA_REG1); | |
2043 | mdelay (1); | |
2044 | ||
2045 | /* EISA REG1: Deassert DecChip 21040 HW Reset */ | |
2046 | outb (ER1_IAM, EISA_REG1); | |
2047 | mdelay (1); | |
2048 | ||
2049 | /* EISA REG3: R/W Burst Transfer Enable */ | |
2050 | outb (ER3_BWE | ER3_BRE, EISA_REG3); | |
f3b197ac | 2051 | |
1da177e4 LT |
2052 | /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */ |
2053 | outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0); | |
2054 | #endif | |
2055 | irq = de4x5_irq[(regval >> 1) & 0x03]; | |
f3b197ac | 2056 | |
1da177e4 LT |
2057 | if (is_DC2114x) { |
2058 | device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); | |
2059 | } | |
2060 | lp->chipset = device; | |
2061 | lp->bus = EISA; | |
2062 | ||
2063 | /* Write the PCI Configuration Registers */ | |
2064 | outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS); | |
2065 | outl(0x00006000, PCI_CFLT); | |
2066 | outl(iobase, PCI_CBIO); | |
f3b197ac | 2067 | |
1da177e4 LT |
2068 | DevicePresent(dev, EISA_APROM); |
2069 | ||
2070 | dev->irq = irq; | |
2071 | ||
2072 | if (!(status = de4x5_hw_init (dev, iobase, gendev))) { | |
2073 | return 0; | |
2074 | } | |
2075 | ||
2076 | free_netdev (dev); | |
2077 | release_reg_2: | |
2078 | release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE); | |
2079 | release_reg_1: | |
2080 | release_region (iobase, DE4X5_EISA_TOTAL_SIZE); | |
2081 | ||
2082 | return status; | |
2083 | } | |
2084 | ||
2085 | static int __devexit de4x5_eisa_remove (struct device *device) | |
2086 | { | |
2087 | struct net_device *dev; | |
2088 | u_long iobase; | |
2089 | ||
2090 | dev = device->driver_data; | |
2091 | iobase = dev->base_addr; | |
f3b197ac | 2092 | |
1da177e4 LT |
2093 | unregister_netdev (dev); |
2094 | free_netdev (dev); | |
2095 | release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE); | |
2096 | release_region (iobase, DE4X5_EISA_TOTAL_SIZE); | |
2097 | ||
2098 | return 0; | |
2099 | } | |
2100 | ||
2101 | static struct eisa_device_id de4x5_eisa_ids[] = { | |
2102 | { "DEC4250", 0 }, /* 0 is the board name index... */ | |
2103 | { "" } | |
2104 | }; | |
07563c71 | 2105 | MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids); |
1da177e4 LT |
2106 | |
2107 | static struct eisa_driver de4x5_eisa_driver = { | |
2108 | .id_table = de4x5_eisa_ids, | |
2109 | .driver = { | |
2110 | .name = "de4x5", | |
2111 | .probe = de4x5_eisa_probe, | |
2112 | .remove = __devexit_p (de4x5_eisa_remove), | |
2113 | } | |
2114 | }; | |
2115 | MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids); | |
2116 | #endif | |
2117 | ||
2118 | #ifdef CONFIG_PCI | |
2119 | ||
2120 | /* | |
2121 | ** This function searches the current bus (which is >0) for a DECchip with an | |
f3b197ac | 2122 | ** SROM, so that in multiport cards that have one SROM shared between multiple |
1da177e4 LT |
2123 | ** DECchips, we can find the base SROM irrespective of the BIOS scan direction. |
2124 | ** For single port cards this is a time waster... | |
2125 | */ | |
f3b197ac | 2126 | static void __devinit |
1da177e4 LT |
2127 | srom_search(struct net_device *dev, struct pci_dev *pdev) |
2128 | { | |
2129 | u_char pb; | |
2130 | u_short vendor, status; | |
2131 | u_int irq = 0, device; | |
2132 | u_long iobase = 0; /* Clear upper 32 bits in Alphas */ | |
44c10138 | 2133 | int i, j; |
1da177e4 | 2134 | struct de4x5_private *lp = netdev_priv(dev); |
0c5719c4 | 2135 | struct list_head *walk; |
1da177e4 | 2136 | |
0c5719c4 | 2137 | list_for_each(walk, &pdev->bus_list) { |
1da177e4 LT |
2138 | struct pci_dev *this_dev = pci_dev_b(walk); |
2139 | ||
2140 | /* Skip the pci_bus list entry */ | |
2141 | if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue; | |
2142 | ||
2143 | vendor = this_dev->vendor; | |
2144 | device = this_dev->device << 8; | |
2145 | if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue; | |
2146 | ||
2147 | /* Get the chip configuration revision register */ | |
2148 | pb = this_dev->bus->number; | |
1da177e4 LT |
2149 | |
2150 | /* Set the device number information */ | |
2151 | lp->device = PCI_SLOT(this_dev->devfn); | |
2152 | lp->bus_num = pb; | |
f3b197ac | 2153 | |
1da177e4 LT |
2154 | /* Set the chipset information */ |
2155 | if (is_DC2114x) { | |
44c10138 AK |
2156 | device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK |
2157 | ? DC21142 : DC21143); | |
1da177e4 LT |
2158 | } |
2159 | lp->chipset = device; | |
2160 | ||
2161 | /* Get the board I/O address (64 bits on sparc64) */ | |
2162 | iobase = pci_resource_start(this_dev, 0); | |
2163 | ||
2164 | /* Fetch the IRQ to be used */ | |
2165 | irq = this_dev->irq; | |
2166 | if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue; | |
f3b197ac | 2167 | |
1da177e4 LT |
2168 | /* Check if I/O accesses are enabled */ |
2169 | pci_read_config_word(this_dev, PCI_COMMAND, &status); | |
2170 | if (!(status & PCI_COMMAND_IO)) continue; | |
2171 | ||
2172 | /* Search for a valid SROM attached to this DECchip */ | |
2173 | DevicePresent(dev, DE4X5_APROM); | |
2174 | for (j=0, i=0; i<ETH_ALEN; i++) { | |
2175 | j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i); | |
2176 | } | |
2177 | if ((j != 0) && (j != 0x5fa)) { | |
2178 | last.chipset = device; | |
2179 | last.bus = pb; | |
2180 | last.irq = irq; | |
2181 | for (i=0; i<ETH_ALEN; i++) { | |
2182 | last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i); | |
2183 | } | |
2184 | return; | |
2185 | } | |
2186 | } | |
2187 | ||
2188 | return; | |
2189 | } | |
2190 | ||
2191 | /* | |
2192 | ** PCI bus I/O device probe | |
2193 | ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not | |
2194 | ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be | |
2195 | ** enabled by the user first in the set up utility. Hence we just check for | |
2196 | ** enabled features and silently ignore the card if they're not. | |
2197 | ** | |
2198 | ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering | |
2199 | ** bit. Here, check for I/O accesses and then set BM. If you put the card in | |
2200 | ** a non BM slot, you're on your own (and complain to the PC vendor that your | |
2201 | ** PC doesn't conform to the PCI standard)! | |
2202 | ** | |
2203 | ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x | |
2204 | ** kernels use the V0.535[n] drivers. | |
2205 | */ | |
2206 | ||
2207 | static int __devinit de4x5_pci_probe (struct pci_dev *pdev, | |
2208 | const struct pci_device_id *ent) | |
2209 | { | |
2210 | u_char pb, pbus = 0, dev_num, dnum = 0, timer; | |
2211 | u_short vendor, status; | |
2212 | u_int irq = 0, device; | |
2213 | u_long iobase = 0; /* Clear upper 32 bits in Alphas */ | |
2214 | int error; | |
2215 | struct net_device *dev; | |
2216 | struct de4x5_private *lp; | |
2217 | ||
2218 | dev_num = PCI_SLOT(pdev->devfn); | |
2219 | pb = pdev->bus->number; | |
2220 | ||
2221 | if (io) { /* probe a single PCI device */ | |
2222 | pbus = (u_short)(io >> 8); | |
2223 | dnum = (u_short)(io & 0xff); | |
2224 | if ((pbus != pb) || (dnum != dev_num)) | |
2225 | return -ENODEV; | |
2226 | } | |
2227 | ||
2228 | vendor = pdev->vendor; | |
2229 | device = pdev->device << 8; | |
2230 | if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) | |
2231 | return -ENODEV; | |
2232 | ||
2233 | /* Ok, the device seems to be for us. */ | |
2234 | if ((error = pci_enable_device (pdev))) | |
2235 | return error; | |
2236 | ||
2237 | if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) { | |
2238 | error = -ENOMEM; | |
2239 | goto disable_dev; | |
2240 | } | |
2241 | ||
2242 | lp = netdev_priv(dev); | |
2243 | lp->bus = PCI; | |
2244 | lp->bus_num = 0; | |
f3b197ac | 2245 | |
1da177e4 LT |
2246 | /* Search for an SROM on this bus */ |
2247 | if (lp->bus_num != pb) { | |
2248 | lp->bus_num = pb; | |
2249 | srom_search(dev, pdev); | |
2250 | } | |
2251 | ||
2252 | /* Get the chip configuration revision register */ | |
44c10138 | 2253 | lp->cfrv = pdev->revision; |
1da177e4 LT |
2254 | |
2255 | /* Set the device number information */ | |
2256 | lp->device = dev_num; | |
2257 | lp->bus_num = pb; | |
f3b197ac | 2258 | |
1da177e4 LT |
2259 | /* Set the chipset information */ |
2260 | if (is_DC2114x) { | |
2261 | device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143); | |
2262 | } | |
2263 | lp->chipset = device; | |
2264 | ||
2265 | /* Get the board I/O address (64 bits on sparc64) */ | |
2266 | iobase = pci_resource_start(pdev, 0); | |
2267 | ||
2268 | /* Fetch the IRQ to be used */ | |
2269 | irq = pdev->irq; | |
2270 | if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) { | |
2271 | error = -ENODEV; | |
2272 | goto free_dev; | |
2273 | } | |
f3b197ac | 2274 | |
1da177e4 LT |
2275 | /* Check if I/O accesses and Bus Mastering are enabled */ |
2276 | pci_read_config_word(pdev, PCI_COMMAND, &status); | |
2277 | #ifdef __powerpc__ | |
2278 | if (!(status & PCI_COMMAND_IO)) { | |
2279 | status |= PCI_COMMAND_IO; | |
2280 | pci_write_config_word(pdev, PCI_COMMAND, status); | |
2281 | pci_read_config_word(pdev, PCI_COMMAND, &status); | |
2282 | } | |
2283 | #endif /* __powerpc__ */ | |
2284 | if (!(status & PCI_COMMAND_IO)) { | |
2285 | error = -ENODEV; | |
2286 | goto free_dev; | |
2287 | } | |
2288 | ||
2289 | if (!(status & PCI_COMMAND_MASTER)) { | |
2290 | status |= PCI_COMMAND_MASTER; | |
2291 | pci_write_config_word(pdev, PCI_COMMAND, status); | |
2292 | pci_read_config_word(pdev, PCI_COMMAND, &status); | |
2293 | } | |
2294 | if (!(status & PCI_COMMAND_MASTER)) { | |
2295 | error = -ENODEV; | |
2296 | goto free_dev; | |
2297 | } | |
2298 | ||
2299 | /* Check the latency timer for values >= 0x60 */ | |
2300 | pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer); | |
2301 | if (timer < 0x60) { | |
2302 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60); | |
2303 | } | |
2304 | ||
2305 | DevicePresent(dev, DE4X5_APROM); | |
2306 | ||
2307 | if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) { | |
2308 | error = -EBUSY; | |
2309 | goto free_dev; | |
2310 | } | |
2311 | ||
2312 | dev->irq = irq; | |
f3b197ac | 2313 | |
1da177e4 LT |
2314 | if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) { |
2315 | goto release; | |
2316 | } | |
2317 | ||
2318 | return 0; | |
2319 | ||
2320 | release: | |
2321 | release_region (iobase, DE4X5_PCI_TOTAL_SIZE); | |
2322 | free_dev: | |
2323 | free_netdev (dev); | |
2324 | disable_dev: | |
2325 | pci_disable_device (pdev); | |
2326 | return error; | |
2327 | } | |
2328 | ||
2329 | static void __devexit de4x5_pci_remove (struct pci_dev *pdev) | |
2330 | { | |
2331 | struct net_device *dev; | |
2332 | u_long iobase; | |
2333 | ||
2334 | dev = pdev->dev.driver_data; | |
2335 | iobase = dev->base_addr; | |
2336 | ||
2337 | unregister_netdev (dev); | |
2338 | free_netdev (dev); | |
2339 | release_region (iobase, DE4X5_PCI_TOTAL_SIZE); | |
2340 | pci_disable_device (pdev); | |
2341 | } | |
2342 | ||
2343 | static struct pci_device_id de4x5_pci_tbl[] = { | |
2344 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP, | |
2345 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, | |
2346 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS, | |
2347 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, | |
2348 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST, | |
2349 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 }, | |
2350 | { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, | |
2351 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 }, | |
2352 | { }, | |
2353 | }; | |
2354 | ||
2355 | static struct pci_driver de4x5_pci_driver = { | |
2356 | .name = "de4x5", | |
2357 | .id_table = de4x5_pci_tbl, | |
2358 | .probe = de4x5_pci_probe, | |
2359 | .remove = __devexit_p (de4x5_pci_remove), | |
2360 | }; | |
2361 | ||
2362 | #endif | |
2363 | ||
2364 | /* | |
2365 | ** Auto configure the media here rather than setting the port at compile | |
2366 | ** time. This routine is called by de4x5_init() and when a loss of media is | |
2367 | ** detected (excessive collisions, loss of carrier, no carrier or link fail | |
f3b197ac | 2368 | ** [TP] or no recent receive activity) to check whether the user has been |
1da177e4 LT |
2369 | ** sneaky and changed the port on us. |
2370 | */ | |
2371 | static int | |
2372 | autoconf_media(struct net_device *dev) | |
2373 | { | |
2374 | struct de4x5_private *lp = netdev_priv(dev); | |
2375 | u_long iobase = dev->base_addr; | |
2376 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2377 | ||
2378 | lp->linkOK = 0; | |
2379 | lp->c_media = AUTO; /* Bogus last media */ | |
2380 | disable_ast(dev); | |
2381 | inl(DE4X5_MFC); /* Zero the lost frames counter */ | |
2382 | lp->media = INIT; | |
2383 | lp->tcount = 0; | |
2384 | ||
2385 | if (lp->useSROM) { | |
2386 | next_tick = srom_autoconf(dev); | |
2387 | } else if (lp->chipset == DC21040) { | |
2388 | next_tick = dc21040_autoconf(dev); | |
2389 | } else if (lp->chipset == DC21041) { | |
2390 | next_tick = dc21041_autoconf(dev); | |
2391 | } else if (lp->chipset == DC21140) { | |
2392 | next_tick = dc21140m_autoconf(dev); | |
2393 | } | |
2394 | ||
2395 | enable_ast(dev, next_tick); | |
f3b197ac | 2396 | |
1da177e4 LT |
2397 | return (lp->media); |
2398 | } | |
2399 | ||
2400 | /* | |
2401 | ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished | |
2402 | ** from BNC as the port has a jumper to set thick or thin wire. When set for | |
2403 | ** BNC, the BNC port will indicate activity if it's not terminated correctly. | |
2404 | ** The only way to test for that is to place a loopback packet onto the | |
2405 | ** network and watch for errors. Since we're messing with the interrupt mask | |
2406 | ** register, disable the board interrupts and do not allow any more packets to | |
2407 | ** be queued to the hardware. Re-enable everything only when the media is | |
2408 | ** found. | |
2409 | ** I may have to "age out" locally queued packets so that the higher layer | |
2410 | ** timeouts don't effectively duplicate packets on the network. | |
2411 | */ | |
2412 | static int | |
2413 | dc21040_autoconf(struct net_device *dev) | |
2414 | { | |
2415 | struct de4x5_private *lp = netdev_priv(dev); | |
2416 | u_long iobase = dev->base_addr; | |
2417 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2418 | s32 imr; | |
f3b197ac | 2419 | |
1da177e4 LT |
2420 | switch (lp->media) { |
2421 | case INIT: | |
2422 | DISABLE_IRQs; | |
eb034a79 | 2423 | lp->tx_enable = false; |
1da177e4 LT |
2424 | lp->timeout = -1; |
2425 | de4x5_save_skbs(dev); | |
2426 | if ((lp->autosense == AUTO) || (lp->autosense == TP)) { | |
2427 | lp->media = TP; | |
2428 | } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) { | |
2429 | lp->media = BNC_AUI; | |
2430 | } else if (lp->autosense == EXT_SIA) { | |
2431 | lp->media = EXT_SIA; | |
2432 | } else { | |
2433 | lp->media = NC; | |
2434 | } | |
2435 | lp->local_state = 0; | |
2436 | next_tick = dc21040_autoconf(dev); | |
2437 | break; | |
f3b197ac | 2438 | |
1da177e4 | 2439 | case TP: |
f3b197ac | 2440 | next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI, |
1da177e4 LT |
2441 | TP_SUSPECT, test_tp); |
2442 | break; | |
f3b197ac | 2443 | |
1da177e4 LT |
2444 | case TP_SUSPECT: |
2445 | next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf); | |
2446 | break; | |
f3b197ac | 2447 | |
1da177e4 LT |
2448 | case BNC: |
2449 | case AUI: | |
2450 | case BNC_AUI: | |
f3b197ac | 2451 | next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA, |
1da177e4 LT |
2452 | BNC_AUI_SUSPECT, ping_media); |
2453 | break; | |
f3b197ac | 2454 | |
1da177e4 LT |
2455 | case BNC_AUI_SUSPECT: |
2456 | next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf); | |
2457 | break; | |
f3b197ac | 2458 | |
1da177e4 | 2459 | case EXT_SIA: |
f3b197ac | 2460 | next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000, |
1da177e4 LT |
2461 | NC, EXT_SIA_SUSPECT, ping_media); |
2462 | break; | |
f3b197ac | 2463 | |
1da177e4 LT |
2464 | case EXT_SIA_SUSPECT: |
2465 | next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf); | |
2466 | break; | |
f3b197ac | 2467 | |
1da177e4 LT |
2468 | case NC: |
2469 | /* default to TP for all */ | |
2470 | reset_init_sia(dev, 0x8f01, 0xffff, 0x0000); | |
2471 | if (lp->media != lp->c_media) { | |
2472 | de4x5_dbg_media(dev); | |
2473 | lp->c_media = lp->media; | |
2474 | } | |
2475 | lp->media = INIT; | |
eb034a79 | 2476 | lp->tx_enable = false; |
1da177e4 LT |
2477 | break; |
2478 | } | |
f3b197ac | 2479 | |
1da177e4 LT |
2480 | return next_tick; |
2481 | } | |
2482 | ||
2483 | static int | |
2484 | dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, | |
f3b197ac | 2485 | int next_state, int suspect_state, |
1da177e4 LT |
2486 | int (*fn)(struct net_device *, int)) |
2487 | { | |
2488 | struct de4x5_private *lp = netdev_priv(dev); | |
2489 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2490 | int linkBad; | |
2491 | ||
2492 | switch (lp->local_state) { | |
2493 | case 0: | |
2494 | reset_init_sia(dev, csr13, csr14, csr15); | |
2495 | lp->local_state++; | |
2496 | next_tick = 500; | |
2497 | break; | |
f3b197ac | 2498 | |
1da177e4 LT |
2499 | case 1: |
2500 | if (!lp->tx_enable) { | |
2501 | linkBad = fn(dev, timeout); | |
2502 | if (linkBad < 0) { | |
2503 | next_tick = linkBad & ~TIMER_CB; | |
2504 | } else { | |
2505 | if (linkBad && (lp->autosense == AUTO)) { | |
2506 | lp->local_state = 0; | |
2507 | lp->media = next_state; | |
2508 | } else { | |
2509 | de4x5_init_connection(dev); | |
2510 | } | |
2511 | } | |
2512 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2513 | lp->media = suspect_state; | |
2514 | next_tick = 3000; | |
2515 | } | |
2516 | break; | |
2517 | } | |
f3b197ac | 2518 | |
1da177e4 LT |
2519 | return next_tick; |
2520 | } | |
2521 | ||
2522 | static int | |
2523 | de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, | |
2524 | int (*fn)(struct net_device *, int), | |
2525 | int (*asfn)(struct net_device *)) | |
2526 | { | |
2527 | struct de4x5_private *lp = netdev_priv(dev); | |
2528 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2529 | int linkBad; | |
2530 | ||
2531 | switch (lp->local_state) { | |
2532 | case 1: | |
2533 | if (lp->linkOK) { | |
2534 | lp->media = prev_state; | |
2535 | } else { | |
2536 | lp->local_state++; | |
2537 | next_tick = asfn(dev); | |
2538 | } | |
2539 | break; | |
2540 | ||
2541 | case 2: | |
2542 | linkBad = fn(dev, timeout); | |
2543 | if (linkBad < 0) { | |
2544 | next_tick = linkBad & ~TIMER_CB; | |
2545 | } else if (!linkBad) { | |
2546 | lp->local_state--; | |
2547 | lp->media = prev_state; | |
2548 | } else { | |
2549 | lp->media = INIT; | |
2550 | lp->tcount++; | |
2551 | } | |
2552 | } | |
2553 | ||
2554 | return next_tick; | |
2555 | } | |
2556 | ||
2557 | /* | |
2558 | ** Autoconfigure the media when using the DC21041. AUI needs to be tested | |
2559 | ** before BNC, because the BNC port will indicate activity if it's not | |
2560 | ** terminated correctly. The only way to test for that is to place a loopback | |
2561 | ** packet onto the network and watch for errors. Since we're messing with | |
2562 | ** the interrupt mask register, disable the board interrupts and do not allow | |
2563 | ** any more packets to be queued to the hardware. Re-enable everything only | |
2564 | ** when the media is found. | |
2565 | */ | |
2566 | static int | |
2567 | dc21041_autoconf(struct net_device *dev) | |
2568 | { | |
2569 | struct de4x5_private *lp = netdev_priv(dev); | |
2570 | u_long iobase = dev->base_addr; | |
2571 | s32 sts, irqs, irq_mask, imr, omr; | |
2572 | int next_tick = DE4X5_AUTOSENSE_MS; | |
f3b197ac | 2573 | |
1da177e4 LT |
2574 | switch (lp->media) { |
2575 | case INIT: | |
2576 | DISABLE_IRQs; | |
eb034a79 | 2577 | lp->tx_enable = false; |
1da177e4 LT |
2578 | lp->timeout = -1; |
2579 | de4x5_save_skbs(dev); /* Save non transmitted skb's */ | |
2580 | if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) { | |
2581 | lp->media = TP; /* On chip auto negotiation is broken */ | |
2582 | } else if (lp->autosense == TP) { | |
2583 | lp->media = TP; | |
2584 | } else if (lp->autosense == BNC) { | |
2585 | lp->media = BNC; | |
2586 | } else if (lp->autosense == AUI) { | |
2587 | lp->media = AUI; | |
2588 | } else { | |
2589 | lp->media = NC; | |
2590 | } | |
2591 | lp->local_state = 0; | |
2592 | next_tick = dc21041_autoconf(dev); | |
2593 | break; | |
f3b197ac | 2594 | |
1da177e4 LT |
2595 | case TP_NW: |
2596 | if (lp->timeout < 0) { | |
2597 | omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */ | |
2598 | outl(omr | OMR_FDX, DE4X5_OMR); | |
2599 | } | |
2600 | irqs = STS_LNF | STS_LNP; | |
2601 | irq_mask = IMR_LFM | IMR_LPM; | |
2602 | sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400); | |
2603 | if (sts < 0) { | |
2604 | next_tick = sts & ~TIMER_CB; | |
2605 | } else { | |
2606 | if (sts & STS_LNP) { | |
2607 | lp->media = ANS; | |
2608 | } else { | |
2609 | lp->media = AUI; | |
2610 | } | |
2611 | next_tick = dc21041_autoconf(dev); | |
2612 | } | |
2613 | break; | |
f3b197ac | 2614 | |
1da177e4 LT |
2615 | case ANS: |
2616 | if (!lp->tx_enable) { | |
2617 | irqs = STS_LNP; | |
2618 | irq_mask = IMR_LPM; | |
2619 | sts = test_ans(dev, irqs, irq_mask, 3000); | |
2620 | if (sts < 0) { | |
2621 | next_tick = sts & ~TIMER_CB; | |
2622 | } else { | |
2623 | if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { | |
2624 | lp->media = TP; | |
2625 | next_tick = dc21041_autoconf(dev); | |
2626 | } else { | |
2627 | lp->local_state = 1; | |
2628 | de4x5_init_connection(dev); | |
2629 | } | |
2630 | } | |
2631 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2632 | lp->media = ANS_SUSPECT; | |
2633 | next_tick = 3000; | |
2634 | } | |
2635 | break; | |
f3b197ac | 2636 | |
1da177e4 LT |
2637 | case ANS_SUSPECT: |
2638 | next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf); | |
2639 | break; | |
f3b197ac | 2640 | |
1da177e4 LT |
2641 | case TP: |
2642 | if (!lp->tx_enable) { | |
2643 | if (lp->timeout < 0) { | |
2644 | omr = inl(DE4X5_OMR); /* Set up half duplex for TP */ | |
2645 | outl(omr & ~OMR_FDX, DE4X5_OMR); | |
2646 | } | |
2647 | irqs = STS_LNF | STS_LNP; | |
2648 | irq_mask = IMR_LFM | IMR_LPM; | |
2649 | sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400); | |
2650 | if (sts < 0) { | |
2651 | next_tick = sts & ~TIMER_CB; | |
2652 | } else { | |
2653 | if (!(sts & STS_LNP) && (lp->autosense == AUTO)) { | |
2654 | if (inl(DE4X5_SISR) & SISR_NRA) { | |
2655 | lp->media = AUI; /* Non selected port activity */ | |
2656 | } else { | |
2657 | lp->media = BNC; | |
2658 | } | |
2659 | next_tick = dc21041_autoconf(dev); | |
2660 | } else { | |
2661 | lp->local_state = 1; | |
2662 | de4x5_init_connection(dev); | |
2663 | } | |
2664 | } | |
2665 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2666 | lp->media = TP_SUSPECT; | |
2667 | next_tick = 3000; | |
2668 | } | |
2669 | break; | |
f3b197ac | 2670 | |
1da177e4 LT |
2671 | case TP_SUSPECT: |
2672 | next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf); | |
2673 | break; | |
f3b197ac | 2674 | |
1da177e4 LT |
2675 | case AUI: |
2676 | if (!lp->tx_enable) { | |
2677 | if (lp->timeout < 0) { | |
2678 | omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */ | |
2679 | outl(omr & ~OMR_FDX, DE4X5_OMR); | |
2680 | } | |
2681 | irqs = 0; | |
2682 | irq_mask = 0; | |
2683 | sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000); | |
2684 | if (sts < 0) { | |
2685 | next_tick = sts & ~TIMER_CB; | |
2686 | } else { | |
2687 | if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { | |
2688 | lp->media = BNC; | |
2689 | next_tick = dc21041_autoconf(dev); | |
2690 | } else { | |
2691 | lp->local_state = 1; | |
2692 | de4x5_init_connection(dev); | |
2693 | } | |
2694 | } | |
2695 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2696 | lp->media = AUI_SUSPECT; | |
2697 | next_tick = 3000; | |
2698 | } | |
2699 | break; | |
f3b197ac | 2700 | |
1da177e4 LT |
2701 | case AUI_SUSPECT: |
2702 | next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf); | |
2703 | break; | |
f3b197ac | 2704 | |
1da177e4 LT |
2705 | case BNC: |
2706 | switch (lp->local_state) { | |
2707 | case 0: | |
2708 | if (lp->timeout < 0) { | |
2709 | omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */ | |
2710 | outl(omr & ~OMR_FDX, DE4X5_OMR); | |
2711 | } | |
2712 | irqs = 0; | |
2713 | irq_mask = 0; | |
2714 | sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000); | |
2715 | if (sts < 0) { | |
2716 | next_tick = sts & ~TIMER_CB; | |
2717 | } else { | |
2718 | lp->local_state++; /* Ensure media connected */ | |
2719 | next_tick = dc21041_autoconf(dev); | |
2720 | } | |
2721 | break; | |
f3b197ac | 2722 | |
1da177e4 LT |
2723 | case 1: |
2724 | if (!lp->tx_enable) { | |
2725 | if ((sts = ping_media(dev, 3000)) < 0) { | |
2726 | next_tick = sts & ~TIMER_CB; | |
2727 | } else { | |
2728 | if (sts) { | |
2729 | lp->local_state = 0; | |
2730 | lp->media = NC; | |
2731 | } else { | |
2732 | de4x5_init_connection(dev); | |
2733 | } | |
2734 | } | |
2735 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2736 | lp->media = BNC_SUSPECT; | |
2737 | next_tick = 3000; | |
2738 | } | |
2739 | break; | |
2740 | } | |
2741 | break; | |
f3b197ac | 2742 | |
1da177e4 LT |
2743 | case BNC_SUSPECT: |
2744 | next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf); | |
2745 | break; | |
f3b197ac | 2746 | |
1da177e4 LT |
2747 | case NC: |
2748 | omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */ | |
2749 | outl(omr | OMR_FDX, DE4X5_OMR); | |
2750 | reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */ | |
2751 | if (lp->media != lp->c_media) { | |
2752 | de4x5_dbg_media(dev); | |
2753 | lp->c_media = lp->media; | |
2754 | } | |
2755 | lp->media = INIT; | |
eb034a79 | 2756 | lp->tx_enable = false; |
1da177e4 LT |
2757 | break; |
2758 | } | |
f3b197ac | 2759 | |
1da177e4 LT |
2760 | return next_tick; |
2761 | } | |
2762 | ||
2763 | /* | |
2764 | ** Some autonegotiation chips are broken in that they do not return the | |
2765 | ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement | |
2766 | ** register, except at the first power up negotiation. | |
2767 | */ | |
2768 | static int | |
2769 | dc21140m_autoconf(struct net_device *dev) | |
2770 | { | |
2771 | struct de4x5_private *lp = netdev_priv(dev); | |
2772 | int ana, anlpa, cap, cr, slnk, sr; | |
2773 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2774 | u_long imr, omr, iobase = dev->base_addr; | |
f3b197ac | 2775 | |
1da177e4 | 2776 | switch(lp->media) { |
f3b197ac | 2777 | case INIT: |
1da177e4 LT |
2778 | if (lp->timeout < 0) { |
2779 | DISABLE_IRQs; | |
eb034a79 | 2780 | lp->tx_enable = false; |
1da177e4 LT |
2781 | lp->linkOK = 0; |
2782 | de4x5_save_skbs(dev); /* Save non transmitted skb's */ | |
2783 | } | |
2784 | if ((next_tick = de4x5_reset_phy(dev)) < 0) { | |
2785 | next_tick &= ~TIMER_CB; | |
2786 | } else { | |
2787 | if (lp->useSROM) { | |
2788 | if (srom_map_media(dev) < 0) { | |
2789 | lp->tcount++; | |
2790 | return next_tick; | |
2791 | } | |
2792 | srom_exec(dev, lp->phy[lp->active].gep); | |
2793 | if (lp->infoblock_media == ANS) { | |
2794 | ana = lp->phy[lp->active].ana | MII_ANA_CSMA; | |
2795 | mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); | |
2796 | } | |
2797 | } else { | |
2798 | lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */ | |
2799 | SET_10Mb; | |
2800 | if (lp->autosense == _100Mb) { | |
2801 | lp->media = _100Mb; | |
2802 | } else if (lp->autosense == _10Mb) { | |
2803 | lp->media = _10Mb; | |
f3b197ac | 2804 | } else if ((lp->autosense == AUTO) && |
1da177e4 LT |
2805 | ((sr=is_anc_capable(dev)) & MII_SR_ANC)) { |
2806 | ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA); | |
2807 | ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); | |
2808 | mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); | |
2809 | lp->media = ANS; | |
2810 | } else if (lp->autosense == AUTO) { | |
2811 | lp->media = SPD_DET; | |
2812 | } else if (is_spd_100(dev) && is_100_up(dev)) { | |
2813 | lp->media = _100Mb; | |
2814 | } else { | |
2815 | lp->media = NC; | |
2816 | } | |
2817 | } | |
2818 | lp->local_state = 0; | |
2819 | next_tick = dc21140m_autoconf(dev); | |
2820 | } | |
2821 | break; | |
f3b197ac | 2822 | |
1da177e4 LT |
2823 | case ANS: |
2824 | switch (lp->local_state) { | |
2825 | case 0: | |
2826 | if (lp->timeout < 0) { | |
2827 | mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); | |
2828 | } | |
eb034a79 | 2829 | cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500); |
1da177e4 LT |
2830 | if (cr < 0) { |
2831 | next_tick = cr & ~TIMER_CB; | |
2832 | } else { | |
2833 | if (cr) { | |
2834 | lp->local_state = 0; | |
2835 | lp->media = SPD_DET; | |
2836 | } else { | |
2837 | lp->local_state++; | |
2838 | } | |
2839 | next_tick = dc21140m_autoconf(dev); | |
2840 | } | |
2841 | break; | |
f3b197ac | 2842 | |
1da177e4 | 2843 | case 1: |
eb034a79 | 2844 | if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) { |
1da177e4 LT |
2845 | next_tick = sr & ~TIMER_CB; |
2846 | } else { | |
2847 | lp->media = SPD_DET; | |
2848 | lp->local_state = 0; | |
2849 | if (sr) { /* Success! */ | |
2850 | lp->tmp = MII_SR_ASSC; | |
2851 | anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); | |
2852 | ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); | |
f3b197ac | 2853 | if (!(anlpa & MII_ANLPA_RF) && |
1da177e4 LT |
2854 | (cap = anlpa & MII_ANLPA_TAF & ana)) { |
2855 | if (cap & MII_ANA_100M) { | |
eb034a79 | 2856 | lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; |
1da177e4 LT |
2857 | lp->media = _100Mb; |
2858 | } else if (cap & MII_ANA_10M) { | |
eb034a79 | 2859 | lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; |
1da177e4 LT |
2860 | |
2861 | lp->media = _10Mb; | |
2862 | } | |
2863 | } | |
2864 | } /* Auto Negotiation failed to finish */ | |
2865 | next_tick = dc21140m_autoconf(dev); | |
2866 | } /* Auto Negotiation failed to start */ | |
2867 | break; | |
2868 | } | |
2869 | break; | |
f3b197ac | 2870 | |
1da177e4 LT |
2871 | case SPD_DET: /* Choose 10Mb/s or 100Mb/s */ |
2872 | if (lp->timeout < 0) { | |
f3b197ac | 2873 | lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS : |
1da177e4 LT |
2874 | (~gep_rd(dev) & GEP_LNP)); |
2875 | SET_100Mb_PDET; | |
2876 | } | |
2877 | if ((slnk = test_for_100Mb(dev, 6500)) < 0) { | |
2878 | next_tick = slnk & ~TIMER_CB; | |
2879 | } else { | |
2880 | if (is_spd_100(dev) && is_100_up(dev)) { | |
2881 | lp->media = _100Mb; | |
2882 | } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) { | |
2883 | lp->media = _10Mb; | |
2884 | } else { | |
2885 | lp->media = NC; | |
2886 | } | |
2887 | next_tick = dc21140m_autoconf(dev); | |
2888 | } | |
2889 | break; | |
f3b197ac | 2890 | |
1da177e4 LT |
2891 | case _100Mb: /* Set 100Mb/s */ |
2892 | next_tick = 3000; | |
2893 | if (!lp->tx_enable) { | |
2894 | SET_100Mb; | |
2895 | de4x5_init_connection(dev); | |
2896 | } else { | |
2897 | if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2898 | if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { | |
2899 | lp->media = INIT; | |
2900 | lp->tcount++; | |
2901 | next_tick = DE4X5_AUTOSENSE_MS; | |
2902 | } | |
2903 | } | |
2904 | } | |
2905 | break; | |
2906 | ||
2907 | case BNC: | |
2908 | case AUI: | |
2909 | case _10Mb: /* Set 10Mb/s */ | |
2910 | next_tick = 3000; | |
2911 | if (!lp->tx_enable) { | |
2912 | SET_10Mb; | |
2913 | de4x5_init_connection(dev); | |
2914 | } else { | |
2915 | if (!lp->linkOK && (lp->autosense == AUTO)) { | |
2916 | if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { | |
2917 | lp->media = INIT; | |
2918 | lp->tcount++; | |
2919 | next_tick = DE4X5_AUTOSENSE_MS; | |
2920 | } | |
2921 | } | |
2922 | } | |
2923 | break; | |
f3b197ac | 2924 | |
1da177e4 LT |
2925 | case NC: |
2926 | if (lp->media != lp->c_media) { | |
2927 | de4x5_dbg_media(dev); | |
2928 | lp->c_media = lp->media; | |
2929 | } | |
2930 | lp->media = INIT; | |
eb034a79 | 2931 | lp->tx_enable = false; |
1da177e4 LT |
2932 | break; |
2933 | } | |
f3b197ac | 2934 | |
1da177e4 LT |
2935 | return next_tick; |
2936 | } | |
2937 | ||
2938 | /* | |
2939 | ** This routine may be merged into dc21140m_autoconf() sometime as I'm | |
2940 | ** changing how I figure out the media - but trying to keep it backwards | |
2941 | ** compatible with the de500-xa and de500-aa. | |
2942 | ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock | |
2943 | ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy(). | |
2944 | ** This routine just has to figure out whether 10Mb/s or 100Mb/s is | |
2945 | ** active. | |
2946 | ** When autonegotiation is working, the ANS part searches the SROM for | |
2947 | ** the highest common speed (TP) link that both can run and if that can | |
2948 | ** be full duplex. That infoblock is executed and then the link speed set. | |
2949 | ** | |
2950 | ** Only _10Mb and _100Mb are tested here. | |
2951 | */ | |
2952 | static int | |
2953 | dc2114x_autoconf(struct net_device *dev) | |
2954 | { | |
2955 | struct de4x5_private *lp = netdev_priv(dev); | |
2956 | u_long iobase = dev->base_addr; | |
2957 | s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts; | |
2958 | int next_tick = DE4X5_AUTOSENSE_MS; | |
2959 | ||
2960 | switch (lp->media) { | |
2961 | case INIT: | |
2962 | if (lp->timeout < 0) { | |
2963 | DISABLE_IRQs; | |
eb034a79 | 2964 | lp->tx_enable = false; |
1da177e4 LT |
2965 | lp->linkOK = 0; |
2966 | lp->timeout = -1; | |
2967 | de4x5_save_skbs(dev); /* Save non transmitted skb's */ | |
2968 | if (lp->params.autosense & ~AUTO) { | |
2969 | srom_map_media(dev); /* Fixed media requested */ | |
2970 | if (lp->media != lp->params.autosense) { | |
2971 | lp->tcount++; | |
2972 | lp->media = INIT; | |
2973 | return next_tick; | |
2974 | } | |
2975 | lp->media = INIT; | |
2976 | } | |
2977 | } | |
2978 | if ((next_tick = de4x5_reset_phy(dev)) < 0) { | |
2979 | next_tick &= ~TIMER_CB; | |
2980 | } else { | |
2981 | if (lp->autosense == _100Mb) { | |
2982 | lp->media = _100Mb; | |
2983 | } else if (lp->autosense == _10Mb) { | |
2984 | lp->media = _10Mb; | |
2985 | } else if (lp->autosense == TP) { | |
2986 | lp->media = TP; | |
2987 | } else if (lp->autosense == BNC) { | |
2988 | lp->media = BNC; | |
2989 | } else if (lp->autosense == AUI) { | |
2990 | lp->media = AUI; | |
2991 | } else { | |
2992 | lp->media = SPD_DET; | |
f3b197ac | 2993 | if ((lp->infoblock_media == ANS) && |
1da177e4 LT |
2994 | ((sr=is_anc_capable(dev)) & MII_SR_ANC)) { |
2995 | ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA); | |
2996 | ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM); | |
2997 | mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); | |
2998 | lp->media = ANS; | |
2999 | } | |
3000 | } | |
3001 | lp->local_state = 0; | |
3002 | next_tick = dc2114x_autoconf(dev); | |
3003 | } | |
3004 | break; | |
f3b197ac | 3005 | |
1da177e4 LT |
3006 | case ANS: |
3007 | switch (lp->local_state) { | |
3008 | case 0: | |
3009 | if (lp->timeout < 0) { | |
3010 | mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); | |
3011 | } | |
eb034a79 | 3012 | cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500); |
1da177e4 LT |
3013 | if (cr < 0) { |
3014 | next_tick = cr & ~TIMER_CB; | |
3015 | } else { | |
3016 | if (cr) { | |
3017 | lp->local_state = 0; | |
3018 | lp->media = SPD_DET; | |
3019 | } else { | |
3020 | lp->local_state++; | |
3021 | } | |
3022 | next_tick = dc2114x_autoconf(dev); | |
3023 | } | |
3024 | break; | |
f3b197ac | 3025 | |
1da177e4 | 3026 | case 1: |
eb034a79 RK |
3027 | sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000); |
3028 | if (sr < 0) { | |
1da177e4 LT |
3029 | next_tick = sr & ~TIMER_CB; |
3030 | } else { | |
3031 | lp->media = SPD_DET; | |
3032 | lp->local_state = 0; | |
3033 | if (sr) { /* Success! */ | |
3034 | lp->tmp = MII_SR_ASSC; | |
3035 | anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII); | |
3036 | ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII); | |
f3b197ac | 3037 | if (!(anlpa & MII_ANLPA_RF) && |
1da177e4 LT |
3038 | (cap = anlpa & MII_ANLPA_TAF & ana)) { |
3039 | if (cap & MII_ANA_100M) { | |
eb034a79 | 3040 | lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0; |
1da177e4 LT |
3041 | lp->media = _100Mb; |
3042 | } else if (cap & MII_ANA_10M) { | |
eb034a79 | 3043 | lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0; |
1da177e4 LT |
3044 | lp->media = _10Mb; |
3045 | } | |
3046 | } | |
3047 | } /* Auto Negotiation failed to finish */ | |
3048 | next_tick = dc2114x_autoconf(dev); | |
3049 | } /* Auto Negotiation failed to start */ | |
3050 | break; | |
3051 | } | |
3052 | break; | |
3053 | ||
3054 | case AUI: | |
3055 | if (!lp->tx_enable) { | |
3056 | if (lp->timeout < 0) { | |
3057 | omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */ | |
3058 | outl(omr & ~OMR_FDX, DE4X5_OMR); | |
3059 | } | |
3060 | irqs = 0; | |
3061 | irq_mask = 0; | |
3062 | sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000); | |
3063 | if (sts < 0) { | |
3064 | next_tick = sts & ~TIMER_CB; | |
3065 | } else { | |
3066 | if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) { | |
3067 | lp->media = BNC; | |
3068 | next_tick = dc2114x_autoconf(dev); | |
3069 | } else { | |
3070 | lp->local_state = 1; | |
3071 | de4x5_init_connection(dev); | |
3072 | } | |
3073 | } | |
3074 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
3075 | lp->media = AUI_SUSPECT; | |
3076 | next_tick = 3000; | |
3077 | } | |
3078 | break; | |
f3b197ac | 3079 | |
1da177e4 LT |
3080 | case AUI_SUSPECT: |
3081 | next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf); | |
3082 | break; | |
f3b197ac | 3083 | |
1da177e4 LT |
3084 | case BNC: |
3085 | switch (lp->local_state) { | |
3086 | case 0: | |
3087 | if (lp->timeout < 0) { | |
3088 | omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */ | |
3089 | outl(omr & ~OMR_FDX, DE4X5_OMR); | |
3090 | } | |
3091 | irqs = 0; | |
3092 | irq_mask = 0; | |
3093 | sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000); | |
3094 | if (sts < 0) { | |
3095 | next_tick = sts & ~TIMER_CB; | |
3096 | } else { | |
3097 | lp->local_state++; /* Ensure media connected */ | |
3098 | next_tick = dc2114x_autoconf(dev); | |
3099 | } | |
3100 | break; | |
f3b197ac | 3101 | |
1da177e4 LT |
3102 | case 1: |
3103 | if (!lp->tx_enable) { | |
3104 | if ((sts = ping_media(dev, 3000)) < 0) { | |
3105 | next_tick = sts & ~TIMER_CB; | |
3106 | } else { | |
3107 | if (sts) { | |
3108 | lp->local_state = 0; | |
3109 | lp->tcount++; | |
3110 | lp->media = INIT; | |
3111 | } else { | |
3112 | de4x5_init_connection(dev); | |
3113 | } | |
3114 | } | |
3115 | } else if (!lp->linkOK && (lp->autosense == AUTO)) { | |
3116 | lp->media = BNC_SUSPECT; | |
3117 | next_tick = 3000; | |
3118 | } | |
3119 | break; | |
3120 | } | |
3121 | break; | |
f3b197ac | 3122 | |
1da177e4 LT |
3123 | case BNC_SUSPECT: |
3124 | next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf); | |
3125 | break; | |
f3b197ac | 3126 | |
1da177e4 LT |
3127 | case SPD_DET: /* Choose 10Mb/s or 100Mb/s */ |
3128 | if (srom_map_media(dev) < 0) { | |
3129 | lp->tcount++; | |
3130 | lp->media = INIT; | |
3131 | return next_tick; | |
3132 | } | |
3133 | if (lp->media == _100Mb) { | |
3134 | if ((slnk = test_for_100Mb(dev, 6500)) < 0) { | |
3135 | lp->media = SPD_DET; | |
3136 | return (slnk & ~TIMER_CB); | |
3137 | } | |
3138 | } else { | |
3139 | if (wait_for_link(dev) < 0) { | |
3140 | lp->media = SPD_DET; | |
3141 | return PDET_LINK_WAIT; | |
3142 | } | |
3143 | } | |
3144 | if (lp->media == ANS) { /* Do MII parallel detection */ | |
3145 | if (is_spd_100(dev)) { | |
3146 | lp->media = _100Mb; | |
3147 | } else { | |
3148 | lp->media = _10Mb; | |
3149 | } | |
3150 | next_tick = dc2114x_autoconf(dev); | |
3151 | } else if (((lp->media == _100Mb) && is_100_up(dev)) || | |
3152 | (((lp->media == _10Mb) || (lp->media == TP) || | |
f3b197ac | 3153 | (lp->media == BNC) || (lp->media == AUI)) && |
1da177e4 LT |
3154 | is_10_up(dev))) { |
3155 | next_tick = dc2114x_autoconf(dev); | |
3156 | } else { | |
3157 | lp->tcount++; | |
3158 | lp->media = INIT; | |
3159 | } | |
3160 | break; | |
f3b197ac | 3161 | |
1da177e4 LT |
3162 | case _10Mb: |
3163 | next_tick = 3000; | |
3164 | if (!lp->tx_enable) { | |
3165 | SET_10Mb; | |
3166 | de4x5_init_connection(dev); | |
3167 | } else { | |
3168 | if (!lp->linkOK && (lp->autosense == AUTO)) { | |
3169 | if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) { | |
3170 | lp->media = INIT; | |
3171 | lp->tcount++; | |
3172 | next_tick = DE4X5_AUTOSENSE_MS; | |
3173 | } | |
3174 | } | |
3175 | } | |
3176 | break; | |
3177 | ||
3178 | case _100Mb: | |
3179 | next_tick = 3000; | |
3180 | if (!lp->tx_enable) { | |
3181 | SET_100Mb; | |
3182 | de4x5_init_connection(dev); | |
3183 | } else { | |
3184 | if (!lp->linkOK && (lp->autosense == AUTO)) { | |
3185 | if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) { | |
3186 | lp->media = INIT; | |
3187 | lp->tcount++; | |
3188 | next_tick = DE4X5_AUTOSENSE_MS; | |
3189 | } | |
3190 | } | |
3191 | } | |
3192 | break; | |
3193 | ||
3194 | default: | |
3195 | lp->tcount++; | |
3196 | printk("Huh?: media:%02x\n", lp->media); | |
3197 | lp->media = INIT; | |
3198 | break; | |
3199 | } | |
f3b197ac | 3200 | |
1da177e4 LT |
3201 | return next_tick; |
3202 | } | |
3203 | ||
3204 | static int | |
3205 | srom_autoconf(struct net_device *dev) | |
3206 | { | |
3207 | struct de4x5_private *lp = netdev_priv(dev); | |
3208 | ||
3209 | return lp->infoleaf_fn(dev); | |
3210 | } | |
3211 | ||
3212 | /* | |
3213 | ** This mapping keeps the original media codes and FDX flag unchanged. | |
3214 | ** While it isn't strictly necessary, it helps me for the moment... | |
3215 | ** The early return avoids a media state / SROM media space clash. | |
3216 | */ | |
3217 | static int | |
3218 | srom_map_media(struct net_device *dev) | |
3219 | { | |
3220 | struct de4x5_private *lp = netdev_priv(dev); | |
3221 | ||
eb034a79 | 3222 | lp->fdx = false; |
f3b197ac | 3223 | if (lp->infoblock_media == lp->media) |
1da177e4 LT |
3224 | return 0; |
3225 | ||
3226 | switch(lp->infoblock_media) { | |
3227 | case SROM_10BASETF: | |
3228 | if (!lp->params.fdx) return -1; | |
eb034a79 | 3229 | lp->fdx = true; |
1da177e4 LT |
3230 | case SROM_10BASET: |
3231 | if (lp->params.fdx && !lp->fdx) return -1; | |
3232 | if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) { | |
3233 | lp->media = _10Mb; | |
3234 | } else { | |
3235 | lp->media = TP; | |
3236 | } | |
3237 | break; | |
3238 | ||
3239 | case SROM_10BASE2: | |
3240 | lp->media = BNC; | |
3241 | break; | |
3242 | ||
3243 | case SROM_10BASE5: | |
3244 | lp->media = AUI; | |
3245 | break; | |
3246 | ||
3247 | case SROM_100BASETF: | |
3248 | if (!lp->params.fdx) return -1; | |
eb034a79 | 3249 | lp->fdx = true; |
1da177e4 LT |
3250 | case SROM_100BASET: |
3251 | if (lp->params.fdx && !lp->fdx) return -1; | |
3252 | lp->media = _100Mb; | |
3253 | break; | |
3254 | ||
3255 | case SROM_100BASET4: | |
3256 | lp->media = _100Mb; | |
3257 | break; | |
3258 | ||
3259 | case SROM_100BASEFF: | |
3260 | if (!lp->params.fdx) return -1; | |
eb034a79 | 3261 | lp->fdx = true; |
f3b197ac | 3262 | case SROM_100BASEF: |
1da177e4 LT |
3263 | if (lp->params.fdx && !lp->fdx) return -1; |
3264 | lp->media = _100Mb; | |
3265 | break; | |
3266 | ||
3267 | case ANS: | |
3268 | lp->media = ANS; | |
3269 | lp->fdx = lp->params.fdx; | |
3270 | break; | |
3271 | ||
f3b197ac JG |
3272 | default: |
3273 | printk("%s: Bad media code [%d] detected in SROM!\n", dev->name, | |
1da177e4 LT |
3274 | lp->infoblock_media); |
3275 | return -1; | |
3276 | break; | |
3277 | } | |
3278 | ||
3279 | return 0; | |
3280 | } | |
3281 | ||
3282 | static void | |
3283 | de4x5_init_connection(struct net_device *dev) | |
3284 | { | |
3285 | struct de4x5_private *lp = netdev_priv(dev); | |
3286 | u_long iobase = dev->base_addr; | |
3287 | u_long flags = 0; | |
3288 | ||
3289 | if (lp->media != lp->c_media) { | |
3290 | de4x5_dbg_media(dev); | |
3291 | lp->c_media = lp->media; /* Stop scrolling media messages */ | |
3292 | } | |
3293 | ||
3294 | spin_lock_irqsave(&lp->lock, flags); | |
3295 | de4x5_rst_desc_ring(dev); | |
3296 | de4x5_setup_intr(dev); | |
eb034a79 | 3297 | lp->tx_enable = true; |
1da177e4 LT |
3298 | spin_unlock_irqrestore(&lp->lock, flags); |
3299 | outl(POLL_DEMAND, DE4X5_TPD); | |
3300 | ||
3301 | netif_wake_queue(dev); | |
3302 | ||
3303 | return; | |
3304 | } | |
3305 | ||
3306 | /* | |
3307 | ** General PHY reset function. Some MII devices don't reset correctly | |
3308 | ** since their MII address pins can float at voltages that are dependent | |
3309 | ** on the signal pin use. Do a double reset to ensure a reset. | |
3310 | */ | |
3311 | static int | |
3312 | de4x5_reset_phy(struct net_device *dev) | |
3313 | { | |
3314 | struct de4x5_private *lp = netdev_priv(dev); | |
3315 | u_long iobase = dev->base_addr; | |
3316 | int next_tick = 0; | |
3317 | ||
3318 | if ((lp->useSROM) || (lp->phy[lp->active].id)) { | |
3319 | if (lp->timeout < 0) { | |
3320 | if (lp->useSROM) { | |
3321 | if (lp->phy[lp->active].rst) { | |
3322 | srom_exec(dev, lp->phy[lp->active].rst); | |
3323 | srom_exec(dev, lp->phy[lp->active].rst); | |
3324 | } else if (lp->rst) { /* Type 5 infoblock reset */ | |
3325 | srom_exec(dev, lp->rst); | |
3326 | srom_exec(dev, lp->rst); | |
3327 | } | |
3328 | } else { | |
3329 | PHY_HARD_RESET; | |
3330 | } | |
3331 | if (lp->useMII) { | |
3332 | mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII); | |
3333 | } | |
3334 | } | |
3335 | if (lp->useMII) { | |
eb034a79 | 3336 | next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500); |
1da177e4 LT |
3337 | } |
3338 | } else if (lp->chipset == DC21140) { | |
3339 | PHY_HARD_RESET; | |
3340 | } | |
3341 | ||
3342 | return next_tick; | |
3343 | } | |
3344 | ||
3345 | static int | |
3346 | test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec) | |
3347 | { | |
3348 | struct de4x5_private *lp = netdev_priv(dev); | |
3349 | u_long iobase = dev->base_addr; | |
3350 | s32 sts, csr12; | |
f3b197ac | 3351 | |
1da177e4 LT |
3352 | if (lp->timeout < 0) { |
3353 | lp->timeout = msec/100; | |
3354 | if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */ | |
3355 | reset_init_sia(dev, csr13, csr14, csr15); | |
3356 | } | |
3357 | ||
3358 | /* set up the interrupt mask */ | |
3359 | outl(irq_mask, DE4X5_IMR); | |
3360 | ||
3361 | /* clear all pending interrupts */ | |
3362 | sts = inl(DE4X5_STS); | |
3363 | outl(sts, DE4X5_STS); | |
f3b197ac | 3364 | |
1da177e4 LT |
3365 | /* clear csr12 NRA and SRA bits */ |
3366 | if ((lp->chipset == DC21041) || lp->useSROM) { | |
3367 | csr12 = inl(DE4X5_SISR); | |
3368 | outl(csr12, DE4X5_SISR); | |
3369 | } | |
3370 | } | |
f3b197ac | 3371 | |
1da177e4 | 3372 | sts = inl(DE4X5_STS) & ~TIMER_CB; |
f3b197ac | 3373 | |
1da177e4 LT |
3374 | if (!(sts & irqs) && --lp->timeout) { |
3375 | sts = 100 | TIMER_CB; | |
3376 | } else { | |
3377 | lp->timeout = -1; | |
3378 | } | |
f3b197ac | 3379 | |
1da177e4 LT |
3380 | return sts; |
3381 | } | |
3382 | ||
3383 | static int | |
3384 | test_tp(struct net_device *dev, s32 msec) | |
3385 | { | |
3386 | struct de4x5_private *lp = netdev_priv(dev); | |
3387 | u_long iobase = dev->base_addr; | |
3388 | int sisr; | |
f3b197ac | 3389 | |
1da177e4 LT |
3390 | if (lp->timeout < 0) { |
3391 | lp->timeout = msec/100; | |
3392 | } | |
f3b197ac | 3393 | |
1da177e4 LT |
3394 | sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR); |
3395 | ||
3396 | if (sisr && --lp->timeout) { | |
3397 | sisr = 100 | TIMER_CB; | |
3398 | } else { | |
3399 | lp->timeout = -1; | |
3400 | } | |
f3b197ac | 3401 | |
1da177e4 LT |
3402 | return sisr; |
3403 | } | |
3404 | ||
3405 | /* | |
3406 | ** Samples the 100Mb Link State Signal. The sample interval is important | |
3407 | ** because too fast a rate can give erroneous results and confuse the | |
3408 | ** speed sense algorithm. | |
3409 | */ | |
3410 | #define SAMPLE_INTERVAL 500 /* ms */ | |
3411 | #define SAMPLE_DELAY 2000 /* ms */ | |
3412 | static int | |
3413 | test_for_100Mb(struct net_device *dev, int msec) | |
3414 | { | |
3415 | struct de4x5_private *lp = netdev_priv(dev); | |
3416 | int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK); | |
3417 | ||
3418 | if (lp->timeout < 0) { | |
3419 | if ((msec/SAMPLE_INTERVAL) <= 0) return 0; | |
3420 | if (msec > SAMPLE_DELAY) { | |
3421 | lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL; | |
3422 | gep = SAMPLE_DELAY | TIMER_CB; | |
3423 | return gep; | |
3424 | } else { | |
3425 | lp->timeout = msec/SAMPLE_INTERVAL; | |
3426 | } | |
3427 | } | |
f3b197ac | 3428 | |
1da177e4 LT |
3429 | if (lp->phy[lp->active].id || lp->useSROM) { |
3430 | gep = is_100_up(dev) | is_spd_100(dev); | |
3431 | } else { | |
3432 | gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP)); | |
3433 | } | |
3434 | if (!(gep & ret) && --lp->timeout) { | |
3435 | gep = SAMPLE_INTERVAL | TIMER_CB; | |
3436 | } else { | |
3437 | lp->timeout = -1; | |
3438 | } | |
f3b197ac | 3439 | |
1da177e4 LT |
3440 | return gep; |
3441 | } | |
3442 | ||
3443 | static int | |
3444 | wait_for_link(struct net_device *dev) | |
3445 | { | |
3446 | struct de4x5_private *lp = netdev_priv(dev); | |
3447 | ||
3448 | if (lp->timeout < 0) { | |
3449 | lp->timeout = 1; | |
3450 | } | |
f3b197ac | 3451 | |
1da177e4 LT |
3452 | if (lp->timeout--) { |
3453 | return TIMER_CB; | |
3454 | } else { | |
3455 | lp->timeout = -1; | |
3456 | } | |
f3b197ac | 3457 | |
1da177e4 LT |
3458 | return 0; |
3459 | } | |
3460 | ||
3461 | /* | |
3462 | ** | |
3463 | ** | |
3464 | */ | |
3465 | static int | |
eb034a79 | 3466 | test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec) |
1da177e4 LT |
3467 | { |
3468 | struct de4x5_private *lp = netdev_priv(dev); | |
3469 | int test; | |
3470 | u_long iobase = dev->base_addr; | |
f3b197ac | 3471 | |
1da177e4 LT |
3472 | if (lp->timeout < 0) { |
3473 | lp->timeout = msec/100; | |
3474 | } | |
f3b197ac | 3475 | |
1da177e4 | 3476 | reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask; |
eb034a79 | 3477 | test = (reg ^ (pol ? ~0 : 0)) & mask; |
f3b197ac | 3478 | |
1da177e4 LT |
3479 | if (test && --lp->timeout) { |
3480 | reg = 100 | TIMER_CB; | |
3481 | } else { | |
3482 | lp->timeout = -1; | |
3483 | } | |
f3b197ac | 3484 | |
1da177e4 LT |
3485 | return reg; |
3486 | } | |
3487 | ||
3488 | static int | |
3489 | is_spd_100(struct net_device *dev) | |
3490 | { | |
3491 | struct de4x5_private *lp = netdev_priv(dev); | |
3492 | u_long iobase = dev->base_addr; | |
3493 | int spd; | |
f3b197ac | 3494 | |
1da177e4 LT |
3495 | if (lp->useMII) { |
3496 | spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII); | |
3497 | spd = ~(spd ^ lp->phy[lp->active].spd.value); | |
3498 | spd &= lp->phy[lp->active].spd.mask; | |
3499 | } else if (!lp->useSROM) { /* de500-xa */ | |
3500 | spd = ((~gep_rd(dev)) & GEP_SLNK); | |
3501 | } else { | |
3502 | if ((lp->ibn == 2) || !lp->asBitValid) | |
3503 | return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); | |
3504 | ||
3505 | spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) | | |
3506 | (lp->linkOK & ~lp->asBitValid); | |
3507 | } | |
f3b197ac | 3508 | |
1da177e4 LT |
3509 | return spd; |
3510 | } | |
3511 | ||
3512 | static int | |
3513 | is_100_up(struct net_device *dev) | |
3514 | { | |
3515 | struct de4x5_private *lp = netdev_priv(dev); | |
3516 | u_long iobase = dev->base_addr; | |
f3b197ac | 3517 | |
1da177e4 LT |
3518 | if (lp->useMII) { |
3519 | /* Double read for sticky bits & temporary drops */ | |
3520 | mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); | |
3521 | return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); | |
3522 | } else if (!lp->useSROM) { /* de500-xa */ | |
3523 | return ((~gep_rd(dev)) & GEP_SLNK); | |
3524 | } else { | |
3525 | if ((lp->ibn == 2) || !lp->asBitValid) | |
3526 | return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0); | |
3527 | ||
3528 | return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | | |
3529 | (lp->linkOK & ~lp->asBitValid)); | |
3530 | } | |
3531 | } | |
3532 | ||
3533 | static int | |
3534 | is_10_up(struct net_device *dev) | |
3535 | { | |
3536 | struct de4x5_private *lp = netdev_priv(dev); | |
3537 | u_long iobase = dev->base_addr; | |
f3b197ac | 3538 | |
1da177e4 LT |
3539 | if (lp->useMII) { |
3540 | /* Double read for sticky bits & temporary drops */ | |
3541 | mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII); | |
3542 | return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS); | |
3543 | } else if (!lp->useSROM) { /* de500-xa */ | |
3544 | return ((~gep_rd(dev)) & GEP_LNP); | |
3545 | } else { | |
3546 | if ((lp->ibn == 2) || !lp->asBitValid) | |
3547 | return (((lp->chipset & ~0x00ff) == DC2114x) ? | |
3548 | (~inl(DE4X5_SISR)&SISR_LS10): | |
3549 | 0); | |
3550 | ||
3551 | return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) | | |
3552 | (lp->linkOK & ~lp->asBitValid)); | |
3553 | } | |
3554 | } | |
3555 | ||
3556 | static int | |
3557 | is_anc_capable(struct net_device *dev) | |
3558 | { | |
3559 | struct de4x5_private *lp = netdev_priv(dev); | |
3560 | u_long iobase = dev->base_addr; | |
f3b197ac | 3561 | |
1da177e4 LT |
3562 | if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { |
3563 | return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII)); | |
3564 | } else if ((lp->chipset & ~0x00ff) == DC2114x) { | |
3565 | return (inl(DE4X5_SISR) & SISR_LPN) >> 12; | |
3566 | } else { | |
3567 | return 0; | |
3568 | } | |
3569 | } | |
3570 | ||
3571 | /* | |
3572 | ** Send a packet onto the media and watch for send errors that indicate the | |
3573 | ** media is bad or unconnected. | |
3574 | */ | |
3575 | static int | |
3576 | ping_media(struct net_device *dev, int msec) | |
3577 | { | |
3578 | struct de4x5_private *lp = netdev_priv(dev); | |
3579 | u_long iobase = dev->base_addr; | |
3580 | int sisr; | |
f3b197ac | 3581 | |
1da177e4 LT |
3582 | if (lp->timeout < 0) { |
3583 | lp->timeout = msec/100; | |
f3b197ac | 3584 | |
1da177e4 LT |
3585 | lp->tmp = lp->tx_new; /* Remember the ring position */ |
3586 | load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1); | |
3587 | lp->tx_new = (++lp->tx_new) % lp->txRingSize; | |
3588 | outl(POLL_DEMAND, DE4X5_TPD); | |
3589 | } | |
f3b197ac | 3590 | |
1da177e4 LT |
3591 | sisr = inl(DE4X5_SISR); |
3592 | ||
f3b197ac JG |
3593 | if ((!(sisr & SISR_NCR)) && |
3594 | ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) && | |
1da177e4 LT |
3595 | (--lp->timeout)) { |
3596 | sisr = 100 | TIMER_CB; | |
3597 | } else { | |
f3b197ac | 3598 | if ((!(sisr & SISR_NCR)) && |
1da177e4 LT |
3599 | !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) && |
3600 | lp->timeout) { | |
3601 | sisr = 0; | |
3602 | } else { | |
3603 | sisr = 1; | |
3604 | } | |
3605 | lp->timeout = -1; | |
3606 | } | |
f3b197ac | 3607 | |
1da177e4 LT |
3608 | return sisr; |
3609 | } | |
3610 | ||
3611 | /* | |
3612 | ** This function does 2 things: on Intels it kmalloc's another buffer to | |
3613 | ** replace the one about to be passed up. On Alpha's it kmallocs a buffer | |
3614 | ** into which the packet is copied. | |
3615 | */ | |
3616 | static struct sk_buff * | |
3617 | de4x5_alloc_rx_buff(struct net_device *dev, int index, int len) | |
3618 | { | |
3619 | struct de4x5_private *lp = netdev_priv(dev); | |
3620 | struct sk_buff *p; | |
3621 | ||
49345103 | 3622 | #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY) |
1da177e4 LT |
3623 | struct sk_buff *ret; |
3624 | u_long i=0, tmp; | |
3625 | ||
3626 | p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2); | |
3627 | if (!p) return NULL; | |
3628 | ||
1da177e4 LT |
3629 | tmp = virt_to_bus(p->data); |
3630 | i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp; | |
3631 | skb_reserve(p, i); | |
3632 | lp->rx_ring[index].buf = cpu_to_le32(tmp + i); | |
3633 | ||
3634 | ret = lp->rx_skb[index]; | |
3635 | lp->rx_skb[index] = p; | |
3636 | ||
3637 | if ((u_long) ret > 1) { | |
3638 | skb_put(ret, len); | |
3639 | } | |
3640 | ||
3641 | return ret; | |
3642 | ||
3643 | #else | |
3644 | if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */ | |
3645 | ||
3646 | p = dev_alloc_skb(len + 2); | |
3647 | if (!p) return NULL; | |
3648 | ||
1da177e4 LT |
3649 | skb_reserve(p, 2); /* Align */ |
3650 | if (index < lp->rx_old) { /* Wrapped buffer */ | |
3651 | short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ; | |
3652 | memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen); | |
3653 | memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen); | |
3654 | } else { /* Linear buffer */ | |
3655 | memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len); | |
3656 | } | |
f3b197ac | 3657 | |
1da177e4 LT |
3658 | return p; |
3659 | #endif | |
3660 | } | |
3661 | ||
3662 | static void | |
3663 | de4x5_free_rx_buffs(struct net_device *dev) | |
3664 | { | |
3665 | struct de4x5_private *lp = netdev_priv(dev); | |
3666 | int i; | |
3667 | ||
3668 | for (i=0; i<lp->rxRingSize; i++) { | |
3669 | if ((u_long) lp->rx_skb[i] > 1) { | |
3670 | dev_kfree_skb(lp->rx_skb[i]); | |
3671 | } | |
3672 | lp->rx_ring[i].status = 0; | |
3673 | lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */ | |
3674 | } | |
3675 | ||
3676 | return; | |
3677 | } | |
3678 | ||
3679 | static void | |
3680 | de4x5_free_tx_buffs(struct net_device *dev) | |
3681 | { | |
3682 | struct de4x5_private *lp = netdev_priv(dev); | |
3683 | int i; | |
3684 | ||
3685 | for (i=0; i<lp->txRingSize; i++) { | |
3686 | if (lp->tx_skb[i]) | |
3687 | de4x5_free_tx_buff(lp, i); | |
3688 | lp->tx_ring[i].status = 0; | |
3689 | } | |
3690 | ||
3691 | /* Unload the locally queued packets */ | |
3692 | while (lp->cache.skb) { | |
3693 | dev_kfree_skb(de4x5_get_cache(dev)); | |
3694 | } | |
3695 | ||
3696 | return; | |
3697 | } | |
3698 | ||
3699 | /* | |
3700 | ** When a user pulls a connection, the DECchip can end up in a | |
3701 | ** 'running - waiting for end of transmission' state. This means that we | |
3702 | ** have to perform a chip soft reset to ensure that we can synchronize | |
3703 | ** the hardware and software and make any media probes using a loopback | |
3704 | ** packet meaningful. | |
3705 | */ | |
3706 | static void | |
3707 | de4x5_save_skbs(struct net_device *dev) | |
3708 | { | |
3709 | struct de4x5_private *lp = netdev_priv(dev); | |
3710 | u_long iobase = dev->base_addr; | |
3711 | s32 omr; | |
3712 | ||
3713 | if (!lp->cache.save_cnt) { | |
3714 | STOP_DE4X5; | |
3715 | de4x5_tx(dev); /* Flush any sent skb's */ | |
3716 | de4x5_free_tx_buffs(dev); | |
3717 | de4x5_cache_state(dev, DE4X5_SAVE_STATE); | |
3718 | de4x5_sw_reset(dev); | |
3719 | de4x5_cache_state(dev, DE4X5_RESTORE_STATE); | |
3720 | lp->cache.save_cnt++; | |
3721 | START_DE4X5; | |
3722 | } | |
3723 | ||
3724 | return; | |
3725 | } | |
3726 | ||
3727 | static void | |
3728 | de4x5_rst_desc_ring(struct net_device *dev) | |
3729 | { | |
3730 | struct de4x5_private *lp = netdev_priv(dev); | |
3731 | u_long iobase = dev->base_addr; | |
3732 | int i; | |
3733 | s32 omr; | |
3734 | ||
3735 | if (lp->cache.save_cnt) { | |
3736 | STOP_DE4X5; | |
3737 | outl(lp->dma_rings, DE4X5_RRBA); | |
3738 | outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc), | |
3739 | DE4X5_TRBA); | |
f3b197ac | 3740 | |
1da177e4 LT |
3741 | lp->rx_new = lp->rx_old = 0; |
3742 | lp->tx_new = lp->tx_old = 0; | |
f3b197ac | 3743 | |
1da177e4 LT |
3744 | for (i = 0; i < lp->rxRingSize; i++) { |
3745 | lp->rx_ring[i].status = cpu_to_le32(R_OWN); | |
3746 | } | |
f3b197ac | 3747 | |
1da177e4 LT |
3748 | for (i = 0; i < lp->txRingSize; i++) { |
3749 | lp->tx_ring[i].status = cpu_to_le32(0); | |
3750 | } | |
f3b197ac | 3751 | |
1da177e4 LT |
3752 | barrier(); |
3753 | lp->cache.save_cnt--; | |
3754 | START_DE4X5; | |
3755 | } | |
f3b197ac | 3756 | |
1da177e4 LT |
3757 | return; |
3758 | } | |
3759 | ||
3760 | static void | |
3761 | de4x5_cache_state(struct net_device *dev, int flag) | |
3762 | { | |
3763 | struct de4x5_private *lp = netdev_priv(dev); | |
3764 | u_long iobase = dev->base_addr; | |
3765 | ||
3766 | switch(flag) { | |
3767 | case DE4X5_SAVE_STATE: | |
3768 | lp->cache.csr0 = inl(DE4X5_BMR); | |
3769 | lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR)); | |
3770 | lp->cache.csr7 = inl(DE4X5_IMR); | |
3771 | break; | |
3772 | ||
3773 | case DE4X5_RESTORE_STATE: | |
3774 | outl(lp->cache.csr0, DE4X5_BMR); | |
3775 | outl(lp->cache.csr6, DE4X5_OMR); | |
3776 | outl(lp->cache.csr7, DE4X5_IMR); | |
3777 | if (lp->chipset == DC21140) { | |
3778 | gep_wr(lp->cache.gepc, dev); | |
3779 | gep_wr(lp->cache.gep, dev); | |
3780 | } else { | |
f3b197ac | 3781 | reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, |
1da177e4 LT |
3782 | lp->cache.csr15); |
3783 | } | |
3784 | break; | |
3785 | } | |
3786 | ||
3787 | return; | |
3788 | } | |
3789 | ||
3790 | static void | |
3791 | de4x5_put_cache(struct net_device *dev, struct sk_buff *skb) | |
3792 | { | |
3793 | struct de4x5_private *lp = netdev_priv(dev); | |
3794 | struct sk_buff *p; | |
3795 | ||
3796 | if (lp->cache.skb) { | |
3797 | for (p=lp->cache.skb; p->next; p=p->next); | |
3798 | p->next = skb; | |
3799 | } else { | |
3800 | lp->cache.skb = skb; | |
3801 | } | |
3802 | skb->next = NULL; | |
3803 | ||
3804 | return; | |
3805 | } | |
3806 | ||
3807 | static void | |
3808 | de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb) | |
3809 | { | |
3810 | struct de4x5_private *lp = netdev_priv(dev); | |
3811 | struct sk_buff *p = lp->cache.skb; | |
3812 | ||
3813 | lp->cache.skb = skb; | |
3814 | skb->next = p; | |
3815 | ||
3816 | return; | |
3817 | } | |
3818 | ||
3819 | static struct sk_buff * | |
3820 | de4x5_get_cache(struct net_device *dev) | |
3821 | { | |
3822 | struct de4x5_private *lp = netdev_priv(dev); | |
3823 | struct sk_buff *p = lp->cache.skb; | |
3824 | ||
3825 | if (p) { | |
3826 | lp->cache.skb = p->next; | |
3827 | p->next = NULL; | |
3828 | } | |
3829 | ||
3830 | return p; | |
3831 | } | |
3832 | ||
3833 | /* | |
3834 | ** Check the Auto Negotiation State. Return OK when a link pass interrupt | |
3835 | ** is received and the auto-negotiation status is NWAY OK. | |
3836 | */ | |
3837 | static int | |
3838 | test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec) | |
3839 | { | |
3840 | struct de4x5_private *lp = netdev_priv(dev); | |
3841 | u_long iobase = dev->base_addr; | |
3842 | s32 sts, ans; | |
f3b197ac | 3843 | |
1da177e4 LT |
3844 | if (lp->timeout < 0) { |
3845 | lp->timeout = msec/100; | |
3846 | outl(irq_mask, DE4X5_IMR); | |
f3b197ac | 3847 | |
1da177e4 LT |
3848 | /* clear all pending interrupts */ |
3849 | sts = inl(DE4X5_STS); | |
3850 | outl(sts, DE4X5_STS); | |
3851 | } | |
f3b197ac | 3852 | |
1da177e4 LT |
3853 | ans = inl(DE4X5_SISR) & SISR_ANS; |
3854 | sts = inl(DE4X5_STS) & ~TIMER_CB; | |
f3b197ac | 3855 | |
1da177e4 LT |
3856 | if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) { |
3857 | sts = 100 | TIMER_CB; | |
3858 | } else { | |
3859 | lp->timeout = -1; | |
3860 | } | |
f3b197ac | 3861 | |
1da177e4 LT |
3862 | return sts; |
3863 | } | |
3864 | ||
3865 | static void | |
3866 | de4x5_setup_intr(struct net_device *dev) | |
3867 | { | |
3868 | struct de4x5_private *lp = netdev_priv(dev); | |
3869 | u_long iobase = dev->base_addr; | |
3870 | s32 imr, sts; | |
f3b197ac | 3871 | |
1da177e4 LT |
3872 | if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */ |
3873 | imr = 0; | |
3874 | UNMASK_IRQs; | |
3875 | sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */ | |
3876 | outl(sts, DE4X5_STS); | |
3877 | ENABLE_IRQs; | |
3878 | } | |
f3b197ac | 3879 | |
1da177e4 LT |
3880 | return; |
3881 | } | |
3882 | ||
3883 | /* | |
3884 | ** | |
3885 | */ | |
3886 | static void | |
3887 | reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15) | |
3888 | { | |
3889 | struct de4x5_private *lp = netdev_priv(dev); | |
3890 | u_long iobase = dev->base_addr; | |
3891 | ||
3892 | RESET_SIA; | |
3893 | if (lp->useSROM) { | |
3894 | if (lp->ibn == 3) { | |
3895 | srom_exec(dev, lp->phy[lp->active].rst); | |
3896 | srom_exec(dev, lp->phy[lp->active].gep); | |
3897 | outl(1, DE4X5_SICR); | |
3898 | return; | |
3899 | } else { | |
3900 | csr15 = lp->cache.csr15; | |
3901 | csr14 = lp->cache.csr14; | |
3902 | csr13 = lp->cache.csr13; | |
3903 | outl(csr15 | lp->cache.gepc, DE4X5_SIGR); | |
3904 | outl(csr15 | lp->cache.gep, DE4X5_SIGR); | |
3905 | } | |
3906 | } else { | |
3907 | outl(csr15, DE4X5_SIGR); | |
3908 | } | |
3909 | outl(csr14, DE4X5_STRR); | |
3910 | outl(csr13, DE4X5_SICR); | |
3911 | ||
3912 | mdelay(10); | |
3913 | ||
3914 | return; | |
3915 | } | |
3916 | ||
3917 | /* | |
3918 | ** Create a loopback ethernet packet | |
3919 | */ | |
3920 | static void | |
3921 | create_packet(struct net_device *dev, char *frame, int len) | |
3922 | { | |
3923 | int i; | |
3924 | char *buf = frame; | |
f3b197ac | 3925 | |
1da177e4 LT |
3926 | for (i=0; i<ETH_ALEN; i++) { /* Use this source address */ |
3927 | *buf++ = dev->dev_addr[i]; | |
3928 | } | |
3929 | for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */ | |
3930 | *buf++ = dev->dev_addr[i]; | |
3931 | } | |
f3b197ac | 3932 | |
1da177e4 LT |
3933 | *buf++ = 0; /* Packet length (2 bytes) */ |
3934 | *buf++ = 1; | |
f3b197ac | 3935 | |
1da177e4 LT |
3936 | return; |
3937 | } | |
3938 | ||
3939 | /* | |
3940 | ** Look for a particular board name in the EISA configuration space | |
3941 | */ | |
3942 | static int | |
3943 | EISA_signature(char *name, struct device *device) | |
3944 | { | |
ff8ac609 | 3945 | int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures); |
1da177e4 LT |
3946 | struct eisa_device *edev; |
3947 | ||
3948 | *name = '\0'; | |
3949 | edev = to_eisa_device (device); | |
3950 | i = edev->id.driver_data; | |
3951 | ||
3952 | if (i >= 0 && i < siglen) { | |
3953 | strcpy (name, de4x5_signatures[i]); | |
3954 | status = 1; | |
3955 | } | |
3956 | ||
3957 | return status; /* return the device name string */ | |
3958 | } | |
3959 | ||
3960 | /* | |
3961 | ** Look for a particular board name in the PCI configuration space | |
3962 | */ | |
3963 | static int | |
3964 | PCI_signature(char *name, struct de4x5_private *lp) | |
3965 | { | |
ff8ac609 | 3966 | int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures); |
f3b197ac | 3967 | |
1da177e4 LT |
3968 | if (lp->chipset == DC21040) { |
3969 | strcpy(name, "DE434/5"); | |
3970 | return status; | |
3971 | } else { /* Search for a DEC name in the SROM */ | |
3972 | int i = *((char *)&lp->srom + 19) * 3; | |
3973 | strncpy(name, (char *)&lp->srom + 26 + i, 8); | |
3974 | } | |
3975 | name[8] = '\0'; | |
3976 | for (i=0; i<siglen; i++) { | |
3977 | if (strstr(name,de4x5_signatures[i])!=NULL) break; | |
3978 | } | |
3979 | if (i == siglen) { | |
3980 | if (dec_only) { | |
3981 | *name = '\0'; | |
3982 | } else { /* Use chip name to avoid confusion */ | |
3983 | strcpy(name, (((lp->chipset == DC21040) ? "DC21040" : | |
3984 | ((lp->chipset == DC21041) ? "DC21041" : | |
3985 | ((lp->chipset == DC21140) ? "DC21140" : | |
3986 | ((lp->chipset == DC21142) ? "DC21142" : | |
3987 | ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN" | |
3988 | ))))))); | |
3989 | } | |
3990 | if (lp->chipset != DC21041) { | |
eb034a79 | 3991 | lp->useSROM = true; /* card is not recognisably DEC */ |
1da177e4 LT |
3992 | } |
3993 | } else if ((lp->chipset & ~0x00ff) == DC2114x) { | |
eb034a79 | 3994 | lp->useSROM = true; |
1da177e4 | 3995 | } |
f3b197ac | 3996 | |
1da177e4 LT |
3997 | return status; |
3998 | } | |
3999 | ||
4000 | /* | |
4001 | ** Set up the Ethernet PROM counter to the start of the Ethernet address on | |
4002 | ** the DC21040, else read the SROM for the other chips. | |
4003 | ** The SROM may not be present in a multi-MAC card, so first read the | |
4004 | ** MAC address and check for a bad address. If there is a bad one then exit | |
4005 | ** immediately with the prior srom contents intact (the h/w address will | |
4006 | ** be fixed up later). | |
4007 | */ | |
4008 | static void | |
4009 | DevicePresent(struct net_device *dev, u_long aprom_addr) | |
4010 | { | |
4011 | int i, j=0; | |
4012 | struct de4x5_private *lp = netdev_priv(dev); | |
f3b197ac | 4013 | |
1da177e4 LT |
4014 | if (lp->chipset == DC21040) { |
4015 | if (lp->bus == EISA) { | |
4016 | enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */ | |
4017 | } else { | |
4018 | outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */ | |
4019 | } | |
4020 | } else { /* Read new srom */ | |
4021 | u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD); | |
4022 | for (i=0; i<(ETH_ALEN>>1); i++) { | |
4023 | tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i); | |
4024 | *p = le16_to_cpu(tmp); | |
4025 | j += *p++; | |
4026 | } | |
4027 | if ((j == 0) || (j == 0x2fffd)) { | |
4028 | return; | |
4029 | } | |
4030 | ||
4031 | p=(short *)&lp->srom; | |
4032 | for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) { | |
4033 | tmp = srom_rd(aprom_addr, i); | |
4034 | *p++ = le16_to_cpu(tmp); | |
4035 | } | |
4036 | de4x5_dbg_srom((struct de4x5_srom *)&lp->srom); | |
4037 | } | |
f3b197ac | 4038 | |
1da177e4 LT |
4039 | return; |
4040 | } | |
4041 | ||
4042 | /* | |
4043 | ** Since the write on the Enet PROM register doesn't seem to reset the PROM | |
4044 | ** pointer correctly (at least on my DE425 EISA card), this routine should do | |
4045 | ** it...from depca.c. | |
4046 | */ | |
4047 | static void | |
4048 | enet_addr_rst(u_long aprom_addr) | |
4049 | { | |
4050 | union { | |
4051 | struct { | |
4052 | u32 a; | |
4053 | u32 b; | |
4054 | } llsig; | |
4055 | char Sig[sizeof(u32) << 1]; | |
4056 | } dev; | |
4057 | short sigLength=0; | |
4058 | s8 data; | |
4059 | int i, j; | |
f3b197ac | 4060 | |
1da177e4 LT |
4061 | dev.llsig.a = ETH_PROM_SIG; |
4062 | dev.llsig.b = ETH_PROM_SIG; | |
4063 | sigLength = sizeof(u32) << 1; | |
f3b197ac | 4064 | |
1da177e4 LT |
4065 | for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) { |
4066 | data = inb(aprom_addr); | |
4067 | if (dev.Sig[j] == data) { /* track signature */ | |
4068 | j++; | |
4069 | } else { /* lost signature; begin search again */ | |
4070 | if (data == dev.Sig[0]) { /* rare case.... */ | |
4071 | j=1; | |
4072 | } else { | |
4073 | j=0; | |
4074 | } | |
4075 | } | |
4076 | } | |
f3b197ac | 4077 | |
1da177e4 LT |
4078 | return; |
4079 | } | |
4080 | ||
4081 | /* | |
4082 | ** For the bad status case and no SROM, then add one to the previous | |
4083 | ** address. However, need to add one backwards in case we have 0xff | |
4084 | ** as one or more of the bytes. Only the last 3 bytes should be checked | |
4085 | ** as the first three are invariant - assigned to an organisation. | |
4086 | */ | |
4087 | static int | |
4088 | get_hw_addr(struct net_device *dev) | |
4089 | { | |
4090 | u_long iobase = dev->base_addr; | |
4091 | int broken, i, k, tmp, status = 0; | |
4092 | u_short j,chksum; | |
4093 | struct de4x5_private *lp = netdev_priv(dev); | |
4094 | ||
4095 | broken = de4x5_bad_srom(lp); | |
4096 | ||
4097 | for (i=0,k=0,j=0;j<3;j++) { | |
4098 | k <<= 1; | |
4099 | if (k > 0xffff) k-=0xffff; | |
f3b197ac | 4100 | |
1da177e4 LT |
4101 | if (lp->bus == PCI) { |
4102 | if (lp->chipset == DC21040) { | |
4103 | while ((tmp = inl(DE4X5_APROM)) < 0); | |
4104 | k += (u_char) tmp; | |
4105 | dev->dev_addr[i++] = (u_char) tmp; | |
4106 | while ((tmp = inl(DE4X5_APROM)) < 0); | |
4107 | k += (u_short) (tmp << 8); | |
4108 | dev->dev_addr[i++] = (u_char) tmp; | |
4109 | } else if (!broken) { | |
4110 | dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; | |
4111 | dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++; | |
4112 | } else if ((broken == SMC) || (broken == ACCTON)) { | |
4113 | dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; | |
4114 | dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++; | |
4115 | } | |
4116 | } else { | |
4117 | k += (u_char) (tmp = inb(EISA_APROM)); | |
4118 | dev->dev_addr[i++] = (u_char) tmp; | |
4119 | k += (u_short) ((tmp = inb(EISA_APROM)) << 8); | |
4120 | dev->dev_addr[i++] = (u_char) tmp; | |
4121 | } | |
f3b197ac | 4122 | |
1da177e4 LT |
4123 | if (k > 0xffff) k-=0xffff; |
4124 | } | |
4125 | if (k == 0xffff) k=0; | |
f3b197ac | 4126 | |
1da177e4 LT |
4127 | if (lp->bus == PCI) { |
4128 | if (lp->chipset == DC21040) { | |
4129 | while ((tmp = inl(DE4X5_APROM)) < 0); | |
4130 | chksum = (u_char) tmp; | |
4131 | while ((tmp = inl(DE4X5_APROM)) < 0); | |
4132 | chksum |= (u_short) (tmp << 8); | |
4133 | if ((k != chksum) && (dec_only)) status = -1; | |
4134 | } | |
4135 | } else { | |
4136 | chksum = (u_char) inb(EISA_APROM); | |
4137 | chksum |= (u_short) (inb(EISA_APROM) << 8); | |
4138 | if ((k != chksum) && (dec_only)) status = -1; | |
4139 | } | |
4140 | ||
4141 | /* If possible, try to fix a broken card - SMC only so far */ | |
4142 | srom_repair(dev, broken); | |
4143 | ||
bfaadcad | 4144 | #ifdef CONFIG_PPC_PMAC |
f3b197ac | 4145 | /* |
1da177e4 LT |
4146 | ** If the address starts with 00 a0, we have to bit-reverse |
4147 | ** each byte of the address. | |
4148 | */ | |
e8222502 | 4149 | if ( machine_is(powermac) && |
1da177e4 LT |
4150 | (dev->dev_addr[0] == 0) && |
4151 | (dev->dev_addr[1] == 0xa0) ) | |
4152 | { | |
4153 | for (i = 0; i < ETH_ALEN; ++i) | |
4154 | { | |
4155 | int x = dev->dev_addr[i]; | |
4156 | x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4); | |
4157 | x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2); | |
4158 | dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1); | |
4159 | } | |
4160 | } | |
bfaadcad | 4161 | #endif /* CONFIG_PPC_PMAC */ |
1da177e4 LT |
4162 | |
4163 | /* Test for a bad enet address */ | |
4164 | status = test_bad_enet(dev, status); | |
4165 | ||
4166 | return status; | |
4167 | } | |
4168 | ||
4169 | /* | |
4170 | ** Test for enet addresses in the first 32 bytes. The built-in strncmp | |
4171 | ** didn't seem to work here...? | |
4172 | */ | |
4173 | static int | |
4174 | de4x5_bad_srom(struct de4x5_private *lp) | |
4175 | { | |
4176 | int i, status = 0; | |
4177 | ||
4178 | for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) { | |
4179 | if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) && | |
4180 | !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) { | |
4181 | if (i == 0) { | |
4182 | status = SMC; | |
4183 | } else if (i == 1) { | |
4184 | status = ACCTON; | |
4185 | } | |
4186 | break; | |
4187 | } | |
4188 | } | |
4189 | ||
4190 | return status; | |
4191 | } | |
4192 | ||
4193 | static int | |
4194 | de4x5_strncmp(char *a, char *b, int n) | |
4195 | { | |
4196 | int ret=0; | |
4197 | ||
4198 | for (;n && !ret;n--) { | |
4199 | ret = *a++ - *b++; | |
4200 | } | |
4201 | ||
4202 | return ret; | |
4203 | } | |
4204 | ||
4205 | static void | |
4206 | srom_repair(struct net_device *dev, int card) | |
4207 | { | |
4208 | struct de4x5_private *lp = netdev_priv(dev); | |
4209 | ||
4210 | switch(card) { | |
4211 | case SMC: | |
4212 | memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom)); | |
4213 | memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN); | |
4214 | memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100); | |
eb034a79 | 4215 | lp->useSROM = true; |
1da177e4 LT |
4216 | break; |
4217 | } | |
4218 | ||
4219 | return; | |
4220 | } | |
4221 | ||
4222 | /* | |
4223 | ** Assume that the irq's do not follow the PCI spec - this is seems | |
4224 | ** to be true so far (2 for 2). | |
4225 | */ | |
4226 | static int | |
4227 | test_bad_enet(struct net_device *dev, int status) | |
4228 | { | |
4229 | struct de4x5_private *lp = netdev_priv(dev); | |
4230 | int i, tmp; | |
4231 | ||
4232 | for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i]; | |
4233 | if ((tmp == 0) || (tmp == 0x5fa)) { | |
f3b197ac | 4234 | if ((lp->chipset == last.chipset) && |
1da177e4 LT |
4235 | (lp->bus_num == last.bus) && (lp->bus_num > 0)) { |
4236 | for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i]; | |
4237 | for (i=ETH_ALEN-1; i>2; --i) { | |
4238 | dev->dev_addr[i] += 1; | |
4239 | if (dev->dev_addr[i] != 0) break; | |
4240 | } | |
4241 | for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; | |
4242 | if (!an_exception(lp)) { | |
4243 | dev->irq = last.irq; | |
4244 | } | |
4245 | ||
4246 | status = 0; | |
4247 | } | |
4248 | } else if (!status) { | |
4249 | last.chipset = lp->chipset; | |
4250 | last.bus = lp->bus_num; | |
4251 | last.irq = dev->irq; | |
4252 | for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i]; | |
4253 | } | |
4254 | ||
4255 | return status; | |
4256 | } | |
4257 | ||
4258 | /* | |
4259 | ** List of board exceptions with correctly wired IRQs | |
4260 | */ | |
4261 | static int | |
4262 | an_exception(struct de4x5_private *lp) | |
4263 | { | |
f3b197ac | 4264 | if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) && |
1da177e4 LT |
4265 | (*(u_short *)lp->srom.sub_system_id == 0x95e0)) { |
4266 | return -1; | |
4267 | } | |
4268 | ||
4269 | return 0; | |
4270 | } | |
4271 | ||
4272 | /* | |
4273 | ** SROM Read | |
4274 | */ | |
4275 | static short | |
4276 | srom_rd(u_long addr, u_char offset) | |
4277 | { | |
4278 | sendto_srom(SROM_RD | SROM_SR, addr); | |
f3b197ac | 4279 | |
1da177e4 LT |
4280 | srom_latch(SROM_RD | SROM_SR | DT_CS, addr); |
4281 | srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr); | |
4282 | srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset); | |
f3b197ac | 4283 | |
1da177e4 LT |
4284 | return srom_data(SROM_RD | SROM_SR | DT_CS, addr); |
4285 | } | |
4286 | ||
4287 | static void | |
4288 | srom_latch(u_int command, u_long addr) | |
4289 | { | |
4290 | sendto_srom(command, addr); | |
4291 | sendto_srom(command | DT_CLK, addr); | |
4292 | sendto_srom(command, addr); | |
f3b197ac | 4293 | |
1da177e4 LT |
4294 | return; |
4295 | } | |
4296 | ||
4297 | static void | |
4298 | srom_command(u_int command, u_long addr) | |
4299 | { | |
4300 | srom_latch(command, addr); | |
4301 | srom_latch(command, addr); | |
4302 | srom_latch((command & 0x0000ff00) | DT_CS, addr); | |
f3b197ac | 4303 | |
1da177e4 LT |
4304 | return; |
4305 | } | |
4306 | ||
4307 | static void | |
4308 | srom_address(u_int command, u_long addr, u_char offset) | |
4309 | { | |
4310 | int i, a; | |
f3b197ac | 4311 | |
1da177e4 LT |
4312 | a = offset << 2; |
4313 | for (i=0; i<6; i++, a <<= 1) { | |
4314 | srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr); | |
4315 | } | |
4316 | udelay(1); | |
f3b197ac | 4317 | |
1da177e4 | 4318 | i = (getfrom_srom(addr) >> 3) & 0x01; |
f3b197ac | 4319 | |
1da177e4 LT |
4320 | return; |
4321 | } | |
4322 | ||
4323 | static short | |
4324 | srom_data(u_int command, u_long addr) | |
4325 | { | |
4326 | int i; | |
4327 | short word = 0; | |
4328 | s32 tmp; | |
f3b197ac | 4329 | |
1da177e4 LT |
4330 | for (i=0; i<16; i++) { |
4331 | sendto_srom(command | DT_CLK, addr); | |
4332 | tmp = getfrom_srom(addr); | |
4333 | sendto_srom(command, addr); | |
f3b197ac | 4334 | |
1da177e4 LT |
4335 | word = (word << 1) | ((tmp >> 3) & 0x01); |
4336 | } | |
f3b197ac | 4337 | |
1da177e4 | 4338 | sendto_srom(command & 0x0000ff00, addr); |
f3b197ac | 4339 | |
1da177e4 LT |
4340 | return word; |
4341 | } | |
4342 | ||
4343 | /* | |
4344 | static void | |
4345 | srom_busy(u_int command, u_long addr) | |
4346 | { | |
4347 | sendto_srom((command & 0x0000ff00) | DT_CS, addr); | |
f3b197ac | 4348 | |
1da177e4 LT |
4349 | while (!((getfrom_srom(addr) >> 3) & 0x01)) { |
4350 | mdelay(1); | |
4351 | } | |
f3b197ac | 4352 | |
1da177e4 | 4353 | sendto_srom(command & 0x0000ff00, addr); |
f3b197ac | 4354 | |
1da177e4 LT |
4355 | return; |
4356 | } | |
4357 | */ | |
4358 | ||
4359 | static void | |
4360 | sendto_srom(u_int command, u_long addr) | |
4361 | { | |
4362 | outl(command, addr); | |
4363 | udelay(1); | |
f3b197ac | 4364 | |
1da177e4 LT |
4365 | return; |
4366 | } | |
4367 | ||
4368 | static int | |
4369 | getfrom_srom(u_long addr) | |
4370 | { | |
4371 | s32 tmp; | |
f3b197ac | 4372 | |
1da177e4 LT |
4373 | tmp = inl(addr); |
4374 | udelay(1); | |
f3b197ac | 4375 | |
1da177e4 LT |
4376 | return tmp; |
4377 | } | |
4378 | ||
4379 | static int | |
4380 | srom_infoleaf_info(struct net_device *dev) | |
4381 | { | |
4382 | struct de4x5_private *lp = netdev_priv(dev); | |
4383 | int i, count; | |
4384 | u_char *p; | |
4385 | ||
4386 | /* Find the infoleaf decoder function that matches this chipset */ | |
4387 | for (i=0; i<INFOLEAF_SIZE; i++) { | |
4388 | if (lp->chipset == infoleaf_array[i].chipset) break; | |
4389 | } | |
4390 | if (i == INFOLEAF_SIZE) { | |
eb034a79 | 4391 | lp->useSROM = false; |
f3b197ac | 4392 | printk("%s: Cannot find correct chipset for SROM decoding!\n", |
1da177e4 LT |
4393 | dev->name); |
4394 | return -ENXIO; | |
4395 | } | |
4396 | ||
4397 | lp->infoleaf_fn = infoleaf_array[i].fn; | |
4398 | ||
4399 | /* Find the information offset that this function should use */ | |
4400 | count = *((u_char *)&lp->srom + 19); | |
4401 | p = (u_char *)&lp->srom + 26; | |
4402 | ||
4403 | if (count > 1) { | |
4404 | for (i=count; i; --i, p+=3) { | |
4405 | if (lp->device == *p) break; | |
4406 | } | |
4407 | if (i == 0) { | |
eb034a79 | 4408 | lp->useSROM = false; |
f3b197ac | 4409 | printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n", |
1da177e4 LT |
4410 | dev->name, lp->device); |
4411 | return -ENXIO; | |
4412 | } | |
4413 | } | |
4414 | ||
4415 | lp->infoleaf_offset = TWIDDLE(p+1); | |
4416 | ||
4417 | return 0; | |
4418 | } | |
4419 | ||
4420 | /* | |
4421 | ** This routine loads any type 1 or 3 MII info into the mii device | |
4422 | ** struct and executes any type 5 code to reset PHY devices for this | |
4423 | ** controller. | |
4424 | ** The info for the MII devices will be valid since the index used | |
4425 | ** will follow the discovery process from MII address 1-31 then 0. | |
4426 | */ | |
4427 | static void | |
4428 | srom_init(struct net_device *dev) | |
4429 | { | |
4430 | struct de4x5_private *lp = netdev_priv(dev); | |
4431 | u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; | |
4432 | u_char count; | |
4433 | ||
4434 | p+=2; | |
4435 | if (lp->chipset == DC21140) { | |
4436 | lp->cache.gepc = (*p++ | GEP_CTRL); | |
4437 | gep_wr(lp->cache.gepc, dev); | |
4438 | } | |
4439 | ||
4440 | /* Block count */ | |
4441 | count = *p++; | |
4442 | ||
4443 | /* Jump the infoblocks to find types */ | |
4444 | for (;count; --count) { | |
4445 | if (*p < 128) { | |
4446 | p += COMPACT_LEN; | |
4447 | } else if (*(p+1) == 5) { | |
4448 | type5_infoblock(dev, 1, p); | |
4449 | p += ((*p & BLOCK_LEN) + 1); | |
4450 | } else if (*(p+1) == 4) { | |
4451 | p += ((*p & BLOCK_LEN) + 1); | |
4452 | } else if (*(p+1) == 3) { | |
4453 | type3_infoblock(dev, 1, p); | |
4454 | p += ((*p & BLOCK_LEN) + 1); | |
4455 | } else if (*(p+1) == 2) { | |
4456 | p += ((*p & BLOCK_LEN) + 1); | |
4457 | } else if (*(p+1) == 1) { | |
4458 | type1_infoblock(dev, 1, p); | |
4459 | p += ((*p & BLOCK_LEN) + 1); | |
4460 | } else { | |
4461 | p += ((*p & BLOCK_LEN) + 1); | |
4462 | } | |
4463 | } | |
4464 | ||
4465 | return; | |
4466 | } | |
4467 | ||
4468 | /* | |
4469 | ** A generic routine that writes GEP control, data and reset information | |
4470 | ** to the GEP register (21140) or csr15 GEP portion (2114[23]). | |
4471 | */ | |
4472 | static void | |
4473 | srom_exec(struct net_device *dev, u_char *p) | |
4474 | { | |
4475 | struct de4x5_private *lp = netdev_priv(dev); | |
4476 | u_long iobase = dev->base_addr; | |
4477 | u_char count = (p ? *p++ : 0); | |
4478 | u_short *w = (u_short *)p; | |
4479 | ||
4480 | if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return; | |
4481 | ||
4482 | if (lp->chipset != DC21140) RESET_SIA; | |
f3b197ac | 4483 | |
1da177e4 | 4484 | while (count--) { |
f3b197ac | 4485 | gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ? |
1da177e4 LT |
4486 | *p++ : TWIDDLE(w++)), dev); |
4487 | mdelay(2); /* 2ms per action */ | |
4488 | } | |
4489 | ||
4490 | if (lp->chipset != DC21140) { | |
4491 | outl(lp->cache.csr14, DE4X5_STRR); | |
4492 | outl(lp->cache.csr13, DE4X5_SICR); | |
4493 | } | |
4494 | ||
4495 | return; | |
4496 | } | |
4497 | ||
4498 | /* | |
4499 | ** Basically this function is a NOP since it will never be called, | |
4500 | ** unless I implement the DC21041 SROM functions. There's no need | |
4501 | ** since the existing code will be satisfactory for all boards. | |
4502 | */ | |
f3b197ac | 4503 | static int |
1da177e4 LT |
4504 | dc21041_infoleaf(struct net_device *dev) |
4505 | { | |
4506 | return DE4X5_AUTOSENSE_MS; | |
4507 | } | |
4508 | ||
f3b197ac | 4509 | static int |
1da177e4 LT |
4510 | dc21140_infoleaf(struct net_device *dev) |
4511 | { | |
4512 | struct de4x5_private *lp = netdev_priv(dev); | |
4513 | u_char count = 0; | |
4514 | u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; | |
4515 | int next_tick = DE4X5_AUTOSENSE_MS; | |
4516 | ||
4517 | /* Read the connection type */ | |
4518 | p+=2; | |
4519 | ||
4520 | /* GEP control */ | |
4521 | lp->cache.gepc = (*p++ | GEP_CTRL); | |
4522 | ||
4523 | /* Block count */ | |
4524 | count = *p++; | |
4525 | ||
4526 | /* Recursively figure out the info blocks */ | |
4527 | if (*p < 128) { | |
4528 | next_tick = dc_infoblock[COMPACT](dev, count, p); | |
4529 | } else { | |
4530 | next_tick = dc_infoblock[*(p+1)](dev, count, p); | |
4531 | } | |
4532 | ||
4533 | if (lp->tcount == count) { | |
4534 | lp->media = NC; | |
4535 | if (lp->media != lp->c_media) { | |
4536 | de4x5_dbg_media(dev); | |
4537 | lp->c_media = lp->media; | |
4538 | } | |
4539 | lp->media = INIT; | |
4540 | lp->tcount = 0; | |
eb034a79 | 4541 | lp->tx_enable = false; |
1da177e4 LT |
4542 | } |
4543 | ||
4544 | return next_tick & ~TIMER_CB; | |
4545 | } | |
4546 | ||
f3b197ac | 4547 | static int |
1da177e4 LT |
4548 | dc21142_infoleaf(struct net_device *dev) |
4549 | { | |
4550 | struct de4x5_private *lp = netdev_priv(dev); | |
4551 | u_char count = 0; | |
4552 | u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; | |
4553 | int next_tick = DE4X5_AUTOSENSE_MS; | |
4554 | ||
4555 | /* Read the connection type */ | |
4556 | p+=2; | |
4557 | ||
4558 | /* Block count */ | |
4559 | count = *p++; | |
4560 | ||
4561 | /* Recursively figure out the info blocks */ | |
4562 | if (*p < 128) { | |
4563 | next_tick = dc_infoblock[COMPACT](dev, count, p); | |
4564 | } else { | |
4565 | next_tick = dc_infoblock[*(p+1)](dev, count, p); | |
4566 | } | |
4567 | ||
4568 | if (lp->tcount == count) { | |
4569 | lp->media = NC; | |
4570 | if (lp->media != lp->c_media) { | |
4571 | de4x5_dbg_media(dev); | |
4572 | lp->c_media = lp->media; | |
4573 | } | |
4574 | lp->media = INIT; | |
4575 | lp->tcount = 0; | |
eb034a79 | 4576 | lp->tx_enable = false; |
1da177e4 LT |
4577 | } |
4578 | ||
4579 | return next_tick & ~TIMER_CB; | |
4580 | } | |
4581 | ||
f3b197ac | 4582 | static int |
1da177e4 LT |
4583 | dc21143_infoleaf(struct net_device *dev) |
4584 | { | |
4585 | struct de4x5_private *lp = netdev_priv(dev); | |
4586 | u_char count = 0; | |
4587 | u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset; | |
4588 | int next_tick = DE4X5_AUTOSENSE_MS; | |
4589 | ||
4590 | /* Read the connection type */ | |
4591 | p+=2; | |
4592 | ||
4593 | /* Block count */ | |
4594 | count = *p++; | |
4595 | ||
4596 | /* Recursively figure out the info blocks */ | |
4597 | if (*p < 128) { | |
4598 | next_tick = dc_infoblock[COMPACT](dev, count, p); | |
4599 | } else { | |
4600 | next_tick = dc_infoblock[*(p+1)](dev, count, p); | |
4601 | } | |
4602 | if (lp->tcount == count) { | |
4603 | lp->media = NC; | |
4604 | if (lp->media != lp->c_media) { | |
4605 | de4x5_dbg_media(dev); | |
4606 | lp->c_media = lp->media; | |
4607 | } | |
4608 | lp->media = INIT; | |
4609 | lp->tcount = 0; | |
eb034a79 | 4610 | lp->tx_enable = false; |
1da177e4 LT |
4611 | } |
4612 | ||
4613 | return next_tick & ~TIMER_CB; | |
4614 | } | |
4615 | ||
4616 | /* | |
4617 | ** The compact infoblock is only designed for DC21140[A] chips, so | |
4618 | ** we'll reuse the dc21140m_autoconf function. Non MII media only. | |
4619 | */ | |
f3b197ac | 4620 | static int |
1da177e4 LT |
4621 | compact_infoblock(struct net_device *dev, u_char count, u_char *p) |
4622 | { | |
4623 | struct de4x5_private *lp = netdev_priv(dev); | |
4624 | u_char flags, csr6; | |
4625 | ||
4626 | /* Recursively figure out the info blocks */ | |
4627 | if (--count > lp->tcount) { | |
4628 | if (*(p+COMPACT_LEN) < 128) { | |
4629 | return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN); | |
4630 | } else { | |
4631 | return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN); | |
4632 | } | |
4633 | } | |
4634 | ||
4635 | if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4636 | lp->ibn = COMPACT; | |
4637 | lp->active = 0; | |
4638 | gep_wr(lp->cache.gepc, dev); | |
4639 | lp->infoblock_media = (*p++) & COMPACT_MC; | |
4640 | lp->cache.gep = *p++; | |
4641 | csr6 = *p++; | |
4642 | flags = *p++; | |
4643 | ||
4644 | lp->asBitValid = (flags & 0x80) ? 0 : -1; | |
4645 | lp->defMedium = (flags & 0x40) ? -1 : 0; | |
4646 | lp->asBit = 1 << ((csr6 >> 1) & 0x07); | |
4647 | lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; | |
4648 | lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); | |
eb034a79 | 4649 | lp->useMII = false; |
1da177e4 LT |
4650 | |
4651 | de4x5_switch_mac_port(dev); | |
4652 | } | |
4653 | ||
4654 | return dc21140m_autoconf(dev); | |
4655 | } | |
4656 | ||
4657 | /* | |
4658 | ** This block describes non MII media for the DC21140[A] only. | |
4659 | */ | |
f3b197ac | 4660 | static int |
1da177e4 LT |
4661 | type0_infoblock(struct net_device *dev, u_char count, u_char *p) |
4662 | { | |
4663 | struct de4x5_private *lp = netdev_priv(dev); | |
4664 | u_char flags, csr6, len = (*p & BLOCK_LEN)+1; | |
4665 | ||
4666 | /* Recursively figure out the info blocks */ | |
4667 | if (--count > lp->tcount) { | |
4668 | if (*(p+len) < 128) { | |
4669 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4670 | } else { | |
4671 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4672 | } | |
4673 | } | |
4674 | ||
4675 | if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4676 | lp->ibn = 0; | |
4677 | lp->active = 0; | |
4678 | gep_wr(lp->cache.gepc, dev); | |
4679 | p+=2; | |
4680 | lp->infoblock_media = (*p++) & BLOCK0_MC; | |
4681 | lp->cache.gep = *p++; | |
4682 | csr6 = *p++; | |
4683 | flags = *p++; | |
4684 | ||
4685 | lp->asBitValid = (flags & 0x80) ? 0 : -1; | |
4686 | lp->defMedium = (flags & 0x40) ? -1 : 0; | |
4687 | lp->asBit = 1 << ((csr6 >> 1) & 0x07); | |
4688 | lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; | |
4689 | lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); | |
eb034a79 | 4690 | lp->useMII = false; |
1da177e4 LT |
4691 | |
4692 | de4x5_switch_mac_port(dev); | |
4693 | } | |
4694 | ||
4695 | return dc21140m_autoconf(dev); | |
4696 | } | |
4697 | ||
4698 | /* These functions are under construction! */ | |
4699 | ||
f3b197ac | 4700 | static int |
1da177e4 LT |
4701 | type1_infoblock(struct net_device *dev, u_char count, u_char *p) |
4702 | { | |
4703 | struct de4x5_private *lp = netdev_priv(dev); | |
4704 | u_char len = (*p & BLOCK_LEN)+1; | |
4705 | ||
4706 | /* Recursively figure out the info blocks */ | |
4707 | if (--count > lp->tcount) { | |
4708 | if (*(p+len) < 128) { | |
4709 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4710 | } else { | |
4711 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4712 | } | |
4713 | } | |
4714 | ||
4715 | p += 2; | |
4716 | if (lp->state == INITIALISED) { | |
4717 | lp->ibn = 1; | |
4718 | lp->active = *p++; | |
4719 | lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1); | |
4720 | lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1); | |
4721 | lp->phy[lp->active].mc = TWIDDLE(p); p += 2; | |
4722 | lp->phy[lp->active].ana = TWIDDLE(p); p += 2; | |
4723 | lp->phy[lp->active].fdx = TWIDDLE(p); p += 2; | |
4724 | lp->phy[lp->active].ttm = TWIDDLE(p); | |
4725 | return 0; | |
4726 | } else if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4727 | lp->ibn = 1; | |
4728 | lp->active = *p; | |
4729 | lp->infoblock_csr6 = OMR_MII_100; | |
eb034a79 | 4730 | lp->useMII = true; |
1da177e4 LT |
4731 | lp->infoblock_media = ANS; |
4732 | ||
4733 | de4x5_switch_mac_port(dev); | |
4734 | } | |
4735 | ||
4736 | return dc21140m_autoconf(dev); | |
4737 | } | |
4738 | ||
f3b197ac | 4739 | static int |
1da177e4 LT |
4740 | type2_infoblock(struct net_device *dev, u_char count, u_char *p) |
4741 | { | |
4742 | struct de4x5_private *lp = netdev_priv(dev); | |
4743 | u_char len = (*p & BLOCK_LEN)+1; | |
4744 | ||
4745 | /* Recursively figure out the info blocks */ | |
4746 | if (--count > lp->tcount) { | |
4747 | if (*(p+len) < 128) { | |
4748 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4749 | } else { | |
4750 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4751 | } | |
4752 | } | |
4753 | ||
4754 | if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4755 | lp->ibn = 2; | |
4756 | lp->active = 0; | |
4757 | p += 2; | |
4758 | lp->infoblock_media = (*p) & MEDIA_CODE; | |
4759 | ||
4760 | if ((*p++) & EXT_FIELD) { | |
4761 | lp->cache.csr13 = TWIDDLE(p); p += 2; | |
4762 | lp->cache.csr14 = TWIDDLE(p); p += 2; | |
4763 | lp->cache.csr15 = TWIDDLE(p); p += 2; | |
4764 | } else { | |
4765 | lp->cache.csr13 = CSR13; | |
4766 | lp->cache.csr14 = CSR14; | |
4767 | lp->cache.csr15 = CSR15; | |
4768 | } | |
4769 | lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2; | |
4770 | lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); | |
4771 | lp->infoblock_csr6 = OMR_SIA; | |
eb034a79 | 4772 | lp->useMII = false; |
1da177e4 LT |
4773 | |
4774 | de4x5_switch_mac_port(dev); | |
4775 | } | |
4776 | ||
4777 | return dc2114x_autoconf(dev); | |
4778 | } | |
4779 | ||
f3b197ac | 4780 | static int |
1da177e4 LT |
4781 | type3_infoblock(struct net_device *dev, u_char count, u_char *p) |
4782 | { | |
4783 | struct de4x5_private *lp = netdev_priv(dev); | |
4784 | u_char len = (*p & BLOCK_LEN)+1; | |
4785 | ||
4786 | /* Recursively figure out the info blocks */ | |
4787 | if (--count > lp->tcount) { | |
4788 | if (*(p+len) < 128) { | |
4789 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4790 | } else { | |
4791 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4792 | } | |
4793 | } | |
4794 | ||
4795 | p += 2; | |
4796 | if (lp->state == INITIALISED) { | |
4797 | lp->ibn = 3; | |
4798 | lp->active = *p++; | |
4799 | if (MOTO_SROM_BUG) lp->active = 0; | |
4800 | lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1); | |
4801 | lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1); | |
4802 | lp->phy[lp->active].mc = TWIDDLE(p); p += 2; | |
4803 | lp->phy[lp->active].ana = TWIDDLE(p); p += 2; | |
4804 | lp->phy[lp->active].fdx = TWIDDLE(p); p += 2; | |
4805 | lp->phy[lp->active].ttm = TWIDDLE(p); p += 2; | |
4806 | lp->phy[lp->active].mci = *p; | |
4807 | return 0; | |
4808 | } else if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4809 | lp->ibn = 3; | |
4810 | lp->active = *p; | |
4811 | if (MOTO_SROM_BUG) lp->active = 0; | |
4812 | lp->infoblock_csr6 = OMR_MII_100; | |
eb034a79 | 4813 | lp->useMII = true; |
1da177e4 LT |
4814 | lp->infoblock_media = ANS; |
4815 | ||
4816 | de4x5_switch_mac_port(dev); | |
4817 | } | |
4818 | ||
4819 | return dc2114x_autoconf(dev); | |
4820 | } | |
4821 | ||
f3b197ac | 4822 | static int |
1da177e4 LT |
4823 | type4_infoblock(struct net_device *dev, u_char count, u_char *p) |
4824 | { | |
4825 | struct de4x5_private *lp = netdev_priv(dev); | |
4826 | u_char flags, csr6, len = (*p & BLOCK_LEN)+1; | |
4827 | ||
4828 | /* Recursively figure out the info blocks */ | |
4829 | if (--count > lp->tcount) { | |
4830 | if (*(p+len) < 128) { | |
4831 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4832 | } else { | |
4833 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4834 | } | |
4835 | } | |
4836 | ||
4837 | if ((lp->media == INIT) && (lp->timeout < 0)) { | |
4838 | lp->ibn = 4; | |
4839 | lp->active = 0; | |
4840 | p+=2; | |
4841 | lp->infoblock_media = (*p++) & MEDIA_CODE; | |
4842 | lp->cache.csr13 = CSR13; /* Hard coded defaults */ | |
4843 | lp->cache.csr14 = CSR14; | |
4844 | lp->cache.csr15 = CSR15; | |
4845 | lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2; | |
4846 | lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2; | |
4847 | csr6 = *p++; | |
4848 | flags = *p++; | |
4849 | ||
4850 | lp->asBitValid = (flags & 0x80) ? 0 : -1; | |
4851 | lp->defMedium = (flags & 0x40) ? -1 : 0; | |
4852 | lp->asBit = 1 << ((csr6 >> 1) & 0x07); | |
4853 | lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit; | |
4854 | lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18); | |
eb034a79 | 4855 | lp->useMII = false; |
1da177e4 LT |
4856 | |
4857 | de4x5_switch_mac_port(dev); | |
4858 | } | |
4859 | ||
4860 | return dc2114x_autoconf(dev); | |
4861 | } | |
4862 | ||
4863 | /* | |
4864 | ** This block type provides information for resetting external devices | |
4865 | ** (chips) through the General Purpose Register. | |
4866 | */ | |
f3b197ac | 4867 | static int |
1da177e4 LT |
4868 | type5_infoblock(struct net_device *dev, u_char count, u_char *p) |
4869 | { | |
4870 | struct de4x5_private *lp = netdev_priv(dev); | |
4871 | u_char len = (*p & BLOCK_LEN)+1; | |
4872 | ||
4873 | /* Recursively figure out the info blocks */ | |
4874 | if (--count > lp->tcount) { | |
4875 | if (*(p+len) < 128) { | |
4876 | return dc_infoblock[COMPACT](dev, count, p+len); | |
4877 | } else { | |
4878 | return dc_infoblock[*(p+len+1)](dev, count, p+len); | |
4879 | } | |
4880 | } | |
4881 | ||
4882 | /* Must be initializing to run this code */ | |
4883 | if ((lp->state == INITIALISED) || (lp->media == INIT)) { | |
4884 | p+=2; | |
4885 | lp->rst = p; | |
4886 | srom_exec(dev, lp->rst); | |
4887 | } | |
4888 | ||
4889 | return DE4X5_AUTOSENSE_MS; | |
4890 | } | |
4891 | ||
4892 | /* | |
4893 | ** MII Read/Write | |
4894 | */ | |
4895 | ||
4896 | static int | |
4897 | mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr) | |
4898 | { | |
4899 | mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */ | |
4900 | mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */ | |
4901 | mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */ | |
4902 | mii_address(phyaddr, ioaddr); /* PHY address to be accessed */ | |
4903 | mii_address(phyreg, ioaddr); /* PHY Register to read */ | |
4904 | mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */ | |
f3b197ac | 4905 | |
1da177e4 LT |
4906 | return mii_rdata(ioaddr); /* Read data */ |
4907 | } | |
4908 | ||
4909 | static void | |
4910 | mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr) | |
4911 | { | |
4912 | mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */ | |
4913 | mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */ | |
4914 | mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */ | |
4915 | mii_address(phyaddr, ioaddr); /* PHY address to be accessed */ | |
4916 | mii_address(phyreg, ioaddr); /* PHY Register to write */ | |
4917 | mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */ | |
4918 | data = mii_swap(data, 16); /* Swap data bit ordering */ | |
4919 | mii_wdata(data, 16, ioaddr); /* Write data */ | |
f3b197ac | 4920 | |
1da177e4 LT |
4921 | return; |
4922 | } | |
4923 | ||
4924 | static int | |
4925 | mii_rdata(u_long ioaddr) | |
4926 | { | |
4927 | int i; | |
4928 | s32 tmp = 0; | |
f3b197ac | 4929 | |
1da177e4 LT |
4930 | for (i=0; i<16; i++) { |
4931 | tmp <<= 1; | |
4932 | tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr); | |
4933 | } | |
f3b197ac | 4934 | |
1da177e4 LT |
4935 | return tmp; |
4936 | } | |
4937 | ||
4938 | static void | |
4939 | mii_wdata(int data, int len, u_long ioaddr) | |
4940 | { | |
4941 | int i; | |
f3b197ac | 4942 | |
1da177e4 LT |
4943 | for (i=0; i<len; i++) { |
4944 | sendto_mii(MII_MWR | MII_WR, data, ioaddr); | |
4945 | data >>= 1; | |
4946 | } | |
f3b197ac | 4947 | |
1da177e4 LT |
4948 | return; |
4949 | } | |
4950 | ||
4951 | static void | |
4952 | mii_address(u_char addr, u_long ioaddr) | |
4953 | { | |
4954 | int i; | |
f3b197ac | 4955 | |
1da177e4 LT |
4956 | addr = mii_swap(addr, 5); |
4957 | for (i=0; i<5; i++) { | |
4958 | sendto_mii(MII_MWR | MII_WR, addr, ioaddr); | |
4959 | addr >>= 1; | |
4960 | } | |
f3b197ac | 4961 | |
1da177e4 LT |
4962 | return; |
4963 | } | |
4964 | ||
4965 | static void | |
4966 | mii_ta(u_long rw, u_long ioaddr) | |
4967 | { | |
4968 | if (rw == MII_STWR) { | |
f3b197ac JG |
4969 | sendto_mii(MII_MWR | MII_WR, 1, ioaddr); |
4970 | sendto_mii(MII_MWR | MII_WR, 0, ioaddr); | |
1da177e4 LT |
4971 | } else { |
4972 | getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */ | |
4973 | } | |
f3b197ac | 4974 | |
1da177e4 LT |
4975 | return; |
4976 | } | |
4977 | ||
4978 | static int | |
4979 | mii_swap(int data, int len) | |
4980 | { | |
4981 | int i, tmp = 0; | |
f3b197ac | 4982 | |
1da177e4 LT |
4983 | for (i=0; i<len; i++) { |
4984 | tmp <<= 1; | |
4985 | tmp |= (data & 1); | |
4986 | data >>= 1; | |
4987 | } | |
f3b197ac | 4988 | |
1da177e4 LT |
4989 | return tmp; |
4990 | } | |
4991 | ||
4992 | static void | |
4993 | sendto_mii(u32 command, int data, u_long ioaddr) | |
4994 | { | |
4995 | u32 j; | |
f3b197ac | 4996 | |
1da177e4 LT |
4997 | j = (data & 1) << 17; |
4998 | outl(command | j, ioaddr); | |
4999 | udelay(1); | |
5000 | outl(command | MII_MDC | j, ioaddr); | |
5001 | udelay(1); | |
f3b197ac | 5002 | |
1da177e4 LT |
5003 | return; |
5004 | } | |
5005 | ||
5006 | static int | |
5007 | getfrom_mii(u32 command, u_long ioaddr) | |
5008 | { | |
5009 | outl(command, ioaddr); | |
5010 | udelay(1); | |
5011 | outl(command | MII_MDC, ioaddr); | |
5012 | udelay(1); | |
f3b197ac | 5013 | |
1da177e4 LT |
5014 | return ((inl(ioaddr) >> 19) & 1); |
5015 | } | |
5016 | ||
5017 | /* | |
5018 | ** Here's 3 ways to calculate the OUI from the ID registers. | |
5019 | */ | |
5020 | static int | |
5021 | mii_get_oui(u_char phyaddr, u_long ioaddr) | |
5022 | { | |
5023 | /* | |
5024 | union { | |
5025 | u_short reg; | |
5026 | u_char breg[2]; | |
5027 | } a; | |
5028 | int i, r2, r3, ret=0;*/ | |
5029 | int r2, r3; | |
5030 | ||
5031 | /* Read r2 and r3 */ | |
5032 | r2 = mii_rd(MII_ID0, phyaddr, ioaddr); | |
5033 | r3 = mii_rd(MII_ID1, phyaddr, ioaddr); | |
5034 | /* SEEQ and Cypress way * / | |
5035 | / * Shuffle r2 and r3 * / | |
5036 | a.reg=0; | |
5037 | r3 = ((r3>>10)|(r2<<6))&0x0ff; | |
5038 | r2 = ((r2>>2)&0x3fff); | |
5039 | ||
5040 | / * Bit reverse r3 * / | |
5041 | for (i=0;i<8;i++) { | |
5042 | ret<<=1; | |
5043 | ret |= (r3&1); | |
5044 | r3>>=1; | |
5045 | } | |
5046 | ||
5047 | / * Bit reverse r2 * / | |
5048 | for (i=0;i<16;i++) { | |
5049 | a.reg<<=1; | |
5050 | a.reg |= (r2&1); | |
5051 | r2>>=1; | |
5052 | } | |
5053 | ||
5054 | / * Swap r2 bytes * / | |
5055 | i=a.breg[0]; | |
5056 | a.breg[0]=a.breg[1]; | |
5057 | a.breg[1]=i; | |
5058 | ||
5059 | return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */ | |
5060 | /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */ | |
5061 | return r2; /* (I did it) My way */ | |
5062 | } | |
5063 | ||
5064 | /* | |
5065 | ** The SROM spec forces us to search addresses [1-31 0]. Bummer. | |
5066 | */ | |
5067 | static int | |
5068 | mii_get_phy(struct net_device *dev) | |
5069 | { | |
5070 | struct de4x5_private *lp = netdev_priv(dev); | |
5071 | u_long iobase = dev->base_addr; | |
ff8ac609 | 5072 | int i, j, k, n, limit=ARRAY_SIZE(phy_info); |
1da177e4 | 5073 | int id; |
f3b197ac | 5074 | |
1da177e4 | 5075 | lp->active = 0; |
eb034a79 | 5076 | lp->useMII = true; |
1da177e4 LT |
5077 | |
5078 | /* Search the MII address space for possible PHY devices */ | |
5079 | for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) { | |
5080 | lp->phy[lp->active].addr = i; | |
5081 | if (i==0) n++; /* Count cycles */ | |
5082 | while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */ | |
f3b197ac | 5083 | id = mii_get_oui(i, DE4X5_MII); |
1da177e4 LT |
5084 | if ((id == 0) || (id == 65535)) continue; /* Valid ID? */ |
5085 | for (j=0; j<limit; j++) { /* Search PHY table */ | |
5086 | if (id != phy_info[j].id) continue; /* ID match? */ | |
5087 | for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++); | |
5088 | if (k < DE4X5_MAX_PHY) { | |
5089 | memcpy((char *)&lp->phy[k], | |
5090 | (char *)&phy_info[j], sizeof(struct phy_table)); | |
5091 | lp->phy[k].addr = i; | |
5092 | lp->mii_cnt++; | |
5093 | lp->active++; | |
5094 | } else { | |
5095 | goto purgatory; /* Stop the search */ | |
5096 | } | |
5097 | break; | |
5098 | } | |
5099 | if ((j == limit) && (i < DE4X5_MAX_MII)) { | |
5100 | for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++); | |
5101 | lp->phy[k].addr = i; | |
5102 | lp->phy[k].id = id; | |
5103 | lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */ | |
5104 | lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */ | |
5105 | lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */ | |
5106 | lp->mii_cnt++; | |
5107 | lp->active++; | |
5108 | printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name); | |
5109 | j = de4x5_debug; | |
5110 | de4x5_debug |= DEBUG_MII; | |
5111 | de4x5_dbg_mii(dev, k); | |
5112 | de4x5_debug = j; | |
5113 | printk("\n"); | |
5114 | } | |
5115 | } | |
5116 | purgatory: | |
5117 | lp->active = 0; | |
5118 | if (lp->phy[0].id) { /* Reset the PHY devices */ | |
5119 | for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/ | |
5120 | mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII); | |
5121 | while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST); | |
f3b197ac | 5122 | |
1da177e4 LT |
5123 | de4x5_dbg_mii(dev, k); |
5124 | } | |
5125 | } | |
eb034a79 | 5126 | if (!lp->mii_cnt) lp->useMII = false; |
1da177e4 LT |
5127 | |
5128 | return lp->mii_cnt; | |
5129 | } | |
5130 | ||
5131 | static char * | |
5132 | build_setup_frame(struct net_device *dev, int mode) | |
5133 | { | |
5134 | struct de4x5_private *lp = netdev_priv(dev); | |
5135 | int i; | |
5136 | char *pa = lp->setup_frame; | |
f3b197ac | 5137 | |
1da177e4 LT |
5138 | /* Initialise the setup frame */ |
5139 | if (mode == ALL) { | |
5140 | memset(lp->setup_frame, 0, SETUP_FRAME_LEN); | |
5141 | } | |
f3b197ac | 5142 | |
1da177e4 LT |
5143 | if (lp->setup_f == HASH_PERF) { |
5144 | for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) { | |
5145 | *(pa + i) = dev->dev_addr[i]; /* Host address */ | |
5146 | if (i & 0x01) pa += 2; | |
5147 | } | |
5148 | *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80; | |
5149 | } else { | |
5150 | for (i=0; i<ETH_ALEN; i++) { /* Host address */ | |
5151 | *(pa + (i&1)) = dev->dev_addr[i]; | |
5152 | if (i & 0x01) pa += 4; | |
5153 | } | |
5154 | for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */ | |
5155 | *(pa + (i&1)) = (char) 0xff; | |
5156 | if (i & 0x01) pa += 4; | |
5157 | } | |
5158 | } | |
f3b197ac | 5159 | |
1da177e4 LT |
5160 | return pa; /* Points to the next entry */ |
5161 | } | |
5162 | ||
5163 | static void | |
5164 | enable_ast(struct net_device *dev, u32 time_out) | |
5165 | { | |
5166 | timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out); | |
f3b197ac | 5167 | |
1da177e4 LT |
5168 | return; |
5169 | } | |
5170 | ||
5171 | static void | |
5172 | disable_ast(struct net_device *dev) | |
5173 | { | |
5174 | struct de4x5_private *lp = netdev_priv(dev); | |
f3b197ac | 5175 | |
1da177e4 | 5176 | del_timer(&lp->timer); |
f3b197ac | 5177 | |
1da177e4 LT |
5178 | return; |
5179 | } | |
5180 | ||
5181 | static long | |
5182 | de4x5_switch_mac_port(struct net_device *dev) | |
5183 | { | |
5184 | struct de4x5_private *lp = netdev_priv(dev); | |
5185 | u_long iobase = dev->base_addr; | |
5186 | s32 omr; | |
5187 | ||
5188 | STOP_DE4X5; | |
5189 | ||
5190 | /* Assert the OMR_PS bit in CSR6 */ | |
5191 | omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR | | |
5192 | OMR_FDX)); | |
5193 | omr |= lp->infoblock_csr6; | |
5194 | if (omr & OMR_PS) omr |= OMR_HBD; | |
5195 | outl(omr, DE4X5_OMR); | |
f3b197ac | 5196 | |
1da177e4 LT |
5197 | /* Soft Reset */ |
5198 | RESET_DE4X5; | |
f3b197ac | 5199 | |
1da177e4 LT |
5200 | /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */ |
5201 | if (lp->chipset == DC21140) { | |
5202 | gep_wr(lp->cache.gepc, dev); | |
5203 | gep_wr(lp->cache.gep, dev); | |
5204 | } else if ((lp->chipset & ~0x0ff) == DC2114x) { | |
5205 | reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15); | |
5206 | } | |
5207 | ||
5208 | /* Restore CSR6 */ | |
5209 | outl(omr, DE4X5_OMR); | |
5210 | ||
5211 | /* Reset CSR8 */ | |
5212 | inl(DE4X5_MFC); | |
5213 | ||
5214 | return omr; | |
5215 | } | |
5216 | ||
5217 | static void | |
5218 | gep_wr(s32 data, struct net_device *dev) | |
5219 | { | |
5220 | struct de4x5_private *lp = netdev_priv(dev); | |
5221 | u_long iobase = dev->base_addr; | |
5222 | ||
5223 | if (lp->chipset == DC21140) { | |
5224 | outl(data, DE4X5_GEP); | |
5225 | } else if ((lp->chipset & ~0x00ff) == DC2114x) { | |
5226 | outl((data<<16) | lp->cache.csr15, DE4X5_SIGR); | |
5227 | } | |
5228 | ||
5229 | return; | |
5230 | } | |
5231 | ||
5232 | static int | |
5233 | gep_rd(struct net_device *dev) | |
5234 | { | |
5235 | struct de4x5_private *lp = netdev_priv(dev); | |
5236 | u_long iobase = dev->base_addr; | |
5237 | ||
5238 | if (lp->chipset == DC21140) { | |
5239 | return inl(DE4X5_GEP); | |
5240 | } else if ((lp->chipset & ~0x00ff) == DC2114x) { | |
5241 | return (inl(DE4X5_SIGR) & 0x000fffff); | |
5242 | } | |
5243 | ||
5244 | return 0; | |
5245 | } | |
5246 | ||
5247 | static void | |
5248 | timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec) | |
5249 | { | |
5250 | struct de4x5_private *lp = netdev_priv(dev); | |
5251 | int dt; | |
f3b197ac | 5252 | |
1da177e4 LT |
5253 | /* First, cancel any pending timer events */ |
5254 | del_timer(&lp->timer); | |
f3b197ac | 5255 | |
1da177e4 LT |
5256 | /* Convert msec to ticks */ |
5257 | dt = (msec * HZ) / 1000; | |
5258 | if (dt==0) dt=1; | |
f3b197ac | 5259 | |
1da177e4 LT |
5260 | /* Set up timer */ |
5261 | init_timer(&lp->timer); | |
5262 | lp->timer.expires = jiffies + dt; | |
5263 | lp->timer.function = fn; | |
5264 | lp->timer.data = data; | |
5265 | add_timer(&lp->timer); | |
f3b197ac | 5266 | |
1da177e4 LT |
5267 | return; |
5268 | } | |
5269 | ||
5270 | static void | |
5271 | yawn(struct net_device *dev, int state) | |
5272 | { | |
5273 | struct de4x5_private *lp = netdev_priv(dev); | |
5274 | u_long iobase = dev->base_addr; | |
5275 | ||
5276 | if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return; | |
5277 | ||
5278 | if(lp->bus == EISA) { | |
5279 | switch(state) { | |
5280 | case WAKEUP: | |
5281 | outb(WAKEUP, PCI_CFPM); | |
5282 | mdelay(10); | |
5283 | break; | |
5284 | ||
5285 | case SNOOZE: | |
5286 | outb(SNOOZE, PCI_CFPM); | |
5287 | break; | |
5288 | ||
5289 | case SLEEP: | |
5290 | outl(0, DE4X5_SICR); | |
5291 | outb(SLEEP, PCI_CFPM); | |
5292 | break; | |
5293 | } | |
5294 | } else { | |
5295 | struct pci_dev *pdev = to_pci_dev (lp->gendev); | |
5296 | switch(state) { | |
5297 | case WAKEUP: | |
5298 | pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP); | |
5299 | mdelay(10); | |
5300 | break; | |
5301 | ||
5302 | case SNOOZE: | |
5303 | pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE); | |
5304 | break; | |
5305 | ||
5306 | case SLEEP: | |
5307 | outl(0, DE4X5_SICR); | |
5308 | pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP); | |
5309 | break; | |
5310 | } | |
5311 | } | |
5312 | ||
5313 | return; | |
5314 | } | |
5315 | ||
5316 | static void | |
5317 | de4x5_parse_params(struct net_device *dev) | |
5318 | { | |
5319 | struct de4x5_private *lp = netdev_priv(dev); | |
5320 | char *p, *q, t; | |
5321 | ||
5322 | lp->params.fdx = 0; | |
5323 | lp->params.autosense = AUTO; | |
5324 | ||
5325 | if (args == NULL) return; | |
5326 | ||
5327 | if ((p = strstr(args, dev->name))) { | |
5328 | if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p); | |
5329 | t = *q; | |
5330 | *q = '\0'; | |
5331 | ||
5332 | if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1; | |
5333 | ||
5334 | if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) { | |
5335 | if (strstr(p, "TP")) { | |
5336 | lp->params.autosense = TP; | |
5337 | } else if (strstr(p, "TP_NW")) { | |
5338 | lp->params.autosense = TP_NW; | |
5339 | } else if (strstr(p, "BNC")) { | |
5340 | lp->params.autosense = BNC; | |
5341 | } else if (strstr(p, "AUI")) { | |
5342 | lp->params.autosense = AUI; | |
5343 | } else if (strstr(p, "BNC_AUI")) { | |
5344 | lp->params.autosense = BNC; | |
5345 | } else if (strstr(p, "10Mb")) { | |
5346 | lp->params.autosense = _10Mb; | |
5347 | } else if (strstr(p, "100Mb")) { | |
5348 | lp->params.autosense = _100Mb; | |
5349 | } else if (strstr(p, "AUTO")) { | |
5350 | lp->params.autosense = AUTO; | |
5351 | } | |
5352 | } | |
5353 | *q = t; | |
5354 | } | |
5355 | ||
5356 | return; | |
5357 | } | |
5358 | ||
5359 | static void | |
5360 | de4x5_dbg_open(struct net_device *dev) | |
5361 | { | |
5362 | struct de4x5_private *lp = netdev_priv(dev); | |
5363 | int i; | |
f3b197ac | 5364 | |
1da177e4 LT |
5365 | if (de4x5_debug & DEBUG_OPEN) { |
5366 | printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq); | |
5367 | printk("\tphysical address: "); | |
5368 | for (i=0;i<6;i++) { | |
5369 | printk("%2.2x:",(short)dev->dev_addr[i]); | |
5370 | } | |
5371 | printk("\n"); | |
5372 | printk("Descriptor head addresses:\n"); | |
5373 | printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring); | |
5374 | printk("Descriptor addresses:\nRX: "); | |
5375 | for (i=0;i<lp->rxRingSize-1;i++){ | |
5376 | if (i < 3) { | |
5377 | printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status); | |
5378 | } | |
5379 | } | |
5380 | printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status); | |
5381 | printk("TX: "); | |
5382 | for (i=0;i<lp->txRingSize-1;i++){ | |
5383 | if (i < 3) { | |
5384 | printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status); | |
5385 | } | |
5386 | } | |
5387 | printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status); | |
5388 | printk("Descriptor buffers:\nRX: "); | |
5389 | for (i=0;i<lp->rxRingSize-1;i++){ | |
5390 | if (i < 3) { | |
5391 | printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf)); | |
5392 | } | |
5393 | } | |
5394 | printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf)); | |
5395 | printk("TX: "); | |
5396 | for (i=0;i<lp->txRingSize-1;i++){ | |
5397 | if (i < 3) { | |
5398 | printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf)); | |
5399 | } | |
5400 | } | |
5401 | printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf)); | |
f3b197ac JG |
5402 | printk("Ring size: \nRX: %d\nTX: %d\n", |
5403 | (short)lp->rxRingSize, | |
5404 | (short)lp->txRingSize); | |
1da177e4 | 5405 | } |
f3b197ac | 5406 | |
1da177e4 LT |
5407 | return; |
5408 | } | |
5409 | ||
5410 | static void | |
5411 | de4x5_dbg_mii(struct net_device *dev, int k) | |
5412 | { | |
5413 | struct de4x5_private *lp = netdev_priv(dev); | |
5414 | u_long iobase = dev->base_addr; | |
f3b197ac | 5415 | |
1da177e4 LT |
5416 | if (de4x5_debug & DEBUG_MII) { |
5417 | printk("\nMII device address: %d\n", lp->phy[k].addr); | |
5418 | printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII)); | |
5419 | printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII)); | |
5420 | printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII)); | |
5421 | printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII)); | |
5422 | if (lp->phy[k].id != BROADCOM_T4) { | |
5423 | printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII)); | |
5424 | printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII)); | |
5425 | } | |
5426 | printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII)); | |
5427 | if (lp->phy[k].id != BROADCOM_T4) { | |
5428 | printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII)); | |
5429 | printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII)); | |
5430 | } else { | |
5431 | printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII)); | |
5432 | } | |
5433 | } | |
f3b197ac | 5434 | |
1da177e4 LT |
5435 | return; |
5436 | } | |
5437 | ||
5438 | static void | |
5439 | de4x5_dbg_media(struct net_device *dev) | |
5440 | { | |
5441 | struct de4x5_private *lp = netdev_priv(dev); | |
f3b197ac | 5442 | |
1da177e4 LT |
5443 | if (lp->media != lp->c_media) { |
5444 | if (de4x5_debug & DEBUG_MEDIA) { | |
5445 | printk("%s: media is %s%s\n", dev->name, | |
5446 | (lp->media == NC ? "unconnected, link down or incompatible connection" : | |
5447 | (lp->media == TP ? "TP" : | |
5448 | (lp->media == ANS ? "TP/Nway" : | |
f3b197ac JG |
5449 | (lp->media == BNC ? "BNC" : |
5450 | (lp->media == AUI ? "AUI" : | |
5451 | (lp->media == BNC_AUI ? "BNC/AUI" : | |
5452 | (lp->media == EXT_SIA ? "EXT SIA" : | |
1da177e4 LT |
5453 | (lp->media == _100Mb ? "100Mb/s" : |
5454 | (lp->media == _10Mb ? "10Mb/s" : | |
5455 | "???" | |
5456 | ))))))))), (lp->fdx?" full duplex.":".")); | |
5457 | } | |
5458 | lp->c_media = lp->media; | |
5459 | } | |
f3b197ac | 5460 | |
1da177e4 LT |
5461 | return; |
5462 | } | |
5463 | ||
5464 | static void | |
5465 | de4x5_dbg_srom(struct de4x5_srom *p) | |
5466 | { | |
5467 | int i; | |
0795af57 | 5468 | DECLARE_MAC_BUF(mac); |
1da177e4 LT |
5469 | |
5470 | if (de4x5_debug & DEBUG_SROM) { | |
5471 | printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id)); | |
5472 | printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id)); | |
5473 | printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc)); | |
5474 | printk("SROM version: %02x\n", (u_char)(p->version)); | |
0795af57 | 5475 | printk("# controllers: %02x\n", (u_char)(p->num_controllers)); |
1da177e4 | 5476 | |
0795af57 | 5477 | printk("Hardware Address: %s\n", print_mac(mac, p->ieee_addr)); |
1da177e4 LT |
5478 | printk("CRC checksum: %04x\n", (u_short)(p->chksum)); |
5479 | for (i=0; i<64; i++) { | |
5480 | printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i)); | |
5481 | } | |
5482 | } | |
5483 | ||
5484 | return; | |
5485 | } | |
5486 | ||
5487 | static void | |
5488 | de4x5_dbg_rx(struct sk_buff *skb, int len) | |
5489 | { | |
5490 | int i, j; | |
0795af57 JP |
5491 | DECLARE_MAC_BUF(mac); |
5492 | DECLARE_MAC_BUF(mac2); | |
1da177e4 LT |
5493 | |
5494 | if (de4x5_debug & DEBUG_RX) { | |
0795af57 JP |
5495 | printk("R: %s <- %s len/SAP:%02x%02x [%d]\n", |
5496 | print_mac(mac, skb->data), print_mac(mac2, &skb->data[6]), | |
1da177e4 LT |
5497 | (u_char)skb->data[12], |
5498 | (u_char)skb->data[13], | |
5499 | len); | |
5500 | for (j=0; len>0;j+=16, len-=16) { | |
5501 | printk(" %03x: ",j); | |
5502 | for (i=0; i<16 && i<len; i++) { | |
5503 | printk("%02x ",(u_char)skb->data[i+j]); | |
5504 | } | |
5505 | printk("\n"); | |
5506 | } | |
5507 | } | |
5508 | ||
5509 | return; | |
5510 | } | |
5511 | ||
5512 | /* | |
5513 | ** Perform IOCTL call functions here. Some are privileged operations and the | |
5514 | ** effective uid is checked in those cases. In the normal course of events | |
5515 | ** this function is only used for my testing. | |
5516 | */ | |
5517 | static int | |
5518 | de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
5519 | { | |
5520 | struct de4x5_private *lp = netdev_priv(dev); | |
5521 | struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru; | |
5522 | u_long iobase = dev->base_addr; | |
5523 | int i, j, status = 0; | |
5524 | s32 omr; | |
5525 | union { | |
5526 | u8 addr[144]; | |
5527 | u16 sval[72]; | |
5528 | u32 lval[36]; | |
5529 | } tmp; | |
5530 | u_long flags = 0; | |
f3b197ac | 5531 | |
1da177e4 LT |
5532 | switch(ioc->cmd) { |
5533 | case DE4X5_GET_HWADDR: /* Get the hardware address */ | |
5534 | ioc->len = ETH_ALEN; | |
5535 | for (i=0; i<ETH_ALEN; i++) { | |
5536 | tmp.addr[i] = dev->dev_addr[i]; | |
5537 | } | |
5538 | if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; | |
5539 | break; | |
5540 | ||
5541 | case DE4X5_SET_HWADDR: /* Set the hardware address */ | |
5542 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5543 | if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT; | |
5544 | if (netif_queue_stopped(dev)) | |
5545 | return -EBUSY; | |
5546 | netif_stop_queue(dev); | |
5547 | for (i=0; i<ETH_ALEN; i++) { | |
5548 | dev->dev_addr[i] = tmp.addr[i]; | |
5549 | } | |
5550 | build_setup_frame(dev, PHYS_ADDR_ONLY); | |
5551 | /* Set up the descriptor and give ownership to the card */ | |
f3b197ac | 5552 | load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET | |
1da177e4 LT |
5553 | SETUP_FRAME_LEN, (struct sk_buff *)1); |
5554 | lp->tx_new = (++lp->tx_new) % lp->txRingSize; | |
5555 | outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */ | |
5556 | netif_wake_queue(dev); /* Unlock the TX ring */ | |
5557 | break; | |
5558 | ||
5559 | case DE4X5_SET_PROM: /* Set Promiscuous Mode */ | |
5560 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5561 | omr = inl(DE4X5_OMR); | |
5562 | omr |= OMR_PR; | |
5563 | outl(omr, DE4X5_OMR); | |
5564 | dev->flags |= IFF_PROMISC; | |
5565 | break; | |
5566 | ||
5567 | case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */ | |
5568 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5569 | omr = inl(DE4X5_OMR); | |
5570 | omr &= ~OMR_PR; | |
5571 | outl(omr, DE4X5_OMR); | |
5572 | dev->flags &= ~IFF_PROMISC; | |
5573 | break; | |
5574 | ||
5575 | case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */ | |
5576 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5577 | printk("%s: Boo!\n", dev->name); | |
5578 | break; | |
5579 | ||
5580 | case DE4X5_MCA_EN: /* Enable pass all multicast addressing */ | |
5581 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5582 | omr = inl(DE4X5_OMR); | |
5583 | omr |= OMR_PM; | |
5584 | outl(omr, DE4X5_OMR); | |
5585 | break; | |
5586 | ||
5587 | case DE4X5_GET_STATS: /* Get the driver statistics */ | |
5588 | { | |
5589 | struct pkt_stats statbuf; | |
5590 | ioc->len = sizeof(statbuf); | |
5591 | spin_lock_irqsave(&lp->lock, flags); | |
5592 | memcpy(&statbuf, &lp->pktStats, ioc->len); | |
5593 | spin_unlock_irqrestore(&lp->lock, flags); | |
f3b197ac JG |
5594 | if (copy_to_user(ioc->data, &statbuf, ioc->len)) |
5595 | return -EFAULT; | |
1da177e4 LT |
5596 | break; |
5597 | } | |
5598 | case DE4X5_CLR_STATS: /* Zero out the driver statistics */ | |
5599 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5600 | spin_lock_irqsave(&lp->lock, flags); | |
5601 | memset(&lp->pktStats, 0, sizeof(lp->pktStats)); | |
5602 | spin_unlock_irqrestore(&lp->lock, flags); | |
5603 | break; | |
5604 | ||
5605 | case DE4X5_GET_OMR: /* Get the OMR Register contents */ | |
5606 | tmp.addr[0] = inl(DE4X5_OMR); | |
5607 | if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT; | |
5608 | break; | |
5609 | ||
5610 | case DE4X5_SET_OMR: /* Set the OMR Register contents */ | |
5611 | if (!capable(CAP_NET_ADMIN)) return -EPERM; | |
5612 | if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT; | |
5613 | outl(tmp.addr[0], DE4X5_OMR); | |
5614 | break; | |
5615 | ||
5616 | case DE4X5_GET_REG: /* Get the DE4X5 Registers */ | |
5617 | j = 0; | |
5618 | tmp.lval[0] = inl(DE4X5_STS); j+=4; | |
5619 | tmp.lval[1] = inl(DE4X5_BMR); j+=4; | |
5620 | tmp.lval[2] = inl(DE4X5_IMR); j+=4; | |
5621 | tmp.lval[3] = inl(DE4X5_OMR); j+=4; | |
5622 | tmp.lval[4] = inl(DE4X5_SISR); j+=4; | |
5623 | tmp.lval[5] = inl(DE4X5_SICR); j+=4; | |
5624 | tmp.lval[6] = inl(DE4X5_STRR); j+=4; | |
5625 | tmp.lval[7] = inl(DE4X5_SIGR); j+=4; | |
5626 | ioc->len = j; | |
5627 | if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; | |
5628 | break; | |
f3b197ac | 5629 | |
1da177e4 | 5630 | #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */ |
f3b197ac | 5631 | /* |
1da177e4 LT |
5632 | case DE4X5_DUMP: |
5633 | j = 0; | |
5634 | tmp.addr[j++] = dev->irq; | |
5635 | for (i=0; i<ETH_ALEN; i++) { | |
5636 | tmp.addr[j++] = dev->dev_addr[i]; | |
5637 | } | |
5638 | tmp.addr[j++] = lp->rxRingSize; | |
5639 | tmp.lval[j>>2] = (long)lp->rx_ring; j+=4; | |
5640 | tmp.lval[j>>2] = (long)lp->tx_ring; j+=4; | |
f3b197ac | 5641 | |
1da177e4 LT |
5642 | for (i=0;i<lp->rxRingSize-1;i++){ |
5643 | if (i < 3) { | |
5644 | tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; | |
5645 | } | |
5646 | } | |
5647 | tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4; | |
5648 | for (i=0;i<lp->txRingSize-1;i++){ | |
5649 | if (i < 3) { | |
5650 | tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; | |
5651 | } | |
5652 | } | |
5653 | tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4; | |
f3b197ac | 5654 | |
1da177e4 LT |
5655 | for (i=0;i<lp->rxRingSize-1;i++){ |
5656 | if (i < 3) { | |
5657 | tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; | |
5658 | } | |
5659 | } | |
5660 | tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4; | |
5661 | for (i=0;i<lp->txRingSize-1;i++){ | |
5662 | if (i < 3) { | |
5663 | tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; | |
5664 | } | |
5665 | } | |
5666 | tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4; | |
f3b197ac | 5667 | |
1da177e4 LT |
5668 | for (i=0;i<lp->rxRingSize;i++){ |
5669 | tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4; | |
5670 | } | |
5671 | for (i=0;i<lp->txRingSize;i++){ | |
5672 | tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4; | |
5673 | } | |
f3b197ac | 5674 | |
1da177e4 LT |
5675 | tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4; |
5676 | tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4; | |
5677 | tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4; | |
5678 | tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4; | |
5679 | tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4; | |
5680 | tmp.lval[j>>2] = inl(DE4X5_STS); j+=4; | |
5681 | tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4; | |
5682 | tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4; | |
f3b197ac | 5683 | tmp.lval[j>>2] = lp->chipset; j+=4; |
1da177e4 LT |
5684 | if (lp->chipset == DC21140) { |
5685 | tmp.lval[j>>2] = gep_rd(dev); j+=4; | |
5686 | } else { | |
5687 | tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4; | |
5688 | tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4; | |
5689 | tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4; | |
f3b197ac | 5690 | tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4; |
1da177e4 | 5691 | } |
f3b197ac | 5692 | tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4; |
1da177e4 | 5693 | if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) { |
f3b197ac | 5694 | tmp.lval[j>>2] = lp->active; j+=4; |
1da177e4 LT |
5695 | tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; |
5696 | tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5697 | tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5698 | tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5699 | if (lp->phy[lp->active].id != BROADCOM_T4) { | |
5700 | tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5701 | tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5702 | } | |
5703 | tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5704 | if (lp->phy[lp->active].id != BROADCOM_T4) { | |
5705 | tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5706 | tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5707 | } else { | |
5708 | tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4; | |
5709 | } | |
5710 | } | |
f3b197ac | 5711 | |
1da177e4 LT |
5712 | tmp.addr[j++] = lp->txRingSize; |
5713 | tmp.addr[j++] = netif_queue_stopped(dev); | |
f3b197ac | 5714 | |
1da177e4 LT |
5715 | ioc->len = j; |
5716 | if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT; | |
5717 | break; | |
5718 | ||
5719 | */ | |
5720 | default: | |
5721 | return -EOPNOTSUPP; | |
5722 | } | |
f3b197ac | 5723 | |
1da177e4 LT |
5724 | return status; |
5725 | } | |
5726 | ||
5727 | static int __init de4x5_module_init (void) | |
5728 | { | |
5729 | int err = 0; | |
5730 | ||
5731 | #ifdef CONFIG_PCI | |
29917620 | 5732 | err = pci_register_driver(&de4x5_pci_driver); |
1da177e4 LT |
5733 | #endif |
5734 | #ifdef CONFIG_EISA | |
5735 | err |= eisa_driver_register (&de4x5_eisa_driver); | |
5736 | #endif | |
5737 | ||
5738 | return err; | |
5739 | } | |
5740 | ||
5741 | static void __exit de4x5_module_exit (void) | |
5742 | { | |
5743 | #ifdef CONFIG_PCI | |
5744 | pci_unregister_driver (&de4x5_pci_driver); | |
5745 | #endif | |
5746 | #ifdef CONFIG_EISA | |
5747 | eisa_driver_unregister (&de4x5_eisa_driver); | |
5748 | #endif | |
5749 | } | |
5750 | ||
5751 | module_init (de4x5_module_init); | |
5752 | module_exit (de4x5_module_exit); |