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drivers/net: Remove deprecated use of pci_module_init()
[net-next-2.6.git] / drivers / net / tulip / de4x5.c
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1da177e4
LT		 1/* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
3
4 Copyright 1994, 1995 Digital Equipment Corporation.
5
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
8
9 The author may be reached at davies@maniac.ultranet.com.
10
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
15
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
30
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
33
34 DE425 TP/COAX EISA
35 DE434 TP PCI
36 DE435 TP/COAX/AUI PCI
37 DE450 TP/COAX/AUI PCI
38 DE500 10/100 PCI Fasternet
39
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
43
f3b197ac
JG		 44 DC21040 (no SROM)
45 DC21041[A]
46 DC21140[A]
47 DC21142
48 DC21143
1da177e4
LT		 49
50 So far the driver is known to work with the following cards:
51
52 KINGSTON
53 Linksys
54 ZNYX342
55 SMC8432
56 SMC9332 (w/new SROM)
57 ZNYX31[45]
f3b197ac 58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
1da177e4
LT		 59
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
63
64 TCP UDP
65 TX RX TX RX
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
70
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
74
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
81
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
86
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
90 address.
91
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
98
99 To utilise this ability, you have to do 8 things:
100
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
103 temporary directory.
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
106 loading by:
107
108 insmod de4x5 io=0xghh where g = bus number
f3b197ac 109 hh = device number
1da177e4
LT		 110
111 NB: autoprobing for modules is now supported by default. You may just
112 use:
113
114 insmod de4x5
115
116 to load all available boards. For a specific board, still use
117 the 'io=?' above.
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
f3b197ac
JG		 123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
1da177e4
LT		 125 7) enjoy!
126
f3b197ac 127 To unload a module, turn off the associated interface(s)
1da177e4
LT		 128 'ifconfig eth?? down' then 'rmmod de4x5'.
129
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
134
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
f3b197ac 138 'dec_only=1' parameter.
1da177e4
LT		 139
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
146
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
149
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
153
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
158
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
168 wired IRQs.
169
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
182
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
189 limitation.
190
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
198
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
205
206 fdx for full duplex
f3b197ac 207 autosense to set the media/speed; with the following
1da177e4
LT		 208 sub-parameters:
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
210
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
213
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
215
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
218
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
227
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
237
f3b197ac 238 TO DO:
1da177e4
LT		 239 ------
240
241 Revision History
242 ----------------
243
244 Version Date Description
f3b197ac 245
1da177e4
LT		 246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
f3b197ac 254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
1da177e4
LT		 255 Fix missed frame counter value and initialisation.
256 Fixed EISA probe.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
264 Portability changes.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
f3b197ac 283 Add new autosense algorithms for media/mode
1da177e4
LT		 284 selection using kernel scheduling/timing.
285 Re-formatted.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
1fb9df5d 295 Duh, put the IRQF_SHARED flag into request_interrupt().
1da177e4
LT		 296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
f3b197ac 310 reported by <koen.gadeyne@barco.com> and
1da177e4
LT		 311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
f3b197ac 313 reported by <csd@microplex.com> and
1da177e4
LT		 314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
f3b197ac 325 0.45 8-Dec-96 Include endian functions for PPC use, from work
1da177e4
LT		 326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
330 Updated debug flags.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
340 <paubert@iram.es>
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
346 <paubert@iram.es>.
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
f3b197ac
JG		 349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
1da177e4
LT		 351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
353 infoblocks.
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
1fb9df5d 356 Added IRQF_DISABLED temporary fix from
1da177e4
LT		 357 <mjacob@feral.com>.
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
364 direction.
365 Completed DC2114[23] autosense functions.
f3b197ac 366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
1da177e4
LT		 367 <robin@intercore.com
368 Fix type1_infoblock() bug introduced in 0.53, from
f3b197ac 369 problem reports by
1da177e4
LT		 370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
375 newer PHY chips.
376 Fix the mess in 2.1.67.
f3b197ac 377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
1da177e4
LT		 378 <redhat@cococo.net>.
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
396 <earl@exis.net>.
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
f3b197ac 401 Fix is_anc_capable() bug reported by
1da177e4
LT		 402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
f3b197ac 416 kernels and modules from bug report by
1da177e4
LT		 417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
f3b197ac 428 0.545 28-Nov-99 Further Moto SROM bug fix from
1da177e4
LT		 429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
f3b197ac
JG		 437 present.
438 <france@handhelds.org>
1da177e4
LT		 439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
444*/
445
1da177e4
LT		 446#include <linux/module.h>
447#include <linux/kernel.h>
448#include <linux/string.h>
449#include <linux/interrupt.h>
450#include <linux/ptrace.h>
451#include <linux/errno.h>
452#include <linux/ioport.h>
453#include <linux/slab.h>
454#include <linux/pci.h>
455#include <linux/eisa.h>
456#include <linux/delay.h>
457#include <linux/init.h>
458#include <linux/spinlock.h>
459#include <linux/crc32.h>
460#include <linux/netdevice.h>
461#include <linux/etherdevice.h>
462#include <linux/skbuff.h>
463#include <linux/time.h>
464#include <linux/types.h>
465#include <linux/unistd.h>
466#include <linux/ctype.h>
467#include <linux/dma-mapping.h>
468#include <linux/moduleparam.h>
469#include <linux/bitops.h>
470
471#include <asm/io.h>
472#include <asm/dma.h>
473#include <asm/byteorder.h>
474#include <asm/unaligned.h>
475#include <asm/uaccess.h>
476#ifdef CONFIG_PPC_MULTIPLATFORM
477#include <asm/machdep.h>
478#endif /* CONFIG_PPC_MULTIPLATFORM */
479
480#include "de4x5.h"
481
482static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
483
484#define c_char const char
485#define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
486
487/*
488** MII Information
489*/
490struct phy_table {
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
495 int reg;
496 int mask;
497 int value;
498 } spd;
499};
500
501struct mii_phy {
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
506 int reg;
507 int mask;
508 int value;
509 } spd;
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
7f927fcc 515 u_int fdx; /* Full DupleX capabilities for each media */
1da177e4
LT		 516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
518};
519
520#define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
521
522struct sia_phy {
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
530};
531
532/*
533** Define the know universe of PHY devices that can be
534** recognised by this driver.
535*/
536static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
542};
543
544/*
545** These GENERIC values assumes that the PHY devices follow 802.3u and
546** allow parallel detection to set the link partner ability register.
547** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
548*/
549#define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550#define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551#define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
552
553/*
554** Define special SROM detection cases
555*/
556static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
559};
560
561#define SMC 1
562#define ACCTON 2
563
564/*
565** SROM Repair definitions. If a broken SROM is detected a card may
566** use this information to help figure out what to do. This is a
567** "stab in the dark" and so far for SMC9332's only.
568*/
569static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
573 0x00,0x18,}
574};
575
576
577#ifdef DE4X5_DEBUG
578static int de4x5_debug = DE4X5_DEBUG;
579#else
580/*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
582#endif
583
584/*
585** Allow per adapter set up. For modules this is simply a command line
f3b197ac 586** parameter, e.g.:
1da177e4
LT		 587** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
588**
589** For a compiled in driver, place e.g.
590** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
591** here
592*/
593#ifdef DE4X5_PARM
594static char *args = DE4X5_PARM;
595#else
596static char *args;
597#endif
598
599struct parameters {
600 int fdx;
601 int autosense;
602};
603
604#define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
605
606#define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
607
608/*
609** Ethernet PROM defines
610*/
611#define PROBE_LENGTH 32
612#define ETH_PROM_SIG 0xAA5500FFUL
613
614/*
615** Ethernet Info
616*/
617#define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618#define IEEE802_3_SZ 1518 /* Packet + CRC */
619#define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620#define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621#define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622#define PKT_HDR_LEN 14 /* Addresses and data length info */
623#define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624#define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
625
626
627/*
628** EISA bus defines
629*/
630#define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631#define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
632
633#define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
634
635#define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636#define DE4X5_NAME_LENGTH 8
637
638static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
639
640/*
641** Ethernet PROM defines for DC21040
642*/
643#define PROBE_LENGTH 32
644#define ETH_PROM_SIG 0xAA5500FFUL
645
646/*
647** PCI Bus defines
648*/
649#define PCI_MAX_BUS_NUM 8
650#define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651#define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
652
653/*
654** Memory Alignment. Each descriptor is 4 longwords long. To force a
655** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656** DESC_ALIGN. ALIGN aligns the start address of the private memory area
f3b197ac 657** and hence the RX descriptor ring's first entry.
1da177e4
LT		 658*/
659#define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660#define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661#define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662#define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663#define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664#define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
665
666#define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667#define DE4X5_CACHE_ALIGN CAL_16LONG
668#define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669/*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
670#define DESC_ALIGN
671
672#ifndef DEC_ONLY /* See README.de4x5 for using this */
673static int dec_only;
674#else
675static int dec_only = 1;
676#endif
677
678/*
679** DE4X5 IRQ ENABLE/DISABLE
680*/
681#define ENABLE_IRQs { \
682 imr |= lp->irq_en;\
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
684}
685
686#define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
688 imr &= ~lp->irq_en;\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
690}
691
692#define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
695}
696
697#define MASK_IRQs {\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
701}
702
703/*
704** DE4X5 START/STOP
705*/
706#define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
710}
711
712#define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
716}
717
718/*
719** DE4X5 SIA RESET
720*/
721#define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
722
723/*
724** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
725*/
726#define DE4X5_AUTOSENSE_MS 250
727
728/*
729** SROM Structure
730*/
731struct de4x5_srom {
732 char sub_vendor_id[2];
733 char sub_system_id[2];
734 char reserved[12];
735 char id_block_crc;
736 char reserved2;
737 char version;
738 char num_controllers;
739 char ieee_addr[6];
740 char info[100];
741 short chksum;
742};
743#define SUB_VENDOR_ID 0x500a
744
745/*
746** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747** and have sizes of both a power of 2 and a multiple of 4.
748** A size of 256 bytes for each buffer could be chosen because over 90% of
749** all packets in our network are <256 bytes long and 64 longword alignment
750** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751** descriptors are needed for machines with an ALPHA CPU.
752*/
753#define NUM_RX_DESC 8 /* Number of RX descriptors */
754#define NUM_TX_DESC 32 /* Number of TX descriptors */
755#define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
758struct de4x5_desc {
759 volatile s32 status;
760 u32 des1;
761 u32 buf;
762 u32 next;
763 DESC_ALIGN
764};
765
766/*
767** The DE4X5 private structure
768*/
769#define DE4X5_PKT_STAT_SZ 16
770#define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
772
773struct pkt_stats {
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
775 u_int unicast;
776 u_int multicast;
777 u_int broadcast;
778 u_int excessive_collisions;
779 u_int tx_underruns;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
782 u_int rx_collision;
783 u_int rx_dribble;
784 u_int rx_overflow;
785};
786
787struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
801 char rxRingSize;
802 char txRingSize;
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 int fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 int tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
825 struct {
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff *skb; /* Save the (re-ordered) skb's */
837 } cache;
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 int useSROM; /* For non-DEC card use SROM */
842 int useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
860};
861
862/*
863** To get around certain poxy cards that don't provide an SROM
864** for the second and more DECchip, I have to key off the first
865** chip's address. I'll assume there's not a bad SROM iff:
866**
867** o the chipset is the same
868** o the bus number is the same and > 0
869** o the sum of all the returned hw address bytes is 0 or 0x5fa
870**
871** Also have to save the irq for those cards whose hardware designers
872** can't follow the PCI to PCI Bridge Architecture spec.
873*/
874static struct {
875 int chipset;
876 int bus;
877 int irq;
878 u_char addr[ETH_ALEN];
879} last = {0,};
880
881/*
882** The transmit ring full condition is described by the tx_old and tx_new
883** pointers by:
884** tx_old = tx_new Empty ring
885** tx_old = tx_new+1 Full ring
886** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
887*/
888#define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
891
892#define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
893
894/*
895** Public Functions
896*/
897static int de4x5_open(struct net_device *dev);
898static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899static irqreturn_t de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs);
900static int de4x5_close(struct net_device *dev);
901static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903static void set_multicast_list(struct net_device *dev);
904static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
905
906/*
907** Private functions
908*/
909static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910static int de4x5_init(struct net_device *dev);
911static int de4x5_sw_reset(struct net_device *dev);
912static int de4x5_rx(struct net_device *dev);
913static int de4x5_tx(struct net_device *dev);
914static int de4x5_ast(struct net_device *dev);
915static int de4x5_txur(struct net_device *dev);
916static int de4x5_rx_ovfc(struct net_device *dev);
917
918static int autoconf_media(struct net_device *dev);
919static void create_packet(struct net_device *dev, char *frame, int len);
920static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921static int dc21040_autoconf(struct net_device *dev);
922static int dc21041_autoconf(struct net_device *dev);
923static int dc21140m_autoconf(struct net_device *dev);
924static int dc2114x_autoconf(struct net_device *dev);
925static int srom_autoconf(struct net_device *dev);
926static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929static int test_for_100Mb(struct net_device *dev, int msec);
930static int wait_for_link(struct net_device *dev);
931static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
932static int is_spd_100(struct net_device *dev);
933static int is_100_up(struct net_device *dev);
934static int is_10_up(struct net_device *dev);
935static int is_anc_capable(struct net_device *dev);
936static int ping_media(struct net_device *dev, int msec);
937static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938static void de4x5_free_rx_buffs(struct net_device *dev);
939static void de4x5_free_tx_buffs(struct net_device *dev);
940static void de4x5_save_skbs(struct net_device *dev);
941static void de4x5_rst_desc_ring(struct net_device *dev);
942static void de4x5_cache_state(struct net_device *dev, int flag);
943static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946static void de4x5_setup_intr(struct net_device *dev);
947static void de4x5_init_connection(struct net_device *dev);
948static int de4x5_reset_phy(struct net_device *dev);
949static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951static int test_tp(struct net_device *dev, s32 msec);
952static int EISA_signature(char *name, struct device *device);
953static int PCI_signature(char *name, struct de4x5_private *lp);
954static void DevicePresent(struct net_device *dev, u_long iobase);
955static void enet_addr_rst(u_long aprom_addr);
956static int de4x5_bad_srom(struct de4x5_private *lp);
957static short srom_rd(u_long address, u_char offset);
958static void srom_latch(u_int command, u_long address);
959static void srom_command(u_int command, u_long address);
960static void srom_address(u_int command, u_long address, u_char offset);
961static short srom_data(u_int command, u_long address);
962/*static void srom_busy(u_int command, u_long address);*/
963static void sendto_srom(u_int command, u_long addr);
964static int getfrom_srom(u_long addr);
965static int srom_map_media(struct net_device *dev);
966static int srom_infoleaf_info(struct net_device *dev);
967static void srom_init(struct net_device *dev);
968static void srom_exec(struct net_device *dev, u_char *p);
969static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971static int mii_rdata(u_long ioaddr);
972static void mii_wdata(int data, int len, u_long ioaddr);
973static void mii_ta(u_long rw, u_long ioaddr);
974static int mii_swap(int data, int len);
975static void mii_address(u_char addr, u_long ioaddr);
976static void sendto_mii(u32 command, int data, u_long ioaddr);
977static int getfrom_mii(u32 command, u_long ioaddr);
978static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979static int mii_get_phy(struct net_device *dev);
980static void SetMulticastFilter(struct net_device *dev);
981static int get_hw_addr(struct net_device *dev);
982static void srom_repair(struct net_device *dev, int card);
983static int test_bad_enet(struct net_device *dev, int status);
984static int an_exception(struct de4x5_private *lp);
985static char *build_setup_frame(struct net_device *dev, int mode);
986static void disable_ast(struct net_device *dev);
987static void enable_ast(struct net_device *dev, u32 time_out);
988static long de4x5_switch_mac_port(struct net_device *dev);
989static int gep_rd(struct net_device *dev);
990static void gep_wr(s32 data, struct net_device *dev);
991static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
992static void yawn(struct net_device *dev, int state);
993static void de4x5_parse_params(struct net_device *dev);
994static void de4x5_dbg_open(struct net_device *dev);
995static void de4x5_dbg_mii(struct net_device *dev, int k);
996static void de4x5_dbg_media(struct net_device *dev);
997static void de4x5_dbg_srom(struct de4x5_srom *p);
998static void de4x5_dbg_rx(struct sk_buff *skb, int len);
999static int de4x5_strncmp(char *a, char *b, int n);
1000static int dc21041_infoleaf(struct net_device *dev);
1001static int dc21140_infoleaf(struct net_device *dev);
1002static int dc21142_infoleaf(struct net_device *dev);
1003static int dc21143_infoleaf(struct net_device *dev);
1004static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1005static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1006static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1007static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1008static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1009static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1010static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1011
1012/*
1013** Note now that module autoprobing is allowed under EISA and PCI. The
1014** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1015** to "do the right thing".
1016*/
1017
1018static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1019
1020module_param(io, int, 0);
1021module_param(de4x5_debug, int, 0);
1022module_param(dec_only, int, 0);
1023module_param(args, charp, 0);
1024
1025MODULE_PARM_DESC(io, "de4x5 I/O base address");
1026MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1027MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1028MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1029MODULE_LICENSE("GPL");
1030
1031/*
1032** List the SROM infoleaf functions and chipsets
1033*/
1034struct InfoLeaf {
1035 int chipset;
1036 int (*fn)(struct net_device *);
1037};
1038static struct InfoLeaf infoleaf_array[] = {
1039 {DC21041, dc21041_infoleaf},
1040 {DC21140, dc21140_infoleaf},
1041 {DC21142, dc21142_infoleaf},
1042 {DC21143, dc21143_infoleaf}
1043};
1044#define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1045
1046/*
1047** List the SROM info block functions
1048*/
1049static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1050 type0_infoblock,
1051 type1_infoblock,
1052 type2_infoblock,
1053 type3_infoblock,
1054 type4_infoblock,
1055 type5_infoblock,
1056 compact_infoblock
1057};
1058
1059#define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1060
1061/*
1062** Miscellaneous defines...
1063*/
1064#define RESET_DE4X5 {\
1065 int i;\
1066 i=inl(DE4X5_BMR);\
1067 mdelay(1);\
1068 outl(i | BMR_SWR, DE4X5_BMR);\
1069 mdelay(1);\
1070 outl(i, DE4X5_BMR);\
1071 mdelay(1);\
1072 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1073 mdelay(1);\
1074}
1075
1076#define PHY_HARD_RESET {\
1077 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1078 mdelay(1); /* Assert for 1ms */\
1079 outl(0x00, DE4X5_GEP);\
1080 mdelay(2); /* Wait for 2ms */\
1081}
1082
f3b197ac
JG		 1083
1084static int __devinit
1da177e4
LT		 1085de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1086{
1087 char name[DE4X5_NAME_LENGTH + 1];
1088 struct de4x5_private *lp = netdev_priv(dev);
1089 struct pci_dev *pdev = NULL;
1090 int i, status=0;
1091
1092 gendev->driver_data = dev;
1093
1094 /* Ensure we're not sleeping */
1095 if (lp->bus == EISA) {
1096 outb(WAKEUP, PCI_CFPM);
1097 } else {
1098 pdev = to_pci_dev (gendev);
1099 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1100 }
1101 mdelay(10);
1102
1103 RESET_DE4X5;
f3b197ac 1104
1da177e4
LT		 1105 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1106 return -ENXIO; /* Hardware could not reset */
1107 }
f3b197ac
JG		 1108
1109 /*
1da177e4
LT		 1110 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1111 */
1112 lp->useSROM = FALSE;
1113 if (lp->bus == PCI) {
1114 PCI_signature(name, lp);
1115 } else {
1116 EISA_signature(name, gendev);
1117 }
f3b197ac 1118
1da177e4
LT		 1119 if (*name == '\0') { /* Not found a board signature */
1120 return -ENXIO;
1121 }
f3b197ac 1122
1da177e4
LT		 1123 dev->base_addr = iobase;
1124 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
f3b197ac 1125
1da177e4
LT		 1126 printk(", h/w address ");
1127 status = get_hw_addr(dev);
1128 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1129 printk("%2.2x:", dev->dev_addr[i]);
1130 }
1131 printk("%2.2x,\n", dev->dev_addr[i]);
f3b197ac 1132
1da177e4
LT		 1133 if (status != 0) {
1134 printk(" which has an Ethernet PROM CRC error.\n");
1135 return -ENXIO;
1136 } else {
1137 lp->cache.gepc = GEP_INIT;
1138 lp->asBit = GEP_SLNK;
1139 lp->asPolarity = GEP_SLNK;
1140 lp->asBitValid = TRUE;
1141 lp->timeout = -1;
1142 lp->gendev = gendev;
1143 spin_lock_init(&lp->lock);
1144 init_timer(&lp->timer);
1145 de4x5_parse_params(dev);
1146
1147 /*
1148 ** Choose correct autosensing in case someone messed up
1149 */
1150 lp->autosense = lp->params.autosense;
1151 if (lp->chipset != DC21140) {
1152 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1153 lp->params.autosense = TP;
1154 }
1155 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1156 lp->params.autosense = BNC;
1157 }
1158 }
1159 lp->fdx = lp->params.fdx;
1160 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1161
1162 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1163#if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1164 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1165#endif
1166 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1167 &lp->dma_rings, GFP_ATOMIC);
1168 if (lp->rx_ring == NULL) {
1169 return -ENOMEM;
1170 }
1171
1172 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
f3b197ac 1173
1da177e4
LT		 1174 /*
1175 ** Set up the RX descriptor ring (Intels)
f3b197ac 1176 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1da177e4
LT		 1177 */
1178#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1179 for (i=0; i<NUM_RX_DESC; i++) {
1180 lp->rx_ring[i].status = 0;
1181 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1182 lp->rx_ring[i].buf = 0;
1183 lp->rx_ring[i].next = 0;
1184 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1185 }
1186
1187#else
1188 {
1189 dma_addr_t dma_rx_bufs;
1190
1191 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1192 * sizeof(struct de4x5_desc);
1193 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1194 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1195 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1196 for (i=0; i<NUM_RX_DESC; i++) {
1197 lp->rx_ring[i].status = 0;
1198 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1199 lp->rx_ring[i].buf =
1200 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1201 lp->rx_ring[i].next = 0;
1202 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1203 }
1204
1205 }
1206#endif
1207
1208 barrier();
1209
1210 lp->rxRingSize = NUM_RX_DESC;
1211 lp->txRingSize = NUM_TX_DESC;
f3b197ac 1212
1da177e4
LT		 1213 /* Write the end of list marker to the descriptor lists */
1214 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1215 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1216
1217 /* Tell the adapter where the TX/RX rings are located. */
1218 outl(lp->dma_rings, DE4X5_RRBA);
1219 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1220 DE4X5_TRBA);
f3b197ac 1221
1da177e4
LT		 1222 /* Initialise the IRQ mask and Enable/Disable */
1223 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1224 lp->irq_en = IMR_NIM | IMR_AIM;
1225
1226 /* Create a loopback packet frame for later media probing */
1227 create_packet(dev, lp->frame, sizeof(lp->frame));
1228
1229 /* Check if the RX overflow bug needs testing for */
1230 i = lp->cfrv & 0x000000fe;
1231 if ((lp->chipset == DC21140) && (i == 0x20)) {
1232 lp->rx_ovf = 1;
1233 }
1234
1235 /* Initialise the SROM pointers if possible */
1236 if (lp->useSROM) {
1237 lp->state = INITIALISED;
1238 if (srom_infoleaf_info(dev)) {
1239 dma_free_coherent (gendev, lp->dma_size,
1240 lp->rx_ring, lp->dma_rings);
1241 return -ENXIO;
1242 }
1243 srom_init(dev);
1244 }
1245
1246 lp->state = CLOSED;
1247
1248 /*
1249 ** Check for an MII interface
1250 */
1251 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1252 mii_get_phy(dev);
1253 }
f3b197ac 1254
1da177e4
LT		 1255#ifndef __sparc_v9__
1256 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1257#else
1258 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1259#endif
1260 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1261 }
f3b197ac 1262
1da177e4
LT		 1263 if (de4x5_debug & DEBUG_VERSION) {
1264 printk(version);
1265 }
f3b197ac 1266
1da177e4
LT		 1267 /* The DE4X5-specific entries in the device structure. */
1268 SET_MODULE_OWNER(dev);
1269 SET_NETDEV_DEV(dev, gendev);
1270 dev->open = &de4x5_open;
1271 dev->hard_start_xmit = &de4x5_queue_pkt;
1272 dev->stop = &de4x5_close;
1273 dev->get_stats = &de4x5_get_stats;
1274 dev->set_multicast_list = &set_multicast_list;
1275 dev->do_ioctl = &de4x5_ioctl;
f3b197ac 1276
1da177e4 1277 dev->mem_start = 0;
f3b197ac 1278
1da177e4
LT		 1279 /* Fill in the generic fields of the device structure. */
1280 if ((status = register_netdev (dev))) {
1281 dma_free_coherent (gendev, lp->dma_size,
1282 lp->rx_ring, lp->dma_rings);
1283 return status;
1284 }
f3b197ac 1285
1da177e4
LT		 1286 /* Let the adapter sleep to save power */
1287 yawn(dev, SLEEP);
f3b197ac 1288
1da177e4
LT		 1289 return status;
1290}
1291
f3b197ac 1292
1da177e4
LT		 1293static int
1294de4x5_open(struct net_device *dev)
1295{
1296 struct de4x5_private *lp = netdev_priv(dev);
1297 u_long iobase = dev->base_addr;
1298 int i, status = 0;
1299 s32 omr;
1300
1301 /* Allocate the RX buffers */
1302 for (i=0; i<lp->rxRingSize; i++) {
1303 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1304 de4x5_free_rx_buffs(dev);
1305 return -EAGAIN;
1306 }
1307 }
1308
1309 /*
1310 ** Wake up the adapter
1311 */
1312 yawn(dev, WAKEUP);
1313
f3b197ac
JG		 1314 /*
1315 ** Re-initialize the DE4X5...
1da177e4
LT		 1316 */
1317 status = de4x5_init(dev);
1318 spin_lock_init(&lp->lock);
1319 lp->state = OPEN;
1320 de4x5_dbg_open(dev);
f3b197ac 1321
1fb9df5d 1322 if (request_irq(dev->irq, (void *)de4x5_interrupt, IRQF_SHARED,
1da177e4
LT		 1323 lp->adapter_name, dev)) {
1324 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1fb9df5d 1325 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1da177e4
LT		 1326 lp->adapter_name, dev)) {
1327 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1328 disable_ast(dev);
1329 de4x5_free_rx_buffs(dev);
1330 de4x5_free_tx_buffs(dev);
1331 yawn(dev, SLEEP);
1332 lp->state = CLOSED;
1333 return -EAGAIN;
1334 } else {
1335 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1336 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1337 }
1338 }
1339
1340 lp->interrupt = UNMASK_INTERRUPTS;
1341 dev->trans_start = jiffies;
f3b197ac 1342
1da177e4 1343 START_DE4X5;
f3b197ac 1344
1da177e4 1345 de4x5_setup_intr(dev);
f3b197ac 1346
1da177e4
LT		 1347 if (de4x5_debug & DEBUG_OPEN) {
1348 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1349 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1350 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1351 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1352 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1353 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1354 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1355 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1356 }
f3b197ac 1357
1da177e4
LT		 1358 return status;
1359}
1360
1361/*
1362** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1363** DC21140 requires using perfect filtering mode for that chip. Since I can't
1364** see why I'd want > 14 multicast addresses, I have changed all chips to use
1365** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1366** to be data corruption problems if it is larger (UDP errors seen from a
1367** ttcp source).
1368*/
1369static int
1370de4x5_init(struct net_device *dev)
f3b197ac 1371{
1da177e4
LT		 1372 /* Lock out other processes whilst setting up the hardware */
1373 netif_stop_queue(dev);
f3b197ac 1374
1da177e4 1375 de4x5_sw_reset(dev);
f3b197ac 1376
1da177e4
LT		 1377 /* Autoconfigure the connected port */
1378 autoconf_media(dev);
f3b197ac 1379
1da177e4
LT		 1380 return 0;
1381}
1382
1383static int
1384de4x5_sw_reset(struct net_device *dev)
1385{
1386 struct de4x5_private *lp = netdev_priv(dev);
1387 u_long iobase = dev->base_addr;
1388 int i, j, status = 0;
1389 s32 bmr, omr;
f3b197ac 1390
1da177e4
LT		 1391 /* Select the MII or SRL port now and RESET the MAC */
1392 if (!lp->useSROM) {
1393 if (lp->phy[lp->active].id != 0) {
1394 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1395 } else {
1396 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1397 }
1398 de4x5_switch_mac_port(dev);
1399 }
1400
f3b197ac 1401 /*
1da177e4
LT		 1402 ** Set the programmable burst length to 8 longwords for all the DC21140
1403 ** Fasternet chips and 4 longwords for all others: DMA errors result
1404 ** without these values. Cache align 16 long.
1405 */
1406 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1407 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1408 outl(bmr, DE4X5_BMR);
1409
1410 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1411 if (lp->chipset == DC21140) {
1412 omr |= (OMR_SDP | OMR_SB);
1413 }
1414 lp->setup_f = PERFECT;
1415 outl(lp->dma_rings, DE4X5_RRBA);
1416 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1417 DE4X5_TRBA);
f3b197ac 1418
1da177e4
LT		 1419 lp->rx_new = lp->rx_old = 0;
1420 lp->tx_new = lp->tx_old = 0;
f3b197ac 1421
1da177e4
LT		 1422 for (i = 0; i < lp->rxRingSize; i++) {
1423 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1424 }
f3b197ac 1425
1da177e4
LT		 1426 for (i = 0; i < lp->txRingSize; i++) {
1427 lp->tx_ring[i].status = cpu_to_le32(0);
1428 }
f3b197ac 1429
1da177e4
LT		 1430 barrier();
1431
1432 /* Build the setup frame depending on filtering mode */
1433 SetMulticastFilter(dev);
f3b197ac 1434
1da177e4
LT		 1435 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1436 outl(omr|OMR_ST, DE4X5_OMR);
1437
1438 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1439
1440 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1441 mdelay(1);
1442 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1443 }
1444 outl(omr, DE4X5_OMR); /* Stop everything! */
1445
1446 if (j == 0) {
f3b197ac 1447 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1da177e4
LT		 1448 inl(DE4X5_STS));
1449 status = -EIO;
1450 }
f3b197ac 1451
1da177e4
LT		 1452 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1453 lp->tx_old = lp->tx_new;
1454
1455 return status;
1456}
1457
f3b197ac 1458/*
1da177e4
LT		 1459** Writes a socket buffer address to the next available transmit descriptor.
1460*/
1461static int
1462de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1463{
1464 struct de4x5_private *lp = netdev_priv(dev);
1465 u_long iobase = dev->base_addr;
1466 int status = 0;
1467 u_long flags = 0;
1468
1469 netif_stop_queue(dev);
1470 if (lp->tx_enable == NO) { /* Cannot send for now */
f3b197ac 1471 return -1;
1da177e4 1472 }
f3b197ac 1473
1da177e4
LT		 1474 /*
1475 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1476 ** interrupts are lost by delayed descriptor status updates relative to
1477 ** the irq assertion, especially with a busy PCI bus.
1478 */
1479 spin_lock_irqsave(&lp->lock, flags);
1480 de4x5_tx(dev);
1481 spin_unlock_irqrestore(&lp->lock, flags);
1482
1483 /* Test if cache is already locked - requeue skb if so */
f3b197ac 1484 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1da177e4
LT		 1485 return -1;
1486
1487 /* Transmit descriptor ring full or stale skb */
1488 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1489 if (lp->interrupt) {
1490 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1491 } else {
1492 de4x5_put_cache(dev, skb);
1493 }
1494 if (de4x5_debug & DEBUG_TX) {
1495 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1496 }
1497 } else if (skb->len > 0) {
1498 /* If we already have stuff queued locally, use that first */
1499 if (lp->cache.skb && !lp->interrupt) {
1500 de4x5_put_cache(dev, skb);
1501 skb = de4x5_get_cache(dev);
1502 }
1503
1504 while (skb && !netif_queue_stopped(dev) &&
1505 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1506 spin_lock_irqsave(&lp->lock, flags);
1507 netif_stop_queue(dev);
1508 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1509 lp->stats.tx_bytes += skb->len;
1510 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
f3b197ac 1511
1da177e4
LT		 1512 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1513 dev->trans_start = jiffies;
f3b197ac 1514
1da177e4
LT		 1515 if (TX_BUFFS_AVAIL) {
1516 netif_start_queue(dev); /* Another pkt may be queued */
1517 }
1518 skb = de4x5_get_cache(dev);
1519 spin_unlock_irqrestore(&lp->lock, flags);
1520 }
1521 if (skb) de4x5_putb_cache(dev, skb);
1522 }
f3b197ac 1523
1da177e4
LT		 1524 lp->cache.lock = 0;
1525
1526 return status;
1527}
1528
1529/*
f3b197ac
JG		 1530** The DE4X5 interrupt handler.
1531**
1da177e4
LT		 1532** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1533** so that the asserted interrupt always has some real data to work with -
1534** if these I/O accesses are ever changed to memory accesses, ensure the
1535** STS write is read immediately to complete the transaction if the adapter
1536** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1537** is high and descriptor status bits cannot be set before the associated
1538** interrupt is asserted and this routine entered.
1539*/
1540static irqreturn_t
1541de4x5_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1542{
1543 struct net_device *dev = (struct net_device *)dev_id;
1544 struct de4x5_private *lp;
1545 s32 imr, omr, sts, limit;
1546 u_long iobase;
1547 unsigned int handled = 0;
f3b197ac 1548
1da177e4
LT		 1549 if (dev == NULL) {
1550 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
1551 return IRQ_NONE;
1552 }
1553 lp = netdev_priv(dev);
1554 spin_lock(&lp->lock);
1555 iobase = dev->base_addr;
f3b197ac 1556
1da177e4
LT		 1557 DISABLE_IRQs; /* Ensure non re-entrancy */
1558
1559 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1560 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1561
1562 synchronize_irq(dev->irq);
f3b197ac 1563
1da177e4
LT		 1564 for (limit=0; limit<8; limit++) {
1565 sts = inl(DE4X5_STS); /* Read IRQ status */
1566 outl(sts, DE4X5_STS); /* Reset the board interrupts */
f3b197ac 1567
1da177e4
LT		 1568 if (!(sts & lp->irq_mask)) break;/* All done */
1569 handled = 1;
f3b197ac 1570
1da177e4
LT		 1571 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1572 de4x5_rx(dev);
f3b197ac 1573
1da177e4 1574 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
f3b197ac
JG		 1575 de4x5_tx(dev);
1576
1da177e4
LT		 1577 if (sts & STS_LNF) { /* TP Link has failed */
1578 lp->irq_mask &= ~IMR_LFM;
1579 }
f3b197ac 1580
1da177e4
LT		 1581 if (sts & STS_UNF) { /* Transmit underrun */
1582 de4x5_txur(dev);
1583 }
f3b197ac 1584
1da177e4
LT		 1585 if (sts & STS_SE) { /* Bus Error */
1586 STOP_DE4X5;
1587 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1588 dev->name, sts);
1589 spin_unlock(&lp->lock);
1590 return IRQ_HANDLED;
1591 }
1592 }
1593
1594 /* Load the TX ring with any locally stored packets */
1595 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1596 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1597 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1598 }
1599 lp->cache.lock = 0;
1600 }
1601
1602 lp->interrupt = UNMASK_INTERRUPTS;
1603 ENABLE_IRQs;
1604 spin_unlock(&lp->lock);
f3b197ac 1605
1da177e4
LT		 1606 return IRQ_RETVAL(handled);
1607}
1608
1609static int
1610de4x5_rx(struct net_device *dev)
1611{
1612 struct de4x5_private *lp = netdev_priv(dev);
1613 u_long iobase = dev->base_addr;
1614 int entry;
1615 s32 status;
f3b197ac 1616
1da177e4
LT		 1617 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1618 entry=lp->rx_new) {
1619 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
f3b197ac 1620
1da177e4
LT		 1621 if (lp->rx_ovf) {
1622 if (inl(DE4X5_MFC) & MFC_FOCM) {
1623 de4x5_rx_ovfc(dev);
1624 break;
1625 }
1626 }
1627
1628 if (status & RD_FS) { /* Remember the start of frame */
1629 lp->rx_old = entry;
1630 }
f3b197ac 1631
1da177e4
LT		 1632 if (status & RD_LS) { /* Valid frame status */
1633 if (lp->tx_enable) lp->linkOK++;
1634 if (status & RD_ES) { /* There was an error. */
1635 lp->stats.rx_errors++; /* Update the error stats. */
1636 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1637 if (status & RD_CE) lp->stats.rx_crc_errors++;
1638 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1639 if (status & RD_TL) lp->stats.rx_length_errors++;
1640 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1641 if (status & RD_CS) lp->pktStats.rx_collision++;
1642 if (status & RD_DB) lp->pktStats.rx_dribble++;
1643 if (status & RD_OF) lp->pktStats.rx_overflow++;
1644 } else { /* A valid frame received */
1645 struct sk_buff *skb;
1646 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1647 >> 16) - 4;
f3b197ac 1648
1da177e4 1649 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
f3b197ac 1650 printk("%s: Insufficient memory; nuking packet.\n",
1da177e4
LT		 1651 dev->name);
1652 lp->stats.rx_dropped++;
1653 } else {
1654 de4x5_dbg_rx(skb, pkt_len);
1655
1656 /* Push up the protocol stack */
1657 skb->protocol=eth_type_trans(skb,dev);
1658 de4x5_local_stats(dev, skb->data, pkt_len);
1659 netif_rx(skb);
f3b197ac 1660
1da177e4
LT		 1661 /* Update stats */
1662 dev->last_rx = jiffies;
1663 lp->stats.rx_packets++;
1664 lp->stats.rx_bytes += pkt_len;
1665 }
1666 }
f3b197ac 1667
1da177e4
LT		 1668 /* Change buffer ownership for this frame, back to the adapter */
1669 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1670 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1671 barrier();
1672 }
1673 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1674 barrier();
1675 }
f3b197ac 1676
1da177e4
LT		 1677 /*
1678 ** Update entry information
1679 */
1680 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1681 }
f3b197ac 1682
1da177e4
LT		 1683 return 0;
1684}
1685
1686static inline void
1687de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1688{
1689 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1690 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1691 DMA_TO_DEVICE);
1692 if ((u_long) lp->tx_skb[entry] > 1)
1693 dev_kfree_skb_irq(lp->tx_skb[entry]);
1694 lp->tx_skb[entry] = NULL;
1695}
1696
1697/*
1698** Buffer sent - check for TX buffer errors.
1699*/
1700static int
1701de4x5_tx(struct net_device *dev)
1702{
1703 struct de4x5_private *lp = netdev_priv(dev);
1704 u_long iobase = dev->base_addr;
1705 int entry;
1706 s32 status;
f3b197ac 1707
1da177e4
LT		 1708 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1709 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1710 if (status < 0) { /* Buffer not sent yet */
1711 break;
1712 } else if (status != 0x7fffffff) { /* Not setup frame */
1713 if (status & TD_ES) { /* An error happened */
f3b197ac 1714 lp->stats.tx_errors++;
1da177e4
LT		 1715 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1716 if (status & TD_LC) lp->stats.tx_window_errors++;
1717 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1718 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1719 if (status & TD_DE) lp->stats.tx_aborted_errors++;
f3b197ac 1720
1da177e4
LT		 1721 if (TX_PKT_PENDING) {
1722 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1723 }
1724 } else { /* Packet sent */
1725 lp->stats.tx_packets++;
1726 if (lp->tx_enable) lp->linkOK++;
1727 }
1728 /* Update the collision counter */
f3b197ac 1729 lp->stats.collisions += ((status & TD_EC) ? 16 :
1da177e4
LT		 1730 ((status & TD_CC) >> 3));
1731
1732 /* Free the buffer. */
1733 if (lp->tx_skb[entry] != NULL)
1734 de4x5_free_tx_buff(lp, entry);
1735 }
f3b197ac 1736
1da177e4
LT		 1737 /* Update all the pointers */
1738 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1739 }
1740
1741 /* Any resources available? */
1742 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1743 if (lp->interrupt)
1744 netif_wake_queue(dev);
1745 else
1746 netif_start_queue(dev);
1747 }
f3b197ac 1748
1da177e4
LT		 1749 return 0;
1750}
1751
1752static int
1753de4x5_ast(struct net_device *dev)
1754{
1755 struct de4x5_private *lp = netdev_priv(dev);
1756 int next_tick = DE4X5_AUTOSENSE_MS;
f3b197ac 1757
1da177e4 1758 disable_ast(dev);
f3b197ac 1759
1da177e4
LT		 1760 if (lp->useSROM) {
1761 next_tick = srom_autoconf(dev);
1762 } else if (lp->chipset == DC21140) {
1763 next_tick = dc21140m_autoconf(dev);
1764 } else if (lp->chipset == DC21041) {
1765 next_tick = dc21041_autoconf(dev);
1766 } else if (lp->chipset == DC21040) {
1767 next_tick = dc21040_autoconf(dev);
1768 }
1769 lp->linkOK = 0;
1770 enable_ast(dev, next_tick);
f3b197ac 1771
1da177e4
LT		 1772 return 0;
1773}
1774
1775static int
1776de4x5_txur(struct net_device *dev)
1777{
1778 struct de4x5_private *lp = netdev_priv(dev);
1779 u_long iobase = dev->base_addr;
1780 int omr;
1781
1782 omr = inl(DE4X5_OMR);
1783 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1784 omr &= ~(OMR_ST|OMR_SR);
1785 outl(omr, DE4X5_OMR);
1786 while (inl(DE4X5_STS) & STS_TS);
1787 if ((omr & OMR_TR) < OMR_TR) {
1788 omr += 0x4000;
1789 } else {
1790 omr |= OMR_SF;
1791 }
1792 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1793 }
f3b197ac 1794
1da177e4
LT		 1795 return 0;
1796}
1797
f3b197ac 1798static int
1da177e4
LT		 1799de4x5_rx_ovfc(struct net_device *dev)
1800{
1801 struct de4x5_private *lp = netdev_priv(dev);
1802 u_long iobase = dev->base_addr;
1803 int omr;
1804
1805 omr = inl(DE4X5_OMR);
1806 outl(omr & ~OMR_SR, DE4X5_OMR);
1807 while (inl(DE4X5_STS) & STS_RS);
1808
1809 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1810 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1811 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1812 }
1813
1814 outl(omr, DE4X5_OMR);
f3b197ac 1815
1da177e4
LT		 1816 return 0;
1817}
1818
1819static int
1820de4x5_close(struct net_device *dev)
1821{
1822 struct de4x5_private *lp = netdev_priv(dev);
1823 u_long iobase = dev->base_addr;
1824 s32 imr, omr;
f3b197ac 1825
1da177e4
LT		 1826 disable_ast(dev);
1827
1828 netif_stop_queue(dev);
f3b197ac 1829
1da177e4
LT		 1830 if (de4x5_debug & DEBUG_CLOSE) {
1831 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1832 dev->name, inl(DE4X5_STS));
1833 }
f3b197ac
JG		 1834
1835 /*
1da177e4
LT		 1836 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1837 */
1838 DISABLE_IRQs;
1839 STOP_DE4X5;
f3b197ac 1840
1da177e4
LT		 1841 /* Free the associated irq */
1842 free_irq(dev->irq, dev);
1843 lp->state = CLOSED;
1844
1845 /* Free any socket buffers */
1846 de4x5_free_rx_buffs(dev);
1847 de4x5_free_tx_buffs(dev);
f3b197ac 1848
1da177e4
LT		 1849 /* Put the adapter to sleep to save power */
1850 yawn(dev, SLEEP);
f3b197ac 1851
1da177e4
LT		 1852 return 0;
1853}
1854
1855static struct net_device_stats *
1856de4x5_get_stats(struct net_device *dev)
1857{
1858 struct de4x5_private *lp = netdev_priv(dev);
1859 u_long iobase = dev->base_addr;
f3b197ac 1860
1da177e4 1861 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
f3b197ac 1862
1da177e4
LT		 1863 return &lp->stats;
1864}
1865
1866static void
1867de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1868{
1869 struct de4x5_private *lp = netdev_priv(dev);
1870 int i;
1871
1872 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1873 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1874 lp->pktStats.bins[i]++;
1875 i = DE4X5_PKT_STAT_SZ;
1876 }
1877 }
1878 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1879 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1880 lp->pktStats.broadcast++;
1881 } else {
1882 lp->pktStats.multicast++;
1883 }
1884 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1885 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1886 lp->pktStats.unicast++;
1887 }
f3b197ac 1888
1da177e4
LT		 1889 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1890 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1891 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1892 }
1893
1894 return;
1895}
1896
1897/*
1898** Removes the TD_IC flag from previous descriptor to improve TX performance.
1899** If the flag is changed on a descriptor that is being read by the hardware,
1900** I assume PCI transaction ordering will mean you are either successful or
1901** just miss asserting the change to the hardware. Anyway you're messing with
1902** a descriptor you don't own, but this shouldn't kill the chip provided
1903** the descriptor register is read only to the hardware.
1904*/
1905static void
1906load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1907{
1908 struct de4x5_private *lp = netdev_priv(dev);
1909 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1910 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1911
1912 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1913 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1914 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1915 lp->tx_skb[lp->tx_new] = skb;
1916 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1917 barrier();
1918
1919 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1920 barrier();
1921}
1922
1923/*
1924** Set or clear the multicast filter for this adaptor.
1925*/
1926static void
1927set_multicast_list(struct net_device *dev)
1928{
1929 struct de4x5_private *lp = netdev_priv(dev);
1930 u_long iobase = dev->base_addr;
1931
1932 /* First, double check that the adapter is open */
1933 if (lp->state == OPEN) {
1934 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1935 u32 omr;
1936 omr = inl(DE4X5_OMR);
1937 omr |= OMR_PR;
1938 outl(omr, DE4X5_OMR);
f3b197ac 1939 } else {
1da177e4 1940 SetMulticastFilter(dev);
f3b197ac 1941 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1da177e4 1942 SETUP_FRAME_LEN, (struct sk_buff *)1);
f3b197ac 1943
1da177e4
LT		 1944 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1945 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1946 dev->trans_start = jiffies;
1947 }
1948 }
1949}
1950
1951/*
1952** Calculate the hash code and update the logical address filter
1953** from a list of ethernet multicast addresses.
1954** Little endian crc one liner from Matt Thomas, DEC.
1955*/
1956static void
1957SetMulticastFilter(struct net_device *dev)
1958{
1959 struct de4x5_private *lp = netdev_priv(dev);
1960 struct dev_mc_list *dmi=dev->mc_list;
1961 u_long iobase = dev->base_addr;
1962 int i, j, bit, byte;
1963 u16 hashcode;
1964 u32 omr, crc;
1965 char *pa;
1966 unsigned char *addrs;
1967
1968 omr = inl(DE4X5_OMR);
1969 omr &= ~(OMR_PR | OMR_PM);
1970 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
f3b197ac 1971
1da177e4
LT		 1972 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1973 omr |= OMR_PM; /* Pass all multicasts */
1974 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1975 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1976 addrs=dmi->dmi_addr;
1977 dmi=dmi->next;
f3b197ac 1978 if ((*addrs & 0x01) == 1) { /* multicast address? */
1da177e4
LT		 1979 crc = ether_crc_le(ETH_ALEN, addrs);
1980 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
f3b197ac 1981
1da177e4
LT		 1982 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1983 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
f3b197ac 1984
1da177e4
LT		 1985 byte <<= 1; /* calc offset into setup frame */
1986 if (byte & 0x02) {
1987 byte -= 1;
1988 }
1989 lp->setup_frame[byte] |= bit;
1990 }
1991 }
1992 } else { /* Perfect filtering */
1993 for (j=0; j<dev->mc_count; j++) {
1994 addrs=dmi->dmi_addr;
1995 dmi=dmi->next;
f3b197ac 1996 for (i=0; i<ETH_ALEN; i++) {
1da177e4
LT		 1997 *(pa + (i&1)) = *addrs++;
1998 if (i & 0x01) pa += 4;
1999 }
2000 }
2001 }
2002 outl(omr, DE4X5_OMR);
f3b197ac 2003
1da177e4
LT		 2004 return;
2005}
2006
2007#ifdef CONFIG_EISA
2008
2009static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2010
2011static int __init de4x5_eisa_probe (struct device *gendev)
2012{
2013 struct eisa_device *edev;
2014 u_long iobase;
2015 u_char irq, regval;
2016 u_short vendor;
2017 u32 cfid;
2018 int status, device;
2019 struct net_device *dev;
2020 struct de4x5_private *lp;
2021
2022 edev = to_eisa_device (gendev);
2023 iobase = edev->base_addr;
2024
2025 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2026 return -EBUSY;
2027
2028 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2029 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2030 status = -EBUSY;
2031 goto release_reg_1;
2032 }
f3b197ac 2033
1da177e4
LT		 2034 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2035 status = -ENOMEM;
2036 goto release_reg_2;
2037 }
2038 lp = netdev_priv(dev);
f3b197ac 2039
1da177e4
LT		 2040 cfid = (u32) inl(PCI_CFID);
2041 lp->cfrv = (u_short) inl(PCI_CFRV);
2042 device = (cfid >> 8) & 0x00ffff00;
2043 vendor = (u_short) cfid;
f3b197ac 2044
1da177e4
LT		 2045 /* Read the EISA Configuration Registers */
2046 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2047#ifdef CONFIG_ALPHA
2048 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2049 * care about the EISA configuration, and thus doesn't
2050 * configure the PLX bridge properly. Oh well... Simply mimic
2051 * the EISA config file to sort it out. */
f3b197ac 2052
1da177e4
LT		 2053 /* EISA REG1: Assert DecChip 21040 HW Reset */
2054 outb (ER1_IAM | 1, EISA_REG1);
2055 mdelay (1);
2056
2057 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2058 outb (ER1_IAM, EISA_REG1);
2059 mdelay (1);
2060
2061 /* EISA REG3: R/W Burst Transfer Enable */
2062 outb (ER3_BWE | ER3_BRE, EISA_REG3);
f3b197ac 2063
1da177e4
LT		 2064 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2065 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2066#endif
2067 irq = de4x5_irq[(regval >> 1) & 0x03];
f3b197ac 2068
1da177e4
LT		 2069 if (is_DC2114x) {
2070 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2071 }
2072 lp->chipset = device;
2073 lp->bus = EISA;
2074
2075 /* Write the PCI Configuration Registers */
2076 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2077 outl(0x00006000, PCI_CFLT);
2078 outl(iobase, PCI_CBIO);
f3b197ac 2079
1da177e4
LT		 2080 DevicePresent(dev, EISA_APROM);
2081
2082 dev->irq = irq;
2083
2084 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2085 return 0;
2086 }
2087
2088 free_netdev (dev);
2089 release_reg_2:
2090 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2091 release_reg_1:
2092 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2093
2094 return status;
2095}
2096
2097static int __devexit de4x5_eisa_remove (struct device *device)
2098{
2099 struct net_device *dev;
2100 u_long iobase;
2101
2102 dev = device->driver_data;
2103 iobase = dev->base_addr;
f3b197ac 2104
1da177e4
LT		 2105 unregister_netdev (dev);
2106 free_netdev (dev);
2107 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2108 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2109
2110 return 0;
2111}
2112
2113static struct eisa_device_id de4x5_eisa_ids[] = {
2114 { "DEC4250", 0 }, /* 0 is the board name index... */
2115 { "" }
2116};
2117
2118static struct eisa_driver de4x5_eisa_driver = {
2119 .id_table = de4x5_eisa_ids,
2120 .driver = {
2121 .name = "de4x5",
2122 .probe = de4x5_eisa_probe,
2123 .remove = __devexit_p (de4x5_eisa_remove),
2124 }
2125};
2126MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2127#endif
2128
2129#ifdef CONFIG_PCI
2130
2131/*
2132** This function searches the current bus (which is >0) for a DECchip with an
f3b197ac 2133** SROM, so that in multiport cards that have one SROM shared between multiple
1da177e4
LT		 2134** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2135** For single port cards this is a time waster...
2136*/
f3b197ac 2137static void __devinit
1da177e4
LT		 2138srom_search(struct net_device *dev, struct pci_dev *pdev)
2139{
2140 u_char pb;
2141 u_short vendor, status;
2142 u_int irq = 0, device;
2143 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2144 int i, j, cfrv;
2145 struct de4x5_private *lp = netdev_priv(dev);
0c5719c4 2146 struct list_head *walk;
1da177e4 2147
0c5719c4 2148 list_for_each(walk, &pdev->bus_list) {
1da177e4
LT		 2149 struct pci_dev *this_dev = pci_dev_b(walk);
2150
2151 /* Skip the pci_bus list entry */
2152 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2153
2154 vendor = this_dev->vendor;
2155 device = this_dev->device << 8;
2156 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2157
2158 /* Get the chip configuration revision register */
2159 pb = this_dev->bus->number;
2160 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2161
2162 /* Set the device number information */
2163 lp->device = PCI_SLOT(this_dev->devfn);
2164 lp->bus_num = pb;
f3b197ac 2165
1da177e4
LT		 2166 /* Set the chipset information */
2167 if (is_DC2114x) {
2168 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2169 }
2170 lp->chipset = device;
2171
2172 /* Get the board I/O address (64 bits on sparc64) */
2173 iobase = pci_resource_start(this_dev, 0);
2174
2175 /* Fetch the IRQ to be used */
2176 irq = this_dev->irq;
2177 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
f3b197ac 2178
1da177e4
LT		 2179 /* Check if I/O accesses are enabled */
2180 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2181 if (!(status & PCI_COMMAND_IO)) continue;
2182
2183 /* Search for a valid SROM attached to this DECchip */
2184 DevicePresent(dev, DE4X5_APROM);
2185 for (j=0, i=0; i<ETH_ALEN; i++) {
2186 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2187 }
2188 if ((j != 0) && (j != 0x5fa)) {
2189 last.chipset = device;
2190 last.bus = pb;
2191 last.irq = irq;
2192 for (i=0; i<ETH_ALEN; i++) {
2193 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2194 }
2195 return;
2196 }
2197 }
2198
2199 return;
2200}
2201
2202/*
2203** PCI bus I/O device probe
2204** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2205** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2206** enabled by the user first in the set up utility. Hence we just check for
2207** enabled features and silently ignore the card if they're not.
2208**
2209** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2210** bit. Here, check for I/O accesses and then set BM. If you put the card in
2211** a non BM slot, you're on your own (and complain to the PC vendor that your
2212** PC doesn't conform to the PCI standard)!
2213**
2214** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2215** kernels use the V0.535[n] drivers.
2216*/
2217
2218static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2219 const struct pci_device_id *ent)
2220{
2221 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2222 u_short vendor, status;
2223 u_int irq = 0, device;
2224 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2225 int error;
2226 struct net_device *dev;
2227 struct de4x5_private *lp;
2228
2229 dev_num = PCI_SLOT(pdev->devfn);
2230 pb = pdev->bus->number;
2231
2232 if (io) { /* probe a single PCI device */
2233 pbus = (u_short)(io >> 8);
2234 dnum = (u_short)(io & 0xff);
2235 if ((pbus != pb) || (dnum != dev_num))
2236 return -ENODEV;
2237 }
2238
2239 vendor = pdev->vendor;
2240 device = pdev->device << 8;
2241 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2242 return -ENODEV;
2243
2244 /* Ok, the device seems to be for us. */
2245 if ((error = pci_enable_device (pdev)))
2246 return error;
2247
2248 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2249 error = -ENOMEM;
2250 goto disable_dev;
2251 }
2252
2253 lp = netdev_priv(dev);
2254 lp->bus = PCI;
2255 lp->bus_num = 0;
f3b197ac 2256
1da177e4
LT		 2257 /* Search for an SROM on this bus */
2258 if (lp->bus_num != pb) {
2259 lp->bus_num = pb;
2260 srom_search(dev, pdev);
2261 }
2262
2263 /* Get the chip configuration revision register */
2264 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2265
2266 /* Set the device number information */
2267 lp->device = dev_num;
2268 lp->bus_num = pb;
f3b197ac 2269
1da177e4
LT		 2270 /* Set the chipset information */
2271 if (is_DC2114x) {
2272 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2273 }
2274 lp->chipset = device;
2275
2276 /* Get the board I/O address (64 bits on sparc64) */
2277 iobase = pci_resource_start(pdev, 0);
2278
2279 /* Fetch the IRQ to be used */
2280 irq = pdev->irq;
2281 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2282 error = -ENODEV;
2283 goto free_dev;
2284 }
f3b197ac 2285
1da177e4
LT		 2286 /* Check if I/O accesses and Bus Mastering are enabled */
2287 pci_read_config_word(pdev, PCI_COMMAND, &status);
2288#ifdef __powerpc__
2289 if (!(status & PCI_COMMAND_IO)) {
2290 status |= PCI_COMMAND_IO;
2291 pci_write_config_word(pdev, PCI_COMMAND, status);
2292 pci_read_config_word(pdev, PCI_COMMAND, &status);
2293 }
2294#endif /* __powerpc__ */
2295 if (!(status & PCI_COMMAND_IO)) {
2296 error = -ENODEV;
2297 goto free_dev;
2298 }
2299
2300 if (!(status & PCI_COMMAND_MASTER)) {
2301 status |= PCI_COMMAND_MASTER;
2302 pci_write_config_word(pdev, PCI_COMMAND, status);
2303 pci_read_config_word(pdev, PCI_COMMAND, &status);
2304 }
2305 if (!(status & PCI_COMMAND_MASTER)) {
2306 error = -ENODEV;
2307 goto free_dev;
2308 }
2309
2310 /* Check the latency timer for values >= 0x60 */
2311 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2312 if (timer < 0x60) {
2313 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2314 }
2315
2316 DevicePresent(dev, DE4X5_APROM);
2317
2318 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2319 error = -EBUSY;
2320 goto free_dev;
2321 }
2322
2323 dev->irq = irq;
f3b197ac 2324
1da177e4
LT		 2325 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2326 goto release;
2327 }
2328
2329 return 0;
2330
2331 release:
2332 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2333 free_dev:
2334 free_netdev (dev);
2335 disable_dev:
2336 pci_disable_device (pdev);
2337 return error;
2338}
2339
2340static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2341{
2342 struct net_device *dev;
2343 u_long iobase;
2344
2345 dev = pdev->dev.driver_data;
2346 iobase = dev->base_addr;
2347
2348 unregister_netdev (dev);
2349 free_netdev (dev);
2350 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2351 pci_disable_device (pdev);
2352}
2353
2354static struct pci_device_id de4x5_pci_tbl[] = {
2355 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2357 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2359 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2361 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2363 { },
2364};
2365
2366static struct pci_driver de4x5_pci_driver = {
2367 .name = "de4x5",
2368 .id_table = de4x5_pci_tbl,
2369 .probe = de4x5_pci_probe,
2370 .remove = __devexit_p (de4x5_pci_remove),
2371};
2372
2373#endif
2374
2375/*
2376** Auto configure the media here rather than setting the port at compile
2377** time. This routine is called by de4x5_init() and when a loss of media is
2378** detected (excessive collisions, loss of carrier, no carrier or link fail
f3b197ac 2379** [TP] or no recent receive activity) to check whether the user has been
1da177e4
LT		 2380** sneaky and changed the port on us.
2381*/
2382static int
2383autoconf_media(struct net_device *dev)
2384{
2385 struct de4x5_private *lp = netdev_priv(dev);
2386 u_long iobase = dev->base_addr;
2387 int next_tick = DE4X5_AUTOSENSE_MS;
2388
2389 lp->linkOK = 0;
2390 lp->c_media = AUTO; /* Bogus last media */
2391 disable_ast(dev);
2392 inl(DE4X5_MFC); /* Zero the lost frames counter */
2393 lp->media = INIT;
2394 lp->tcount = 0;
2395
2396 if (lp->useSROM) {
2397 next_tick = srom_autoconf(dev);
2398 } else if (lp->chipset == DC21040) {
2399 next_tick = dc21040_autoconf(dev);
2400 } else if (lp->chipset == DC21041) {
2401 next_tick = dc21041_autoconf(dev);
2402 } else if (lp->chipset == DC21140) {
2403 next_tick = dc21140m_autoconf(dev);
2404 }
2405
2406 enable_ast(dev, next_tick);
f3b197ac 2407
1da177e4
LT		 2408 return (lp->media);
2409}
2410
2411/*
2412** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2413** from BNC as the port has a jumper to set thick or thin wire. When set for
2414** BNC, the BNC port will indicate activity if it's not terminated correctly.
2415** The only way to test for that is to place a loopback packet onto the
2416** network and watch for errors. Since we're messing with the interrupt mask
2417** register, disable the board interrupts and do not allow any more packets to
2418** be queued to the hardware. Re-enable everything only when the media is
2419** found.
2420** I may have to "age out" locally queued packets so that the higher layer
2421** timeouts don't effectively duplicate packets on the network.
2422*/
2423static int
2424dc21040_autoconf(struct net_device *dev)
2425{
2426 struct de4x5_private *lp = netdev_priv(dev);
2427 u_long iobase = dev->base_addr;
2428 int next_tick = DE4X5_AUTOSENSE_MS;
2429 s32 imr;
f3b197ac 2430
1da177e4
LT		 2431 switch (lp->media) {
2432 case INIT:
2433 DISABLE_IRQs;
2434 lp->tx_enable = NO;
2435 lp->timeout = -1;
2436 de4x5_save_skbs(dev);
2437 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2438 lp->media = TP;
2439 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2440 lp->media = BNC_AUI;
2441 } else if (lp->autosense == EXT_SIA) {
2442 lp->media = EXT_SIA;
2443 } else {
2444 lp->media = NC;
2445 }
2446 lp->local_state = 0;
2447 next_tick = dc21040_autoconf(dev);
2448 break;
f3b197ac 2449
1da177e4 2450 case TP:
f3b197ac 2451 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
1da177e4
LT		 2452 TP_SUSPECT, test_tp);
2453 break;
f3b197ac 2454
1da177e4
LT		 2455 case TP_SUSPECT:
2456 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2457 break;
f3b197ac 2458
1da177e4
LT		 2459 case BNC:
2460 case AUI:
2461 case BNC_AUI:
f3b197ac 2462 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
1da177e4
LT		 2463 BNC_AUI_SUSPECT, ping_media);
2464 break;
f3b197ac 2465
1da177e4
LT		 2466 case BNC_AUI_SUSPECT:
2467 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2468 break;
f3b197ac 2469
1da177e4 2470 case EXT_SIA:
f3b197ac 2471 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
1da177e4
LT		 2472 NC, EXT_SIA_SUSPECT, ping_media);
2473 break;
f3b197ac 2474
1da177e4
LT		 2475 case EXT_SIA_SUSPECT:
2476 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2477 break;
f3b197ac 2478
1da177e4
LT		 2479 case NC:
2480 /* default to TP for all */
2481 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2482 if (lp->media != lp->c_media) {
2483 de4x5_dbg_media(dev);
2484 lp->c_media = lp->media;
2485 }
2486 lp->media = INIT;
2487 lp->tx_enable = NO;
2488 break;
2489 }
f3b197ac 2490
1da177e4
LT		 2491 return next_tick;
2492}
2493
2494static int
2495dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
f3b197ac 2496 int next_state, int suspect_state,
1da177e4
LT		 2497 int (*fn)(struct net_device *, int))
2498{
2499 struct de4x5_private *lp = netdev_priv(dev);
2500 int next_tick = DE4X5_AUTOSENSE_MS;
2501 int linkBad;
2502
2503 switch (lp->local_state) {
2504 case 0:
2505 reset_init_sia(dev, csr13, csr14, csr15);
2506 lp->local_state++;
2507 next_tick = 500;
2508 break;
f3b197ac 2509
1da177e4
LT		 2510 case 1:
2511 if (!lp->tx_enable) {
2512 linkBad = fn(dev, timeout);
2513 if (linkBad < 0) {
2514 next_tick = linkBad & ~TIMER_CB;
2515 } else {
2516 if (linkBad && (lp->autosense == AUTO)) {
2517 lp->local_state = 0;
2518 lp->media = next_state;
2519 } else {
2520 de4x5_init_connection(dev);
2521 }
2522 }
2523 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2524 lp->media = suspect_state;
2525 next_tick = 3000;
2526 }
2527 break;
2528 }
f3b197ac 2529
1da177e4
LT		 2530 return next_tick;
2531}
2532
2533static int
2534de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2535 int (*fn)(struct net_device *, int),
2536 int (*asfn)(struct net_device *))
2537{
2538 struct de4x5_private *lp = netdev_priv(dev);
2539 int next_tick = DE4X5_AUTOSENSE_MS;
2540 int linkBad;
2541
2542 switch (lp->local_state) {
2543 case 1:
2544 if (lp->linkOK) {
2545 lp->media = prev_state;
2546 } else {
2547 lp->local_state++;
2548 next_tick = asfn(dev);
2549 }
2550 break;
2551
2552 case 2:
2553 linkBad = fn(dev, timeout);
2554 if (linkBad < 0) {
2555 next_tick = linkBad & ~TIMER_CB;
2556 } else if (!linkBad) {
2557 lp->local_state--;
2558 lp->media = prev_state;
2559 } else {
2560 lp->media = INIT;
2561 lp->tcount++;
2562 }
2563 }
2564
2565 return next_tick;
2566}
2567
2568/*
2569** Autoconfigure the media when using the DC21041. AUI needs to be tested
2570** before BNC, because the BNC port will indicate activity if it's not
2571** terminated correctly. The only way to test for that is to place a loopback
2572** packet onto the network and watch for errors. Since we're messing with
2573** the interrupt mask register, disable the board interrupts and do not allow
2574** any more packets to be queued to the hardware. Re-enable everything only
2575** when the media is found.
2576*/
2577static int
2578dc21041_autoconf(struct net_device *dev)
2579{
2580 struct de4x5_private *lp = netdev_priv(dev);
2581 u_long iobase = dev->base_addr;
2582 s32 sts, irqs, irq_mask, imr, omr;
2583 int next_tick = DE4X5_AUTOSENSE_MS;
f3b197ac 2584
1da177e4
LT		 2585 switch (lp->media) {
2586 case INIT:
2587 DISABLE_IRQs;
2588 lp->tx_enable = NO;
2589 lp->timeout = -1;
2590 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2591 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2592 lp->media = TP; /* On chip auto negotiation is broken */
2593 } else if (lp->autosense == TP) {
2594 lp->media = TP;
2595 } else if (lp->autosense == BNC) {
2596 lp->media = BNC;
2597 } else if (lp->autosense == AUI) {
2598 lp->media = AUI;
2599 } else {
2600 lp->media = NC;
2601 }
2602 lp->local_state = 0;
2603 next_tick = dc21041_autoconf(dev);
2604 break;
f3b197ac 2605
1da177e4
LT		 2606 case TP_NW:
2607 if (lp->timeout < 0) {
2608 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2609 outl(omr | OMR_FDX, DE4X5_OMR);
2610 }
2611 irqs = STS_LNF | STS_LNP;
2612 irq_mask = IMR_LFM | IMR_LPM;
2613 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2614 if (sts < 0) {
2615 next_tick = sts & ~TIMER_CB;
2616 } else {
2617 if (sts & STS_LNP) {
2618 lp->media = ANS;
2619 } else {
2620 lp->media = AUI;
2621 }
2622 next_tick = dc21041_autoconf(dev);
2623 }
2624 break;
f3b197ac 2625
1da177e4
LT		 2626 case ANS:
2627 if (!lp->tx_enable) {
2628 irqs = STS_LNP;
2629 irq_mask = IMR_LPM;
2630 sts = test_ans(dev, irqs, irq_mask, 3000);
2631 if (sts < 0) {
2632 next_tick = sts & ~TIMER_CB;
2633 } else {
2634 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2635 lp->media = TP;
2636 next_tick = dc21041_autoconf(dev);
2637 } else {
2638 lp->local_state = 1;
2639 de4x5_init_connection(dev);
2640 }
2641 }
2642 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2643 lp->media = ANS_SUSPECT;
2644 next_tick = 3000;
2645 }
2646 break;
f3b197ac 2647
1da177e4
LT		 2648 case ANS_SUSPECT:
2649 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2650 break;
f3b197ac 2651
1da177e4
LT		 2652 case TP:
2653 if (!lp->tx_enable) {
2654 if (lp->timeout < 0) {
2655 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2656 outl(omr & ~OMR_FDX, DE4X5_OMR);
2657 }
2658 irqs = STS_LNF | STS_LNP;
2659 irq_mask = IMR_LFM | IMR_LPM;
2660 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2661 if (sts < 0) {
2662 next_tick = sts & ~TIMER_CB;
2663 } else {
2664 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2665 if (inl(DE4X5_SISR) & SISR_NRA) {
2666 lp->media = AUI; /* Non selected port activity */
2667 } else {
2668 lp->media = BNC;
2669 }
2670 next_tick = dc21041_autoconf(dev);
2671 } else {
2672 lp->local_state = 1;
2673 de4x5_init_connection(dev);
2674 }
2675 }
2676 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2677 lp->media = TP_SUSPECT;
2678 next_tick = 3000;
2679 }
2680 break;
f3b197ac 2681
1da177e4
LT		 2682 case TP_SUSPECT:
2683 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2684 break;
f3b197ac 2685
1da177e4
LT		 2686 case AUI:
2687 if (!lp->tx_enable) {
2688 if (lp->timeout < 0) {
2689 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2690 outl(omr & ~OMR_FDX, DE4X5_OMR);
2691 }
2692 irqs = 0;
2693 irq_mask = 0;
2694 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2695 if (sts < 0) {
2696 next_tick = sts & ~TIMER_CB;
2697 } else {
2698 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2699 lp->media = BNC;
2700 next_tick = dc21041_autoconf(dev);
2701 } else {
2702 lp->local_state = 1;
2703 de4x5_init_connection(dev);
2704 }
2705 }
2706 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2707 lp->media = AUI_SUSPECT;
2708 next_tick = 3000;
2709 }
2710 break;
f3b197ac 2711
1da177e4
LT		 2712 case AUI_SUSPECT:
2713 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2714 break;
f3b197ac 2715
1da177e4
LT		 2716 case BNC:
2717 switch (lp->local_state) {
2718 case 0:
2719 if (lp->timeout < 0) {
2720 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2721 outl(omr & ~OMR_FDX, DE4X5_OMR);
2722 }
2723 irqs = 0;
2724 irq_mask = 0;
2725 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2726 if (sts < 0) {
2727 next_tick = sts & ~TIMER_CB;
2728 } else {
2729 lp->local_state++; /* Ensure media connected */
2730 next_tick = dc21041_autoconf(dev);
2731 }
2732 break;
f3b197ac 2733
1da177e4
LT		 2734 case 1:
2735 if (!lp->tx_enable) {
2736 if ((sts = ping_media(dev, 3000)) < 0) {
2737 next_tick = sts & ~TIMER_CB;
2738 } else {
2739 if (sts) {
2740 lp->local_state = 0;
2741 lp->media = NC;
2742 } else {
2743 de4x5_init_connection(dev);
2744 }
2745 }
2746 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2747 lp->media = BNC_SUSPECT;
2748 next_tick = 3000;
2749 }
2750 break;
2751 }
2752 break;
f3b197ac 2753
1da177e4
LT		 2754 case BNC_SUSPECT:
2755 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2756 break;
f3b197ac 2757
1da177e4
LT		 2758 case NC:
2759 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2760 outl(omr | OMR_FDX, DE4X5_OMR);
2761 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2762 if (lp->media != lp->c_media) {
2763 de4x5_dbg_media(dev);
2764 lp->c_media = lp->media;
2765 }
2766 lp->media = INIT;
2767 lp->tx_enable = NO;
2768 break;
2769 }
f3b197ac 2770
1da177e4
LT		 2771 return next_tick;
2772}
2773
2774/*
2775** Some autonegotiation chips are broken in that they do not return the
2776** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2777** register, except at the first power up negotiation.
2778*/
2779static int
2780dc21140m_autoconf(struct net_device *dev)
2781{
2782 struct de4x5_private *lp = netdev_priv(dev);
2783 int ana, anlpa, cap, cr, slnk, sr;
2784 int next_tick = DE4X5_AUTOSENSE_MS;
2785 u_long imr, omr, iobase = dev->base_addr;
f3b197ac 2786
1da177e4 2787 switch(lp->media) {
f3b197ac 2788 case INIT:
1da177e4
LT		 2789 if (lp->timeout < 0) {
2790 DISABLE_IRQs;
2791 lp->tx_enable = FALSE;
2792 lp->linkOK = 0;
2793 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2794 }
2795 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2796 next_tick &= ~TIMER_CB;
2797 } else {
2798 if (lp->useSROM) {
2799 if (srom_map_media(dev) < 0) {
2800 lp->tcount++;
2801 return next_tick;
2802 }
2803 srom_exec(dev, lp->phy[lp->active].gep);
2804 if (lp->infoblock_media == ANS) {
2805 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2806 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2807 }
2808 } else {
2809 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2810 SET_10Mb;
2811 if (lp->autosense == _100Mb) {
2812 lp->media = _100Mb;
2813 } else if (lp->autosense == _10Mb) {
2814 lp->media = _10Mb;
f3b197ac 2815 } else if ((lp->autosense == AUTO) &&
1da177e4
LT		 2816 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2817 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2818 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2819 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2820 lp->media = ANS;
2821 } else if (lp->autosense == AUTO) {
2822 lp->media = SPD_DET;
2823 } else if (is_spd_100(dev) && is_100_up(dev)) {
2824 lp->media = _100Mb;
2825 } else {
2826 lp->media = NC;
2827 }
2828 }
2829 lp->local_state = 0;
2830 next_tick = dc21140m_autoconf(dev);
2831 }
2832 break;
f3b197ac 2833
1da177e4
LT		 2834 case ANS:
2835 switch (lp->local_state) {
2836 case 0:
2837 if (lp->timeout < 0) {
2838 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2839 }
2840 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2841 if (cr < 0) {
2842 next_tick = cr & ~TIMER_CB;
2843 } else {
2844 if (cr) {
2845 lp->local_state = 0;
2846 lp->media = SPD_DET;
2847 } else {
2848 lp->local_state++;
2849 }
2850 next_tick = dc21140m_autoconf(dev);
2851 }
2852 break;
f3b197ac 2853
1da177e4
LT		 2854 case 1:
2855 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2856 next_tick = sr & ~TIMER_CB;
2857 } else {
2858 lp->media = SPD_DET;
2859 lp->local_state = 0;
2860 if (sr) { /* Success! */
2861 lp->tmp = MII_SR_ASSC;
2862 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2863 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
f3b197ac 2864 if (!(anlpa & MII_ANLPA_RF) &&
1da177e4
LT		 2865 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2866 if (cap & MII_ANA_100M) {
2867 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2868 lp->media = _100Mb;
2869 } else if (cap & MII_ANA_10M) {
2870 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2871
2872 lp->media = _10Mb;
2873 }
2874 }
2875 } /* Auto Negotiation failed to finish */
2876 next_tick = dc21140m_autoconf(dev);
2877 } /* Auto Negotiation failed to start */
2878 break;
2879 }
2880 break;
f3b197ac 2881
1da177e4
LT		 2882 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2883 if (lp->timeout < 0) {
f3b197ac 2884 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
1da177e4
LT		 2885 (~gep_rd(dev) & GEP_LNP));
2886 SET_100Mb_PDET;
2887 }
2888 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2889 next_tick = slnk & ~TIMER_CB;
2890 } else {
2891 if (is_spd_100(dev) && is_100_up(dev)) {
2892 lp->media = _100Mb;
2893 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2894 lp->media = _10Mb;
2895 } else {
2896 lp->media = NC;
2897 }
2898 next_tick = dc21140m_autoconf(dev);
2899 }
2900 break;
f3b197ac 2901
1da177e4
LT		 2902 case _100Mb: /* Set 100Mb/s */
2903 next_tick = 3000;
2904 if (!lp->tx_enable) {
2905 SET_100Mb;
2906 de4x5_init_connection(dev);
2907 } else {
2908 if (!lp->linkOK && (lp->autosense == AUTO)) {
2909 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2910 lp->media = INIT;
2911 lp->tcount++;
2912 next_tick = DE4X5_AUTOSENSE_MS;
2913 }
2914 }
2915 }
2916 break;
2917
2918 case BNC:
2919 case AUI:
2920 case _10Mb: /* Set 10Mb/s */
2921 next_tick = 3000;
2922 if (!lp->tx_enable) {
2923 SET_10Mb;
2924 de4x5_init_connection(dev);
2925 } else {
2926 if (!lp->linkOK && (lp->autosense == AUTO)) {
2927 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2928 lp->media = INIT;
2929 lp->tcount++;
2930 next_tick = DE4X5_AUTOSENSE_MS;
2931 }
2932 }
2933 }
2934 break;
f3b197ac 2935
1da177e4
LT		 2936 case NC:
2937 if (lp->media != lp->c_media) {
2938 de4x5_dbg_media(dev);
2939 lp->c_media = lp->media;
2940 }
2941 lp->media = INIT;
2942 lp->tx_enable = FALSE;
2943 break;
2944 }
f3b197ac 2945
1da177e4
LT		 2946 return next_tick;
2947}
2948
2949/*
2950** This routine may be merged into dc21140m_autoconf() sometime as I'm
2951** changing how I figure out the media - but trying to keep it backwards
2952** compatible with the de500-xa and de500-aa.
2953** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2954** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2955** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2956** active.
2957** When autonegotiation is working, the ANS part searches the SROM for
2958** the highest common speed (TP) link that both can run and if that can
2959** be full duplex. That infoblock is executed and then the link speed set.
2960**
2961** Only _10Mb and _100Mb are tested here.
2962*/
2963static int
2964dc2114x_autoconf(struct net_device *dev)
2965{
2966 struct de4x5_private *lp = netdev_priv(dev);
2967 u_long iobase = dev->base_addr;
2968 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2969 int next_tick = DE4X5_AUTOSENSE_MS;
2970
2971 switch (lp->media) {
2972 case INIT:
2973 if (lp->timeout < 0) {
2974 DISABLE_IRQs;
2975 lp->tx_enable = FALSE;
2976 lp->linkOK = 0;
2977 lp->timeout = -1;
2978 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2979 if (lp->params.autosense & ~AUTO) {
2980 srom_map_media(dev); /* Fixed media requested */
2981 if (lp->media != lp->params.autosense) {
2982 lp->tcount++;
2983 lp->media = INIT;
2984 return next_tick;
2985 }
2986 lp->media = INIT;
2987 }
2988 }
2989 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2990 next_tick &= ~TIMER_CB;
2991 } else {
2992 if (lp->autosense == _100Mb) {
2993 lp->media = _100Mb;
2994 } else if (lp->autosense == _10Mb) {
2995 lp->media = _10Mb;
2996 } else if (lp->autosense == TP) {
2997 lp->media = TP;
2998 } else if (lp->autosense == BNC) {
2999 lp->media = BNC;
3000 } else if (lp->autosense == AUI) {
3001 lp->media = AUI;
3002 } else {
3003 lp->media = SPD_DET;
f3b197ac 3004 if ((lp->infoblock_media == ANS) &&
1da177e4
LT		 3005 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3006 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3007 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3008 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3009 lp->media = ANS;
3010 }
3011 }
3012 lp->local_state = 0;
3013 next_tick = dc2114x_autoconf(dev);
3014 }
3015 break;
f3b197ac 3016
1da177e4
LT		 3017 case ANS:
3018 switch (lp->local_state) {
3019 case 0:
3020 if (lp->timeout < 0) {
3021 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3022 }
3023 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3024 if (cr < 0) {
3025 next_tick = cr & ~TIMER_CB;
3026 } else {
3027 if (cr) {
3028 lp->local_state = 0;
3029 lp->media = SPD_DET;
3030 } else {
3031 lp->local_state++;
3032 }
3033 next_tick = dc2114x_autoconf(dev);
3034 }
3035 break;
f3b197ac 3036
1da177e4
LT		 3037 case 1:
3038 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3039 next_tick = sr & ~TIMER_CB;
3040 } else {
3041 lp->media = SPD_DET;
3042 lp->local_state = 0;
3043 if (sr) { /* Success! */
3044 lp->tmp = MII_SR_ASSC;
3045 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3046 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
f3b197ac 3047 if (!(anlpa & MII_ANLPA_RF) &&
1da177e4
LT		 3048 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3049 if (cap & MII_ANA_100M) {
3050 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3051 lp->media = _100Mb;
3052 } else if (cap & MII_ANA_10M) {
3053 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3054 lp->media = _10Mb;
3055 }
3056 }
3057 } /* Auto Negotiation failed to finish */
3058 next_tick = dc2114x_autoconf(dev);
3059 } /* Auto Negotiation failed to start */
3060 break;
3061 }
3062 break;
3063
3064 case AUI:
3065 if (!lp->tx_enable) {
3066 if (lp->timeout < 0) {
3067 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3068 outl(omr & ~OMR_FDX, DE4X5_OMR);
3069 }
3070 irqs = 0;
3071 irq_mask = 0;
3072 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3073 if (sts < 0) {
3074 next_tick = sts & ~TIMER_CB;
3075 } else {
3076 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3077 lp->media = BNC;
3078 next_tick = dc2114x_autoconf(dev);
3079 } else {
3080 lp->local_state = 1;
3081 de4x5_init_connection(dev);
3082 }
3083 }
3084 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3085 lp->media = AUI_SUSPECT;
3086 next_tick = 3000;
3087 }
3088 break;
f3b197ac 3089
1da177e4
LT		 3090 case AUI_SUSPECT:
3091 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3092 break;
f3b197ac 3093
1da177e4
LT		 3094 case BNC:
3095 switch (lp->local_state) {
3096 case 0:
3097 if (lp->timeout < 0) {
3098 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3099 outl(omr & ~OMR_FDX, DE4X5_OMR);
3100 }
3101 irqs = 0;
3102 irq_mask = 0;
3103 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3104 if (sts < 0) {
3105 next_tick = sts & ~TIMER_CB;
3106 } else {
3107 lp->local_state++; /* Ensure media connected */
3108 next_tick = dc2114x_autoconf(dev);
3109 }
3110 break;
f3b197ac 3111
1da177e4
LT		 3112 case 1:
3113 if (!lp->tx_enable) {
3114 if ((sts = ping_media(dev, 3000)) < 0) {
3115 next_tick = sts & ~TIMER_CB;
3116 } else {
3117 if (sts) {
3118 lp->local_state = 0;
3119 lp->tcount++;
3120 lp->media = INIT;
3121 } else {
3122 de4x5_init_connection(dev);
3123 }
3124 }
3125 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3126 lp->media = BNC_SUSPECT;
3127 next_tick = 3000;
3128 }
3129 break;
3130 }
3131 break;
f3b197ac 3132
1da177e4
LT		 3133 case BNC_SUSPECT:
3134 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3135 break;
f3b197ac 3136
1da177e4
LT		 3137 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3138 if (srom_map_media(dev) < 0) {
3139 lp->tcount++;
3140 lp->media = INIT;
3141 return next_tick;
3142 }
3143 if (lp->media == _100Mb) {
3144 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3145 lp->media = SPD_DET;
3146 return (slnk & ~TIMER_CB);
3147 }
3148 } else {
3149 if (wait_for_link(dev) < 0) {
3150 lp->media = SPD_DET;
3151 return PDET_LINK_WAIT;
3152 }
3153 }
3154 if (lp->media == ANS) { /* Do MII parallel detection */
3155 if (is_spd_100(dev)) {
3156 lp->media = _100Mb;
3157 } else {
3158 lp->media = _10Mb;
3159 }
3160 next_tick = dc2114x_autoconf(dev);
3161 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3162 (((lp->media == _10Mb) || (lp->media == TP) ||
f3b197ac 3163 (lp->media == BNC) || (lp->media == AUI)) &&
1da177e4
LT		 3164 is_10_up(dev))) {
3165 next_tick = dc2114x_autoconf(dev);
3166 } else {
3167 lp->tcount++;
3168 lp->media = INIT;
3169 }
3170 break;
f3b197ac 3171
1da177e4
LT		 3172 case _10Mb:
3173 next_tick = 3000;
3174 if (!lp->tx_enable) {
3175 SET_10Mb;
3176 de4x5_init_connection(dev);
3177 } else {
3178 if (!lp->linkOK && (lp->autosense == AUTO)) {
3179 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3180 lp->media = INIT;
3181 lp->tcount++;
3182 next_tick = DE4X5_AUTOSENSE_MS;
3183 }
3184 }
3185 }
3186 break;
3187
3188 case _100Mb:
3189 next_tick = 3000;
3190 if (!lp->tx_enable) {
3191 SET_100Mb;
3192 de4x5_init_connection(dev);
3193 } else {
3194 if (!lp->linkOK && (lp->autosense == AUTO)) {
3195 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3196 lp->media = INIT;
3197 lp->tcount++;
3198 next_tick = DE4X5_AUTOSENSE_MS;
3199 }
3200 }
3201 }
3202 break;
3203
3204 default:
3205 lp->tcount++;
3206printk("Huh?: media:%02x\n", lp->media);
3207 lp->media = INIT;
3208 break;
3209 }
f3b197ac 3210
1da177e4
LT		 3211 return next_tick;
3212}
3213
3214static int
3215srom_autoconf(struct net_device *dev)
3216{
3217 struct de4x5_private *lp = netdev_priv(dev);
3218
3219 return lp->infoleaf_fn(dev);
3220}
3221
3222/*
3223** This mapping keeps the original media codes and FDX flag unchanged.
3224** While it isn't strictly necessary, it helps me for the moment...
3225** The early return avoids a media state / SROM media space clash.
3226*/
3227static int
3228srom_map_media(struct net_device *dev)
3229{
3230 struct de4x5_private *lp = netdev_priv(dev);
3231
3232 lp->fdx = 0;
f3b197ac 3233 if (lp->infoblock_media == lp->media)
1da177e4
LT		 3234 return 0;
3235
3236 switch(lp->infoblock_media) {
3237 case SROM_10BASETF:
3238 if (!lp->params.fdx) return -1;
3239 lp->fdx = TRUE;
3240 case SROM_10BASET:
3241 if (lp->params.fdx && !lp->fdx) return -1;
3242 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3243 lp->media = _10Mb;
3244 } else {
3245 lp->media = TP;
3246 }
3247 break;
3248
3249 case SROM_10BASE2:
3250 lp->media = BNC;
3251 break;
3252
3253 case SROM_10BASE5:
3254 lp->media = AUI;
3255 break;
3256
3257 case SROM_100BASETF:
3258 if (!lp->params.fdx) return -1;
3259 lp->fdx = TRUE;
3260 case SROM_100BASET:
3261 if (lp->params.fdx && !lp->fdx) return -1;
3262 lp->media = _100Mb;
3263 break;
3264
3265 case SROM_100BASET4:
3266 lp->media = _100Mb;
3267 break;
3268
3269 case SROM_100BASEFF:
3270 if (!lp->params.fdx) return -1;
3271 lp->fdx = TRUE;
f3b197ac 3272 case SROM_100BASEF:
1da177e4
LT		 3273 if (lp->params.fdx && !lp->fdx) return -1;
3274 lp->media = _100Mb;
3275 break;
3276
3277 case ANS:
3278 lp->media = ANS;
3279 lp->fdx = lp->params.fdx;
3280 break;
3281
f3b197ac
JG		 3282 default:
3283 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
1da177e4
LT		 3284 lp->infoblock_media);
3285 return -1;
3286 break;
3287 }
3288
3289 return 0;
3290}
3291
3292static void
3293de4x5_init_connection(struct net_device *dev)
3294{
3295 struct de4x5_private *lp = netdev_priv(dev);
3296 u_long iobase = dev->base_addr;
3297 u_long flags = 0;
3298
3299 if (lp->media != lp->c_media) {
3300 de4x5_dbg_media(dev);
3301 lp->c_media = lp->media; /* Stop scrolling media messages */
3302 }
3303
3304 spin_lock_irqsave(&lp->lock, flags);
3305 de4x5_rst_desc_ring(dev);
3306 de4x5_setup_intr(dev);
3307 lp->tx_enable = YES;
3308 spin_unlock_irqrestore(&lp->lock, flags);
3309 outl(POLL_DEMAND, DE4X5_TPD);
3310
3311 netif_wake_queue(dev);
3312
3313 return;
3314}
3315
3316/*
3317** General PHY reset function. Some MII devices don't reset correctly
3318** since their MII address pins can float at voltages that are dependent
3319** on the signal pin use. Do a double reset to ensure a reset.
3320*/
3321static int
3322de4x5_reset_phy(struct net_device *dev)
3323{
3324 struct de4x5_private *lp = netdev_priv(dev);
3325 u_long iobase = dev->base_addr;
3326 int next_tick = 0;
3327
3328 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3329 if (lp->timeout < 0) {
3330 if (lp->useSROM) {
3331 if (lp->phy[lp->active].rst) {
3332 srom_exec(dev, lp->phy[lp->active].rst);
3333 srom_exec(dev, lp->phy[lp->active].rst);
3334 } else if (lp->rst) { /* Type 5 infoblock reset */
3335 srom_exec(dev, lp->rst);
3336 srom_exec(dev, lp->rst);
3337 }
3338 } else {
3339 PHY_HARD_RESET;
3340 }
3341 if (lp->useMII) {
3342 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3343 }
3344 }
3345 if (lp->useMII) {
3346 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3347 }
3348 } else if (lp->chipset == DC21140) {
3349 PHY_HARD_RESET;
3350 }
3351
3352 return next_tick;
3353}
3354
3355static int
3356test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3357{
3358 struct de4x5_private *lp = netdev_priv(dev);
3359 u_long iobase = dev->base_addr;
3360 s32 sts, csr12;
f3b197ac 3361
1da177e4
LT		 3362 if (lp->timeout < 0) {
3363 lp->timeout = msec/100;
3364 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3365 reset_init_sia(dev, csr13, csr14, csr15);
3366 }
3367
3368 /* set up the interrupt mask */
3369 outl(irq_mask, DE4X5_IMR);
3370
3371 /* clear all pending interrupts */
3372 sts = inl(DE4X5_STS);
3373 outl(sts, DE4X5_STS);
f3b197ac 3374
1da177e4
LT		 3375 /* clear csr12 NRA and SRA bits */
3376 if ((lp->chipset == DC21041) || lp->useSROM) {
3377 csr12 = inl(DE4X5_SISR);
3378 outl(csr12, DE4X5_SISR);
3379 }
3380 }
f3b197ac 3381
1da177e4 3382 sts = inl(DE4X5_STS) & ~TIMER_CB;
f3b197ac 3383
1da177e4
LT		 3384 if (!(sts & irqs) && --lp->timeout) {
3385 sts = 100 | TIMER_CB;
3386 } else {
3387 lp->timeout = -1;
3388 }
f3b197ac 3389
1da177e4
LT		 3390 return sts;
3391}
3392
3393static int
3394test_tp(struct net_device *dev, s32 msec)
3395{
3396 struct de4x5_private *lp = netdev_priv(dev);
3397 u_long iobase = dev->base_addr;
3398 int sisr;
f3b197ac 3399
1da177e4
LT		 3400 if (lp->timeout < 0) {
3401 lp->timeout = msec/100;
3402 }
f3b197ac 3403
1da177e4
LT		 3404 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3405
3406 if (sisr && --lp->timeout) {
3407 sisr = 100 | TIMER_CB;
3408 } else {
3409 lp->timeout = -1;
3410 }
f3b197ac 3411
1da177e4
LT		 3412 return sisr;
3413}
3414
3415/*
3416** Samples the 100Mb Link State Signal. The sample interval is important
3417** because too fast a rate can give erroneous results and confuse the
3418** speed sense algorithm.
3419*/
3420#define SAMPLE_INTERVAL 500 /* ms */
3421#define SAMPLE_DELAY 2000 /* ms */
3422static int
3423test_for_100Mb(struct net_device *dev, int msec)
3424{
3425 struct de4x5_private *lp = netdev_priv(dev);
3426 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3427
3428 if (lp->timeout < 0) {
3429 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3430 if (msec > SAMPLE_DELAY) {
3431 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3432 gep = SAMPLE_DELAY | TIMER_CB;
3433 return gep;
3434 } else {
3435 lp->timeout = msec/SAMPLE_INTERVAL;
3436 }
3437 }
f3b197ac 3438
1da177e4
LT		 3439 if (lp->phy[lp->active].id || lp->useSROM) {
3440 gep = is_100_up(dev) | is_spd_100(dev);
3441 } else {
3442 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3443 }
3444 if (!(gep & ret) && --lp->timeout) {
3445 gep = SAMPLE_INTERVAL | TIMER_CB;
3446 } else {
3447 lp->timeout = -1;
3448 }
f3b197ac 3449
1da177e4
LT		 3450 return gep;
3451}
3452
3453static int
3454wait_for_link(struct net_device *dev)
3455{
3456 struct de4x5_private *lp = netdev_priv(dev);
3457
3458 if (lp->timeout < 0) {
3459 lp->timeout = 1;
3460 }
f3b197ac 3461
1da177e4
LT		 3462 if (lp->timeout--) {
3463 return TIMER_CB;
3464 } else {
3465 lp->timeout = -1;
3466 }
f3b197ac 3467
1da177e4
LT		 3468 return 0;
3469}
3470
3471/*
3472**
3473**
3474*/
3475static int
3476test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3477{
3478 struct de4x5_private *lp = netdev_priv(dev);
3479 int test;
3480 u_long iobase = dev->base_addr;
f3b197ac 3481
1da177e4
LT		 3482 if (lp->timeout < 0) {
3483 lp->timeout = msec/100;
3484 }
f3b197ac 3485
1da177e4
LT		 3486 if (pol) pol = ~0;
3487 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3488 test = (reg ^ pol) & mask;
f3b197ac 3489
1da177e4
LT		 3490 if (test && --lp->timeout) {
3491 reg = 100 | TIMER_CB;
3492 } else {
3493 lp->timeout = -1;
3494 }
f3b197ac 3495
1da177e4
LT		 3496 return reg;
3497}
3498
3499static int
3500is_spd_100(struct net_device *dev)
3501{
3502 struct de4x5_private *lp = netdev_priv(dev);
3503 u_long iobase = dev->base_addr;
3504 int spd;
f3b197ac 3505
1da177e4
LT		 3506 if (lp->useMII) {
3507 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3508 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3509 spd &= lp->phy[lp->active].spd.mask;
3510 } else if (!lp->useSROM) { /* de500-xa */
3511 spd = ((~gep_rd(dev)) & GEP_SLNK);
3512 } else {
3513 if ((lp->ibn == 2) || !lp->asBitValid)
3514 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3515
3516 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3517 (lp->linkOK & ~lp->asBitValid);
3518 }
f3b197ac 3519
1da177e4
LT		 3520 return spd;
3521}
3522
3523static int
3524is_100_up(struct net_device *dev)
3525{
3526 struct de4x5_private *lp = netdev_priv(dev);
3527 u_long iobase = dev->base_addr;
f3b197ac 3528
1da177e4
LT		 3529 if (lp->useMII) {
3530 /* Double read for sticky bits & temporary drops */
3531 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3532 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3533 } else if (!lp->useSROM) { /* de500-xa */
3534 return ((~gep_rd(dev)) & GEP_SLNK);
3535 } else {
3536 if ((lp->ibn == 2) || !lp->asBitValid)
3537 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3538
3539 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3540 (lp->linkOK & ~lp->asBitValid));
3541 }
3542}
3543
3544static int
3545is_10_up(struct net_device *dev)
3546{
3547 struct de4x5_private *lp = netdev_priv(dev);
3548 u_long iobase = dev->base_addr;
f3b197ac 3549
1da177e4
LT		 3550 if (lp->useMII) {
3551 /* Double read for sticky bits & temporary drops */
3552 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3553 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3554 } else if (!lp->useSROM) { /* de500-xa */
3555 return ((~gep_rd(dev)) & GEP_LNP);
3556 } else {
3557 if ((lp->ibn == 2) || !lp->asBitValid)
3558 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3559 (~inl(DE4X5_SISR)&SISR_LS10):
3560 0);
3561
3562 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3563 (lp->linkOK & ~lp->asBitValid));
3564 }
3565}
3566
3567static int
3568is_anc_capable(struct net_device *dev)
3569{
3570 struct de4x5_private *lp = netdev_priv(dev);
3571 u_long iobase = dev->base_addr;
f3b197ac 3572
1da177e4
LT		 3573 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3574 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3575 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3576 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3577 } else {
3578 return 0;
3579 }
3580}
3581
3582/*
3583** Send a packet onto the media and watch for send errors that indicate the
3584** media is bad or unconnected.
3585*/
3586static int
3587ping_media(struct net_device *dev, int msec)
3588{
3589 struct de4x5_private *lp = netdev_priv(dev);
3590 u_long iobase = dev->base_addr;
3591 int sisr;
f3b197ac 3592
1da177e4
LT		 3593 if (lp->timeout < 0) {
3594 lp->timeout = msec/100;
f3b197ac 3595
1da177e4
LT		 3596 lp->tmp = lp->tx_new; /* Remember the ring position */
3597 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3598 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3599 outl(POLL_DEMAND, DE4X5_TPD);
3600 }
f3b197ac 3601
1da177e4
LT		 3602 sisr = inl(DE4X5_SISR);
3603
f3b197ac
JG		 3604 if ((!(sisr & SISR_NCR)) &&
3605 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
1da177e4
LT		 3606 (--lp->timeout)) {
3607 sisr = 100 | TIMER_CB;
3608 } else {
f3b197ac 3609 if ((!(sisr & SISR_NCR)) &&
1da177e4
LT		 3610 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3611 lp->timeout) {
3612 sisr = 0;
3613 } else {
3614 sisr = 1;
3615 }
3616 lp->timeout = -1;
3617 }
f3b197ac 3618
1da177e4
LT		 3619 return sisr;
3620}
3621
3622/*
3623** This function does 2 things: on Intels it kmalloc's another buffer to
3624** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3625** into which the packet is copied.
3626*/
3627static struct sk_buff *
3628de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3629{
3630 struct de4x5_private *lp = netdev_priv(dev);
3631 struct sk_buff *p;
3632
3633#if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3634 struct sk_buff *ret;
3635 u_long i=0, tmp;
3636
3637 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3638 if (!p) return NULL;
3639
3640 p->dev = dev;
3641 tmp = virt_to_bus(p->data);
3642 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3643 skb_reserve(p, i);
3644 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3645
3646 ret = lp->rx_skb[index];
3647 lp->rx_skb[index] = p;
3648
3649 if ((u_long) ret > 1) {
3650 skb_put(ret, len);
3651 }
3652
3653 return ret;
3654
3655#else
3656 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3657
3658 p = dev_alloc_skb(len + 2);
3659 if (!p) return NULL;
3660
3661 p->dev = dev;
3662 skb_reserve(p, 2); /* Align */
3663 if (index < lp->rx_old) { /* Wrapped buffer */
3664 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3665 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3666 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3667 } else { /* Linear buffer */
3668 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3669 }
f3b197ac 3670
1da177e4
LT		 3671 return p;
3672#endif
3673}
3674
3675static void
3676de4x5_free_rx_buffs(struct net_device *dev)
3677{
3678 struct de4x5_private *lp = netdev_priv(dev);
3679 int i;
3680
3681 for (i=0; i<lp->rxRingSize; i++) {
3682 if ((u_long) lp->rx_skb[i] > 1) {
3683 dev_kfree_skb(lp->rx_skb[i]);
3684 }
3685 lp->rx_ring[i].status = 0;
3686 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3687 }
3688
3689 return;
3690}
3691
3692static void
3693de4x5_free_tx_buffs(struct net_device *dev)
3694{
3695 struct de4x5_private *lp = netdev_priv(dev);
3696 int i;
3697
3698 for (i=0; i<lp->txRingSize; i++) {
3699 if (lp->tx_skb[i])
3700 de4x5_free_tx_buff(lp, i);
3701 lp->tx_ring[i].status = 0;
3702 }
3703
3704 /* Unload the locally queued packets */
3705 while (lp->cache.skb) {
3706 dev_kfree_skb(de4x5_get_cache(dev));
3707 }
3708
3709 return;
3710}
3711
3712/*
3713** When a user pulls a connection, the DECchip can end up in a
3714** 'running - waiting for end of transmission' state. This means that we
3715** have to perform a chip soft reset to ensure that we can synchronize
3716** the hardware and software and make any media probes using a loopback
3717** packet meaningful.
3718*/
3719static void
3720de4x5_save_skbs(struct net_device *dev)
3721{
3722 struct de4x5_private *lp = netdev_priv(dev);
3723 u_long iobase = dev->base_addr;
3724 s32 omr;
3725
3726 if (!lp->cache.save_cnt) {
3727 STOP_DE4X5;
3728 de4x5_tx(dev); /* Flush any sent skb's */
3729 de4x5_free_tx_buffs(dev);
3730 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3731 de4x5_sw_reset(dev);
3732 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3733 lp->cache.save_cnt++;
3734 START_DE4X5;
3735 }
3736
3737 return;
3738}
3739
3740static void
3741de4x5_rst_desc_ring(struct net_device *dev)
3742{
3743 struct de4x5_private *lp = netdev_priv(dev);
3744 u_long iobase = dev->base_addr;
3745 int i;
3746 s32 omr;
3747
3748 if (lp->cache.save_cnt) {
3749 STOP_DE4X5;
3750 outl(lp->dma_rings, DE4X5_RRBA);
3751 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3752 DE4X5_TRBA);
f3b197ac 3753
1da177e4
LT		 3754 lp->rx_new = lp->rx_old = 0;
3755 lp->tx_new = lp->tx_old = 0;
f3b197ac 3756
1da177e4
LT		 3757 for (i = 0; i < lp->rxRingSize; i++) {
3758 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3759 }
f3b197ac 3760
1da177e4
LT		 3761 for (i = 0; i < lp->txRingSize; i++) {
3762 lp->tx_ring[i].status = cpu_to_le32(0);
3763 }
f3b197ac 3764
1da177e4
LT		 3765 barrier();
3766 lp->cache.save_cnt--;
3767 START_DE4X5;
3768 }
f3b197ac 3769
1da177e4
LT		 3770 return;
3771}
3772
3773static void
3774de4x5_cache_state(struct net_device *dev, int flag)
3775{
3776 struct de4x5_private *lp = netdev_priv(dev);
3777 u_long iobase = dev->base_addr;
3778
3779 switch(flag) {
3780 case DE4X5_SAVE_STATE:
3781 lp->cache.csr0 = inl(DE4X5_BMR);
3782 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3783 lp->cache.csr7 = inl(DE4X5_IMR);
3784 break;
3785
3786 case DE4X5_RESTORE_STATE:
3787 outl(lp->cache.csr0, DE4X5_BMR);
3788 outl(lp->cache.csr6, DE4X5_OMR);
3789 outl(lp->cache.csr7, DE4X5_IMR);
3790 if (lp->chipset == DC21140) {
3791 gep_wr(lp->cache.gepc, dev);
3792 gep_wr(lp->cache.gep, dev);
3793 } else {
f3b197ac 3794 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
1da177e4
LT		 3795 lp->cache.csr15);
3796 }
3797 break;
3798 }
3799
3800 return;
3801}
3802
3803static void
3804de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3805{
3806 struct de4x5_private *lp = netdev_priv(dev);
3807 struct sk_buff *p;
3808
3809 if (lp->cache.skb) {
3810 for (p=lp->cache.skb; p->next; p=p->next);
3811 p->next = skb;
3812 } else {
3813 lp->cache.skb = skb;
3814 }
3815 skb->next = NULL;
3816
3817 return;
3818}
3819
3820static void
3821de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3822{
3823 struct de4x5_private *lp = netdev_priv(dev);
3824 struct sk_buff *p = lp->cache.skb;
3825
3826 lp->cache.skb = skb;
3827 skb->next = p;
3828
3829 return;
3830}
3831
3832static struct sk_buff *
3833de4x5_get_cache(struct net_device *dev)
3834{
3835 struct de4x5_private *lp = netdev_priv(dev);
3836 struct sk_buff *p = lp->cache.skb;
3837
3838 if (p) {
3839 lp->cache.skb = p->next;
3840 p->next = NULL;
3841 }
3842
3843 return p;
3844}
3845
3846/*
3847** Check the Auto Negotiation State. Return OK when a link pass interrupt
3848** is received and the auto-negotiation status is NWAY OK.
3849*/
3850static int
3851test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3852{
3853 struct de4x5_private *lp = netdev_priv(dev);
3854 u_long iobase = dev->base_addr;
3855 s32 sts, ans;
f3b197ac 3856
1da177e4
LT		 3857 if (lp->timeout < 0) {
3858 lp->timeout = msec/100;
3859 outl(irq_mask, DE4X5_IMR);
f3b197ac 3860
1da177e4
LT		 3861 /* clear all pending interrupts */
3862 sts = inl(DE4X5_STS);
3863 outl(sts, DE4X5_STS);
3864 }
f3b197ac 3865
1da177e4
LT		 3866 ans = inl(DE4X5_SISR) & SISR_ANS;
3867 sts = inl(DE4X5_STS) & ~TIMER_CB;
f3b197ac 3868
1da177e4
LT		 3869 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3870 sts = 100 | TIMER_CB;
3871 } else {
3872 lp->timeout = -1;
3873 }
f3b197ac 3874
1da177e4
LT		 3875 return sts;
3876}
3877
3878static void
3879de4x5_setup_intr(struct net_device *dev)
3880{
3881 struct de4x5_private *lp = netdev_priv(dev);
3882 u_long iobase = dev->base_addr;
3883 s32 imr, sts;
f3b197ac 3884
1da177e4
LT		 3885 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3886 imr = 0;
3887 UNMASK_IRQs;
3888 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3889 outl(sts, DE4X5_STS);
3890 ENABLE_IRQs;
3891 }
f3b197ac 3892
1da177e4
LT		 3893 return;
3894}
3895
3896/*
3897**
3898*/
3899static void
3900reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3901{
3902 struct de4x5_private *lp = netdev_priv(dev);
3903 u_long iobase = dev->base_addr;
3904
3905 RESET_SIA;
3906 if (lp->useSROM) {
3907 if (lp->ibn == 3) {
3908 srom_exec(dev, lp->phy[lp->active].rst);
3909 srom_exec(dev, lp->phy[lp->active].gep);
3910 outl(1, DE4X5_SICR);
3911 return;
3912 } else {
3913 csr15 = lp->cache.csr15;
3914 csr14 = lp->cache.csr14;
3915 csr13 = lp->cache.csr13;
3916 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3917 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3918 }
3919 } else {
3920 outl(csr15, DE4X5_SIGR);
3921 }
3922 outl(csr14, DE4X5_STRR);
3923 outl(csr13, DE4X5_SICR);
3924
3925 mdelay(10);
3926
3927 return;
3928}
3929
3930/*
3931** Create a loopback ethernet packet
3932*/
3933static void
3934create_packet(struct net_device *dev, char *frame, int len)
3935{
3936 int i;
3937 char *buf = frame;
f3b197ac 3938
1da177e4
LT		 3939 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3940 *buf++ = dev->dev_addr[i];
3941 }
3942 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3943 *buf++ = dev->dev_addr[i];
3944 }
f3b197ac 3945
1da177e4
LT		 3946 *buf++ = 0; /* Packet length (2 bytes) */
3947 *buf++ = 1;
f3b197ac 3948
1da177e4
LT		 3949 return;
3950}
3951
3952/*
3953** Look for a particular board name in the EISA configuration space
3954*/
3955static int
3956EISA_signature(char *name, struct device *device)
3957{
3958 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3959 struct eisa_device *edev;
3960
3961 *name = '\0';
3962 edev = to_eisa_device (device);
3963 i = edev->id.driver_data;
3964
3965 if (i >= 0 && i < siglen) {
3966 strcpy (name, de4x5_signatures[i]);
3967 status = 1;
3968 }
3969
3970 return status; /* return the device name string */
3971}
3972
3973/*
3974** Look for a particular board name in the PCI configuration space
3975*/
3976static int
3977PCI_signature(char *name, struct de4x5_private *lp)
3978{
3979 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
f3b197ac 3980
1da177e4
LT		 3981 if (lp->chipset == DC21040) {
3982 strcpy(name, "DE434/5");
3983 return status;
3984 } else { /* Search for a DEC name in the SROM */
3985 int i = *((char *)&lp->srom + 19) * 3;
3986 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3987 }
3988 name[8] = '\0';
3989 for (i=0; i<siglen; i++) {
3990 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3991 }
3992 if (i == siglen) {
3993 if (dec_only) {
3994 *name = '\0';
3995 } else { /* Use chip name to avoid confusion */
3996 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3997 ((lp->chipset == DC21041) ? "DC21041" :
3998 ((lp->chipset == DC21140) ? "DC21140" :
3999 ((lp->chipset == DC21142) ? "DC21142" :
4000 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
4001 )))))));
4002 }
4003 if (lp->chipset != DC21041) {
4004 lp->useSROM = TRUE; /* card is not recognisably DEC */
4005 }
4006 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4007 lp->useSROM = TRUE;
4008 }
f3b197ac 4009
1da177e4
LT		 4010 return status;
4011}
4012
4013/*
4014** Set up the Ethernet PROM counter to the start of the Ethernet address on
4015** the DC21040, else read the SROM for the other chips.
4016** The SROM may not be present in a multi-MAC card, so first read the
4017** MAC address and check for a bad address. If there is a bad one then exit
4018** immediately with the prior srom contents intact (the h/w address will
4019** be fixed up later).
4020*/
4021static void
4022DevicePresent(struct net_device *dev, u_long aprom_addr)
4023{
4024 int i, j=0;
4025 struct de4x5_private *lp = netdev_priv(dev);
f3b197ac 4026
1da177e4
LT		 4027 if (lp->chipset == DC21040) {
4028 if (lp->bus == EISA) {
4029 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4030 } else {
4031 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4032 }
4033 } else { /* Read new srom */
4034 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4035 for (i=0; i<(ETH_ALEN>>1); i++) {
4036 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4037 *p = le16_to_cpu(tmp);
4038 j += *p++;
4039 }
4040 if ((j == 0) || (j == 0x2fffd)) {
4041 return;
4042 }
4043
4044 p=(short *)&lp->srom;
4045 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4046 tmp = srom_rd(aprom_addr, i);
4047 *p++ = le16_to_cpu(tmp);
4048 }
4049 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4050 }
f3b197ac 4051
1da177e4
LT		 4052 return;
4053}
4054
4055/*
4056** Since the write on the Enet PROM register doesn't seem to reset the PROM
4057** pointer correctly (at least on my DE425 EISA card), this routine should do
4058** it...from depca.c.
4059*/
4060static void
4061enet_addr_rst(u_long aprom_addr)
4062{
4063 union {
4064 struct {
4065 u32 a;
4066 u32 b;
4067 } llsig;
4068 char Sig[sizeof(u32) << 1];
4069 } dev;
4070 short sigLength=0;
4071 s8 data;
4072 int i, j;
f3b197ac 4073
1da177e4
LT		 4074 dev.llsig.a = ETH_PROM_SIG;
4075 dev.llsig.b = ETH_PROM_SIG;
4076 sigLength = sizeof(u32) << 1;
f3b197ac 4077
1da177e4
LT		 4078 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4079 data = inb(aprom_addr);
4080 if (dev.Sig[j] == data) { /* track signature */
4081 j++;
4082 } else { /* lost signature; begin search again */
4083 if (data == dev.Sig[0]) { /* rare case.... */
4084 j=1;
4085 } else {
4086 j=0;
4087 }
4088 }
4089 }
f3b197ac 4090
1da177e4
LT		 4091 return;
4092}
4093
4094/*
4095** For the bad status case and no SROM, then add one to the previous
4096** address. However, need to add one backwards in case we have 0xff
4097** as one or more of the bytes. Only the last 3 bytes should be checked
4098** as the first three are invariant - assigned to an organisation.
4099*/
4100static int
4101get_hw_addr(struct net_device *dev)
4102{
4103 u_long iobase = dev->base_addr;
4104 int broken, i, k, tmp, status = 0;
4105 u_short j,chksum;
4106 struct de4x5_private *lp = netdev_priv(dev);
4107
4108 broken = de4x5_bad_srom(lp);
4109
4110 for (i=0,k=0,j=0;j<3;j++) {
4111 k <<= 1;
4112 if (k > 0xffff) k-=0xffff;
f3b197ac 4113
1da177e4
LT		 4114 if (lp->bus == PCI) {
4115 if (lp->chipset == DC21040) {
4116 while ((tmp = inl(DE4X5_APROM)) < 0);
4117 k += (u_char) tmp;
4118 dev->dev_addr[i++] = (u_char) tmp;
4119 while ((tmp = inl(DE4X5_APROM)) < 0);
4120 k += (u_short) (tmp << 8);
4121 dev->dev_addr[i++] = (u_char) tmp;
4122 } else if (!broken) {
4123 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4124 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4125 } else if ((broken == SMC) || (broken == ACCTON)) {
4126 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4127 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4128 }
4129 } else {
4130 k += (u_char) (tmp = inb(EISA_APROM));
4131 dev->dev_addr[i++] = (u_char) tmp;
4132 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4133 dev->dev_addr[i++] = (u_char) tmp;
4134 }
f3b197ac 4135
1da177e4
LT		 4136 if (k > 0xffff) k-=0xffff;
4137 }
4138 if (k == 0xffff) k=0;
f3b197ac 4139
1da177e4
LT		 4140 if (lp->bus == PCI) {
4141 if (lp->chipset == DC21040) {
4142 while ((tmp = inl(DE4X5_APROM)) < 0);
4143 chksum = (u_char) tmp;
4144 while ((tmp = inl(DE4X5_APROM)) < 0);
4145 chksum |= (u_short) (tmp << 8);
4146 if ((k != chksum) && (dec_only)) status = -1;
4147 }
4148 } else {
4149 chksum = (u_char) inb(EISA_APROM);
4150 chksum |= (u_short) (inb(EISA_APROM) << 8);
4151 if ((k != chksum) && (dec_only)) status = -1;
4152 }
4153
4154 /* If possible, try to fix a broken card - SMC only so far */
4155 srom_repair(dev, broken);
4156
4157#ifdef CONFIG_PPC_MULTIPLATFORM
f3b197ac 4158 /*
1da177e4
LT		 4159 ** If the address starts with 00 a0, we have to bit-reverse
4160 ** each byte of the address.
4161 */
e8222502 4162 if ( machine_is(powermac) &&
1da177e4
LT		 4163 (dev->dev_addr[0] == 0) &&
4164 (dev->dev_addr[1] == 0xa0) )
4165 {
4166 for (i = 0; i < ETH_ALEN; ++i)
4167 {
4168 int x = dev->dev_addr[i];
4169 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4170 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4171 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4172 }
4173 }
4174#endif /* CONFIG_PPC_MULTIPLATFORM */
4175
4176 /* Test for a bad enet address */
4177 status = test_bad_enet(dev, status);
4178
4179 return status;
4180}
4181
4182/*
4183** Test for enet addresses in the first 32 bytes. The built-in strncmp
4184** didn't seem to work here...?
4185*/
4186static int
4187de4x5_bad_srom(struct de4x5_private *lp)
4188{
4189 int i, status = 0;
4190
4191 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4192 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4193 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4194 if (i == 0) {
4195 status = SMC;
4196 } else if (i == 1) {
4197 status = ACCTON;
4198 }
4199 break;
4200 }
4201 }
4202
4203 return status;
4204}
4205
4206static int
4207de4x5_strncmp(char *a, char *b, int n)
4208{
4209 int ret=0;
4210
4211 for (;n && !ret;n--) {
4212 ret = *a++ - *b++;
4213 }
4214
4215 return ret;
4216}
4217
4218static void
4219srom_repair(struct net_device *dev, int card)
4220{
4221 struct de4x5_private *lp = netdev_priv(dev);
4222
4223 switch(card) {
4224 case SMC:
4225 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4226 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4227 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4228 lp->useSROM = TRUE;
4229 break;
4230 }
4231
4232 return;
4233}
4234
4235/*
4236** Assume that the irq's do not follow the PCI spec - this is seems
4237** to be true so far (2 for 2).
4238*/
4239static int
4240test_bad_enet(struct net_device *dev, int status)
4241{
4242 struct de4x5_private *lp = netdev_priv(dev);
4243 int i, tmp;
4244
4245 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4246 if ((tmp == 0) || (tmp == 0x5fa)) {
f3b197ac 4247 if ((lp->chipset == last.chipset) &&
1da177e4
LT		 4248 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4249 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4250 for (i=ETH_ALEN-1; i>2; --i) {
4251 dev->dev_addr[i] += 1;
4252 if (dev->dev_addr[i] != 0) break;
4253 }
4254 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4255 if (!an_exception(lp)) {
4256 dev->irq = last.irq;
4257 }
4258
4259 status = 0;
4260 }
4261 } else if (!status) {
4262 last.chipset = lp->chipset;
4263 last.bus = lp->bus_num;
4264 last.irq = dev->irq;
4265 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4266 }
4267
4268 return status;
4269}
4270
4271/*
4272** List of board exceptions with correctly wired IRQs
4273*/
4274static int
4275an_exception(struct de4x5_private *lp)
4276{
f3b197ac 4277 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
1da177e4
LT		 4278 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4279 return -1;
4280 }
4281
4282 return 0;
4283}
4284
4285/*
4286** SROM Read
4287*/
4288static short
4289srom_rd(u_long addr, u_char offset)
4290{
4291 sendto_srom(SROM_RD | SROM_SR, addr);
f3b197ac 4292
1da177e4
LT		 4293 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4294 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4295 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
f3b197ac 4296
1da177e4
LT		 4297 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4298}
4299
4300static void
4301srom_latch(u_int command, u_long addr)
4302{
4303 sendto_srom(command, addr);
4304 sendto_srom(command | DT_CLK, addr);
4305 sendto_srom(command, addr);
f3b197ac 4306
1da177e4
LT		 4307 return;
4308}
4309
4310static void
4311srom_command(u_int command, u_long addr)
4312{
4313 srom_latch(command, addr);
4314 srom_latch(command, addr);
4315 srom_latch((command & 0x0000ff00) | DT_CS, addr);
f3b197ac 4316
1da177e4
LT		 4317 return;
4318}
4319
4320static void
4321srom_address(u_int command, u_long addr, u_char offset)
4322{
4323 int i, a;
f3b197ac 4324
1da177e4
LT		 4325 a = offset << 2;
4326 for (i=0; i<6; i++, a <<= 1) {
4327 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4328 }
4329 udelay(1);
f3b197ac 4330
1da177e4 4331 i = (getfrom_srom(addr) >> 3) & 0x01;
f3b197ac 4332
1da177e4
LT		 4333 return;
4334}
4335
4336static short
4337srom_data(u_int command, u_long addr)
4338{
4339 int i;
4340 short word = 0;
4341 s32 tmp;
f3b197ac 4342
1da177e4
LT		 4343 for (i=0; i<16; i++) {
4344 sendto_srom(command | DT_CLK, addr);
4345 tmp = getfrom_srom(addr);
4346 sendto_srom(command, addr);
f3b197ac 4347
1da177e4
LT		 4348 word = (word << 1) | ((tmp >> 3) & 0x01);
4349 }
f3b197ac 4350
1da177e4 4351 sendto_srom(command & 0x0000ff00, addr);
f3b197ac 4352
1da177e4
LT		 4353 return word;
4354}
4355
4356/*
4357static void
4358srom_busy(u_int command, u_long addr)
4359{
4360 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
f3b197ac 4361
1da177e4
LT		 4362 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4363 mdelay(1);
4364 }
f3b197ac 4365
1da177e4 4366 sendto_srom(command & 0x0000ff00, addr);
f3b197ac 4367
1da177e4
LT		 4368 return;
4369}
4370*/
4371
4372static void
4373sendto_srom(u_int command, u_long addr)
4374{
4375 outl(command, addr);
4376 udelay(1);
f3b197ac 4377
1da177e4
LT		 4378 return;
4379}
4380
4381static int
4382getfrom_srom(u_long addr)
4383{
4384 s32 tmp;
f3b197ac 4385
1da177e4
LT		 4386 tmp = inl(addr);
4387 udelay(1);
f3b197ac 4388
1da177e4
LT		 4389 return tmp;
4390}
4391
4392static int
4393srom_infoleaf_info(struct net_device *dev)
4394{
4395 struct de4x5_private *lp = netdev_priv(dev);
4396 int i, count;
4397 u_char *p;
4398
4399 /* Find the infoleaf decoder function that matches this chipset */
4400 for (i=0; i<INFOLEAF_SIZE; i++) {
4401 if (lp->chipset == infoleaf_array[i].chipset) break;
4402 }
4403 if (i == INFOLEAF_SIZE) {
4404 lp->useSROM = FALSE;
f3b197ac 4405 printk("%s: Cannot find correct chipset for SROM decoding!\n",
1da177e4
LT		 4406 dev->name);
4407 return -ENXIO;
4408 }
4409
4410 lp->infoleaf_fn = infoleaf_array[i].fn;
4411
4412 /* Find the information offset that this function should use */
4413 count = *((u_char *)&lp->srom + 19);
4414 p = (u_char *)&lp->srom + 26;
4415
4416 if (count > 1) {
4417 for (i=count; i; --i, p+=3) {
4418 if (lp->device == *p) break;
4419 }
4420 if (i == 0) {
4421 lp->useSROM = FALSE;
f3b197ac 4422 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
1da177e4
LT		 4423 dev->name, lp->device);
4424 return -ENXIO;
4425 }
4426 }
4427
4428 lp->infoleaf_offset = TWIDDLE(p+1);
4429
4430 return 0;
4431}
4432
4433/*
4434** This routine loads any type 1 or 3 MII info into the mii device
4435** struct and executes any type 5 code to reset PHY devices for this
4436** controller.
4437** The info for the MII devices will be valid since the index used
4438** will follow the discovery process from MII address 1-31 then 0.
4439*/
4440static void
4441srom_init(struct net_device *dev)
4442{
4443 struct de4x5_private *lp = netdev_priv(dev);
4444 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4445 u_char count;
4446
4447 p+=2;
4448 if (lp->chipset == DC21140) {
4449 lp->cache.gepc = (*p++ | GEP_CTRL);
4450 gep_wr(lp->cache.gepc, dev);
4451 }
4452
4453 /* Block count */
4454 count = *p++;
4455
4456 /* Jump the infoblocks to find types */
4457 for (;count; --count) {
4458 if (*p < 128) {
4459 p += COMPACT_LEN;
4460 } else if (*(p+1) == 5) {
4461 type5_infoblock(dev, 1, p);
4462 p += ((*p & BLOCK_LEN) + 1);
4463 } else if (*(p+1) == 4) {
4464 p += ((*p & BLOCK_LEN) + 1);
4465 } else if (*(p+1) == 3) {
4466 type3_infoblock(dev, 1, p);
4467 p += ((*p & BLOCK_LEN) + 1);
4468 } else if (*(p+1) == 2) {
4469 p += ((*p & BLOCK_LEN) + 1);
4470 } else if (*(p+1) == 1) {
4471 type1_infoblock(dev, 1, p);
4472 p += ((*p & BLOCK_LEN) + 1);
4473 } else {
4474 p += ((*p & BLOCK_LEN) + 1);
4475 }
4476 }
4477
4478 return;
4479}
4480
4481/*
4482** A generic routine that writes GEP control, data and reset information
4483** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4484*/
4485static void
4486srom_exec(struct net_device *dev, u_char *p)
4487{
4488 struct de4x5_private *lp = netdev_priv(dev);
4489 u_long iobase = dev->base_addr;
4490 u_char count = (p ? *p++ : 0);
4491 u_short *w = (u_short *)p;
4492
4493 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4494
4495 if (lp->chipset != DC21140) RESET_SIA;
f3b197ac 4496
1da177e4 4497 while (count--) {
f3b197ac 4498 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
1da177e4
LT		 4499 *p++ : TWIDDLE(w++)), dev);
4500 mdelay(2); /* 2ms per action */
4501 }
4502
4503 if (lp->chipset != DC21140) {
4504 outl(lp->cache.csr14, DE4X5_STRR);
4505 outl(lp->cache.csr13, DE4X5_SICR);
4506 }
4507
4508 return;
4509}
4510
4511/*
4512** Basically this function is a NOP since it will never be called,
4513** unless I implement the DC21041 SROM functions. There's no need
4514** since the existing code will be satisfactory for all boards.
4515*/
f3b197ac 4516static int
1da177e4
LT		 4517dc21041_infoleaf(struct net_device *dev)
4518{
4519 return DE4X5_AUTOSENSE_MS;
4520}
4521
f3b197ac 4522static int
1da177e4
LT		 4523dc21140_infoleaf(struct net_device *dev)
4524{
4525 struct de4x5_private *lp = netdev_priv(dev);
4526 u_char count = 0;
4527 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4528 int next_tick = DE4X5_AUTOSENSE_MS;
4529
4530 /* Read the connection type */
4531 p+=2;
4532
4533 /* GEP control */
4534 lp->cache.gepc = (*p++ | GEP_CTRL);
4535
4536 /* Block count */
4537 count = *p++;
4538
4539 /* Recursively figure out the info blocks */
4540 if (*p < 128) {
4541 next_tick = dc_infoblock[COMPACT](dev, count, p);
4542 } else {
4543 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4544 }
4545
4546 if (lp->tcount == count) {
4547 lp->media = NC;
4548 if (lp->media != lp->c_media) {
4549 de4x5_dbg_media(dev);
4550 lp->c_media = lp->media;
4551 }
4552 lp->media = INIT;
4553 lp->tcount = 0;
4554 lp->tx_enable = FALSE;
4555 }
4556
4557 return next_tick & ~TIMER_CB;
4558}
4559
f3b197ac 4560static int
1da177e4
LT		 4561dc21142_infoleaf(struct net_device *dev)
4562{
4563 struct de4x5_private *lp = netdev_priv(dev);
4564 u_char count = 0;
4565 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4566 int next_tick = DE4X5_AUTOSENSE_MS;
4567
4568 /* Read the connection type */
4569 p+=2;
4570
4571 /* Block count */
4572 count = *p++;
4573
4574 /* Recursively figure out the info blocks */
4575 if (*p < 128) {
4576 next_tick = dc_infoblock[COMPACT](dev, count, p);
4577 } else {
4578 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4579 }
4580
4581 if (lp->tcount == count) {
4582 lp->media = NC;
4583 if (lp->media != lp->c_media) {
4584 de4x5_dbg_media(dev);
4585 lp->c_media = lp->media;
4586 }
4587 lp->media = INIT;
4588 lp->tcount = 0;
4589 lp->tx_enable = FALSE;
4590 }
4591
4592 return next_tick & ~TIMER_CB;
4593}
4594
f3b197ac 4595static int
1da177e4
LT		 4596dc21143_infoleaf(struct net_device *dev)
4597{
4598 struct de4x5_private *lp = netdev_priv(dev);
4599 u_char count = 0;
4600 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4601 int next_tick = DE4X5_AUTOSENSE_MS;
4602
4603 /* Read the connection type */
4604 p+=2;
4605
4606 /* Block count */
4607 count = *p++;
4608
4609 /* Recursively figure out the info blocks */
4610 if (*p < 128) {
4611 next_tick = dc_infoblock[COMPACT](dev, count, p);
4612 } else {
4613 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4614 }
4615 if (lp->tcount == count) {
4616 lp->media = NC;
4617 if (lp->media != lp->c_media) {
4618 de4x5_dbg_media(dev);
4619 lp->c_media = lp->media;
4620 }
4621 lp->media = INIT;
4622 lp->tcount = 0;
4623 lp->tx_enable = FALSE;
4624 }
4625
4626 return next_tick & ~TIMER_CB;
4627}
4628
4629/*
4630** The compact infoblock is only designed for DC21140[A] chips, so
4631** we'll reuse the dc21140m_autoconf function. Non MII media only.
4632*/
f3b197ac 4633static int
1da177e4
LT		 4634compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4635{
4636 struct de4x5_private *lp = netdev_priv(dev);
4637 u_char flags, csr6;
4638
4639 /* Recursively figure out the info blocks */
4640 if (--count > lp->tcount) {
4641 if (*(p+COMPACT_LEN) < 128) {
4642 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4643 } else {
4644 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4645 }
4646 }
4647
4648 if ((lp->media == INIT) && (lp->timeout < 0)) {
4649 lp->ibn = COMPACT;
4650 lp->active = 0;
4651 gep_wr(lp->cache.gepc, dev);
4652 lp->infoblock_media = (*p++) & COMPACT_MC;
4653 lp->cache.gep = *p++;
4654 csr6 = *p++;
4655 flags = *p++;
4656
4657 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4658 lp->defMedium = (flags & 0x40) ? -1 : 0;
4659 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4660 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4661 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4662 lp->useMII = FALSE;
4663
4664 de4x5_switch_mac_port(dev);
4665 }
4666
4667 return dc21140m_autoconf(dev);
4668}
4669
4670/*
4671** This block describes non MII media for the DC21140[A] only.
4672*/
f3b197ac 4673static int
1da177e4
LT		 4674type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4675{
4676 struct de4x5_private *lp = netdev_priv(dev);
4677 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4678
4679 /* Recursively figure out the info blocks */
4680 if (--count > lp->tcount) {
4681 if (*(p+len) < 128) {
4682 return dc_infoblock[COMPACT](dev, count, p+len);
4683 } else {
4684 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4685 }
4686 }
4687
4688 if ((lp->media == INIT) && (lp->timeout < 0)) {
4689 lp->ibn = 0;
4690 lp->active = 0;
4691 gep_wr(lp->cache.gepc, dev);
4692 p+=2;
4693 lp->infoblock_media = (*p++) & BLOCK0_MC;
4694 lp->cache.gep = *p++;
4695 csr6 = *p++;
4696 flags = *p++;
4697
4698 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4699 lp->defMedium = (flags & 0x40) ? -1 : 0;
4700 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4701 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4702 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4703 lp->useMII = FALSE;
4704
4705 de4x5_switch_mac_port(dev);
4706 }
4707
4708 return dc21140m_autoconf(dev);
4709}
4710
4711/* These functions are under construction! */
4712
f3b197ac 4713static int
1da177e4
LT		 4714type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4715{
4716 struct de4x5_private *lp = netdev_priv(dev);
4717 u_char len = (*p & BLOCK_LEN)+1;
4718
4719 /* Recursively figure out the info blocks */
4720 if (--count > lp->tcount) {
4721 if (*(p+len) < 128) {
4722 return dc_infoblock[COMPACT](dev, count, p+len);
4723 } else {
4724 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4725 }
4726 }
4727
4728 p += 2;
4729 if (lp->state == INITIALISED) {
4730 lp->ibn = 1;
4731 lp->active = *p++;
4732 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4733 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4734 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4735 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4736 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4737 lp->phy[lp->active].ttm = TWIDDLE(p);
4738 return 0;
4739 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4740 lp->ibn = 1;
4741 lp->active = *p;
4742 lp->infoblock_csr6 = OMR_MII_100;
4743 lp->useMII = TRUE;
4744 lp->infoblock_media = ANS;
4745
4746 de4x5_switch_mac_port(dev);
4747 }
4748
4749 return dc21140m_autoconf(dev);
4750}
4751
f3b197ac 4752static int
1da177e4
LT		 4753type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4754{
4755 struct de4x5_private *lp = netdev_priv(dev);
4756 u_char len = (*p & BLOCK_LEN)+1;
4757
4758 /* Recursively figure out the info blocks */
4759 if (--count > lp->tcount) {
4760 if (*(p+len) < 128) {
4761 return dc_infoblock[COMPACT](dev, count, p+len);
4762 } else {
4763 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4764 }
4765 }
4766
4767 if ((lp->media == INIT) && (lp->timeout < 0)) {
4768 lp->ibn = 2;
4769 lp->active = 0;
4770 p += 2;
4771 lp->infoblock_media = (*p) & MEDIA_CODE;
4772
4773 if ((*p++) & EXT_FIELD) {
4774 lp->cache.csr13 = TWIDDLE(p); p += 2;
4775 lp->cache.csr14 = TWIDDLE(p); p += 2;
4776 lp->cache.csr15 = TWIDDLE(p); p += 2;
4777 } else {
4778 lp->cache.csr13 = CSR13;
4779 lp->cache.csr14 = CSR14;
4780 lp->cache.csr15 = CSR15;
4781 }
4782 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4783 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4784 lp->infoblock_csr6 = OMR_SIA;
4785 lp->useMII = FALSE;
4786
4787 de4x5_switch_mac_port(dev);
4788 }
4789
4790 return dc2114x_autoconf(dev);
4791}
4792
f3b197ac 4793static int
1da177e4
LT		 4794type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4795{
4796 struct de4x5_private *lp = netdev_priv(dev);
4797 u_char len = (*p & BLOCK_LEN)+1;
4798
4799 /* Recursively figure out the info blocks */
4800 if (--count > lp->tcount) {
4801 if (*(p+len) < 128) {
4802 return dc_infoblock[COMPACT](dev, count, p+len);
4803 } else {
4804 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4805 }
4806 }
4807
4808 p += 2;
4809 if (lp->state == INITIALISED) {
4810 lp->ibn = 3;
4811 lp->active = *p++;
4812 if (MOTO_SROM_BUG) lp->active = 0;
4813 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4814 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4815 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4816 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4817 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4818 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4819 lp->phy[lp->active].mci = *p;
4820 return 0;
4821 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4822 lp->ibn = 3;
4823 lp->active = *p;
4824 if (MOTO_SROM_BUG) lp->active = 0;
4825 lp->infoblock_csr6 = OMR_MII_100;
4826 lp->useMII = TRUE;
4827 lp->infoblock_media = ANS;
4828
4829 de4x5_switch_mac_port(dev);
4830 }
4831
4832 return dc2114x_autoconf(dev);
4833}
4834
f3b197ac 4835static int
1da177e4
LT		 4836type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4837{
4838 struct de4x5_private *lp = netdev_priv(dev);
4839 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4840
4841 /* Recursively figure out the info blocks */
4842 if (--count > lp->tcount) {
4843 if (*(p+len) < 128) {
4844 return dc_infoblock[COMPACT](dev, count, p+len);
4845 } else {
4846 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4847 }
4848 }
4849
4850 if ((lp->media == INIT) && (lp->timeout < 0)) {
4851 lp->ibn = 4;
4852 lp->active = 0;
4853 p+=2;
4854 lp->infoblock_media = (*p++) & MEDIA_CODE;
4855 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4856 lp->cache.csr14 = CSR14;
4857 lp->cache.csr15 = CSR15;
4858 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4859 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4860 csr6 = *p++;
4861 flags = *p++;
4862
4863 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4864 lp->defMedium = (flags & 0x40) ? -1 : 0;
4865 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4866 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4867 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4868 lp->useMII = FALSE;
4869
4870 de4x5_switch_mac_port(dev);
4871 }
4872
4873 return dc2114x_autoconf(dev);
4874}
4875
4876/*
4877** This block type provides information for resetting external devices
4878** (chips) through the General Purpose Register.
4879*/
f3b197ac 4880static int
1da177e4
LT		 4881type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4882{
4883 struct de4x5_private *lp = netdev_priv(dev);
4884 u_char len = (*p & BLOCK_LEN)+1;
4885
4886 /* Recursively figure out the info blocks */
4887 if (--count > lp->tcount) {
4888 if (*(p+len) < 128) {
4889 return dc_infoblock[COMPACT](dev, count, p+len);
4890 } else {
4891 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4892 }
4893 }
4894
4895 /* Must be initializing to run this code */
4896 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4897 p+=2;
4898 lp->rst = p;
4899 srom_exec(dev, lp->rst);
4900 }
4901
4902 return DE4X5_AUTOSENSE_MS;
4903}
4904
4905/*
4906** MII Read/Write
4907*/
4908
4909static int
4910mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4911{
4912 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4913 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4914 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4915 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4916 mii_address(phyreg, ioaddr); /* PHY Register to read */
4917 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
f3b197ac 4918
1da177e4
LT		 4919 return mii_rdata(ioaddr); /* Read data */
4920}
4921
4922static void
4923mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4924{
4925 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4926 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4927 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4928 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4929 mii_address(phyreg, ioaddr); /* PHY Register to write */
4930 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4931 data = mii_swap(data, 16); /* Swap data bit ordering */
4932 mii_wdata(data, 16, ioaddr); /* Write data */
f3b197ac 4933
1da177e4
LT		 4934 return;
4935}
4936
4937static int
4938mii_rdata(u_long ioaddr)
4939{
4940 int i;
4941 s32 tmp = 0;
f3b197ac 4942
1da177e4
LT		 4943 for (i=0; i<16; i++) {
4944 tmp <<= 1;
4945 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4946 }
f3b197ac 4947
1da177e4
LT		 4948 return tmp;
4949}
4950
4951static void
4952mii_wdata(int data, int len, u_long ioaddr)
4953{
4954 int i;
f3b197ac 4955
1da177e4
LT		 4956 for (i=0; i<len; i++) {
4957 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4958 data >>= 1;
4959 }
f3b197ac 4960
1da177e4
LT		 4961 return;
4962}
4963
4964static void
4965mii_address(u_char addr, u_long ioaddr)
4966{
4967 int i;
f3b197ac 4968
1da177e4
LT		 4969 addr = mii_swap(addr, 5);
4970 for (i=0; i<5; i++) {
4971 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4972 addr >>= 1;
4973 }
f3b197ac 4974
1da177e4
LT		 4975 return;
4976}
4977
4978static void
4979mii_ta(u_long rw, u_long ioaddr)
4980{
4981 if (rw == MII_STWR) {
f3b197ac
JG		 4982 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4983 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
1da177e4
LT		 4984 } else {
4985 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4986 }
f3b197ac 4987
1da177e4
LT		 4988 return;
4989}
4990
4991static int
4992mii_swap(int data, int len)
4993{
4994 int i, tmp = 0;
f3b197ac 4995
1da177e4
LT		 4996 for (i=0; i<len; i++) {
4997 tmp <<= 1;
4998 tmp |= (data & 1);
4999 data >>= 1;
5000 }
f3b197ac 5001
1da177e4
LT		 5002 return tmp;
5003}
5004
5005static void
5006sendto_mii(u32 command, int data, u_long ioaddr)
5007{
5008 u32 j;
f3b197ac 5009
1da177e4
LT		 5010 j = (data & 1) << 17;
5011 outl(command | j, ioaddr);
5012 udelay(1);
5013 outl(command | MII_MDC | j, ioaddr);
5014 udelay(1);
f3b197ac 5015
1da177e4
LT		 5016 return;
5017}
5018
5019static int
5020getfrom_mii(u32 command, u_long ioaddr)
5021{
5022 outl(command, ioaddr);
5023 udelay(1);
5024 outl(command | MII_MDC, ioaddr);
5025 udelay(1);
f3b197ac 5026
1da177e4
LT		 5027 return ((inl(ioaddr) >> 19) & 1);
5028}
5029
5030/*
5031** Here's 3 ways to calculate the OUI from the ID registers.
5032*/
5033static int
5034mii_get_oui(u_char phyaddr, u_long ioaddr)
5035{
5036/*
5037 union {
5038 u_short reg;
5039 u_char breg[2];
5040 } a;
5041 int i, r2, r3, ret=0;*/
5042 int r2, r3;
5043
5044 /* Read r2 and r3 */
5045 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5046 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5047 /* SEEQ and Cypress way * /
5048 / * Shuffle r2 and r3 * /
5049 a.reg=0;
5050 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5051 r2 = ((r2>>2)&0x3fff);
5052
5053 / * Bit reverse r3 * /
5054 for (i=0;i<8;i++) {
5055 ret<<=1;
5056 ret |= (r3&1);
5057 r3>>=1;
5058 }
5059
5060 / * Bit reverse r2 * /
5061 for (i=0;i<16;i++) {
5062 a.reg<<=1;
5063 a.reg |= (r2&1);
5064 r2>>=1;
5065 }
5066
5067 / * Swap r2 bytes * /
5068 i=a.breg[0];
5069 a.breg[0]=a.breg[1];
5070 a.breg[1]=i;
5071
5072 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5073/* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5074 return r2; /* (I did it) My way */
5075}
5076
5077/*
5078** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5079*/
5080static int
5081mii_get_phy(struct net_device *dev)
5082{
5083 struct de4x5_private *lp = netdev_priv(dev);
5084 u_long iobase = dev->base_addr;
5085 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5086 int id;
f3b197ac 5087
1da177e4
LT		 5088 lp->active = 0;
5089 lp->useMII = TRUE;
5090
5091 /* Search the MII address space for possible PHY devices */
5092 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5093 lp->phy[lp->active].addr = i;
5094 if (i==0) n++; /* Count cycles */
5095 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
f3b197ac 5096 id = mii_get_oui(i, DE4X5_MII);
1da177e4
LT		 5097 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5098 for (j=0; j<limit; j++) { /* Search PHY table */
5099 if (id != phy_info[j].id) continue; /* ID match? */
5100 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5101 if (k < DE4X5_MAX_PHY) {
5102 memcpy((char *)&lp->phy[k],
5103 (char *)&phy_info[j], sizeof(struct phy_table));
5104 lp->phy[k].addr = i;
5105 lp->mii_cnt++;
5106 lp->active++;
5107 } else {
5108 goto purgatory; /* Stop the search */
5109 }
5110 break;
5111 }
5112 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5113 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5114 lp->phy[k].addr = i;
5115 lp->phy[k].id = id;
5116 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5117 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5118 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5119 lp->mii_cnt++;
5120 lp->active++;
5121 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5122 j = de4x5_debug;
5123 de4x5_debug |= DEBUG_MII;
5124 de4x5_dbg_mii(dev, k);
5125 de4x5_debug = j;
5126 printk("\n");
5127 }
5128 }
5129 purgatory:
5130 lp->active = 0;
5131 if (lp->phy[0].id) { /* Reset the PHY devices */
5132 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5133 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5134 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
f3b197ac 5135
1da177e4
LT		 5136 de4x5_dbg_mii(dev, k);
5137 }
5138 }
5139 if (!lp->mii_cnt) lp->useMII = FALSE;
5140
5141 return lp->mii_cnt;
5142}
5143
5144static char *
5145build_setup_frame(struct net_device *dev, int mode)
5146{
5147 struct de4x5_private *lp = netdev_priv(dev);
5148 int i;
5149 char *pa = lp->setup_frame;
f3b197ac 5150
1da177e4
LT		 5151 /* Initialise the setup frame */
5152 if (mode == ALL) {
5153 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5154 }
f3b197ac 5155
1da177e4
LT		 5156 if (lp->setup_f == HASH_PERF) {
5157 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5158 *(pa + i) = dev->dev_addr[i]; /* Host address */
5159 if (i & 0x01) pa += 2;
5160 }
5161 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5162 } else {
5163 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5164 *(pa + (i&1)) = dev->dev_addr[i];
5165 if (i & 0x01) pa += 4;
5166 }
5167 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5168 *(pa + (i&1)) = (char) 0xff;
5169 if (i & 0x01) pa += 4;
5170 }
5171 }
f3b197ac 5172
1da177e4
LT		 5173 return pa; /* Points to the next entry */
5174}
5175
5176static void
5177enable_ast(struct net_device *dev, u32 time_out)
5178{
5179 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
f3b197ac 5180
1da177e4
LT		 5181 return;
5182}
5183
5184static void
5185disable_ast(struct net_device *dev)
5186{
5187 struct de4x5_private *lp = netdev_priv(dev);
f3b197ac 5188
1da177e4 5189 del_timer(&lp->timer);
f3b197ac 5190
1da177e4
LT		 5191 return;
5192}
5193
5194static long
5195de4x5_switch_mac_port(struct net_device *dev)
5196{
5197 struct de4x5_private *lp = netdev_priv(dev);
5198 u_long iobase = dev->base_addr;
5199 s32 omr;
5200
5201 STOP_DE4X5;
5202
5203 /* Assert the OMR_PS bit in CSR6 */
5204 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5205 OMR_FDX));
5206 omr |= lp->infoblock_csr6;
5207 if (omr & OMR_PS) omr |= OMR_HBD;
5208 outl(omr, DE4X5_OMR);
f3b197ac 5209
1da177e4
LT		 5210 /* Soft Reset */
5211 RESET_DE4X5;
f3b197ac 5212
1da177e4
LT		 5213 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5214 if (lp->chipset == DC21140) {
5215 gep_wr(lp->cache.gepc, dev);
5216 gep_wr(lp->cache.gep, dev);
5217 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5218 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5219 }
5220
5221 /* Restore CSR6 */
5222 outl(omr, DE4X5_OMR);
5223
5224 /* Reset CSR8 */
5225 inl(DE4X5_MFC);
5226
5227 return omr;
5228}
5229
5230static void
5231gep_wr(s32 data, struct net_device *dev)
5232{
5233 struct de4x5_private *lp = netdev_priv(dev);
5234 u_long iobase = dev->base_addr;
5235
5236 if (lp->chipset == DC21140) {
5237 outl(data, DE4X5_GEP);
5238 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5239 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5240 }
5241
5242 return;
5243}
5244
5245static int
5246gep_rd(struct net_device *dev)
5247{
5248 struct de4x5_private *lp = netdev_priv(dev);
5249 u_long iobase = dev->base_addr;
5250
5251 if (lp->chipset == DC21140) {
5252 return inl(DE4X5_GEP);
5253 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5254 return (inl(DE4X5_SIGR) & 0x000fffff);
5255 }
5256
5257 return 0;
5258}
5259
5260static void
5261timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5262{
5263 struct de4x5_private *lp = netdev_priv(dev);
5264 int dt;
f3b197ac 5265
1da177e4
LT		 5266 /* First, cancel any pending timer events */
5267 del_timer(&lp->timer);
f3b197ac 5268
1da177e4
LT		 5269 /* Convert msec to ticks */
5270 dt = (msec * HZ) / 1000;
5271 if (dt==0) dt=1;
f3b197ac 5272
1da177e4
LT		 5273 /* Set up timer */
5274 init_timer(&lp->timer);
5275 lp->timer.expires = jiffies + dt;
5276 lp->timer.function = fn;
5277 lp->timer.data = data;
5278 add_timer(&lp->timer);
f3b197ac 5279
1da177e4
LT		 5280 return;
5281}
5282
5283static void
5284yawn(struct net_device *dev, int state)
5285{
5286 struct de4x5_private *lp = netdev_priv(dev);
5287 u_long iobase = dev->base_addr;
5288
5289 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5290
5291 if(lp->bus == EISA) {
5292 switch(state) {
5293 case WAKEUP:
5294 outb(WAKEUP, PCI_CFPM);
5295 mdelay(10);
5296 break;
5297
5298 case SNOOZE:
5299 outb(SNOOZE, PCI_CFPM);
5300 break;
5301
5302 case SLEEP:
5303 outl(0, DE4X5_SICR);
5304 outb(SLEEP, PCI_CFPM);
5305 break;
5306 }
5307 } else {
5308 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5309 switch(state) {
5310 case WAKEUP:
5311 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5312 mdelay(10);
5313 break;
5314
5315 case SNOOZE:
5316 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5317 break;
5318
5319 case SLEEP:
5320 outl(0, DE4X5_SICR);
5321 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5322 break;
5323 }
5324 }
5325
5326 return;
5327}
5328
5329static void
5330de4x5_parse_params(struct net_device *dev)
5331{
5332 struct de4x5_private *lp = netdev_priv(dev);
5333 char *p, *q, t;
5334
5335 lp->params.fdx = 0;
5336 lp->params.autosense = AUTO;
5337
5338 if (args == NULL) return;
5339
5340 if ((p = strstr(args, dev->name))) {
5341 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5342 t = *q;
5343 *q = '\0';
5344
5345 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5346
5347 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5348 if (strstr(p, "TP")) {
5349 lp->params.autosense = TP;
5350 } else if (strstr(p, "TP_NW")) {
5351 lp->params.autosense = TP_NW;
5352 } else if (strstr(p, "BNC")) {
5353 lp->params.autosense = BNC;
5354 } else if (strstr(p, "AUI")) {
5355 lp->params.autosense = AUI;
5356 } else if (strstr(p, "BNC_AUI")) {
5357 lp->params.autosense = BNC;
5358 } else if (strstr(p, "10Mb")) {
5359 lp->params.autosense = _10Mb;
5360 } else if (strstr(p, "100Mb")) {
5361 lp->params.autosense = _100Mb;
5362 } else if (strstr(p, "AUTO")) {
5363 lp->params.autosense = AUTO;
5364 }
5365 }
5366 *q = t;
5367 }
5368
5369 return;
5370}
5371
5372static void
5373de4x5_dbg_open(struct net_device *dev)
5374{
5375 struct de4x5_private *lp = netdev_priv(dev);
5376 int i;
f3b197ac 5377
1da177e4
LT		 5378 if (de4x5_debug & DEBUG_OPEN) {
5379 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5380 printk("\tphysical address: ");
5381 for (i=0;i<6;i++) {
5382 printk("%2.2x:",(short)dev->dev_addr[i]);
5383 }
5384 printk("\n");
5385 printk("Descriptor head addresses:\n");
5386 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5387 printk("Descriptor addresses:\nRX: ");
5388 for (i=0;i<lp->rxRingSize-1;i++){
5389 if (i < 3) {
5390 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5391 }
5392 }
5393 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5394 printk("TX: ");
5395 for (i=0;i<lp->txRingSize-1;i++){
5396 if (i < 3) {
5397 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5398 }
5399 }
5400 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5401 printk("Descriptor buffers:\nRX: ");
5402 for (i=0;i<lp->rxRingSize-1;i++){
5403 if (i < 3) {
5404 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5405 }
5406 }
5407 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5408 printk("TX: ");
5409 for (i=0;i<lp->txRingSize-1;i++){
5410 if (i < 3) {
5411 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5412 }
5413 }
5414 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
f3b197ac
JG		 5415 printk("Ring size: \nRX: %d\nTX: %d\n",
5416 (short)lp->rxRingSize,
5417 (short)lp->txRingSize);
1da177e4 5418 }
f3b197ac 5419
1da177e4
LT		 5420 return;
5421}
5422
5423static void
5424de4x5_dbg_mii(struct net_device *dev, int k)
5425{
5426 struct de4x5_private *lp = netdev_priv(dev);
5427 u_long iobase = dev->base_addr;
f3b197ac 5428
1da177e4
LT		 5429 if (de4x5_debug & DEBUG_MII) {
5430 printk("\nMII device address: %d\n", lp->phy[k].addr);
5431 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5432 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5433 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5435 if (lp->phy[k].id != BROADCOM_T4) {
5436 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5437 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5438 }
5439 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5440 if (lp->phy[k].id != BROADCOM_T4) {
5441 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5442 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5443 } else {
5444 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5445 }
5446 }
f3b197ac 5447
1da177e4
LT		 5448 return;
5449}
5450
5451static void
5452de4x5_dbg_media(struct net_device *dev)
5453{
5454 struct de4x5_private *lp = netdev_priv(dev);
f3b197ac 5455
1da177e4
LT		 5456 if (lp->media != lp->c_media) {
5457 if (de4x5_debug & DEBUG_MEDIA) {
5458 printk("%s: media is %s%s\n", dev->name,
5459 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5460 (lp->media == TP ? "TP" :
5461 (lp->media == ANS ? "TP/Nway" :
f3b197ac
JG		 5462 (lp->media == BNC ? "BNC" :
5463 (lp->media == AUI ? "AUI" :
5464 (lp->media == BNC_AUI ? "BNC/AUI" :
5465 (lp->media == EXT_SIA ? "EXT SIA" :
1da177e4
LT		 5466 (lp->media == _100Mb ? "100Mb/s" :
5467 (lp->media == _10Mb ? "10Mb/s" :
5468 "???"
5469 ))))))))), (lp->fdx?" full duplex.":"."));
5470 }
5471 lp->c_media = lp->media;
5472 }
f3b197ac 5473
1da177e4
LT		 5474 return;
5475}
5476
5477static void
5478de4x5_dbg_srom(struct de4x5_srom *p)
5479{
5480 int i;
5481
5482 if (de4x5_debug & DEBUG_SROM) {
5483 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5484 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5485 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5486 printk("SROM version: %02x\n", (u_char)(p->version));
5487 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5488
5489 printk("Hardware Address: ");
5490 for (i=0;i<ETH_ALEN-1;i++) {
5491 printk("%02x:", (u_char)*(p->ieee_addr+i));
5492 }
5493 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5494 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5495 for (i=0; i<64; i++) {
5496 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5497 }
5498 }
5499
5500 return;
5501}
5502
5503static void
5504de4x5_dbg_rx(struct sk_buff *skb, int len)
5505{
5506 int i, j;
5507
5508 if (de4x5_debug & DEBUG_RX) {
5509 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5510 (u_char)skb->data[0],
5511 (u_char)skb->data[1],
5512 (u_char)skb->data[2],
5513 (u_char)skb->data[3],
5514 (u_char)skb->data[4],
5515 (u_char)skb->data[5],
5516 (u_char)skb->data[6],
5517 (u_char)skb->data[7],
5518 (u_char)skb->data[8],
5519 (u_char)skb->data[9],
5520 (u_char)skb->data[10],
5521 (u_char)skb->data[11],
5522 (u_char)skb->data[12],
5523 (u_char)skb->data[13],
5524 len);
5525 for (j=0; len>0;j+=16, len-=16) {
5526 printk(" %03x: ",j);
5527 for (i=0; i<16 && i<len; i++) {
5528 printk("%02x ",(u_char)skb->data[i+j]);
5529 }
5530 printk("\n");
5531 }
5532 }
5533
5534 return;
5535}
5536
5537/*
5538** Perform IOCTL call functions here. Some are privileged operations and the
5539** effective uid is checked in those cases. In the normal course of events
5540** this function is only used for my testing.
5541*/
5542static int
5543de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5544{
5545 struct de4x5_private *lp = netdev_priv(dev);
5546 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5547 u_long iobase = dev->base_addr;
5548 int i, j, status = 0;
5549 s32 omr;
5550 union {
5551 u8 addr[144];
5552 u16 sval[72];
5553 u32 lval[36];
5554 } tmp;
5555 u_long flags = 0;
f3b197ac 5556
1da177e4
LT		 5557 switch(ioc->cmd) {
5558 case DE4X5_GET_HWADDR: /* Get the hardware address */
5559 ioc->len = ETH_ALEN;
5560 for (i=0; i<ETH_ALEN; i++) {
5561 tmp.addr[i] = dev->dev_addr[i];
5562 }
5563 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5564 break;
5565
5566 case DE4X5_SET_HWADDR: /* Set the hardware address */
5567 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5568 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5569 if (netif_queue_stopped(dev))
5570 return -EBUSY;
5571 netif_stop_queue(dev);
5572 for (i=0; i<ETH_ALEN; i++) {
5573 dev->dev_addr[i] = tmp.addr[i];
5574 }
5575 build_setup_frame(dev, PHYS_ADDR_ONLY);
5576 /* Set up the descriptor and give ownership to the card */
f3b197ac 5577 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1da177e4
LT		 5578 SETUP_FRAME_LEN, (struct sk_buff *)1);
5579 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5580 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5581 netif_wake_queue(dev); /* Unlock the TX ring */
5582 break;
5583
5584 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5585 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5586 omr = inl(DE4X5_OMR);
5587 omr |= OMR_PR;
5588 outl(omr, DE4X5_OMR);
5589 dev->flags |= IFF_PROMISC;
5590 break;
5591
5592 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5593 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5594 omr = inl(DE4X5_OMR);
5595 omr &= ~OMR_PR;
5596 outl(omr, DE4X5_OMR);
5597 dev->flags &= ~IFF_PROMISC;
5598 break;
5599
5600 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5601 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5602 printk("%s: Boo!\n", dev->name);
5603 break;
5604
5605 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5606 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5607 omr = inl(DE4X5_OMR);
5608 omr |= OMR_PM;
5609 outl(omr, DE4X5_OMR);
5610 break;
5611
5612 case DE4X5_GET_STATS: /* Get the driver statistics */
5613 {
5614 struct pkt_stats statbuf;
5615 ioc->len = sizeof(statbuf);
5616 spin_lock_irqsave(&lp->lock, flags);
5617 memcpy(&statbuf, &lp->pktStats, ioc->len);
5618 spin_unlock_irqrestore(&lp->lock, flags);
f3b197ac
JG		 5619 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5620 return -EFAULT;
1da177e4
LT		 5621 break;
5622 }
5623 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5624 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5625 spin_lock_irqsave(&lp->lock, flags);
5626 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5627 spin_unlock_irqrestore(&lp->lock, flags);
5628 break;
5629
5630 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5631 tmp.addr[0] = inl(DE4X5_OMR);
5632 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5633 break;
5634
5635 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5636 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5637 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5638 outl(tmp.addr[0], DE4X5_OMR);
5639 break;
5640
5641 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5642 j = 0;
5643 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5644 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5645 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5646 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5647 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5648 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5649 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5650 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5651 ioc->len = j;
5652 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5653 break;
f3b197ac 5654
1da177e4 5655#define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
f3b197ac 5656/*
1da177e4
LT		 5657 case DE4X5_DUMP:
5658 j = 0;
5659 tmp.addr[j++] = dev->irq;
5660 for (i=0; i<ETH_ALEN; i++) {
5661 tmp.addr[j++] = dev->dev_addr[i];
5662 }
5663 tmp.addr[j++] = lp->rxRingSize;
5664 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5665 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
f3b197ac 5666
1da177e4
LT		 5667 for (i=0;i<lp->rxRingSize-1;i++){
5668 if (i < 3) {
5669 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5670 }
5671 }
5672 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5673 for (i=0;i<lp->txRingSize-1;i++){
5674 if (i < 3) {
5675 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5676 }
5677 }
5678 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
f3b197ac 5679
1da177e4
LT		 5680 for (i=0;i<lp->rxRingSize-1;i++){
5681 if (i < 3) {
5682 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5683 }
5684 }
5685 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5686 for (i=0;i<lp->txRingSize-1;i++){
5687 if (i < 3) {
5688 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5689 }
5690 }
5691 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
f3b197ac 5692
1da177e4
LT		 5693 for (i=0;i<lp->rxRingSize;i++){
5694 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5695 }
5696 for (i=0;i<lp->txRingSize;i++){
5697 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5698 }
f3b197ac 5699
1da177e4
LT		 5700 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5701 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5703 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5704 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5705 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5706 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
f3b197ac 5708 tmp.lval[j>>2] = lp->chipset; j+=4;
1da177e4
LT		 5709 if (lp->chipset == DC21140) {
5710 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5711 } else {
5712 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5713 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5714 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
f3b197ac 5715 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
1da177e4 5716 }
f3b197ac 5717 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
1da177e4 5718 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
f3b197ac 5719 tmp.lval[j>>2] = lp->active; j+=4;
1da177e4
LT		 5720 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5722 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 if (lp->phy[lp->active].id != BROADCOM_T4) {
5725 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5726 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5727 }
5728 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5729 if (lp->phy[lp->active].id != BROADCOM_T4) {
5730 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5731 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5732 } else {
5733 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5734 }
5735 }
f3b197ac 5736
1da177e4
LT		 5737 tmp.addr[j++] = lp->txRingSize;
5738 tmp.addr[j++] = netif_queue_stopped(dev);
f3b197ac 5739
1da177e4
LT		 5740 ioc->len = j;
5741 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5742 break;
5743
5744*/
5745 default:
5746 return -EOPNOTSUPP;
5747 }
f3b197ac 5748
1da177e4
LT		 5749 return status;
5750}
5751
5752static int __init de4x5_module_init (void)
5753{
5754 int err = 0;
5755
5756#ifdef CONFIG_PCI
29917620 5757 err = pci_register_driver(&de4x5_pci_driver);
1da177e4
LT		 5758#endif
5759#ifdef CONFIG_EISA
5760 err |= eisa_driver_register (&de4x5_eisa_driver);
5761#endif
5762
5763 return err;
5764}
5765
5766static void __exit de4x5_module_exit (void)
5767{
5768#ifdef CONFIG_PCI
5769 pci_unregister_driver (&de4x5_pci_driver);
5770#endif
5771#ifdef CONFIG_EISA
5772 eisa_driver_unregister (&de4x5_eisa_driver);
5773#endif
5774}
5775
5776module_init (de4x5_module_init);
5777module_exit (de4x5_module_exit);
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