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NET: sungem, use spin_trylock_irqsave
[net-next-2.6.git] / drivers / net / sungem.c
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1da177e4
LT		 1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
6aa20a22 5 *
1da177e4
LT		 6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
6aa20a22
JG		 12 *
13 * TODO:
1da177e4
LT		 14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
6aa20a22 19 *
1da177e4
LT		 20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
bea3348e 22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
1da177e4
LT		 23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/in.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/errno.h>
46#include <linux/pci.h>
1e7f0bd8 47#include <linux/dma-mapping.h>
1da177e4
LT		 48#include <linux/netdevice.h>
49#include <linux/etherdevice.h>
50#include <linux/skbuff.h>
51#include <linux/mii.h>
52#include <linux/ethtool.h>
53#include <linux/crc32.h>
54#include <linux/random.h>
55#include <linux/workqueue.h>
56#include <linux/if_vlan.h>
57#include <linux/bitops.h>
e3968fc0 58#include <linux/mutex.h>
d7fe0f24 59#include <linux/mm.h>
1da177e4
LT		 60
61#include <asm/system.h>
62#include <asm/io.h>
63#include <asm/byteorder.h>
64#include <asm/uaccess.h>
65#include <asm/irq.h>
66
dadb830d 67#ifdef CONFIG_SPARC
1da177e4 68#include <asm/idprom.h>
457e1a8a 69#include <asm/prom.h>
1da177e4
LT		 70#endif
71
72#ifdef CONFIG_PPC_PMAC
73#include <asm/pci-bridge.h>
74#include <asm/prom.h>
75#include <asm/machdep.h>
76#include <asm/pmac_feature.h>
77#endif
78
79#include "sungem_phy.h"
80#include "sungem.h"
81
82/* Stripping FCS is causing problems, disabled for now */
83#undef STRIP_FCS
84
85#define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
63ea998a
BH		 91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
92 SUPPORTED_Pause | SUPPORTED_Autoneg)
1da177e4
LT		 93
94#define DRV_NAME "sungem"
95#define DRV_VERSION "0.98"
96#define DRV_RELDATE "8/24/03"
97#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102MODULE_AUTHOR(DRV_AUTHOR);
103MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104MODULE_LICENSE("GPL");
105
106#define GEM_MODULE_NAME "gem"
107#define PFX GEM_MODULE_NAME ": "
108
109static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
6aa20a22 116 *
1da177e4
LT		 117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
7fce260a
OJ		 132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
1da177e4
LT		 134 {0, }
135};
136
137MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140{
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
46578a69 151 while (--limit) {
1da177e4
LT		 152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163}
164
165static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166{
8f15ea42 167 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 168 return __phy_read(gp, mii_id, reg);
169}
170
171static inline u16 phy_read(struct gem *gp, int reg)
172{
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174}
175
176static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177{
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196}
197
198static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199{
8f15ea42 200 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 201 __phy_write(gp, mii_id, reg, val & 0xffff);
202}
203
204static inline void phy_write(struct gem *gp, int reg, u16 val)
205{
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207}
208
209static inline void gem_enable_ints(struct gem *gp)
210{
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213}
214
215static inline void gem_disable_ints(struct gem *gp)
216{
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219}
220
221static void gem_get_cell(struct gem *gp)
222{
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225#ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231#endif /* CONFIG_PPC_PMAC */
232}
233
234/* Turn off the chip's clock */
235static void gem_put_cell(struct gem *gp)
236{
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239#ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245#endif /* CONFIG_PPC_PMAC */
246}
247
248static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249{
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252}
253
254static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255{
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307}
308
309static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310{
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356}
357
358/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364static int gem_rxmac_reset(struct gem *gp)
365{
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467}
468
469static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470{
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502}
503
504static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505{
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523}
524
525static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526{
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536}
537
538static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539{
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601}
602
603/* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609{
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665}
666
667static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668{
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725}
726
727static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728{
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755}
756
757static int gem_rx(struct gem *gp, int work_to_do)
758{
759 int entry, drops, work_done = 0;
760 u32 done;
439104b3 761 __sum16 csum;
1da177e4
LT		 762
763 if (netif_msg_rx_status(gp))
764 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
765 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
766
767 entry = gp->rx_new;
768 drops = 0;
769 done = readl(gp->regs + RXDMA_DONE);
770 for (;;) {
771 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
772 struct sk_buff *skb;
439104b3 773 u64 status = le64_to_cpu(rxd->status_word);
1da177e4
LT		 774 dma_addr_t dma_addr;
775 int len;
776
777 if ((status & RXDCTRL_OWN) != 0)
778 break;
779
780 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
781 break;
782
783 /* When writing back RX descriptor, GEM writes status
784 * then buffer address, possibly in seperate transactions.
785 * If we don't wait for the chip to write both, we could
786 * post a new buffer to this descriptor then have GEM spam
787 * on the buffer address. We sync on the RX completion
788 * register to prevent this from happening.
789 */
790 if (entry == done) {
791 done = readl(gp->regs + RXDMA_DONE);
792 if (entry == done)
793 break;
794 }
795
796 /* We can now account for the work we're about to do */
797 work_done++;
798
799 skb = gp->rx_skbs[entry];
800
801 len = (status & RXDCTRL_BUFSZ) >> 16;
802 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
803 gp->net_stats.rx_errors++;
804 if (len < ETH_ZLEN)
805 gp->net_stats.rx_length_errors++;
806 if (len & RXDCTRL_BAD)
807 gp->net_stats.rx_crc_errors++;
808
809 /* We'll just return it to GEM. */
810 drop_it:
811 gp->net_stats.rx_dropped++;
812 goto next;
813 }
814
439104b3 815 dma_addr = le64_to_cpu(rxd->buffer);
1da177e4
LT		 816 if (len > RX_COPY_THRESHOLD) {
817 struct sk_buff *new_skb;
818
819 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
820 if (new_skb == NULL) {
821 drops++;
822 goto drop_it;
823 }
824 pci_unmap_page(gp->pdev, dma_addr,
825 RX_BUF_ALLOC_SIZE(gp),
826 PCI_DMA_FROMDEVICE);
827 gp->rx_skbs[entry] = new_skb;
828 new_skb->dev = gp->dev;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
1da177e4
LT		 847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
d626f62b 850 skb_copy_from_linear_data(skb, copy_skb->data, len);
1da177e4
LT		 851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
439104b3
AV		 857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
84fa7933 859 skb->ip_summed = CHECKSUM_COMPLETE;
1da177e4
LT		 860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 netif_receive_skb(skb);
863
864 gp->net_stats.rx_packets++;
865 gp->net_stats.rx_bytes += len;
1da177e4
LT		 866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
877 gp->dev->name);
878
879 return work_done;
880}
881
bea3348e 882static int gem_poll(struct napi_struct *napi, int budget)
1da177e4 883{
bea3348e
SH		 884 struct gem *gp = container_of(napi, struct gem, napi);
885 struct net_device *dev = gp->dev;
1da177e4 886 unsigned long flags;
bea3348e 887 int work_done;
1da177e4
LT		 888
889 /*
6aa20a22 890 * NAPI locking nightmare: See comment at head of driver
1da177e4
LT		 891 */
892 spin_lock_irqsave(&gp->lock, flags);
893
bea3348e 894 work_done = 0;
1da177e4 895 do {
1da177e4
LT		 896 /* Handle anomalies */
897 if (gp->status & GREG_STAT_ABNORMAL) {
898 if (gem_abnormal_irq(dev, gp, gp->status))
899 break;
900 }
901
902 /* Run TX completion thread */
903 spin_lock(&gp->tx_lock);
904 gem_tx(dev, gp, gp->status);
905 spin_unlock(&gp->tx_lock);
906
907 spin_unlock_irqrestore(&gp->lock, flags);
908
6aa20a22
JG		 909 /* Run RX thread. We don't use any locking here,
910 * code willing to do bad things - like cleaning the
bea3348e 911 * rx ring - must call napi_disable(), which
1da177e4
LT		 912 * schedule_timeout()'s if polling is already disabled.
913 */
da990a24 914 work_done += gem_rx(gp, budget - work_done);
1da177e4 915
bea3348e
SH		 916 if (work_done >= budget)
917 return work_done;
1da177e4
LT		 918
919 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 920
1da177e4
LT		 921 gp->status = readl(gp->regs + GREG_STAT);
922 } while (gp->status & GREG_STAT_NAPI);
923
288379f0 924 __napi_complete(napi);
1da177e4
LT		 925 gem_enable_ints(gp);
926
927 spin_unlock_irqrestore(&gp->lock, flags);
bea3348e
SH		 928
929 return work_done;
1da177e4
LT		 930}
931
7d12e780 932static irqreturn_t gem_interrupt(int irq, void *dev_id)
1da177e4
LT		 933{
934 struct net_device *dev = dev_id;
8f15ea42 935 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 936 unsigned long flags;
937
938 /* Swallow interrupts when shutting the chip down, though
939 * that shouldn't happen, we should have done free_irq() at
940 * this point...
941 */
942 if (!gp->running)
943 return IRQ_HANDLED;
944
945 spin_lock_irqsave(&gp->lock, flags);
6aa20a22 946
288379f0 947 if (napi_schedule_prep(&gp->napi)) {
1da177e4
LT		 948 u32 gem_status = readl(gp->regs + GREG_STAT);
949
950 if (gem_status == 0) {
bea3348e 951 napi_enable(&gp->napi);
1da177e4
LT		 952 spin_unlock_irqrestore(&gp->lock, flags);
953 return IRQ_NONE;
954 }
955 gp->status = gem_status;
956 gem_disable_ints(gp);
288379f0 957 __napi_schedule(&gp->napi);
1da177e4
LT		 958 }
959
960 spin_unlock_irqrestore(&gp->lock, flags);
6aa20a22 961
1da177e4 962 /* If polling was disabled at the time we received that
6aa20a22 963 * interrupt, we may return IRQ_HANDLED here while we
1da177e4
LT		 964 * should return IRQ_NONE. No big deal...
965 */
966 return IRQ_HANDLED;
967}
968
969#ifdef CONFIG_NET_POLL_CONTROLLER
970static void gem_poll_controller(struct net_device *dev)
971{
972 /* gem_interrupt is safe to reentrance so no need
973 * to disable_irq here.
974 */
7d12e780 975 gem_interrupt(dev->irq, dev);
1da177e4
LT		 976}
977#endif
978
979static void gem_tx_timeout(struct net_device *dev)
980{
8f15ea42 981 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 982
983 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
984 if (!gp->running) {
985 printk("%s: hrm.. hw not running !\n", dev->name);
986 return;
987 }
988 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
989 dev->name,
990 readl(gp->regs + TXDMA_CFG),
991 readl(gp->regs + MAC_TXSTAT),
992 readl(gp->regs + MAC_TXCFG));
993 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
994 dev->name,
995 readl(gp->regs + RXDMA_CFG),
996 readl(gp->regs + MAC_RXSTAT),
997 readl(gp->regs + MAC_RXCFG));
998
999 spin_lock_irq(&gp->lock);
1000 spin_lock(&gp->tx_lock);
1001
1002 gp->reset_task_pending = 1;
1003 schedule_work(&gp->reset_task);
1004
1005 spin_unlock(&gp->tx_lock);
1006 spin_unlock_irq(&gp->lock);
1007}
1008
1009static __inline__ int gem_intme(int entry)
1010{
1011 /* Algorithm: IRQ every 1/2 of descriptors. */
1012 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1013 return 1;
1014
1015 return 0;
1016}
1017
61357325
SH		 1018static netdev_tx_t gem_start_xmit(struct sk_buff *skb,
1019 struct net_device *dev)
1da177e4 1020{
8f15ea42 1021 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 1022 int entry;
1023 u64 ctrl;
1024 unsigned long flags;
1025
1026 ctrl = 0;
84fa7933 1027 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d
ACM		 1028 const u64 csum_start_off = skb_transport_offset(skb);
1029 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1da177e4
LT		 1030
1031 ctrl = (TXDCTRL_CENAB |
1032 (csum_start_off << 15) |
1033 (csum_stuff_off << 21));
1034 }
1035
b8883a65 1036 if (!spin_trylock_irqsave(&gp->tx_lock, flags)) {
1da177e4 1037 /* Tell upper layer to requeue */
1da177e4
LT		 1038 return NETDEV_TX_LOCKED;
1039 }
1040 /* We raced with gem_do_stop() */
1041 if (!gp->running) {
1042 spin_unlock_irqrestore(&gp->tx_lock, flags);
1043 return NETDEV_TX_BUSY;
1044 }
1045
1046 /* This is a hard error, log it. */
1047 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1048 netif_stop_queue(dev);
1049 spin_unlock_irqrestore(&gp->tx_lock, flags);
1050 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1051 dev->name);
1052 return NETDEV_TX_BUSY;
1053 }
1054
1055 entry = gp->tx_new;
1056 gp->tx_skbs[entry] = skb;
1057
1058 if (skb_shinfo(skb)->nr_frags == 0) {
1059 struct gem_txd *txd = &gp->init_block->txd[entry];
1060 dma_addr_t mapping;
1061 u32 len;
1062
1063 len = skb->len;
1064 mapping = pci_map_page(gp->pdev,
1065 virt_to_page(skb->data),
1066 offset_in_page(skb->data),
1067 len, PCI_DMA_TODEVICE);
1068 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1069 if (gem_intme(entry))
1070 ctrl |= TXDCTRL_INTME;
1071 txd->buffer = cpu_to_le64(mapping);
1072 wmb();
1073 txd->control_word = cpu_to_le64(ctrl);
1074 entry = NEXT_TX(entry);
1075 } else {
1076 struct gem_txd *txd;
1077 u32 first_len;
1078 u64 intme;
1079 dma_addr_t first_mapping;
1080 int frag, first_entry = entry;
1081
1082 intme = 0;
1083 if (gem_intme(entry))
1084 intme |= TXDCTRL_INTME;
1085
1086 /* We must give this initial chunk to the device last.
1087 * Otherwise we could race with the device.
1088 */
1089 first_len = skb_headlen(skb);
1090 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1091 offset_in_page(skb->data),
1092 first_len, PCI_DMA_TODEVICE);
1093 entry = NEXT_TX(entry);
1094
1095 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1096 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1097 u32 len;
1098 dma_addr_t mapping;
1099 u64 this_ctrl;
1100
1101 len = this_frag->size;
1102 mapping = pci_map_page(gp->pdev,
1103 this_frag->page,
1104 this_frag->page_offset,
1105 len, PCI_DMA_TODEVICE);
1106 this_ctrl = ctrl;
1107 if (frag == skb_shinfo(skb)->nr_frags - 1)
1108 this_ctrl |= TXDCTRL_EOF;
6aa20a22 1109
1da177e4
LT		 1110 txd = &gp->init_block->txd[entry];
1111 txd->buffer = cpu_to_le64(mapping);
1112 wmb();
1113 txd->control_word = cpu_to_le64(this_ctrl | len);
1114
1115 if (gem_intme(entry))
1116 intme |= TXDCTRL_INTME;
1117
1118 entry = NEXT_TX(entry);
1119 }
1120 txd = &gp->init_block->txd[first_entry];
1121 txd->buffer = cpu_to_le64(first_mapping);
1122 wmb();
1123 txd->control_word =
1124 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1125 }
1126
1127 gp->tx_new = entry;
1128 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1129 netif_stop_queue(dev);
1130
1131 if (netif_msg_tx_queued(gp))
1132 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1133 dev->name, entry, skb->len);
1134 mb();
1135 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1136 spin_unlock_irqrestore(&gp->tx_lock, flags);
1137
1138 dev->trans_start = jiffies;
1139
1140 return NETDEV_TX_OK;
1141}
1142
8c83f80b
DM		 1143static void gem_pcs_reset(struct gem *gp)
1144{
1145 int limit;
1146 u32 val;
1147
1148 /* Reset PCS unit. */
1149 val = readl(gp->regs + PCS_MIICTRL);
1150 val |= PCS_MIICTRL_RST;
1151 writel(val, gp->regs + PCS_MIICTRL);
1152
1153 limit = 32;
1154 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1155 udelay(100);
1156 if (limit-- <= 0)
1157 break;
1158 }
d13c11f6 1159 if (limit < 0)
8c83f80b
DM		 1160 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1161 gp->dev->name);
1162}
1163
1164static void gem_pcs_reinit_adv(struct gem *gp)
1165{
1166 u32 val;
1167
1168 /* Make sure PCS is disabled while changing advertisement
1169 * configuration.
1170 */
1171 val = readl(gp->regs + PCS_CFG);
1172 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1173 writel(val, gp->regs + PCS_CFG);
1174
1175 /* Advertise all capabilities except assymetric
1176 * pause.
1177 */
1178 val = readl(gp->regs + PCS_MIIADV);
1179 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1180 PCS_MIIADV_SP | PCS_MIIADV_AP);
1181 writel(val, gp->regs + PCS_MIIADV);
1182
1183 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1184 * and re-enable PCS.
1185 */
1186 val = readl(gp->regs + PCS_MIICTRL);
1187 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1188 val &= ~PCS_MIICTRL_WB;
1189 writel(val, gp->regs + PCS_MIICTRL);
1190
1191 val = readl(gp->regs + PCS_CFG);
1192 val |= PCS_CFG_ENABLE;
1193 writel(val, gp->regs + PCS_CFG);
1194
1195 /* Make sure serialink loopback is off. The meaning
1196 * of this bit is logically inverted based upon whether
1197 * you are in Serialink or SERDES mode.
1198 */
1199 val = readl(gp->regs + PCS_SCTRL);
1200 if (gp->phy_type == phy_serialink)
1201 val &= ~PCS_SCTRL_LOOP;
1202 else
1203 val |= PCS_SCTRL_LOOP;
1204 writel(val, gp->regs + PCS_SCTRL);
1205}
1206
1da177e4
LT		 1207#define STOP_TRIES 32
1208
1209/* Must be invoked under gp->lock and gp->tx_lock. */
1210static void gem_reset(struct gem *gp)
1211{
1212 int limit;
1213 u32 val;
1214
1215 /* Make sure we won't get any more interrupts */
1216 writel(0xffffffff, gp->regs + GREG_IMASK);
1217
1218 /* Reset the chip */
1219 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1220 gp->regs + GREG_SWRST);
1221
1222 limit = STOP_TRIES;
1223
1224 do {
1225 udelay(20);
1226 val = readl(gp->regs + GREG_SWRST);
1227 if (limit-- <= 0)
1228 break;
1229 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1230
4a8fd2cf 1231 if (limit < 0)
1da177e4 1232 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
8c83f80b
DM		 1233
1234 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1235 gem_pcs_reinit_adv(gp);
1da177e4
LT		 1236}
1237
1238/* Must be invoked under gp->lock and gp->tx_lock. */
1239static void gem_start_dma(struct gem *gp)
1240{
1241 u32 val;
6aa20a22 1242
1da177e4
LT		 1243 /* We are ready to rock, turn everything on. */
1244 val = readl(gp->regs + TXDMA_CFG);
1245 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1246 val = readl(gp->regs + RXDMA_CFG);
1247 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1248 val = readl(gp->regs + MAC_TXCFG);
1249 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1250 val = readl(gp->regs + MAC_RXCFG);
1251 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1252
1253 (void) readl(gp->regs + MAC_RXCFG);
1254 udelay(100);
1255
1256 gem_enable_ints(gp);
1257
1258 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1259}
1260
1261/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1262 * actually stopped before about 4ms tho ...
1263 */
1264static void gem_stop_dma(struct gem *gp)
1265{
1266 u32 val;
1267
1268 /* We are done rocking, turn everything off. */
1269 val = readl(gp->regs + TXDMA_CFG);
1270 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1271 val = readl(gp->regs + RXDMA_CFG);
1272 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1273 val = readl(gp->regs + MAC_TXCFG);
1274 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1275 val = readl(gp->regs + MAC_RXCFG);
1276 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1277
1278 (void) readl(gp->regs + MAC_RXCFG);
1279
1280 /* Need to wait a bit ... done by the caller */
1281}
1282
1283
1284/* Must be invoked under gp->lock and gp->tx_lock. */
1285// XXX dbl check what that function should do when called on PCS PHY
1286static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1287{
1288 u32 advertise, features;
1289 int autoneg;
1290 int speed;
1291 int duplex;
1292
1293 if (gp->phy_type != phy_mii_mdio0 &&
1294 gp->phy_type != phy_mii_mdio1)
1295 goto non_mii;
1296
1297 /* Setup advertise */
1298 if (found_mii_phy(gp))
1299 features = gp->phy_mii.def->features;
1300 else
1301 features = 0;
1302
1303 advertise = features & ADVERTISE_MASK;
1304 if (gp->phy_mii.advertising != 0)
1305 advertise &= gp->phy_mii.advertising;
1306
1307 autoneg = gp->want_autoneg;
1308 speed = gp->phy_mii.speed;
1309 duplex = gp->phy_mii.duplex;
6aa20a22 1310
1da177e4
LT		 1311 /* Setup link parameters */
1312 if (!ep)
1313 goto start_aneg;
1314 if (ep->autoneg == AUTONEG_ENABLE) {
1315 advertise = ep->advertising;
1316 autoneg = 1;
1317 } else {
1318 autoneg = 0;
1319 speed = ep->speed;
1320 duplex = ep->duplex;
1321 }
1322
1323start_aneg:
1324 /* Sanitize settings based on PHY capabilities */
1325 if ((features & SUPPORTED_Autoneg) == 0)
1326 autoneg = 0;
1327 if (speed == SPEED_1000 &&
1328 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1329 speed = SPEED_100;
1330 if (speed == SPEED_100 &&
1331 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1332 speed = SPEED_10;
1333 if (duplex == DUPLEX_FULL &&
1334 !(features & (SUPPORTED_1000baseT_Full |
1335 SUPPORTED_100baseT_Full |
1336 SUPPORTED_10baseT_Full)))
1337 duplex = DUPLEX_HALF;
1338 if (speed == 0)
1339 speed = SPEED_10;
6aa20a22 1340
1da177e4
LT		 1341 /* If we are asleep, we don't try to actually setup the PHY, we
1342 * just store the settings
1343 */
1344 if (gp->asleep) {
1345 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1346 gp->phy_mii.speed = speed;
1347 gp->phy_mii.duplex = duplex;
1348 return;
1349 }
1350
1351 /* Configure PHY & start aneg */
1352 gp->want_autoneg = autoneg;
1353 if (autoneg) {
1354 if (found_mii_phy(gp))
1355 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1356 gp->lstate = link_aneg;
1357 } else {
1358 if (found_mii_phy(gp))
1359 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1360 gp->lstate = link_force_ok;
1361 }
1362
1363non_mii:
1364 gp->timer_ticks = 0;
1365 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1366}
1367
1368/* A link-up condition has occurred, initialize and enable the
1369 * rest of the chip.
1370 *
1371 * Must be invoked under gp->lock and gp->tx_lock.
1372 */
1373static int gem_set_link_modes(struct gem *gp)
1374{
1375 u32 val;
1376 int full_duplex, speed, pause;
1377
1378 full_duplex = 0;
1379 speed = SPEED_10;
1380 pause = 0;
1381
1382 if (found_mii_phy(gp)) {
1383 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1384 return 1;
1385 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1386 speed = gp->phy_mii.speed;
1387 pause = gp->phy_mii.pause;
1388 } else if (gp->phy_type == phy_serialink ||
1389 gp->phy_type == phy_serdes) {
1390 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1391
8c83f80b 1392 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1da177e4
LT		 1393 full_duplex = 1;
1394 speed = SPEED_1000;
1395 }
1396
1397 if (netif_msg_link(gp))
1398 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1399 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1400
1401 if (!gp->running)
1402 return 0;
1403
1404 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1405 if (full_duplex) {
1406 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1407 } else {
1408 /* MAC_TXCFG_NBO must be zero. */
6aa20a22 1409 }
1da177e4
LT		 1410 writel(val, gp->regs + MAC_TXCFG);
1411
1412 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1413 if (!full_duplex &&
1414 (gp->phy_type == phy_mii_mdio0 ||
1415 gp->phy_type == phy_mii_mdio1)) {
1416 val |= MAC_XIFCFG_DISE;
1417 } else if (full_duplex) {
1418 val |= MAC_XIFCFG_FLED;
1419 }
1420
1421 if (speed == SPEED_1000)
1422 val |= (MAC_XIFCFG_GMII);
1423
1424 writel(val, gp->regs + MAC_XIFCFG);
1425
1426 /* If gigabit and half-duplex, enable carrier extension
1427 * mode. Else, disable it.
1428 */
1429 if (speed == SPEED_1000 && !full_duplex) {
1430 val = readl(gp->regs + MAC_TXCFG);
1431 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1432
1433 val = readl(gp->regs + MAC_RXCFG);
1434 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1435 } else {
1436 val = readl(gp->regs + MAC_TXCFG);
1437 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1438
1439 val = readl(gp->regs + MAC_RXCFG);
1440 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1441 }
1442
1443 if (gp->phy_type == phy_serialink ||
1444 gp->phy_type == phy_serdes) {
1445 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1446
1447 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1448 pause = 1;
1449 }
1450
1451 if (netif_msg_link(gp)) {
1452 if (pause) {
1453 printk(KERN_INFO "%s: Pause is enabled "
1454 "(rxfifo: %d off: %d on: %d)\n",
1455 gp->dev->name,
1456 gp->rx_fifo_sz,
1457 gp->rx_pause_off,
1458 gp->rx_pause_on);
1459 } else {
1460 printk(KERN_INFO "%s: Pause is disabled\n",
1461 gp->dev->name);
1462 }
1463 }
1464
1465 if (!full_duplex)
1466 writel(512, gp->regs + MAC_STIME);
1467 else
1468 writel(64, gp->regs + MAC_STIME);
1469 val = readl(gp->regs + MAC_MCCFG);
1470 if (pause)
1471 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1472 else
1473 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1474 writel(val, gp->regs + MAC_MCCFG);
1475
1476 gem_start_dma(gp);
1477
1478 return 0;
1479}
1480
1481/* Must be invoked under gp->lock and gp->tx_lock. */
1482static int gem_mdio_link_not_up(struct gem *gp)
1483{
1484 switch (gp->lstate) {
1485 case link_force_ret:
1486 if (netif_msg_link(gp))
1487 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1488 " forced mode\n", gp->dev->name);
1489 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1490 gp->last_forced_speed, DUPLEX_HALF);
1491 gp->timer_ticks = 5;
1492 gp->lstate = link_force_ok;
1493 return 0;
1494 case link_aneg:
1495 /* We try forced modes after a failed aneg only on PHYs that don't
1496 * have "magic_aneg" bit set, which means they internally do the
1497 * while forced-mode thingy. On these, we just restart aneg
1498 */
1499 if (gp->phy_mii.def->magic_aneg)
1500 return 1;
1501 if (netif_msg_link(gp))
1502 printk(KERN_INFO "%s: switching to forced 100bt\n",
1503 gp->dev->name);
1504 /* Try forced modes. */
1505 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1506 DUPLEX_HALF);
1507 gp->timer_ticks = 5;
1508 gp->lstate = link_force_try;
1509 return 0;
1510 case link_force_try:
1511 /* Downgrade from 100 to 10 Mbps if necessary.
1512 * If already at 10Mbps, warn user about the
1513 * situation every 10 ticks.
1514 */
1515 if (gp->phy_mii.speed == SPEED_100) {
1516 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1517 DUPLEX_HALF);
1518 gp->timer_ticks = 5;
1519 if (netif_msg_link(gp))
1520 printk(KERN_INFO "%s: switching to forced 10bt\n",
1521 gp->dev->name);
1522 return 0;
1523 } else
1524 return 1;
1525 default:
1526 return 0;
1527 }
1528}
1529
1530static void gem_link_timer(unsigned long data)
1531{
1532 struct gem *gp = (struct gem *) data;
1533 int restart_aneg = 0;
6aa20a22 1534
1da177e4
LT		 1535 if (gp->asleep)
1536 return;
1537
1538 spin_lock_irq(&gp->lock);
1539 spin_lock(&gp->tx_lock);
1540 gem_get_cell(gp);
1541
1542 /* If the reset task is still pending, we just
1543 * reschedule the link timer
1544 */
1545 if (gp->reset_task_pending)
1546 goto restart;
6aa20a22 1547
1da177e4
LT		 1548 if (gp->phy_type == phy_serialink ||
1549 gp->phy_type == phy_serdes) {
1550 u32 val = readl(gp->regs + PCS_MIISTAT);
1551
1552 if (!(val & PCS_MIISTAT_LS))
1553 val = readl(gp->regs + PCS_MIISTAT);
1554
1555 if ((val & PCS_MIISTAT_LS) != 0) {
8c83f80b
DM		 1556 if (gp->lstate == link_up)
1557 goto restart;
1558
1da177e4
LT		 1559 gp->lstate = link_up;
1560 netif_carrier_on(gp->dev);
1561 (void)gem_set_link_modes(gp);
1562 }
1563 goto restart;
1564 }
1565 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1566 /* Ok, here we got a link. If we had it due to a forced
1567 * fallback, and we were configured for autoneg, we do
1568 * retry a short autoneg pass. If you know your hub is
1569 * broken, use ethtool ;)
1570 */
1571 if (gp->lstate == link_force_try && gp->want_autoneg) {
1572 gp->lstate = link_force_ret;
1573 gp->last_forced_speed = gp->phy_mii.speed;
1574 gp->timer_ticks = 5;
1575 if (netif_msg_link(gp))
1576 printk(KERN_INFO "%s: Got link after fallback, retrying"
1577 " autoneg once...\n", gp->dev->name);
1578 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1579 } else if (gp->lstate != link_up) {
1580 gp->lstate = link_up;
1581 netif_carrier_on(gp->dev);
1582 if (gem_set_link_modes(gp))
1583 restart_aneg = 1;
1584 }
1585 } else {
1586 /* If the link was previously up, we restart the
1587 * whole process
1588 */
1589 if (gp->lstate == link_up) {
1590 gp->lstate = link_down;
1591 if (netif_msg_link(gp))
1592 printk(KERN_INFO "%s: Link down\n",
1593 gp->dev->name);
1594 netif_carrier_off(gp->dev);
1595 gp->reset_task_pending = 1;
1596 schedule_work(&gp->reset_task);
1597 restart_aneg = 1;
1598 } else if (++gp->timer_ticks > 10) {
1599 if (found_mii_phy(gp))
1600 restart_aneg = gem_mdio_link_not_up(gp);
1601 else
1602 restart_aneg = 1;
1603 }
1604 }
1605 if (restart_aneg) {
1606 gem_begin_auto_negotiation(gp, NULL);
1607 goto out_unlock;
1608 }
1609restart:
1610 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1611out_unlock:
1612 gem_put_cell(gp);
1613 spin_unlock(&gp->tx_lock);
1614 spin_unlock_irq(&gp->lock);
1615}
1616
1617/* Must be invoked under gp->lock and gp->tx_lock. */
1618static void gem_clean_rings(struct gem *gp)
1619{
1620 struct gem_init_block *gb = gp->init_block;
1621 struct sk_buff *skb;
1622 int i;
1623 dma_addr_t dma_addr;
1624
1625 for (i = 0; i < RX_RING_SIZE; i++) {
1626 struct gem_rxd *rxd;
1627
1628 rxd = &gb->rxd[i];
1629 if (gp->rx_skbs[i] != NULL) {
1630 skb = gp->rx_skbs[i];
1631 dma_addr = le64_to_cpu(rxd->buffer);
1632 pci_unmap_page(gp->pdev, dma_addr,
1633 RX_BUF_ALLOC_SIZE(gp),
1634 PCI_DMA_FROMDEVICE);
1635 dev_kfree_skb_any(skb);
1636 gp->rx_skbs[i] = NULL;
1637 }
1638 rxd->status_word = 0;
1639 wmb();
1640 rxd->buffer = 0;
1641 }
1642
1643 for (i = 0; i < TX_RING_SIZE; i++) {
1644 if (gp->tx_skbs[i] != NULL) {
1645 struct gem_txd *txd;
1646 int frag;
1647
1648 skb = gp->tx_skbs[i];
1649 gp->tx_skbs[i] = NULL;
1650
1651 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1652 int ent = i & (TX_RING_SIZE - 1);
1653
1654 txd = &gb->txd[ent];
1655 dma_addr = le64_to_cpu(txd->buffer);
1656 pci_unmap_page(gp->pdev, dma_addr,
1657 le64_to_cpu(txd->control_word) &
1658 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1659
1660 if (frag != skb_shinfo(skb)->nr_frags)
1661 i++;
1662 }
1663 dev_kfree_skb_any(skb);
1664 }
1665 }
1666}
1667
1668/* Must be invoked under gp->lock and gp->tx_lock. */
1669static void gem_init_rings(struct gem *gp)
1670{
1671 struct gem_init_block *gb = gp->init_block;
1672 struct net_device *dev = gp->dev;
1673 int i;
1674 dma_addr_t dma_addr;
1675
1676 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1677
1678 gem_clean_rings(gp);
1679
1680 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1681 (unsigned)VLAN_ETH_FRAME_LEN);
1682
1683 for (i = 0; i < RX_RING_SIZE; i++) {
1684 struct sk_buff *skb;
1685 struct gem_rxd *rxd = &gb->rxd[i];
1686
1687 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1688 if (!skb) {
1689 rxd->buffer = 0;
1690 rxd->status_word = 0;
1691 continue;
1692 }
1693
1694 gp->rx_skbs[i] = skb;
1695 skb->dev = dev;
1696 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1697 dma_addr = pci_map_page(gp->pdev,
1698 virt_to_page(skb->data),
1699 offset_in_page(skb->data),
1700 RX_BUF_ALLOC_SIZE(gp),
1701 PCI_DMA_FROMDEVICE);
1702 rxd->buffer = cpu_to_le64(dma_addr);
1703 wmb();
1704 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1705 skb_reserve(skb, RX_OFFSET);
1706 }
1707
1708 for (i = 0; i < TX_RING_SIZE; i++) {
1709 struct gem_txd *txd = &gb->txd[i];
1710
1711 txd->control_word = 0;
1712 wmb();
1713 txd->buffer = 0;
1714 }
1715 wmb();
1716}
1717
1718/* Init PHY interface and start link poll state machine */
1719static void gem_init_phy(struct gem *gp)
1720{
7fb76aa0 1721 u32 mifcfg;
1da177e4
LT		 1722
1723 /* Revert MIF CFG setting done on stop_phy */
7fb76aa0
DM		 1724 mifcfg = readl(gp->regs + MIF_CFG);
1725 mifcfg &= ~MIF_CFG_BBMODE;
1726 writel(mifcfg, gp->regs + MIF_CFG);
6aa20a22 1727
1da177e4
LT		 1728 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1729 int i;
1730
7fb76aa0
DM		 1731 /* Those delay sucks, the HW seem to love them though, I'll
1732 * serisouly consider breaking some locks here to be able
1733 * to schedule instead
1734 */
1735 for (i = 0; i < 3; i++) {
1da177e4 1736#ifdef CONFIG_PPC_PMAC
7fb76aa0
DM		 1737 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1738 msleep(20);
1da177e4 1739#endif
7fb76aa0
DM		 1740 /* Some PHYs used by apple have problem getting back to us,
1741 * we do an additional reset here
1742 */
1743 phy_write(gp, MII_BMCR, BMCR_RESET);
1744 msleep(20);
1745 if (phy_read(gp, MII_BMCR) != 0xffff)
1da177e4 1746 break;
7fb76aa0
DM		 1747 if (i == 2)
1748 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1749 gp->dev->name);
1da177e4
LT		 1750 }
1751 }
1752
1753 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1754 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1755 u32 val;
1756
1757 /* Init datapath mode register. */
1758 if (gp->phy_type == phy_mii_mdio0 ||
1759 gp->phy_type == phy_mii_mdio1) {
1760 val = PCS_DMODE_MGM;
1761 } else if (gp->phy_type == phy_serialink) {
1762 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1763 } else {
1764 val = PCS_DMODE_ESM;
1765 }
1766
1767 writel(val, gp->regs + PCS_DMODE);
1768 }
1769
1770 if (gp->phy_type == phy_mii_mdio0 ||
1771 gp->phy_type == phy_mii_mdio1) {
1772 // XXX check for errors
1773 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1774
1775 /* Init PHY */
1776 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1777 gp->phy_mii.def->ops->init(&gp->phy_mii);
1778 } else {
8c83f80b
DM		 1779 gem_pcs_reset(gp);
1780 gem_pcs_reinit_adv(gp);
1da177e4
LT		 1781 }
1782
1783 /* Default aneg parameters */
1784 gp->timer_ticks = 0;
1785 gp->lstate = link_down;
1786 netif_carrier_off(gp->dev);
1787
1788 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1789 spin_lock_irq(&gp->lock);
1790 gem_begin_auto_negotiation(gp, NULL);
1791 spin_unlock_irq(&gp->lock);
1792}
1793
1794/* Must be invoked under gp->lock and gp->tx_lock. */
1795static void gem_init_dma(struct gem *gp)
1796{
1797 u64 desc_dma = (u64) gp->gblock_dvma;
1798 u32 val;
1799
1800 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1801 writel(val, gp->regs + TXDMA_CFG);
1802
1803 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1804 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1805 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1806
1807 writel(0, gp->regs + TXDMA_KICK);
1808
1809 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1810 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1811 writel(val, gp->regs + RXDMA_CFG);
1812
1813 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1814 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1815
1816 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1817
1818 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1819 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1820 writel(val, gp->regs + RXDMA_PTHRESH);
1821
1822 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1823 writel(((5 & RXDMA_BLANK_IPKTS) |
1824 ((8 << 12) & RXDMA_BLANK_ITIME)),
1825 gp->regs + RXDMA_BLANK);
1826 else
1827 writel(((5 & RXDMA_BLANK_IPKTS) |
1828 ((4 << 12) & RXDMA_BLANK_ITIME)),
1829 gp->regs + RXDMA_BLANK);
1830}
1831
1832/* Must be invoked under gp->lock and gp->tx_lock. */
1833static u32 gem_setup_multicast(struct gem *gp)
1834{
1835 u32 rxcfg = 0;
1836 int i;
6aa20a22 1837
1da177e4
LT		 1838 if ((gp->dev->flags & IFF_ALLMULTI) ||
1839 (gp->dev->mc_count > 256)) {
1840 for (i=0; i<16; i++)
1841 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1842 rxcfg |= MAC_RXCFG_HFE;
1843 } else if (gp->dev->flags & IFF_PROMISC) {
1844 rxcfg |= MAC_RXCFG_PROM;
1845 } else {
1846 u16 hash_table[16];
1847 u32 crc;
1848 struct dev_mc_list *dmi = gp->dev->mc_list;
1849 int i;
1850
1851 for (i = 0; i < 16; i++)
1852 hash_table[i] = 0;
1853
1854 for (i = 0; i < gp->dev->mc_count; i++) {
1855 char *addrs = dmi->dmi_addr;
1856
1857 dmi = dmi->next;
1858
1859 if (!(*addrs & 1))
1860 continue;
1861
1862 crc = ether_crc_le(6, addrs);
1863 crc >>= 24;
1864 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1865 }
1866 for (i=0; i<16; i++)
1867 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1868 rxcfg |= MAC_RXCFG_HFE;
1869 }
1870
1871 return rxcfg;
1872}
1873
1874/* Must be invoked under gp->lock and gp->tx_lock. */
1875static void gem_init_mac(struct gem *gp)
1876{
1877 unsigned char *e = &gp->dev->dev_addr[0];
1878
1879 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1880
1881 writel(0x00, gp->regs + MAC_IPG0);
1882 writel(0x08, gp->regs + MAC_IPG1);
1883 writel(0x04, gp->regs + MAC_IPG2);
1884 writel(0x40, gp->regs + MAC_STIME);
1885 writel(0x40, gp->regs + MAC_MINFSZ);
1886
1887 /* Ethernet payload + header + FCS + optional VLAN tag. */
1888 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1889
1890 writel(0x07, gp->regs + MAC_PASIZE);
1891 writel(0x04, gp->regs + MAC_JAMSIZE);
1892 writel(0x10, gp->regs + MAC_ATTLIM);
1893 writel(0x8808, gp->regs + MAC_MCTYPE);
1894
1895 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1896
1897 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1898 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1899 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1900
1901 writel(0, gp->regs + MAC_ADDR3);
1902 writel(0, gp->regs + MAC_ADDR4);
1903 writel(0, gp->regs + MAC_ADDR5);
1904
1905 writel(0x0001, gp->regs + MAC_ADDR6);
1906 writel(0xc200, gp->regs + MAC_ADDR7);
1907 writel(0x0180, gp->regs + MAC_ADDR8);
1908
1909 writel(0, gp->regs + MAC_AFILT0);
1910 writel(0, gp->regs + MAC_AFILT1);
1911 writel(0, gp->regs + MAC_AFILT2);
1912 writel(0, gp->regs + MAC_AF21MSK);
1913 writel(0, gp->regs + MAC_AF0MSK);
1914
1915 gp->mac_rx_cfg = gem_setup_multicast(gp);
1916#ifdef STRIP_FCS
1917 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1918#endif
1919 writel(0, gp->regs + MAC_NCOLL);
1920 writel(0, gp->regs + MAC_FASUCC);
1921 writel(0, gp->regs + MAC_ECOLL);
1922 writel(0, gp->regs + MAC_LCOLL);
1923 writel(0, gp->regs + MAC_DTIMER);
1924 writel(0, gp->regs + MAC_PATMPS);
1925 writel(0, gp->regs + MAC_RFCTR);
1926 writel(0, gp->regs + MAC_LERR);
1927 writel(0, gp->regs + MAC_AERR);
1928 writel(0, gp->regs + MAC_FCSERR);
1929 writel(0, gp->regs + MAC_RXCVERR);
1930
1931 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1932 * them once a link is established.
1933 */
1934 writel(0, gp->regs + MAC_TXCFG);
1935 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1936 writel(0, gp->regs + MAC_MCCFG);
1937 writel(0, gp->regs + MAC_XIFCFG);
1938
1939 /* Setup MAC interrupts. We want to get all of the interesting
1940 * counter expiration events, but we do not want to hear about
1941 * normal rx/tx as the DMA engine tells us that.
1942 */
1943 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1944 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1945
1946 /* Don't enable even the PAUSE interrupts for now, we
1947 * make no use of those events other than to record them.
1948 */
1949 writel(0xffffffff, gp->regs + MAC_MCMASK);
1950
1951 /* Don't enable GEM's WOL in normal operations
1952 */
1953 if (gp->has_wol)
1954 writel(0, gp->regs + WOL_WAKECSR);
1955}
1956
1957/* Must be invoked under gp->lock and gp->tx_lock. */
1958static void gem_init_pause_thresholds(struct gem *gp)
1959{
1960 u32 cfg;
1961
1962 /* Calculate pause thresholds. Setting the OFF threshold to the
1963 * full RX fifo size effectively disables PAUSE generation which
1964 * is what we do for 10/100 only GEMs which have FIFOs too small
1965 * to make real gains from PAUSE.
1966 */
1967 if (gp->rx_fifo_sz <= (2 * 1024)) {
1968 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1969 } else {
1970 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1971 int off = (gp->rx_fifo_sz - (max_frame * 2));
1972 int on = off - max_frame;
1973
1974 gp->rx_pause_off = off;
1975 gp->rx_pause_on = on;
1976 }
1977
1978
1979 /* Configure the chip "burst" DMA mode & enable some
1980 * HW bug fixes on Apple version
1981 */
1982 cfg = 0;
1983 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1984 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1985#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1986 cfg |= GREG_CFG_IBURST;
1987#endif
1988 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1989 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1990 writel(cfg, gp->regs + GREG_CFG);
1991
1992 /* If Infinite Burst didn't stick, then use different
1993 * thresholds (and Apple bug fixes don't exist)
1994 */
1995 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1996 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1997 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1998 writel(cfg, gp->regs + GREG_CFG);
6aa20a22 1999 }
1da177e4
LT		 2000}
2001
2002static int gem_check_invariants(struct gem *gp)
2003{
2004 struct pci_dev *pdev = gp->pdev;
2005 u32 mif_cfg;
2006
2007 /* On Apple's sungem, we can't rely on registers as the chip
2008 * was been powered down by the firmware. The PHY is looked
2009 * up later on.
2010 */
2011 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
2012 gp->phy_type = phy_mii_mdio0;
2013 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2014 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2015 gp->swrst_base = 0;
2016
2017 mif_cfg = readl(gp->regs + MIF_CFG);
2018 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2019 mif_cfg |= MIF_CFG_MDI0;
2020 writel(mif_cfg, gp->regs + MIF_CFG);
2021 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2022 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2023
2024 /* We hard-code the PHY address so we can properly bring it out of
2025 * reset later on, we can't really probe it at this point, though
2026 * that isn't an issue.
2027 */
2028 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2029 gp->mii_phy_addr = 1;
2030 else
2031 gp->mii_phy_addr = 0;
2032
2033 return 0;
2034 }
2035
2036 mif_cfg = readl(gp->regs + MIF_CFG);
2037
2038 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2039 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2040 /* One of the MII PHYs _must_ be present
2041 * as this chip has no gigabit PHY.
2042 */
2043 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2044 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2045 mif_cfg);
2046 return -1;
2047 }
2048 }
2049
2050 /* Determine initial PHY interface type guess. MDIO1 is the
2051 * external PHY and thus takes precedence over MDIO0.
2052 */
6aa20a22 2053
1da177e4
LT		 2054 if (mif_cfg & MIF_CFG_MDI1) {
2055 gp->phy_type = phy_mii_mdio1;
2056 mif_cfg |= MIF_CFG_PSELECT;
2057 writel(mif_cfg, gp->regs + MIF_CFG);
2058 } else if (mif_cfg & MIF_CFG_MDI0) {
2059 gp->phy_type = phy_mii_mdio0;
2060 mif_cfg &= ~MIF_CFG_PSELECT;
2061 writel(mif_cfg, gp->regs + MIF_CFG);
2062 } else {
2063 gp->phy_type = phy_serialink;
2064 }
2065 if (gp->phy_type == phy_mii_mdio1 ||
2066 gp->phy_type == phy_mii_mdio0) {
2067 int i;
2068
2069 for (i = 0; i < 32; i++) {
2070 gp->mii_phy_addr = i;
2071 if (phy_read(gp, MII_BMCR) != 0xffff)
2072 break;
2073 }
2074 if (i == 32) {
2075 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2076 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2077 return -1;
2078 }
2079 gp->phy_type = phy_serdes;
2080 }
2081 }
2082
2083 /* Fetch the FIFO configurations now too. */
2084 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2085 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2086
2087 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2088 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2089 if (gp->tx_fifo_sz != (9 * 1024) ||
2090 gp->rx_fifo_sz != (20 * 1024)) {
2091 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2092 gp->tx_fifo_sz, gp->rx_fifo_sz);
2093 return -1;
2094 }
2095 gp->swrst_base = 0;
2096 } else {
2097 if (gp->tx_fifo_sz != (2 * 1024) ||
2098 gp->rx_fifo_sz != (2 * 1024)) {
2099 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2100 gp->tx_fifo_sz, gp->rx_fifo_sz);
2101 return -1;
2102 }
2103 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2104 }
2105 }
2106
2107 return 0;
2108}
2109
2110/* Must be invoked under gp->lock and gp->tx_lock. */
2111static void gem_reinit_chip(struct gem *gp)
2112{
2113 /* Reset the chip */
2114 gem_reset(gp);
2115
2116 /* Make sure ints are disabled */
2117 gem_disable_ints(gp);
2118
2119 /* Allocate & setup ring buffers */
2120 gem_init_rings(gp);
2121
2122 /* Configure pause thresholds */
2123 gem_init_pause_thresholds(gp);
2124
2125 /* Init DMA & MAC engines */
2126 gem_init_dma(gp);
2127 gem_init_mac(gp);
2128}
2129
2130
2131/* Must be invoked with no lock held. */
2132static void gem_stop_phy(struct gem *gp, int wol)
2133{
7fb76aa0 2134 u32 mifcfg;
1da177e4
LT		 2135 unsigned long flags;
2136
2137 /* Let the chip settle down a bit, it seems that helps
2138 * for sleep mode on some models
2139 */
2140 msleep(10);
2141
2142 /* Make sure we aren't polling PHY status change. We
2143 * don't currently use that feature though
2144 */
7fb76aa0
DM		 2145 mifcfg = readl(gp->regs + MIF_CFG);
2146 mifcfg &= ~MIF_CFG_POLL;
2147 writel(mifcfg, gp->regs + MIF_CFG);
1da177e4
LT		 2148
2149 if (wol && gp->has_wol) {
2150 unsigned char *e = &gp->dev->dev_addr[0];
2151 u32 csr;
2152
2153 /* Setup wake-on-lan for MAGIC packet */
2154 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
6aa20a22 2155 gp->regs + MAC_RXCFG);
1da177e4
LT		 2156 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2157 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2158 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2159
2160 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2161 csr = WOL_WAKECSR_ENABLE;
2162 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2163 csr |= WOL_WAKECSR_MII;
2164 writel(csr, gp->regs + WOL_WAKECSR);
2165 } else {
2166 writel(0, gp->regs + MAC_RXCFG);
2167 (void)readl(gp->regs + MAC_RXCFG);
2168 /* Machine sleep will die in strange ways if we
2169 * dont wait a bit here, looks like the chip takes
2170 * some time to really shut down
2171 */
2172 msleep(10);
2173 }
2174
2175 writel(0, gp->regs + MAC_TXCFG);
2176 writel(0, gp->regs + MAC_XIFCFG);
2177 writel(0, gp->regs + TXDMA_CFG);
2178 writel(0, gp->regs + RXDMA_CFG);
2179
2180 if (!wol) {
2181 spin_lock_irqsave(&gp->lock, flags);
2182 spin_lock(&gp->tx_lock);
2183 gem_reset(gp);
2184 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2185 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2186 spin_unlock(&gp->tx_lock);
2187 spin_unlock_irqrestore(&gp->lock, flags);
2188
2189 /* No need to take the lock here */
2190
2191 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2192 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2193
2194 /* According to Apple, we must set the MDIO pins to this begnign
2195 * state or we may 1) eat more current, 2) damage some PHYs
2196 */
7fb76aa0 2197 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
1da177e4
LT		 2198 writel(0, gp->regs + MIF_BBCLK);
2199 writel(0, gp->regs + MIF_BBDATA);
2200 writel(0, gp->regs + MIF_BBOENAB);
2201 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2202 (void) readl(gp->regs + MAC_XIFCFG);
2203 }
2204}
2205
2206
2207static int gem_do_start(struct net_device *dev)
2208{
8f15ea42 2209 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2210 unsigned long flags;
2211
2212 spin_lock_irqsave(&gp->lock, flags);
2213 spin_lock(&gp->tx_lock);
2214
2215 /* Enable the cell */
2216 gem_get_cell(gp);
2217
2218 /* Init & setup chip hardware */
2219 gem_reinit_chip(gp);
2220
2221 gp->running = 1;
2222
71822faa
IV		 2223 napi_enable(&gp->napi);
2224
1da177e4
LT		 2225 if (gp->lstate == link_up) {
2226 netif_carrier_on(gp->dev);
2227 gem_set_link_modes(gp);
2228 }
2229
2230 netif_wake_queue(gp->dev);
2231
2232 spin_unlock(&gp->tx_lock);
2233 spin_unlock_irqrestore(&gp->lock, flags);
2234
2235 if (request_irq(gp->pdev->irq, gem_interrupt,
1fb9df5d 2236 IRQF_SHARED, dev->name, (void *)dev)) {
1da177e4
LT		 2237 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2238
2239 spin_lock_irqsave(&gp->lock, flags);
2240 spin_lock(&gp->tx_lock);
2241
71822faa
IV		 2242 napi_disable(&gp->napi);
2243
1da177e4
LT		 2244 gp->running = 0;
2245 gem_reset(gp);
2246 gem_clean_rings(gp);
2247 gem_put_cell(gp);
6aa20a22 2248
1da177e4
LT		 2249 spin_unlock(&gp->tx_lock);
2250 spin_unlock_irqrestore(&gp->lock, flags);
2251
2252 return -EAGAIN;
2253 }
2254
2255 return 0;
2256}
2257
2258static void gem_do_stop(struct net_device *dev, int wol)
2259{
8f15ea42 2260 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2261 unsigned long flags;
2262
2263 spin_lock_irqsave(&gp->lock, flags);
2264 spin_lock(&gp->tx_lock);
2265
2266 gp->running = 0;
2267
2268 /* Stop netif queue */
2269 netif_stop_queue(dev);
2270
2271 /* Make sure ints are disabled */
2272 gem_disable_ints(gp);
2273
2274 /* We can drop the lock now */
2275 spin_unlock(&gp->tx_lock);
2276 spin_unlock_irqrestore(&gp->lock, flags);
2277
2278 /* If we are going to sleep with WOL */
2279 gem_stop_dma(gp);
2280 msleep(10);
2281 if (!wol)
2282 gem_reset(gp);
2283 msleep(10);
2284
2285 /* Get rid of rings */
2286 gem_clean_rings(gp);
2287
2288 /* No irq needed anymore */
2289 free_irq(gp->pdev->irq, (void *) dev);
2290
2291 /* Cell not needed neither if no WOL */
2292 if (!wol) {
2293 spin_lock_irqsave(&gp->lock, flags);
2294 gem_put_cell(gp);
2295 spin_unlock_irqrestore(&gp->lock, flags);
2296 }
2297}
2298
c4028958 2299static void gem_reset_task(struct work_struct *work)
1da177e4 2300{
c4028958 2301 struct gem *gp = container_of(work, struct gem, reset_task);
1da177e4 2302
e3968fc0 2303 mutex_lock(&gp->pm_mutex);
1da177e4 2304
dde655c9
JB		 2305 if (gp->opened)
2306 napi_disable(&gp->napi);
1da177e4
LT		 2307
2308 spin_lock_irq(&gp->lock);
2309 spin_lock(&gp->tx_lock);
2310
1da177e4
LT		 2311 if (gp->running) {
2312 netif_stop_queue(gp->dev);
2313
2314 /* Reset the chip & rings */
2315 gem_reinit_chip(gp);
2316 if (gp->lstate == link_up)
2317 gem_set_link_modes(gp);
2318 netif_wake_queue(gp->dev);
2319 }
dde655c9 2320
1da177e4
LT		 2321 gp->reset_task_pending = 0;
2322
2323 spin_unlock(&gp->tx_lock);
2324 spin_unlock_irq(&gp->lock);
2325
dde655c9
JB		 2326 if (gp->opened)
2327 napi_enable(&gp->napi);
1da177e4 2328
e3968fc0 2329 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2330}
2331
2332
2333static int gem_open(struct net_device *dev)
2334{
8f15ea42 2335 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2336 int rc = 0;
2337
e3968fc0 2338 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2339
2340 /* We need the cell enabled */
2341 if (!gp->asleep)
2342 rc = gem_do_start(dev);
2343 gp->opened = (rc == 0);
2344
e3968fc0 2345 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2346
2347 return rc;
2348}
2349
2350static int gem_close(struct net_device *dev)
2351{
8f15ea42 2352 struct gem *gp = netdev_priv(dev);
1da177e4 2353
e3968fc0 2354 mutex_lock(&gp->pm_mutex);
1da177e4 2355
62768e28
JB		 2356 napi_disable(&gp->napi);
2357
6aa20a22 2358 gp->opened = 0;
1da177e4
LT		 2359 if (!gp->asleep)
2360 gem_do_stop(dev, 0);
2361
e3968fc0 2362 mutex_unlock(&gp->pm_mutex);
6aa20a22 2363
1da177e4
LT		 2364 return 0;
2365}
2366
2367#ifdef CONFIG_PM
2368static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2369{
2370 struct net_device *dev = pci_get_drvdata(pdev);
8f15ea42 2371 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2372 unsigned long flags;
2373
e3968fc0 2374 mutex_lock(&gp->pm_mutex);
1da177e4 2375
1da177e4
LT		 2376 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2377 dev->name,
2378 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
6aa20a22 2379
1da177e4
LT		 2380 /* Keep the cell enabled during the entire operation */
2381 spin_lock_irqsave(&gp->lock, flags);
2382 spin_lock(&gp->tx_lock);
2383 gem_get_cell(gp);
2384 spin_unlock(&gp->tx_lock);
2385 spin_unlock_irqrestore(&gp->lock, flags);
2386
2387 /* If the driver is opened, we stop the MAC */
2388 if (gp->opened) {
62768e28
JB		 2389 napi_disable(&gp->napi);
2390
1da177e4
LT		 2391 /* Stop traffic, mark us closed */
2392 netif_device_detach(dev);
2393
2394 /* Switch off MAC, remember WOL setting */
2395 gp->asleep_wol = gp->wake_on_lan;
2396 gem_do_stop(dev, gp->asleep_wol);
2397 } else
2398 gp->asleep_wol = 0;
2399
2400 /* Mark us asleep */
2401 gp->asleep = 1;
2402 wmb();
2403
2404 /* Stop the link timer */
2405 del_timer_sync(&gp->link_timer);
2406
e3968fc0 2407 /* Now we release the mutex to not block the reset task who
1da177e4
LT		 2408 * can take it too. We are marked asleep, so there will be no
2409 * conflict here
2410 */
e3968fc0 2411 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2412
2413 /* Wait for a pending reset task to complete */
2414 while (gp->reset_task_pending)
2415 yield();
2416 flush_scheduled_work();
2417
2418 /* Shut the PHY down eventually and setup WOL */
2419 gem_stop_phy(gp, gp->asleep_wol);
2420
2421 /* Make sure bus master is disabled */
2422 pci_disable_device(gp->pdev);
2423
2424 /* Release the cell, no need to take a lock at this point since
2425 * nothing else can happen now
2426 */
2427 gem_put_cell(gp);
2428
2429 return 0;
2430}
2431
2432static int gem_resume(struct pci_dev *pdev)
2433{
2434 struct net_device *dev = pci_get_drvdata(pdev);
8f15ea42 2435 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2436 unsigned long flags;
2437
2438 printk(KERN_INFO "%s: resuming\n", dev->name);
2439
e3968fc0 2440 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2441
2442 /* Keep the cell enabled during the entire operation, no need to
2443 * take a lock here tho since nothing else can happen while we are
2444 * marked asleep
2445 */
2446 gem_get_cell(gp);
2447
2448 /* Make sure PCI access and bus master are enabled */
2449 if (pci_enable_device(gp->pdev)) {
2450 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2451 dev->name);
2452 /* Put cell and forget it for now, it will be considered as
2453 * still asleep, a new sleep cycle may bring it back
2454 */
2455 gem_put_cell(gp);
e3968fc0 2456 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2457 return 0;
2458 }
2459 pci_set_master(gp->pdev);
2460
2461 /* Reset everything */
2462 gem_reset(gp);
2463
2464 /* Mark us woken up */
2465 gp->asleep = 0;
2466 wmb();
2467
2468 /* Bring the PHY back. Again, lock is useless at this point as
2469 * nothing can be happening until we restart the whole thing
2470 */
2471 gem_init_phy(gp);
2472
2473 /* If we were opened, bring everything back */
2474 if (gp->opened) {
2475 /* Restart MAC */
2476 gem_do_start(dev);
2477
2478 /* Re-attach net device */
2479 netif_device_attach(dev);
1da177e4
LT		 2480 }
2481
2482 spin_lock_irqsave(&gp->lock, flags);
2483 spin_lock(&gp->tx_lock);
2484
2485 /* If we had WOL enabled, the cell clock was never turned off during
2486 * sleep, so we end up beeing unbalanced. Fix that here
2487 */
2488 if (gp->asleep_wol)
2489 gem_put_cell(gp);
2490
2491 /* This function doesn't need to hold the cell, it will be held if the
2492 * driver is open by gem_do_start().
2493 */
2494 gem_put_cell(gp);
2495
2496 spin_unlock(&gp->tx_lock);
2497 spin_unlock_irqrestore(&gp->lock, flags);
2498
e3968fc0 2499 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2500
2501 return 0;
2502}
2503#endif /* CONFIG_PM */
2504
2505static struct net_device_stats *gem_get_stats(struct net_device *dev)
2506{
8f15ea42 2507 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2508 struct net_device_stats *stats = &gp->net_stats;
2509
2510 spin_lock_irq(&gp->lock);
2511 spin_lock(&gp->tx_lock);
2512
2513 /* I have seen this being called while the PM was in progress,
2514 * so we shield against this
2515 */
2516 if (gp->running) {
2517 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2518 writel(0, gp->regs + MAC_FCSERR);
2519
2520 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2521 writel(0, gp->regs + MAC_AERR);
2522
2523 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2524 writel(0, gp->regs + MAC_LERR);
2525
2526 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2527 stats->collisions +=
2528 (readl(gp->regs + MAC_ECOLL) +
2529 readl(gp->regs + MAC_LCOLL));
2530 writel(0, gp->regs + MAC_ECOLL);
2531 writel(0, gp->regs + MAC_LCOLL);
2532 }
2533
2534 spin_unlock(&gp->tx_lock);
2535 spin_unlock_irq(&gp->lock);
2536
2537 return &gp->net_stats;
2538}
2539
09c72ec8
RV		 2540static int gem_set_mac_address(struct net_device *dev, void *addr)
2541{
2542 struct sockaddr *macaddr = (struct sockaddr *) addr;
8f15ea42 2543 struct gem *gp = netdev_priv(dev);
09c72ec8
RV		 2544 unsigned char *e = &dev->dev_addr[0];
2545
2546 if (!is_valid_ether_addr(macaddr->sa_data))
2547 return -EADDRNOTAVAIL;
2548
2549 if (!netif_running(dev) || !netif_device_present(dev)) {
2550 /* We'll just catch it later when the
2551 * device is up'd or resumed.
2552 */
2553 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2554 return 0;
2555 }
2556
2557 mutex_lock(&gp->pm_mutex);
2558 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2559 if (gp->running) {
2560 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2561 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2562 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2563 }
2564 mutex_unlock(&gp->pm_mutex);
2565
2566 return 0;
2567}
2568
1da177e4
LT		 2569static void gem_set_multicast(struct net_device *dev)
2570{
8f15ea42 2571 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2572 u32 rxcfg, rxcfg_new;
2573 int limit = 10000;
6aa20a22 2574
1da177e4
LT		 2575
2576 spin_lock_irq(&gp->lock);
2577 spin_lock(&gp->tx_lock);
2578
2579 if (!gp->running)
2580 goto bail;
2581
2582 netif_stop_queue(dev);
2583
2584 rxcfg = readl(gp->regs + MAC_RXCFG);
2585 rxcfg_new = gem_setup_multicast(gp);
2586#ifdef STRIP_FCS
2587 rxcfg_new |= MAC_RXCFG_SFCS;
2588#endif
2589 gp->mac_rx_cfg = rxcfg_new;
6aa20a22 2590
1da177e4
LT		 2591 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2592 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2593 if (!limit--)
2594 break;
2595 udelay(10);
2596 }
2597
2598 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2599 rxcfg |= rxcfg_new;
2600
2601 writel(rxcfg, gp->regs + MAC_RXCFG);
2602
2603 netif_wake_queue(dev);
2604
2605 bail:
2606 spin_unlock(&gp->tx_lock);
2607 spin_unlock_irq(&gp->lock);
2608}
2609
2610/* Jumbo-grams don't seem to work :-( */
2611#define GEM_MIN_MTU 68
2612#if 1
2613#define GEM_MAX_MTU 1500
2614#else
2615#define GEM_MAX_MTU 9000
2616#endif
2617
2618static int gem_change_mtu(struct net_device *dev, int new_mtu)
2619{
8f15ea42 2620 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2621
2622 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2623 return -EINVAL;
2624
2625 if (!netif_running(dev) || !netif_device_present(dev)) {
2626 /* We'll just catch it later when the
2627 * device is up'd or resumed.
2628 */
2629 dev->mtu = new_mtu;
2630 return 0;
2631 }
2632
e3968fc0 2633 mutex_lock(&gp->pm_mutex);
1da177e4
LT		 2634 spin_lock_irq(&gp->lock);
2635 spin_lock(&gp->tx_lock);
2636 dev->mtu = new_mtu;
2637 if (gp->running) {
2638 gem_reinit_chip(gp);
2639 if (gp->lstate == link_up)
2640 gem_set_link_modes(gp);
2641 }
2642 spin_unlock(&gp->tx_lock);
2643 spin_unlock_irq(&gp->lock);
e3968fc0 2644 mutex_unlock(&gp->pm_mutex);
1da177e4
LT		 2645
2646 return 0;
2647}
2648
2649static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2650{
8f15ea42 2651 struct gem *gp = netdev_priv(dev);
6aa20a22 2652
1da177e4
LT		 2653 strcpy(info->driver, DRV_NAME);
2654 strcpy(info->version, DRV_VERSION);
2655 strcpy(info->bus_info, pci_name(gp->pdev));
2656}
6aa20a22 2657
1da177e4
LT		 2658static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2659{
8f15ea42 2660 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2661
2662 if (gp->phy_type == phy_mii_mdio0 ||
2663 gp->phy_type == phy_mii_mdio1) {
2664 if (gp->phy_mii.def)
2665 cmd->supported = gp->phy_mii.def->features;
2666 else
2667 cmd->supported = (SUPPORTED_10baseT_Half |
2668 SUPPORTED_10baseT_Full);
2669
2670 /* XXX hardcoded stuff for now */
2671 cmd->port = PORT_MII;
2672 cmd->transceiver = XCVR_EXTERNAL;
2673 cmd->phy_address = 0; /* XXX fixed PHYAD */
2674
2675 /* Return current PHY settings */
2676 spin_lock_irq(&gp->lock);
2677 cmd->autoneg = gp->want_autoneg;
2678 cmd->speed = gp->phy_mii.speed;
6aa20a22 2679 cmd->duplex = gp->phy_mii.duplex;
1da177e4
LT		 2680 cmd->advertising = gp->phy_mii.advertising;
2681
2682 /* If we started with a forced mode, we don't have a default
2683 * advertise set, we need to return something sensible so
2684 * userland can re-enable autoneg properly.
2685 */
2686 if (cmd->advertising == 0)
2687 cmd->advertising = cmd->supported;
2688 spin_unlock_irq(&gp->lock);
2689 } else { // XXX PCS ?
2690 cmd->supported =
2691 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2692 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2693 SUPPORTED_Autoneg);
2694 cmd->advertising = cmd->supported;
2695 cmd->speed = 0;
2696 cmd->duplex = cmd->port = cmd->phy_address =
2697 cmd->transceiver = cmd->autoneg = 0;
fbf0229e
HL		 2698
2699 /* serdes means usually a Fibre connector, with most fixed */
2700 if (gp->phy_type == phy_serdes) {
2701 cmd->port = PORT_FIBRE;
2702 cmd->supported = (SUPPORTED_1000baseT_Half |
2703 SUPPORTED_1000baseT_Full |
2704 SUPPORTED_FIBRE | SUPPORTED_Autoneg |
2705 SUPPORTED_Pause | SUPPORTED_Asym_Pause);
2706 cmd->advertising = cmd->supported;
2707 cmd->transceiver = XCVR_INTERNAL;
2708 if (gp->lstate == link_up)
2709 cmd->speed = SPEED_1000;
2710 cmd->duplex = DUPLEX_FULL;
2711 cmd->autoneg = 1;
2712 }
1da177e4
LT		 2713 }
2714 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2715
2716 return 0;
2717}
2718
2719static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2720{
8f15ea42 2721 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2722
2723 /* Verify the settings we care about. */
2724 if (cmd->autoneg != AUTONEG_ENABLE &&
2725 cmd->autoneg != AUTONEG_DISABLE)
2726 return -EINVAL;
2727
2728 if (cmd->autoneg == AUTONEG_ENABLE &&
2729 cmd->advertising == 0)
2730 return -EINVAL;
2731
2732 if (cmd->autoneg == AUTONEG_DISABLE &&
2733 ((cmd->speed != SPEED_1000 &&
2734 cmd->speed != SPEED_100 &&
2735 cmd->speed != SPEED_10) ||
2736 (cmd->duplex != DUPLEX_HALF &&
2737 cmd->duplex != DUPLEX_FULL)))
2738 return -EINVAL;
6aa20a22 2739
1da177e4
LT		 2740 /* Apply settings and restart link process. */
2741 spin_lock_irq(&gp->lock);
2742 gem_get_cell(gp);
2743 gem_begin_auto_negotiation(gp, cmd);
2744 gem_put_cell(gp);
2745 spin_unlock_irq(&gp->lock);
2746
2747 return 0;
2748}
2749
2750static int gem_nway_reset(struct net_device *dev)
2751{
8f15ea42 2752 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2753
2754 if (!gp->want_autoneg)
2755 return -EINVAL;
2756
2757 /* Restart link process. */
2758 spin_lock_irq(&gp->lock);
2759 gem_get_cell(gp);
2760 gem_begin_auto_negotiation(gp, NULL);
2761 gem_put_cell(gp);
2762 spin_unlock_irq(&gp->lock);
2763
2764 return 0;
2765}
2766
2767static u32 gem_get_msglevel(struct net_device *dev)
2768{
8f15ea42 2769 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2770 return gp->msg_enable;
2771}
6aa20a22 2772
1da177e4
LT		 2773static void gem_set_msglevel(struct net_device *dev, u32 value)
2774{
8f15ea42 2775 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2776 gp->msg_enable = value;
2777}
2778
2779
2780/* Add more when I understand how to program the chip */
2781/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2782
2783#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2784
2785static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2786{
8f15ea42 2787 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2788
2789 /* Add more when I understand how to program the chip */
2790 if (gp->has_wol) {
2791 wol->supported = WOL_SUPPORTED_MASK;
2792 wol->wolopts = gp->wake_on_lan;
2793 } else {
2794 wol->supported = 0;
2795 wol->wolopts = 0;
2796 }
2797}
2798
2799static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2800{
8f15ea42 2801 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2802
2803 if (!gp->has_wol)
2804 return -EOPNOTSUPP;
2805 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2806 return 0;
2807}
2808
7282d491 2809static const struct ethtool_ops gem_ethtool_ops = {
1da177e4
LT		 2810 .get_drvinfo = gem_get_drvinfo,
2811 .get_link = ethtool_op_get_link,
2812 .get_settings = gem_get_settings,
2813 .set_settings = gem_set_settings,
2814 .nway_reset = gem_nway_reset,
2815 .get_msglevel = gem_get_msglevel,
2816 .set_msglevel = gem_set_msglevel,
2817 .get_wol = gem_get_wol,
2818 .set_wol = gem_set_wol,
2819};
2820
2821static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2822{
8f15ea42 2823 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2824 struct mii_ioctl_data *data = if_mii(ifr);
2825 int rc = -EOPNOTSUPP;
2826 unsigned long flags;
2827
e3968fc0 2828 /* Hold the PM mutex while doing ioctl's or we may collide
1da177e4
LT		 2829 * with power management.
2830 */
e3968fc0 2831 mutex_lock(&gp->pm_mutex);
6aa20a22 2832
1da177e4
LT		 2833 spin_lock_irqsave(&gp->lock, flags);
2834 gem_get_cell(gp);
2835 spin_unlock_irqrestore(&gp->lock, flags);
2836
2837 switch (cmd) {
2838 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2839 data->phy_id = gp->mii_phy_addr;
2840 /* Fallthrough... */
2841
2842 case SIOCGMIIREG: /* Read MII PHY register. */
2843 if (!gp->running)
2844 rc = -EAGAIN;
2845 else {
2846 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2847 data->reg_num & 0x1f);
2848 rc = 0;
2849 }
2850 break;
2851
2852 case SIOCSMIIREG: /* Write MII PHY register. */
7ab0f273 2853 if (!gp->running)
1da177e4
LT		 2854 rc = -EAGAIN;
2855 else {
2856 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2857 data->val_in);
2858 rc = 0;
2859 }
2860 break;
2861 };
6aa20a22 2862
1da177e4
LT		 2863 spin_lock_irqsave(&gp->lock, flags);
2864 gem_put_cell(gp);
2865 spin_unlock_irqrestore(&gp->lock, flags);
2866
e3968fc0 2867 mutex_unlock(&gp->pm_mutex);
6aa20a22 2868
1da177e4
LT		 2869 return rc;
2870}
2871
dadb830d 2872#if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
1da177e4 2873/* Fetch MAC address from vital product data of PCI ROM. */
4120b028 2874static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
1da177e4
LT		 2875{
2876 int this_offset;
2877
2878 for (this_offset = 0x20; this_offset < len; this_offset++) {
2879 void __iomem *p = rom_base + this_offset;
2880 int i;
2881
2882 if (readb(p + 0) != 0x90 ||
2883 readb(p + 1) != 0x00 ||
2884 readb(p + 2) != 0x09 ||
2885 readb(p + 3) != 0x4e ||
2886 readb(p + 4) != 0x41 ||
2887 readb(p + 5) != 0x06)
2888 continue;
2889
2890 this_offset += 6;
2891 p += 6;
2892
2893 for (i = 0; i < 6; i++)
2894 dev_addr[i] = readb(p + i);
4120b028 2895 return 1;
1da177e4 2896 }
4120b028 2897 return 0;
1da177e4
LT		 2898}
2899
2900static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2901{
4120b028
LT		 2902 size_t size;
2903 void __iomem *p = pci_map_rom(pdev, &size);
1da177e4 2904
4120b028
LT		 2905 if (p) {
2906 int found;
1da177e4 2907
4120b028
LT		 2908 found = readb(p) == 0x55 &&
2909 readb(p + 1) == 0xaa &&
2910 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2911 pci_unmap_rom(pdev, p);
2912 if (found)
2913 return;
2914 }
1da177e4 2915
1da177e4
LT		 2916 /* Sun MAC prefix then 3 random bytes. */
2917 dev_addr[0] = 0x08;
2918 dev_addr[1] = 0x00;
2919 dev_addr[2] = 0x20;
2920 get_random_bytes(dev_addr + 3, 3);
2921 return;
2922}
2923#endif /* not Sparc and not PPC */
2924
2925static int __devinit gem_get_device_address(struct gem *gp)
2926{
dadb830d 2927#if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
1da177e4 2928 struct net_device *dev = gp->dev;
1a2509c9 2929 const unsigned char *addr;
1da177e4 2930
40cd3a45 2931 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
1da177e4 2932 if (addr == NULL) {
457e1a8a
DM		 2933#ifdef CONFIG_SPARC
2934 addr = idprom->id_ethaddr;
2935#else
1da177e4
LT		 2936 printk("\n");
2937 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2938 return -1;
457e1a8a 2939#endif
1da177e4
LT		 2940 }
2941 memcpy(dev->dev_addr, addr, 6);
2942#else
2943 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2944#endif
2945 return 0;
2946}
2947
14904398 2948static void gem_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2949{
2950 struct net_device *dev = pci_get_drvdata(pdev);
2951
2952 if (dev) {
8f15ea42 2953 struct gem *gp = netdev_priv(dev);
1da177e4
LT		 2954
2955 unregister_netdev(dev);
2956
2957 /* Stop the link timer */
2958 del_timer_sync(&gp->link_timer);
2959
2960 /* We shouldn't need any locking here */
2961 gem_get_cell(gp);
2962
2963 /* Wait for a pending reset task to complete */
2964 while (gp->reset_task_pending)
2965 yield();
2966 flush_scheduled_work();
2967
2968 /* Shut the PHY down */
2969 gem_stop_phy(gp, 0);
2970
2971 gem_put_cell(gp);
2972
2973 /* Make sure bus master is disabled */
2974 pci_disable_device(gp->pdev);
2975
2976 /* Free resources */
2977 pci_free_consistent(pdev,
2978 sizeof(struct gem_init_block),
2979 gp->init_block,
2980 gp->gblock_dvma);
2981 iounmap(gp->regs);
2982 pci_release_regions(pdev);
2983 free_netdev(dev);
2984
2985 pci_set_drvdata(pdev, NULL);
2986 }
2987}
2988
d9a811d5
SH		 2989static const struct net_device_ops gem_netdev_ops = {
2990 .ndo_open = gem_open,
2991 .ndo_stop = gem_close,
2992 .ndo_start_xmit = gem_start_xmit,
2993 .ndo_get_stats = gem_get_stats,
2994 .ndo_set_multicast_list = gem_set_multicast,
2995 .ndo_do_ioctl = gem_ioctl,
2996 .ndo_tx_timeout = gem_tx_timeout,
2997 .ndo_change_mtu = gem_change_mtu,
d9a811d5 2998 .ndo_validate_addr = eth_validate_addr,
5ed0102f
SH		 2999 .ndo_set_mac_address = gem_set_mac_address,
3000#ifdef CONFIG_NET_POLL_CONTROLLER
3001 .ndo_poll_controller = gem_poll_controller,
3002#endif
d9a811d5
SH		 3003};
3004
1da177e4
LT		 3005static int __devinit gem_init_one(struct pci_dev *pdev,
3006 const struct pci_device_id *ent)
3007{
3008 static int gem_version_printed = 0;
3009 unsigned long gemreg_base, gemreg_len;
3010 struct net_device *dev;
3011 struct gem *gp;
0795af57 3012 int err, pci_using_dac;
1da177e4
LT		 3013
3014 if (gem_version_printed++ == 0)
3015 printk(KERN_INFO "%s", version);
3016
3017 /* Apple gmac note: during probe, the chip is powered up by
3018 * the arch code to allow the code below to work (and to let
3019 * the chip be probed on the config space. It won't stay powered
3020 * up until the interface is brought up however, so we can't rely
3021 * on register configuration done at this point.
3022 */
3023 err = pci_enable_device(pdev);
3024 if (err) {
3025 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
3026 "aborting.\n");
3027 return err;
3028 }
3029 pci_set_master(pdev);
3030
3031 /* Configure DMA attributes. */
3032
3033 /* All of the GEM documentation states that 64-bit DMA addressing
3034 * is fully supported and should work just fine. However the
3035 * front end for RIO based GEMs is different and only supports
3036 * 32-bit addressing.
3037 *
3038 * For now we assume the various PPC GEMs are 32-bit only as well.
3039 */
3040 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
3041 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
6a35528a 3042 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1da177e4
LT		 3043 pci_using_dac = 1;
3044 } else {
284901a9 3045 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4
LT		 3046 if (err) {
3047 printk(KERN_ERR PFX "No usable DMA configuration, "
3048 "aborting.\n");
3049 goto err_disable_device;
3050 }
3051 pci_using_dac = 0;
3052 }
6aa20a22 3053
1da177e4
LT		 3054 gemreg_base = pci_resource_start(pdev, 0);
3055 gemreg_len = pci_resource_len(pdev, 0);
3056
3057 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3058 printk(KERN_ERR PFX "Cannot find proper PCI device "
3059 "base address, aborting.\n");
3060 err = -ENODEV;
3061 goto err_disable_device;
3062 }
3063
3064 dev = alloc_etherdev(sizeof(*gp));
3065 if (!dev) {
3066 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3067 err = -ENOMEM;
3068 goto err_disable_device;
3069 }
1da177e4
LT		 3070 SET_NETDEV_DEV(dev, &pdev->dev);
3071
8f15ea42 3072 gp = netdev_priv(dev);
1da177e4
LT		 3073
3074 err = pci_request_regions(pdev, DRV_NAME);
3075 if (err) {
3076 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3077 "aborting.\n");
3078 goto err_out_free_netdev;
3079 }
3080
3081 gp->pdev = pdev;
3082 dev->base_addr = (long) pdev;
3083 gp->dev = dev;
3084
3085 gp->msg_enable = DEFAULT_MSG;
3086
3087 spin_lock_init(&gp->lock);
3088 spin_lock_init(&gp->tx_lock);
e3968fc0 3089 mutex_init(&gp->pm_mutex);
1da177e4
LT		 3090
3091 init_timer(&gp->link_timer);
3092 gp->link_timer.function = gem_link_timer;
3093 gp->link_timer.data = (unsigned long) gp;
3094
c4028958 3095 INIT_WORK(&gp->reset_task, gem_reset_task);
6aa20a22 3096
1da177e4
LT		 3097 gp->lstate = link_down;
3098 gp->timer_ticks = 0;
3099 netif_carrier_off(dev);
3100
3101 gp->regs = ioremap(gemreg_base, gemreg_len);
79ea13ce 3102 if (!gp->regs) {
1da177e4
LT		 3103 printk(KERN_ERR PFX "Cannot map device registers, "
3104 "aborting.\n");
3105 err = -EIO;
3106 goto err_out_free_res;
3107 }
3108
3109 /* On Apple, we want a reference to the Open Firmware device-tree
3110 * node. We use it for clock control.
3111 */
457e1a8a 3112#if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
1da177e4
LT		 3113 gp->of_node = pci_device_to_OF_node(pdev);
3114#endif
3115
3116 /* Only Apple version supports WOL afaik */
3117 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3118 gp->has_wol = 1;
3119
3120 /* Make sure cell is enabled */
3121 gem_get_cell(gp);
3122
3123 /* Make sure everything is stopped and in init state */
3124 gem_reset(gp);
3125
3126 /* Fill up the mii_phy structure (even if we won't use it) */
3127 gp->phy_mii.dev = dev;
3128 gp->phy_mii.mdio_read = _phy_read;
3129 gp->phy_mii.mdio_write = _phy_write;
3c326fe9
BH		 3130#ifdef CONFIG_PPC_PMAC
3131 gp->phy_mii.platform_data = gp->of_node;
3132#endif
1da177e4
LT		 3133 /* By default, we start with autoneg */
3134 gp->want_autoneg = 1;
3135
3136 /* Check fifo sizes, PHY type, etc... */
3137 if (gem_check_invariants(gp)) {
3138 err = -ENODEV;
3139 goto err_out_iounmap;
3140 }
3141
3142 /* It is guaranteed that the returned buffer will be at least
3143 * PAGE_SIZE aligned.
3144 */
3145 gp->init_block = (struct gem_init_block *)
3146 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3147 &gp->gblock_dvma);
3148 if (!gp->init_block) {
3149 printk(KERN_ERR PFX "Cannot allocate init block, "
3150 "aborting.\n");
3151 err = -ENOMEM;
3152 goto err_out_iounmap;
3153 }
3154
3155 if (gem_get_device_address(gp))
3156 goto err_out_free_consistent;
3157
d9a811d5 3158 dev->netdev_ops = &gem_netdev_ops;
bea3348e 3159 netif_napi_add(dev, &gp->napi, gem_poll, 64);
1da177e4 3160 dev->ethtool_ops = &gem_ethtool_ops;
1da177e4 3161 dev->watchdog_timeo = 5 * HZ;
1da177e4
LT		 3162 dev->irq = pdev->irq;
3163 dev->dma = 0;
1da177e4
LT		 3164
3165 /* Set that now, in case PM kicks in now */
3166 pci_set_drvdata(pdev, dev);
3167
3168 /* Detect & init PHY, start autoneg, we release the cell now
3169 * too, it will be managed by whoever needs it
3170 */
3171 gem_init_phy(gp);
3172
3173 spin_lock_irq(&gp->lock);
3174 gem_put_cell(gp);
3175 spin_unlock_irq(&gp->lock);
3176
3177 /* Register with kernel */
3178 if (register_netdev(dev)) {
3179 printk(KERN_ERR PFX "Cannot register net device, "
3180 "aborting.\n");
3181 err = -ENOMEM;
3182 goto err_out_free_consistent;
3183 }
3184
e174961c
JB		 3185 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3186 dev->name, dev->dev_addr);
1da177e4
LT		 3187
3188 if (gp->phy_type == phy_mii_mdio0 ||
3189 gp->phy_type == phy_mii_mdio1)
6aa20a22 3190 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
1da177e4
LT		 3191 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3192
3193 /* GEM can do it all... */
3194 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3195 if (pci_using_dac)
3196 dev->features |= NETIF_F_HIGHDMA;
3197
3198 return 0;
3199
3200err_out_free_consistent:
3201 gem_remove_one(pdev);
3202err_out_iounmap:
3203 gem_put_cell(gp);
3204 iounmap(gp->regs);
3205
3206err_out_free_res:
3207 pci_release_regions(pdev);
3208
3209err_out_free_netdev:
3210 free_netdev(dev);
3211err_disable_device:
3212 pci_disable_device(pdev);
3213 return err;
3214
3215}
3216
3217
3218static struct pci_driver gem_driver = {
3219 .name = GEM_MODULE_NAME,
3220 .id_table = gem_pci_tbl,
3221 .probe = gem_init_one,
14904398 3222 .remove = gem_remove_one,
1da177e4
LT		 3223#ifdef CONFIG_PM
3224 .suspend = gem_suspend,
3225 .resume = gem_resume,
3226#endif /* CONFIG_PM */
3227};
3228
3229static int __init gem_init(void)
3230{
29917620 3231 return pci_register_driver(&gem_driver);
1da177e4
LT		 3232}
3233
3234static void __exit gem_cleanup(void)
3235{
3236 pci_unregister_driver(&gem_driver);
3237}
3238
3239module_init(gem_init);
3240module_exit(gem_cleanup);
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