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sundance: Add initial ethtool stats support
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1da177e4
LT		 1/* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
2/*
3 Written 1999-2000 by Donald Becker.
4
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
11
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
15 Annapolis MD 21403
16
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
03a8c661 19 [link no longer provides useful info -jgarzik]
e714d99c
PDM		 20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
1da177e4 22
1da177e4
LT		 23*/
24
25#define DRV_NAME "sundance"
d5b20697
AG		 26#define DRV_VERSION "1.2"
27#define DRV_RELDATE "11-Sep-2006"
1da177e4
LT		 28
29
30/* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
f71e1309 35static const int multicast_filter_limit = 32;
1da177e4
LT		 36
37/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
40 need a copy-align. */
41static int rx_copybreak;
42static int flowctrl=1;
43
44/* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
51 1 10Mbps half duplex.
52 2 10Mbps full duplex.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
55*/
56#define MAX_UNITS 8
57static char *media[MAX_UNITS];
58
59
60/* Operational parameters that are set at compile time. */
61
62/* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
66 Tx error recovery.
67 Large receive rings merely waste memory. */
68#define TX_RING_SIZE 32
69#define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70#define RX_RING_SIZE 64
71#define RX_BUDGET 32
72#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
74
75/* Operational parameters that usually are not changed. */
76/* Time in jiffies before concluding the transmitter is hung. */
77#define TX_TIMEOUT (4*HZ)
78#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
79
80/* Include files, designed to support most kernel versions 2.0.0 and later. */
81#include <linux/module.h>
82#include <linux/kernel.h>
83#include <linux/string.h>
84#include <linux/timer.h>
85#include <linux/errno.h>
86#include <linux/ioport.h>
1da177e4
LT		 87#include <linux/interrupt.h>
88#include <linux/pci.h>
89#include <linux/netdevice.h>
90#include <linux/etherdevice.h>
91#include <linux/skbuff.h>
92#include <linux/init.h>
93#include <linux/bitops.h>
94#include <asm/uaccess.h>
95#include <asm/processor.h> /* Processor type for cache alignment. */
96#include <asm/io.h>
97#include <linux/delay.h>
98#include <linux/spinlock.h>
0c8a745f 99#include <linux/dma-mapping.h>
1da177e4
LT		 100#include <linux/crc32.h>
101#include <linux/ethtool.h>
102#include <linux/mii.h>
1da177e4
LT		 103
104/* These identify the driver base version and may not be removed. */
3af0fe39
SH		 105static const char version[] __devinitconst =
106 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE
107 " Written by Donald Becker\n";
1da177e4
LT		 108
109MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
110MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
111MODULE_LICENSE("GPL");
112
113module_param(debug, int, 0);
114module_param(rx_copybreak, int, 0);
115module_param_array(media, charp, NULL, 0);
116module_param(flowctrl, int, 0);
117MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
118MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
119MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
120
121/*
122 Theory of Operation
123
124I. Board Compatibility
125
126This driver is designed for the Sundance Technologies "Alta" ST201 chip.
127
128II. Board-specific settings
129
130III. Driver operation
131
132IIIa. Ring buffers
133
134This driver uses two statically allocated fixed-size descriptor lists
135formed into rings by a branch from the final descriptor to the beginning of
136the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
137Some chips explicitly use only 2^N sized rings, while others use a
138'next descriptor' pointer that the driver forms into rings.
139
140IIIb/c. Transmit/Receive Structure
141
142This driver uses a zero-copy receive and transmit scheme.
143The driver allocates full frame size skbuffs for the Rx ring buffers at
144open() time and passes the skb->data field to the chip as receive data
145buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
146a fresh skbuff is allocated and the frame is copied to the new skbuff.
147When the incoming frame is larger, the skbuff is passed directly up the
148protocol stack. Buffers consumed this way are replaced by newly allocated
149skbuffs in a later phase of receives.
150
151The RX_COPYBREAK value is chosen to trade-off the memory wasted by
152using a full-sized skbuff for small frames vs. the copying costs of larger
153frames. New boards are typically used in generously configured machines
154and the underfilled buffers have negligible impact compared to the benefit of
155a single allocation size, so the default value of zero results in never
156copying packets. When copying is done, the cost is usually mitigated by using
157a combined copy/checksum routine. Copying also preloads the cache, which is
158most useful with small frames.
159
160A subtle aspect of the operation is that the IP header at offset 14 in an
161ethernet frame isn't longword aligned for further processing.
162Unaligned buffers are permitted by the Sundance hardware, so
163frames are received into the skbuff at an offset of "+2", 16-byte aligning
164the IP header.
165
166IIId. Synchronization
167
168The driver runs as two independent, single-threaded flows of control. One
169is the send-packet routine, which enforces single-threaded use by the
170dev->tbusy flag. The other thread is the interrupt handler, which is single
171threaded by the hardware and interrupt handling software.
172
173The send packet thread has partial control over the Tx ring and 'dev->tbusy'
174flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
175queue slot is empty, it clears the tbusy flag when finished otherwise it sets
176the 'lp->tx_full' flag.
177
178The interrupt handler has exclusive control over the Rx ring and records stats
179from the Tx ring. After reaping the stats, it marks the Tx queue entry as
180empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
181clears both the tx_full and tbusy flags.
182
183IV. Notes
184
185IVb. References
186
187The Sundance ST201 datasheet, preliminary version.
b71b95ef
PDM		 188The Kendin KS8723 datasheet, preliminary version.
189The ICplus IP100 datasheet, preliminary version.
190http://www.scyld.com/expert/100mbps.html
191http://www.scyld.com/expert/NWay.html
1da177e4
LT		 192
193IVc. Errata
194
195*/
196
197/* Work-around for Kendin chip bugs. */
198#ifndef CONFIG_SUNDANCE_MMIO
199#define USE_IO_OPS 1
200#endif
201
a3aa1884 202static DEFINE_PCI_DEVICE_TABLE(sundance_pci_tbl) = {
46009c8b
JG		 203 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
204 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
205 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
206 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
207 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
208 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
209 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
210 { }
1da177e4
LT		 211};
212MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
213
214enum {
215 netdev_io_size = 128
216};
217
218struct pci_id_info {
219 const char *name;
220};
46009c8b 221static const struct pci_id_info pci_id_tbl[] __devinitdata = {
1da177e4
LT		 222 {"D-Link DFE-550TX FAST Ethernet Adapter"},
223 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
224 {"D-Link DFE-580TX 4 port Server Adapter"},
225 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
226 {"D-Link DL10050-based FAST Ethernet Adapter"},
227 {"Sundance Technology Alta"},
1668b19f 228 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
46009c8b 229 { } /* terminate list. */
1da177e4
LT		 230};
231
232/* This driver was written to use PCI memory space, however x86-oriented
233 hardware often uses I/O space accesses. */
234
235/* Offsets to the device registers.
236 Unlike software-only systems, device drivers interact with complex hardware.
237 It's not useful to define symbolic names for every register bit in the
238 device. The name can only partially document the semantics and make
239 the driver longer and more difficult to read.
240 In general, only the important configuration values or bits changed
241 multiple times should be defined symbolically.
242*/
243enum alta_offsets {
244 DMACtrl = 0x00,
245 TxListPtr = 0x04,
246 TxDMABurstThresh = 0x08,
247 TxDMAUrgentThresh = 0x09,
248 TxDMAPollPeriod = 0x0a,
249 RxDMAStatus = 0x0c,
250 RxListPtr = 0x10,
251 DebugCtrl0 = 0x1a,
252 DebugCtrl1 = 0x1c,
253 RxDMABurstThresh = 0x14,
254 RxDMAUrgentThresh = 0x15,
255 RxDMAPollPeriod = 0x16,
256 LEDCtrl = 0x1a,
257 ASICCtrl = 0x30,
258 EEData = 0x34,
259 EECtrl = 0x36,
1da177e4
LT		 260 FlashAddr = 0x40,
261 FlashData = 0x44,
262 TxStatus = 0x46,
263 TxFrameId = 0x47,
264 DownCounter = 0x18,
265 IntrClear = 0x4a,
266 IntrEnable = 0x4c,
267 IntrStatus = 0x4e,
268 MACCtrl0 = 0x50,
269 MACCtrl1 = 0x52,
270 StationAddr = 0x54,
271 MaxFrameSize = 0x5A,
272 RxMode = 0x5c,
273 MIICtrl = 0x5e,
274 MulticastFilter0 = 0x60,
275 MulticastFilter1 = 0x64,
276 RxOctetsLow = 0x68,
277 RxOctetsHigh = 0x6a,
278 TxOctetsLow = 0x6c,
279 TxOctetsHigh = 0x6e,
280 TxFramesOK = 0x70,
281 RxFramesOK = 0x72,
282 StatsCarrierError = 0x74,
283 StatsLateColl = 0x75,
284 StatsMultiColl = 0x76,
285 StatsOneColl = 0x77,
286 StatsTxDefer = 0x78,
287 RxMissed = 0x79,
288 StatsTxXSDefer = 0x7a,
289 StatsTxAbort = 0x7b,
290 StatsBcastTx = 0x7c,
291 StatsBcastRx = 0x7d,
292 StatsMcastTx = 0x7e,
293 StatsMcastRx = 0x7f,
294 /* Aliased and bogus values! */
295 RxStatus = 0x0c,
296};
297enum ASICCtrl_HiWord_bit {
298 GlobalReset = 0x0001,
299 RxReset = 0x0002,
300 TxReset = 0x0004,
301 DMAReset = 0x0008,
302 FIFOReset = 0x0010,
303 NetworkReset = 0x0020,
304 HostReset = 0x0040,
305 ResetBusy = 0x0400,
306};
307
308/* Bits in the interrupt status/mask registers. */
309enum intr_status_bits {
310 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
311 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
312 IntrDrvRqst=0x0040,
313 StatsMax=0x0080, LinkChange=0x0100,
314 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
315};
316
317/* Bits in the RxMode register. */
318enum rx_mode_bits {
319 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
320 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
321};
322/* Bits in MACCtrl. */
323enum mac_ctrl0_bits {
324 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
325 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
326};
327enum mac_ctrl1_bits {
328 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
329 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
330 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
331};
332
333/* The Rx and Tx buffer descriptors. */
334/* Note that using only 32 bit fields simplifies conversion to big-endian
335 architectures. */
336struct netdev_desc {
14c9d9b0
AV		 337 __le32 next_desc;
338 __le32 status;
339 struct desc_frag { __le32 addr, length; } frag[1];
1da177e4
LT		 340};
341
342/* Bits in netdev_desc.status */
343enum desc_status_bits {
344 DescOwn=0x8000,
345 DescEndPacket=0x4000,
346 DescEndRing=0x2000,
347 LastFrag=0x80000000,
348 DescIntrOnTx=0x8000,
349 DescIntrOnDMADone=0x80000000,
350 DisableAlign = 0x00000001,
351};
352
353#define PRIV_ALIGN 15 /* Required alignment mask */
354/* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
355 within the structure. */
356#define MII_CNT 4
357struct netdev_private {
358 /* Descriptor rings first for alignment. */
359 struct netdev_desc *rx_ring;
360 struct netdev_desc *tx_ring;
361 struct sk_buff* rx_skbuff[RX_RING_SIZE];
362 struct sk_buff* tx_skbuff[TX_RING_SIZE];
363 dma_addr_t tx_ring_dma;
364 dma_addr_t rx_ring_dma;
1da177e4 365 struct timer_list timer; /* Media monitoring timer. */
725a4a46
DK		 366 /* ethtool extra stats */
367 struct {
368 u64 tx_multiple_collisions;
369 u64 tx_single_collisions;
370 u64 tx_late_collisions;
371 u64 tx_deferred;
372 u64 tx_deferred_excessive;
373 u64 tx_aborted;
374 u64 tx_bcasts;
375 u64 rx_bcasts;
376 u64 tx_mcasts;
377 u64 rx_mcasts;
378 } xstats;
1da177e4
LT		 379 /* Frequently used values: keep some adjacent for cache effect. */
380 spinlock_t lock;
1da177e4
LT		 381 int msg_enable;
382 int chip_id;
383 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
384 unsigned int rx_buf_sz; /* Based on MTU+slack. */
385 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
386 unsigned int cur_tx, dirty_tx;
387 /* These values are keep track of the transceiver/media in use. */
388 unsigned int flowctrl:1;
389 unsigned int default_port:4; /* Last dev->if_port value. */
390 unsigned int an_enable:1;
391 unsigned int speed;
392 struct tasklet_struct rx_tasklet;
393 struct tasklet_struct tx_tasklet;
394 int budget;
395 int cur_task;
396 /* Multicast and receive mode. */
397 spinlock_t mcastlock; /* SMP lock multicast updates. */
398 u16 mcast_filter[4];
399 /* MII transceiver section. */
400 struct mii_if_info mii_if;
401 int mii_preamble_required;
402 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
403 struct pci_dev *pci_dev;
404 void __iomem *base;
7b738b55 405 spinlock_t statlock;
1da177e4
LT		 406};
407
408/* The station address location in the EEPROM. */
409#define EEPROM_SA_OFFSET 0x10
410#define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
411 IntrDrvRqst | IntrTxDone | StatsMax | \
412 LinkChange)
413
414static int change_mtu(struct net_device *dev, int new_mtu);
415static int eeprom_read(void __iomem *ioaddr, int location);
416static int mdio_read(struct net_device *dev, int phy_id, int location);
417static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
50500155 418static int mdio_wait_link(struct net_device *dev, int wait);
1da177e4
LT		 419static int netdev_open(struct net_device *dev);
420static void check_duplex(struct net_device *dev);
421static void netdev_timer(unsigned long data);
422static void tx_timeout(struct net_device *dev);
423static void init_ring(struct net_device *dev);
61357325 424static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev);
1da177e4 425static int reset_tx (struct net_device *dev);
7d12e780 426static irqreturn_t intr_handler(int irq, void *dev_instance);
1da177e4
LT		 427static void rx_poll(unsigned long data);
428static void tx_poll(unsigned long data);
429static void refill_rx (struct net_device *dev);
430static void netdev_error(struct net_device *dev, int intr_status);
431static void netdev_error(struct net_device *dev, int intr_status);
432static void set_rx_mode(struct net_device *dev);
433static int __set_mac_addr(struct net_device *dev);
434static struct net_device_stats *get_stats(struct net_device *dev);
435static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
436static int netdev_close(struct net_device *dev);
7282d491 437static const struct ethtool_ops ethtool_ops;
1da177e4 438
b71b95ef
PDM		 439static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
440{
441 struct netdev_private *np = netdev_priv(dev);
442 void __iomem *ioaddr = np->base + ASICCtrl;
443 int countdown;
444
445 /* ST201 documentation states ASICCtrl is a 32bit register */
446 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
447 /* ST201 documentation states reset can take up to 1 ms */
448 countdown = 10 + 1;
449 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
450 if (--countdown == 0) {
451 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
452 break;
453 }
454 udelay(100);
455 }
456}
457
633a277e
SH		 458static const struct net_device_ops netdev_ops = {
459 .ndo_open = netdev_open,
460 .ndo_stop = netdev_close,
461 .ndo_start_xmit = start_tx,
462 .ndo_get_stats = get_stats,
463 .ndo_set_multicast_list = set_rx_mode,
464 .ndo_do_ioctl = netdev_ioctl,
465 .ndo_tx_timeout = tx_timeout,
466 .ndo_change_mtu = change_mtu,
467 .ndo_set_mac_address = eth_mac_addr,
468 .ndo_validate_addr = eth_validate_addr,
469};
470
1da177e4
LT		 471static int __devinit sundance_probe1 (struct pci_dev *pdev,
472 const struct pci_device_id *ent)
473{
474 struct net_device *dev;
475 struct netdev_private *np;
476 static int card_idx;
477 int chip_idx = ent->driver_data;
478 int irq;
479 int i;
480 void __iomem *ioaddr;
481 u16 mii_ctl;
482 void *ring_space;
483 dma_addr_t ring_dma;
484#ifdef USE_IO_OPS
485 int bar = 0;
486#else
487 int bar = 1;
488#endif
ac1d49f8 489 int phy, phy_end, phy_idx = 0;
1da177e4
LT		 490
491/* when built into the kernel, we only print version if device is found */
492#ifndef MODULE
493 static int printed_version;
494 if (!printed_version++)
495 printk(version);
496#endif
497
498 if (pci_enable_device(pdev))
499 return -EIO;
500 pci_set_master(pdev);
501
502 irq = pdev->irq;
503
504 dev = alloc_etherdev(sizeof(*np));
505 if (!dev)
506 return -ENOMEM;
1da177e4
LT		 507 SET_NETDEV_DEV(dev, &pdev->dev);
508
509 if (pci_request_regions(pdev, DRV_NAME))
510 goto err_out_netdev;
511
512 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
513 if (!ioaddr)
514 goto err_out_res;
515
516 for (i = 0; i < 3; i++)
14c9d9b0
AV		 517 ((__le16 *)dev->dev_addr)[i] =
518 cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
30d60a82 519 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 520
521 dev->base_addr = (unsigned long)ioaddr;
522 dev->irq = irq;
523
524 np = netdev_priv(dev);
525 np->base = ioaddr;
526 np->pci_dev = pdev;
527 np->chip_id = chip_idx;
528 np->msg_enable = (1 << debug) - 1;
529 spin_lock_init(&np->lock);
7b738b55 530 spin_lock_init(&np->statlock);
1da177e4
LT		 531 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
532 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
533
0c8a745f
DK		 534 ring_space = dma_alloc_coherent(&pdev->dev, TX_TOTAL_SIZE,
535 &ring_dma, GFP_KERNEL);
1da177e4
LT		 536 if (!ring_space)
537 goto err_out_cleardev;
538 np->tx_ring = (struct netdev_desc *)ring_space;
539 np->tx_ring_dma = ring_dma;
540
0c8a745f
DK		 541 ring_space = dma_alloc_coherent(&pdev->dev, RX_TOTAL_SIZE,
542 &ring_dma, GFP_KERNEL);
1da177e4
LT		 543 if (!ring_space)
544 goto err_out_unmap_tx;
545 np->rx_ring = (struct netdev_desc *)ring_space;
546 np->rx_ring_dma = ring_dma;
547
548 np->mii_if.dev = dev;
549 np->mii_if.mdio_read = mdio_read;
550 np->mii_if.mdio_write = mdio_write;
551 np->mii_if.phy_id_mask = 0x1f;
552 np->mii_if.reg_num_mask = 0x1f;
553
554 /* The chip-specific entries in the device structure. */
633a277e 555 dev->netdev_ops = &netdev_ops;
1da177e4 556 SET_ETHTOOL_OPS(dev, &ethtool_ops);
1da177e4 557 dev->watchdog_timeo = TX_TIMEOUT;
633a277e 558
1da177e4
LT		 559 pci_set_drvdata(pdev, dev);
560
1da177e4
LT		 561 i = register_netdev(dev);
562 if (i)
563 goto err_out_unmap_rx;
564
e174961c 565 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
0795af57 566 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
e174961c 567 dev->dev_addr, irq);
1da177e4 568
67ec2f80
JL		 569 np->phys[0] = 1; /* Default setting */
570 np->mii_preamble_required++;
ac1d49f8 571
0d615ec2
ACM		 572 /*
573 * It seems some phys doesn't deal well with address 0 being accessed
ac1d49f8 574 * first
0d615ec2 575 */
ac1d49f8
JG		 576 if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
577 phy = 0;
578 phy_end = 31;
579 } else {
580 phy = 1;
581 phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
582 }
583 for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
b06c093e 584 int phyx = phy & 0x1f;
0d615ec2 585 int mii_status = mdio_read(dev, phyx, MII_BMSR);
67ec2f80 586 if (mii_status != 0xffff && mii_status != 0x0000) {
b06c093e
JL		 587 np->phys[phy_idx++] = phyx;
588 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
67ec2f80
JL		 589 if ((mii_status & 0x0040) == 0)
590 np->mii_preamble_required++;
591 printk(KERN_INFO "%s: MII PHY found at address %d, status "
592 "0x%4.4x advertising %4.4x.\n",
b06c093e 593 dev->name, phyx, mii_status, np->mii_if.advertising);
1da177e4 594 }
67ec2f80
JL		 595 }
596 np->mii_preamble_required--;
1da177e4 597
67ec2f80
JL		 598 if (phy_idx == 0) {
599 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
600 dev->name, ioread32(ioaddr + ASICCtrl));
601 goto err_out_unregister;
1da177e4
LT		 602 }
603
67ec2f80
JL		 604 np->mii_if.phy_id = np->phys[0];
605
1da177e4
LT		 606 /* Parse override configuration */
607 np->an_enable = 1;
608 if (card_idx < MAX_UNITS) {
609 if (media[card_idx] != NULL) {
610 np->an_enable = 0;
611 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
612 strcmp (media[card_idx], "4") == 0) {
613 np->speed = 100;
614 np->mii_if.full_duplex = 1;
8e95a202
JP		 615 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
616 strcmp (media[card_idx], "3") == 0) {
1da177e4
LT		 617 np->speed = 100;
618 np->mii_if.full_duplex = 0;
619 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
620 strcmp (media[card_idx], "2") == 0) {
621 np->speed = 10;
622 np->mii_if.full_duplex = 1;
623 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
624 strcmp (media[card_idx], "1") == 0) {
625 np->speed = 10;
626 np->mii_if.full_duplex = 0;
627 } else {
628 np->an_enable = 1;
629 }
630 }
631 if (flowctrl == 1)
632 np->flowctrl = 1;
633 }
634
635 /* Fibre PHY? */
636 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
637 /* Default 100Mbps Full */
638 if (np->an_enable) {
639 np->speed = 100;
640 np->mii_if.full_duplex = 1;
641 np->an_enable = 0;
642 }
643 }
644 /* Reset PHY */
645 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
646 mdelay (300);
647 /* If flow control enabled, we need to advertise it.*/
648 if (np->flowctrl)
649 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
650 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
651 /* Force media type */
652 if (!np->an_enable) {
653 mii_ctl = 0;
654 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
655 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
656 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
657 printk (KERN_INFO "Override speed=%d, %s duplex\n",
658 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
659
660 }
661
662 /* Perhaps move the reset here? */
663 /* Reset the chip to erase previous misconfiguration. */
664 if (netif_msg_hw(np))
665 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
e714d99c 666 sundance_reset(dev, 0x00ff << 16);
1da177e4
LT		 667 if (netif_msg_hw(np))
668 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
669
670 card_idx++;
671 return 0;
672
673err_out_unregister:
674 unregister_netdev(dev);
675err_out_unmap_rx:
0c8a745f
DK		 676 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
677 np->rx_ring, np->rx_ring_dma);
1da177e4 678err_out_unmap_tx:
0c8a745f
DK		 679 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
680 np->tx_ring, np->tx_ring_dma);
1da177e4
LT		 681err_out_cleardev:
682 pci_set_drvdata(pdev, NULL);
683 pci_iounmap(pdev, ioaddr);
684err_out_res:
685 pci_release_regions(pdev);
686err_out_netdev:
687 free_netdev (dev);
688 return -ENODEV;
689}
690
691static int change_mtu(struct net_device *dev, int new_mtu)
692{
693 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
694 return -EINVAL;
695 if (netif_running(dev))
696 return -EBUSY;
697 dev->mtu = new_mtu;
698 return 0;
699}
700
701#define eeprom_delay(ee_addr) ioread32(ee_addr)
702/* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
703static int __devinit eeprom_read(void __iomem *ioaddr, int location)
704{
705 int boguscnt = 10000; /* Typical 1900 ticks. */
706 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
707 do {
708 eeprom_delay(ioaddr + EECtrl);
709 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
710 return ioread16(ioaddr + EEData);
711 }
712 } while (--boguscnt > 0);
713 return 0;
714}
715
716/* MII transceiver control section.
717 Read and write the MII registers using software-generated serial
718 MDIO protocol. See the MII specifications or DP83840A data sheet
719 for details.
720
721 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
722 met by back-to-back 33Mhz PCI cycles. */
723#define mdio_delay() ioread8(mdio_addr)
724
725enum mii_reg_bits {
726 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
727};
728#define MDIO_EnbIn (0)
729#define MDIO_WRITE0 (MDIO_EnbOutput)
730#define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
731
732/* Generate the preamble required for initial synchronization and
733 a few older transceivers. */
734static void mdio_sync(void __iomem *mdio_addr)
735{
736 int bits = 32;
737
738 /* Establish sync by sending at least 32 logic ones. */
739 while (--bits >= 0) {
740 iowrite8(MDIO_WRITE1, mdio_addr);
741 mdio_delay();
742 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
743 mdio_delay();
744 }
745}
746
747static int mdio_read(struct net_device *dev, int phy_id, int location)
748{
749 struct netdev_private *np = netdev_priv(dev);
750 void __iomem *mdio_addr = np->base + MIICtrl;
751 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
752 int i, retval = 0;
753
754 if (np->mii_preamble_required)
755 mdio_sync(mdio_addr);
756
757 /* Shift the read command bits out. */
758 for (i = 15; i >= 0; i--) {
759 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
760
761 iowrite8(dataval, mdio_addr);
762 mdio_delay();
763 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
764 mdio_delay();
765 }
766 /* Read the two transition, 16 data, and wire-idle bits. */
767 for (i = 19; i > 0; i--) {
768 iowrite8(MDIO_EnbIn, mdio_addr);
769 mdio_delay();
770 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
771 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
772 mdio_delay();
773 }
774 return (retval>>1) & 0xffff;
775}
776
777static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
778{
779 struct netdev_private *np = netdev_priv(dev);
780 void __iomem *mdio_addr = np->base + MIICtrl;
781 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
782 int i;
783
784 if (np->mii_preamble_required)
785 mdio_sync(mdio_addr);
786
787 /* Shift the command bits out. */
788 for (i = 31; i >= 0; i--) {
789 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
790
791 iowrite8(dataval, mdio_addr);
792 mdio_delay();
793 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
794 mdio_delay();
795 }
796 /* Clear out extra bits. */
797 for (i = 2; i > 0; i--) {
798 iowrite8(MDIO_EnbIn, mdio_addr);
799 mdio_delay();
800 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
801 mdio_delay();
802 }
1da177e4
LT		 803}
804
50500155
DN		 805static int mdio_wait_link(struct net_device *dev, int wait)
806{
807 int bmsr;
808 int phy_id;
809 struct netdev_private *np;
810
811 np = netdev_priv(dev);
812 phy_id = np->phys[0];
813
814 do {
815 bmsr = mdio_read(dev, phy_id, MII_BMSR);
816 if (bmsr & 0x0004)
817 return 0;
818 mdelay(1);
819 } while (--wait > 0);
820 return -1;
821}
822
1da177e4
LT		 823static int netdev_open(struct net_device *dev)
824{
825 struct netdev_private *np = netdev_priv(dev);
826 void __iomem *ioaddr = np->base;
acd70c2b 827 unsigned long flags;
1da177e4
LT		 828 int i;
829
830 /* Do we need to reset the chip??? */
831
a0607fd3 832 i = request_irq(dev->irq, intr_handler, IRQF_SHARED, dev->name, dev);
1da177e4
LT		 833 if (i)
834 return i;
835
836 if (netif_msg_ifup(np))
837 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
838 dev->name, dev->irq);
839 init_ring(dev);
840
841 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
842 /* The Tx list pointer is written as packets are queued. */
843
844 /* Initialize other registers. */
845 __set_mac_addr(dev);
846#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
847 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
848#else
849 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
850#endif
851 if (dev->mtu > 2047)
852 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
853
854 /* Configure the PCI bus bursts and FIFO thresholds. */
855
856 if (dev->if_port == 0)
857 dev->if_port = np->default_port;
858
859 spin_lock_init(&np->mcastlock);
860
861 set_rx_mode(dev);
862 iowrite16(0, ioaddr + IntrEnable);
863 iowrite16(0, ioaddr + DownCounter);
864 /* Set the chip to poll every N*320nsec. */
865 iowrite8(100, ioaddr + RxDMAPollPeriod);
866 iowrite8(127, ioaddr + TxDMAPollPeriod);
867 /* Fix DFE-580TX packet drop issue */
44c10138 868 if (np->pci_dev->revision >= 0x14)
1da177e4
LT		 869 iowrite8(0x01, ioaddr + DebugCtrl1);
870 netif_start_queue(dev);
871
acd70c2b
JH		 872 spin_lock_irqsave(&np->lock, flags);
873 reset_tx(dev);
874 spin_unlock_irqrestore(&np->lock, flags);
875
1da177e4
LT		 876 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
877
878 if (netif_msg_ifup(np))
879 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
880 "MAC Control %x, %4.4x %4.4x.\n",
881 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
882 ioread32(ioaddr + MACCtrl0),
883 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
884
885 /* Set the timer to check for link beat. */
886 init_timer(&np->timer);
887 np->timer.expires = jiffies + 3*HZ;
888 np->timer.data = (unsigned long)dev;
c061b18d 889 np->timer.function = netdev_timer; /* timer handler */
1da177e4
LT		 890 add_timer(&np->timer);
891
892 /* Enable interrupts by setting the interrupt mask. */
893 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
894
895 return 0;
896}
897
898static void check_duplex(struct net_device *dev)
899{
900 struct netdev_private *np = netdev_priv(dev);
901 void __iomem *ioaddr = np->base;
902 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
903 int negotiated = mii_lpa & np->mii_if.advertising;
904 int duplex;
905
906 /* Force media */
907 if (!np->an_enable || mii_lpa == 0xffff) {
908 if (np->mii_if.full_duplex)
909 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
910 ioaddr + MACCtrl0);
911 return;
912 }
913
914 /* Autonegotiation */
915 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
916 if (np->mii_if.full_duplex != duplex) {
917 np->mii_if.full_duplex = duplex;
918 if (netif_msg_link(np))
919 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
920 "negotiated capability %4.4x.\n", dev->name,
921 duplex ? "full" : "half", np->phys[0], negotiated);
62660e28 922 iowrite16(ioread16(ioaddr + MACCtrl0) | (duplex ? 0x20 : 0), ioaddr + MACCtrl0);
1da177e4
LT		 923 }
924}
925
926static void netdev_timer(unsigned long data)
927{
928 struct net_device *dev = (struct net_device *)data;
929 struct netdev_private *np = netdev_priv(dev);
930 void __iomem *ioaddr = np->base;
931 int next_tick = 10*HZ;
932
933 if (netif_msg_timer(np)) {
934 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
935 "Tx %x Rx %x.\n",
936 dev->name, ioread16(ioaddr + IntrEnable),
937 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
938 }
939 check_duplex(dev);
940 np->timer.expires = jiffies + next_tick;
941 add_timer(&np->timer);
942}
943
944static void tx_timeout(struct net_device *dev)
945{
946 struct netdev_private *np = netdev_priv(dev);
947 void __iomem *ioaddr = np->base;
948 unsigned long flag;
6aa20a22 949
1da177e4
LT		 950 netif_stop_queue(dev);
951 tasklet_disable(&np->tx_tasklet);
952 iowrite16(0, ioaddr + IntrEnable);
953 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
954 "TxFrameId %2.2x,"
955 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
956 ioread8(ioaddr + TxFrameId));
957
958 {
959 int i;
960 for (i=0; i<TX_RING_SIZE; i++) {
961 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
962 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
963 le32_to_cpu(np->tx_ring[i].next_desc),
964 le32_to_cpu(np->tx_ring[i].status),
965 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
6aa20a22 966 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1da177e4
LT		 967 le32_to_cpu(np->tx_ring[i].frag[0].length));
968 }
6aa20a22
JG		 969 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
970 ioread32(np->base + TxListPtr),
1da177e4 971 netif_queue_stopped(dev));
6aa20a22 972 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
1da177e4
LT		 973 np->cur_tx, np->cur_tx % TX_RING_SIZE,
974 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
975 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
976 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
977 }
978 spin_lock_irqsave(&np->lock, flag);
979
980 /* Stop and restart the chip's Tx processes . */
981 reset_tx(dev);
982 spin_unlock_irqrestore(&np->lock, flag);
983
984 dev->if_port = 0;
985
1ae5dc34 986 dev->trans_start = jiffies; /* prevent tx timeout */
553e2335 987 dev->stats.tx_errors++;
1da177e4
LT		 988 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
989 netif_wake_queue(dev);
990 }
991 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
992 tasklet_enable(&np->tx_tasklet);
993}
994
995
996/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
997static void init_ring(struct net_device *dev)
998{
999 struct netdev_private *np = netdev_priv(dev);
1000 int i;
1001
1002 np->cur_rx = np->cur_tx = 0;
1003 np->dirty_rx = np->dirty_tx = 0;
1004 np->cur_task = 0;
1005
1006 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
1007
1008 /* Initialize all Rx descriptors. */
1009 for (i = 0; i < RX_RING_SIZE; i++) {
1010 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
1011 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
1012 np->rx_ring[i].status = 0;
1013 np->rx_ring[i].frag[0].length = 0;
1014 np->rx_skbuff[i] = NULL;
1015 }
1016
1017 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1018 for (i = 0; i < RX_RING_SIZE; i++) {
1019 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1020 np->rx_skbuff[i] = skb;
1021 if (skb == NULL)
1022 break;
1023 skb->dev = dev; /* Mark as being used by this device. */
1024 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1025 np->rx_ring[i].frag[0].addr = cpu_to_le32(
0c8a745f
DK		 1026 dma_map_single(&np->pci_dev->dev, skb->data,
1027 np->rx_buf_sz, DMA_FROM_DEVICE));
d91dc279
DK		 1028 if (dma_mapping_error(&np->pci_dev->dev,
1029 np->rx_ring[i].frag[0].addr)) {
1030 dev_kfree_skb(skb);
1031 np->rx_skbuff[i] = NULL;
1032 break;
1033 }
1da177e4
LT		 1034 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
1035 }
1036 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1037
1038 for (i = 0; i < TX_RING_SIZE; i++) {
1039 np->tx_skbuff[i] = NULL;
1040 np->tx_ring[i].status = 0;
1041 }
1da177e4
LT		 1042}
1043
1044static void tx_poll (unsigned long data)
1045{
1046 struct net_device *dev = (struct net_device *)data;
1047 struct netdev_private *np = netdev_priv(dev);
1048 unsigned head = np->cur_task % TX_RING_SIZE;
6aa20a22 1049 struct netdev_desc *txdesc =
1da177e4 1050 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
6aa20a22 1051
1da177e4
LT		 1052 /* Chain the next pointer */
1053 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1054 int entry = np->cur_task % TX_RING_SIZE;
1055 txdesc = &np->tx_ring[entry];
1056 if (np->last_tx) {
1057 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1058 entry*sizeof(struct netdev_desc));
1059 }
1060 np->last_tx = txdesc;
1061 }
1062 /* Indicate the latest descriptor of tx ring */
1063 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1064
1065 if (ioread32 (np->base + TxListPtr) == 0)
1066 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1067 np->base + TxListPtr);
1da177e4
LT		 1068}
1069
61357325 1070static netdev_tx_t
1da177e4
LT		 1071start_tx (struct sk_buff *skb, struct net_device *dev)
1072{
1073 struct netdev_private *np = netdev_priv(dev);
1074 struct netdev_desc *txdesc;
1075 unsigned entry;
1076
1077 /* Calculate the next Tx descriptor entry. */
1078 entry = np->cur_tx % TX_RING_SIZE;
1079 np->tx_skbuff[entry] = skb;
1080 txdesc = &np->tx_ring[entry];
1081
1082 txdesc->next_desc = 0;
1083 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
0c8a745f
DK		 1084 txdesc->frag[0].addr = cpu_to_le32(dma_map_single(&np->pci_dev->dev,
1085 skb->data, skb->len, DMA_TO_DEVICE));
d91dc279
DK		 1086 if (dma_mapping_error(&np->pci_dev->dev,
1087 txdesc->frag[0].addr))
1088 goto drop_frame;
1da177e4
LT		 1089 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1090
1091 /* Increment cur_tx before tasklet_schedule() */
1092 np->cur_tx++;
1093 mb();
1094 /* Schedule a tx_poll() task */
1095 tasklet_schedule(&np->tx_tasklet);
1096
1097 /* On some architectures: explicitly flush cache lines here. */
8e95a202
JP		 1098 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1 &&
1099 !netif_queue_stopped(dev)) {
1da177e4
LT		 1100 /* do nothing */
1101 } else {
1102 netif_stop_queue (dev);
1103 }
1da177e4
LT		 1104 if (netif_msg_tx_queued(np)) {
1105 printk (KERN_DEBUG
1106 "%s: Transmit frame #%d queued in slot %d.\n",
1107 dev->name, np->cur_tx, entry);
1108 }
6ed10654 1109 return NETDEV_TX_OK;
d91dc279
DK		 1110
1111drop_frame:
1112 dev_kfree_skb(skb);
1113 np->tx_skbuff[entry] = NULL;
1114 dev->stats.tx_dropped++;
1115 return NETDEV_TX_OK;
1da177e4
LT		 1116}
1117
1118/* Reset hardware tx and free all of tx buffers */
1119static int
1120reset_tx (struct net_device *dev)
1121{
1122 struct netdev_private *np = netdev_priv(dev);
1123 void __iomem *ioaddr = np->base;
1124 struct sk_buff *skb;
1125 int i;
6aa20a22 1126
1da177e4
LT		 1127 /* Reset tx logic, TxListPtr will be cleaned */
1128 iowrite16 (TxDisable, ioaddr + MACCtrl1);
e714d99c
PDM		 1129 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1130
1da177e4
LT		 1131 /* free all tx skbuff */
1132 for (i = 0; i < TX_RING_SIZE; i++) {
2109f89f
JH		 1133 np->tx_ring[i].next_desc = 0;
1134
1da177e4
LT		 1135 skb = np->tx_skbuff[i];
1136 if (skb) {
0c8a745f 1137 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1138 le32_to_cpu(np->tx_ring[i].frag[0].addr),
0c8a745f 1139 skb->len, DMA_TO_DEVICE);
a9478e38 1140 dev_kfree_skb_any(skb);
1da177e4 1141 np->tx_skbuff[i] = NULL;
553e2335 1142 dev->stats.tx_dropped++;
1da177e4
LT		 1143 }
1144 }
1145 np->cur_tx = np->dirty_tx = 0;
1146 np->cur_task = 0;
2109f89f 1147
bca79eb7 1148 np->last_tx = NULL;
2109f89f
JH		 1149 iowrite8(127, ioaddr + TxDMAPollPeriod);
1150
1da177e4
LT		 1151 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1152 return 0;
1153}
1154
6aa20a22 1155/* The interrupt handler cleans up after the Tx thread,
1da177e4 1156 and schedule a Rx thread work */
7d12e780 1157static irqreturn_t intr_handler(int irq, void *dev_instance)
1da177e4
LT		 1158{
1159 struct net_device *dev = (struct net_device *)dev_instance;
1160 struct netdev_private *np = netdev_priv(dev);
1161 void __iomem *ioaddr = np->base;
1162 int hw_frame_id;
1163 int tx_cnt;
1164 int tx_status;
1165 int handled = 0;
e242040d 1166 int i;
1da177e4
LT		 1167
1168
1169 do {
1170 int intr_status = ioread16(ioaddr + IntrStatus);
1171 iowrite16(intr_status, ioaddr + IntrStatus);
1172
1173 if (netif_msg_intr(np))
1174 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1175 dev->name, intr_status);
1176
1177 if (!(intr_status & DEFAULT_INTR))
1178 break;
1179
1180 handled = 1;
1181
1182 if (intr_status & (IntrRxDMADone)) {
1183 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1184 ioaddr + IntrEnable);
1185 if (np->budget < 0)
1186 np->budget = RX_BUDGET;
1187 tasklet_schedule(&np->rx_tasklet);
1188 }
1189 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1190 tx_status = ioread16 (ioaddr + TxStatus);
1191 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1192 if (netif_msg_tx_done(np))
1193 printk
1194 ("%s: Transmit status is %2.2x.\n",
1195 dev->name, tx_status);
1196 if (tx_status & 0x1e) {
b71b95ef
PDM		 1197 if (netif_msg_tx_err(np))
1198 printk("%s: Transmit error status %4.4x.\n",
1199 dev->name, tx_status);
553e2335 1200 dev->stats.tx_errors++;
1da177e4 1201 if (tx_status & 0x10)
553e2335 1202 dev->stats.tx_fifo_errors++;
1da177e4 1203 if (tx_status & 0x08)
553e2335 1204 dev->stats.collisions++;
b71b95ef 1205 if (tx_status & 0x04)
553e2335 1206 dev->stats.tx_fifo_errors++;
1da177e4 1207 if (tx_status & 0x02)
553e2335 1208 dev->stats.tx_window_errors++;
e242040d 1209
b71b95ef
PDM		 1210 /*
1211 ** This reset has been verified on
1212 ** DFE-580TX boards ! phdm@macqel.be.
1213 */
1214 if (tx_status & 0x10) { /* TxUnderrun */
b71b95ef
PDM		 1215 /* Restart Tx FIFO and transmitter */
1216 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
b71b95ef 1217 /* No need to reset the Tx pointer here */
1da177e4 1218 }
2109f89f
JH		 1219 /* Restart the Tx. Need to make sure tx enabled */
1220 i = 10;
1221 do {
1222 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1223 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1224 break;
1225 mdelay(1);
1226 } while (--i);
1da177e4
LT		 1227 }
1228 /* Yup, this is a documentation bug. It cost me *hours*. */
1229 iowrite16 (0, ioaddr + TxStatus);
1230 if (tx_cnt < 0) {
1231 iowrite32(5000, ioaddr + DownCounter);
1232 break;
1233 }
1234 tx_status = ioread16 (ioaddr + TxStatus);
1235 }
1236 hw_frame_id = (tx_status >> 8) & 0xff;
1237 } else {
1238 hw_frame_id = ioread8(ioaddr + TxFrameId);
1239 }
6aa20a22 1240
44c10138 1241 if (np->pci_dev->revision >= 0x14) {
1da177e4
LT		 1242 spin_lock(&np->lock);
1243 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1244 int entry = np->dirty_tx % TX_RING_SIZE;
1245 struct sk_buff *skb;
1246 int sw_frame_id;
1247 sw_frame_id = (le32_to_cpu(
1248 np->tx_ring[entry].status) >> 2) & 0xff;
1249 if (sw_frame_id == hw_frame_id &&
1250 !(le32_to_cpu(np->tx_ring[entry].status)
1251 & 0x00010000))
1252 break;
6aa20a22 1253 if (sw_frame_id == (hw_frame_id + 1) %
1da177e4
LT		 1254 TX_RING_SIZE)
1255 break;
1256 skb = np->tx_skbuff[entry];
1257 /* Free the original skb. */
0c8a745f 1258 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1259 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
0c8a745f 1260 skb->len, DMA_TO_DEVICE);
1da177e4
LT		 1261 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1262 np->tx_skbuff[entry] = NULL;
1263 np->tx_ring[entry].frag[0].addr = 0;
1264 np->tx_ring[entry].frag[0].length = 0;
1265 }
1266 spin_unlock(&np->lock);
1267 } else {
1268 spin_lock(&np->lock);
1269 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1270 int entry = np->dirty_tx % TX_RING_SIZE;
1271 struct sk_buff *skb;
6aa20a22 1272 if (!(le32_to_cpu(np->tx_ring[entry].status)
1da177e4
LT		 1273 & 0x00010000))
1274 break;
1275 skb = np->tx_skbuff[entry];
1276 /* Free the original skb. */
0c8a745f 1277 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1278 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
0c8a745f 1279 skb->len, DMA_TO_DEVICE);
1da177e4
LT		 1280 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1281 np->tx_skbuff[entry] = NULL;
1282 np->tx_ring[entry].frag[0].addr = 0;
1283 np->tx_ring[entry].frag[0].length = 0;
1284 }
1285 spin_unlock(&np->lock);
1286 }
6aa20a22 1287
1da177e4
LT		 1288 if (netif_queue_stopped(dev) &&
1289 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1290 /* The ring is no longer full, clear busy flag. */
1291 netif_wake_queue (dev);
1292 }
1293 /* Abnormal error summary/uncommon events handlers. */
1294 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1295 netdev_error(dev, intr_status);
1296 } while (0);
1297 if (netif_msg_intr(np))
1298 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1299 dev->name, ioread16(ioaddr + IntrStatus));
1300 return IRQ_RETVAL(handled);
1301}
1302
1303static void rx_poll(unsigned long data)
1304{
1305 struct net_device *dev = (struct net_device *)data;
1306 struct netdev_private *np = netdev_priv(dev);
1307 int entry = np->cur_rx % RX_RING_SIZE;
1308 int boguscnt = np->budget;
1309 void __iomem *ioaddr = np->base;
1310 int received = 0;
1311
1312 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1313 while (1) {
1314 struct netdev_desc *desc = &(np->rx_ring[entry]);
1315 u32 frame_status = le32_to_cpu(desc->status);
1316 int pkt_len;
1317
1318 if (--boguscnt < 0) {
1319 goto not_done;
1320 }
1321 if (!(frame_status & DescOwn))
1322 break;
1323 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1324 if (netif_msg_rx_status(np))
1325 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1326 frame_status);
1327 if (frame_status & 0x001f4000) {
1328 /* There was a error. */
1329 if (netif_msg_rx_err(np))
1330 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1331 frame_status);
553e2335
ED		 1332 dev->stats.rx_errors++;
1333 if (frame_status & 0x00100000)
1334 dev->stats.rx_length_errors++;
1335 if (frame_status & 0x00010000)
1336 dev->stats.rx_fifo_errors++;
1337 if (frame_status & 0x00060000)
1338 dev->stats.rx_frame_errors++;
1339 if (frame_status & 0x00080000)
1340 dev->stats.rx_crc_errors++;
1da177e4
LT		 1341 if (frame_status & 0x00100000) {
1342 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1343 " status %8.8x.\n",
1344 dev->name, frame_status);
1345 }
1346 } else {
1347 struct sk_buff *skb;
1348#ifndef final_version
1349 if (netif_msg_rx_status(np))
1350 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1351 ", bogus_cnt %d.\n",
1352 pkt_len, boguscnt);
1353#endif
1354 /* Check if the packet is long enough to accept without copying
1355 to a minimally-sized skbuff. */
8e95a202
JP		 1356 if (pkt_len < rx_copybreak &&
1357 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1da177e4 1358 skb_reserve(skb, 2); /* 16 byte align the IP header */
0c8a745f
DK		 1359 dma_sync_single_for_cpu(&np->pci_dev->dev,
1360 le32_to_cpu(desc->frag[0].addr),
1361 np->rx_buf_sz, DMA_FROM_DEVICE);
8c7b7faa 1362 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
0c8a745f
DK		 1363 dma_sync_single_for_device(&np->pci_dev->dev,
1364 le32_to_cpu(desc->frag[0].addr),
1365 np->rx_buf_sz, DMA_FROM_DEVICE);
1da177e4
LT		 1366 skb_put(skb, pkt_len);
1367 } else {
0c8a745f 1368 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1369 le32_to_cpu(desc->frag[0].addr),
0c8a745f 1370 np->rx_buf_sz, DMA_FROM_DEVICE);
1da177e4
LT		 1371 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1372 np->rx_skbuff[entry] = NULL;
1373 }
1374 skb->protocol = eth_type_trans(skb, dev);
1375 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1376 netif_rx(skb);
1da177e4
LT		 1377 }
1378 entry = (entry + 1) % RX_RING_SIZE;
1379 received++;
1380 }
1381 np->cur_rx = entry;
1382 refill_rx (dev);
1383 np->budget -= received;
1384 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1385 return;
1386
1387not_done:
1388 np->cur_rx = entry;
1389 refill_rx (dev);
1390 if (!received)
1391 received = 1;
1392 np->budget -= received;
1393 if (np->budget <= 0)
1394 np->budget = RX_BUDGET;
1395 tasklet_schedule(&np->rx_tasklet);
1da177e4
LT		 1396}
1397
1398static void refill_rx (struct net_device *dev)
1399{
1400 struct netdev_private *np = netdev_priv(dev);
1401 int entry;
1402 int cnt = 0;
1403
1404 /* Refill the Rx ring buffers. */
1405 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1406 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1407 struct sk_buff *skb;
1408 entry = np->dirty_rx % RX_RING_SIZE;
1409 if (np->rx_skbuff[entry] == NULL) {
1410 skb = dev_alloc_skb(np->rx_buf_sz);
1411 np->rx_skbuff[entry] = skb;
1412 if (skb == NULL)
1413 break; /* Better luck next round. */
1414 skb->dev = dev; /* Mark as being used by this device. */
1415 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1416 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
0c8a745f
DK		 1417 dma_map_single(&np->pci_dev->dev, skb->data,
1418 np->rx_buf_sz, DMA_FROM_DEVICE));
d91dc279
DK		 1419 if (dma_mapping_error(&np->pci_dev->dev,
1420 np->rx_ring[entry].frag[0].addr)) {
1421 dev_kfree_skb_irq(skb);
1422 np->rx_skbuff[entry] = NULL;
1423 break;
1424 }
1da177e4
LT		 1425 }
1426 /* Perhaps we need not reset this field. */
1427 np->rx_ring[entry].frag[0].length =
1428 cpu_to_le32(np->rx_buf_sz | LastFrag);
1429 np->rx_ring[entry].status = 0;
1430 cnt++;
1431 }
1da177e4
LT		 1432}
1433static void netdev_error(struct net_device *dev, int intr_status)
1434{
1435 struct netdev_private *np = netdev_priv(dev);
1436 void __iomem *ioaddr = np->base;
1437 u16 mii_ctl, mii_advertise, mii_lpa;
1438 int speed;
1439
1440 if (intr_status & LinkChange) {
50500155
DN		 1441 if (mdio_wait_link(dev, 10) == 0) {
1442 printk(KERN_INFO "%s: Link up\n", dev->name);
1443 if (np->an_enable) {
1444 mii_advertise = mdio_read(dev, np->phys[0],
1445 MII_ADVERTISE);
1446 mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
1447 mii_advertise &= mii_lpa;
1448 printk(KERN_INFO "%s: Link changed: ",
1449 dev->name);
1450 if (mii_advertise & ADVERTISE_100FULL) {
1451 np->speed = 100;
1452 printk("100Mbps, full duplex\n");
1453 } else if (mii_advertise & ADVERTISE_100HALF) {
1454 np->speed = 100;
1455 printk("100Mbps, half duplex\n");
1456 } else if (mii_advertise & ADVERTISE_10FULL) {
1457 np->speed = 10;
1458 printk("10Mbps, full duplex\n");
1459 } else if (mii_advertise & ADVERTISE_10HALF) {
1460 np->speed = 10;
1461 printk("10Mbps, half duplex\n");
1462 } else
1463 printk("\n");
1da177e4 1464
50500155
DN		 1465 } else {
1466 mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
1467 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1468 np->speed = speed;
1469 printk(KERN_INFO "%s: Link changed: %dMbps ,",
1470 dev->name, speed);
1471 printk("%s duplex.\n",
1472 (mii_ctl & BMCR_FULLDPLX) ?
1473 "full" : "half");
1474 }
1475 check_duplex(dev);
1476 if (np->flowctrl && np->mii_if.full_duplex) {
1477 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1478 ioaddr + MulticastFilter1+2);
1479 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1480 ioaddr + MACCtrl0);
1481 }
1482 netif_carrier_on(dev);
1da177e4 1483 } else {
50500155
DN		 1484 printk(KERN_INFO "%s: Link down\n", dev->name);
1485 netif_carrier_off(dev);
1da177e4
LT		 1486 }
1487 }
1488 if (intr_status & StatsMax) {
1489 get_stats(dev);
1490 }
1491 if (intr_status & IntrPCIErr) {
1492 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1493 dev->name, intr_status);
1494 /* We must do a global reset of DMA to continue. */
1495 }
1496}
1497
1498static struct net_device_stats *get_stats(struct net_device *dev)
1499{
1500 struct netdev_private *np = netdev_priv(dev);
1501 void __iomem *ioaddr = np->base;
7b738b55 1502 unsigned long flags;
725a4a46 1503 u8 late_coll, single_coll, mult_coll;
1da177e4 1504
7b738b55 1505 spin_lock_irqsave(&np->statlock, flags);
1da177e4 1506 /* The chip only need report frame silently dropped. */
553e2335
ED		 1507 dev->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1508 dev->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1509 dev->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
553e2335 1510 dev->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
725a4a46
DK		 1511
1512 mult_coll = ioread8(ioaddr + StatsMultiColl);
1513 np->xstats.tx_multiple_collisions += mult_coll;
1514 single_coll = ioread8(ioaddr + StatsOneColl);
1515 np->xstats.tx_single_collisions += single_coll;
1516 late_coll = ioread8(ioaddr + StatsLateColl);
1517 np->xstats.tx_late_collisions += late_coll;
1518 dev->stats.collisions += mult_coll
1519 + single_coll
1520 + late_coll;
1521
1522 np->xstats.tx_deferred += ioread8(ioaddr + StatsTxDefer);
1523 np->xstats.tx_deferred_excessive += ioread8(ioaddr + StatsTxXSDefer);
1524 np->xstats.tx_aborted += ioread8(ioaddr + StatsTxAbort);
1525 np->xstats.tx_bcasts += ioread8(ioaddr + StatsBcastTx);
1526 np->xstats.rx_bcasts += ioread8(ioaddr + StatsBcastRx);
1527 np->xstats.tx_mcasts += ioread8(ioaddr + StatsMcastTx);
1528 np->xstats.rx_mcasts += ioread8(ioaddr + StatsMcastRx);
1529
553e2335
ED		 1530 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1531 dev->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1532 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1533 dev->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1da177e4 1534
7b738b55
ED		 1535 spin_unlock_irqrestore(&np->statlock, flags);
1536
553e2335 1537 return &dev->stats;
1da177e4
LT		 1538}
1539
1540static void set_rx_mode(struct net_device *dev)
1541{
1542 struct netdev_private *np = netdev_priv(dev);
1543 void __iomem *ioaddr = np->base;
1544 u16 mc_filter[4]; /* Multicast hash filter */
1545 u32 rx_mode;
1546 int i;
1547
1548 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1da177e4
LT		 1549 memset(mc_filter, 0xff, sizeof(mc_filter));
1550 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
4cd24eaf 1551 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 1552 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 1553 /* Too many to match, or accept all multicasts. */
1554 memset(mc_filter, 0xff, sizeof(mc_filter));
1555 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4cd24eaf 1556 } else if (!netdev_mc_empty(dev)) {
22bedad3 1557 struct netdev_hw_addr *ha;
1da177e4
LT		 1558 int bit;
1559 int index;
1560 int crc;
1561 memset (mc_filter, 0, sizeof (mc_filter));
22bedad3
JP		 1562 netdev_for_each_mc_addr(ha, dev) {
1563 crc = ether_crc_le(ETH_ALEN, ha->addr);
1da177e4
LT		 1564 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1565 if (crc & 0x80000000) index |= 1 << bit;
1566 mc_filter[index/16] |= (1 << (index % 16));
1567 }
1568 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1569 } else {
1570 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1571 return;
1572 }
1573 if (np->mii_if.full_duplex && np->flowctrl)
1574 mc_filter[3] |= 0x0200;
1575
1576 for (i = 0; i < 4; i++)
1577 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1578 iowrite8(rx_mode, ioaddr + RxMode);
1579}
1580
1581static int __set_mac_addr(struct net_device *dev)
1582{
1583 struct netdev_private *np = netdev_priv(dev);
1584 u16 addr16;
1585
1586 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1587 iowrite16(addr16, np->base + StationAddr);
1588 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1589 iowrite16(addr16, np->base + StationAddr+2);
1590 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1591 iowrite16(addr16, np->base + StationAddr+4);
1592 return 0;
1593}
1594
725a4a46
DK		 1595static const struct {
1596 const char name[ETH_GSTRING_LEN];
1597} sundance_stats[] = {
1598 { "tx_multiple_collisions" },
1599 { "tx_single_collisions" },
1600 { "tx_late_collisions" },
1601 { "tx_deferred" },
1602 { "tx_deferred_excessive" },
1603 { "tx_aborted" },
1604 { "tx_bcasts" },
1605 { "rx_bcasts" },
1606 { "tx_mcasts" },
1607 { "rx_mcasts" },
1608};
1609
1da177e4
LT		 1610static int check_if_running(struct net_device *dev)
1611{
1612 if (!netif_running(dev))
1613 return -EINVAL;
1614 return 0;
1615}
1616
1617static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1618{
1619 struct netdev_private *np = netdev_priv(dev);
1620 strcpy(info->driver, DRV_NAME);
1621 strcpy(info->version, DRV_VERSION);
1622 strcpy(info->bus_info, pci_name(np->pci_dev));
1623}
1624
1625static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1626{
1627 struct netdev_private *np = netdev_priv(dev);
1628 spin_lock_irq(&np->lock);
1629 mii_ethtool_gset(&np->mii_if, ecmd);
1630 spin_unlock_irq(&np->lock);
1631 return 0;
1632}
1633
1634static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1635{
1636 struct netdev_private *np = netdev_priv(dev);
1637 int res;
1638 spin_lock_irq(&np->lock);
1639 res = mii_ethtool_sset(&np->mii_if, ecmd);
1640 spin_unlock_irq(&np->lock);
1641 return res;
1642}
1643
1644static int nway_reset(struct net_device *dev)
1645{
1646 struct netdev_private *np = netdev_priv(dev);
1647 return mii_nway_restart(&np->mii_if);
1648}
1649
1650static u32 get_link(struct net_device *dev)
1651{
1652 struct netdev_private *np = netdev_priv(dev);
1653 return mii_link_ok(&np->mii_if);
1654}
1655
1656static u32 get_msglevel(struct net_device *dev)
1657{
1658 struct netdev_private *np = netdev_priv(dev);
1659 return np->msg_enable;
1660}
1661
1662static void set_msglevel(struct net_device *dev, u32 val)
1663{
1664 struct netdev_private *np = netdev_priv(dev);
1665 np->msg_enable = val;
1666}
1667
725a4a46
DK		 1668static void get_strings(struct net_device *dev, u32 stringset,
1669 u8 *data)
1670{
1671 if (stringset == ETH_SS_STATS)
1672 memcpy(data, sundance_stats, sizeof(sundance_stats));
1673}
1674
1675static int get_sset_count(struct net_device *dev, int sset)
1676{
1677 switch (sset) {
1678 case ETH_SS_STATS:
1679 return ARRAY_SIZE(sundance_stats);
1680 default:
1681 return -EOPNOTSUPP;
1682 }
1683}
1684
1685static void get_ethtool_stats(struct net_device *dev,
1686 struct ethtool_stats *stats, u64 *data)
1687{
1688 struct netdev_private *np = netdev_priv(dev);
1689 int i = 0;
1690
1691 get_stats(dev);
1692 data[i++] = np->xstats.tx_multiple_collisions;
1693 data[i++] = np->xstats.tx_single_collisions;
1694 data[i++] = np->xstats.tx_late_collisions;
1695 data[i++] = np->xstats.tx_deferred;
1696 data[i++] = np->xstats.tx_deferred_excessive;
1697 data[i++] = np->xstats.tx_aborted;
1698 data[i++] = np->xstats.tx_bcasts;
1699 data[i++] = np->xstats.rx_bcasts;
1700 data[i++] = np->xstats.tx_mcasts;
1701 data[i++] = np->xstats.rx_mcasts;
1702}
1703
7282d491 1704static const struct ethtool_ops ethtool_ops = {
1da177e4
LT		 1705 .begin = check_if_running,
1706 .get_drvinfo = get_drvinfo,
1707 .get_settings = get_settings,
1708 .set_settings = set_settings,
1709 .nway_reset = nway_reset,
1710 .get_link = get_link,
1711 .get_msglevel = get_msglevel,
1712 .set_msglevel = set_msglevel,
725a4a46
DK		 1713 .get_strings = get_strings,
1714 .get_sset_count = get_sset_count,
1715 .get_ethtool_stats = get_ethtool_stats,
1da177e4
LT		 1716};
1717
1718static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1719{
1720 struct netdev_private *np = netdev_priv(dev);
1da177e4 1721 int rc;
1da177e4
LT		 1722
1723 if (!netif_running(dev))
1724 return -EINVAL;
1725
1726 spin_lock_irq(&np->lock);
1727 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1728 spin_unlock_irq(&np->lock);
1da177e4
LT		 1729
1730 return rc;
1731}
1732
1733static int netdev_close(struct net_device *dev)
1734{
1735 struct netdev_private *np = netdev_priv(dev);
1736 void __iomem *ioaddr = np->base;
1737 struct sk_buff *skb;
1738 int i;
1739
31f817e9
JH		 1740 /* Wait and kill tasklet */
1741 tasklet_kill(&np->rx_tasklet);
1742 tasklet_kill(&np->tx_tasklet);
1743 np->cur_tx = 0;
1744 np->dirty_tx = 0;
1745 np->cur_task = 0;
bca79eb7 1746 np->last_tx = NULL;
31f817e9 1747
1da177e4
LT		 1748 netif_stop_queue(dev);
1749
1750 if (netif_msg_ifdown(np)) {
1751 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1752 "Rx %4.4x Int %2.2x.\n",
1753 dev->name, ioread8(ioaddr + TxStatus),
1754 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1755 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1756 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1757 }
1758
1759 /* Disable interrupts by clearing the interrupt mask. */
1760 iowrite16(0x0000, ioaddr + IntrEnable);
1761
acd70c2b
JH		 1762 /* Disable Rx and Tx DMA for safely release resource */
1763 iowrite32(0x500, ioaddr + DMACtrl);
1764
1da177e4
LT		 1765 /* Stop the chip's Tx and Rx processes. */
1766 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1767
31f817e9
JH		 1768 for (i = 2000; i > 0; i--) {
1769 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1770 break;
1771 mdelay(1);
1772 }
1773
1774 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1775 ioaddr +ASICCtrl + 2);
1776
1777 for (i = 2000; i > 0; i--) {
1778 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1779 break;
1780 mdelay(1);
1781 }
1da177e4
LT		 1782
1783#ifdef __i386__
1784 if (netif_msg_hw(np)) {
ad361c98 1785 printk(KERN_DEBUG " Tx ring at %8.8x:\n",
1da177e4
LT		 1786 (int)(np->tx_ring_dma));
1787 for (i = 0; i < TX_RING_SIZE; i++)
ad361c98 1788 printk(KERN_DEBUG " #%d desc. %4.4x %8.8x %8.8x.\n",
1da177e4
LT		 1789 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1790 np->tx_ring[i].frag[0].length);
ad361c98 1791 printk(KERN_DEBUG " Rx ring %8.8x:\n",
1da177e4
LT		 1792 (int)(np->rx_ring_dma));
1793 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1794 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1795 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1796 np->rx_ring[i].frag[0].length);
1797 }
1798 }
1799#endif /* __i386__ debugging only */
1800
1801 free_irq(dev->irq, dev);
1802
1803 del_timer_sync(&np->timer);
1804
1805 /* Free all the skbuffs in the Rx queue. */
1806 for (i = 0; i < RX_RING_SIZE; i++) {
1807 np->rx_ring[i].status = 0;
1da177e4
LT		 1808 skb = np->rx_skbuff[i];
1809 if (skb) {
0c8a745f 1810 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1811 le32_to_cpu(np->rx_ring[i].frag[0].addr),
0c8a745f 1812 np->rx_buf_sz, DMA_FROM_DEVICE);
1da177e4
LT		 1813 dev_kfree_skb(skb);
1814 np->rx_skbuff[i] = NULL;
1815 }
14c9d9b0 1816 np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
1da177e4
LT		 1817 }
1818 for (i = 0; i < TX_RING_SIZE; i++) {
31f817e9 1819 np->tx_ring[i].next_desc = 0;
1da177e4
LT		 1820 skb = np->tx_skbuff[i];
1821 if (skb) {
0c8a745f 1822 dma_unmap_single(&np->pci_dev->dev,
14c9d9b0 1823 le32_to_cpu(np->tx_ring[i].frag[0].addr),
0c8a745f 1824 skb->len, DMA_TO_DEVICE);
1da177e4
LT		 1825 dev_kfree_skb(skb);
1826 np->tx_skbuff[i] = NULL;
1827 }
1828 }
1829
1830 return 0;
1831}
1832
1833static void __devexit sundance_remove1 (struct pci_dev *pdev)
1834{
1835 struct net_device *dev = pci_get_drvdata(pdev);
1836
1837 if (dev) {
0c8a745f
DK		 1838 struct netdev_private *np = netdev_priv(dev);
1839 unregister_netdev(dev);
1840 dma_free_coherent(&pdev->dev, RX_TOTAL_SIZE,
1841 np->rx_ring, np->rx_ring_dma);
1842 dma_free_coherent(&pdev->dev, TX_TOTAL_SIZE,
1843 np->tx_ring, np->tx_ring_dma);
1844 pci_iounmap(pdev, np->base);
1845 pci_release_regions(pdev);
1846 free_netdev(dev);
1847 pci_set_drvdata(pdev, NULL);
1da177e4
LT		 1848 }
1849}
1850
61a21455
DK		 1851#ifdef CONFIG_PM
1852
1853static int sundance_suspend(struct pci_dev *pci_dev, pm_message_t state)
1854{
1855 struct net_device *dev = pci_get_drvdata(pci_dev);
1856
1857 if (!netif_running(dev))
1858 return 0;
1859
1860 netdev_close(dev);
1861 netif_device_detach(dev);
1862
1863 pci_save_state(pci_dev);
1864 pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
1865
1866 return 0;
1867}
1868
1869static int sundance_resume(struct pci_dev *pci_dev)
1870{
1871 struct net_device *dev = pci_get_drvdata(pci_dev);
1872 int err = 0;
1873
1874 if (!netif_running(dev))
1875 return 0;
1876
1877 pci_set_power_state(pci_dev, PCI_D0);
1878 pci_restore_state(pci_dev);
1879
1880 err = netdev_open(dev);
1881 if (err) {
1882 printk(KERN_ERR "%s: Can't resume interface!\n",
1883 dev->name);
1884 goto out;
1885 }
1886
1887 netif_device_attach(dev);
1888
1889out:
1890 return err;
1891}
1892
1893#endif /* CONFIG_PM */
1894
1da177e4
LT		 1895static struct pci_driver sundance_driver = {
1896 .name = DRV_NAME,
1897 .id_table = sundance_pci_tbl,
1898 .probe = sundance_probe1,
1899 .remove = __devexit_p(sundance_remove1),
61a21455
DK		 1900#ifdef CONFIG_PM
1901 .suspend = sundance_suspend,
1902 .resume = sundance_resume,
1903#endif /* CONFIG_PM */
1da177e4
LT		 1904};
1905
1906static int __init sundance_init(void)
1907{
1908/* when a module, this is printed whether or not devices are found in probe */
1909#ifdef MODULE
1910 printk(version);
1911#endif
29917620 1912 return pci_register_driver(&sundance_driver);
1da177e4
LT		 1913}
1914
1915static void __exit sundance_exit(void)
1916{
1917 pci_unregister_driver(&sundance_driver);
1918}
1919
1920module_init(sundance_init);
1921module_exit(sundance_exit);
1922
1923
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