[net-next-2.6.git] / drivers / net / stmmac / dwmac100_core.c

/*******************************************************************************
  This is the driver for the MAC 10/100 on-chip Ethernet controller
  currently tested on all the ST boards based on STb7109 and stx7200 SoCs.

  DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
  this code.

  This only implements the mac core functions for this chip.

  Copyright (C) 2007-2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#include <linux/crc32.h>
#include "dwmac100.h"

static void dwmac100_core_init(void __iomem *ioaddr)
{
	u32 value = readl(ioaddr + MAC_CONTROL);

	writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL);

#ifdef STMMAC_VLAN_TAG_USED
	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
#endif
}

static int dwmac100_rx_coe_supported(void __iomem *ioaddr)
{
	return 0;
}

static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
{
	pr_info("\t----------------------------------------------\n"
		"\t  DWMAC 100 CSR (base addr = 0x%p)\n"
		"\t----------------------------------------------\n",
		ioaddr);
	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
		readl(ioaddr + MAC_CONTROL));
	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
		readl(ioaddr + MAC_ADDR_HIGH));
	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
		readl(ioaddr + MAC_ADDR_LOW));
	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
		MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
		MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
		MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
		readl(ioaddr + MAC_VLAN1));
	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
		readl(ioaddr + MAC_VLAN2));
	pr_info("\n\tMAC management counter registers\n");
	pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
		MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
	pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
		MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
	pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
		MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
	pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
		MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
	pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
		MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
}

static void dwmac100_irq_status(void __iomem *ioaddr)
{
	return;
}

static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
				   unsigned int reg_n)
{
	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr,
				   unsigned int reg_n)
{
	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
}

static void dwmac100_set_filter(struct net_device *dev)
{
	void __iomem *ioaddr = (void __iomem *) dev->base_addr;
	u32 value = readl(ioaddr + MAC_CONTROL);

	if (dev->flags & IFF_PROMISC) {
		value |= MAC_CONTROL_PR;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
			   MAC_CONTROL_HP);
	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
		   || (dev->flags & IFF_ALLMULTI)) {
		value |= MAC_CONTROL_PM;
		value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
		writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
		writel(0xffffffff, ioaddr + MAC_HASH_LOW);
	} else if (netdev_mc_empty(dev)) {	/* no multicast */
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
			   MAC_CONTROL_HO | MAC_CONTROL_HP);
	} else {
		u32 mc_filter[2];
		struct netdev_hw_addr *ha;

		/* Perfect filter mode for physical address and Hash
		   filter for multicast */
		value |= MAC_CONTROL_HP;
		value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
			   MAC_CONTROL_IF | MAC_CONTROL_HO);

		memset(mc_filter, 0, sizeof(mc_filter));
		netdev_for_each_mc_addr(ha, dev) {
			/* The upper 6 bits of the calculated CRC are used to
			 * index the contens of the hash table */
			int bit_nr =
			    ether_crc(ETH_ALEN, ha->addr) >> 26;
			/* The most significant bit determines the register to
			 * use (H/L) while the other 5 bits determine the bit
			 * within the register. */
			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
		}
		writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
		writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	}

	writel(value, ioaddr + MAC_CONTROL);

	CHIP_DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
	    "HI 0x%08x, LO 0x%08x\n",
	    __func__, readl(ioaddr + MAC_CONTROL),
	    readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
}

static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
			       unsigned int fc, unsigned int pause_time)
{
	unsigned int flow = MAC_FLOW_CTRL_ENABLE;

	if (duplex)
		flow |= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	writel(flow, ioaddr + MAC_FLOW_CTRL);
}

/* No PMT module supported for this Ethernet Controller.
 * Tested on ST platforms only.
 */
static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
{
	return;
}

struct stmmac_ops dwmac100_ops = {
	.core_init = dwmac100_core_init,
	.rx_coe = dwmac100_rx_coe_supported,
	.dump_regs = dwmac100_dump_mac_regs,
	.host_irq_status = dwmac100_irq_status,
	.set_filter = dwmac100_set_filter,
	.flow_ctrl = dwmac100_flow_ctrl,
	.pmt = dwmac100_pmt,
	.set_umac_addr = dwmac100_set_umac_addr,
	.get_umac_addr = dwmac100_get_umac_addr,
};

struct mac_device_info *dwmac100_setup(void __iomem *ioaddr)
{
	struct mac_device_info *mac;

	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
	if (!mac)
		return NULL;

	pr_info("\tDWMAC100\n");

	mac->mac = &dwmac100_ops;
	mac->dma = &dwmac100_dma_ops;

	mac->link.port = MAC_CONTROL_PS;
	mac->link.duplex = MAC_CONTROL_F;
	mac->link.speed = 0;
	mac->mii.addr = MAC_MII_ADDR;
	mac->mii.data = MAC_MII_DATA;

	return mac;
}
Commit	Line	Data
3c32be63 GC	1	/*******************************************************************************
	2	This is the driver for the MAC 10/100 on-chip Ethernet controller
	3	currently tested on all the ST boards based on STb7109 and stx7200 SoCs.
	4
	5	DWC Ether MAC 10/100 Universal version 4.0 has been used for developing
	6	this code.
	7
	8	This only implements the mac core functions for this chip.
	9
	10	Copyright (C) 2007-2009 STMicroelectronics Ltd
	11
	12	This program is free software; you can redistribute it and/or modify it
	13	under the terms and conditions of the GNU General Public License,
	14	version 2, as published by the Free Software Foundation.
	15
	16	This program is distributed in the hope it will be useful, but WITHOUT
	17	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	18	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	19	more details.
	20
	21	You should have received a copy of the GNU General Public License along with
	22	this program; if not, write to the Free Software Foundation, Inc.,
	23	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	24
	25	The full GNU General Public License is included in this distribution in
	26	the file called "COPYING".
	27
	28	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	29	*******************************************************************************/
	30
	31	#include <linux/crc32.h>
	32	#include "dwmac100.h"
	33
ad01b7d4	34	static void dwmac100_core_init(void __iomem *ioaddr)
3c32be63 GC	35	{
	36	u32 value = readl(ioaddr + MAC_CONTROL);
	37
	38	writel((value \| MAC_CORE_INIT), ioaddr + MAC_CONTROL);
	39
	40	#ifdef STMMAC_VLAN_TAG_USED
	41	writel(ETH_P_8021Q, ioaddr + MAC_VLAN1);
	42	#endif
3c32be63 GC	43	}
3c32be63 GC	44
ebbb293f GC	45	static int dwmac100_rx_coe_supported(void __iomem *ioaddr)
	46	{
	47	return 0;
	48	}
	49
ad01b7d4	50	static void dwmac100_dump_mac_regs(void __iomem *ioaddr)
3c32be63 GC	51	{
3c32be63 GC	52	pr_info("\t----------------------------------------------\n"
74af4c7d	53	"\t DWMAC 100 CSR (base addr = 0x%p)\n"
3c32be63	54	"\t----------------------------------------------\n",
74af4c7d	55	ioaddr);
3c32be63 GC	56	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
	57	readl(ioaddr + MAC_CONTROL));
	58	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
	59	readl(ioaddr + MAC_ADDR_HIGH));
	60	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
	61	readl(ioaddr + MAC_ADDR_LOW));
	62	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
	63	MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
	64	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
	65	MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
	66	pr_info("\tflow control (offset 0x%x): 0x%08x\n",
	67	MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
	68	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
	69	readl(ioaddr + MAC_VLAN1));
	70	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
	71	readl(ioaddr + MAC_VLAN2));
	72	pr_info("\n\tMAC management counter registers\n");
	73	pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
	74	MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
	75	pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
	76	MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
	77	pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
	78	MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
	79	pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
	80	MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
	81	pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
	82	MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
3c32be63 GC	83	}
3c32be63 GC	84
ad01b7d4	85	static void dwmac100_irq_status(void __iomem *ioaddr)
3c32be63 GC	86	{
	87	return;
	88	}
	89
ad01b7d4	90	static void dwmac100_set_umac_addr(void __iomem ioaddr, unsigned char addr,
3c32be63 GC	91	unsigned int reg_n)
	92	{
	93	stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	94	}
	95
ad01b7d4	96	static void dwmac100_get_umac_addr(void __iomem ioaddr, unsigned char addr,
3c32be63 GC	97	unsigned int reg_n)
	98	{
	99	stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
	100	}
	101
	102	static void dwmac100_set_filter(struct net_device *dev)
	103	{
ad01b7d4	104	void __iomem ioaddr = (void __iomem ) dev->base_addr;
3c32be63 GC	105	u32 value = readl(ioaddr + MAC_CONTROL);
	106
	107	if (dev->flags & IFF_PROMISC) {
	108	value \|= MAC_CONTROL_PR;
	109	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_IF \| MAC_CONTROL_HO \|
	110	MAC_CONTROL_HP);
	111	} else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
	112	\|\| (dev->flags & IFF_ALLMULTI)) {
	113	value \|= MAC_CONTROL_PM;
	114	value &= ~(MAC_CONTROL_PR \| MAC_CONTROL_IF \| MAC_CONTROL_HO);
	115	writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
	116	writel(0xffffffff, ioaddr + MAC_HASH_LOW);
	117	} else if (netdev_mc_empty(dev)) { /* no multicast */
	118	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \| MAC_CONTROL_IF \|
	119	MAC_CONTROL_HO \| MAC_CONTROL_HP);
	120	} else {
	121	u32 mc_filter[2];
	122	struct netdev_hw_addr *ha;
	123
	124	/* Perfect filter mode for physical address and Hash
	125	filter for multicast */
	126	value \|= MAC_CONTROL_HP;
	127	value &= ~(MAC_CONTROL_PM \| MAC_CONTROL_PR \|
	128	MAC_CONTROL_IF \| MAC_CONTROL_HO);
	129
	130	memset(mc_filter, 0, sizeof(mc_filter));
	131	netdev_for_each_mc_addr(ha, dev) {
	132	/* The upper 6 bits of the calculated CRC are used to
	133	* index the contens of the hash table */
	134	int bit_nr =
	135	ether_crc(ETH_ALEN, ha->addr) >> 26;
	136	/* The most significant bit determines the register to
	137	* use (H/L) while the other 5 bits determine the bit
	138	* within the register. */
	139	mc_filter[bit_nr >> 5] \|= 1 << (bit_nr & 31);
	140	}
	141	writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
	142	writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
	143	}
	144
	145	writel(value, ioaddr + MAC_CONTROL);
	146
56b106ae	147	CHIP_DBG(KERN_INFO "%s: CTRL reg: 0x%08x Hash regs: "
3c32be63 GC	148	"HI 0x%08x, LO 0x%08x\n",
	149	__func__, readl(ioaddr + MAC_CONTROL),
	150	readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW));
3c32be63 GC	151	}
3c32be63 GC	152
ad01b7d4	153	static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex,
3c32be63 GC	154	unsigned int fc, unsigned int pause_time)
	155	{
	156	unsigned int flow = MAC_FLOW_CTRL_ENABLE;
	157
	158	if (duplex)
	159	flow \|= (pause_time << MAC_FLOW_CTRL_PT_SHIFT);
	160	writel(flow, ioaddr + MAC_FLOW_CTRL);
3c32be63 GC	161	}
	162
	163	/* No PMT module supported for this Ethernet Controller.
	164	* Tested on ST platforms only.
	165	*/
ad01b7d4	166	static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode)
3c32be63 GC	167	{
	168	return;
	169	}
	170
	171	struct stmmac_ops dwmac100_ops = {
	172	.core_init = dwmac100_core_init,
ebbb293f	173	.rx_coe = dwmac100_rx_coe_supported,
3c32be63 GC	174	.dump_regs = dwmac100_dump_mac_regs,
	175	.host_irq_status = dwmac100_irq_status,
	176	.set_filter = dwmac100_set_filter,
	177	.flow_ctrl = dwmac100_flow_ctrl,
	178	.pmt = dwmac100_pmt,
	179	.set_umac_addr = dwmac100_set_umac_addr,
	180	.get_umac_addr = dwmac100_get_umac_addr,
	181	};
	182
ad01b7d4	183	struct mac_device_info dwmac100_setup(void __iomem ioaddr)
3c32be63 GC	184	{
	185	struct mac_device_info *mac;
	186
	187	mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
1ff21906 DC	188	if (!mac)
1ff21906 DC	189	return NULL;
3c32be63 GC	190
	191	pr_info("\tDWMAC100\n");
	192
	193	mac->mac = &dwmac100_ops;
3c32be63 GC	194	mac->dma = &dwmac100_dma_ops;
3c32be63 GC	195
3c32be63 GC	196	mac->link.port = MAC_CONTROL_PS;
	197	mac->link.duplex = MAC_CONTROL_F;
	198	mac->link.speed = 0;
	199	mac->mii.addr = MAC_MII_ADDR;
	200	mac->mii.data = MAC_MII_DATA;
	201
	202	return mac;
	203	}