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sky2: size status ring based on Tx/Rx ring
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
5a0e3ad6 36#include <linux/slab.h>
c9bdd4b5 37#include <net/ip.h>
cd28ab6a
SH		 38#include <linux/tcp.h>
39#include <linux/in.h>
40#include <linux/delay.h>
91c86df5 41#include <linux/workqueue.h>
d1f13708 42#include <linux/if_vlan.h>
d70cd51a 43#include <linux/prefetch.h>
3cf26753 44#include <linux/debugfs.h>
ef743d33 45#include <linux/mii.h>
cd28ab6a
SH		 46
47#include <asm/irq.h>
48
d1f13708
SH		 49#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50#define SKY2_VLAN_TAG_USED 1
51#endif
52
cd28ab6a
SH		 53#include "sky2.h"
54
55#define DRV_NAME "sky2"
cfc0861b 56#define DRV_VERSION "1.27"
cd28ab6a
SH		 57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 68
ee5f68fe 69/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 72#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 73#define TX_MAX_PENDING 1024
ee5f68fe 74#define TX_DEF_PENDING 127
cd28ab6a 75
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
e6cac9ba 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 143 { 0 }
144};
793b883e 145
cd28ab6a
SH		 146MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148/* Avoid conditionals by using array */
149static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 151static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 152
d1b139c0
SH		 153static void sky2_set_multicast(struct net_device *dev);
154
af043aa5 155/* Access to PHY via serial interconnect */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
af043aa5
SH		 171
172 udelay(10);
cd28ab6a 173 }
ef743d33 174
af043aa5 175 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 176 return -ETIMEDOUT;
af043aa5
SH		 177
178io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
cd28ab6a
SH		 181}
182
ef743d33 183static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 184{
185 int i;
186
793b883e 187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
af043aa5 200 udelay(10);
cd28ab6a
SH		 201 }
202
af043aa5 203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 204 return -ETIMEDOUT;
af043aa5
SH		 205io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
ef743d33
SH		 208}
209
af043aa5 210static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 211{
212 u16 v;
af043aa5 213 __gm_phy_read(hw, port, reg, &v);
ef743d33 214 return v;
cd28ab6a
SH		 215}
216
5afa0a9c 217
ae306cca
SH		 218static void sky2_power_on(struct sky2_hw *hw)
219{
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 223
ae306cca
SH		 224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 226
4b7c47aa 227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 235
ea76e635 236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 237 u32 reg;
5afa0a9c 238
b32f40c4 239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 240
b32f40c4 241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 250
b32f40c4 251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 252
5f8ae5c5 253 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
254
8f70920f
SH		 255 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
256 reg = sky2_read32(hw, B2_GP_IO);
257 reg |= GLB_GPIO_STAT_RACE_DIS;
258 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 259
260 sky2_read32(hw, B2_GP_IO);
5afa0a9c 261 }
10547ae2
SH		 262
263 /* Turn on "driver loaded" LED */
264 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
4b7c47aa 269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
c23ddf8f
SH		 278 /* switch power to VAUX if supported and PME from D3cold */
279 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
280 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 284
285 /* turn off "driver loaded LED" */
286 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 287}
288
d3bcfbeb 289static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 290{
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 295
cd28ab6a
SH		 296 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
297 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300
301 reg = gma_read16(hw, port, GM_RX_CTRL);
302 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
303 gma_write16(hw, port, GM_RX_CTRL, reg);
304}
305
16ad91e1
SH		 306/* flow control to advertise bits */
307static const u16 copper_fc_adv[] = {
308 [FC_NONE] = 0,
309 [FC_TX] = PHY_M_AN_ASP,
310 [FC_RX] = PHY_M_AN_PC,
311 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312};
313
314/* flow control to advertise bits when using 1000BaseX */
315static const u16 fiber_fc_adv[] = {
df3fe1f3 316 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 317 [FC_TX] = PHY_M_P_ASYM_MD_X,
318 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 319 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 320};
321
322/* flow control to GMA disable bits */
323static const u16 gm_fc_disable[] = {
324 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
325 [FC_TX] = GM_GPCR_FC_RX_DIS,
326 [FC_RX] = GM_GPCR_FC_TX_DIS,
327 [FC_BOTH] = 0,
328};
329
330
cd28ab6a
SH		 331static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332{
333 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 334 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 335
0ea065e5 336 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 337 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 338 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339
340 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 341 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 342 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343
53419c68 344 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 345 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 346 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 347 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 else
53419c68
SH		 349 /* set master & slave downshift counter to 1x */
350 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 351
352 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 356 if (sky2_is_copper(hw)) {
05745c4a 357 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 358 /* enable automatic crossover */
359 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 360
361 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
362 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 u16 spec;
364
365 /* Enable Class A driver for FE+ A0 */
366 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
367 spec |= PHY_M_FESC_SEL_CL_A;
368 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 }
cd28ab6a
SH		 370 } else {
371 /* disable energy detect */
372 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373
374 /* enable automatic crossover */
375 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376
53419c68 377 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 378 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
379 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 380 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 381 ctrl &= ~PHY_M_PC_DSC_MSK;
382 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 }
384 }
cd28ab6a
SH		 385 } else {
386 /* workaround for deviation #4.88 (CRC errors) */
387 /* disable Automatic Crossover */
388
389 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 390 }
cd28ab6a 391
b89165f2
SH		 392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393
394 /* special setup for PHY 88E1112 Fiber */
ea76e635 395 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 397
b89165f2
SH		 398 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
399 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl &= ~PHY_M_MAC_MD_MSK;
402 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404
405 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 406 /* select page 1 to access Fiber registers */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 408
409 /* for SFP-module set SIGDET polarity to low */
410 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
411 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 413 }
b89165f2
SH		 414
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 416 }
417
7800fddc 418 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 419 ct1000 = 0;
420 adv = PHY_AN_CSMA;
2eaba1a2 421 reg = 0;
cd28ab6a 422
0ea065e5 423 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 424 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 425 if (sky2->advertising & ADVERTISED_1000baseT_Full)
426 ct1000 |= PHY_M_1000C_AFD;
427 if (sky2->advertising & ADVERTISED_1000baseT_Half)
428 ct1000 |= PHY_M_1000C_AHD;
429 if (sky2->advertising & ADVERTISED_100baseT_Full)
430 adv |= PHY_M_AN_100_FD;
431 if (sky2->advertising & ADVERTISED_100baseT_Half)
432 adv |= PHY_M_AN_100_HD;
433 if (sky2->advertising & ADVERTISED_10baseT_Full)
434 adv |= PHY_M_AN_10_FD;
435 if (sky2->advertising & ADVERTISED_10baseT_Half)
436 adv |= PHY_M_AN_10_HD;
709c6e7b 437
b89165f2
SH		 438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
0ea065e5
SH		 451 /* Disable auto update for duplex flow control and duplex */
452 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
0ea065e5 470 }
2eaba1a2 471
0ea065e5
SH		 472 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
473 if (sky2_is_copper(hw))
474 adv |= copper_fc_adv[sky2->flow_mode];
475 else
476 adv |= fiber_fc_adv[sky2->flow_mode];
477 } else {
478 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 479 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 480
481 /* Forward pause packets to GMAC? */
16ad91e1 482 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 else
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 486 }
487
2eaba1a2
SH		 488 gma_write16(hw, port, GM_GP_CTRL, reg);
489
05745c4a 490 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 491 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492
493 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
494 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495
496 /* Setup Phy LED's */
497 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
498 ledover = 0;
499
500 switch (hw->chip_id) {
501 case CHIP_ID_YUKON_FE:
502 /* on 88E3082 these bits are at 11..9 (shifted left) */
503 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504
505 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506
507 /* delete ACT LED control bits */
508 ctrl &= ~PHY_M_FELP_LED1_MSK;
509 /* change ACT LED control to blink mode */
510 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
511 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
512 break;
513
05745c4a
SH		 514 case CHIP_ID_YUKON_FE_P:
515 /* Enable Link Partner Next Page */
516 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
517 ctrl |= PHY_M_PC_ENA_LIP_NP;
518
519 /* disable Energy Detect and enable scrambler */
520 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522
523 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
524 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
525 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
526 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527
528 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
529 break;
530
cd28ab6a 531 case CHIP_ID_YUKON_XL:
793b883e 532 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 533
534 /* select page 3 to access LED control register */
535 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536
537 /* set LED Function Control register */
ed6d32c7
SH		 538 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
539 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
540 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
541 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
542 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 543
544 /* set Polarity Control register */
545 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 546 (PHY_M_POLC_LS1_P_MIX(4) |
547 PHY_M_POLC_IS0_P_MIX(4) |
548 PHY_M_POLC_LOS_CTRL(2) |
549 PHY_M_POLC_INIT_CTRL(2) |
550 PHY_M_POLC_STA1_CTRL(2) |
551 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 552
553 /* restore page register */
793b883e 554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 555 break;
93745494 556
ed6d32c7 557 case CHIP_ID_YUKON_EC_U:
93745494 558 case CHIP_ID_YUKON_EX:
ed4d4161 559 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 560 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561
562 /* select page 3 to access LED control register */
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564
565 /* set LED Function Control register */
566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
567 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
568 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
569 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
570 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571
572 /* set Blink Rate in LED Timer Control Register */
573 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
574 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
575 /* restore page register */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 break;
cd28ab6a
SH		 578
579 default:
580 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
581 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 582
cd28ab6a 583 /* turn off the Rx LED (LED_RX) */
a84d0a3d 584 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 585 }
586
0ce8b98d 587 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 588 /* apply fixes in PHY AFE */
ed6d32c7
SH		 589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590
977bdf06 591 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 592 gm_phy_write(hw, port, 0x18, 0xaa99);
593 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 594
0ce8b98d
SH		 595 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
596 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xa204);
598 gm_phy_write(hw, port, 0x17, 0x2002);
599 }
977bdf06
SH		 600
601 /* set page register to 0 */
9467a8fc 602 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 603 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
604 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
605 /* apply workaround for integrated resistors calibration */
606 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
607 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 608 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
609 /* apply fixes in PHY AFE */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611
612 /* apply RDAC termination workaround */
613 gm_phy_write(hw, port, 24, 0x2800);
614 gm_phy_write(hw, port, 23, 0x2001);
615
616 /* set page register back to 0 */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 618 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
619 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 620 /* no effect on Yukon-XL */
977bdf06 621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 622
8e95a202
JP		 623 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
624 sky2->speed == SPEED_100) {
977bdf06 625 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 627 }
cd28ab6a 628
977bdf06
SH		 629 if (ledover)
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
631
632 }
2eaba1a2 633
d571b694 634 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 635 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 else
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
639}
640
b96936da
SH		 641static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
642static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643
644static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 645{
646 u32 reg1;
d3bcfbeb 647
a40ccc68 648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 650 reg1 &= ~phy_power[port];
d3bcfbeb 651
4b7c47aa 652 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 653 reg1 |= coma_mode[port];
654
b32f40c4 655 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 657 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 658
659 if (hw->chip_id == CHIP_ID_YUKON_FE)
660 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
661 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 663}
167f53d0 664
b96936da
SH		 665static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
666{
667 u32 reg1;
db99b988
SH		 668 u16 ctrl;
669
670 /* release GPHY Control reset */
671 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
672
673 /* release GMAC reset */
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675
676 if (hw->flags & SKY2_HW_NEWER_PHY) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
679
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* allow GMII Power Down */
682 ctrl &= ~PHY_M_MAC_GMIF_PUP;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
684
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
687 }
688
689 /* setup General Purpose Control Register */
690 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 691 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
692 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
693 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 694
695 if (hw->chip_id != CHIP_ID_YUKON_EC) {
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 697 /* select page 2 to access MAC control register */
698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 699
e484d5f5 700 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 701 /* enable Power Down */
702 ctrl |= PHY_M_PC_POW_D_ENA;
703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 704
705 /* set page register back to 0 */
706 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 707 }
708
709 /* set IEEE compatible Power Down Mode (dev. #4.99) */
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
711 }
b96936da 712
a40ccc68 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 715 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 718}
719
1b537565
SH		 720/* Force a renegotiation */
721static void sky2_phy_reinit(struct sky2_port *sky2)
722{
e07b1aa8 723 spin_lock_bh(&sky2->phy_lock);
1b537565 724 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 725 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 726}
727
e3173832
SH		 728/* Put device in state to listen for Wake On Lan */
729static void sky2_wol_init(struct sky2_port *sky2)
730{
731 struct sky2_hw *hw = sky2->hw;
732 unsigned port = sky2->port;
733 enum flow_control save_mode;
734 u16 ctrl;
e3173832
SH		 735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
b96936da
SH		 751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
a419aef8 780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
5f8ae5c5 785 /* Disable PiG firmware */
786 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
787
e3173832
SH		 788 /* block receiver */
789 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 790}
791
69161611
SH		 792static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
793{
05745c4a
SH		 794 struct net_device *dev = hw->dev[port];
795
ed4d4161
SH		 796 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
797 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 798 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 799 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
801 } else if (dev->mtu > ETH_DATA_LEN) {
802 /* set Tx GMAC FIFO Almost Empty Threshold */
803 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
804 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 805
44dde56d 806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
807 } else
808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 809}
810
cd28ab6a
SH		 811static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
812{
813 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
814 u16 reg;
25cccecc 815 u32 rx_reg;
cd28ab6a
SH		 816 int i;
817 const u8 *addr = hw->dev[port]->dev_addr;
818
f350339c
SH		 819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 821
822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
823
4b7c47aa 824 if (hw->chip_id == CHIP_ID_YUKON_XL &&
825 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
826 port == 1) {
cd28ab6a
SH		 827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 do {
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
833 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
834 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
835 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
836 }
837
793b883e 838 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 839
2eaba1a2
SH		 840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842
e07b1aa8 843 spin_lock_bh(&sky2->phy_lock);
b96936da 844 sky2_phy_power_up(hw, port);
cd28ab6a 845 sky2_phy_init(hw, port);
e07b1aa8 846 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 847
848 /* MIB clear */
849 reg = gma_read16(hw, port, GM_PHY_ADDR);
850 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851
43f2f104
SH		 852 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
853 gma_read16(hw, port, i);
cd28ab6a
SH		 854 gma_write16(hw, port, GM_PHY_ADDR, reg);
855
856 /* transmit control */
857 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw, port, GM_RX_CTRL,
793b883e 861 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 862
863 /* transmit flow control */
864 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865
866 /* transmit parameter */
867 gma_write16(hw, port, GM_TX_PARAM,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872
873 /* serial mode register */
874 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 875 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 876
6b1a3aef 877 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 878 reg |= GM_SMOD_JUMBO_ENA;
879
c1cd0a85 880 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
881 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
882 reg |= GM_NEW_FLOW_CTRL;
883
cd28ab6a
SH		 884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885
cd28ab6a
SH		 886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888
793b883e
SH		 889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891
892 /* ignore counter overflows */
cd28ab6a
SH		 893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 902 rx_reg |= GMF_RX_OVER_ON;
69161611 903
25cccecc 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 905
798fdd07
SH		 906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 } else {
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
912 }
cd28ab6a 913
8df9a876 914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 reg = 0x178;
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 921
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 925
e0c28116 926 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 928 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 929 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
930 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 931 reg = 1568 / 8;
932 else
933 reg = 1024 / 8;
934 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
935 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 936
69161611 937 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 938 }
939
e970d1f8
SH		 940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
942 /* disable dynamic watermark */
943 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
944 reg &= ~TX_DYN_WM_ENA;
945 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
946 }
cd28ab6a
SH		 947}
948
67712901
SH		 949/* Assign Ram Buffer allocation to queue */
950static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 951{
67712901
SH		 952 u32 end;
953
954 /* convert from K bytes to qwords used for hw register */
955 start *= 1024/8;
956 space *= 1024/8;
957 end = start + space - 1;
793b883e 958
cd28ab6a
SH		 959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
960 sky2_write32(hw, RB_ADDR(q, RB_START), start);
961 sky2_write32(hw, RB_ADDR(q, RB_END), end);
962 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
963 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
964
965 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 966 u32 tp = space - space/4;
793b883e 967
1c28f6ba
SH		 968 /* On receive queue's set the thresholds
969 * give receiver priority when > 3/4 full
970 * send pause when down to 2K
971 */
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 974
1c28f6ba
SH		 975 tp = space - 2048/8;
976 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
977 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 978 } else {
979 /* Enable store & forward on Tx queue's because
980 * Tx FIFO is only 1K on Yukon
981 */
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
983 }
984
985 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 986 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 987}
988
cd28ab6a 989/* Setup Bus Memory Interface */
af4ed7e6 990static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 991{
992 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 995 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 996}
997
cd28ab6a
SH		 998/* Setup prefetch unit registers. This is the interface between
999 * hardware and driver list elements
1000 */
8cc048e3 1001static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1002 dma_addr_t addr, u32 last)
cd28ab6a 1003{
cd28ab6a
SH		 1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1008 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1010
1011 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1012}
1013
9b289c33 1014static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1015{
9b289c33 1016 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1017
ee5f68fe 1018 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1019 le->ctrl = 0;
793b883e
SH		 1020 return le;
1021}
cd28ab6a 1022
88f5f0ca
SH		 1023static void tx_init(struct sky2_port *sky2)
1024{
1025 struct sky2_tx_le *le;
1026
1027 sky2->tx_prod = sky2->tx_cons = 0;
1028 sky2->tx_tcpsum = 0;
1029 sky2->tx_last_mss = 0;
1030
9b289c33 1031 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1032 le->addr = 0;
1033 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1034 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1035}
1036
290d4de5
SH		 1037/* Update chip's next pointer */
1038static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1039{
50432cb5 1040 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1041 wmb();
50432cb5
SH		 1042 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1043
1044 /* Synchronize I/O on since next processor may write to tail */
1045 mmiowb();
cd28ab6a
SH		 1046}
1047
793b883e 1048
cd28ab6a
SH		 1049static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1050{
1051 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1052 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1053 le->ctrl = 0;
cd28ab6a
SH		 1054 return le;
1055}
1056
39ef110b
MM		 1057static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1058{
1059 unsigned size;
1060
1061 /* Space needed for frame data + headers rounded up */
1062 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1063
1064 /* Stopping point for hardware truncation */
1065 return (size - 8) / sizeof(u32);
1066}
1067
1068static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1069{
1070 struct rx_ring_info *re;
1071 unsigned size;
1072
1073 /* Space needed for frame data + headers rounded up */
1074 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1075
1076 sky2->rx_nfrags = size >> PAGE_SHIFT;
1077 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1078
1079 /* Compute residue after pages */
1080 size -= sky2->rx_nfrags << PAGE_SHIFT;
1081
1082 /* Optimize to handle small packets and headers */
1083 if (size < copybreak)
1084 size = copybreak;
1085 if (size < ETH_HLEN)
1086 size = ETH_HLEN;
1087
1088 return size;
1089}
1090
14d0263f
SH		 1091/* Build description to hardware for one receive segment */
1092static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1093 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1094{
1095 struct sky2_rx_le *le;
1096
86c6887e 1097 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1098 le = sky2_next_rx(sky2);
86c6887e 1099 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1100 le->opcode = OP_ADDR64 | HW_OWNER;
1101 }
793b883e 1102
cd28ab6a 1103 le = sky2_next_rx(sky2);
d6e74b6b 1104 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1105 le->length = cpu_to_le16(len);
14d0263f 1106 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1107}
1108
14d0263f
SH		 1109/* Build description to hardware for one possibly fragmented skb */
1110static void sky2_rx_submit(struct sky2_port *sky2,
1111 const struct rx_ring_info *re)
1112{
1113 int i;
1114
1115 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1116
1117 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1118 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1119}
1120
1121
454e6cb6 1122static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1123 unsigned size)
1124{
1125 struct sk_buff *skb = re->skb;
1126 int i;
1127
1128 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1129 if (pci_dma_mapping_error(pdev, re->data_addr))
1130 goto mapping_error;
454e6cb6 1131
14d0263f
SH		 1132 pci_unmap_len_set(re, data_size, size);
1133
3fbd9187 1134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1136
1137 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1138 frag->page_offset,
1139 frag->size,
14d0263f 1140 PCI_DMA_FROMDEVICE);
3fbd9187 1141
1142 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1143 goto map_page_error;
1144 }
454e6cb6 1145 return 0;
3fbd9187 1146
1147map_page_error:
1148 while (--i >= 0) {
1149 pci_unmap_page(pdev, re->frag_addr[i],
1150 skb_shinfo(skb)->frags[i].size,
1151 PCI_DMA_FROMDEVICE);
1152 }
1153
1154 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1155 PCI_DMA_FROMDEVICE);
1156
1157mapping_error:
1158 if (net_ratelimit())
1159 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1160 skb->dev->name);
1161 return -EIO;
14d0263f
SH		 1162}
1163
1164static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1165{
1166 struct sk_buff *skb = re->skb;
1167 int i;
1168
1169 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1170 PCI_DMA_FROMDEVICE);
1171
1172 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1173 pci_unmap_page(pdev, re->frag_addr[i],
1174 skb_shinfo(skb)->frags[i].size,
1175 PCI_DMA_FROMDEVICE);
1176}
793b883e 1177
cd28ab6a
SH		 1178/* Tell chip where to start receive checksum.
1179 * Actually has two checksums, but set both same to avoid possible byte
1180 * order problems.
1181 */
793b883e 1182static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1183{
ea76e635 1184 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1185
ea76e635
SH		 1186 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1187 le->ctrl = 0;
1188 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1189
ea76e635
SH		 1190 sky2_write32(sky2->hw,
1191 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1192 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1193 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1194}
1195
6b1a3aef
SH		 1196/*
1197 * The RX Stop command will not work for Yukon-2 if the BMU does not
1198 * reach the end of packet and since we can't make sure that we have
1199 * incoming data, we must reset the BMU while it is not doing a DMA
1200 * transfer. Since it is possible that the RX path is still active,
1201 * the RX RAM buffer will be stopped first, so any possible incoming
1202 * data will not trigger a DMA. After the RAM buffer is stopped, the
1203 * BMU is polled until any DMA in progress is ended and only then it
1204 * will be reset.
1205 */
1206static void sky2_rx_stop(struct sky2_port *sky2)
1207{
1208 struct sky2_hw *hw = sky2->hw;
1209 unsigned rxq = rxqaddr[sky2->port];
1210 int i;
1211
1212 /* disable the RAM Buffer receive queue */
1213 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1214
1215 for (i = 0; i < 0xffff; i++)
1216 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1217 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1218 goto stopped;
1219
ada1db5c 1220 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1221stopped:
1222 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1223
1224 /* reset the Rx prefetch unit */
1225 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1226 mmiowb();
6b1a3aef 1227}
793b883e 1228
d571b694 1229/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1230static void sky2_rx_clean(struct sky2_port *sky2)
1231{
1232 unsigned i;
1233
1234 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1235 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1236 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1237
1238 if (re->skb) {
14d0263f 1239 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1240 kfree_skb(re->skb);
1241 re->skb = NULL;
1242 }
1243 }
1244}
1245
ef743d33
SH		 1246/* Basic MII support */
1247static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1248{
1249 struct mii_ioctl_data *data = if_mii(ifr);
1250 struct sky2_port *sky2 = netdev_priv(dev);
1251 struct sky2_hw *hw = sky2->hw;
1252 int err = -EOPNOTSUPP;
1253
1254 if (!netif_running(dev))
1255 return -ENODEV; /* Phy still in reset */
1256
d89e1343 1257 switch (cmd) {
ef743d33
SH		 1258 case SIOCGMIIPHY:
1259 data->phy_id = PHY_ADDR_MARV;
1260
1261 /* fallthru */
1262 case SIOCGMIIREG: {
1263 u16 val = 0;
91c86df5 1264
e07b1aa8 1265 spin_lock_bh(&sky2->phy_lock);
ef743d33 1266 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1267 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1268
ef743d33
SH		 1269 data->val_out = val;
1270 break;
1271 }
1272
1273 case SIOCSMIIREG:
e07b1aa8 1274 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1275 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1276 data->val_in);
e07b1aa8 1277 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1278 break;
1279 }
1280 return err;
1281}
1282
d1f13708 1283#ifdef SKY2_VLAN_TAG_USED
d494eacd 1284static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1285{
d494eacd 1286 if (onoff) {
3d4e66f5
SH		 1287 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1288 RX_VLAN_STRIP_ON);
1289 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1290 TX_VLAN_TAG_ON);
1291 } else {
1292 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1293 RX_VLAN_STRIP_OFF);
1294 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1295 TX_VLAN_TAG_OFF);
1296 }
d494eacd
SH		 1297}
1298
1299static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1300{
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
1303 u16 port = sky2->port;
1304
1305 netif_tx_lock_bh(dev);
1306 napi_disable(&hw->napi);
1307
1308 sky2->vlgrp = grp;
1309 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1310
d1d08d12 1311 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1312 napi_enable(&hw->napi);
2bb8c262 1313 netif_tx_unlock_bh(dev);
d1f13708
SH		 1314}
1315#endif
1316
bd1c6869
SH		 1317/* Amount of required worst case padding in rx buffer */
1318static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1319{
1320 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1321}
1322
82788c7a 1323/*
14d0263f
SH		 1324 * Allocate an skb for receiving. If the MTU is large enough
1325 * make the skb non-linear with a fragment list of pages.
82788c7a 1326 */
14d0263f 1327static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1328{
1329 struct sk_buff *skb;
14d0263f 1330 int i;
82788c7a 1331
724b6942
SH		 1332 skb = netdev_alloc_skb(sky2->netdev,
1333 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1334 if (!skb)
1335 goto nomem;
1336
39dbd958 1337 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1338 unsigned char *start;
1339 /*
1340 * Workaround for a bug in FIFO that cause hang
1341 * if the FIFO if the receive buffer is not 64 byte aligned.
1342 * The buffer returned from netdev_alloc_skb is
1343 * aligned except if slab debugging is enabled.
1344 */
f03b8654
SH		 1345 start = PTR_ALIGN(skb->data, 8);
1346 skb_reserve(skb, start - skb->data);
bd1c6869 1347 } else
f03b8654 1348 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1349
1350 for (i = 0; i < sky2->rx_nfrags; i++) {
1351 struct page *page = alloc_page(GFP_ATOMIC);
1352
1353 if (!page)
1354 goto free_partial;
1355 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1356 }
1357
1358 return skb;
14d0263f
SH		 1359free_partial:
1360 kfree_skb(skb);
1361nomem:
1362 return NULL;
82788c7a
SH		 1363}
1364
55c9dd35
SH		 1365static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1366{
1367 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1368}
1369
200ac492
MM		 1370static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1371{
1372 struct sky2_hw *hw = sky2->hw;
1373 unsigned i;
1374
1375 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1376
1377 /* Fill Rx ring */
1378 for (i = 0; i < sky2->rx_pending; i++) {
1379 struct rx_ring_info *re = sky2->rx_ring + i;
1380
1381 re->skb = sky2_rx_alloc(sky2);
1382 if (!re->skb)
1383 return -ENOMEM;
1384
1385 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1386 dev_kfree_skb(re->skb);
1387 re->skb = NULL;
1388 return -ENOMEM;
1389 }
1390 }
1391 return 0;
1392}
1393
cd28ab6a 1394/*
200ac492 1395 * Setup receiver buffer pool.
14d0263f
SH		 1396 * Normal case this ends up creating one list element for skb
1397 * in the receive ring. Worst case if using large MTU and each
1398 * allocation falls on a different 64 bit region, that results
1399 * in 6 list elements per ring entry.
1400 * One element is used for checksum enable/disable, and one
1401 * extra to avoid wrap.
cd28ab6a 1402 */
200ac492 1403static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1404{
6b1a3aef 1405 struct sky2_hw *hw = sky2->hw;
14d0263f 1406 struct rx_ring_info *re;
6b1a3aef 1407 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1408 unsigned i, thresh;
cd28ab6a 1409
6b1a3aef 1410 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1411 sky2_qset(hw, rxq);
977bdf06 1412
c3905bc4
SH		 1413 /* On PCI express lowering the watermark gives better performance */
1414 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1415 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1416
1417 /* These chips have no ram buffer?
1418 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1419 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1420 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1421 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1422
6b1a3aef
SH		 1423 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1424
ea76e635
SH		 1425 if (!(hw->flags & SKY2_HW_NEW_LE))
1426 rx_set_checksum(sky2);
14d0263f 1427
200ac492 1428 /* submit Rx ring */
793b883e 1429 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1430 re = sky2->rx_ring + i;
14d0263f 1431 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1432 }
1433
a1433ac4
SH		 1434 /*
1435 * The receiver hangs if it receives frames larger than the
1436 * packet buffer. As a workaround, truncate oversize frames, but
1437 * the register is limited to 9 bits, so if you do frames > 2052
1438 * you better get the MTU right!
1439 */
39ef110b 1440 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1441 if (thresh > 0x1ff)
1442 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1443 else {
1444 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1445 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1446 }
1447
6b1a3aef 1448 /* Tell chip about available buffers */
55c9dd35 1449 sky2_rx_update(sky2, rxq);
877c8570
SH		 1450
1451 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1452 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1453 /*
1454 * Disable flushing of non ASF packets;
1455 * must be done after initializing the BMUs;
1456 * drivers without ASF support should do this too, otherwise
1457 * it may happen that they cannot run on ASF devices;
1458 * remember that the MAC FIFO isn't reset during initialization.
1459 */
1460 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1461 }
1462
1463 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1464 /* Enable RX Home Address & Routing Header checksum fix */
1465 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1466 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1467
1468 /* Enable TX Home Address & Routing Header checksum fix */
1469 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1470 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1471 }
cd28ab6a
SH		 1472}
1473
90bbebb4
MM		 1474static int sky2_alloc_buffers(struct sky2_port *sky2)
1475{
1476 struct sky2_hw *hw = sky2->hw;
1477
1478 /* must be power of 2 */
1479 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1480 sky2->tx_ring_size *
1481 sizeof(struct sky2_tx_le),
1482 &sky2->tx_le_map);
1483 if (!sky2->tx_le)
1484 goto nomem;
1485
1486 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1487 GFP_KERNEL);
1488 if (!sky2->tx_ring)
1489 goto nomem;
1490
1491 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1492 &sky2->rx_le_map);
1493 if (!sky2->rx_le)
1494 goto nomem;
1495 memset(sky2->rx_le, 0, RX_LE_BYTES);
1496
1497 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1498 GFP_KERNEL);
1499 if (!sky2->rx_ring)
1500 goto nomem;
1501
200ac492 1502 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1503nomem:
1504 return -ENOMEM;
1505}
1506
1507static void sky2_free_buffers(struct sky2_port *sky2)
1508{
1509 struct sky2_hw *hw = sky2->hw;
1510
200ac492
MM		 1511 sky2_rx_clean(sky2);
1512
90bbebb4
MM		 1513 if (sky2->rx_le) {
1514 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1515 sky2->rx_le, sky2->rx_le_map);
1516 sky2->rx_le = NULL;
1517 }
1518 if (sky2->tx_le) {
1519 pci_free_consistent(hw->pdev,
1520 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1521 sky2->tx_le, sky2->tx_le_map);
1522 sky2->tx_le = NULL;
1523 }
1524 kfree(sky2->tx_ring);
1525 kfree(sky2->rx_ring);
1526
1527 sky2->tx_ring = NULL;
1528 sky2->rx_ring = NULL;
1529}
1530
ea0f71e5 1531static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1532{
cd28ab6a
SH		 1533 struct sky2_hw *hw = sky2->hw;
1534 unsigned port = sky2->port;
ea0f71e5
MM		 1535 u32 ramsize;
1536 int cap;
843a46f4 1537 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1538
ea0f71e5
MM		 1539 tx_init(sky2);
1540
ee7abb04
SH		 1541 /*
1542 * On dual port PCI-X card, there is an problem where status
1543 * can be received out of order due to split transactions
843a46f4 1544 */
ee7abb04
SH		 1545 if (otherdev && netif_running(otherdev) &&
1546 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1547 u16 cmd;
1548
b32f40c4 1549 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1550 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1551 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1552 }
cd28ab6a 1553
cd28ab6a
SH		 1554 sky2_mac_init(hw, port);
1555
e0c28116
SH		 1556 /* Register is number of 4K blocks on internal RAM buffer. */
1557 ramsize = sky2_read8(hw, B2_E_0) * 4;
1558 if (ramsize > 0) {
67712901 1559 u32 rxspace;
cd28ab6a 1560
ada1db5c 1561 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1562 if (ramsize < 16)
1563 rxspace = ramsize / 2;
1564 else
1565 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1566
67712901
SH		 1567 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1568 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1569
1570 /* Make sure SyncQ is disabled */
1571 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1572 RB_RST_SET);
1573 }
793b883e 1574
af4ed7e6 1575 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1576
69161611
SH		 1577 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1578 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1579 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1580
977bdf06 1581 /* Set almost empty threshold */
8e95a202
JP		 1582 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1583 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1584 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1585
6b1a3aef 1586 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1587 sky2->tx_ring_size - 1);
cd28ab6a 1588
d494eacd
SH		 1589#ifdef SKY2_VLAN_TAG_USED
1590 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1591#endif
1592
200ac492 1593 sky2_rx_start(sky2);
ea0f71e5
MM		 1594}
1595
1596/* Bring up network interface. */
1597static int sky2_up(struct net_device *dev)
1598{
1599 struct sky2_port *sky2 = netdev_priv(dev);
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u32 imask;
1603 int err;
1604
1605 netif_carrier_off(dev);
1606
1607 err = sky2_alloc_buffers(sky2);
1608 if (err)
1609 goto err_out;
1610
1611 sky2_hw_up(sky2);
cd28ab6a 1612
cd28ab6a 1613 /* Enable interrupts from phy/mac for port */
e07b1aa8 1614 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1615 imask |= portirq_msk[port];
e07b1aa8 1616 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1617 sky2_read32(hw, B0_IMSK);
e07b1aa8 1618
6c35abae 1619 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1620
cd28ab6a
SH		 1621 return 0;
1622
1623err_out:
90bbebb4 1624 sky2_free_buffers(sky2);
cd28ab6a
SH		 1625 return err;
1626}
1627
793b883e 1628/* Modular subtraction in ring */
ee5f68fe 1629static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1630{
ee5f68fe 1631 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1632}
cd28ab6a 1633
793b883e
SH		 1634/* Number of list elements available for next tx */
1635static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1636{
ee5f68fe 1637 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1638}
1639
793b883e 1640/* Estimate of number of transmit list elements required */
28bd181a 1641static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1642{
793b883e
SH		 1643 unsigned count;
1644
07e31637
SH		 1645 count = (skb_shinfo(skb)->nr_frags + 1)
1646 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1647
89114afd 1648 if (skb_is_gso(skb))
793b883e 1649 ++count;
07e31637
SH		 1650 else if (sizeof(dma_addr_t) == sizeof(u32))
1651 ++count; /* possible vlan */
793b883e 1652
84fa7933 1653 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1654 ++count;
1655
1656 return count;
cd28ab6a
SH		 1657}
1658
f6815077 1659static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1660{
1661 if (re->flags & TX_MAP_SINGLE)
1662 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1663 pci_unmap_len(re, maplen),
1664 PCI_DMA_TODEVICE);
1665 else if (re->flags & TX_MAP_PAGE)
1666 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1667 pci_unmap_len(re, maplen),
1668 PCI_DMA_TODEVICE);
f6815077 1669 re->flags = 0;
6b84daca
SH		 1670}
1671
793b883e
SH		 1672/*
1673 * Put one packet in ring for transmit.
1674 * A single packet can generate multiple list elements, and
1675 * the number of ring elements will probably be less than the number
1676 * of list elements used.
1677 */
61357325
SH		 1678static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1679 struct net_device *dev)
cd28ab6a
SH		 1680{
1681 struct sky2_port *sky2 = netdev_priv(dev);
1682 struct sky2_hw *hw = sky2->hw;
d1f13708 1683 struct sky2_tx_le *le = NULL;
6cdbbdf3 1684 struct tx_ring_info *re;
9b289c33 1685 unsigned i, len;
cd28ab6a 1686 dma_addr_t mapping;
5dce95e5
SH		 1687 u32 upper;
1688 u16 slot;
cd28ab6a
SH		 1689 u16 mss;
1690 u8 ctrl;
1691
2bb8c262
SH		 1692 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1693 return NETDEV_TX_BUSY;
cd28ab6a 1694
cd28ab6a
SH		 1695 len = skb_headlen(skb);
1696 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1697
454e6cb6
SH		 1698 if (pci_dma_mapping_error(hw->pdev, mapping))
1699 goto mapping_error;
1700
9b289c33 1701 slot = sky2->tx_prod;
6c35abae
JP		 1702 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1703 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1704
86c6887e 1705 /* Send high bits if needed */
5dce95e5
SH		 1706 upper = upper_32_bits(mapping);
1707 if (upper != sky2->tx_last_upper) {
9b289c33 1708 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1709 le->addr = cpu_to_le32(upper);
1710 sky2->tx_last_upper = upper;
793b883e 1711 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1712 }
cd28ab6a
SH		 1713
1714 /* Check for TCP Segmentation Offload */
7967168c 1715 mss = skb_shinfo(skb)->gso_size;
793b883e 1716 if (mss != 0) {
ea76e635
SH		 1717
1718 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1719 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1720
1721 if (mss != sky2->tx_last_mss) {
9b289c33 1722 le = get_tx_le(sky2, &slot);
69161611 1723 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1724
1725 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1726 le->opcode = OP_MSS | HW_OWNER;
1727 else
1728 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1729 sky2->tx_last_mss = mss;
1730 }
cd28ab6a
SH		 1731 }
1732
cd28ab6a 1733 ctrl = 0;
d1f13708
SH		 1734#ifdef SKY2_VLAN_TAG_USED
1735 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1736 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1737 if (!le) {
9b289c33 1738 le = get_tx_le(sky2, &slot);
f65b138c 1739 le->addr = 0;
d1f13708 1740 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1741 } else
1742 le->opcode |= OP_VLAN;
1743 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1744 ctrl |= INS_VLAN;
1745 }
1746#endif
1747
1748 /* Handle TCP checksum offload */
84fa7933 1749 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1750 /* On Yukon EX (some versions) encoding change. */
ea76e635 1751 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1752 ctrl |= CALSUM; /* auto checksum */
1753 else {
1754 const unsigned offset = skb_transport_offset(skb);
1755 u32 tcpsum;
1756
1757 tcpsum = offset << 16; /* sum start */
1758 tcpsum |= offset + skb->csum_offset; /* sum write */
1759
1760 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1761 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1762 ctrl |= UDPTCP;
1763
1764 if (tcpsum != sky2->tx_tcpsum) {
1765 sky2->tx_tcpsum = tcpsum;
1766
9b289c33 1767 le = get_tx_le(sky2, &slot);
69161611
SH		 1768 le->addr = cpu_to_le32(tcpsum);
1769 le->length = 0; /* initial checksum value */
1770 le->ctrl = 1; /* one packet */
1771 le->opcode = OP_TCPLISW | HW_OWNER;
1772 }
1d179332 1773 }
cd28ab6a
SH		 1774 }
1775
6b84daca
SH		 1776 re = sky2->tx_ring + slot;
1777 re->flags = TX_MAP_SINGLE;
1778 pci_unmap_addr_set(re, mapaddr, mapping);
1779 pci_unmap_len_set(re, maplen, len);
1780
9b289c33 1781 le = get_tx_le(sky2, &slot);
d6e74b6b 1782 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1783 le->length = cpu_to_le16(len);
1784 le->ctrl = ctrl;
793b883e 1785 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1786
cd28ab6a
SH		 1787
1788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1789 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1790
1791 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1792 frag->size, PCI_DMA_TODEVICE);
86c6887e 1793
454e6cb6
SH		 1794 if (pci_dma_mapping_error(hw->pdev, mapping))
1795 goto mapping_unwind;
1796
5dce95e5
SH		 1797 upper = upper_32_bits(mapping);
1798 if (upper != sky2->tx_last_upper) {
9b289c33 1799 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1800 le->addr = cpu_to_le32(upper);
1801 sky2->tx_last_upper = upper;
793b883e 1802 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1803 }
1804
6b84daca
SH		 1805 re = sky2->tx_ring + slot;
1806 re->flags = TX_MAP_PAGE;
1807 pci_unmap_addr_set(re, mapaddr, mapping);
1808 pci_unmap_len_set(re, maplen, frag->size);
1809
9b289c33 1810 le = get_tx_le(sky2, &slot);
d6e74b6b 1811 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1812 le->length = cpu_to_le16(frag->size);
1813 le->ctrl = ctrl;
793b883e 1814 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1815 }
6cdbbdf3 1816
6b84daca 1817 re->skb = skb;
cd28ab6a
SH		 1818 le->ctrl |= EOP;
1819
9b289c33
MM		 1820 sky2->tx_prod = slot;
1821
97bda706
SH		 1822 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1823 netif_stop_queue(dev);
b19666d9 1824
290d4de5 1825 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1826
cd28ab6a 1827 return NETDEV_TX_OK;
454e6cb6
SH		 1828
1829mapping_unwind:
ee5f68fe 1830 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1831 re = sky2->tx_ring + i;
1832
6b84daca 1833 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1834 }
1835
454e6cb6
SH		 1836mapping_error:
1837 if (net_ratelimit())
1838 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1839 dev_kfree_skb(skb);
1840 return NETDEV_TX_OK;
cd28ab6a
SH		 1841}
1842
cd28ab6a 1843/*
793b883e
SH		 1844 * Free ring elements from starting at tx_cons until "done"
1845 *
481cea4a
SH		 1846 * NB:
1847 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1848 * buffers so make sure not to free skb to early.
481cea4a
SH		 1849 * 2. This may run in parallel start_xmit because the it only
1850 * looks at the tail of the queue of FIFO (tx_cons), not
1851 * the head (tx_prod)
cd28ab6a 1852 */
d11c13e7 1853static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1854{
d11c13e7 1855 struct net_device *dev = sky2->netdev;
291ea614 1856 unsigned idx;
cd28ab6a 1857
ee5f68fe 1858 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1859
291ea614 1860 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1861 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1862 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1863 struct sk_buff *skb = re->skb;
291ea614 1864
6b84daca 1865 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1866
6b84daca 1867 if (skb) {
6c35abae
JP		 1868 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1869 "tx done %u\n", idx);
3cf26753 1870
7138a0f5 1871 dev->stats.tx_packets++;
bd1c6869
SH		 1872 dev->stats.tx_bytes += skb->len;
1873
f6815077 1874 re->skb = NULL;
724b6942 1875 dev_kfree_skb_any(skb);
2bf56fe2 1876
ee5f68fe 1877 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1878 }
793b883e 1879 }
793b883e 1880
291ea614 1881 sky2->tx_cons = idx;
50432cb5 1882 smp_mb();
cd28ab6a
SH		 1883}
1884
264bb4fa 1885static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1886{
a510996b
MM		 1887 /* Disable Force Sync bit and Enable Alloc bit */
1888 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1889 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1890
1891 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1892 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1893 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1894
1895 /* Reset the PCI FIFO of the async Tx queue */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1897 BMU_RST_SET | BMU_FIFO_RST);
1898
1899 /* Reset the Tx prefetch units */
1900 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1901 PREF_UNIT_RST_SET);
1902
1903 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1904 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1905}
1906
f2b31cb3 1907static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1908{
cd28ab6a
SH		 1909 struct sky2_hw *hw = sky2->hw;
1910 unsigned port = sky2->port;
f2b31cb3 1911 u16 ctrl;
cd28ab6a 1912
d104acaf
SH		 1913 /* Force flow control off */
1914 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1915
cd28ab6a
SH		 1916 /* Stop transmitter */
1917 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1918 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1919
1920 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1921 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1922
1923 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1924 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1925 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1926
1927 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1928
1929 /* Workaround shared GMAC reset */
8e95a202
JP		 1930 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1931 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1932 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1933
cd28ab6a 1934 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1935
6c83504f
SH		 1936 /* Force any delayed status interrrupt and NAPI */
1937 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1938 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1939 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1940 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1941
a947a39d
MM		 1942 sky2_rx_stop(sky2);
1943
0da6d7b3 1944 spin_lock_bh(&sky2->phy_lock);
b96936da 1945 sky2_phy_power_down(hw, port);
0da6d7b3 1946 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1947
264bb4fa
MM		 1948 sky2_tx_reset(hw, port);
1949
481cea4a
SH		 1950 /* Free any pending frames stuck in HW queue */
1951 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1952}
1953
1954/* Network shutdown */
1955static int sky2_down(struct net_device *dev)
1956{
1957 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1958 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1959
1960 /* Never really got started! */
1961 if (!sky2->tx_le)
1962 return 0;
1963
6c35abae 1964 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 1965
8a0c9228
MM		 1966 /* Disable port IRQ */
1967 sky2_write32(hw, B0_IMSK,
1968 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
1969 sky2_read32(hw, B0_IMSK);
1970
1971 synchronize_irq(hw->pdev->irq);
1972 napi_synchronize(&hw->napi);
1973
f2b31cb3 1974 sky2_hw_down(sky2);
481cea4a 1975
90bbebb4 1976 sky2_free_buffers(sky2);
1b537565 1977
cd28ab6a
SH		 1978 return 0;
1979}
1980
1981static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1982{
ea76e635 1983 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1984 return SPEED_1000;
1985
05745c4a
SH		 1986 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1987 if (aux & PHY_M_PS_SPEED_100)
1988 return SPEED_100;
1989 else
1990 return SPEED_10;
1991 }
cd28ab6a
SH		 1992
1993 switch (aux & PHY_M_PS_SPEED_MSK) {
1994 case PHY_M_PS_SPEED_1000:
1995 return SPEED_1000;
1996 case PHY_M_PS_SPEED_100:
1997 return SPEED_100;
1998 default:
1999 return SPEED_10;
2000 }
2001}
2002
2003static void sky2_link_up(struct sky2_port *sky2)
2004{
2005 struct sky2_hw *hw = sky2->hw;
2006 unsigned port = sky2->port;
2007 u16 reg;
16ad91e1
SH		 2008 static const char *fc_name[] = {
2009 [FC_NONE] = "none",
2010 [FC_TX] = "tx",
2011 [FC_RX] = "rx",
2012 [FC_BOTH] = "both",
2013 };
cd28ab6a 2014
cd28ab6a 2015 /* enable Rx/Tx */
2eaba1a2 2016 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2017 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2018 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2019
2020 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2021
2022 netif_carrier_on(sky2->netdev);
cd28ab6a 2023
75e80683 2024 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2025
cd28ab6a 2026 /* Turn on link LED */
793b883e 2027 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2028 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2029
6c35abae
JP		 2030 netif_info(sky2, link, sky2->netdev,
2031 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2032 sky2->speed,
2033 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2034 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2035}
2036
2037static void sky2_link_down(struct sky2_port *sky2)
2038{
2039 struct sky2_hw *hw = sky2->hw;
2040 unsigned port = sky2->port;
2041 u16 reg;
2042
2043 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2044
2045 reg = gma_read16(hw, port, GM_GP_CTRL);
2046 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2047 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2048
cd28ab6a 2049 netif_carrier_off(sky2->netdev);
cd28ab6a 2050
809aaaae 2051 /* Turn off link LED */
cd28ab6a
SH		 2052 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2053
6c35abae 2054 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2055
cd28ab6a
SH		 2056 sky2_phy_init(hw, port);
2057}
2058
16ad91e1
SH		 2059static enum flow_control sky2_flow(int rx, int tx)
2060{
2061 if (rx)
2062 return tx ? FC_BOTH : FC_RX;
2063 else
2064 return tx ? FC_TX : FC_NONE;
2065}
2066
793b883e
SH		 2067static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2068{
2069 struct sky2_hw *hw = sky2->hw;
2070 unsigned port = sky2->port;
da4c1ff4 2071 u16 advert, lpa;
793b883e 2072
da4c1ff4 2073 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2074 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2075 if (lpa & PHY_M_AN_RF) {
ada1db5c 2076 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2077 return -1;
2078 }
2079
793b883e 2080 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2081 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2082 return -1;
2083 }
2084
793b883e 2085 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2086 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2087
da4c1ff4
SH		 2088 /* Since the pause result bits seem to in different positions on
2089 * different chips. look at registers.
2090 */
ea76e635 2091 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2092 /* Shift for bits in fiber PHY */
2093 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2094 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2095
2096 if (advert & ADVERTISE_1000XPAUSE)
2097 advert |= ADVERTISE_PAUSE_CAP;
2098 if (advert & ADVERTISE_1000XPSE_ASYM)
2099 advert |= ADVERTISE_PAUSE_ASYM;
2100 if (lpa & LPA_1000XPAUSE)
2101 lpa |= LPA_PAUSE_CAP;
2102 if (lpa & LPA_1000XPAUSE_ASYM)
2103 lpa |= LPA_PAUSE_ASYM;
2104 }
793b883e 2105
da4c1ff4
SH		 2106 sky2->flow_status = FC_NONE;
2107 if (advert & ADVERTISE_PAUSE_CAP) {
2108 if (lpa & LPA_PAUSE_CAP)
2109 sky2->flow_status = FC_BOTH;
2110 else if (advert & ADVERTISE_PAUSE_ASYM)
2111 sky2->flow_status = FC_RX;
2112 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2113 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2114 sky2->flow_status = FC_TX;
2115 }
793b883e 2116
8e95a202
JP		 2117 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2118 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2119 sky2->flow_status = FC_NONE;
2eaba1a2 2120
da4c1ff4 2121 if (sky2->flow_status & FC_TX)
793b883e
SH		 2122 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2123 else
2124 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2125
2126 return 0;
2127}
cd28ab6a 2128
e07b1aa8
SH		 2129/* Interrupt from PHY */
2130static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2131{
e07b1aa8
SH		 2132 struct net_device *dev = hw->dev[port];
2133 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2134 u16 istatus, phystat;
2135
ebc646f6
SH		 2136 if (!netif_running(dev))
2137 return;
2138
e07b1aa8
SH		 2139 spin_lock(&sky2->phy_lock);
2140 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2141 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2142
6c35abae
JP		 2143 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2144 istatus, phystat);
cd28ab6a 2145
0ea065e5 2146 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2147 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2148 !netif_carrier_ok(dev))
793b883e
SH		 2149 sky2_link_up(sky2);
2150 goto out;
2151 }
cd28ab6a 2152
793b883e
SH		 2153 if (istatus & PHY_M_IS_LSP_CHANGE)
2154 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2155
793b883e
SH		 2156 if (istatus & PHY_M_IS_DUP_CHANGE)
2157 sky2->duplex =
2158 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2159
793b883e
SH		 2160 if (istatus & PHY_M_IS_LST_CHANGE) {
2161 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2162 sky2_link_up(sky2);
793b883e
SH		 2163 else
2164 sky2_link_down(sky2);
cd28ab6a 2165 }
793b883e 2166out:
e07b1aa8 2167 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2168}
2169
0f5aac70
SH		 2170/* Special quick link interrupt (Yukon-2 Optima only) */
2171static void sky2_qlink_intr(struct sky2_hw *hw)
2172{
2173 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2174 u32 imask;
2175 u16 phy;
2176
2177 /* disable irq */
2178 imask = sky2_read32(hw, B0_IMSK);
2179 imask &= ~Y2_IS_PHY_QLNK;
2180 sky2_write32(hw, B0_IMSK, imask);
2181
2182 /* reset PHY Link Detect */
2183 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2185 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2186 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2187
2188 sky2_link_up(sky2);
2189}
2190
62335ab0 2191/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2192 * and tx queue is full (stopped).
2193 */
cd28ab6a
SH		 2194static void sky2_tx_timeout(struct net_device *dev)
2195{
2196 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2197 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2198
6c35abae 2199 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2200
ada1db5c
JP		 2201 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2202 sky2->tx_cons, sky2->tx_prod,
2203 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2204 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2205
81906791
SH		 2206 /* can't restart safely under softirq */
2207 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2208}
2209
2210static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2211{
6b1a3aef
SH		 2212 struct sky2_port *sky2 = netdev_priv(dev);
2213 struct sky2_hw *hw = sky2->hw;
b628ed98 2214 unsigned port = sky2->port;
6b1a3aef
SH		 2215 int err;
2216 u16 ctl, mode;
e07b1aa8 2217 u32 imask;
cd28ab6a 2218
44dde56d 2219 /* MTU size outside the spec */
cd28ab6a
SH		 2220 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2221 return -EINVAL;
2222
44dde56d 2223 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2224 if (new_mtu > ETH_DATA_LEN &&
2225 (hw->chip_id == CHIP_ID_YUKON_FE ||
2226 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2227 return -EINVAL;
2228
44dde56d 2229 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2230 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2231 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2232
6b1a3aef
SH		 2233 if (!netif_running(dev)) {
2234 dev->mtu = new_mtu;
2235 return 0;
2236 }
2237
e07b1aa8 2238 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2239 sky2_write32(hw, B0_IMSK, 0);
2240
018d1c66
SH		 2241 dev->trans_start = jiffies; /* prevent tx timeout */
2242 netif_stop_queue(dev);
bea3348e 2243 napi_disable(&hw->napi);
018d1c66 2244
e07b1aa8
SH		 2245 synchronize_irq(hw->pdev->irq);
2246
39dbd958 2247 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2248 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2249
2250 ctl = gma_read16(hw, port, GM_GP_CTRL);
2251 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2252 sky2_rx_stop(sky2);
2253 sky2_rx_clean(sky2);
cd28ab6a
SH		 2254
2255 dev->mtu = new_mtu;
14d0263f 2256
6b1a3aef
SH		 2257 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2258 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2259
2260 if (dev->mtu > ETH_DATA_LEN)
2261 mode |= GM_SMOD_JUMBO_ENA;
2262
b628ed98 2263 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2264
b628ed98 2265 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2266
200ac492
MM		 2267 err = sky2_alloc_rx_skbs(sky2);
2268 if (!err)
2269 sky2_rx_start(sky2);
2270 else
2271 sky2_rx_clean(sky2);
e07b1aa8 2272 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2273
d1d08d12 2274 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2275 napi_enable(&hw->napi);
2276
1b537565
SH		 2277 if (err)
2278 dev_close(dev);
2279 else {
b628ed98 2280 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2281
1b537565
SH		 2282 netif_wake_queue(dev);
2283 }
2284
cd28ab6a
SH		 2285 return err;
2286}
2287
14d0263f
SH		 2288/* For small just reuse existing skb for next receive */
2289static struct sk_buff *receive_copy(struct sky2_port *sky2,
2290 const struct rx_ring_info *re,
2291 unsigned length)
2292{
2293 struct sk_buff *skb;
2294
89d71a66 2295 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2296 if (likely(skb)) {
14d0263f
SH		 2297 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2298 length, PCI_DMA_FROMDEVICE);
d626f62b 2299 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2300 skb->ip_summed = re->skb->ip_summed;
2301 skb->csum = re->skb->csum;
2302 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2303 length, PCI_DMA_FROMDEVICE);
2304 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2305 skb_put(skb, length);
14d0263f
SH		 2306 }
2307 return skb;
2308}
2309
2310/* Adjust length of skb with fragments to match received data */
2311static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2312 unsigned int length)
2313{
2314 int i, num_frags;
2315 unsigned int size;
2316
2317 /* put header into skb */
2318 size = min(length, hdr_space);
2319 skb->tail += size;
2320 skb->len += size;
2321 length -= size;
2322
2323 num_frags = skb_shinfo(skb)->nr_frags;
2324 for (i = 0; i < num_frags; i++) {
2325 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2326
2327 if (length == 0) {
2328 /* don't need this page */
2329 __free_page(frag->page);
2330 --skb_shinfo(skb)->nr_frags;
2331 } else {
2332 size = min(length, (unsigned) PAGE_SIZE);
2333
2334 frag->size = size;
2335 skb->data_len += size;
2336 skb->truesize += size;
2337 skb->len += size;
2338 length -= size;
2339 }
2340 }
2341}
2342
2343/* Normal packet - take skb from ring element and put in a new one */
2344static struct sk_buff *receive_new(struct sky2_port *sky2,
2345 struct rx_ring_info *re,
2346 unsigned int length)
2347{
3fbd9187 2348 struct sk_buff *skb;
2349 struct rx_ring_info nre;
14d0263f
SH		 2350 unsigned hdr_space = sky2->rx_data_size;
2351
3fbd9187 2352 nre.skb = sky2_rx_alloc(sky2);
2353 if (unlikely(!nre.skb))
2354 goto nobuf;
2355
2356 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2357 goto nomap;
14d0263f
SH		 2358
2359 skb = re->skb;
2360 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2361 prefetch(skb->data);
3fbd9187 2362 *re = nre;
14d0263f
SH		 2363
2364 if (skb_shinfo(skb)->nr_frags)
2365 skb_put_frags(skb, hdr_space, length);
2366 else
489b10c1 2367 skb_put(skb, length);
14d0263f 2368 return skb;
3fbd9187 2369
2370nomap:
2371 dev_kfree_skb(nre.skb);
2372nobuf:
2373 return NULL;
14d0263f
SH		 2374}
2375
cd28ab6a
SH		 2376/*
2377 * Receive one packet.
d571b694 2378 * For larger packets, get new buffer.
cd28ab6a 2379 */
497d7c86 2380static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2381 u16 length, u32 status)
2382{
497d7c86 2383 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2384 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2385 struct sk_buff *skb = NULL;
d6532232
SH		 2386 u16 count = (status & GMR_FS_LEN) >> 16;
2387
2388#ifdef SKY2_VLAN_TAG_USED
2389 /* Account for vlan tag */
2390 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2391 count -= VLAN_HLEN;
2392#endif
cd28ab6a 2393
6c35abae
JP		 2394 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2395 "rx slot %u status 0x%x len %d\n",
2396 sky2->rx_next, status, length);
cd28ab6a 2397
793b883e 2398 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2399 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2400
3b12e014
SH		 2401 /* This chip has hardware problems that generates bogus status.
2402 * So do only marginal checking and expect higher level protocols
2403 * to handle crap frames.
2404 */
2405 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2406 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2407 length != count)
2408 goto okay;
2409
42eeea01 2410 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2411 goto error;
2412
42eeea01
SH		 2413 if (!(status & GMR_FS_RX_OK))
2414 goto resubmit;
2415
d6532232
SH		 2416 /* if length reported by DMA does not match PHY, packet was truncated */
2417 if (length != count)
3b12e014 2418 goto len_error;
71749531 2419
3b12e014 2420okay:
14d0263f
SH		 2421 if (length < copybreak)
2422 skb = receive_copy(sky2, re, length);
2423 else
2424 skb = receive_new(sky2, re, length);
90c30335
SH		 2425
2426 dev->stats.rx_dropped += (skb == NULL);
2427
793b883e 2428resubmit:
14d0263f 2429 sky2_rx_submit(sky2, re);
79e57d32 2430
cd28ab6a
SH		 2431 return skb;
2432
3b12e014 2433len_error:
71749531
SH		 2434 /* Truncation of overlength packets
2435 causes PHY length to not match MAC length */
7138a0f5 2436 ++dev->stats.rx_length_errors;
6c35abae
JP		 2437 if (net_ratelimit())
2438 netif_info(sky2, rx_err, dev,
2439 "rx length error: status %#x length %d\n",
2440 status, length);
d6532232 2441 goto resubmit;
71749531 2442
cd28ab6a 2443error:
7138a0f5 2444 ++dev->stats.rx_errors;
b6d77734 2445 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2446 dev->stats.rx_over_errors++;
b6d77734
SH		 2447 goto resubmit;
2448 }
6e15b712 2449
6c35abae
JP		 2450 if (net_ratelimit())
2451 netif_info(sky2, rx_err, dev,
2452 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2453
2454 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2455 dev->stats.rx_length_errors++;
cd28ab6a 2456 if (status & GMR_FS_FRAGMENT)
7138a0f5 2457 dev->stats.rx_frame_errors++;
cd28ab6a 2458 if (status & GMR_FS_CRC_ERR)
7138a0f5 2459 dev->stats.rx_crc_errors++;
79e57d32 2460
793b883e 2461 goto resubmit;
cd28ab6a
SH		 2462}
2463
e07b1aa8
SH		 2464/* Transmit complete */
2465static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2466{
e07b1aa8 2467 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2468
8a0c9228 2469 if (netif_running(dev)) {
e07b1aa8 2470 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2471
2472 /* Wake unless it's detached, and called e.g. from sky2_down() */
2473 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2474 netif_wake_queue(dev);
2475 }
cd28ab6a
SH		 2476}
2477
37e5a243
SH		 2478static inline void sky2_skb_rx(const struct sky2_port *sky2,
2479 u32 status, struct sk_buff *skb)
2480{
2481#ifdef SKY2_VLAN_TAG_USED
2482 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2483 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2484 if (skb->ip_summed == CHECKSUM_NONE)
2485 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2486 else
2487 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2488 vlan_tag, skb);
2489 return;
2490 }
2491#endif
2492 if (skb->ip_summed == CHECKSUM_NONE)
2493 netif_receive_skb(skb);
2494 else
2495 napi_gro_receive(&sky2->hw->napi, skb);
2496}
2497
bf15fe99
SH		 2498static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2499 unsigned packets, unsigned bytes)
2500{
2501 if (packets) {
2502 struct net_device *dev = hw->dev[port];
2503
2504 dev->stats.rx_packets += packets;
2505 dev->stats.rx_bytes += bytes;
2506 dev->last_rx = jiffies;
2507 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2508 }
2509}
2510
375c5688 2511static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2512{
2513 /* If this happens then driver assuming wrong format for chip type */
2514 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2515
2516 /* Both checksum counters are programmed to start at
2517 * the same offset, so unless there is a problem they
2518 * should match. This failure is an early indication that
2519 * hardware receive checksumming won't work.
2520 */
2521 if (likely((u16)(status >> 16) == (u16)status)) {
2522 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2523 skb->ip_summed = CHECKSUM_COMPLETE;
2524 skb->csum = le16_to_cpu(status);
2525 } else {
2526 dev_notice(&sky2->hw->pdev->dev,
2527 "%s: receive checksum problem (status = %#x)\n",
2528 sky2->netdev->name, status);
2529
2530 /* Disable checksum offload */
2531 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2532 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2533 BMU_DIS_RX_CHKSUM);
2534 }
2535}
2536
e07b1aa8 2537/* Process status response ring */
26691830 2538static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2539{
e07b1aa8 2540 int work_done = 0;
bf15fe99
SH		 2541 unsigned int total_bytes[2] = { 0 };
2542 unsigned int total_packets[2] = { 0 };
a8fd6266 2543
af2a58ac 2544 rmb();
26691830 2545 do {
55c9dd35 2546 struct sky2_port *sky2;
13210ce5 2547 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2548 unsigned port;
13210ce5 2549 struct net_device *dev;
cd28ab6a 2550 struct sk_buff *skb;
cd28ab6a
SH		 2551 u32 status;
2552 u16 length;
ab5adecb
SH		 2553 u8 opcode = le->opcode;
2554
2555 if (!(opcode & HW_OWNER))
2556 break;
cd28ab6a 2557
efe91932 2558 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2559
ab5adecb 2560 port = le->css & CSS_LINK_BIT;
69161611 2561 dev = hw->dev[port];
13210ce5 2562 sky2 = netdev_priv(dev);
f65b138c
SH		 2563 length = le16_to_cpu(le->length);
2564 status = le32_to_cpu(le->status);
cd28ab6a 2565
ab5adecb
SH		 2566 le->opcode = 0;
2567 switch (opcode & ~HW_OWNER) {
cd28ab6a 2568 case OP_RXSTAT:
bf15fe99
SH		 2569 total_packets[port]++;
2570 total_bytes[port] += length;
90c30335 2571
497d7c86 2572 skb = sky2_receive(dev, length, status);
90c30335 2573 if (!skb)
55c9dd35 2574 break;
13210ce5 2575
69161611 2576 /* This chip reports checksum status differently */
05745c4a 2577 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2578 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2579 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2580 (le->css & CSS_TCPUDPCSOK))
2581 skb->ip_summed = CHECKSUM_UNNECESSARY;
2582 else
2583 skb->ip_summed = CHECKSUM_NONE;
2584 }
2585
13210ce5 2586 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2587
37e5a243 2588 sky2_skb_rx(sky2, status, skb);
13210ce5 2589
22e11703 2590 /* Stop after net poll weight */
13210ce5
SH		 2591 if (++work_done >= to_do)
2592 goto exit_loop;
cd28ab6a
SH		 2593 break;
2594
d1f13708
SH		 2595#ifdef SKY2_VLAN_TAG_USED
2596 case OP_RXVLAN:
2597 sky2->rx_tag = length;
2598 break;
2599
2600 case OP_RXCHKSVLAN:
2601 sky2->rx_tag = length;
2602 /* fall through */
2603#endif
cd28ab6a 2604 case OP_RXCHKS:
375c5688 2605 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2606 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2607 break;
2608
2609 case OP_TXINDEXLE:
13b97b74 2610 /* TX index reports status for both ports */
f55925d7 2611 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2612 if (hw->dev[1])
2613 sky2_tx_done(hw->dev[1],
2614 ((status >> 24) & 0xff)
2615 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2616 break;
2617
cd28ab6a
SH		 2618 default:
2619 if (net_ratelimit())
ada1db5c 2620 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2621 }
26691830 2622 } while (hw->st_idx != idx);
cd28ab6a 2623
fe2a24df
SH		 2624 /* Fully processed status ring so clear irq */
2625 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2626
13210ce5 2627exit_loop:
bf15fe99
SH		 2628 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2629 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2630
e07b1aa8 2631 return work_done;
cd28ab6a
SH		 2632}
2633
2634static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2635{
2636 struct net_device *dev = hw->dev[port];
2637
3be92a70 2638 if (net_ratelimit())
ada1db5c 2639 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2640
2641 if (status & Y2_IS_PAR_RD1) {
3be92a70 2642 if (net_ratelimit())
ada1db5c 2643 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2644 /* Clear IRQ */
2645 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2646 }
2647
2648 if (status & Y2_IS_PAR_WR1) {
3be92a70 2649 if (net_ratelimit())
ada1db5c 2650 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2651
2652 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2653 }
2654
2655 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2656 if (net_ratelimit())
ada1db5c 2657 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2658 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2659 }
2660
2661 if (status & Y2_IS_PAR_RX1) {
3be92a70 2662 if (net_ratelimit())
ada1db5c 2663 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2664 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2665 }
2666
2667 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2668 if (net_ratelimit())
ada1db5c 2669 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2670 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2671 }
2672}
2673
2674static void sky2_hw_intr(struct sky2_hw *hw)
2675{
555382cb 2676 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2677 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2678 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2679
2680 status &= hwmsk;
cd28ab6a 2681
793b883e 2682 if (status & Y2_IS_TIST_OV)
cd28ab6a 2683 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2684
2685 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2686 u16 pci_err;
2687
a40ccc68 2688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2689 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2690 if (net_ratelimit())
555382cb 2691 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2692 pci_err);
cd28ab6a 2693
b32f40c4 2694 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2695 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2696 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2697 }
2698
2699 if (status & Y2_IS_PCI_EXP) {
d571b694 2700 /* PCI-Express uncorrectable Error occurred */
555382cb 2701 u32 err;
cd28ab6a 2702
a40ccc68 2703 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2704 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2705 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2706 0xfffffffful);
3be92a70 2707 if (net_ratelimit())
555382cb 2708 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2709
7782c8c4 2710 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2711 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2712 }
2713
2714 if (status & Y2_HWE_L1_MASK)
2715 sky2_hw_error(hw, 0, status);
2716 status >>= 8;
2717 if (status & Y2_HWE_L1_MASK)
2718 sky2_hw_error(hw, 1, status);
2719}
2720
2721static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2722{
2723 struct net_device *dev = hw->dev[port];
2724 struct sky2_port *sky2 = netdev_priv(dev);
2725 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2726
6c35abae 2727 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2728
a3caeada
SH		 2729 if (status & GM_IS_RX_CO_OV)
2730 gma_read16(hw, port, GM_RX_IRQ_SRC);
2731
2732 if (status & GM_IS_TX_CO_OV)
2733 gma_read16(hw, port, GM_TX_IRQ_SRC);
2734
cd28ab6a 2735 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2736 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2737 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2738 }
2739
2740 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2741 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2742 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2743 }
cd28ab6a
SH		 2744}
2745
40b01727 2746/* This should never happen it is a bug. */
c119731d 2747static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2748{
2749 struct net_device *dev = hw->dev[port];
c119731d 2750 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2751
ada1db5c 2752 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2753 dev->name, (unsigned) q, (unsigned) idx,
2754 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2755
40b01727 2756 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2757}
cd28ab6a 2758
75e80683
SH		 2759static int sky2_rx_hung(struct net_device *dev)
2760{
2761 struct sky2_port *sky2 = netdev_priv(dev);
2762 struct sky2_hw *hw = sky2->hw;
2763 unsigned port = sky2->port;
2764 unsigned rxq = rxqaddr[port];
2765 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2766 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2767 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2768 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2769
2770 /* If idle and MAC or PCI is stuck */
2771 if (sky2->check.last == dev->last_rx &&
2772 ((mac_rp == sky2->check.mac_rp &&
2773 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2774 /* Check if the PCI RX hang */
2775 (fifo_rp == sky2->check.fifo_rp &&
2776 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2777 netdev_printk(KERN_DEBUG, dev,
2778 "hung mac %d:%d fifo %d (%d:%d)\n",
2779 mac_lev, mac_rp, fifo_lev,
2780 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2781 return 1;
2782 } else {
2783 sky2->check.last = dev->last_rx;
2784 sky2->check.mac_rp = mac_rp;
2785 sky2->check.mac_lev = mac_lev;
2786 sky2->check.fifo_rp = fifo_rp;
2787 sky2->check.fifo_lev = fifo_lev;
2788 return 0;
2789 }
2790}
2791
32c2c300 2792static void sky2_watchdog(unsigned long arg)
d27ed387 2793{
01bd7564 2794 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2795
75e80683 2796 /* Check for lost IRQ once a second */
32c2c300 2797 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2798 napi_schedule(&hw->napi);
75e80683
SH		 2799 } else {
2800 int i, active = 0;
2801
2802 for (i = 0; i < hw->ports; i++) {
bea3348e 2803 struct net_device *dev = hw->dev[i];
75e80683
SH		 2804 if (!netif_running(dev))
2805 continue;
2806 ++active;
2807
2808 /* For chips with Rx FIFO, check if stuck */
39dbd958 2809 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2810 sky2_rx_hung(dev)) {
ada1db5c 2811 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2812 schedule_work(&hw->restart_work);
2813 return;
2814 }
2815 }
2816
2817 if (active == 0)
2818 return;
32c2c300 2819 }
01bd7564 2820
75e80683 2821 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2822}
2823
40b01727
SH		 2824/* Hardware/software error handling */
2825static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2826{
40b01727
SH		 2827 if (net_ratelimit())
2828 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2829
1e5f1283
SH		 2830 if (status & Y2_IS_HW_ERR)
2831 sky2_hw_intr(hw);
d257924e 2832
1e5f1283
SH		 2833 if (status & Y2_IS_IRQ_MAC1)
2834 sky2_mac_intr(hw, 0);
cd28ab6a 2835
1e5f1283
SH		 2836 if (status & Y2_IS_IRQ_MAC2)
2837 sky2_mac_intr(hw, 1);
cd28ab6a 2838
1e5f1283 2839 if (status & Y2_IS_CHK_RX1)
c119731d 2840 sky2_le_error(hw, 0, Q_R1);
d257924e 2841
1e5f1283 2842 if (status & Y2_IS_CHK_RX2)
c119731d 2843 sky2_le_error(hw, 1, Q_R2);
d257924e 2844
1e5f1283 2845 if (status & Y2_IS_CHK_TXA1)
c119731d 2846 sky2_le_error(hw, 0, Q_XA1);
d257924e 2847
1e5f1283 2848 if (status & Y2_IS_CHK_TXA2)
c119731d 2849 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2850}
2851
bea3348e 2852static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2853{
bea3348e 2854 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2855 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2856 int work_done = 0;
26691830 2857 u16 idx;
40b01727
SH		 2858
2859 if (unlikely(status & Y2_IS_ERROR))
2860 sky2_err_intr(hw, status);
2861
2862 if (status & Y2_IS_IRQ_PHY1)
2863 sky2_phy_intr(hw, 0);
2864
2865 if (status & Y2_IS_IRQ_PHY2)
2866 sky2_phy_intr(hw, 1);
cd28ab6a 2867
0f5aac70
SH		 2868 if (status & Y2_IS_PHY_QLNK)
2869 sky2_qlink_intr(hw);
2870
26691830
SH		 2871 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2872 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2873
2874 if (work_done >= work_limit)
26691830
SH		 2875 goto done;
2876 }
6f535763 2877
26691830
SH		 2878 napi_complete(napi);
2879 sky2_read32(hw, B0_Y2_SP_LISR);
2880done:
6f535763 2881
bea3348e 2882 return work_done;
e07b1aa8
SH		 2883}
2884
7d12e780 2885static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2886{
2887 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2888 u32 status;
2889
2890 /* Reading this mask interrupts as side effect */
2891 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2892 if (status == 0 || status == ~0)
2893 return IRQ_NONE;
793b883e 2894
e07b1aa8 2895 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2896
2897 napi_schedule(&hw->napi);
793b883e 2898
cd28ab6a
SH		 2899 return IRQ_HANDLED;
2900}
2901
2902#ifdef CONFIG_NET_POLL_CONTROLLER
2903static void sky2_netpoll(struct net_device *dev)
2904{
2905 struct sky2_port *sky2 = netdev_priv(dev);
2906
bea3348e 2907 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2908}
2909#endif
2910
2911/* Chip internal frequency for clock calculations */
05745c4a 2912static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2913{
793b883e 2914 switch (hw->chip_id) {
cd28ab6a 2915 case CHIP_ID_YUKON_EC:
5a5b1ea0 2916 case CHIP_ID_YUKON_EC_U:
93745494 2917 case CHIP_ID_YUKON_EX:
ed4d4161 2918 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2919 case CHIP_ID_YUKON_UL_2:
0f5aac70 2920 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2921 return 125;
2922
cd28ab6a 2923 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2924 return 100;
2925
2926 case CHIP_ID_YUKON_FE_P:
2927 return 50;
2928
2929 case CHIP_ID_YUKON_XL:
2930 return 156;
2931
2932 default:
2933 BUG();
cd28ab6a
SH		 2934 }
2935}
2936
fb17358f 2937static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2938{
fb17358f 2939 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2940}
2941
fb17358f 2942static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2943{
fb17358f 2944 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2945}
2946
fb17358f 2947
e3173832 2948static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2949{
b89165f2 2950 u8 t8;
cd28ab6a 2951
167f53d0 2952 /* Enable all clocks and check for bad PCI access */
b32f40c4 2953 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2954
cd28ab6a 2955 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2956
cd28ab6a 2957 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2958 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2959
2960 switch(hw->chip_id) {
2961 case CHIP_ID_YUKON_XL:
39dbd958 2962 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2963 break;
2964
2965 case CHIP_ID_YUKON_EC_U:
2966 hw->flags = SKY2_HW_GIGABIT
2967 | SKY2_HW_NEWER_PHY
2968 | SKY2_HW_ADV_POWER_CTL;
2969 break;
2970
2971 case CHIP_ID_YUKON_EX:
2972 hw->flags = SKY2_HW_GIGABIT
2973 | SKY2_HW_NEWER_PHY
2974 | SKY2_HW_NEW_LE
2975 | SKY2_HW_ADV_POWER_CTL;
2976
2977 /* New transmit checksum */
2978 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2979 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2980 break;
2981
2982 case CHIP_ID_YUKON_EC:
2983 /* This rev is really old, and requires untested workarounds */
2984 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2985 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2986 return -EOPNOTSUPP;
2987 }
39dbd958 2988 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2989 break;
2990
2991 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2992 break;
2993
05745c4a
SH		 2994 case CHIP_ID_YUKON_FE_P:
2995 hw->flags = SKY2_HW_NEWER_PHY
2996 | SKY2_HW_NEW_LE
2997 | SKY2_HW_AUTO_TX_SUM
2998 | SKY2_HW_ADV_POWER_CTL;
2999 break;
ed4d4161
SH		 3000
3001 case CHIP_ID_YUKON_SUPR:
3002 hw->flags = SKY2_HW_GIGABIT
3003 | SKY2_HW_NEWER_PHY
3004 | SKY2_HW_NEW_LE
3005 | SKY2_HW_AUTO_TX_SUM
3006 | SKY2_HW_ADV_POWER_CTL;
3007 break;
3008
0ce8b98d 3009 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3010 hw->flags = SKY2_HW_GIGABIT
3011 | SKY2_HW_ADV_POWER_CTL;
3012 break;
3013
0f5aac70 3014 case CHIP_ID_YUKON_OPT:
0ce8b98d 3015 hw->flags = SKY2_HW_GIGABIT
b338682d 3016 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3017 | SKY2_HW_ADV_POWER_CTL;
3018 break;
3019
ea76e635 3020 default:
b02a9258
SH		 3021 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3022 hw->chip_id);
cd28ab6a
SH		 3023 return -EOPNOTSUPP;
3024 }
3025
ea76e635
SH		 3026 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3027 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3028 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3029
e3173832
SH		 3030 hw->ports = 1;
3031 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3032 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3033 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3034 ++hw->ports;
3035 }
3036
74a61ebf
MM		 3037 if (sky2_read8(hw, B2_E_0))
3038 hw->flags |= SKY2_HW_RAM_BUFFER;
3039
e3173832
SH		 3040 return 0;
3041}
3042
3043static void sky2_reset(struct sky2_hw *hw)
3044{
555382cb 3045 struct pci_dev *pdev = hw->pdev;
e3173832 3046 u16 status;
555382cb
SH		 3047 int i, cap;
3048 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3049
cd28ab6a 3050 /* disable ASF */
acd12dde 3051 if (hw->chip_id == CHIP_ID_YUKON_EX
3052 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3053 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3054 status = sky2_read16(hw, HCU_CCSR);
3055 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3056 HCU_CCSR_UC_STATE_MSK);
acd12dde 3057 /*
3058 * CPU clock divider shouldn't be used because
3059 * - ASF firmware may malfunction
3060 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3061 */
3062 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3063 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3064 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3065 } else
3066 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3067 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3068
3069 /* do a SW reset */
3070 sky2_write8(hw, B0_CTST, CS_RST_SET);
3071 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3072
ac93a394
SH		 3073 /* allow writes to PCI config */
3074 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3075
cd28ab6a 3076 /* clear PCI errors, if any */
b32f40c4 3077 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3078 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3079 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3080
3081 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3082
555382cb
SH		 3083 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3084 if (cap) {
7782c8c4
SH		 3085 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3086 0xfffffffful);
555382cb
SH		 3087
3088 /* If error bit is stuck on ignore it */
3089 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3090 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3091 else
555382cb
SH		 3092 hwe_mask |= Y2_IS_PCI_EXP;
3093 }
cd28ab6a 3094
ae306cca 3095 sky2_power_on(hw);
a40ccc68 3096 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3097
3098 for (i = 0; i < hw->ports; i++) {
3099 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3100 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3101
ed4d4161
SH		 3102 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3103 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3104 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3105 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3106 | GMC_BYP_RETR_ON);
877c8570
SH		 3107
3108 }
3109
3110 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3111 /* enable MACSec clock gating */
3112 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3113 }
3114
0f5aac70
SH		 3115 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3116 u16 reg;
3117 u32 msk;
3118
3119 if (hw->chip_rev == 0) {
3120 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3121 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3122
3123 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3124 reg = 10;
3125 } else {
3126 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3127 reg = 3;
3128 }
3129
3130 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3131
3132 /* reset PHY Link Detect */
a40ccc68 3133 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3134 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3135 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3136 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3137
3138
3139 /* enable PHY Quick Link */
3140 msk = sky2_read32(hw, B0_IMSK);
3141 msk |= Y2_IS_PHY_QLNK;
3142 sky2_write32(hw, B0_IMSK, msk);
3143
3144 /* check if PSMv2 was running before */
3145 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3146 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3147 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3148 /* restore the PCIe Link Control register */
3149 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3150 }
a40ccc68 3151 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3152
3153 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3154 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3155 }
3156
793b883e
SH		 3157 /* Clear I2C IRQ noise */
3158 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3159
3160 /* turn off hardware timer (unused) */
3161 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3162 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3163
69634ee7
SH		 3164 /* Turn off descriptor polling */
3165 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3166
3167 /* Turn off receive timestamp */
3168 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3169 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3170
3171 /* enable the Tx Arbiters */
3172 for (i = 0; i < hw->ports; i++)
3173 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3174
3175 /* Initialize ram interface */
3176 for (i = 0; i < hw->ports; i++) {
793b883e 3177 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3178
3179 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3180 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3181 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3182 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3183 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3184 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3185 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3186 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3187 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3188 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3189 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3190 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3191 }
3192
555382cb 3193 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3194
cd28ab6a 3195 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3196 sky2_gmac_reset(hw, i);
cd28ab6a 3197
efe91932 3198 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3199 hw->st_idx = 0;
3200
3201 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3202 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3203
3204 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3205 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3206
3207 /* Set the list last index */
efe91932 3208 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3209
290d4de5
SH		 3210 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3211 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3212
290d4de5
SH		 3213 /* set Status-FIFO ISR watermark */
3214 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3215 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3216 else
3217 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3218
290d4de5 3219 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3220 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3221 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3222
793b883e 3223 /* enable status unit */
cd28ab6a
SH		 3224 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3225
3226 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3227 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3228 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3229}
3230
af18d8b8
SH		 3231/* Take device down (offline).
3232 * Equivalent to doing dev_stop() but this does not
3233 * inform upper layers of the transistion.
3234 */
3235static void sky2_detach(struct net_device *dev)
3236{
3237 if (netif_running(dev)) {
c36531b9 3238 netif_tx_lock(dev);
af18d8b8 3239 netif_device_detach(dev); /* stop txq */
c36531b9 3240 netif_tx_unlock(dev);
af18d8b8
SH		 3241 sky2_down(dev);
3242 }
3243}
3244
3245/* Bring device back after doing sky2_detach */
3246static int sky2_reattach(struct net_device *dev)
3247{
3248 int err = 0;
3249
3250 if (netif_running(dev)) {
3251 err = sky2_up(dev);
3252 if (err) {
ada1db5c 3253 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3254 dev_close(dev);
3255 } else {
3256 netif_device_attach(dev);
3257 sky2_set_multicast(dev);
3258 }
3259 }
3260
3261 return err;
3262}
3263
81906791
SH		 3264static void sky2_restart(struct work_struct *work)
3265{
3266 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3267 u32 imask;
af18d8b8 3268 int i;
81906791 3269
81906791 3270 rtnl_lock();
81906791 3271
8cfcbe99 3272 napi_disable(&hw->napi);
8a0c9228
MM		 3273 synchronize_irq(hw->pdev->irq);
3274 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3275 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3276
3277 for (i = 0; i < hw->ports; i++) {
3278 struct net_device *dev = hw->dev[i];
3279 struct sky2_port *sky2 = netdev_priv(dev);
3280
3281 if (!netif_running(dev))
3282 continue;
3283
3284 netif_carrier_off(dev);
3285 netif_tx_disable(dev);
3286 sky2_hw_down(sky2);
3287 }
3288
81906791 3289 sky2_reset(hw);
81906791 3290
8a0c9228
MM		 3291 for (i = 0; i < hw->ports; i++) {
3292 struct net_device *dev = hw->dev[i];
3293 struct sky2_port *sky2 = netdev_priv(dev);
3294
3295 if (!netif_running(dev))
3296 continue;
3297
3298 sky2_hw_up(sky2);
3299 netif_wake_queue(dev);
3300 }
3301
3302 sky2_write32(hw, B0_IMSK, imask);
3303 sky2_read32(hw, B0_IMSK);
3304
3305 sky2_read32(hw, B0_Y2_SP_LISR);
3306 napi_enable(&hw->napi);
81906791 3307
81906791
SH		 3308 rtnl_unlock();
3309}
3310
e3173832
SH		 3311static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3312{
3313 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3314}
3315
3316static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3317{
3318 const struct sky2_port *sky2 = netdev_priv(dev);
3319
3320 wol->supported = sky2_wol_supported(sky2->hw);
3321 wol->wolopts = sky2->wol;
3322}
3323
3324static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3325{
3326 struct sky2_port *sky2 = netdev_priv(dev);
3327 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3328
8e95a202
JP		 3329 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3330 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3331 return -EOPNOTSUPP;
3332
3333 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3334 return 0;
3335}
3336
28bd181a 3337static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3338{
b89165f2
SH		 3339 if (sky2_is_copper(hw)) {
3340 u32 modes = SUPPORTED_10baseT_Half
3341 | SUPPORTED_10baseT_Full
3342 | SUPPORTED_100baseT_Half
3343 | SUPPORTED_100baseT_Full
3344 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3345
ea76e635 3346 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3347 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3348 | SUPPORTED_1000baseT_Full;
3349 return modes;
cd28ab6a 3350 } else
b89165f2
SH		 3351 return SUPPORTED_1000baseT_Half
3352 | SUPPORTED_1000baseT_Full
3353 | SUPPORTED_Autoneg
3354 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3355}
3356
793b883e 3357static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3358{
3359 struct sky2_port *sky2 = netdev_priv(dev);
3360 struct sky2_hw *hw = sky2->hw;
3361
3362 ecmd->transceiver = XCVR_INTERNAL;
3363 ecmd->supported = sky2_supported_modes(hw);
3364 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3365 if (sky2_is_copper(hw)) {
cd28ab6a 3366 ecmd->port = PORT_TP;
b89165f2
SH		 3367 ecmd->speed = sky2->speed;
3368 } else {
3369 ecmd->speed = SPEED_1000;
cd28ab6a 3370 ecmd->port = PORT_FIBRE;
b89165f2 3371 }
cd28ab6a
SH		 3372
3373 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3374 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3375 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3376 ecmd->duplex = sky2->duplex;
3377 return 0;
3378}
3379
3380static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3381{
3382 struct sky2_port *sky2 = netdev_priv(dev);
3383 const struct sky2_hw *hw = sky2->hw;
3384 u32 supported = sky2_supported_modes(hw);
3385
3386 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3387 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3388 ecmd->advertising = supported;
3389 sky2->duplex = -1;
3390 sky2->speed = -1;
3391 } else {
3392 u32 setting;
3393
793b883e 3394 switch (ecmd->speed) {
cd28ab6a
SH		 3395 case SPEED_1000:
3396 if (ecmd->duplex == DUPLEX_FULL)
3397 setting = SUPPORTED_1000baseT_Full;
3398 else if (ecmd->duplex == DUPLEX_HALF)
3399 setting = SUPPORTED_1000baseT_Half;
3400 else
3401 return -EINVAL;
3402 break;
3403 case SPEED_100:
3404 if (ecmd->duplex == DUPLEX_FULL)
3405 setting = SUPPORTED_100baseT_Full;
3406 else if (ecmd->duplex == DUPLEX_HALF)
3407 setting = SUPPORTED_100baseT_Half;
3408 else
3409 return -EINVAL;
3410 break;
3411
3412 case SPEED_10:
3413 if (ecmd->duplex == DUPLEX_FULL)
3414 setting = SUPPORTED_10baseT_Full;
3415 else if (ecmd->duplex == DUPLEX_HALF)
3416 setting = SUPPORTED_10baseT_Half;
3417 else
3418 return -EINVAL;
3419 break;
3420 default:
3421 return -EINVAL;
3422 }
3423
3424 if ((setting & supported) == 0)
3425 return -EINVAL;
3426
3427 sky2->speed = ecmd->speed;
3428 sky2->duplex = ecmd->duplex;
0ea065e5 3429 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3430 }
3431
cd28ab6a
SH		 3432 sky2->advertising = ecmd->advertising;
3433
d1b139c0 3434 if (netif_running(dev)) {
1b537565 3435 sky2_phy_reinit(sky2);
d1b139c0
SH		 3436 sky2_set_multicast(dev);
3437 }
cd28ab6a
SH		 3438
3439 return 0;
3440}
3441
3442static void sky2_get_drvinfo(struct net_device *dev,
3443 struct ethtool_drvinfo *info)
3444{
3445 struct sky2_port *sky2 = netdev_priv(dev);
3446
3447 strcpy(info->driver, DRV_NAME);
3448 strcpy(info->version, DRV_VERSION);
3449 strcpy(info->fw_version, "N/A");
3450 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3451}
3452
3453static const struct sky2_stat {
793b883e
SH		 3454 char name[ETH_GSTRING_LEN];
3455 u16 offset;
cd28ab6a
SH		 3456} sky2_stats[] = {
3457 { "tx_bytes", GM_TXO_OK_HI },
3458 { "rx_bytes", GM_RXO_OK_HI },
3459 { "tx_broadcast", GM_TXF_BC_OK },
3460 { "rx_broadcast", GM_RXF_BC_OK },
3461 { "tx_multicast", GM_TXF_MC_OK },
3462 { "rx_multicast", GM_RXF_MC_OK },
3463 { "tx_unicast", GM_TXF_UC_OK },
3464 { "rx_unicast", GM_RXF_UC_OK },
3465 { "tx_mac_pause", GM_TXF_MPAUSE },
3466 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3467 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3468 { "late_collision",GM_TXF_LAT_COL },
3469 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3470 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3471 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3472
d2604540 3473 { "rx_short", GM_RXF_SHT },
cd28ab6a 3474 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3475 { "rx_64_byte_packets", GM_RXF_64B },
3476 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3477 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3478 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3479 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3480 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3481 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3482 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3483 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3484 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3485 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3486
3487 { "tx_64_byte_packets", GM_TXF_64B },
3488 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3489 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3490 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3491 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3492 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3493 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3494 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3495};
3496
cd28ab6a
SH		 3497static u32 sky2_get_rx_csum(struct net_device *dev)
3498{
3499 struct sky2_port *sky2 = netdev_priv(dev);
3500
0ea065e5 3501 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3502}
3503
3504static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3505{
3506 struct sky2_port *sky2 = netdev_priv(dev);
3507
0ea065e5
SH		 3508 if (data)
3509 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3510 else
3511 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3512
cd28ab6a
SH		 3513 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3514 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3515
3516 return 0;
3517}
3518
3519static u32 sky2_get_msglevel(struct net_device *netdev)
3520{
3521 struct sky2_port *sky2 = netdev_priv(netdev);
3522 return sky2->msg_enable;
3523}
3524
9a7ae0a9
SH		 3525static int sky2_nway_reset(struct net_device *dev)
3526{
3527 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3528
0ea065e5 3529 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3530 return -EINVAL;
3531
1b537565 3532 sky2_phy_reinit(sky2);
d1b139c0 3533 sky2_set_multicast(dev);
9a7ae0a9
SH		 3534
3535 return 0;
3536}
3537
793b883e 3538static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3539{
3540 struct sky2_hw *hw = sky2->hw;
3541 unsigned port = sky2->port;
3542 int i;
3543
3544 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3545 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3546 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3547 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3548
793b883e 3549 for (i = 2; i < count; i++)
cd28ab6a
SH		 3550 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3551}
3552
cd28ab6a
SH		 3553static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3554{
3555 struct sky2_port *sky2 = netdev_priv(netdev);
3556 sky2->msg_enable = value;
3557}
3558
b9f2c044 3559static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3560{
b9f2c044
JG		 3561 switch (sset) {
3562 case ETH_SS_STATS:
3563 return ARRAY_SIZE(sky2_stats);
3564 default:
3565 return -EOPNOTSUPP;
3566 }
cd28ab6a
SH		 3567}
3568
3569static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3570 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3571{
3572 struct sky2_port *sky2 = netdev_priv(dev);
3573
793b883e 3574 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3575}
3576
793b883e 3577static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3578{
3579 int i;
3580
3581 switch (stringset) {
3582 case ETH_SS_STATS:
3583 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3584 memcpy(data + i * ETH_GSTRING_LEN,
3585 sky2_stats[i].name, ETH_GSTRING_LEN);
3586 break;
3587 }
3588}
3589
cd28ab6a
SH		 3590static int sky2_set_mac_address(struct net_device *dev, void *p)
3591{
3592 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3593 struct sky2_hw *hw = sky2->hw;
3594 unsigned port = sky2->port;
3595 const struct sockaddr *addr = p;
cd28ab6a
SH		 3596
3597 if (!is_valid_ether_addr(addr->sa_data))
3598 return -EADDRNOTAVAIL;
3599
cd28ab6a 3600 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3601 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3602 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3603 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3604 dev->dev_addr, ETH_ALEN);
1b537565 3605
a8ab1ec0
SH		 3606 /* virtual address for data */
3607 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3608
3609 /* physical address: used for pause frames */
3610 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3611
3612 return 0;
cd28ab6a
SH		 3613}
3614
a052b52f
SH		 3615static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3616{
3617 u32 bit;
3618
3619 bit = ether_crc(ETH_ALEN, addr) & 63;
3620 filter[bit >> 3] |= 1 << (bit & 7);
3621}
3622
cd28ab6a
SH		 3623static void sky2_set_multicast(struct net_device *dev)
3624{
3625 struct sky2_port *sky2 = netdev_priv(dev);
3626 struct sky2_hw *hw = sky2->hw;
3627 unsigned port = sky2->port;
22bedad3 3628 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3629 u16 reg;
3630 u8 filter[8];
a052b52f
SH		 3631 int rx_pause;
3632 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3633
a052b52f 3634 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3635 memset(filter, 0, sizeof(filter));
3636
3637 reg = gma_read16(hw, port, GM_RX_CTRL);
3638 reg |= GM_RXCR_UCF_ENA;
3639
d571b694 3640 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3641 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3642 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3643 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3644 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3645 reg &= ~GM_RXCR_MCF_ENA;
3646 else {
cd28ab6a
SH		 3647 reg |= GM_RXCR_MCF_ENA;
3648
a052b52f
SH		 3649 if (rx_pause)
3650 sky2_add_filter(filter, pause_mc_addr);
3651
22bedad3
JP		 3652 netdev_for_each_mc_addr(ha, dev)
3653 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3654 }
3655
cd28ab6a 3656 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3657 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3658 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3659 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3660 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3661 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3662 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3663 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3664
3665 gma_write16(hw, port, GM_RX_CTRL, reg);
3666}
3667
3668/* Can have one global because blinking is controlled by
3669 * ethtool and that is always under RTNL mutex
3670 */
a84d0a3d 3671static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3672{
a84d0a3d
SH		 3673 struct sky2_hw *hw = sky2->hw;
3674 unsigned port = sky2->port;
793b883e 3675
a84d0a3d
SH		 3676 spin_lock_bh(&sky2->phy_lock);
3677 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3678 hw->chip_id == CHIP_ID_YUKON_EX ||
3679 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3680 u16 pg;
793b883e
SH		 3681 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3682 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3683
a84d0a3d
SH		 3684 switch (mode) {
3685 case MO_LED_OFF:
3686 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3687 PHY_M_LEDC_LOS_CTRL(8) |
3688 PHY_M_LEDC_INIT_CTRL(8) |
3689 PHY_M_LEDC_STA1_CTRL(8) |
3690 PHY_M_LEDC_STA0_CTRL(8));
3691 break;
3692 case MO_LED_ON:
3693 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3694 PHY_M_LEDC_LOS_CTRL(9) |
3695 PHY_M_LEDC_INIT_CTRL(9) |
3696 PHY_M_LEDC_STA1_CTRL(9) |
3697 PHY_M_LEDC_STA0_CTRL(9));
3698 break;
3699 case MO_LED_BLINK:
3700 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3701 PHY_M_LEDC_LOS_CTRL(0xa) |
3702 PHY_M_LEDC_INIT_CTRL(0xa) |
3703 PHY_M_LEDC_STA1_CTRL(0xa) |
3704 PHY_M_LEDC_STA0_CTRL(0xa));
3705 break;
3706 case MO_LED_NORM:
3707 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3708 PHY_M_LEDC_LOS_CTRL(1) |
3709 PHY_M_LEDC_INIT_CTRL(8) |
3710 PHY_M_LEDC_STA1_CTRL(7) |
3711 PHY_M_LEDC_STA0_CTRL(7));
3712 }
793b883e 3713
a84d0a3d
SH		 3714 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3715 } else
7d2e3cb7 3716 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3717 PHY_M_LED_MO_DUP(mode) |
3718 PHY_M_LED_MO_10(mode) |
3719 PHY_M_LED_MO_100(mode) |
3720 PHY_M_LED_MO_1000(mode) |
3721 PHY_M_LED_MO_RX(mode) |
3722 PHY_M_LED_MO_TX(mode));
3723
3724 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3725}
3726
3727/* blink LED's for finding board */
3728static int sky2_phys_id(struct net_device *dev, u32 data)
3729{
3730 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3731 unsigned int i;
cd28ab6a 3732
a84d0a3d
SH		 3733 if (data == 0)
3734 data = UINT_MAX;
cd28ab6a 3735
a84d0a3d
SH		 3736 for (i = 0; i < data; i++) {
3737 sky2_led(sky2, MO_LED_ON);
3738 if (msleep_interruptible(500))
3739 break;
3740 sky2_led(sky2, MO_LED_OFF);
3741 if (msleep_interruptible(500))
3742 break;
793b883e 3743 }
a84d0a3d 3744 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3745
3746 return 0;
3747}
3748
3749static void sky2_get_pauseparam(struct net_device *dev,
3750 struct ethtool_pauseparam *ecmd)
3751{
3752 struct sky2_port *sky2 = netdev_priv(dev);
3753
16ad91e1
SH		 3754 switch (sky2->flow_mode) {
3755 case FC_NONE:
3756 ecmd->tx_pause = ecmd->rx_pause = 0;
3757 break;
3758 case FC_TX:
3759 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3760 break;
3761 case FC_RX:
3762 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3763 break;
3764 case FC_BOTH:
3765 ecmd->tx_pause = ecmd->rx_pause = 1;
3766 }
3767
0ea065e5
SH		 3768 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3769 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3770}
3771
3772static int sky2_set_pauseparam(struct net_device *dev,
3773 struct ethtool_pauseparam *ecmd)
3774{
3775 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3776
0ea065e5
SH		 3777 if (ecmd->autoneg == AUTONEG_ENABLE)
3778 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3779 else
3780 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3781
16ad91e1 3782 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3783
16ad91e1
SH		 3784 if (netif_running(dev))
3785 sky2_phy_reinit(sky2);
cd28ab6a 3786
2eaba1a2 3787 return 0;
cd28ab6a
SH		 3788}
3789
fb17358f
SH		 3790static int sky2_get_coalesce(struct net_device *dev,
3791 struct ethtool_coalesce *ecmd)
3792{
3793 struct sky2_port *sky2 = netdev_priv(dev);
3794 struct sky2_hw *hw = sky2->hw;
3795
3796 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3797 ecmd->tx_coalesce_usecs = 0;
3798 else {
3799 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3800 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3801 }
3802 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3803
3804 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3805 ecmd->rx_coalesce_usecs = 0;
3806 else {
3807 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3808 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3809 }
3810 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3811
3812 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3813 ecmd->rx_coalesce_usecs_irq = 0;
3814 else {
3815 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3816 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3817 }
3818
3819 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3820
3821 return 0;
3822}
3823
3824/* Note: this affect both ports */
3825static int sky2_set_coalesce(struct net_device *dev,
3826 struct ethtool_coalesce *ecmd)
3827{
3828 struct sky2_port *sky2 = netdev_priv(dev);
3829 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3830 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3831
77b3d6a2
SH		 3832 if (ecmd->tx_coalesce_usecs > tmax ||
3833 ecmd->rx_coalesce_usecs > tmax ||
3834 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3835 return -EINVAL;
3836
ee5f68fe 3837 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3838 return -EINVAL;
ff81fbbe 3839 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3840 return -EINVAL;
ff81fbbe 3841 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3842 return -EINVAL;
3843
3844 if (ecmd->tx_coalesce_usecs == 0)
3845 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3846 else {
3847 sky2_write32(hw, STAT_TX_TIMER_INI,
3848 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3849 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3850 }
3851 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3852
3853 if (ecmd->rx_coalesce_usecs == 0)
3854 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3855 else {
3856 sky2_write32(hw, STAT_LEV_TIMER_INI,
3857 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3858 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3859 }
3860 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3861
3862 if (ecmd->rx_coalesce_usecs_irq == 0)
3863 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3864 else {
d28d4870 3865 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3866 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3867 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3868 }
3869 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3870 return 0;
3871}
3872
793b883e
SH		 3873static void sky2_get_ringparam(struct net_device *dev,
3874 struct ethtool_ringparam *ering)
3875{
3876 struct sky2_port *sky2 = netdev_priv(dev);
3877
3878 ering->rx_max_pending = RX_MAX_PENDING;
3879 ering->rx_mini_max_pending = 0;
3880 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3881 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3882
3883 ering->rx_pending = sky2->rx_pending;
3884 ering->rx_mini_pending = 0;
3885 ering->rx_jumbo_pending = 0;
3886 ering->tx_pending = sky2->tx_pending;
3887}
3888
3889static int sky2_set_ringparam(struct net_device *dev,
3890 struct ethtool_ringparam *ering)
3891{
3892 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3893
3894 if (ering->rx_pending > RX_MAX_PENDING ||
3895 ering->rx_pending < 8 ||
ee5f68fe
SH		 3896 ering->tx_pending < TX_MIN_PENDING ||
3897 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3898 return -EINVAL;
3899
af18d8b8 3900 sky2_detach(dev);
793b883e
SH		 3901
3902 sky2->rx_pending = ering->rx_pending;
3903 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3904 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3905
af18d8b8 3906 return sky2_reattach(dev);
793b883e
SH		 3907}
3908
793b883e
SH		 3909static int sky2_get_regs_len(struct net_device *dev)
3910{
6e4cbb34 3911 return 0x4000;
793b883e
SH		 3912}
3913
c32bbff8
MM		 3914static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3915{
3916 /* This complicated switch statement is to make sure and
3917 * only access regions that are unreserved.
3918 * Some blocks are only valid on dual port cards.
3919 */
3920 switch (b) {
3921 /* second port */
3922 case 5: /* Tx Arbiter 2 */
3923 case 9: /* RX2 */
3924 case 14 ... 15: /* TX2 */
3925 case 17: case 19: /* Ram Buffer 2 */
3926 case 22 ... 23: /* Tx Ram Buffer 2 */
3927 case 25: /* Rx MAC Fifo 1 */
3928 case 27: /* Tx MAC Fifo 2 */
3929 case 31: /* GPHY 2 */
3930 case 40 ... 47: /* Pattern Ram 2 */
3931 case 52: case 54: /* TCP Segmentation 2 */
3932 case 112 ... 116: /* GMAC 2 */
3933 return hw->ports > 1;
3934
3935 case 0: /* Control */
3936 case 2: /* Mac address */
3937 case 4: /* Tx Arbiter 1 */
3938 case 7: /* PCI express reg */
3939 case 8: /* RX1 */
3940 case 12 ... 13: /* TX1 */
3941 case 16: case 18:/* Rx Ram Buffer 1 */
3942 case 20 ... 21: /* Tx Ram Buffer 1 */
3943 case 24: /* Rx MAC Fifo 1 */
3944 case 26: /* Tx MAC Fifo 1 */
3945 case 28 ... 29: /* Descriptor and status unit */
3946 case 30: /* GPHY 1*/
3947 case 32 ... 39: /* Pattern Ram 1 */
3948 case 48: case 50: /* TCP Segmentation 1 */
3949 case 56 ... 60: /* PCI space */
3950 case 80 ... 84: /* GMAC 1 */
3951 return 1;
3952
3953 default:
3954 return 0;
3955 }
3956}
3957
793b883e
SH		 3958/*
3959 * Returns copy of control register region
3ead5db7 3960 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3961 */
3962static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3963 void *p)
3964{
3965 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3966 const void __iomem *io = sky2->hw->regs;
295b54c4 3967 unsigned int b;
793b883e
SH		 3968
3969 regs->version = 1;
793b883e 3970
295b54c4 3971 for (b = 0; b < 128; b++) {
c32bbff8
MM		 3972 /* skip poisonous diagnostic ram region in block 3 */
3973 if (b == 3)
295b54c4 3974 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 3975 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 3976 memcpy_fromio(p, io, 128);
c32bbff8 3977 else
295b54c4 3978 memset(p, 0, 128);
3ead5db7 3979
295b54c4
SH		 3980 p += 128;
3981 io += 128;
3982 }
793b883e 3983}
cd28ab6a 3984
b628ed98
SH		 3985/* In order to do Jumbo packets on these chips, need to turn off the
3986 * transmit store/forward. Therefore checksum offload won't work.
3987 */
3988static int no_tx_offload(struct net_device *dev)
3989{
3990 const struct sky2_port *sky2 = netdev_priv(dev);
3991 const struct sky2_hw *hw = sky2->hw;
3992
69161611 3993 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3994}
3995
3996static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3997{
3998 if (data && no_tx_offload(dev))
3999 return -EINVAL;
4000
4001 return ethtool_op_set_tx_csum(dev, data);
4002}
4003
4004
4005static int sky2_set_tso(struct net_device *dev, u32 data)
4006{
4007 if (data && no_tx_offload(dev))
4008 return -EINVAL;
4009
4010 return ethtool_op_set_tso(dev, data);
4011}
4012
f4331a6d
SH		 4013static int sky2_get_eeprom_len(struct net_device *dev)
4014{
4015 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4016 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4017 u16 reg2;
4018
b32f40c4 4019 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4020 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4021}
4022
1413235c 4023static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4024{
1413235c 4025 unsigned long start = jiffies;
f4331a6d 4026
1413235c
SH		 4027 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4028 /* Can take up to 10.6 ms for write */
4029 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4030 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4031 return -ETIMEDOUT;
4032 }
4033 mdelay(1);
4034 }
167f53d0 4035
1413235c
SH		 4036 return 0;
4037}
167f53d0 4038
1413235c
SH		 4039static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4040 u16 offset, size_t length)
4041{
4042 int rc = 0;
4043
4044 while (length > 0) {
4045 u32 val;
4046
4047 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4048 rc = sky2_vpd_wait(hw, cap, 0);
4049 if (rc)
4050 break;
4051
4052 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4053
4054 memcpy(data, &val, min(sizeof(val), length));
4055 offset += sizeof(u32);
4056 data += sizeof(u32);
4057 length -= sizeof(u32);
4058 }
4059
4060 return rc;
f4331a6d
SH		 4061}
4062
1413235c
SH		 4063static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4064 u16 offset, unsigned int length)
f4331a6d 4065{
1413235c
SH		 4066 unsigned int i;
4067 int rc = 0;
4068
4069 for (i = 0; i < length; i += sizeof(u32)) {
4070 u32 val = *(u32 *)(data + i);
4071
4072 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4073 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4074
4075 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4076 if (rc)
4077 break;
4078 }
4079 return rc;
f4331a6d
SH		 4080}
4081
4082static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4083 u8 *data)
4084{
4085 struct sky2_port *sky2 = netdev_priv(dev);
4086 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4087
4088 if (!cap)
4089 return -EINVAL;
4090
4091 eeprom->magic = SKY2_EEPROM_MAGIC;
4092
1413235c 4093 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4094}
4095
4096static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4097 u8 *data)
4098{
4099 struct sky2_port *sky2 = netdev_priv(dev);
4100 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4101
4102 if (!cap)
4103 return -EINVAL;
4104
4105 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4106 return -EINVAL;
4107
1413235c
SH		 4108 /* Partial writes not supported */
4109 if ((eeprom->offset & 3) || (eeprom->len & 3))
4110 return -EINVAL;
f4331a6d 4111
1413235c 4112 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4113}
4114
4115
7282d491 4116static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4117 .get_settings = sky2_get_settings,
4118 .set_settings = sky2_set_settings,
4119 .get_drvinfo = sky2_get_drvinfo,
4120 .get_wol = sky2_get_wol,
4121 .set_wol = sky2_set_wol,
4122 .get_msglevel = sky2_get_msglevel,
4123 .set_msglevel = sky2_set_msglevel,
4124 .nway_reset = sky2_nway_reset,
4125 .get_regs_len = sky2_get_regs_len,
4126 .get_regs = sky2_get_regs,
4127 .get_link = ethtool_op_get_link,
4128 .get_eeprom_len = sky2_get_eeprom_len,
4129 .get_eeprom = sky2_get_eeprom,
4130 .set_eeprom = sky2_set_eeprom,
f4331a6d 4131 .set_sg = ethtool_op_set_sg,
f4331a6d 4132 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4133 .set_tso = sky2_set_tso,
4134 .get_rx_csum = sky2_get_rx_csum,
4135 .set_rx_csum = sky2_set_rx_csum,
4136 .get_strings = sky2_get_strings,
4137 .get_coalesce = sky2_get_coalesce,
4138 .set_coalesce = sky2_set_coalesce,
4139 .get_ringparam = sky2_get_ringparam,
4140 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4141 .get_pauseparam = sky2_get_pauseparam,
4142 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4143 .phys_id = sky2_phys_id,
b9f2c044 4144 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4145 .get_ethtool_stats = sky2_get_ethtool_stats,
4146};
4147
3cf26753
SH		 4148#ifdef CONFIG_SKY2_DEBUG
4149
4150static struct dentry *sky2_debug;
4151
e4c2abe2
SH		 4152
4153/*
4154 * Read and parse the first part of Vital Product Data
4155 */
4156#define VPD_SIZE 128
4157#define VPD_MAGIC 0x82
4158
4159static const struct vpd_tag {
4160 char tag[2];
4161 char *label;
4162} vpd_tags[] = {
4163 { "PN", "Part Number" },
4164 { "EC", "Engineering Level" },
4165 { "MN", "Manufacturer" },
4166 { "SN", "Serial Number" },
4167 { "YA", "Asset Tag" },
4168 { "VL", "First Error Log Message" },
4169 { "VF", "Second Error Log Message" },
4170 { "VB", "Boot Agent ROM Configuration" },
4171 { "VE", "EFI UNDI Configuration" },
4172};
4173
4174static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4175{
4176 size_t vpd_size;
4177 loff_t offs;
4178 u8 len;
4179 unsigned char *buf;
4180 u16 reg2;
4181
4182 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4183 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4184
4185 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4186 buf = kmalloc(vpd_size, GFP_KERNEL);
4187 if (!buf) {
4188 seq_puts(seq, "no memory!\n");
4189 return;
4190 }
4191
4192 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4193 seq_puts(seq, "VPD read failed\n");
4194 goto out;
4195 }
4196
4197 if (buf[0] != VPD_MAGIC) {
4198 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4199 goto out;
4200 }
4201 len = buf[1];
4202 if (len == 0 || len > vpd_size - 4) {
4203 seq_printf(seq, "Invalid id length: %d\n", len);
4204 goto out;
4205 }
4206
4207 seq_printf(seq, "%.*s\n", len, buf + 3);
4208 offs = len + 3;
4209
4210 while (offs < vpd_size - 4) {
4211 int i;
4212
4213 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4214 break;
4215 len = buf[offs + 2];
4216 if (offs + len + 3 >= vpd_size)
4217 break;
4218
4219 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4220 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4221 seq_printf(seq, " %s: %.*s\n",
4222 vpd_tags[i].label, len, buf + offs + 3);
4223 break;
4224 }
4225 }
4226 offs += len + 3;
4227 }
4228out:
4229 kfree(buf);
4230}
4231
3cf26753
SH		 4232static int sky2_debug_show(struct seq_file *seq, void *v)
4233{
4234 struct net_device *dev = seq->private;
4235 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4236 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4237 unsigned port = sky2->port;
4238 unsigned idx, last;
4239 int sop;
4240
e4c2abe2 4241 sky2_show_vpd(seq, hw);
3cf26753 4242
e4c2abe2 4243 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4244 sky2_read32(hw, B0_ISRC),
4245 sky2_read32(hw, B0_IMSK),
4246 sky2_read32(hw, B0_Y2_SP_ICR));
4247
e4c2abe2
SH		 4248 if (!netif_running(dev)) {
4249 seq_printf(seq, "network not running\n");
4250 return 0;
4251 }
4252
bea3348e 4253 napi_disable(&hw->napi);
3cf26753
SH		 4254 last = sky2_read16(hw, STAT_PUT_IDX);
4255
efe91932 4256 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4257 if (hw->st_idx == last)
4258 seq_puts(seq, "Status ring (empty)\n");
4259 else {
4260 seq_puts(seq, "Status ring\n");
efe91932 4261 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4262 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4263 const struct sky2_status_le *le = hw->st_le + idx;
4264 seq_printf(seq, "[%d] %#x %d %#x\n",
4265 idx, le->opcode, le->length, le->status);
4266 }
4267 seq_puts(seq, "\n");
4268 }
4269
4270 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4271 sky2->tx_cons, sky2->tx_prod,
4272 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4273 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4274
4275 /* Dump contents of tx ring */
4276 sop = 1;
ee5f68fe
SH		 4277 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4278 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4279 const struct sky2_tx_le *le = sky2->tx_le + idx;
4280 u32 a = le32_to_cpu(le->addr);
4281
4282 if (sop)
4283 seq_printf(seq, "%u:", idx);
4284 sop = 0;
4285
4286 switch(le->opcode & ~HW_OWNER) {
4287 case OP_ADDR64:
4288 seq_printf(seq, " %#x:", a);
4289 break;
4290 case OP_LRGLEN:
4291 seq_printf(seq, " mtu=%d", a);
4292 break;
4293 case OP_VLAN:
4294 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4295 break;
4296 case OP_TCPLISW:
4297 seq_printf(seq, " csum=%#x", a);
4298 break;
4299 case OP_LARGESEND:
4300 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4301 break;
4302 case OP_PACKET:
4303 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4304 break;
4305 case OP_BUFFER:
4306 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4307 break;
4308 default:
4309 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4310 a, le16_to_cpu(le->length));
4311 }
4312
4313 if (le->ctrl & EOP) {
4314 seq_putc(seq, '\n');
4315 sop = 1;
4316 }
4317 }
4318
4319 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4320 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4321 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4322 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4323
d1d08d12 4324 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4325 napi_enable(&hw->napi);
3cf26753
SH		 4326 return 0;
4327}
4328
4329static int sky2_debug_open(struct inode *inode, struct file *file)
4330{
4331 return single_open(file, sky2_debug_show, inode->i_private);
4332}
4333
4334static const struct file_operations sky2_debug_fops = {
4335 .owner = THIS_MODULE,
4336 .open = sky2_debug_open,
4337 .read = seq_read,
4338 .llseek = seq_lseek,
4339 .release = single_release,
4340};
4341
4342/*
4343 * Use network device events to create/remove/rename
4344 * debugfs file entries
4345 */
4346static int sky2_device_event(struct notifier_block *unused,
4347 unsigned long event, void *ptr)
4348{
4349 struct net_device *dev = ptr;
5b296bc9 4350 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4351
1436b301 4352 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4353 return NOTIFY_DONE;
3cf26753 4354
5b296bc9
SH		 4355 switch(event) {
4356 case NETDEV_CHANGENAME:
4357 if (sky2->debugfs) {
4358 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4359 sky2_debug, dev->name);
4360 }
4361 break;
3cf26753 4362
5b296bc9
SH		 4363 case NETDEV_GOING_DOWN:
4364 if (sky2->debugfs) {
ada1db5c 4365 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4366 debugfs_remove(sky2->debugfs);
4367 sky2->debugfs = NULL;
3cf26753 4368 }
5b296bc9
SH		 4369 break;
4370
4371 case NETDEV_UP:
4372 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4373 sky2_debug, dev,
4374 &sky2_debug_fops);
4375 if (IS_ERR(sky2->debugfs))
4376 sky2->debugfs = NULL;
3cf26753
SH		 4377 }
4378
4379 return NOTIFY_DONE;
4380}
4381
4382static struct notifier_block sky2_notifier = {
4383 .notifier_call = sky2_device_event,
4384};
4385
4386
4387static __init void sky2_debug_init(void)
4388{
4389 struct dentry *ent;
4390
4391 ent = debugfs_create_dir("sky2", NULL);
4392 if (!ent || IS_ERR(ent))
4393 return;
4394
4395 sky2_debug = ent;
4396 register_netdevice_notifier(&sky2_notifier);
4397}
4398
4399static __exit void sky2_debug_cleanup(void)
4400{
4401 if (sky2_debug) {
4402 unregister_netdevice_notifier(&sky2_notifier);
4403 debugfs_remove(sky2_debug);
4404 sky2_debug = NULL;
4405 }
4406}
4407
4408#else
4409#define sky2_debug_init()
4410#define sky2_debug_cleanup()
4411#endif
4412
1436b301
SH		 4413/* Two copies of network device operations to handle special case of
4414 not allowing netpoll on second port */
4415static const struct net_device_ops sky2_netdev_ops[2] = {
4416 {
4417 .ndo_open = sky2_up,
4418 .ndo_stop = sky2_down,
00829823 4419 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4420 .ndo_do_ioctl = sky2_ioctl,
4421 .ndo_validate_addr = eth_validate_addr,
4422 .ndo_set_mac_address = sky2_set_mac_address,
4423 .ndo_set_multicast_list = sky2_set_multicast,
4424 .ndo_change_mtu = sky2_change_mtu,
4425 .ndo_tx_timeout = sky2_tx_timeout,
4426#ifdef SKY2_VLAN_TAG_USED
4427 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4428#endif
4429#ifdef CONFIG_NET_POLL_CONTROLLER
4430 .ndo_poll_controller = sky2_netpoll,
4431#endif
4432 },
4433 {
4434 .ndo_open = sky2_up,
4435 .ndo_stop = sky2_down,
00829823 4436 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4437 .ndo_do_ioctl = sky2_ioctl,
4438 .ndo_validate_addr = eth_validate_addr,
4439 .ndo_set_mac_address = sky2_set_mac_address,
4440 .ndo_set_multicast_list = sky2_set_multicast,
4441 .ndo_change_mtu = sky2_change_mtu,
4442 .ndo_tx_timeout = sky2_tx_timeout,
4443#ifdef SKY2_VLAN_TAG_USED
4444 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4445#endif
4446 },
4447};
3cf26753 4448
cd28ab6a
SH		 4449/* Initialize network device */
4450static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4451 unsigned port,
be63a21c 4452 int highmem, int wol)
cd28ab6a
SH		 4453{
4454 struct sky2_port *sky2;
4455 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4456
4457 if (!dev) {
898eb71c 4458 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4459 return NULL;
4460 }
4461
cd28ab6a 4462 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4463 dev->irq = hw->pdev->irq;
cd28ab6a 4464 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4465 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4466 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4467
4468 sky2 = netdev_priv(dev);
4469 sky2->netdev = dev;
4470 sky2->hw = hw;
4471 sky2->msg_enable = netif_msg_init(debug, default_msg);
4472
cd28ab6a 4473 /* Auto speed and flow control */
0ea065e5
SH		 4474 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4475 if (hw->chip_id != CHIP_ID_YUKON_XL)
4476 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4477
16ad91e1
SH		 4478 sky2->flow_mode = FC_BOTH;
4479
cd28ab6a
SH		 4480 sky2->duplex = -1;
4481 sky2->speed = -1;
4482 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4483 sky2->wol = wol;
75d070c5 4484
e07b1aa8 4485 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4486
793b883e 4487 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4488 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4489 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4490
4491 hw->dev[port] = dev;
4492
4493 sky2->port = port;
4494
4a50a876 4495 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4496 if (highmem)
4497 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4498
d1f13708 4499#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4500 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4501 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4502 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4503 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4504 }
d1f13708
SH		 4505#endif
4506
cd28ab6a 4507 /* read the mac address */
793b883e 4508 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4509 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4510
cd28ab6a
SH		 4511 return dev;
4512}
4513
28bd181a 4514static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4515{
4516 const struct sky2_port *sky2 = netdev_priv(dev);
4517
6c35abae 4518 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4519}
4520
fb2690a9 4521/* Handle software interrupt used during MSI test */
7d12e780 4522static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4523{
4524 struct sky2_hw *hw = dev_id;
4525 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4526
4527 if (status == 0)
4528 return IRQ_NONE;
4529
4530 if (status & Y2_IS_IRQ_SW) {
ea76e635 4531 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4532 wake_up(&hw->msi_wait);
4533 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4534 }
4535 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4536
4537 return IRQ_HANDLED;
4538}
4539
4540/* Test interrupt path by forcing a a software IRQ */
4541static int __devinit sky2_test_msi(struct sky2_hw *hw)
4542{
4543 struct pci_dev *pdev = hw->pdev;
4544 int err;
4545
bb507fe1
SH		 4546 init_waitqueue_head (&hw->msi_wait);
4547
fb2690a9
SH		 4548 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4549
b0a20ded 4550 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4551 if (err) {
b02a9258 4552 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4553 return err;
4554 }
4555
fb2690a9 4556 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4557 sky2_read8(hw, B0_CTST);
fb2690a9 4558
ea76e635 4559 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4560
ea76e635 4561 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4562 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4563 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4564 "switching to INTx mode.\n");
fb2690a9
SH		 4565
4566 err = -EOPNOTSUPP;
4567 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4568 }
4569
4570 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4571 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4572
4573 free_irq(pdev->irq, hw);
4574
4575 return err;
4576}
4577
c7127a34
SH		 4578/* This driver supports yukon2 chipset only */
4579static const char *sky2_name(u8 chipid, char *buf, int sz)
4580{
4581 const char *name[] = {
4582 "XL", /* 0xb3 */
4583 "EC Ultra", /* 0xb4 */
4584 "Extreme", /* 0xb5 */
4585 "EC", /* 0xb6 */
4586 "FE", /* 0xb7 */
4587 "FE+", /* 0xb8 */
4588 "Supreme", /* 0xb9 */
0ce8b98d 4589 "UL 2", /* 0xba */
0f5aac70
SH		 4590 "Unknown", /* 0xbb */
4591 "Optima", /* 0xbc */
c7127a34
SH		 4592 };
4593
dae3a511 4594 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4595 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4596 else
4597 snprintf(buf, sz, "(chip %#x)", chipid);
4598 return buf;
4599}
4600
cd28ab6a
SH		 4601static int __devinit sky2_probe(struct pci_dev *pdev,
4602 const struct pci_device_id *ent)
4603{
7f60c64b 4604 struct net_device *dev;
cd28ab6a 4605 struct sky2_hw *hw;
be63a21c 4606 int err, using_dac = 0, wol_default;
3834507d 4607 u32 reg;
c7127a34 4608 char buf1[16];
cd28ab6a 4609
793b883e
SH		 4610 err = pci_enable_device(pdev);
4611 if (err) {
b02a9258 4612 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4613 goto err_out;
4614 }
4615
6cc90a5a
SH		 4616 /* Get configuration information
4617 * Note: only regular PCI config access once to test for HW issues
4618 * other PCI access through shared memory for speed and to
4619 * avoid MMCONFIG problems.
4620 */
4621 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4622 if (err) {
4623 dev_err(&pdev->dev, "PCI read config failed\n");
4624 goto err_out;
4625 }
4626
4627 if (~reg == 0) {
4628 dev_err(&pdev->dev, "PCI configuration read error\n");
4629 goto err_out;
4630 }
4631
793b883e
SH		 4632 err = pci_request_regions(pdev, DRV_NAME);
4633 if (err) {
b02a9258 4634 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4635 goto err_out_disable;
cd28ab6a
SH		 4636 }
4637
4638 pci_set_master(pdev);
4639
d1f3d4dd 4640 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4641 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4642 using_dac = 1;
6a35528a 4643 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4644 if (err < 0) {
b02a9258
SH		 4645 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4646 "for consistent allocations\n");
d1f3d4dd
SH		 4647 goto err_out_free_regions;
4648 }
d1f3d4dd 4649 } else {
284901a9 4650 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4651 if (err) {
b02a9258 4652 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4653 goto err_out_free_regions;
4654 }
4655 }
d1f3d4dd 4656
3834507d
SH		 4657
4658#ifdef __BIG_ENDIAN
4659 /* The sk98lin vendor driver uses hardware byte swapping but
4660 * this driver uses software swapping.
4661 */
4662 reg &= ~PCI_REV_DESC;
4663 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4664 if (err) {
4665 dev_err(&pdev->dev, "PCI write config failed\n");
4666 goto err_out_free_regions;
4667 }
4668#endif
4669
9d731d77 4670 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4671
cd28ab6a 4672 err = -ENOMEM;
66466797
SH		 4673
4674 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4675 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4676 if (!hw) {
b02a9258 4677 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4678 goto err_out_free_regions;
4679 }
4680
cd28ab6a 4681 hw->pdev = pdev;
66466797 4682 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4683
4684 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4685 if (!hw->regs) {
b02a9258 4686 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4687 goto err_out_free_hw;
4688 }
4689
e3173832 4690 err = sky2_init(hw);
cd28ab6a 4691 if (err)
793b883e 4692 goto err_out_iounmap;
cd28ab6a 4693
efe91932 4694 /* ring for status responses */
4695 hw->st_size = hw->ports * roundup_pow_of_two(2*RX_MAX_PENDING + TX_MAX_PENDING);
4696 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4697 &hw->st_dma);
4698 if (!hw->st_le)
4699 goto err_out_reset;
4700
c844d483
SH		 4701 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4702 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4703
e3173832
SH		 4704 sky2_reset(hw);
4705
be63a21c 4706 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4707 if (!dev) {
4708 err = -ENOMEM;
cd28ab6a 4709 goto err_out_free_pci;
7f60c64b 4710 }
cd28ab6a 4711
9fa1b1f3
SH		 4712 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4713 err = sky2_test_msi(hw);
4714 if (err == -EOPNOTSUPP)
4715 pci_disable_msi(pdev);
4716 else if (err)
4717 goto err_out_free_netdev;
4718 }
4719
793b883e
SH		 4720 err = register_netdev(dev);
4721 if (err) {
b02a9258 4722 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4723 goto err_out_free_netdev;
4724 }
4725
33cb7d33
BP		 4726 netif_carrier_off(dev);
4727
6de16237
SH		 4728 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4729
ea76e635
SH		 4730 err = request_irq(pdev->irq, sky2_intr,
4731 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4732 hw->irq_name, hw);
9fa1b1f3 4733 if (err) {
b02a9258 4734 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4735 goto err_out_unregister;
4736 }
4737 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4738 napi_enable(&hw->napi);
9fa1b1f3 4739
cd28ab6a
SH		 4740 sky2_show_addr(dev);
4741
7f60c64b 4742 if (hw->ports > 1) {
4743 struct net_device *dev1;
4744
ca519274 4745 err = -ENOMEM;
be63a21c 4746 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4747 if (dev1 && (err = register_netdev(dev1)) == 0)
4748 sky2_show_addr(dev1);
4749 else {
b02a9258
SH		 4750 dev_warn(&pdev->dev,
4751 "register of second port failed (%d)\n", err);
cd28ab6a 4752 hw->dev[1] = NULL;
ca519274
SH		 4753 hw->ports = 1;
4754 if (dev1)
4755 free_netdev(dev1);
4756 }
cd28ab6a
SH		 4757 }
4758
32c2c300 4759 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4760 INIT_WORK(&hw->restart_work, sky2_restart);
4761
793b883e 4762 pci_set_drvdata(pdev, hw);
1ae861e6 4763 pdev->d3_delay = 150;
793b883e 4764
cd28ab6a
SH		 4765 return 0;
4766
793b883e 4767err_out_unregister:
ea76e635 4768 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4769 pci_disable_msi(pdev);
793b883e 4770 unregister_netdev(dev);
cd28ab6a
SH		 4771err_out_free_netdev:
4772 free_netdev(dev);
cd28ab6a 4773err_out_free_pci:
efe91932 4774 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4775 hw->st_le, hw->st_dma);
4776err_out_reset:
793b883e 4777 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4778err_out_iounmap:
4779 iounmap(hw->regs);
4780err_out_free_hw:
4781 kfree(hw);
4782err_out_free_regions:
4783 pci_release_regions(pdev);
44a1d2e5 4784err_out_disable:
cd28ab6a 4785 pci_disable_device(pdev);
cd28ab6a 4786err_out:
549a68c3 4787 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4788 return err;
4789}
4790
4791static void __devexit sky2_remove(struct pci_dev *pdev)
4792{
793b883e 4793 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4794 int i;
cd28ab6a 4795
793b883e 4796 if (!hw)
cd28ab6a
SH		 4797 return;
4798
32c2c300 4799 del_timer_sync(&hw->watchdog_timer);
6de16237 4800 cancel_work_sync(&hw->restart_work);
d27ed387 4801
b877fe28 4802 for (i = hw->ports-1; i >= 0; --i)
6de16237 4803 unregister_netdev(hw->dev[i]);
81906791 4804
d27ed387 4805 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4806
ae306cca
SH		 4807 sky2_power_aux(hw);
4808
793b883e 4809 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4810 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4811
4812 free_irq(pdev->irq, hw);
ea76e635 4813 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4814 pci_disable_msi(pdev);
efe91932 4815 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4816 hw->st_le, hw->st_dma);
cd28ab6a
SH		 4817 pci_release_regions(pdev);
4818 pci_disable_device(pdev);
793b883e 4819
b877fe28 4820 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4821 free_netdev(hw->dev[i]);
4822
cd28ab6a
SH		 4823 iounmap(hw->regs);
4824 kfree(hw);
5afa0a9c 4825
cd28ab6a
SH		 4826 pci_set_drvdata(pdev, NULL);
4827}
4828
cd28ab6a
SH		 4829static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4830{
793b883e 4831 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4832 int i, wol = 0;
cd28ab6a 4833
549a68c3
SH		 4834 if (!hw)
4835 return 0;
4836
063a0b38
SH		 4837 del_timer_sync(&hw->watchdog_timer);
4838 cancel_work_sync(&hw->restart_work);
4839
19720737 4840 rtnl_lock();
f05267e7 4841 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4842 struct net_device *dev = hw->dev[i];
e3173832 4843 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4844
af18d8b8 4845 sky2_detach(dev);
e3173832
SH		 4846
4847 if (sky2->wol)
4848 sky2_wol_init(sky2);
4849
4850 wol |= sky2->wol;
cd28ab6a
SH		 4851 }
4852
5f8ae5c5 4853 device_set_wakeup_enable(&pdev->dev, wol != 0);
4854
8ab8fca2 4855 sky2_write32(hw, B0_IMSK, 0);
6de16237 4856 napi_disable(&hw->napi);
ae306cca 4857 sky2_power_aux(hw);
19720737 4858 rtnl_unlock();
e3173832 4859
d374c1c1 4860 pci_save_state(pdev);
e3173832 4861 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4862 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4863
2ccc99b7 4864 return 0;
cd28ab6a
SH		 4865}
4866
5f8ae5c5 4867#ifdef CONFIG_PM
cd28ab6a
SH		 4868static int sky2_resume(struct pci_dev *pdev)
4869{
793b883e 4870 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4871 int i, err;
cd28ab6a 4872
549a68c3
SH		 4873 if (!hw)
4874 return 0;
4875
2a400189 4876 rtnl_lock();
f71eb1a2
SH		 4877 err = pci_set_power_state(pdev, PCI_D0);
4878 if (err)
4879 goto out;
ae306cca
SH		 4880
4881 err = pci_restore_state(pdev);
4882 if (err)
4883 goto out;
4884
cd28ab6a 4885 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4886
4887 /* Re-enable all clocks */
a0db28b8 4888 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4889 if (err) {
4890 dev_err(&pdev->dev, "PCI write config failed\n");
4891 goto out;
4892 }
1ad5b4a5 4893
e3173832 4894 sky2_reset(hw);
8ab8fca2 4895 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4896 napi_enable(&hw->napi);
8ab8fca2 4897
f05267e7 4898 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4899 err = sky2_reattach(hw->dev[i]);
4900 if (err)
4901 goto out;
cd28ab6a 4902 }
af18d8b8 4903 rtnl_unlock();
eb35cf60 4904
ae306cca 4905 return 0;
08c06d8a 4906out:
af18d8b8
SH		 4907 rtnl_unlock();
4908
b02a9258 4909 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4910 pci_disable_device(pdev);
08c06d8a 4911 return err;
cd28ab6a
SH		 4912}
4913#endif
4914
e3173832
SH		 4915static void sky2_shutdown(struct pci_dev *pdev)
4916{
5f8ae5c5 4917 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4918}
4919
cd28ab6a 4920static struct pci_driver sky2_driver = {
793b883e
SH		 4921 .name = DRV_NAME,
4922 .id_table = sky2_id_table,
4923 .probe = sky2_probe,
4924 .remove = __devexit_p(sky2_remove),
cd28ab6a 4925#ifdef CONFIG_PM
793b883e
SH		 4926 .suspend = sky2_suspend,
4927 .resume = sky2_resume,
cd28ab6a 4928#endif
e3173832 4929 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4930};
4931
4932static int __init sky2_init_module(void)
4933{
ada1db5c 4934 pr_info("driver version " DRV_VERSION "\n");
c844d483 4935
3cf26753 4936 sky2_debug_init();
50241c4c 4937 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4938}
4939
4940static void __exit sky2_cleanup_module(void)
4941{
4942 pci_unregister_driver(&sky2_driver);
3cf26753 4943 sky2_debug_cleanup();
cd28ab6a
SH		 4944}
4945
4946module_init(sky2_init_module);
4947module_exit(sky2_cleanup_module);
4948
4949MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4950MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4951MODULE_LICENSE("GPL");
5f4f9dc1 4952MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree