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sky2: flow control negotiation for Yukon-FE
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
683349a3 52#define DRV_VERSION "1.12"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 133 { 0 }
134};
793b883e 135
cd28ab6a
SH		 136MODULE_DEVICE_TABLE(pci, sky2_id_table);
137
138/* Avoid conditionals by using array */
139static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
140static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 141static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 142
92f965e8
SH		 143/* This driver supports yukon2 chipset only */
144static const char *yukon2_name[] = {
145 "XL", /* 0xb3 */
146 "EC Ultra", /* 0xb4 */
93745494 147 "Extreme", /* 0xb5 */
92f965e8
SH		 148 "EC", /* 0xb6 */
149 "FE", /* 0xb7 */
793b883e
SH		 150};
151
793b883e 152/* Access to external PHY */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 162 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 163 return 0;
793b883e 164 udelay(1);
cd28ab6a 165 }
ef743d33 166
793b883e 167 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 168 return -ETIMEDOUT;
cd28ab6a
SH		 169}
170
ef743d33 171static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 172{
173 int i;
174
793b883e 175 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 176 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
177
178 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 179 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
180 *val = gma_read16(hw, port, GM_SMI_DATA);
181 return 0;
182 }
183
793b883e 184 udelay(1);
cd28ab6a
SH		 185 }
186
ef743d33
SH		 187 return -ETIMEDOUT;
188}
189
190static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
191{
192 u16 v;
193
194 if (__gm_phy_read(hw, port, reg, &v) != 0)
195 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
196 return v;
cd28ab6a
SH		 197}
198
5afa0a9c 199
ae306cca
SH		 200static void sky2_power_on(struct sky2_hw *hw)
201{
202 /* switch power to VCC (WA for VAUX problem) */
203 sky2_write8(hw, B0_POWER_CTRL,
204 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 205
ae306cca
SH		 206 /* disable Core Clock Division, */
207 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 208
ae306cca
SH		 209 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
210 /* enable bits are inverted */
211 sky2_write8(hw, B2_Y2_CLK_GATE,
212 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
213 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
214 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
215 else
216 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 217
93745494 218 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 219 u32 reg1;
5afa0a9c 220
ae306cca
SH		 221 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
222 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
223 reg1 &= P_ASPM_CONTROL_MSK;
224 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
225 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 226 }
ae306cca 227}
5afa0a9c 228
ae306cca
SH		 229static void sky2_power_aux(struct sky2_hw *hw)
230{
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233 else
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239
240 /* switch power to VAUX */
241 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
242 sky2_write8(hw, B0_POWER_CTRL,
243 (PC_VAUX_ENA | PC_VCC_ENA |
244 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 245}
246
d3bcfbeb 247static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 248{
249 u16 reg;
250
251 /* disable all GMAC IRQ's */
252 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
253 /* disable PHY IRQs */
254 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 255
cd28ab6a
SH		 256 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
257 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
258 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
259 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
260
261 reg = gma_read16(hw, port, GM_RX_CTRL);
262 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
263 gma_write16(hw, port, GM_RX_CTRL, reg);
264}
265
16ad91e1
SH		 266/* flow control to advertise bits */
267static const u16 copper_fc_adv[] = {
268 [FC_NONE] = 0,
269 [FC_TX] = PHY_M_AN_ASP,
270 [FC_RX] = PHY_M_AN_PC,
271 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
272};
273
274/* flow control to advertise bits when using 1000BaseX */
275static const u16 fiber_fc_adv[] = {
276 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
277 [FC_TX] = PHY_M_P_ASYM_MD_X,
278 [FC_RX] = PHY_M_P_SYM_MD_X,
279 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
280};
281
282/* flow control to GMA disable bits */
283static const u16 gm_fc_disable[] = {
284 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
285 [FC_TX] = GM_GPCR_FC_RX_DIS,
286 [FC_RX] = GM_GPCR_FC_TX_DIS,
287 [FC_BOTH] = 0,
288};
289
290
cd28ab6a
SH		 291static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
292{
293 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 294 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 295
93745494
SH		 296 if (sky2->autoneg == AUTONEG_ENABLE
297 && !(hw->chip_id == CHIP_ID_YUKON_XL
298 || hw->chip_id == CHIP_ID_YUKON_EC_U
299 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 303 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 315 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
93745494
SH		 326 if (sky2->autoneg == AUTONEG_ENABLE
327 && (hw->chip_id == CHIP_ID_YUKON_XL
328 || hw->chip_id == CHIP_ID_YUKON_EC_U
329 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 330 ctrl &= ~PHY_M_PC_DSC_MSK;
331 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
332 }
333 }
cd28ab6a
SH		 334 } else {
335 /* workaround for deviation #4.88 (CRC errors) */
336 /* disable Automatic Crossover */
337
338 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 339 }
cd28ab6a 340
b89165f2
SH		 341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
342
343 /* special setup for PHY 88E1112 Fiber */
344 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
345 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 346
b89165f2
SH		 347 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
350 ctrl &= ~PHY_M_MAC_MD_MSK;
351 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
353
354 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 355 /* select page 1 to access Fiber registers */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 357
358 /* for SFP-module set SIGDET polarity to low */
359 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
360 ctrl |= PHY_M_FIB_SIGD_POL;
361 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 362 }
b89165f2
SH		 363
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 365 }
366
7800fddc 367 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 368 ct1000 = 0;
369 adv = PHY_AN_CSMA;
2eaba1a2 370 reg = 0;
cd28ab6a
SH		 371
372 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 373 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 374 if (sky2->advertising & ADVERTISED_1000baseT_Full)
375 ct1000 |= PHY_M_1000C_AFD;
376 if (sky2->advertising & ADVERTISED_1000baseT_Half)
377 ct1000 |= PHY_M_1000C_AHD;
378 if (sky2->advertising & ADVERTISED_100baseT_Full)
379 adv |= PHY_M_AN_100_FD;
380 if (sky2->advertising & ADVERTISED_100baseT_Half)
381 adv |= PHY_M_AN_100_HD;
382 if (sky2->advertising & ADVERTISED_10baseT_Full)
383 adv |= PHY_M_AN_10_FD;
384 if (sky2->advertising & ADVERTISED_10baseT_Half)
385 adv |= PHY_M_AN_10_HD;
709c6e7b 386
16ad91e1 387 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 388 } else { /* special defines for FIBER (88E1040S only) */
389 if (sky2->advertising & ADVERTISED_1000baseT_Full)
390 adv |= PHY_M_AN_1000X_AFD;
391 if (sky2->advertising & ADVERTISED_1000baseT_Half)
392 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 393
16ad91e1 394 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 395 }
cd28ab6a
SH		 396
397 /* Restart Auto-negotiation */
398 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
399 } else {
400 /* forced speed/duplex settings */
401 ct1000 = PHY_M_1000C_MSE;
402
2eaba1a2
SH		 403 /* Disable auto update for duplex flow control and speed */
404 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 405
406 switch (sky2->speed) {
407 case SPEED_1000:
408 ctrl |= PHY_CT_SP1000;
2eaba1a2 409 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 410 break;
411 case SPEED_100:
412 ctrl |= PHY_CT_SP100;
2eaba1a2 413 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 414 break;
415 }
416
2eaba1a2
SH		 417 if (sky2->duplex == DUPLEX_FULL) {
418 reg |= GM_GPCR_DUP_FULL;
419 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 420 } else if (sky2->speed < SPEED_1000)
421 sky2->flow_mode = FC_NONE;
2eaba1a2 422
2eaba1a2 423
16ad91e1 424 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 425
426 /* Forward pause packets to GMAC? */
16ad91e1 427 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 428 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
429 else
430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 431 }
432
2eaba1a2
SH		 433 gma_write16(hw, port, GM_GP_CTRL, reg);
434
cd28ab6a
SH		 435 if (hw->chip_id != CHIP_ID_YUKON_FE)
436 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
437
438 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
439 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
440
441 /* Setup Phy LED's */
442 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
443 ledover = 0;
444
445 switch (hw->chip_id) {
446 case CHIP_ID_YUKON_FE:
447 /* on 88E3082 these bits are at 11..9 (shifted left) */
448 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
449
450 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
451
452 /* delete ACT LED control bits */
453 ctrl &= ~PHY_M_FELP_LED1_MSK;
454 /* change ACT LED control to blink mode */
455 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
456 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
457 break;
458
459 case CHIP_ID_YUKON_XL:
793b883e 460 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 461
462 /* select page 3 to access LED control register */
463 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
464
465 /* set LED Function Control register */
ed6d32c7
SH		 466 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
467 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
468 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
469 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
470 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 471
472 /* set Polarity Control register */
473 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 474 (PHY_M_POLC_LS1_P_MIX(4) |
475 PHY_M_POLC_IS0_P_MIX(4) |
476 PHY_M_POLC_LOS_CTRL(2) |
477 PHY_M_POLC_INIT_CTRL(2) |
478 PHY_M_POLC_STA1_CTRL(2) |
479 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 480
481 /* restore page register */
793b883e 482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 483 break;
93745494 484
ed6d32c7 485 case CHIP_ID_YUKON_EC_U:
93745494 486 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 487 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
488
489 /* select page 3 to access LED control register */
490 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
491
492 /* set LED Function Control register */
493 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
494 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
495 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
496 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
497 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
498
499 /* set Blink Rate in LED Timer Control Register */
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
501 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
502 /* restore page register */
503 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
504 break;
cd28ab6a
SH		 505
506 default:
507 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
508 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
509 /* turn off the Rx LED (LED_RX) */
0efdf262 510 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 511 }
512
ed6d32c7 513 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 514 /* apply fixes in PHY AFE */
ed6d32c7
SH		 515 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
517
977bdf06 518 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 519 gm_phy_write(hw, port, 0x18, 0xaa99);
520 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 521
977bdf06 522 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 523 gm_phy_write(hw, port, 0x18, 0xa204);
524 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 525
526 /* set page register to 0 */
ed6d32c7 527 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
93745494 528 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 529 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 530
977bdf06
SH		 531 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
532 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 533 ledover |= PHY_M_LED_MO_100;
977bdf06 534 }
cd28ab6a 535
977bdf06
SH		 536 if (ledover)
537 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
538
539 }
2eaba1a2 540
d571b694 541 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 542 if (sky2->autoneg == AUTONEG_ENABLE)
543 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
544 else
545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
546}
547
d3bcfbeb
SH		 548static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
549{
550 u32 reg1;
551 static const u32 phy_power[]
552 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
553
554 /* looks like this XL is back asswards .. */
555 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
556 onoff = !onoff;
557
aed2cec4 558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 559 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 560 if (onoff)
561 /* Turn off phy power saving */
562 reg1 &= ~phy_power[port];
563 else
564 reg1 |= phy_power[port];
565
566 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 567 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 568 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 569 udelay(100);
570}
571
1b537565
SH		 572/* Force a renegotiation */
573static void sky2_phy_reinit(struct sky2_port *sky2)
574{
e07b1aa8 575 spin_lock_bh(&sky2->phy_lock);
1b537565 576 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 577 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 578}
579
e3173832
SH		 580/* Put device in state to listen for Wake On Lan */
581static void sky2_wol_init(struct sky2_port *sky2)
582{
583 struct sky2_hw *hw = sky2->hw;
584 unsigned port = sky2->port;
585 enum flow_control save_mode;
586 u16 ctrl;
587 u32 reg1;
588
589 /* Bring hardware out of reset */
590 sky2_write16(hw, B0_CTST, CS_RST_CLR);
591 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
592
593 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
594 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
595
596 /* Force to 10/100
597 * sky2_reset will re-enable on resume
598 */
599 save_mode = sky2->flow_mode;
600 ctrl = sky2->advertising;
601
602 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
603 sky2->flow_mode = FC_NONE;
604 sky2_phy_power(hw, port, 1);
605 sky2_phy_reinit(sky2);
606
607 sky2->flow_mode = save_mode;
608 sky2->advertising = ctrl;
609
610 /* Set GMAC to no flow control and auto update for speed/duplex */
611 gma_write16(hw, port, GM_GP_CTRL,
612 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
613 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
614
615 /* Set WOL address */
616 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
617 sky2->netdev->dev_addr, ETH_ALEN);
618
619 /* Turn on appropriate WOL control bits */
620 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
621 ctrl = 0;
622 if (sky2->wol & WAKE_PHY)
623 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
624 else
625 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
626
627 if (sky2->wol & WAKE_MAGIC)
628 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
629 else
630 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
631
632 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
633 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
634
635 /* Turn on legacy PCI-Express PME mode */
636 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638 reg1 |= PCI_Y2_PME_LEGACY;
639 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
641
642 /* block receiver */
643 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
644
645}
646
cd28ab6a
SH		 647static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
648{
649 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
650 u16 reg;
651 int i;
652 const u8 *addr = hw->dev[port]->dev_addr;
653
42eeea01
SH		 654 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
655 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 656
657 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
658
793b883e 659 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 660 /* WA DEV_472 -- looks like crossed wires on port 2 */
661 /* clear GMAC 1 Control reset */
662 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
663 do {
664 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
665 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
666 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
667 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
668 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
669 }
670
793b883e 671 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 672
2eaba1a2
SH		 673 /* Enable Transmit FIFO Underrun */
674 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
675
e07b1aa8 676 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 677 sky2_phy_init(hw, port);
e07b1aa8 678 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 679
680 /* MIB clear */
681 reg = gma_read16(hw, port, GM_PHY_ADDR);
682 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
683
43f2f104
SH		 684 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
685 gma_read16(hw, port, i);
cd28ab6a
SH		 686 gma_write16(hw, port, GM_PHY_ADDR, reg);
687
688 /* transmit control */
689 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
690
691 /* receive control reg: unicast + multicast + no FCS */
692 gma_write16(hw, port, GM_RX_CTRL,
793b883e 693 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 694
695 /* transmit flow control */
696 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
697
698 /* transmit parameter */
699 gma_write16(hw, port, GM_TX_PARAM,
700 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
701 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
702 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
703 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
704
705 /* serial mode register */
706 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 707 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 708
6b1a3aef 709 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 710 reg |= GM_SMOD_JUMBO_ENA;
711
712 gma_write16(hw, port, GM_SERIAL_MODE, reg);
713
cd28ab6a
SH		 714 /* virtual address for data */
715 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
716
793b883e
SH		 717 /* physical address: used for pause frames */
718 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
719
720 /* ignore counter overflows */
cd28ab6a
SH		 721 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
722 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
723 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
724
725 /* Configure Rx MAC FIFO */
726 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 727 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
728 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 729
d571b694 730 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 731 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 732
8df9a876
SH		 733 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 735
736 /* Configure Tx MAC FIFO */
737 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
738 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 739
93745494 740 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 741 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 742 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
743 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
744 /* set Tx GMAC FIFO Almost Empty Threshold */
745 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
746 /* Disable Store & Forward mode for TX */
747 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
748 }
749 }
750
cd28ab6a
SH		 751}
752
67712901
SH		 753/* Assign Ram Buffer allocation to queue */
754static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 755{
67712901
SH		 756 u32 end;
757
758 /* convert from K bytes to qwords used for hw register */
759 start *= 1024/8;
760 space *= 1024/8;
761 end = start + space - 1;
793b883e 762
cd28ab6a
SH		 763 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
764 sky2_write32(hw, RB_ADDR(q, RB_START), start);
765 sky2_write32(hw, RB_ADDR(q, RB_END), end);
766 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
767 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
768
769 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 770 u32 tp = space - space/4;
793b883e 771
1c28f6ba
SH		 772 /* On receive queue's set the thresholds
773 * give receiver priority when > 3/4 full
774 * send pause when down to 2K
775 */
776 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
777 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 778
1c28f6ba
SH		 779 tp = space - 2048/8;
780 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
781 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 782 } else {
783 /* Enable store & forward on Tx queue's because
784 * Tx FIFO is only 1K on Yukon
785 */
786 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
787 }
788
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 790 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 791}
792
cd28ab6a 793/* Setup Bus Memory Interface */
af4ed7e6 794static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 795{
796 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
797 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
798 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 799 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 800}
801
cd28ab6a
SH		 802/* Setup prefetch unit registers. This is the interface between
803 * hardware and driver list elements
804 */
8cc048e3 805static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 806 u64 addr, u32 last)
807{
cd28ab6a
SH		 808 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
809 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
810 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
812 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 814
815 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 816}
817
793b883e
SH		 818static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
819{
820 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
821
cb5d9547 822 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 823 le->ctrl = 0;
793b883e
SH		 824 return le;
825}
cd28ab6a 826
291ea614
SH		 827static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
828 struct sky2_tx_le *le)
829{
830 return sky2->tx_ring + (le - sky2->tx_le);
831}
832
290d4de5
SH		 833/* Update chip's next pointer */
834static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 835{
98232f85 836 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 837 wmb();
98232f85
SH		 838 sky2_write16(hw, q, idx);
839 sky2_read16(hw, q);
cd28ab6a
SH		 840}
841
793b883e 842
cd28ab6a
SH		 843static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
844{
845 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 846 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 847 le->ctrl = 0;
cd28ab6a
SH		 848 return le;
849}
850
a018e330
SH		 851/* Return high part of DMA address (could be 32 or 64 bit) */
852static inline u32 high32(dma_addr_t a)
853{
a036119f 854 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 855}
856
14d0263f
SH		 857/* Build description to hardware for one receive segment */
858static void sky2_rx_add(struct sky2_port *sky2, u8 op,
859 dma_addr_t map, unsigned len)
cd28ab6a
SH		 860{
861 struct sky2_rx_le *le;
734d1868 862 u32 hi = high32(map);
cd28ab6a 863
793b883e 864 if (sky2->rx_addr64 != hi) {
cd28ab6a 865 le = sky2_next_rx(sky2);
793b883e 866 le->addr = cpu_to_le32(hi);
cd28ab6a 867 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 868 sky2->rx_addr64 = high32(map + len);
cd28ab6a 869 }
793b883e 870
cd28ab6a 871 le = sky2_next_rx(sky2);
734d1868
SH		 872 le->addr = cpu_to_le32((u32) map);
873 le->length = cpu_to_le16(len);
14d0263f 874 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 875}
876
14d0263f
SH		 877/* Build description to hardware for one possibly fragmented skb */
878static void sky2_rx_submit(struct sky2_port *sky2,
879 const struct rx_ring_info *re)
880{
881 int i;
882
883 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
884
885 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
886 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
887}
888
889
890static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
891 unsigned size)
892{
893 struct sk_buff *skb = re->skb;
894 int i;
895
896 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
897 pci_unmap_len_set(re, data_size, size);
898
899 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
900 re->frag_addr[i] = pci_map_page(pdev,
901 skb_shinfo(skb)->frags[i].page,
902 skb_shinfo(skb)->frags[i].page_offset,
903 skb_shinfo(skb)->frags[i].size,
904 PCI_DMA_FROMDEVICE);
905}
906
907static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
908{
909 struct sk_buff *skb = re->skb;
910 int i;
911
912 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
913 PCI_DMA_FROMDEVICE);
914
915 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
916 pci_unmap_page(pdev, re->frag_addr[i],
917 skb_shinfo(skb)->frags[i].size,
918 PCI_DMA_FROMDEVICE);
919}
793b883e 920
cd28ab6a
SH		 921/* Tell chip where to start receive checksum.
922 * Actually has two checksums, but set both same to avoid possible byte
923 * order problems.
924 */
793b883e 925static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 926{
927 struct sky2_rx_le *le;
928
cd28ab6a 929 le = sky2_next_rx(sky2);
f65b138c 930 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 931 le->ctrl = 0;
932 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 933
793b883e
SH		 934 sky2_write32(sky2->hw,
935 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
936 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 937
938}
939
6b1a3aef
SH		 940/*
941 * The RX Stop command will not work for Yukon-2 if the BMU does not
942 * reach the end of packet and since we can't make sure that we have
943 * incoming data, we must reset the BMU while it is not doing a DMA
944 * transfer. Since it is possible that the RX path is still active,
945 * the RX RAM buffer will be stopped first, so any possible incoming
946 * data will not trigger a DMA. After the RAM buffer is stopped, the
947 * BMU is polled until any DMA in progress is ended and only then it
948 * will be reset.
949 */
950static void sky2_rx_stop(struct sky2_port *sky2)
951{
952 struct sky2_hw *hw = sky2->hw;
953 unsigned rxq = rxqaddr[sky2->port];
954 int i;
955
956 /* disable the RAM Buffer receive queue */
957 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
958
959 for (i = 0; i < 0xffff; i++)
960 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
961 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
962 goto stopped;
963
964 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
965 sky2->netdev->name);
966stopped:
967 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
968
969 /* reset the Rx prefetch unit */
970 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
971}
793b883e 972
d571b694 973/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 974static void sky2_rx_clean(struct sky2_port *sky2)
975{
976 unsigned i;
977
978 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 979 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 980 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 981
982 if (re->skb) {
14d0263f 983 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 984 kfree_skb(re->skb);
985 re->skb = NULL;
986 }
987 }
988}
989
ef743d33
SH		 990/* Basic MII support */
991static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
992{
993 struct mii_ioctl_data *data = if_mii(ifr);
994 struct sky2_port *sky2 = netdev_priv(dev);
995 struct sky2_hw *hw = sky2->hw;
996 int err = -EOPNOTSUPP;
997
998 if (!netif_running(dev))
999 return -ENODEV; /* Phy still in reset */
1000
d89e1343 1001 switch (cmd) {
ef743d33
SH		 1002 case SIOCGMIIPHY:
1003 data->phy_id = PHY_ADDR_MARV;
1004
1005 /* fallthru */
1006 case SIOCGMIIREG: {
1007 u16 val = 0;
91c86df5 1008
e07b1aa8 1009 spin_lock_bh(&sky2->phy_lock);
ef743d33 1010 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1011 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1012
ef743d33
SH		 1013 data->val_out = val;
1014 break;
1015 }
1016
1017 case SIOCSMIIREG:
1018 if (!capable(CAP_NET_ADMIN))
1019 return -EPERM;
1020
e07b1aa8 1021 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1022 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1023 data->val_in);
e07b1aa8 1024 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1025 break;
1026 }
1027 return err;
1028}
1029
d1f13708
SH		 1030#ifdef SKY2_VLAN_TAG_USED
1031static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1032{
1033 struct sky2_port *sky2 = netdev_priv(dev);
1034 struct sky2_hw *hw = sky2->hw;
1035 u16 port = sky2->port;
d1f13708 1036
2bb8c262 1037 netif_tx_lock_bh(dev);
d1f13708
SH		 1038
1039 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1040 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1041 sky2->vlgrp = grp;
1042
2bb8c262 1043 netif_tx_unlock_bh(dev);
d1f13708
SH		 1044}
1045
1046static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1047{
1048 struct sky2_port *sky2 = netdev_priv(dev);
1049 struct sky2_hw *hw = sky2->hw;
1050 u16 port = sky2->port;
d1f13708 1051
2bb8c262 1052 netif_tx_lock_bh(dev);
d1f13708
SH		 1053
1054 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1055 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1056 if (sky2->vlgrp)
1057 sky2->vlgrp->vlan_devices[vid] = NULL;
1058
2bb8c262 1059 netif_tx_unlock_bh(dev);
d1f13708
SH		 1060}
1061#endif
1062
82788c7a 1063/*
14d0263f
SH		 1064 * Allocate an skb for receiving. If the MTU is large enough
1065 * make the skb non-linear with a fragment list of pages.
1066 *
82788c7a
SH		 1067 * It appears the hardware has a bug in the FIFO logic that
1068 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1069 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1070 * aligned except if slab debugging is enabled.
82788c7a 1071 */
14d0263f 1072static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1073{
1074 struct sk_buff *skb;
14d0263f
SH		 1075 unsigned long p;
1076 int i;
82788c7a 1077
14d0263f
SH		 1078 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1079 if (!skb)
1080 goto nomem;
1081
1082 p = (unsigned long) skb->data;
1083 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1084
1085 for (i = 0; i < sky2->rx_nfrags; i++) {
1086 struct page *page = alloc_page(GFP_ATOMIC);
1087
1088 if (!page)
1089 goto free_partial;
1090 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1091 }
1092
1093 return skb;
14d0263f
SH		 1094free_partial:
1095 kfree_skb(skb);
1096nomem:
1097 return NULL;
82788c7a
SH		 1098}
1099
cd28ab6a
SH		 1100/*
1101 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1102 * Normal case this ends up creating one list element for skb
1103 * in the receive ring. Worst case if using large MTU and each
1104 * allocation falls on a different 64 bit region, that results
1105 * in 6 list elements per ring entry.
1106 * One element is used for checksum enable/disable, and one
1107 * extra to avoid wrap.
cd28ab6a 1108 */
6b1a3aef 1109static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1110{
6b1a3aef 1111 struct sky2_hw *hw = sky2->hw;
14d0263f 1112 struct rx_ring_info *re;
6b1a3aef 1113 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1114 unsigned i, size, space, thresh;
cd28ab6a 1115
6b1a3aef 1116 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1117 sky2_qset(hw, rxq);
977bdf06 1118
c3905bc4
SH		 1119 /* On PCI express lowering the watermark gives better performance */
1120 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1121 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1122
1123 /* These chips have no ram buffer?
1124 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1125 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1126 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1127 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1128 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1129
6b1a3aef
SH		 1130 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1131
1132 rx_set_checksum(sky2);
14d0263f
SH		 1133
1134 /* Space needed for frame data + headers rounded up */
1135 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1136 + 8;
1137
1138 /* Stopping point for hardware truncation */
1139 thresh = (size - 8) / sizeof(u32);
1140
1141 /* Account for overhead of skb - to avoid order > 0 allocation */
1142 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1143 + sizeof(struct skb_shared_info);
1144
1145 sky2->rx_nfrags = space >> PAGE_SHIFT;
1146 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1147
1148 if (sky2->rx_nfrags != 0) {
1149 /* Compute residue after pages */
1150 space = sky2->rx_nfrags << PAGE_SHIFT;
1151
1152 if (space < size)
1153 size -= space;
1154 else
1155 size = 0;
1156
1157 /* Optimize to handle small packets and headers */
1158 if (size < copybreak)
1159 size = copybreak;
1160 if (size < ETH_HLEN)
1161 size = ETH_HLEN;
1162 }
1163 sky2->rx_data_size = size;
1164
1165 /* Fill Rx ring */
793b883e 1166 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1167 re = sky2->rx_ring + i;
cd28ab6a 1168
14d0263f 1169 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1170 if (!re->skb)
1171 goto nomem;
1172
14d0263f
SH		 1173 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1174 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1175 }
1176
a1433ac4
SH		 1177 /*
1178 * The receiver hangs if it receives frames larger than the
1179 * packet buffer. As a workaround, truncate oversize frames, but
1180 * the register is limited to 9 bits, so if you do frames > 2052
1181 * you better get the MTU right!
1182 */
a1433ac4
SH		 1183 if (thresh > 0x1ff)
1184 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1185 else {
1186 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1187 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1188 }
1189
6b1a3aef
SH		 1190 /* Tell chip about available buffers */
1191 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1192 return 0;
1193nomem:
1194 sky2_rx_clean(sky2);
1195 return -ENOMEM;
1196}
1197
1198/* Bring up network interface. */
1199static int sky2_up(struct net_device *dev)
1200{
1201 struct sky2_port *sky2 = netdev_priv(dev);
1202 struct sky2_hw *hw = sky2->hw;
1203 unsigned port = sky2->port;
67712901 1204 u32 ramsize, imask;
ee7abb04 1205 int cap, err = -ENOMEM;
843a46f4 1206 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1207
ee7abb04
SH		 1208 /*
1209 * On dual port PCI-X card, there is an problem where status
1210 * can be received out of order due to split transactions
843a46f4 1211 */
ee7abb04
SH		 1212 if (otherdev && netif_running(otherdev) &&
1213 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1214 struct sky2_port *osky2 = netdev_priv(otherdev);
1215 u16 cmd;
1216
1217 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1218 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1219 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1220
1221 sky2->rx_csum = 0;
1222 osky2->rx_csum = 0;
1223 }
843a46f4 1224
cd28ab6a
SH		 1225 if (netif_msg_ifup(sky2))
1226 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1227
1228 /* must be power of 2 */
1229 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1230 TX_RING_SIZE *
1231 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1232 &sky2->tx_le_map);
1233 if (!sky2->tx_le)
1234 goto err_out;
1235
6cdbbdf3 1236 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1237 GFP_KERNEL);
1238 if (!sky2->tx_ring)
1239 goto err_out;
1240 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1241
1242 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1243 &sky2->rx_le_map);
1244 if (!sky2->rx_le)
1245 goto err_out;
1246 memset(sky2->rx_le, 0, RX_LE_BYTES);
1247
291ea614 1248 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1249 GFP_KERNEL);
1250 if (!sky2->rx_ring)
1251 goto err_out;
1252
d3bcfbeb
SH		 1253 sky2_phy_power(hw, port, 1);
1254
cd28ab6a
SH		 1255 sky2_mac_init(hw, port);
1256
67712901
SH		 1257 /* Register is number of 4K blocks on internal RAM buffer. */
1258 ramsize = sky2_read8(hw, B2_E_0) * 4;
1259 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1260
67712901
SH		 1261 if (ramsize > 0) {
1262 u32 rxspace;
cd28ab6a 1263
67712901
SH		 1264 if (ramsize < 16)
1265 rxspace = ramsize / 2;
1266 else
1267 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1268
67712901
SH		 1269 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1270 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1271
1272 /* Make sure SyncQ is disabled */
1273 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1274 RB_RST_SET);
1275 }
793b883e 1276
af4ed7e6 1277 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1278
977bdf06 1279 /* Set almost empty threshold */
c2716fb4
SH		 1280 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1281 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1282 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1283
6b1a3aef
SH		 1284 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1285 TX_RING_SIZE - 1);
cd28ab6a 1286
6b1a3aef 1287 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1288 if (err)
1289 goto err_out;
1290
cd28ab6a 1291 /* Enable interrupts from phy/mac for port */
e07b1aa8 1292 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1293 imask |= portirq_msk[port];
e07b1aa8
SH		 1294 sky2_write32(hw, B0_IMSK, imask);
1295
cd28ab6a
SH		 1296 return 0;
1297
1298err_out:
1b537565 1299 if (sky2->rx_le) {
cd28ab6a
SH		 1300 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1301 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1302 sky2->rx_le = NULL;
1303 }
1304 if (sky2->tx_le) {
cd28ab6a
SH		 1305 pci_free_consistent(hw->pdev,
1306 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1307 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1308 sky2->tx_le = NULL;
1309 }
1310 kfree(sky2->tx_ring);
1311 kfree(sky2->rx_ring);
cd28ab6a 1312
1b537565
SH		 1313 sky2->tx_ring = NULL;
1314 sky2->rx_ring = NULL;
cd28ab6a
SH		 1315 return err;
1316}
1317
793b883e
SH		 1318/* Modular subtraction in ring */
1319static inline int tx_dist(unsigned tail, unsigned head)
1320{
cb5d9547 1321 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1322}
cd28ab6a 1323
793b883e
SH		 1324/* Number of list elements available for next tx */
1325static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1326{
793b883e 1327 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1328}
1329
793b883e 1330/* Estimate of number of transmit list elements required */
28bd181a 1331static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1332{
793b883e
SH		 1333 unsigned count;
1334
1335 count = sizeof(dma_addr_t) / sizeof(u32);
1336 count += skb_shinfo(skb)->nr_frags * count;
1337
89114afd 1338 if (skb_is_gso(skb))
793b883e
SH		 1339 ++count;
1340
84fa7933 1341 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1342 ++count;
1343
1344 return count;
cd28ab6a
SH		 1345}
1346
793b883e
SH		 1347/*
1348 * Put one packet in ring for transmit.
1349 * A single packet can generate multiple list elements, and
1350 * the number of ring elements will probably be less than the number
1351 * of list elements used.
1352 */
cd28ab6a
SH		 1353static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1354{
1355 struct sky2_port *sky2 = netdev_priv(dev);
1356 struct sky2_hw *hw = sky2->hw;
d1f13708 1357 struct sky2_tx_le *le = NULL;
6cdbbdf3 1358 struct tx_ring_info *re;
cd28ab6a
SH		 1359 unsigned i, len;
1360 dma_addr_t mapping;
1361 u32 addr64;
1362 u16 mss;
1363 u8 ctrl;
1364
2bb8c262
SH		 1365 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1366 return NETDEV_TX_BUSY;
cd28ab6a 1367
793b883e 1368 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1369 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1370 dev->name, sky2->tx_prod, skb->len);
1371
cd28ab6a
SH		 1372 len = skb_headlen(skb);
1373 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1374 addr64 = high32(mapping);
793b883e 1375
a018e330
SH		 1376 /* Send high bits if changed or crosses boundary */
1377 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1378 le = get_tx_le(sky2);
f65b138c 1379 le->addr = cpu_to_le32(addr64);
793b883e 1380 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1381 sky2->tx_addr64 = high32(mapping + len);
793b883e 1382 }
cd28ab6a
SH		 1383
1384 /* Check for TCP Segmentation Offload */
7967168c 1385 mss = skb_shinfo(skb)->gso_size;
793b883e 1386 if (mss != 0) {
cd28ab6a
SH		 1387 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1388 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1389 mss += ETH_HLEN;
1390
e07560cd
SH		 1391 if (mss != sky2->tx_last_mss) {
1392 le = get_tx_le(sky2);
f65b138c 1393 le->addr = cpu_to_le32(mss);
e07560cd 1394 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1395 sky2->tx_last_mss = mss;
1396 }
cd28ab6a
SH		 1397 }
1398
cd28ab6a 1399 ctrl = 0;
d1f13708
SH		 1400#ifdef SKY2_VLAN_TAG_USED
1401 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1402 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1403 if (!le) {
1404 le = get_tx_le(sky2);
f65b138c 1405 le->addr = 0;
d1f13708 1406 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1407 } else
1408 le->opcode |= OP_VLAN;
1409 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1410 ctrl |= INS_VLAN;
1411 }
1412#endif
1413
1414 /* Handle TCP checksum offload */
84fa7933 1415 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1416 unsigned offset = skb->h.raw - skb->data;
1417 u32 tcpsum;
1418
1419 tcpsum = offset << 16; /* sum start */
ff1dcadb 1420 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1421
1422 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1423 if (skb->nh.iph->protocol == IPPROTO_UDP)
1424 ctrl |= UDPTCP;
1425
f65b138c
SH		 1426 if (tcpsum != sky2->tx_tcpsum) {
1427 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1428
1429 le = get_tx_le(sky2);
f65b138c 1430 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1431 le->length = 0; /* initial checksum value */
1432 le->ctrl = 1; /* one packet */
1433 le->opcode = OP_TCPLISW | HW_OWNER;
1434 }
cd28ab6a
SH		 1435 }
1436
1437 le = get_tx_le(sky2);
f65b138c 1438 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1439 le->length = cpu_to_le16(len);
1440 le->ctrl = ctrl;
793b883e 1441 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1442
291ea614 1443 re = tx_le_re(sky2, le);
cd28ab6a 1444 re->skb = skb;
6cdbbdf3 1445 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1446 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1447
1448 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1449 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1450
1451 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1452 frag->size, PCI_DMA_TODEVICE);
a036119f 1453 addr64 = high32(mapping);
793b883e
SH		 1454 if (addr64 != sky2->tx_addr64) {
1455 le = get_tx_le(sky2);
f65b138c 1456 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1457 le->ctrl = 0;
1458 le->opcode = OP_ADDR64 | HW_OWNER;
1459 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1460 }
1461
1462 le = get_tx_le(sky2);
f65b138c 1463 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1464 le->length = cpu_to_le16(frag->size);
1465 le->ctrl = ctrl;
793b883e 1466 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1467
291ea614
SH		 1468 re = tx_le_re(sky2, le);
1469 re->skb = skb;
1470 pci_unmap_addr_set(re, mapaddr, mapping);
1471 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1472 }
6cdbbdf3 1473
cd28ab6a
SH		 1474 le->ctrl |= EOP;
1475
97bda706
SH		 1476 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1477 netif_stop_queue(dev);
b19666d9 1478
290d4de5 1479 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1480
cd28ab6a
SH		 1481 dev->trans_start = jiffies;
1482 return NETDEV_TX_OK;
1483}
1484
cd28ab6a 1485/*
793b883e
SH		 1486 * Free ring elements from starting at tx_cons until "done"
1487 *
1488 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1489 * buffers so make sure not to free skb to early.
cd28ab6a 1490 */
d11c13e7 1491static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1492{
d11c13e7 1493 struct net_device *dev = sky2->netdev;
af2a58ac 1494 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1495 unsigned idx;
cd28ab6a 1496
0e3ff6aa 1497 BUG_ON(done >= TX_RING_SIZE);
2224795d 1498
291ea614
SH		 1499 for (idx = sky2->tx_cons; idx != done;
1500 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1501 struct sky2_tx_le *le = sky2->tx_le + idx;
1502 struct tx_ring_info *re = sky2->tx_ring + idx;
1503
1504 switch(le->opcode & ~HW_OWNER) {
1505 case OP_LARGESEND:
1506 case OP_PACKET:
1507 pci_unmap_single(pdev,
1508 pci_unmap_addr(re, mapaddr),
1509 pci_unmap_len(re, maplen),
1510 PCI_DMA_TODEVICE);
af2a58ac 1511 break;
291ea614
SH		 1512 case OP_BUFFER:
1513 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1514 pci_unmap_len(re, maplen),
734d1868 1515 PCI_DMA_TODEVICE);
291ea614
SH		 1516 break;
1517 }
1518
1519 if (le->ctrl & EOP) {
1520 if (unlikely(netif_msg_tx_done(sky2)))
1521 printk(KERN_DEBUG "%s: tx done %u\n",
1522 dev->name, idx);
2bf56fe2 1523 sky2->net_stats.tx_packets++;
1524 sky2->net_stats.tx_bytes += re->skb->len;
1525
794b2bd2 1526 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1527 }
1528
291ea614 1529 le->opcode = 0; /* paranoia */
793b883e 1530 }
793b883e 1531
291ea614 1532 sky2->tx_cons = idx;
22e11703 1533 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1534 netif_wake_queue(dev);
cd28ab6a
SH		 1535}
1536
1537/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1538static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1539{
2bb8c262
SH		 1540 struct sky2_port *sky2 = netdev_priv(dev);
1541
1542 netif_tx_lock_bh(dev);
d11c13e7 1543 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1544 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1545}
1546
1547/* Network shutdown */
1548static int sky2_down(struct net_device *dev)
1549{
1550 struct sky2_port *sky2 = netdev_priv(dev);
1551 struct sky2_hw *hw = sky2->hw;
1552 unsigned port = sky2->port;
1553 u16 ctrl;
e07b1aa8 1554 u32 imask;
cd28ab6a 1555
1b537565
SH		 1556 /* Never really got started! */
1557 if (!sky2->tx_le)
1558 return 0;
1559
cd28ab6a
SH		 1560 if (netif_msg_ifdown(sky2))
1561 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1562
018d1c66 1563 /* Stop more packets from being queued */
cd28ab6a
SH		 1564 netif_stop_queue(dev);
1565
ebc646f6
SH		 1566 /* Disable port IRQ */
1567 imask = sky2_read32(hw, B0_IMSK);
1568 imask &= ~portirq_msk[port];
1569 sky2_write32(hw, B0_IMSK, imask);
1570
25d82d7a
SH		 1571 /*
1572 * Both ports share the NAPI poll on port 0, so if necessary undo the
1573 * the disable that is done in dev_close.
1574 */
1575 if (sky2->port == 0 && hw->ports > 1)
1576 netif_poll_enable(dev);
1577
d3bcfbeb 1578 sky2_gmac_reset(hw, port);
793b883e 1579
cd28ab6a
SH		 1580 /* Stop transmitter */
1581 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1582 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1583
1584 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1585 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1586
c2716fb4
SH		 1587 /* WA for dev. #4.209 */
1588 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1589 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1590 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1591 sky2->speed != SPEED_1000 ?
1592 TX_STFW_ENA : TX_STFW_DIS);
1593
cd28ab6a 1594 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1595 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1596 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1597
1598 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1599
1600 /* Workaround shared GMAC reset */
793b883e
SH		 1601 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1602 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1603 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1604
1605 /* Disable Force Sync bit and Enable Alloc bit */
1606 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1607 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1608
1609 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1610 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1611 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1612
1613 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1614 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1615 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1616
1617 /* Reset the Tx prefetch units */
1618 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1619 PREF_UNIT_RST_SET);
1620
1621 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1622
6b1a3aef 1623 sky2_rx_stop(sky2);
cd28ab6a
SH		 1624
1625 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1626 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1627
d3bcfbeb
SH		 1628 sky2_phy_power(hw, port, 0);
1629
d571b694 1630 /* turn off LED's */
cd28ab6a
SH		 1631 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1632
018d1c66
SH		 1633 synchronize_irq(hw->pdev->irq);
1634
2bb8c262 1635 sky2_tx_clean(dev);
cd28ab6a
SH		 1636 sky2_rx_clean(sky2);
1637
1638 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1639 sky2->rx_le, sky2->rx_le_map);
1640 kfree(sky2->rx_ring);
1641
1642 pci_free_consistent(hw->pdev,
1643 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1644 sky2->tx_le, sky2->tx_le_map);
1645 kfree(sky2->tx_ring);
1646
1b537565
SH		 1647 sky2->tx_le = NULL;
1648 sky2->rx_le = NULL;
1649
1650 sky2->rx_ring = NULL;
1651 sky2->tx_ring = NULL;
1652
cd28ab6a
SH		 1653 return 0;
1654}
1655
1656static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1657{
b89165f2 1658 if (!sky2_is_copper(hw))
793b883e
SH		 1659 return SPEED_1000;
1660
cd28ab6a
SH		 1661 if (hw->chip_id == CHIP_ID_YUKON_FE)
1662 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1663
1664 switch (aux & PHY_M_PS_SPEED_MSK) {
1665 case PHY_M_PS_SPEED_1000:
1666 return SPEED_1000;
1667 case PHY_M_PS_SPEED_100:
1668 return SPEED_100;
1669 default:
1670 return SPEED_10;
1671 }
1672}
1673
1674static void sky2_link_up(struct sky2_port *sky2)
1675{
1676 struct sky2_hw *hw = sky2->hw;
1677 unsigned port = sky2->port;
1678 u16 reg;
16ad91e1
SH		 1679 static const char *fc_name[] = {
1680 [FC_NONE] = "none",
1681 [FC_TX] = "tx",
1682 [FC_RX] = "rx",
1683 [FC_BOTH] = "both",
1684 };
cd28ab6a 1685
cd28ab6a 1686 /* enable Rx/Tx */
2eaba1a2 1687 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1688 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1689 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1690
1691 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1692
1693 netif_carrier_on(sky2->netdev);
1694 netif_wake_queue(sky2->netdev);
1695
1696 /* Turn on link LED */
793b883e 1697 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1698 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1699
93745494
SH		 1700 if (hw->chip_id == CHIP_ID_YUKON_XL
1701 || hw->chip_id == CHIP_ID_YUKON_EC_U
1702 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1703 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1704 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1705
1706 switch(sky2->speed) {
1707 case SPEED_10:
1708 led |= PHY_M_LEDC_INIT_CTRL(7);
1709 break;
1710
1711 case SPEED_100:
1712 led |= PHY_M_LEDC_STA1_CTRL(7);
1713 break;
1714
1715 case SPEED_1000:
1716 led |= PHY_M_LEDC_STA0_CTRL(7);
1717 break;
1718 }
793b883e
SH		 1719
1720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1721 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1723 }
1724
cd28ab6a
SH		 1725 if (netif_msg_link(sky2))
1726 printk(KERN_INFO PFX
d571b694 1727 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1728 sky2->netdev->name, sky2->speed,
1729 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1730 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1731}
1732
1733static void sky2_link_down(struct sky2_port *sky2)
1734{
1735 struct sky2_hw *hw = sky2->hw;
1736 unsigned port = sky2->port;
1737 u16 reg;
1738
1739 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1740
1741 reg = gma_read16(hw, port, GM_GP_CTRL);
1742 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1743 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1744
cd28ab6a
SH		 1745 netif_carrier_off(sky2->netdev);
1746 netif_stop_queue(sky2->netdev);
1747
1748 /* Turn on link LED */
1749 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1750
1751 if (netif_msg_link(sky2))
1752 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1753
cd28ab6a
SH		 1754 sky2_phy_init(hw, port);
1755}
1756
16ad91e1
SH		 1757static enum flow_control sky2_flow(int rx, int tx)
1758{
1759 if (rx)
1760 return tx ? FC_BOTH : FC_RX;
1761 else
1762 return tx ? FC_TX : FC_NONE;
1763}
1764
793b883e
SH		 1765static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1766{
1767 struct sky2_hw *hw = sky2->hw;
1768 unsigned port = sky2->port;
da4c1ff4 1769 u16 advert, lpa;
793b883e 1770
da4c1ff4 1771 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1772 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1773 if (lpa & PHY_M_AN_RF) {
1774 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1775 return -1;
1776 }
1777
793b883e
SH		 1778 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1779 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1780 sky2->netdev->name);
1781 return -1;
1782 }
1783
793b883e 1784 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1785 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1786
da4c1ff4
SH		 1787 /* Since the pause result bits seem to in different positions on
1788 * different chips. look at registers.
1789 */
1790 if (!sky2_is_copper(hw)) {
1791 /* Shift for bits in fiber PHY */
1792 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1793 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1794
1795 if (advert & ADVERTISE_1000XPAUSE)
1796 advert |= ADVERTISE_PAUSE_CAP;
1797 if (advert & ADVERTISE_1000XPSE_ASYM)
1798 advert |= ADVERTISE_PAUSE_ASYM;
1799 if (lpa & LPA_1000XPAUSE)
1800 lpa |= LPA_PAUSE_CAP;
1801 if (lpa & LPA_1000XPAUSE_ASYM)
1802 lpa |= LPA_PAUSE_ASYM;
1803 }
793b883e 1804
da4c1ff4
SH		 1805 sky2->flow_status = FC_NONE;
1806 if (advert & ADVERTISE_PAUSE_CAP) {
1807 if (lpa & LPA_PAUSE_CAP)
1808 sky2->flow_status = FC_BOTH;
1809 else if (advert & ADVERTISE_PAUSE_ASYM)
1810 sky2->flow_status = FC_RX;
1811 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1812 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1813 sky2->flow_status = FC_TX;
1814 }
793b883e 1815
16ad91e1 1816 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1817 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1818 sky2->flow_status = FC_NONE;
2eaba1a2 1819
da4c1ff4 1820 if (sky2->flow_status & FC_TX)
793b883e
SH		 1821 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1822 else
1823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1824
1825 return 0;
1826}
cd28ab6a 1827
e07b1aa8
SH		 1828/* Interrupt from PHY */
1829static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1830{
e07b1aa8
SH		 1831 struct net_device *dev = hw->dev[port];
1832 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1833 u16 istatus, phystat;
1834
ebc646f6
SH		 1835 if (!netif_running(dev))
1836 return;
1837
e07b1aa8
SH		 1838 spin_lock(&sky2->phy_lock);
1839 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1840 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1841
cd28ab6a
SH		 1842 if (netif_msg_intr(sky2))
1843 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1844 sky2->netdev->name, istatus, phystat);
1845
2eaba1a2 1846 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1847 if (sky2_autoneg_done(sky2, phystat) == 0)
1848 sky2_link_up(sky2);
1849 goto out;
1850 }
cd28ab6a 1851
793b883e
SH		 1852 if (istatus & PHY_M_IS_LSP_CHANGE)
1853 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1854
793b883e
SH		 1855 if (istatus & PHY_M_IS_DUP_CHANGE)
1856 sky2->duplex =
1857 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1858
793b883e
SH		 1859 if (istatus & PHY_M_IS_LST_CHANGE) {
1860 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1861 sky2_link_up(sky2);
793b883e
SH		 1862 else
1863 sky2_link_down(sky2);
cd28ab6a 1864 }
793b883e 1865out:
e07b1aa8 1866 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1867}
1868
302d1252 1869
62335ab0 1870/* Transmit timeout is only called if we are running, carrier is up
302d1252 1871 * and tx queue is full (stopped).
62335ab0 1872 * Called with netif_tx_lock held.
302d1252 1873 */
cd28ab6a
SH		 1874static void sky2_tx_timeout(struct net_device *dev)
1875{
1876 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1877 struct sky2_hw *hw = sky2->hw;
62335ab0 1878 u32 imask;
cd28ab6a
SH		 1879
1880 if (netif_msg_timer(sky2))
1881 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1882
8f24664d 1883 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1884 dev->name, sky2->tx_cons, sky2->tx_prod,
1885 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1886 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1887
62335ab0
SH		 1888 imask = sky2_read32(hw, B0_IMSK); /* block IRQ in hw */
1889 sky2_write32(hw, B0_IMSK, 0);
1890 sky2_read32(hw, B0_IMSK);
8f24664d 1891
62335ab0
SH		 1892 netif_poll_disable(hw->dev[0]); /* stop NAPI poll */
1893 synchronize_irq(hw->pdev->irq);
8cc048e3 1894
62335ab0
SH		 1895 netif_start_queue(dev); /* don't wakeup during flush */
1896 sky2_tx_complete(sky2, sky2->tx_prod); /* Flush transmit queue */
8f24664d 1897
62335ab0 1898 sky2_write32(hw, B0_IMSK, imask);
8f24664d 1899
62335ab0 1900 sky2_phy_reinit(sky2); /* this clears flow control etc */
cd28ab6a
SH		 1901}
1902
1903static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1904{
6b1a3aef
SH		 1905 struct sky2_port *sky2 = netdev_priv(dev);
1906 struct sky2_hw *hw = sky2->hw;
1907 int err;
1908 u16 ctl, mode;
e07b1aa8 1909 u32 imask;
cd28ab6a
SH		 1910
1911 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1912 return -EINVAL;
1913
4a50a876 1914 /* TSO on Yukon Ultra and MTU > 1500 not supported */
5a5b1ea0 1915 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
4a50a876 1916 dev->features &= ~NETIF_F_TSO;
5a5b1ea0 1917
6b1a3aef
SH		 1918 if (!netif_running(dev)) {
1919 dev->mtu = new_mtu;
1920 return 0;
1921 }
1922
e07b1aa8 1923 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1924 sky2_write32(hw, B0_IMSK, 0);
1925
018d1c66
SH		 1926 dev->trans_start = jiffies; /* prevent tx timeout */
1927 netif_stop_queue(dev);
1928 netif_poll_disable(hw->dev[0]);
1929
e07b1aa8
SH		 1930 synchronize_irq(hw->pdev->irq);
1931
6b1a3aef
SH		 1932 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1933 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1934 sky2_rx_stop(sky2);
1935 sky2_rx_clean(sky2);
cd28ab6a
SH		 1936
1937 dev->mtu = new_mtu;
14d0263f 1938
6b1a3aef
SH		 1939 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1940 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1941
1942 if (dev->mtu > ETH_DATA_LEN)
1943 mode |= GM_SMOD_JUMBO_ENA;
1944
1945 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1946
6b1a3aef 1947 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1948
6b1a3aef 1949 err = sky2_rx_start(sky2);
e07b1aa8 1950 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1951
1b537565
SH		 1952 if (err)
1953 dev_close(dev);
1954 else {
1955 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1956
1957 netif_poll_enable(hw->dev[0]);
1958 netif_wake_queue(dev);
1959 }
1960
cd28ab6a
SH		 1961 return err;
1962}
1963
14d0263f
SH		 1964/* For small just reuse existing skb for next receive */
1965static struct sk_buff *receive_copy(struct sky2_port *sky2,
1966 const struct rx_ring_info *re,
1967 unsigned length)
1968{
1969 struct sk_buff *skb;
1970
1971 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1972 if (likely(skb)) {
1973 skb_reserve(skb, 2);
1974 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1975 length, PCI_DMA_FROMDEVICE);
1976 memcpy(skb->data, re->skb->data, length);
1977 skb->ip_summed = re->skb->ip_summed;
1978 skb->csum = re->skb->csum;
1979 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1980 length, PCI_DMA_FROMDEVICE);
1981 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1982 skb_put(skb, length);
14d0263f
SH		 1983 }
1984 return skb;
1985}
1986
1987/* Adjust length of skb with fragments to match received data */
1988static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1989 unsigned int length)
1990{
1991 int i, num_frags;
1992 unsigned int size;
1993
1994 /* put header into skb */
1995 size = min(length, hdr_space);
1996 skb->tail += size;
1997 skb->len += size;
1998 length -= size;
1999
2000 num_frags = skb_shinfo(skb)->nr_frags;
2001 for (i = 0; i < num_frags; i++) {
2002 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2003
2004 if (length == 0) {
2005 /* don't need this page */
2006 __free_page(frag->page);
2007 --skb_shinfo(skb)->nr_frags;
2008 } else {
2009 size = min(length, (unsigned) PAGE_SIZE);
2010
2011 frag->size = size;
2012 skb->data_len += size;
2013 skb->truesize += size;
2014 skb->len += size;
2015 length -= size;
2016 }
2017 }
2018}
2019
2020/* Normal packet - take skb from ring element and put in a new one */
2021static struct sk_buff *receive_new(struct sky2_port *sky2,
2022 struct rx_ring_info *re,
2023 unsigned int length)
2024{
2025 struct sk_buff *skb, *nskb;
2026 unsigned hdr_space = sky2->rx_data_size;
2027
2028 pr_debug(PFX "receive new length=%d\n", length);
2029
2030 /* Don't be tricky about reusing pages (yet) */
2031 nskb = sky2_rx_alloc(sky2);
2032 if (unlikely(!nskb))
2033 return NULL;
2034
2035 skb = re->skb;
2036 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2037
2038 prefetch(skb->data);
2039 re->skb = nskb;
2040 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2041
2042 if (skb_shinfo(skb)->nr_frags)
2043 skb_put_frags(skb, hdr_space, length);
2044 else
489b10c1 2045 skb_put(skb, length);
14d0263f
SH		 2046 return skb;
2047}
2048
cd28ab6a
SH		 2049/*
2050 * Receive one packet.
d571b694 2051 * For larger packets, get new buffer.
cd28ab6a 2052 */
497d7c86 2053static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2054 u16 length, u32 status)
2055{
497d7c86 2056 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2057 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2058 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2059
2060 if (unlikely(netif_msg_rx_status(sky2)))
2061 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2062 dev->name, sky2->rx_next, status, length);
cd28ab6a 2063
793b883e 2064 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2065 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2066
42eeea01 2067 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2068 goto error;
2069
42eeea01
SH		 2070 if (!(status & GMR_FS_RX_OK))
2071 goto resubmit;
2072
497d7c86 2073 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2074 goto oversize;
2075
14d0263f
SH		 2076 if (length < copybreak)
2077 skb = receive_copy(sky2, re, length);
2078 else
2079 skb = receive_new(sky2, re, length);
793b883e 2080resubmit:
14d0263f 2081 sky2_rx_submit(sky2, re);
79e57d32 2082
cd28ab6a
SH		 2083 return skb;
2084
6e15b712
SH		 2085oversize:
2086 ++sky2->net_stats.rx_over_errors;
2087 goto resubmit;
2088
cd28ab6a 2089error:
6e15b712 2090 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2091 if (status & GMR_FS_RX_FF_OV) {
2092 sky2->net_stats.rx_fifo_errors++;
2093 goto resubmit;
2094 }
6e15b712 2095
3be92a70 2096 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2097 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2098 dev->name, status, length);
793b883e
SH		 2099
2100 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2101 sky2->net_stats.rx_length_errors++;
2102 if (status & GMR_FS_FRAGMENT)
2103 sky2->net_stats.rx_frame_errors++;
2104 if (status & GMR_FS_CRC_ERR)
2105 sky2->net_stats.rx_crc_errors++;
79e57d32 2106
793b883e 2107 goto resubmit;
cd28ab6a
SH		 2108}
2109
e07b1aa8
SH		 2110/* Transmit complete */
2111static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2112{
e07b1aa8 2113 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2114
e07b1aa8 2115 if (netif_running(dev)) {
2bb8c262 2116 netif_tx_lock(dev);
e07b1aa8 2117 sky2_tx_complete(sky2, last);
2bb8c262 2118 netif_tx_unlock(dev);
2224795d 2119 }
cd28ab6a
SH		 2120}
2121
e07b1aa8
SH		 2122/* Process status response ring */
2123static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2124{
22e11703 2125 struct sky2_port *sky2;
e07b1aa8 2126 int work_done = 0;
22e11703 2127 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2128 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2129
af2a58ac 2130 rmb();
bea86103 2131
e71ebd73 2132 while (hw->st_idx != hwidx) {
13210ce5
SH		 2133 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2134 struct net_device *dev;
cd28ab6a 2135 struct sk_buff *skb;
cd28ab6a
SH		 2136 u32 status;
2137 u16 length;
2138
cb5d9547 2139 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2140
e71ebd73
SH		 2141 BUG_ON(le->link >= 2);
2142 dev = hw->dev[le->link];
13210ce5
SH		 2143
2144 sky2 = netdev_priv(dev);
f65b138c
SH		 2145 length = le16_to_cpu(le->length);
2146 status = le32_to_cpu(le->status);
cd28ab6a 2147
e71ebd73 2148 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2149 case OP_RXSTAT:
497d7c86 2150 skb = sky2_receive(dev, length, status);
d1f13708 2151 if (!skb)
5df79111 2152 goto force_update;
13210ce5 2153
13210ce5 2154 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2155 sky2->net_stats.rx_packets++;
2156 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2157 dev->last_rx = jiffies;
2158
d1f13708
SH		 2159#ifdef SKY2_VLAN_TAG_USED
2160 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2161 vlan_hwaccel_receive_skb(skb,
2162 sky2->vlgrp,
2163 be16_to_cpu(sky2->rx_tag));
2164 } else
2165#endif
cd28ab6a 2166 netif_receive_skb(skb);
13210ce5 2167
22e11703
SH		 2168 /* Update receiver after 16 frames */
2169 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2170force_update:
2171 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2172 buf_write[le->link] = 0;
2173 }
2174
2175 /* Stop after net poll weight */
13210ce5
SH		 2176 if (++work_done >= to_do)
2177 goto exit_loop;
cd28ab6a
SH		 2178 break;
2179
d1f13708
SH		 2180#ifdef SKY2_VLAN_TAG_USED
2181 case OP_RXVLAN:
2182 sky2->rx_tag = length;
2183 break;
2184
2185 case OP_RXCHKSVLAN:
2186 sky2->rx_tag = length;
2187 /* fall through */
2188#endif
cd28ab6a 2189 case OP_RXCHKS:
d11c13e7 2190 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2191 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2192 skb->csum = status & 0xffff;
cd28ab6a
SH		 2193 break;
2194
2195 case OP_TXINDEXLE:
13b97b74 2196 /* TX index reports status for both ports */
f55925d7
SH		 2197 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2198 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2199 if (hw->dev[1])
2200 sky2_tx_done(hw->dev[1],
2201 ((status >> 24) & 0xff)
2202 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2203 break;
2204
cd28ab6a
SH		 2205 default:
2206 if (net_ratelimit())
793b883e 2207 printk(KERN_WARNING PFX
e71ebd73
SH		 2208 "unknown status opcode 0x%x\n", le->opcode);
2209 goto exit_loop;
cd28ab6a 2210 }
13210ce5 2211 }
cd28ab6a 2212
fe2a24df
SH		 2213 /* Fully processed status ring so clear irq */
2214 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2215
13210ce5 2216exit_loop:
22e11703
SH		 2217 if (buf_write[0]) {
2218 sky2 = netdev_priv(hw->dev[0]);
2219 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2220 }
2221
2222 if (buf_write[1]) {
2223 sky2 = netdev_priv(hw->dev[1]);
2224 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2225 }
2226
e07b1aa8 2227 return work_done;
cd28ab6a
SH		 2228}
2229
2230static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2231{
2232 struct net_device *dev = hw->dev[port];
2233
3be92a70
SH		 2234 if (net_ratelimit())
2235 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2236 dev->name, status);
cd28ab6a
SH		 2237
2238 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2239 if (net_ratelimit())
2240 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2241 dev->name);
cd28ab6a
SH		 2242 /* Clear IRQ */
2243 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2244 }
2245
2246 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2249 dev->name);
cd28ab6a
SH		 2250
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2257 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2258 }
2259
2260 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2263 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2264 }
2265
2266 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2269 dev->name);
cd28ab6a
SH		 2270 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2271 }
2272}
2273
2274static void sky2_hw_intr(struct sky2_hw *hw)
2275{
2276 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2277
793b883e 2278 if (status & Y2_IS_TIST_OV)
cd28ab6a 2279 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2280
2281 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2282 u16 pci_err;
2283
56a645cc 2284 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2285 if (net_ratelimit())
b02a9258
SH		 2286 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2287 pci_err);
cd28ab6a
SH		 2288
2289 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2290 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2291 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2292 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2293 }
2294
2295 if (status & Y2_IS_PCI_EXP) {
d571b694 2296 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2297 u32 pex_err;
2298
7bd656d1 2299 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2300
3be92a70 2301 if (net_ratelimit())
b02a9258
SH		 2302 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2303 pex_err);
cd28ab6a
SH		 2304
2305 /* clear the interrupt */
2306 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2307 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2308 0xffffffffUL);
cd28ab6a
SH		 2309 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2310
7bd656d1 2311 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2312 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2313 hwmsk &= ~Y2_IS_PCI_EXP;
2314 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2315 }
2316 }
2317
2318 if (status & Y2_HWE_L1_MASK)
2319 sky2_hw_error(hw, 0, status);
2320 status >>= 8;
2321 if (status & Y2_HWE_L1_MASK)
2322 sky2_hw_error(hw, 1, status);
2323}
2324
2325static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2326{
2327 struct net_device *dev = hw->dev[port];
2328 struct sky2_port *sky2 = netdev_priv(dev);
2329 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2330
2331 if (netif_msg_intr(sky2))
2332 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2333 dev->name, status);
2334
2335 if (status & GM_IS_RX_FF_OR) {
2336 ++sky2->net_stats.rx_fifo_errors;
2337 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2338 }
2339
2340 if (status & GM_IS_TX_FF_UR) {
2341 ++sky2->net_stats.tx_fifo_errors;
2342 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2343 }
cd28ab6a
SH		 2344}
2345
d257924e
SH		 2346/* This should never happen it is a fatal situation */
2347static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2348 const char *rxtx, u32 mask)
2349{
2350 struct net_device *dev = hw->dev[port];
2351 struct sky2_port *sky2 = netdev_priv(dev);
2352 u32 imask;
2353
2354 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2355 dev ? dev->name : "<not registered>", rxtx);
2356
2357 imask = sky2_read32(hw, B0_IMSK);
2358 imask &= ~mask;
2359 sky2_write32(hw, B0_IMSK, imask);
2360
2361 if (dev) {
2362 spin_lock(&sky2->phy_lock);
2363 sky2_link_down(sky2);
2364 spin_unlock(&sky2->phy_lock);
2365 }
2366}
cd28ab6a 2367
d27ed387
SH		 2368/* If idle then force a fake soft NAPI poll once a second
2369 * to work around cases where sharing an edge triggered interrupt.
2370 */
eb35cf60
SH		 2371static inline void sky2_idle_start(struct sky2_hw *hw)
2372{
2373 if (idle_timeout > 0)
2374 mod_timer(&hw->idle_timer,
2375 jiffies + msecs_to_jiffies(idle_timeout));
2376}
2377
d27ed387
SH		 2378static void sky2_idle(unsigned long arg)
2379{
01bd7564
SH		 2380 struct sky2_hw *hw = (struct sky2_hw *) arg;
2381 struct net_device *dev = hw->dev[0];
d27ed387 2382
d27ed387
SH		 2383 if (__netif_rx_schedule_prep(dev))
2384 __netif_rx_schedule(dev);
01bd7564
SH		 2385
2386 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2387}
2388
2389
e07b1aa8 2390static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2391{
e07b1aa8
SH		 2392 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2393 int work_limit = min(dev0->quota, *budget);
2394 int work_done = 0;
fb2690a9 2395 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2396
1e5f1283
SH		 2397 if (status & Y2_IS_HW_ERR)
2398 sky2_hw_intr(hw);
d257924e 2399
1e5f1283
SH		 2400 if (status & Y2_IS_IRQ_PHY1)
2401 sky2_phy_intr(hw, 0);
cd28ab6a 2402
1e5f1283
SH		 2403 if (status & Y2_IS_IRQ_PHY2)
2404 sky2_phy_intr(hw, 1);
cd28ab6a 2405
1e5f1283
SH		 2406 if (status & Y2_IS_IRQ_MAC1)
2407 sky2_mac_intr(hw, 0);
cd28ab6a 2408
1e5f1283
SH		 2409 if (status & Y2_IS_IRQ_MAC2)
2410 sky2_mac_intr(hw, 1);
cd28ab6a 2411
1e5f1283
SH		 2412 if (status & Y2_IS_CHK_RX1)
2413 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2414
1e5f1283
SH		 2415 if (status & Y2_IS_CHK_RX2)
2416 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2417
1e5f1283
SH		 2418 if (status & Y2_IS_CHK_TXA1)
2419 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2420
1e5f1283
SH		 2421 if (status & Y2_IS_CHK_TXA2)
2422 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2423
1e5f1283 2424 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2425 if (work_done < work_limit) {
2426 netif_rx_complete(dev0);
86fba634 2427
fe2a24df
SH		 2428 sky2_read32(hw, B0_Y2_SP_LISR);
2429 return 0;
2430 } else {
2431 *budget -= work_done;
2432 dev0->quota -= work_done;
1e5f1283 2433 return 1;
fe2a24df 2434 }
e07b1aa8
SH		 2435}
2436
7d12e780 2437static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2438{
2439 struct sky2_hw *hw = dev_id;
2440 struct net_device *dev0 = hw->dev[0];
2441 u32 status;
2442
2443 /* Reading this mask interrupts as side effect */
2444 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2445 if (status == 0 || status == ~0)
2446 return IRQ_NONE;
793b883e 2447
e07b1aa8
SH		 2448 prefetch(&hw->st_le[hw->st_idx]);
2449 if (likely(__netif_rx_schedule_prep(dev0)))
2450 __netif_rx_schedule(dev0);
793b883e 2451
cd28ab6a
SH		 2452 return IRQ_HANDLED;
2453}
2454
2455#ifdef CONFIG_NET_POLL_CONTROLLER
2456static void sky2_netpoll(struct net_device *dev)
2457{
2458 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2459 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2460
88d11360
SH		 2461 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2462 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2463}
2464#endif
2465
2466/* Chip internal frequency for clock calculations */
fb17358f 2467static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2468{
793b883e 2469 switch (hw->chip_id) {
cd28ab6a 2470 case CHIP_ID_YUKON_EC:
5a5b1ea0 2471 case CHIP_ID_YUKON_EC_U:
93745494 2472 case CHIP_ID_YUKON_EX:
fb17358f 2473 return 125; /* 125 Mhz */
cd28ab6a 2474 case CHIP_ID_YUKON_FE:
fb17358f 2475 return 100; /* 100 Mhz */
793b883e 2476 default: /* YUKON_XL */
fb17358f 2477 return 156; /* 156 Mhz */
cd28ab6a
SH		 2478 }
2479}
2480
fb17358f 2481static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2482{
fb17358f 2483 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2484}
2485
fb17358f 2486static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2487{
fb17358f 2488 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2489}
2490
fb17358f 2491
e3173832 2492static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2493{
b89165f2 2494 u8 t8;
cd28ab6a 2495
cd28ab6a 2496 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2497
cd28ab6a
SH		 2498 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2499 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2500 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2501 hw->chip_id);
cd28ab6a
SH		 2502 return -EOPNOTSUPP;
2503 }
2504
93745494
SH		 2505 if (hw->chip_id == CHIP_ID_YUKON_EX)
2506 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2507 "Please report success or failure to <netdev@vger.kernel.org>\n");
2508
2509 /* Make sure and enable all clocks */
2510 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2511 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2512
290d4de5
SH		 2513 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2514
2515 /* This rev is really old, and requires untested workarounds */
2516 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2517 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2518 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2519 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2520 return -EOPNOTSUPP;
2521 }
2522
e3173832
SH		 2523 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2524 hw->ports = 1;
2525 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2526 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2527 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2528 ++hw->ports;
2529 }
2530
2531 return 0;
2532}
2533
2534static void sky2_reset(struct sky2_hw *hw)
2535{
2536 u16 status;
2537 int i;
2538
cd28ab6a
SH		 2539 /* disable ASF */
2540 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
93745494
SH		 2541 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2542 status = sky2_read16(hw, HCU_CCSR);
2543 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2544 HCU_CCSR_UC_STATE_MSK);
2545 sky2_write16(hw, HCU_CCSR, status);
2546 } else
2547 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
cd28ab6a
SH		 2548 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2549 }
2550
2551 /* do a SW reset */
2552 sky2_write8(hw, B0_CTST, CS_RST_SET);
2553 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2554
2555 /* clear PCI errors, if any */
56a645cc 2556 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2557
cd28ab6a 2558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2559 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2560
cd28ab6a
SH		 2561
2562 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2563
2564 /* clear any PEX errors */
7bd656d1
SH		 2565 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2566 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2567
cd28ab6a 2568
ae306cca 2569 sky2_power_on(hw);
cd28ab6a
SH		 2570
2571 for (i = 0; i < hw->ports; i++) {
2572 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2573 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2574 }
2575
2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2577
793b883e
SH		 2578 /* Clear I2C IRQ noise */
2579 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2580
2581 /* turn off hardware timer (unused) */
2582 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2583 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2584
cd28ab6a
SH		 2585 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2586
69634ee7
SH		 2587 /* Turn off descriptor polling */
2588 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2589
2590 /* Turn off receive timestamp */
2591 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2592 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2593
2594 /* enable the Tx Arbiters */
2595 for (i = 0; i < hw->ports; i++)
2596 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2597
2598 /* Initialize ram interface */
2599 for (i = 0; i < hw->ports; i++) {
793b883e 2600 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2601
2602 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2603 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2604 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2605 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2607 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2614 }
2615
7bd656d1 2616 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2617
cd28ab6a 2618 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2619 sky2_gmac_reset(hw, i);
cd28ab6a 2620
cd28ab6a
SH		 2621 memset(hw->st_le, 0, STATUS_LE_BYTES);
2622 hw->st_idx = 0;
2623
2624 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2625 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2626
2627 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2628 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2629
2630 /* Set the list last index */
793b883e 2631 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2632
290d4de5
SH		 2633 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2634 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2635
290d4de5
SH		 2636 /* set Status-FIFO ISR watermark */
2637 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2638 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2639 else
2640 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2641
290d4de5 2642 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2643 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2644 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2645
793b883e 2646 /* enable status unit */
cd28ab6a
SH		 2647 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2648
2649 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2650 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2651 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2652}
2653
2654static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2655{
2656 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2657}
2658
2659static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2660{
2661 const struct sky2_port *sky2 = netdev_priv(dev);
2662
2663 wol->supported = sky2_wol_supported(sky2->hw);
2664 wol->wolopts = sky2->wol;
2665}
2666
2667static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2668{
2669 struct sky2_port *sky2 = netdev_priv(dev);
2670 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2671
e3173832
SH		 2672 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2673 return -EOPNOTSUPP;
2674
2675 sky2->wol = wol->wolopts;
2676
2677 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2678 sky2_write32(hw, B0_CTST, sky2->wol
2679 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2680
2681 if (!netif_running(dev))
2682 sky2_wol_init(sky2);
cd28ab6a
SH		 2683 return 0;
2684}
2685
28bd181a 2686static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2687{
b89165f2
SH		 2688 if (sky2_is_copper(hw)) {
2689 u32 modes = SUPPORTED_10baseT_Half
2690 | SUPPORTED_10baseT_Full
2691 | SUPPORTED_100baseT_Half
2692 | SUPPORTED_100baseT_Full
2693 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2694
2695 if (hw->chip_id != CHIP_ID_YUKON_FE)
2696 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2697 | SUPPORTED_1000baseT_Full;
2698 return modes;
cd28ab6a 2699 } else
b89165f2
SH		 2700 return SUPPORTED_1000baseT_Half
2701 | SUPPORTED_1000baseT_Full
2702 | SUPPORTED_Autoneg
2703 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2704}
2705
793b883e 2706static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2707{
2708 struct sky2_port *sky2 = netdev_priv(dev);
2709 struct sky2_hw *hw = sky2->hw;
2710
2711 ecmd->transceiver = XCVR_INTERNAL;
2712 ecmd->supported = sky2_supported_modes(hw);
2713 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2714 if (sky2_is_copper(hw)) {
cd28ab6a 2715 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2716 | SUPPORTED_10baseT_Full
2717 | SUPPORTED_100baseT_Half
2718 | SUPPORTED_100baseT_Full
2719 | SUPPORTED_1000baseT_Half
2720 | SUPPORTED_1000baseT_Full
2721 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2722 ecmd->port = PORT_TP;
b89165f2
SH		 2723 ecmd->speed = sky2->speed;
2724 } else {
2725 ecmd->speed = SPEED_1000;
cd28ab6a 2726 ecmd->port = PORT_FIBRE;
b89165f2 2727 }
cd28ab6a
SH		 2728
2729 ecmd->advertising = sky2->advertising;
2730 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2731 ecmd->duplex = sky2->duplex;
2732 return 0;
2733}
2734
2735static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2736{
2737 struct sky2_port *sky2 = netdev_priv(dev);
2738 const struct sky2_hw *hw = sky2->hw;
2739 u32 supported = sky2_supported_modes(hw);
2740
2741 if (ecmd->autoneg == AUTONEG_ENABLE) {
2742 ecmd->advertising = supported;
2743 sky2->duplex = -1;
2744 sky2->speed = -1;
2745 } else {
2746 u32 setting;
2747
793b883e 2748 switch (ecmd->speed) {
cd28ab6a
SH		 2749 case SPEED_1000:
2750 if (ecmd->duplex == DUPLEX_FULL)
2751 setting = SUPPORTED_1000baseT_Full;
2752 else if (ecmd->duplex == DUPLEX_HALF)
2753 setting = SUPPORTED_1000baseT_Half;
2754 else
2755 return -EINVAL;
2756 break;
2757 case SPEED_100:
2758 if (ecmd->duplex == DUPLEX_FULL)
2759 setting = SUPPORTED_100baseT_Full;
2760 else if (ecmd->duplex == DUPLEX_HALF)
2761 setting = SUPPORTED_100baseT_Half;
2762 else
2763 return -EINVAL;
2764 break;
2765
2766 case SPEED_10:
2767 if (ecmd->duplex == DUPLEX_FULL)
2768 setting = SUPPORTED_10baseT_Full;
2769 else if (ecmd->duplex == DUPLEX_HALF)
2770 setting = SUPPORTED_10baseT_Half;
2771 else
2772 return -EINVAL;
2773 break;
2774 default:
2775 return -EINVAL;
2776 }
2777
2778 if ((setting & supported) == 0)
2779 return -EINVAL;
2780
2781 sky2->speed = ecmd->speed;
2782 sky2->duplex = ecmd->duplex;
2783 }
2784
2785 sky2->autoneg = ecmd->autoneg;
2786 sky2->advertising = ecmd->advertising;
2787
1b537565
SH		 2788 if (netif_running(dev))
2789 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2790
2791 return 0;
2792}
2793
2794static void sky2_get_drvinfo(struct net_device *dev,
2795 struct ethtool_drvinfo *info)
2796{
2797 struct sky2_port *sky2 = netdev_priv(dev);
2798
2799 strcpy(info->driver, DRV_NAME);
2800 strcpy(info->version, DRV_VERSION);
2801 strcpy(info->fw_version, "N/A");
2802 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2803}
2804
2805static const struct sky2_stat {
793b883e
SH		 2806 char name[ETH_GSTRING_LEN];
2807 u16 offset;
cd28ab6a
SH		 2808} sky2_stats[] = {
2809 { "tx_bytes", GM_TXO_OK_HI },
2810 { "rx_bytes", GM_RXO_OK_HI },
2811 { "tx_broadcast", GM_TXF_BC_OK },
2812 { "rx_broadcast", GM_RXF_BC_OK },
2813 { "tx_multicast", GM_TXF_MC_OK },
2814 { "rx_multicast", GM_RXF_MC_OK },
2815 { "tx_unicast", GM_TXF_UC_OK },
2816 { "rx_unicast", GM_RXF_UC_OK },
2817 { "tx_mac_pause", GM_TXF_MPAUSE },
2818 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2819 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2820 { "late_collision",GM_TXF_LAT_COL },
2821 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2822 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2823 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2824
d2604540 2825 { "rx_short", GM_RXF_SHT },
cd28ab6a 2826 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2827 { "rx_64_byte_packets", GM_RXF_64B },
2828 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2829 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2830 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2831 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2832 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2833 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2834 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2835 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2836 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2837 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2838
2839 { "tx_64_byte_packets", GM_TXF_64B },
2840 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2841 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2842 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2843 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2844 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2845 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2846 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2847};
2848
cd28ab6a
SH		 2849static u32 sky2_get_rx_csum(struct net_device *dev)
2850{
2851 struct sky2_port *sky2 = netdev_priv(dev);
2852
2853 return sky2->rx_csum;
2854}
2855
2856static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2857{
2858 struct sky2_port *sky2 = netdev_priv(dev);
2859
2860 sky2->rx_csum = data;
793b883e 2861
cd28ab6a
SH		 2862 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2863 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2864
2865 return 0;
2866}
2867
2868static u32 sky2_get_msglevel(struct net_device *netdev)
2869{
2870 struct sky2_port *sky2 = netdev_priv(netdev);
2871 return sky2->msg_enable;
2872}
2873
9a7ae0a9
SH		 2874static int sky2_nway_reset(struct net_device *dev)
2875{
2876 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2877
16ad91e1 2878 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2879 return -EINVAL;
2880
1b537565 2881 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2882
2883 return 0;
2884}
2885
793b883e 2886static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2887{
2888 struct sky2_hw *hw = sky2->hw;
2889 unsigned port = sky2->port;
2890 int i;
2891
2892 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2893 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2894 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2895 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2896
793b883e 2897 for (i = 2; i < count; i++)
cd28ab6a
SH		 2898 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2899}
2900
cd28ab6a
SH		 2901static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2902{
2903 struct sky2_port *sky2 = netdev_priv(netdev);
2904 sky2->msg_enable = value;
2905}
2906
2907static int sky2_get_stats_count(struct net_device *dev)
2908{
2909 return ARRAY_SIZE(sky2_stats);
2910}
2911
2912static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2913 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2914{
2915 struct sky2_port *sky2 = netdev_priv(dev);
2916
793b883e 2917 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2918}
2919
793b883e 2920static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2921{
2922 int i;
2923
2924 switch (stringset) {
2925 case ETH_SS_STATS:
2926 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2927 memcpy(data + i * ETH_GSTRING_LEN,
2928 sky2_stats[i].name, ETH_GSTRING_LEN);
2929 break;
2930 }
2931}
2932
cd28ab6a
SH		 2933static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2934{
2935 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2936 return &sky2->net_stats;
2937}
2938
2939static int sky2_set_mac_address(struct net_device *dev, void *p)
2940{
2941 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2942 struct sky2_hw *hw = sky2->hw;
2943 unsigned port = sky2->port;
2944 const struct sockaddr *addr = p;
cd28ab6a
SH		 2945
2946 if (!is_valid_ether_addr(addr->sa_data))
2947 return -EADDRNOTAVAIL;
2948
cd28ab6a 2949 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2950 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2951 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2952 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2953 dev->dev_addr, ETH_ALEN);
1b537565 2954
a8ab1ec0
SH		 2955 /* virtual address for data */
2956 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2957
2958 /* physical address: used for pause frames */
2959 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2960
2961 return 0;
cd28ab6a
SH		 2962}
2963
a052b52f
SH		 2964static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2965{
2966 u32 bit;
2967
2968 bit = ether_crc(ETH_ALEN, addr) & 63;
2969 filter[bit >> 3] |= 1 << (bit & 7);
2970}
2971
cd28ab6a
SH		 2972static void sky2_set_multicast(struct net_device *dev)
2973{
2974 struct sky2_port *sky2 = netdev_priv(dev);
2975 struct sky2_hw *hw = sky2->hw;
2976 unsigned port = sky2->port;
2977 struct dev_mc_list *list = dev->mc_list;
2978 u16 reg;
2979 u8 filter[8];
a052b52f
SH		 2980 int rx_pause;
2981 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2982
a052b52f 2983 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2984 memset(filter, 0, sizeof(filter));
2985
2986 reg = gma_read16(hw, port, GM_RX_CTRL);
2987 reg |= GM_RXCR_UCF_ENA;
2988
d571b694 2989 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2990 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2991 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2992 memset(filter, 0xff, sizeof(filter));
a052b52f 2993 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2994 reg &= ~GM_RXCR_MCF_ENA;
2995 else {
2996 int i;
2997 reg |= GM_RXCR_MCF_ENA;
2998
a052b52f
SH		 2999 if (rx_pause)
3000 sky2_add_filter(filter, pause_mc_addr);
3001
3002 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3003 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3004 }
3005
cd28ab6a 3006 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3007 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3008 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3009 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3010 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3011 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3012 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3013 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3014
3015 gma_write16(hw, port, GM_RX_CTRL, reg);
3016}
3017
3018/* Can have one global because blinking is controlled by
3019 * ethtool and that is always under RTNL mutex
3020 */
91c86df5 3021static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3022{
793b883e
SH		 3023 u16 pg;
3024
793b883e
SH		 3025 switch (hw->chip_id) {
3026 case CHIP_ID_YUKON_XL:
3027 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3028 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3029 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3030 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3031 PHY_M_LEDC_INIT_CTRL(7) |
3032 PHY_M_LEDC_STA1_CTRL(7) |
3033 PHY_M_LEDC_STA0_CTRL(7))
3034 : 0);
3035
3036 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3037 break;
3038
3039 default:
3040 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3041 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3042 on ? PHY_M_LED_ALL : 0);
793b883e 3043 }
cd28ab6a
SH		 3044}
3045
3046/* blink LED's for finding board */
3047static int sky2_phys_id(struct net_device *dev, u32 data)
3048{
3049 struct sky2_port *sky2 = netdev_priv(dev);
3050 struct sky2_hw *hw = sky2->hw;
3051 unsigned port = sky2->port;
793b883e 3052 u16 ledctrl, ledover = 0;
cd28ab6a 3053 long ms;
91c86df5 3054 int interrupted;
cd28ab6a
SH		 3055 int onoff = 1;
3056
793b883e 3057 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3058 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3059 else
3060 ms = data * 1000;
3061
3062 /* save initial values */
e07b1aa8 3063 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3064 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3065 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3066 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3067 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3068 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3069 } else {
3070 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3071 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3072 }
cd28ab6a 3073
91c86df5
SH		 3074 interrupted = 0;
3075 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3076 sky2_led(hw, port, onoff);
3077 onoff = !onoff;
3078
e07b1aa8 3079 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3080 interrupted = msleep_interruptible(250);
e07b1aa8 3081 spin_lock_bh(&sky2->phy_lock);
91c86df5 3082
cd28ab6a
SH		 3083 ms -= 250;
3084 }
3085
3086 /* resume regularly scheduled programming */
793b883e
SH		 3087 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3088 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3089 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3090 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3091 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3092 } else {
3093 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3094 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3095 }
e07b1aa8 3096 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3097
3098 return 0;
3099}
3100
3101static void sky2_get_pauseparam(struct net_device *dev,
3102 struct ethtool_pauseparam *ecmd)
3103{
3104 struct sky2_port *sky2 = netdev_priv(dev);
3105
16ad91e1
SH		 3106 switch (sky2->flow_mode) {
3107 case FC_NONE:
3108 ecmd->tx_pause = ecmd->rx_pause = 0;
3109 break;
3110 case FC_TX:
3111 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3112 break;
3113 case FC_RX:
3114 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3115 break;
3116 case FC_BOTH:
3117 ecmd->tx_pause = ecmd->rx_pause = 1;
3118 }
3119
cd28ab6a
SH		 3120 ecmd->autoneg = sky2->autoneg;
3121}
3122
3123static int sky2_set_pauseparam(struct net_device *dev,
3124 struct ethtool_pauseparam *ecmd)
3125{
3126 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3127
3128 sky2->autoneg = ecmd->autoneg;
16ad91e1 3129 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3130
16ad91e1
SH		 3131 if (netif_running(dev))
3132 sky2_phy_reinit(sky2);
cd28ab6a 3133
2eaba1a2 3134 return 0;
cd28ab6a
SH		 3135}
3136
fb17358f
SH		 3137static int sky2_get_coalesce(struct net_device *dev,
3138 struct ethtool_coalesce *ecmd)
3139{
3140 struct sky2_port *sky2 = netdev_priv(dev);
3141 struct sky2_hw *hw = sky2->hw;
3142
3143 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3144 ecmd->tx_coalesce_usecs = 0;
3145 else {
3146 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3147 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3148 }
3149 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3150
3151 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3152 ecmd->rx_coalesce_usecs = 0;
3153 else {
3154 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3155 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3156 }
3157 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3158
3159 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3160 ecmd->rx_coalesce_usecs_irq = 0;
3161 else {
3162 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3163 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3164 }
3165
3166 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3167
3168 return 0;
3169}
3170
3171/* Note: this affect both ports */
3172static int sky2_set_coalesce(struct net_device *dev,
3173 struct ethtool_coalesce *ecmd)
3174{
3175 struct sky2_port *sky2 = netdev_priv(dev);
3176 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3177 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3178
77b3d6a2
SH		 3179 if (ecmd->tx_coalesce_usecs > tmax ||
3180 ecmd->rx_coalesce_usecs > tmax ||
3181 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3182 return -EINVAL;
3183
ff81fbbe 3184 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3185 return -EINVAL;
ff81fbbe 3186 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3187 return -EINVAL;
ff81fbbe 3188 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3189 return -EINVAL;
3190
3191 if (ecmd->tx_coalesce_usecs == 0)
3192 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3193 else {
3194 sky2_write32(hw, STAT_TX_TIMER_INI,
3195 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3196 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3197 }
3198 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3199
3200 if (ecmd->rx_coalesce_usecs == 0)
3201 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3202 else {
3203 sky2_write32(hw, STAT_LEV_TIMER_INI,
3204 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3205 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3206 }
3207 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3208
3209 if (ecmd->rx_coalesce_usecs_irq == 0)
3210 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3211 else {
d28d4870 3212 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3213 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3214 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3215 }
3216 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3217 return 0;
3218}
3219
793b883e
SH		 3220static void sky2_get_ringparam(struct net_device *dev,
3221 struct ethtool_ringparam *ering)
3222{
3223 struct sky2_port *sky2 = netdev_priv(dev);
3224
3225 ering->rx_max_pending = RX_MAX_PENDING;
3226 ering->rx_mini_max_pending = 0;
3227 ering->rx_jumbo_max_pending = 0;
3228 ering->tx_max_pending = TX_RING_SIZE - 1;
3229
3230 ering->rx_pending = sky2->rx_pending;
3231 ering->rx_mini_pending = 0;
3232 ering->rx_jumbo_pending = 0;
3233 ering->tx_pending = sky2->tx_pending;
3234}
3235
3236static int sky2_set_ringparam(struct net_device *dev,
3237 struct ethtool_ringparam *ering)
3238{
3239 struct sky2_port *sky2 = netdev_priv(dev);
3240 int err = 0;
3241
3242 if (ering->rx_pending > RX_MAX_PENDING ||
3243 ering->rx_pending < 8 ||
3244 ering->tx_pending < MAX_SKB_TX_LE ||
3245 ering->tx_pending > TX_RING_SIZE - 1)
3246 return -EINVAL;
3247
3248 if (netif_running(dev))
3249 sky2_down(dev);
3250
3251 sky2->rx_pending = ering->rx_pending;
3252 sky2->tx_pending = ering->tx_pending;
3253
1b537565 3254 if (netif_running(dev)) {
793b883e 3255 err = sky2_up(dev);
1b537565
SH		 3256 if (err)
3257 dev_close(dev);
6ed995bb
SH		 3258 else
3259 sky2_set_multicast(dev);
1b537565 3260 }
793b883e
SH		 3261
3262 return err;
3263}
3264
793b883e
SH		 3265static int sky2_get_regs_len(struct net_device *dev)
3266{
6e4cbb34 3267 return 0x4000;
793b883e
SH		 3268}
3269
3270/*
3271 * Returns copy of control register region
6e4cbb34 3272 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3273 */
3274static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3275 void *p)
3276{
3277 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3278 const void __iomem *io = sky2->hw->regs;
793b883e 3279
6e4cbb34 3280 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3281 regs->version = 1;
6e4cbb34 3282 memset(p, 0, regs->len);
793b883e 3283
6e4cbb34
SH		 3284 memcpy_fromio(p, io, B3_RAM_ADDR);
3285
3286 memcpy_fromio(p + B3_RI_WTO_R1,
3287 io + B3_RI_WTO_R1,
3288 regs->len - B3_RI_WTO_R1);
793b883e 3289}
cd28ab6a 3290
7282d491 3291static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3292 .get_settings = sky2_get_settings,
3293 .set_settings = sky2_set_settings,
e3173832
SH		 3294 .get_drvinfo = sky2_get_drvinfo,
3295 .get_wol = sky2_get_wol,
3296 .set_wol = sky2_set_wol,
793b883e
SH		 3297 .get_msglevel = sky2_get_msglevel,
3298 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3299 .nway_reset = sky2_nway_reset,
793b883e
SH		 3300 .get_regs_len = sky2_get_regs_len,
3301 .get_regs = sky2_get_regs,
3302 .get_link = ethtool_op_get_link,
3303 .get_sg = ethtool_op_get_sg,
3304 .set_sg = ethtool_op_set_sg,
3305 .get_tx_csum = ethtool_op_get_tx_csum,
3306 .set_tx_csum = ethtool_op_set_tx_csum,
3307 .get_tso = ethtool_op_get_tso,
3308 .set_tso = ethtool_op_set_tso,
3309 .get_rx_csum = sky2_get_rx_csum,
3310 .set_rx_csum = sky2_set_rx_csum,
3311 .get_strings = sky2_get_strings,
fb17358f
SH		 3312 .get_coalesce = sky2_get_coalesce,
3313 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3314 .get_ringparam = sky2_get_ringparam,
3315 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3316 .get_pauseparam = sky2_get_pauseparam,
3317 .set_pauseparam = sky2_set_pauseparam,
793b883e 3318 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3319 .get_stats_count = sky2_get_stats_count,
3320 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3321 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3322};
3323
3324/* Initialize network device */
3325static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3326 unsigned port,
3327 int highmem, int wol)
cd28ab6a
SH		 3328{
3329 struct sky2_port *sky2;
3330 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3331
3332 if (!dev) {
b02a9258 3333 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3334 return NULL;
3335 }
3336
3337 SET_MODULE_OWNER(dev);
3338 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3339 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3340 dev->open = sky2_up;
3341 dev->stop = sky2_down;
ef743d33 3342 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3343 dev->hard_start_xmit = sky2_xmit_frame;
3344 dev->get_stats = sky2_get_stats;
3345 dev->set_multicast_list = sky2_set_multicast;
3346 dev->set_mac_address = sky2_set_mac_address;
3347 dev->change_mtu = sky2_change_mtu;
3348 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3349 dev->tx_timeout = sky2_tx_timeout;
3350 dev->watchdog_timeo = TX_WATCHDOG;
3351 if (port == 0)
3352 dev->poll = sky2_poll;
3353 dev->weight = NAPI_WEIGHT;
3354#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3355 /* Network console (only works on port 0)
3356 * because netpoll makes assumptions about NAPI
3357 */
3358 if (port == 0)
3359 dev->poll_controller = sky2_netpoll;
cd28ab6a 3360#endif
cd28ab6a
SH		 3361
3362 sky2 = netdev_priv(dev);
3363 sky2->netdev = dev;
3364 sky2->hw = hw;
3365 sky2->msg_enable = netif_msg_init(debug, default_msg);
3366
cd28ab6a
SH		 3367 /* Auto speed and flow control */
3368 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3369 sky2->flow_mode = FC_BOTH;
3370
cd28ab6a
SH		 3371 sky2->duplex = -1;
3372 sky2->speed = -1;
3373 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3374 sky2->rx_csum = 1;
e3173832 3375 sky2->wol = wol;
75d070c5 3376
e07b1aa8 3377 spin_lock_init(&sky2->phy_lock);
793b883e 3378 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3379 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3380
3381 hw->dev[port] = dev;
3382
3383 sky2->port = port;
3384
4a50a876 3385 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3386 if (highmem)
3387 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3388
d1f13708
SH		 3389#ifdef SKY2_VLAN_TAG_USED
3390 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3391 dev->vlan_rx_register = sky2_vlan_rx_register;
3392 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3393#endif
3394
cd28ab6a 3395 /* read the mac address */
793b883e 3396 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3397 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3398
3399 /* device is off until link detection */
3400 netif_carrier_off(dev);
3401 netif_stop_queue(dev);
3402
3403 return dev;
3404}
3405
28bd181a 3406static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3407{
3408 const struct sky2_port *sky2 = netdev_priv(dev);
3409
3410 if (netif_msg_probe(sky2))
3411 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3412 dev->name,
3413 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3414 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3415}
3416
fb2690a9 3417/* Handle software interrupt used during MSI test */
7d12e780 3418static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3419{
3420 struct sky2_hw *hw = dev_id;
3421 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3422
3423 if (status == 0)
3424 return IRQ_NONE;
3425
3426 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3427 hw->msi = 1;
fb2690a9
SH		 3428 wake_up(&hw->msi_wait);
3429 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3430 }
3431 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3432
3433 return IRQ_HANDLED;
3434}
3435
3436/* Test interrupt path by forcing a a software IRQ */
3437static int __devinit sky2_test_msi(struct sky2_hw *hw)
3438{
3439 struct pci_dev *pdev = hw->pdev;
3440 int err;
3441
bb507fe1
SH		 3442 init_waitqueue_head (&hw->msi_wait);
3443
fb2690a9
SH		 3444 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3445
b0a20ded 3446 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3447 if (err) {
b02a9258 3448 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3449 return err;
3450 }
3451
fb2690a9 3452 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3453 sky2_read8(hw, B0_CTST);
fb2690a9 3454
b0a20ded 3455 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3456
b0a20ded 3457 if (!hw->msi) {
fb2690a9 3458 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3459 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3460 "switching to INTx mode.\n");
fb2690a9
SH		 3461
3462 err = -EOPNOTSUPP;
3463 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3464 }
3465
3466 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3467 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3468
3469 free_irq(pdev->irq, hw);
3470
3471 return err;
3472}
3473
e3173832
SH		 3474static int __devinit pci_wake_enabled(struct pci_dev *dev)
3475{
3476 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3477 u16 value;
3478
3479 if (!pm)
3480 return 0;
3481 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3482 return 0;
3483 return value & PCI_PM_CTRL_PME_ENABLE;
3484}
3485
cd28ab6a
SH		 3486static int __devinit sky2_probe(struct pci_dev *pdev,
3487 const struct pci_device_id *ent)
3488{
7f60c64b 3489 struct net_device *dev;
cd28ab6a 3490 struct sky2_hw *hw;
e3173832 3491 int err, using_dac = 0, wol_default;
cd28ab6a 3492
793b883e
SH		 3493 err = pci_enable_device(pdev);
3494 if (err) {
b02a9258 3495 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3496 goto err_out;
3497 }
3498
793b883e
SH		 3499 err = pci_request_regions(pdev, DRV_NAME);
3500 if (err) {
b02a9258 3501 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3502 goto err_out;
cd28ab6a
SH		 3503 }
3504
3505 pci_set_master(pdev);
3506
d1f3d4dd
SH		 3507 if (sizeof(dma_addr_t) > sizeof(u32) &&
3508 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3509 using_dac = 1;
3510 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3511 if (err < 0) {
b02a9258
SH		 3512 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3513 "for consistent allocations\n");
d1f3d4dd
SH		 3514 goto err_out_free_regions;
3515 }
d1f3d4dd 3516 } else {
cd28ab6a
SH		 3517 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3518 if (err) {
b02a9258 3519 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3520 goto err_out_free_regions;
3521 }
3522 }
d1f3d4dd 3523
e3173832
SH		 3524 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3525
cd28ab6a 3526 err = -ENOMEM;
6aad85d6 3527 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3528 if (!hw) {
b02a9258 3529 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3530 goto err_out_free_regions;
3531 }
3532
cd28ab6a 3533 hw->pdev = pdev;
cd28ab6a
SH		 3534
3535 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3536 if (!hw->regs) {
b02a9258 3537 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3538 goto err_out_free_hw;
3539 }
3540
56a645cc 3541#ifdef __BIG_ENDIAN
f65b138c
SH		 3542 /* The sk98lin vendor driver uses hardware byte swapping but
3543 * this driver uses software swapping.
3544 */
56a645cc
SH		 3545 {
3546 u32 reg;
56a645cc 3547 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3548 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3549 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3550 }
3551#endif
3552
08c06d8a
SH		 3553 /* ring for status responses */
3554 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3555 &hw->st_dma);
3556 if (!hw->st_le)
3557 goto err_out_iounmap;
3558
e3173832 3559 err = sky2_init(hw);
cd28ab6a 3560 if (err)
793b883e 3561 goto err_out_iounmap;
cd28ab6a 3562
b02a9258 3563 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3564 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3565 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3566 hw->chip_id, hw->chip_rev);
cd28ab6a 3567
e3173832
SH		 3568 sky2_reset(hw);
3569
3570 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3571 if (!dev) {
3572 err = -ENOMEM;
cd28ab6a 3573 goto err_out_free_pci;
7f60c64b 3574 }
cd28ab6a 3575
9fa1b1f3
SH		 3576 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3577 err = sky2_test_msi(hw);
3578 if (err == -EOPNOTSUPP)
3579 pci_disable_msi(pdev);
3580 else if (err)
3581 goto err_out_free_netdev;
3582 }
3583
793b883e
SH		 3584 err = register_netdev(dev);
3585 if (err) {
b02a9258 3586 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3587 goto err_out_free_netdev;
3588 }
3589
b0a20ded
SH		 3590 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3591 dev->name, hw);
9fa1b1f3 3592 if (err) {
b02a9258 3593 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3594 goto err_out_unregister;
3595 }
3596 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3597
cd28ab6a
SH		 3598 sky2_show_addr(dev);
3599
7f60c64b 3600 if (hw->ports > 1) {
3601 struct net_device *dev1;
3602
e3173832 3603 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3604 if (!dev1)
3605 dev_warn(&pdev->dev, "allocation for second device failed\n");
3606 else if ((err = register_netdev(dev1))) {
3607 dev_warn(&pdev->dev,
3608 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3609 hw->dev[1] = NULL;
3610 free_netdev(dev1);
b02a9258
SH		 3611 } else
3612 sky2_show_addr(dev1);
cd28ab6a
SH		 3613 }
3614
01bd7564 3615 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3616 sky2_idle_start(hw);
d27ed387 3617
793b883e
SH		 3618 pci_set_drvdata(pdev, hw);
3619
cd28ab6a
SH		 3620 return 0;
3621
793b883e 3622err_out_unregister:
b0a20ded
SH		 3623 if (hw->msi)
3624 pci_disable_msi(pdev);
793b883e 3625 unregister_netdev(dev);
cd28ab6a
SH		 3626err_out_free_netdev:
3627 free_netdev(dev);
cd28ab6a 3628err_out_free_pci:
793b883e 3629 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3630 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3631err_out_iounmap:
3632 iounmap(hw->regs);
3633err_out_free_hw:
3634 kfree(hw);
3635err_out_free_regions:
3636 pci_release_regions(pdev);
cd28ab6a 3637 pci_disable_device(pdev);
cd28ab6a
SH		 3638err_out:
3639 return err;
3640}
3641
3642static void __devexit sky2_remove(struct pci_dev *pdev)
3643{
793b883e 3644 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3645 struct net_device *dev0, *dev1;
3646
793b883e 3647 if (!hw)
cd28ab6a
SH		 3648 return;
3649
d27ed387
SH		 3650 del_timer_sync(&hw->idle_timer);
3651
3652 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3653 synchronize_irq(hw->pdev->irq);
3654
cd28ab6a 3655 dev0 = hw->dev[0];
793b883e
SH		 3656 dev1 = hw->dev[1];
3657 if (dev1)
3658 unregister_netdev(dev1);
cd28ab6a
SH		 3659 unregister_netdev(dev0);
3660
ae306cca
SH		 3661 sky2_power_aux(hw);
3662
cd28ab6a 3663 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3664 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3665 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3666
3667 free_irq(pdev->irq, hw);
b0a20ded
SH		 3668 if (hw->msi)
3669 pci_disable_msi(pdev);
793b883e 3670 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3671 pci_release_regions(pdev);
3672 pci_disable_device(pdev);
793b883e 3673
cd28ab6a
SH		 3674 if (dev1)
3675 free_netdev(dev1);
3676 free_netdev(dev0);
3677 iounmap(hw->regs);
3678 kfree(hw);
5afa0a9c 3679
cd28ab6a
SH		 3680 pci_set_drvdata(pdev, NULL);
3681}
3682
3683#ifdef CONFIG_PM
3684static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3685{
793b883e 3686 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3687 int i, wol = 0;
cd28ab6a 3688
eb35cf60 3689 del_timer_sync(&hw->idle_timer);
6a5706b9 3690 netif_poll_disable(hw->dev[0]);
eb35cf60 3691
f05267e7 3692 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3693 struct net_device *dev = hw->dev[i];
e3173832 3694 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3695
e3173832 3696 if (netif_running(dev))
5afa0a9c 3697 sky2_down(dev);
e3173832
SH		 3698
3699 if (sky2->wol)
3700 sky2_wol_init(sky2);
3701
3702 wol |= sky2->wol;
cd28ab6a
SH		 3703 }
3704
8ab8fca2 3705 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3706 sky2_power_aux(hw);
e3173832 3707
d374c1c1 3708 pci_save_state(pdev);
e3173832 3709 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3710 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3711
2ccc99b7 3712 return 0;
cd28ab6a
SH		 3713}
3714
3715static int sky2_resume(struct pci_dev *pdev)
3716{
793b883e 3717 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3718 int i, err;
cd28ab6a 3719
ae306cca
SH		 3720 err = pci_set_power_state(pdev, PCI_D0);
3721 if (err)
3722 goto out;
3723
3724 err = pci_restore_state(pdev);
3725 if (err)
3726 goto out;
3727
cd28ab6a 3728 pci_enable_wake(pdev, PCI_D0, 0);
e3173832 3729 sky2_reset(hw);
cd28ab6a 3730
8ab8fca2
SH		 3731 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3732
f05267e7 3733 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3734 struct net_device *dev = hw->dev[i];
6a5706b9 3735 if (netif_running(dev)) {
08c06d8a
SH		 3736 err = sky2_up(dev);
3737 if (err) {
3738 printk(KERN_ERR PFX "%s: could not up: %d\n",
3739 dev->name, err);
3740 dev_close(dev);
eb35cf60 3741 goto out;
5afa0a9c 3742 }
cd28ab6a
SH		 3743 }
3744 }
eb35cf60 3745
6a5706b9 3746 netif_poll_enable(hw->dev[0]);
eb35cf60 3747 sky2_idle_start(hw);
ae306cca 3748 return 0;
08c06d8a 3749out:
b02a9258 3750 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3751 pci_disable_device(pdev);
08c06d8a 3752 return err;
cd28ab6a
SH		 3753}
3754#endif
3755
e3173832
SH		 3756static void sky2_shutdown(struct pci_dev *pdev)
3757{
3758 struct sky2_hw *hw = pci_get_drvdata(pdev);
3759 int i, wol = 0;
3760
3761 del_timer_sync(&hw->idle_timer);
3762 netif_poll_disable(hw->dev[0]);
3763
3764 for (i = 0; i < hw->ports; i++) {
3765 struct net_device *dev = hw->dev[i];
3766 struct sky2_port *sky2 = netdev_priv(dev);
3767
3768 if (sky2->wol) {
3769 wol = 1;
3770 sky2_wol_init(sky2);
3771 }
3772 }
3773
3774 if (wol)
3775 sky2_power_aux(hw);
3776
3777 pci_enable_wake(pdev, PCI_D3hot, wol);
3778 pci_enable_wake(pdev, PCI_D3cold, wol);
3779
3780 pci_disable_device(pdev);
3781 pci_set_power_state(pdev, PCI_D3hot);
3782
3783}
3784
cd28ab6a 3785static struct pci_driver sky2_driver = {
793b883e
SH		 3786 .name = DRV_NAME,
3787 .id_table = sky2_id_table,
3788 .probe = sky2_probe,
3789 .remove = __devexit_p(sky2_remove),
cd28ab6a 3790#ifdef CONFIG_PM
793b883e
SH		 3791 .suspend = sky2_suspend,
3792 .resume = sky2_resume,
cd28ab6a 3793#endif
e3173832 3794 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3795};
3796
3797static int __init sky2_init_module(void)
3798{
50241c4c 3799 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3800}
3801
3802static void __exit sky2_cleanup_module(void)
3803{
3804 pci_unregister_driver(&sky2_driver);
3805}
3806
3807module_init(sky2_init_module);
3808module_exit(sky2_cleanup_module);
3809
3810MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3811MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3812MODULE_LICENSE("GPL");
5f4f9dc1 3813MODULE_VERSION(DRV_VERSION);
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