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[PATCH] sky2: drop broken wake on lan support
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
cd28ab6a 26#include <linux/config.h>
793b883e 27#include <linux/crc32.h>
cd28ab6a
SH		 28#include <linux/kernel.h>
29#include <linux/version.h>
30#include <linux/module.h>
31#include <linux/netdevice.h>
d0bbccfa 32#include <linux/dma-mapping.h>
cd28ab6a
SH		 33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/ip.h>
37#include <linux/tcp.h>
38#include <linux/in.h>
39#include <linux/delay.h>
91c86df5 40#include <linux/workqueue.h>
d1f13708 41#include <linux/if_vlan.h>
d70cd51a 42#include <linux/prefetch.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
fa8d3549 54#define DRV_VERSION "0.15"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
62 */
63
13210ce5 64#define RX_LE_SIZE 512
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 66#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 68#define RX_SKB_ALIGN 8
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
bdb5c58e
SH		 91static int copybreak __read_mostly = 256;
92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
cd28ab6a 95static const struct pci_device_id sky2_id_table[] = {
793b883e 96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 97 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
98 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
99 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
100 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
101 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 115 { 0 }
116};
793b883e 117
cd28ab6a
SH		 118MODULE_DEVICE_TABLE(pci, sky2_id_table);
119
120/* Avoid conditionals by using array */
121static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
122static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
123
92f965e8
SH		 124/* This driver supports yukon2 chipset only */
125static const char *yukon2_name[] = {
126 "XL", /* 0xb3 */
127 "EC Ultra", /* 0xb4 */
128 "UNKNOWN", /* 0xb5 */
129 "EC", /* 0xb6 */
130 "FE", /* 0xb7 */
793b883e
SH		 131};
132
793b883e 133/* Access to external PHY */
ef743d33 134static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 135{
136 int i;
137
138 gma_write16(hw, port, GM_SMI_DATA, val);
139 gma_write16(hw, port, GM_SMI_CTRL,
140 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
141
142 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 143 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 144 return 0;
793b883e 145 udelay(1);
cd28ab6a 146 }
ef743d33 147
793b883e 148 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 149 return -ETIMEDOUT;
cd28ab6a
SH		 150}
151
ef743d33 152static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 153{
154 int i;
155
793b883e 156 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 157 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
158
159 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 160 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
161 *val = gma_read16(hw, port, GM_SMI_DATA);
162 return 0;
163 }
164
793b883e 165 udelay(1);
cd28ab6a
SH		 166 }
167
ef743d33
SH		 168 return -ETIMEDOUT;
169}
170
171static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
172{
173 u16 v;
174
175 if (__gm_phy_read(hw, port, reg, &v) != 0)
176 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
177 return v;
cd28ab6a
SH		 178}
179
5afa0a9c
SH		 180static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
181{
182 u16 power_control;
183 u32 reg1;
184 int vaux;
185 int ret = 0;
186
187 pr_debug("sky2_set_power_state %d\n", state);
188 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
189
56a645cc 190 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 191 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 192 (power_control & PCI_PM_CAP_PME_D3cold);
193
56a645cc 194 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 195
196 power_control |= PCI_PM_CTRL_PME_STATUS;
197 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
198
199 switch (state) {
200 case PCI_D0:
201 /* switch power to VCC (WA for VAUX problem) */
202 sky2_write8(hw, B0_POWER_CTRL,
203 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
204
205 /* disable Core Clock Division, */
206 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
207
208 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
209 /* enable bits are inverted */
210 sky2_write8(hw, B2_Y2_CLK_GATE,
211 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
212 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
213 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
214 else
215 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
216
217 /* Turn off phy power saving */
56a645cc 218 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 219 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
220
d571b694 221 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
223 reg1 |= PCI_Y2_PHY1_COMA;
224 if (hw->ports > 1)
225 reg1 |= PCI_Y2_PHY2_COMA;
226 }
977bdf06
SH		 227
228 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 229 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
230 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 231 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 232 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
233 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 234 }
235
56a645cc 236 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
977bdf06 237
5afa0a9c
SH		 238 break;
239
240 case PCI_D3hot:
241 case PCI_D3cold:
242 /* Turn on phy power saving */
56a645cc 243 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 else
247 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 248 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
5afa0a9c
SH		 249
250 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
251 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 else
253 /* enable bits are inverted */
254 sky2_write8(hw, B2_Y2_CLK_GATE,
255 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
256 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
257 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258
259 /* switch power to VAUX */
260 if (vaux && state != PCI_D3cold)
261 sky2_write8(hw, B0_POWER_CTRL,
262 (PC_VAUX_ENA | PC_VCC_ENA |
263 PC_VAUX_ON | PC_VCC_OFF));
264 break;
265 default:
266 printk(KERN_ERR PFX "Unknown power state %d\n", state);
267 ret = -1;
268 }
269
56a645cc 270 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c
SH		 271 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
272 return ret;
273}
274
cd28ab6a
SH		 275static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
276{
277 u16 reg;
278
279 /* disable all GMAC IRQ's */
280 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
281 /* disable PHY IRQs */
282 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
294static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295{
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 298
793b883e 299 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 300 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301
302 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 303 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 304 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305
306 if (hw->chip_id == CHIP_ID_YUKON_EC)
307 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 else
309 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310
311 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
312 }
313
314 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->copper) {
316 if (hw->chip_id == CHIP_ID_YUKON_FE) {
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 } else {
320 /* disable energy detect */
321 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322
323 /* enable automatic crossover */
324 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325
326 if (sky2->autoneg == AUTONEG_ENABLE &&
327 hw->chip_id == CHIP_ID_YUKON_XL) {
328 ctrl &= ~PHY_M_PC_DSC_MSK;
329 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
330 }
331 }
332 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 } else {
334 /* workaround for deviation #4.88 (CRC errors) */
335 /* disable Automatic Crossover */
336
337 ctrl &= ~PHY_M_PC_MDIX_MSK;
338 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339
340 if (hw->chip_id == CHIP_ID_YUKON_XL) {
341 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
342 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
344 ctrl &= ~PHY_M_MAC_MD_MSK;
345 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347
348 /* select page 1 to access Fiber registers */
349 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
350 }
cd28ab6a
SH		 351 }
352
353 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
354 if (sky2->autoneg == AUTONEG_DISABLE)
355 ctrl &= ~PHY_CT_ANE;
356 else
357 ctrl |= PHY_CT_ANE;
358
359 ctrl |= PHY_CT_RESET;
360 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
361
362 ctrl = 0;
363 ct1000 = 0;
364 adv = PHY_AN_CSMA;
365
366 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (hw->copper) {
368 if (sky2->advertising & ADVERTISED_1000baseT_Full)
369 ct1000 |= PHY_M_1000C_AFD;
370 if (sky2->advertising & ADVERTISED_1000baseT_Half)
371 ct1000 |= PHY_M_1000C_AHD;
372 if (sky2->advertising & ADVERTISED_100baseT_Full)
373 adv |= PHY_M_AN_100_FD;
374 if (sky2->advertising & ADVERTISED_100baseT_Half)
375 adv |= PHY_M_AN_100_HD;
376 if (sky2->advertising & ADVERTISED_10baseT_Full)
377 adv |= PHY_M_AN_10_FD;
378 if (sky2->advertising & ADVERTISED_10baseT_Half)
379 adv |= PHY_M_AN_10_HD;
793b883e 380 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 381 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382
383 /* Set Flow-control capabilities */
384 if (sky2->tx_pause && sky2->rx_pause)
793b883e 385 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 386 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 387 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 388 else if (!sky2->rx_pause && sky2->tx_pause)
389 adv |= PHY_AN_PAUSE_ASYM; /* local */
390
391 /* Restart Auto-negotiation */
392 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 } else {
394 /* forced speed/duplex settings */
395 ct1000 = PHY_M_1000C_MSE;
396
397 if (sky2->duplex == DUPLEX_FULL)
398 ctrl |= PHY_CT_DUP_MD;
399
400 switch (sky2->speed) {
401 case SPEED_1000:
402 ctrl |= PHY_CT_SP1000;
403 break;
404 case SPEED_100:
405 ctrl |= PHY_CT_SP100;
406 break;
407 }
408
409 ctrl |= PHY_CT_RESET;
410 }
411
412 if (hw->chip_id != CHIP_ID_YUKON_FE)
413 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414
415 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
416 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417
418 /* Setup Phy LED's */
419 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
420 ledover = 0;
421
422 switch (hw->chip_id) {
423 case CHIP_ID_YUKON_FE:
424 /* on 88E3082 these bits are at 11..9 (shifted left) */
425 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426
427 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428
429 /* delete ACT LED control bits */
430 ctrl &= ~PHY_M_FELP_LED1_MSK;
431 /* change ACT LED control to blink mode */
432 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
433 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
434 break;
435
436 case CHIP_ID_YUKON_XL:
793b883e 437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 438
439 /* select page 3 to access LED control register */
440 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441
442 /* set LED Function Control register */
793b883e
SH		 443 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
444 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
445 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
446 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 447
448 /* set Polarity Control register */
449 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 450 (PHY_M_POLC_LS1_P_MIX(4) |
451 PHY_M_POLC_IS0_P_MIX(4) |
452 PHY_M_POLC_LOS_CTRL(2) |
453 PHY_M_POLC_INIT_CTRL(2) |
454 PHY_M_POLC_STA1_CTRL(2) |
455 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 456
457 /* restore page register */
793b883e 458 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 459 break;
460
461 default:
462 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
463 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
464 /* turn off the Rx LED (LED_RX) */
465 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
466 }
467
977bdf06
SH		 468 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
469 /* apply fixes in PHY AFE */
470 gm_phy_write(hw, port, 22, 255);
471 /* increase differential signal amplitude in 10BASE-T */
472 gm_phy_write(hw, port, 24, 0xaa99);
473 gm_phy_write(hw, port, 23, 0x2011);
cd28ab6a 474
977bdf06
SH		 475 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
476 gm_phy_write(hw, port, 24, 0xa204);
477 gm_phy_write(hw, port, 23, 0x2002);
478
479 /* set page register to 0 */
480 gm_phy_write(hw, port, 22, 0);
481 } else {
482 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 483
977bdf06
SH		 484 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
485 /* turn on 100 Mbps LED (LED_LINK100) */
486 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
487 }
cd28ab6a 488
977bdf06
SH		 489 if (ledover)
490 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
491
492 }
d571b694 493 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 494 if (sky2->autoneg == AUTONEG_ENABLE)
495 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
496 else
497 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
498}
499
1b537565
SH		 500/* Force a renegotiation */
501static void sky2_phy_reinit(struct sky2_port *sky2)
502{
503 down(&sky2->phy_sema);
504 sky2_phy_init(sky2->hw, sky2->port);
505 up(&sky2->phy_sema);
506}
507
cd28ab6a
SH		 508static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
509{
510 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
511 u16 reg;
512 int i;
513 const u8 *addr = hw->dev[port]->dev_addr;
514
42eeea01
SH		 515 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
516 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 517
518 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
519
793b883e 520 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 521 /* WA DEV_472 -- looks like crossed wires on port 2 */
522 /* clear GMAC 1 Control reset */
523 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
524 do {
525 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
526 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
527 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
528 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
529 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
530 }
531
cd28ab6a
SH		 532 if (sky2->autoneg == AUTONEG_DISABLE) {
533 reg = gma_read16(hw, port, GM_GP_CTRL);
534 reg |= GM_GPCR_AU_ALL_DIS;
535 gma_write16(hw, port, GM_GP_CTRL, reg);
536 gma_read16(hw, port, GM_GP_CTRL);
537
cd28ab6a
SH		 538 switch (sky2->speed) {
539 case SPEED_1000:
6f4c56b2 540 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 541 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 542 break;
cd28ab6a 543 case SPEED_100:
6f4c56b2 544 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 545 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 546 break;
547 case SPEED_10:
548 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
549 break;
cd28ab6a
SH		 550 }
551
552 if (sky2->duplex == DUPLEX_FULL)
553 reg |= GM_GPCR_DUP_FULL;
554 } else
555 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
556
557 if (!sky2->tx_pause && !sky2->rx_pause) {
558 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 559 reg |=
560 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
561 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 562 /* disable Rx flow-control */
563 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
564 }
565
566 gma_write16(hw, port, GM_GP_CTRL, reg);
567
793b883e 568 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 569
91c86df5 570 down(&sky2->phy_sema);
cd28ab6a 571 sky2_phy_init(hw, port);
91c86df5 572 up(&sky2->phy_sema);
cd28ab6a
SH		 573
574 /* MIB clear */
575 reg = gma_read16(hw, port, GM_PHY_ADDR);
576 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
577
578 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 579 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 580 gma_write16(hw, port, GM_PHY_ADDR, reg);
581
582 /* transmit control */
583 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
584
585 /* receive control reg: unicast + multicast + no FCS */
586 gma_write16(hw, port, GM_RX_CTRL,
793b883e 587 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 588
589 /* transmit flow control */
590 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
591
592 /* transmit parameter */
593 gma_write16(hw, port, GM_TX_PARAM,
594 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
595 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
596 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
597 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
598
599 /* serial mode register */
600 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 601 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 602
6b1a3aef 603 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 604 reg |= GM_SMOD_JUMBO_ENA;
605
606 gma_write16(hw, port, GM_SERIAL_MODE, reg);
607
cd28ab6a
SH		 608 /* virtual address for data */
609 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
610
793b883e
SH		 611 /* physical address: used for pause frames */
612 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
613
614 /* ignore counter overflows */
cd28ab6a
SH		 615 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
616 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
617 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
618
619 /* Configure Rx MAC FIFO */
620 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 621 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
622 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 623
d571b694 624 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 625 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 626
793b883e
SH		 627 /* Set threshold to 0xa (64 bytes)
628 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 629 */
630 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
631
632 /* Configure Tx MAC FIFO */
633 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
634 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 635
636 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
637 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
638 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
639 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
640 /* set Tx GMAC FIFO Almost Empty Threshold */
641 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
642 /* Disable Store & Forward mode for TX */
643 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
644 }
645 }
646
cd28ab6a
SH		 647}
648
1c28f6ba
SH		 649/* Assign Ram Buffer allocation.
650 * start and end are in units of 4k bytes
651 * ram registers are in units of 64bit words
652 */
653static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 654{
1c28f6ba 655 u32 start, end;
cd28ab6a 656
1c28f6ba
SH		 657 start = startk * 4096/8;
658 end = (endk * 4096/8) - 1;
793b883e 659
cd28ab6a
SH		 660 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
661 sky2_write32(hw, RB_ADDR(q, RB_START), start);
662 sky2_write32(hw, RB_ADDR(q, RB_END), end);
663 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
664 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
665
666 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 667 u32 space = (endk - startk) * 4096/8;
668 u32 tp = space - space/4;
793b883e 669
1c28f6ba
SH		 670 /* On receive queue's set the thresholds
671 * give receiver priority when > 3/4 full
672 * send pause when down to 2K
673 */
674 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
675 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 676
1c28f6ba
SH		 677 tp = space - 2048/8;
678 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
679 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 680 } else {
681 /* Enable store & forward on Tx queue's because
682 * Tx FIFO is only 1K on Yukon
683 */
684 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
685 }
686
687 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 688 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 689}
690
cd28ab6a 691/* Setup Bus Memory Interface */
af4ed7e6 692static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 693{
694 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
695 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
696 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 697 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 698}
699
cd28ab6a
SH		 700/* Setup prefetch unit registers. This is the interface between
701 * hardware and driver list elements
702 */
8cc048e3 703static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 704 u64 addr, u32 last)
705{
cd28ab6a
SH		 706 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
707 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
708 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
710 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 712
713 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 714}
715
793b883e
SH		 716static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
717{
718 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
719
720 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
721 return le;
722}
cd28ab6a 723
290d4de5
SH		 724/* Update chip's next pointer */
725static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 726{
762c2de2 727 wmb();
290d4de5 728 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 729 mmiowb();
cd28ab6a
SH		 730}
731
793b883e 732
cd28ab6a
SH		 733static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
734{
735 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
736 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
737 return le;
738}
739
a018e330
SH		 740/* Return high part of DMA address (could be 32 or 64 bit) */
741static inline u32 high32(dma_addr_t a)
742{
a036119f 743 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 744}
745
793b883e 746/* Build description to hardware about buffer */
28bd181a 747static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 748{
749 struct sky2_rx_le *le;
734d1868
SH		 750 u32 hi = high32(map);
751 u16 len = sky2->rx_bufsize;
cd28ab6a 752
793b883e 753 if (sky2->rx_addr64 != hi) {
cd28ab6a 754 le = sky2_next_rx(sky2);
793b883e 755 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 756 le->ctrl = 0;
757 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 758 sky2->rx_addr64 = high32(map + len);
cd28ab6a 759 }
793b883e 760
cd28ab6a 761 le = sky2_next_rx(sky2);
734d1868
SH		 762 le->addr = cpu_to_le32((u32) map);
763 le->length = cpu_to_le16(len);
cd28ab6a
SH		 764 le->ctrl = 0;
765 le->opcode = OP_PACKET | HW_OWNER;
766}
767
793b883e 768
cd28ab6a
SH		 769/* Tell chip where to start receive checksum.
770 * Actually has two checksums, but set both same to avoid possible byte
771 * order problems.
772 */
793b883e 773static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 774{
775 struct sky2_rx_le *le;
776
cd28ab6a 777 le = sky2_next_rx(sky2);
793b883e 778 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 779 le->ctrl = 0;
780 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 781
793b883e
SH		 782 sky2_write32(sky2->hw,
783 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
784 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 785
786}
787
6b1a3aef
SH		 788/*
789 * The RX Stop command will not work for Yukon-2 if the BMU does not
790 * reach the end of packet and since we can't make sure that we have
791 * incoming data, we must reset the BMU while it is not doing a DMA
792 * transfer. Since it is possible that the RX path is still active,
793 * the RX RAM buffer will be stopped first, so any possible incoming
794 * data will not trigger a DMA. After the RAM buffer is stopped, the
795 * BMU is polled until any DMA in progress is ended and only then it
796 * will be reset.
797 */
798static void sky2_rx_stop(struct sky2_port *sky2)
799{
800 struct sky2_hw *hw = sky2->hw;
801 unsigned rxq = rxqaddr[sky2->port];
802 int i;
803
804 /* disable the RAM Buffer receive queue */
805 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
806
807 for (i = 0; i < 0xffff; i++)
808 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
809 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
810 goto stopped;
811
812 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
813 sky2->netdev->name);
814stopped:
815 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
816
817 /* reset the Rx prefetch unit */
818 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
819}
793b883e 820
d571b694 821/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 822static void sky2_rx_clean(struct sky2_port *sky2)
823{
824 unsigned i;
825
826 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 827 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 828 struct ring_info *re = sky2->rx_ring + i;
829
830 if (re->skb) {
793b883e 831 pci_unmap_single(sky2->hw->pdev,
734d1868 832 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 833 PCI_DMA_FROMDEVICE);
834 kfree_skb(re->skb);
835 re->skb = NULL;
836 }
837 }
838}
839
ef743d33
SH		 840/* Basic MII support */
841static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
842{
843 struct mii_ioctl_data *data = if_mii(ifr);
844 struct sky2_port *sky2 = netdev_priv(dev);
845 struct sky2_hw *hw = sky2->hw;
846 int err = -EOPNOTSUPP;
847
848 if (!netif_running(dev))
849 return -ENODEV; /* Phy still in reset */
850
851 switch(cmd) {
852 case SIOCGMIIPHY:
853 data->phy_id = PHY_ADDR_MARV;
854
855 /* fallthru */
856 case SIOCGMIIREG: {
857 u16 val = 0;
91c86df5
SH		 858
859 down(&sky2->phy_sema);
ef743d33 860 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 861 up(&sky2->phy_sema);
862
ef743d33
SH		 863 data->val_out = val;
864 break;
865 }
866
867 case SIOCSMIIREG:
868 if (!capable(CAP_NET_ADMIN))
869 return -EPERM;
870
91c86df5 871 down(&sky2->phy_sema);
ef743d33
SH		 872 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
873 data->val_in);
91c86df5 874 up(&sky2->phy_sema);
ef743d33
SH		 875 break;
876 }
877 return err;
878}
879
d1f13708
SH		 880#ifdef SKY2_VLAN_TAG_USED
881static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
882{
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
d1f13708 886
302d1252 887 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 888
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
891 sky2->vlgrp = grp;
892
302d1252 893 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 894}
895
896static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
897{
898 struct sky2_port *sky2 = netdev_priv(dev);
899 struct sky2_hw *hw = sky2->hw;
900 u16 port = sky2->port;
d1f13708 901
302d1252 902 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 903
904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
905 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
906 if (sky2->vlgrp)
907 sky2->vlgrp->vlan_devices[vid] = NULL;
908
302d1252 909 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 910}
911#endif
912
82788c7a
SH		 913/*
914 * It appears the hardware has a bug in the FIFO logic that
915 * cause it to hang if the FIFO gets overrun and the receive buffer
916 * is not aligned. ALso alloc_skb() won't align properly if slab
917 * debugging is enabled.
918 */
919static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
920{
921 struct sk_buff *skb;
922
923 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
924 if (likely(skb)) {
925 unsigned long p = (unsigned long) skb->data;
926 skb_reserve(skb,
927 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
928 }
929
930 return skb;
931}
932
cd28ab6a
SH		 933/*
934 * Allocate and setup receiver buffer pool.
935 * In case of 64 bit dma, there are 2X as many list elements
936 * available as ring entries
937 * and need to reserve one list element so we don't wrap around.
938 */
6b1a3aef 939static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 940{
6b1a3aef 941 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 942 unsigned rxq = rxqaddr[sky2->port];
943 int i;
cd28ab6a 944
6b1a3aef 945 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 946 sky2_qset(hw, rxq);
977bdf06
SH		 947
948 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
949 /* MAC Rx RAM Read is controlled by hardware */
950 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
951 }
952
6b1a3aef
SH		 953 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
954
955 rx_set_checksum(sky2);
793b883e 956 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 957 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 958
82788c7a 959 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
cd28ab6a
SH		 960 if (!re->skb)
961 goto nomem;
962
6b1a3aef 963 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 964 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
965 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 966 }
967
70f1be48
SH		 968 /* Truncate oversize frames */
969 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
970 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
971
6b1a3aef
SH		 972 /* Tell chip about available buffers */
973 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 974 return 0;
975nomem:
976 sky2_rx_clean(sky2);
977 return -ENOMEM;
978}
979
980/* Bring up network interface. */
981static int sky2_up(struct net_device *dev)
982{
983 struct sky2_port *sky2 = netdev_priv(dev);
984 struct sky2_hw *hw = sky2->hw;
985 unsigned port = sky2->port;
986 u32 ramsize, rxspace;
987 int err = -ENOMEM;
988
989 if (netif_msg_ifup(sky2))
990 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
991
992 /* must be power of 2 */
993 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 994 TX_RING_SIZE *
995 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 996 &sky2->tx_le_map);
997 if (!sky2->tx_le)
998 goto err_out;
999
6cdbbdf3 1000 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1001 GFP_KERNEL);
1002 if (!sky2->tx_ring)
1003 goto err_out;
1004 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1005
1006 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1007 &sky2->rx_le_map);
1008 if (!sky2->rx_le)
1009 goto err_out;
1010 memset(sky2->rx_le, 0, RX_LE_BYTES);
1011
6cdbbdf3 1012 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1013 GFP_KERNEL);
1014 if (!sky2->rx_ring)
1015 goto err_out;
1016
1017 sky2_mac_init(hw, port);
1018
1c28f6ba
SH		 1019 /* Determine available ram buffer space (in 4K blocks).
1020 * Note: not sure about the FE setting below yet
1021 */
1022 if (hw->chip_id == CHIP_ID_YUKON_FE)
1023 ramsize = 4;
1024 else
1025 ramsize = sky2_read8(hw, B2_E_0);
1026
1027 /* Give transmitter one third (rounded up) */
1028 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1029
cd28ab6a 1030 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1031 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1032
793b883e
SH		 1033 /* Make sure SyncQ is disabled */
1034 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1035 RB_RST_SET);
1036
af4ed7e6 1037 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1038
977bdf06
SH		 1039 /* Set almost empty threshold */
1040 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1041 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1042
6b1a3aef
SH		 1043 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1044 TX_RING_SIZE - 1);
cd28ab6a 1045
6b1a3aef 1046 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1047 if (err)
1048 goto err_out;
1049
cd28ab6a 1050 /* Enable interrupts from phy/mac for port */
791917de 1051 spin_lock_irq(&hw->hw_lock);
cd28ab6a
SH		 1052 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1053 sky2_write32(hw, B0_IMSK, hw->intr_mask);
791917de 1054 spin_unlock_irq(&hw->hw_lock);
cd28ab6a
SH		 1055 return 0;
1056
1057err_out:
1b537565 1058 if (sky2->rx_le) {
cd28ab6a
SH		 1059 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1060 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1061 sky2->rx_le = NULL;
1062 }
1063 if (sky2->tx_le) {
cd28ab6a
SH		 1064 pci_free_consistent(hw->pdev,
1065 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1066 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1067 sky2->tx_le = NULL;
1068 }
1069 kfree(sky2->tx_ring);
1070 kfree(sky2->rx_ring);
cd28ab6a 1071
1b537565
SH		 1072 sky2->tx_ring = NULL;
1073 sky2->rx_ring = NULL;
cd28ab6a
SH		 1074 return err;
1075}
1076
793b883e
SH		 1077/* Modular subtraction in ring */
1078static inline int tx_dist(unsigned tail, unsigned head)
1079{
129372d0 1080 return (head - tail) % TX_RING_SIZE;
793b883e 1081}
cd28ab6a 1082
793b883e
SH		 1083/* Number of list elements available for next tx */
1084static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1085{
793b883e 1086 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1087}
1088
793b883e 1089/* Estimate of number of transmit list elements required */
28bd181a 1090static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1091{
793b883e
SH		 1092 unsigned count;
1093
1094 count = sizeof(dma_addr_t) / sizeof(u32);
1095 count += skb_shinfo(skb)->nr_frags * count;
1096
1097 if (skb_shinfo(skb)->tso_size)
1098 ++count;
1099
0e3ff6aa 1100 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1101 ++count;
1102
1103 return count;
cd28ab6a
SH		 1104}
1105
793b883e
SH		 1106/*
1107 * Put one packet in ring for transmit.
1108 * A single packet can generate multiple list elements, and
1109 * the number of ring elements will probably be less than the number
1110 * of list elements used.
f2e46561
SH		 1111 *
1112 * No BH disabling for tx_lock here (like tg3)
793b883e 1113 */
cd28ab6a
SH		 1114static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1115{
1116 struct sky2_port *sky2 = netdev_priv(dev);
1117 struct sky2_hw *hw = sky2->hw;
d1f13708 1118 struct sky2_tx_le *le = NULL;
6cdbbdf3 1119 struct tx_ring_info *re;
cd28ab6a 1120 unsigned i, len;
b19666d9 1121 int avail;
cd28ab6a
SH		 1122 dma_addr_t mapping;
1123 u32 addr64;
1124 u16 mss;
1125 u8 ctrl;
1126
302d1252
SH		 1127 /* No BH disabling for tx_lock here. We are running in BH disabled
1128 * context and TX reclaim runs via poll inside of a software
1129 * interrupt, and no related locks in IRQ processing.
1130 */
f2e46561 1131 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1132 return NETDEV_TX_LOCKED;
1133
793b883e 1134 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1135 /* There is a known but harmless race with lockless tx
1136 * and netif_stop_queue.
1137 */
1138 if (!netif_queue_stopped(dev)) {
1139 netif_stop_queue(dev);
3be92a70
SH		 1140 if (net_ratelimit())
1141 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1142 dev->name);
8c463ef7 1143 }
f2e46561 1144 spin_unlock(&sky2->tx_lock);
cd28ab6a 1145
cd28ab6a
SH		 1146 return NETDEV_TX_BUSY;
1147 }
1148
793b883e 1149 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1150 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1151 dev->name, sky2->tx_prod, skb->len);
1152
cd28ab6a
SH		 1153 len = skb_headlen(skb);
1154 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1155 addr64 = high32(mapping);
793b883e
SH		 1156
1157 re = sky2->tx_ring + sky2->tx_prod;
1158
a018e330
SH		 1159 /* Send high bits if changed or crosses boundary */
1160 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1161 le = get_tx_le(sky2);
1162 le->tx.addr = cpu_to_le32(addr64);
1163 le->ctrl = 0;
1164 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1165 sky2->tx_addr64 = high32(mapping + len);
793b883e 1166 }
cd28ab6a
SH		 1167
1168 /* Check for TCP Segmentation Offload */
1169 mss = skb_shinfo(skb)->tso_size;
793b883e 1170 if (mss != 0) {
cd28ab6a
SH		 1171 /* just drop the packet if non-linear expansion fails */
1172 if (skb_header_cloned(skb) &&
1173 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1174 dev_kfree_skb_any(skb);
1175 goto out_unlock;
cd28ab6a
SH		 1176 }
1177
1178 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1179 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1180 mss += ETH_HLEN;
793b883e 1181 }
cd28ab6a 1182
793b883e 1183 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1184 le = get_tx_le(sky2);
1185 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1186 le->tx.tso.rsvd = 0;
cd28ab6a 1187 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1188 le->ctrl = 0;
793b883e 1189 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1190 }
1191
cd28ab6a 1192 ctrl = 0;
d1f13708
SH		 1193#ifdef SKY2_VLAN_TAG_USED
1194 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1195 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1196 if (!le) {
1197 le = get_tx_le(sky2);
1198 le->tx.addr = 0;
1199 le->opcode = OP_VLAN|HW_OWNER;
1200 le->ctrl = 0;
1201 } else
1202 le->opcode |= OP_VLAN;
1203 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1204 ctrl |= INS_VLAN;
1205 }
1206#endif
1207
1208 /* Handle TCP checksum offload */
cd28ab6a 1209 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1210 u16 hdr = skb->h.raw - skb->data;
1211 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1212
1213 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1214 if (skb->nh.iph->protocol == IPPROTO_UDP)
1215 ctrl |= UDPTCP;
1216
1217 le = get_tx_le(sky2);
1218 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1219 le->tx.csum.offset = cpu_to_le16(offset);
1220 le->length = 0; /* initial checksum value */
cd28ab6a 1221 le->ctrl = 1; /* one packet */
793b883e 1222 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1223 }
1224
1225 le = get_tx_le(sky2);
1226 le->tx.addr = cpu_to_le32((u32) mapping);
1227 le->length = cpu_to_le16(len);
1228 le->ctrl = ctrl;
793b883e 1229 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1230
793b883e 1231 /* Record the transmit mapping info */
cd28ab6a 1232 re->skb = skb;
6cdbbdf3 1233 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1234
1235 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1236 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1237 struct tx_ring_info *fre;
cd28ab6a
SH		 1238
1239 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1240 frag->size, PCI_DMA_TODEVICE);
a036119f 1241 addr64 = high32(mapping);
793b883e
SH		 1242 if (addr64 != sky2->tx_addr64) {
1243 le = get_tx_le(sky2);
1244 le->tx.addr = cpu_to_le32(addr64);
1245 le->ctrl = 0;
1246 le->opcode = OP_ADDR64 | HW_OWNER;
1247 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1248 }
1249
1250 le = get_tx_le(sky2);
1251 le->tx.addr = cpu_to_le32((u32) mapping);
1252 le->length = cpu_to_le16(frag->size);
1253 le->ctrl = ctrl;
793b883e 1254 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1255
793b883e
SH		 1256 fre = sky2->tx_ring
1257 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1258 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1259 }
6cdbbdf3 1260
793b883e 1261 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1262 le->ctrl |= EOP;
1263
b19666d9
SH		 1264 avail = tx_avail(sky2);
1265 if (mss != 0 || avail < TX_MIN_PENDING) {
1266 le->ctrl |= FRC_STAT;
1267 if (avail <= MAX_SKB_TX_LE)
1268 netif_stop_queue(dev);
1269 }
1270
290d4de5 1271 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1272
793b883e 1273out_unlock:
f2e46561 1274 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1275
1276 dev->trans_start = jiffies;
1277 return NETDEV_TX_OK;
1278}
1279
cd28ab6a 1280/*
793b883e
SH		 1281 * Free ring elements from starting at tx_cons until "done"
1282 *
1283 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1284 * buffers; these are deferred until completion.
cd28ab6a 1285 */
d11c13e7 1286static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1287{
d11c13e7 1288 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1289 struct pci_dev *pdev = sky2->hw->pdev;
1290 u16 nxt, put;
793b883e 1291 unsigned i;
cd28ab6a 1292
0e3ff6aa 1293 BUG_ON(done >= TX_RING_SIZE);
2224795d 1294
d11c13e7 1295 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1296 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1297 dev->name, done);
cd28ab6a 1298
af2a58ac
SH		 1299 for (put = sky2->tx_cons; put != done; put = nxt) {
1300 struct tx_ring_info *re = sky2->tx_ring + put;
1301 struct sk_buff *skb = re->skb;
cd28ab6a 1302
af2a58ac
SH		 1303 nxt = re->idx;
1304 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1305 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1306
793b883e 1307 /* Check for partial status */
af2a58ac
SH		 1308 if (tx_dist(put, done) < tx_dist(put, nxt))
1309 break;
793b883e
SH		 1310
1311 skb = re->skb;
af2a58ac 1312 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1313 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1314
1315 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1316 struct tx_ring_info *fre;
af2a58ac
SH		 1317 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1318 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1319 skb_shinfo(skb)->frags[i].size,
734d1868 1320 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1321 }
1322
cd28ab6a 1323 dev_kfree_skb_any(skb);
793b883e 1324 }
793b883e 1325
af2a58ac 1326 sky2->tx_cons = put;
793b883e 1327 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a 1328 netif_wake_queue(dev);
cd28ab6a
SH		 1329}
1330
1331/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1332static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1333{
302d1252 1334 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1335 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1336 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1337}
1338
1339/* Network shutdown */
1340static int sky2_down(struct net_device *dev)
1341{
1342 struct sky2_port *sky2 = netdev_priv(dev);
1343 struct sky2_hw *hw = sky2->hw;
1344 unsigned port = sky2->port;
1345 u16 ctrl;
cd28ab6a 1346
1b537565
SH		 1347 /* Never really got started! */
1348 if (!sky2->tx_le)
1349 return 0;
1350
cd28ab6a
SH		 1351 if (netif_msg_ifdown(sky2))
1352 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1353
018d1c66 1354 /* Stop more packets from being queued */
cd28ab6a
SH		 1355 netif_stop_queue(dev);
1356
018d1c66 1357 /* Disable port IRQ */
791917de 1358 spin_lock_irq(&hw->hw_lock);
018d1c66
SH		 1359 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1360 sky2_write32(hw, B0_IMSK, hw->intr_mask);
791917de 1361 spin_unlock_irq(&hw->hw_lock);
018d1c66 1362
91c86df5 1363 flush_scheduled_work();
018d1c66 1364
793b883e
SH		 1365 sky2_phy_reset(hw, port);
1366
cd28ab6a
SH		 1367 /* Stop transmitter */
1368 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1369 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1370
1371 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1372 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1373
1374 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1375 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1376 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1377
1378 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1379
1380 /* Workaround shared GMAC reset */
793b883e
SH		 1381 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1382 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1383 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1384
1385 /* Disable Force Sync bit and Enable Alloc bit */
1386 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1387 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1388
1389 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1390 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1391 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1392
1393 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1394 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1395 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1396
1397 /* Reset the Tx prefetch units */
1398 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1399 PREF_UNIT_RST_SET);
1400
1401 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1402
6b1a3aef 1403 sky2_rx_stop(sky2);
cd28ab6a
SH		 1404
1405 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1407
d571b694 1408 /* turn off LED's */
cd28ab6a
SH		 1409 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1410
018d1c66
SH		 1411 synchronize_irq(hw->pdev->irq);
1412
cd28ab6a
SH		 1413 sky2_tx_clean(sky2);
1414 sky2_rx_clean(sky2);
1415
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1418 kfree(sky2->rx_ring);
1419
1420 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map);
1423 kfree(sky2->tx_ring);
1424
1b537565
SH		 1425 sky2->tx_le = NULL;
1426 sky2->rx_le = NULL;
1427
1428 sky2->rx_ring = NULL;
1429 sky2->tx_ring = NULL;
1430
cd28ab6a
SH		 1431 return 0;
1432}
1433
1434static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1435{
793b883e
SH		 1436 if (!hw->copper)
1437 return SPEED_1000;
1438
cd28ab6a
SH		 1439 if (hw->chip_id == CHIP_ID_YUKON_FE)
1440 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1441
1442 switch (aux & PHY_M_PS_SPEED_MSK) {
1443 case PHY_M_PS_SPEED_1000:
1444 return SPEED_1000;
1445 case PHY_M_PS_SPEED_100:
1446 return SPEED_100;
1447 default:
1448 return SPEED_10;
1449 }
1450}
1451
1452static void sky2_link_up(struct sky2_port *sky2)
1453{
1454 struct sky2_hw *hw = sky2->hw;
1455 unsigned port = sky2->port;
1456 u16 reg;
1457
1458 /* Enable Transmit FIFO Underrun */
793b883e 1459 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1460
1461 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1462 if (sky2->autoneg == AUTONEG_DISABLE) {
1463 reg |= GM_GPCR_AU_ALL_DIS;
1464
1465 /* Is write/read necessary? Copied from sky2_mac_init */
1466 gma_write16(hw, port, GM_GP_CTRL, reg);
1467 gma_read16(hw, port, GM_GP_CTRL);
1468
1469 switch (sky2->speed) {
1470 case SPEED_1000:
1471 reg &= ~GM_GPCR_SPEED_100;
1472 reg |= GM_GPCR_SPEED_1000;
1473 break;
1474 case SPEED_100:
1475 reg &= ~GM_GPCR_SPEED_1000;
1476 reg |= GM_GPCR_SPEED_100;
1477 break;
1478 case SPEED_10:
1479 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1480 break;
1481 }
1482 } else
1483 reg &= ~GM_GPCR_AU_ALL_DIS;
1484
cd28ab6a
SH		 1485 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1486 reg |= GM_GPCR_DUP_FULL;
1487
cd28ab6a
SH		 1488 /* enable Rx/Tx */
1489 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1490 gma_write16(hw, port, GM_GP_CTRL, reg);
1491 gma_read16(hw, port, GM_GP_CTRL);
1492
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1494
1495 netif_carrier_on(sky2->netdev);
1496 netif_wake_queue(sky2->netdev);
1497
1498 /* Turn on link LED */
793b883e 1499 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1500 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1501
793b883e
SH		 1502 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1504
1505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1507 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1508 SPEED_10 ? 7 : 0) |
1509 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1510 SPEED_100 ? 7 : 0) |
1511 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1512 SPEED_1000 ? 7 : 0));
1513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1514 }
1515
cd28ab6a
SH		 1516 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX
d571b694 1518 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1519 sky2->netdev->name, sky2->speed,
1520 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1521 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1522 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1523}
1524
1525static void sky2_link_down(struct sky2_port *sky2)
1526{
1527 struct sky2_hw *hw = sky2->hw;
1528 unsigned port = sky2->port;
1529 u16 reg;
1530
1531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1532
1533 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1535 gma_write16(hw, port, GM_GP_CTRL, reg);
1536 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1537
1538 if (sky2->rx_pause && !sky2->tx_pause) {
1539 /* restore Asymmetric Pause bit */
1540 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1541 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1542 | PHY_M_AN_ASP);
cd28ab6a
SH		 1543 }
1544
cd28ab6a
SH		 1545 netif_carrier_off(sky2->netdev);
1546 netif_stop_queue(sky2->netdev);
1547
1548 /* Turn on link LED */
1549 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1550
1551 if (netif_msg_link(sky2))
1552 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1553 sky2_phy_init(hw, port);
1554}
1555
793b883e
SH		 1556static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1557{
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1560 u16 lpa;
1561
1562 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1563
1564 if (lpa & PHY_M_AN_RF) {
1565 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1566 return -1;
1567 }
1568
1569 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1570 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1571 printk(KERN_ERR PFX "%s: master/slave fault",
1572 sky2->netdev->name);
1573 return -1;
1574 }
1575
1576 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1577 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1578 sky2->netdev->name);
1579 return -1;
1580 }
1581
1582 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1583
1584 sky2->speed = sky2_phy_speed(hw, aux);
1585
1586 /* Pause bits are offset (9..8) */
1587 if (hw->chip_id == CHIP_ID_YUKON_XL)
1588 aux >>= 6;
1589
1590 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1591 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1592
1593 if ((sky2->tx_pause || sky2->rx_pause)
1594 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1596 else
1597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1598
1599 return 0;
1600}
cd28ab6a
SH		 1601
1602/*
91c86df5 1603 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1604 * because accessing phy registers requires spin wait which might
1605 * cause excess interrupt latency.
1606 */
91c86df5 1607static void sky2_phy_task(void *arg)
cd28ab6a 1608{
91c86df5 1609 struct sky2_port *sky2 = arg;
cd28ab6a 1610 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1611 u16 istatus, phystat;
1612
91c86df5 1613 down(&sky2->phy_sema);
793b883e
SH		 1614 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1615 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1616
1617 if (netif_msg_intr(sky2))
1618 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1619 sky2->netdev->name, istatus, phystat);
1620
1621 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1622 if (sky2_autoneg_done(sky2, phystat) == 0)
1623 sky2_link_up(sky2);
1624 goto out;
1625 }
cd28ab6a 1626
793b883e
SH		 1627 if (istatus & PHY_M_IS_LSP_CHANGE)
1628 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1629
793b883e
SH		 1630 if (istatus & PHY_M_IS_DUP_CHANGE)
1631 sky2->duplex =
1632 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1633
793b883e
SH		 1634 if (istatus & PHY_M_IS_LST_CHANGE) {
1635 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1636 sky2_link_up(sky2);
793b883e
SH		 1637 else
1638 sky2_link_down(sky2);
cd28ab6a 1639 }
793b883e 1640out:
91c86df5 1641 up(&sky2->phy_sema);
cd28ab6a 1642
791917de 1643 spin_lock_irq(&hw->hw_lock);
793b883e 1644 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a 1645 sky2_write32(hw, B0_IMSK, hw->intr_mask);
791917de 1646 spin_unlock_irq(&hw->hw_lock);
cd28ab6a
SH		 1647}
1648
302d1252
SH		 1649
1650/* Transmit timeout is only called if we are running, carries is up
1651 * and tx queue is full (stopped).
1652 */
cd28ab6a
SH		 1653static void sky2_tx_timeout(struct net_device *dev)
1654{
1655 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1656 struct sky2_hw *hw = sky2->hw;
1657 unsigned txq = txqaddr[sky2->port];
302d1252
SH		 1658 u16 ridx;
1659
1660 /* Maybe we just missed an status interrupt */
1661 spin_lock(&sky2->tx_lock);
1662 ridx = sky2_read16(hw,
1663 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1664 sky2_tx_complete(sky2, ridx);
1665 spin_unlock(&sky2->tx_lock);
1666
1667 if (!netif_queue_stopped(dev)) {
1668 if (net_ratelimit())
1669 pr_info(PFX "transmit interrupt missed? recovered\n");
1670 return;
1671 }
cd28ab6a
SH		 1672
1673 if (netif_msg_timer(sky2))
1674 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1675
8cc048e3 1676 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
8cc048e3 1677 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
cd28ab6a
SH		 1678
1679 sky2_tx_clean(sky2);
8cc048e3
SH		 1680
1681 sky2_qset(hw, txq);
1682 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
cd28ab6a
SH		 1683}
1684
734d1868
SH		 1685
1686#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
70f1be48
SH		 1687/* Want receive buffer size to be multiple of 64 bits
1688 * and incl room for vlan and truncation
1689 */
734d1868
SH		 1690static inline unsigned sky2_buf_size(int mtu)
1691{
70f1be48 1692 return roundup(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1693}
1694
cd28ab6a
SH		 1695static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1696{
6b1a3aef
SH		 1697 struct sky2_port *sky2 = netdev_priv(dev);
1698 struct sky2_hw *hw = sky2->hw;
1699 int err;
1700 u16 ctl, mode;
cd28ab6a
SH		 1701
1702 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1703 return -EINVAL;
1704
5a5b1ea0
SH		 1705 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1706 return -EINVAL;
1707
6b1a3aef
SH		 1708 if (!netif_running(dev)) {
1709 dev->mtu = new_mtu;
1710 return 0;
1711 }
1712
6b1a3aef
SH		 1713 sky2_write32(hw, B0_IMSK, 0);
1714
018d1c66
SH		 1715 dev->trans_start = jiffies; /* prevent tx timeout */
1716 netif_stop_queue(dev);
1717 netif_poll_disable(hw->dev[0]);
1718
6b1a3aef
SH		 1719 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1720 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1721 sky2_rx_stop(sky2);
1722 sky2_rx_clean(sky2);
cd28ab6a
SH		 1723
1724 dev->mtu = new_mtu;
734d1868 1725 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1726 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1727 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1728
1729 if (dev->mtu > ETH_DATA_LEN)
1730 mode |= GM_SMOD_JUMBO_ENA;
1731
1732 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1733
6b1a3aef 1734 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1735
6b1a3aef 1736 err = sky2_rx_start(sky2);
6b1a3aef 1737 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1738
1b537565
SH		 1739 if (err)
1740 dev_close(dev);
1741 else {
1742 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1743
1744 netif_poll_enable(hw->dev[0]);
1745 netif_wake_queue(dev);
1746 }
1747
cd28ab6a
SH		 1748 return err;
1749}
1750
1751/*
1752 * Receive one packet.
1753 * For small packets or errors, just reuse existing skb.
d571b694 1754 * For larger packets, get new buffer.
cd28ab6a 1755 */
d11c13e7 1756static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1757 u16 length, u32 status)
1758{
cd28ab6a 1759 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1760 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1761
1762 if (unlikely(netif_msg_rx_status(sky2)))
1763 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1764 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1765
793b883e 1766 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1767 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1768
42eeea01 1769 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1770 goto error;
1771
42eeea01
SH		 1772 if (!(status & GMR_FS_RX_OK))
1773 goto resubmit;
1774
70f1be48 1775 if (length > sky2->netdev->mtu + ETH_HLEN)
6e15b712
SH		 1776 goto oversize;
1777
bdb5c58e 1778 if (length < copybreak) {
79e57d32
SH		 1779 skb = alloc_skb(length + 2, GFP_ATOMIC);
1780 if (!skb)
793b883e
SH		 1781 goto resubmit;
1782
79e57d32 1783 skb_reserve(skb, 2);
793b883e
SH		 1784 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1785 length, PCI_DMA_FROMDEVICE);
79e57d32 1786 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1787 skb->ip_summed = re->skb->ip_summed;
1788 skb->csum = re->skb->csum;
793b883e
SH		 1789 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1790 length, PCI_DMA_FROMDEVICE);
793b883e 1791 } else {
79e57d32
SH		 1792 struct sk_buff *nskb;
1793
82788c7a 1794 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1795 if (!nskb)
1796 goto resubmit;
cd28ab6a 1797
793b883e 1798 skb = re->skb;
79e57d32 1799 re->skb = nskb;
793b883e 1800 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1801 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1802 prefetch(skb->data);
cd28ab6a 1803
793b883e 1804 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1805 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1806 }
cd28ab6a 1807
79e57d32 1808 skb_put(skb, length);
793b883e 1809resubmit:
d11c13e7 1810 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1811 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1812
bea86103 1813 /* Tell receiver about new buffers. */
290d4de5 1814 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
bea86103 1815
cd28ab6a
SH		 1816 return skb;
1817
6e15b712
SH		 1818oversize:
1819 ++sky2->net_stats.rx_over_errors;
1820 goto resubmit;
1821
cd28ab6a 1822error:
6e15b712
SH		 1823 ++sky2->net_stats.rx_errors;
1824
3be92a70 1825 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a
SH		 1826 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1827 sky2->netdev->name, status, length);
793b883e
SH		 1828
1829 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1830 sky2->net_stats.rx_length_errors++;
1831 if (status & GMR_FS_FRAGMENT)
1832 sky2->net_stats.rx_frame_errors++;
1833 if (status & GMR_FS_CRC_ERR)
1834 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1835 if (status & GMR_FS_RX_FF_OV)
1836 sky2->net_stats.rx_fifo_errors++;
79e57d32 1837
793b883e 1838 goto resubmit;
cd28ab6a
SH		 1839}
1840
2224795d
SH		 1841/*
1842 * Check for transmit complete
793b883e 1843 */
13b97b74 1844#define TX_NO_STATUS 0xffff
2224795d 1845
28bd181a 1846static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
13b97b74
SH		 1847{
1848 if (last != TX_NO_STATUS) {
1849 struct net_device *dev = hw->dev[port];
1850 if (dev && netif_running(dev)) {
1851 struct sky2_port *sky2 = netdev_priv(dev);
302d1252
SH		 1852
1853 spin_lock(&sky2->tx_lock);
13b97b74 1854 sky2_tx_complete(sky2, last);
302d1252 1855 spin_unlock(&sky2->tx_lock);
13b97b74 1856 }
2224795d 1857 }
cd28ab6a
SH		 1858}
1859
1860/*
cd28ab6a
SH		 1861 * Both ports share the same status interrupt, therefore there is only
1862 * one poll routine.
cd28ab6a 1863 */
d11c13e7 1864static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1865{
d11c13e7
SH		 1866 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1867 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1868 unsigned int work_done = 0;
793b883e 1869 u16 hwidx;
13b97b74 1870 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
cd28ab6a 1871
f9a66c7f
SH		 1872 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1873
a8fd6266
SH		 1874 /*
1875 * Kick the STAT_LEV_TIMER_CTRL timer.
1876 * This fixes my hangs on Yukon-EC (0xb6) rev 1.
1877 * The if clause is there to start the timer only if it has been
1878 * configured correctly and not been disabled via ethtool.
1879 */
1880 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_START) {
1881 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
1882 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
1883 }
1884
793b883e 1885 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1886 BUG_ON(hwidx >= STATUS_RING_SIZE);
af2a58ac 1887 rmb();
bea86103 1888
13210ce5
SH		 1889 while (hwidx != hw->st_idx) {
1890 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1891 struct net_device *dev;
d11c13e7 1892 struct sky2_port *sky2;
cd28ab6a 1893 struct sk_buff *skb;
cd28ab6a
SH		 1894 u32 status;
1895 u16 length;
1896
13210ce5 1897 le = hw->st_le + hw->st_idx;
bea86103 1898 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1899 prefetch(hw->st_le + hw->st_idx);
bea86103 1900
13210ce5
SH		 1901 BUG_ON(le->link >= 2);
1902 dev = hw->dev[le->link];
1903 if (dev == NULL || !netif_running(dev))
1904 continue;
1905
1906 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1907 status = le32_to_cpu(le->status);
1908 length = le16_to_cpu(le->length);
cd28ab6a 1909
dc4d5ea2 1910 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1911 case OP_RXSTAT:
d11c13e7 1912 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1913 if (!skb)
1914 break;
13210ce5
SH		 1915
1916 skb->dev = dev;
1917 skb->protocol = eth_type_trans(skb, dev);
1918 dev->last_rx = jiffies;
1919
d1f13708
SH		 1920#ifdef SKY2_VLAN_TAG_USED
1921 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1922 vlan_hwaccel_receive_skb(skb,
1923 sky2->vlgrp,
1924 be16_to_cpu(sky2->rx_tag));
1925 } else
1926#endif
cd28ab6a 1927 netif_receive_skb(skb);
13210ce5
SH		 1928
1929 if (++work_done >= to_do)
1930 goto exit_loop;
cd28ab6a
SH		 1931 break;
1932
d1f13708
SH		 1933#ifdef SKY2_VLAN_TAG_USED
1934 case OP_RXVLAN:
1935 sky2->rx_tag = length;
1936 break;
1937
1938 case OP_RXCHKSVLAN:
1939 sky2->rx_tag = length;
1940 /* fall through */
1941#endif
cd28ab6a 1942 case OP_RXCHKS:
d11c13e7
SH		 1943 skb = sky2->rx_ring[sky2->rx_next].skb;
1944 skb->ip_summed = CHECKSUM_HW;
1945 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1946 break;
1947
1948 case OP_TXINDEXLE:
13b97b74
SH		 1949 /* TX index reports status for both ports */
1950 tx_done[0] = status & 0xffff;
1951 tx_done[1] = ((status >> 24) & 0xff)
1952 | (u16)(length & 0xf) << 8;
cd28ab6a
SH		 1953 break;
1954
cd28ab6a
SH		 1955 default:
1956 if (net_ratelimit())
793b883e 1957 printk(KERN_WARNING PFX
dc4d5ea2 1958 "unknown status opcode 0x%x\n", le->opcode);
cd28ab6a
SH		 1959 break;
1960 }
13210ce5 1961 }
cd28ab6a 1962
13210ce5 1963exit_loop:
13b97b74
SH		 1964 sky2_tx_check(hw, 0, tx_done[0]);
1965 sky2_tx_check(hw, 1, tx_done[1]);
1966
9a6d3431
SH		 1967 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
1968 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1969 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1970 }
cd28ab6a 1971
9a6d3431 1972 if (likely(work_done < to_do)) {
791917de
SH		 1973 spin_lock_irq(&hw->hw_lock);
1974 __netif_rx_complete(dev0);
1975
cd28ab6a
SH		 1976 hw->intr_mask |= Y2_IS_STAT_BMU;
1977 sky2_write32(hw, B0_IMSK, hw->intr_mask);
791917de
SH		 1978 spin_unlock_irq(&hw->hw_lock);
1979
13210ce5
SH		 1980 return 0;
1981 } else {
1982 *budget -= work_done;
1983 dev0->quota -= work_done;
1984 return 1;
cd28ab6a 1985 }
cd28ab6a
SH		 1986}
1987
1988static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1989{
1990 struct net_device *dev = hw->dev[port];
1991
3be92a70
SH		 1992 if (net_ratelimit())
1993 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1994 dev->name, status);
cd28ab6a
SH		 1995
1996 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 1997 if (net_ratelimit())
1998 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1999 dev->name);
cd28ab6a
SH		 2000 /* Clear IRQ */
2001 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2002 }
2003
2004 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2005 if (net_ratelimit())
2006 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2007 dev->name);
cd28ab6a
SH		 2008
2009 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2010 }
2011
2012 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2013 if (net_ratelimit())
2014 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2015 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2016 }
2017
2018 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2019 if (net_ratelimit())
2020 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2021 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2022 }
2023
2024 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2025 if (net_ratelimit())
2026 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2027 dev->name);
cd28ab6a
SH		 2028 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2029 }
2030}
2031
2032static void sky2_hw_intr(struct sky2_hw *hw)
2033{
2034 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2035
793b883e 2036 if (status & Y2_IS_TIST_OV)
cd28ab6a 2037 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2038
2039 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2040 u16 pci_err;
2041
56a645cc 2042 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2043 if (net_ratelimit())
2044 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2045 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2046
2047 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2048 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2049 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2050 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2051 }
2052
2053 if (status & Y2_IS_PCI_EXP) {
d571b694 2054 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2055 u32 pex_err;
2056
56a645cc 2057 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2058
3be92a70
SH		 2059 if (net_ratelimit())
2060 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2061 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2062
2063 /* clear the interrupt */
2064 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2065 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2066 0xffffffffUL);
cd28ab6a
SH		 2067 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2068
2069 if (pex_err & PEX_FATAL_ERRORS) {
2070 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2071 hwmsk &= ~Y2_IS_PCI_EXP;
2072 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2073 }
2074 }
2075
2076 if (status & Y2_HWE_L1_MASK)
2077 sky2_hw_error(hw, 0, status);
2078 status >>= 8;
2079 if (status & Y2_HWE_L1_MASK)
2080 sky2_hw_error(hw, 1, status);
2081}
2082
2083static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2084{
2085 struct net_device *dev = hw->dev[port];
2086 struct sky2_port *sky2 = netdev_priv(dev);
2087 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2088
2089 if (netif_msg_intr(sky2))
2090 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2091 dev->name, status);
2092
2093 if (status & GM_IS_RX_FF_OR) {
2094 ++sky2->net_stats.rx_fifo_errors;
2095 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2096 }
2097
2098 if (status & GM_IS_TX_FF_UR) {
2099 ++sky2->net_stats.tx_fifo_errors;
2100 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2101 }
cd28ab6a
SH		 2102}
2103
2104static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2105{
2106 struct net_device *dev = hw->dev[port];
2107 struct sky2_port *sky2 = netdev_priv(dev);
2108
2109 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2110 sky2_write32(hw, B0_IMSK, hw->intr_mask);
791917de 2111
91c86df5 2112 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 2113}
2114
2115static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2116{
2117 struct sky2_hw *hw = dev_id;
bea86103 2118 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 2119 u32 status;
2120
2121 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 2122 if (status == 0 || status == ~0)
cd28ab6a
SH		 2123 return IRQ_NONE;
2124
791917de 2125 spin_lock(&hw->hw_lock);
cd28ab6a
SH		 2126 if (status & Y2_IS_HW_ERR)
2127 sky2_hw_intr(hw);
2128
793b883e 2129 /* Do NAPI for Rx and Tx status */
bea86103 2130 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 2131 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2132 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 2133
0a122576
SH		 2134 if (likely(__netif_rx_schedule_prep(dev0))) {
2135 prefetch(&hw->st_le[hw->st_idx]);
bea86103 2136 __netif_rx_schedule(dev0);
0a122576 2137 }
cd28ab6a
SH		 2138 }
2139
793b883e 2140 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 2141 sky2_phy_intr(hw, 0);
2142
2143 if (status & Y2_IS_IRQ_PHY2)
2144 sky2_phy_intr(hw, 1);
2145
2146 if (status & Y2_IS_IRQ_MAC1)
2147 sky2_mac_intr(hw, 0);
2148
2149 if (status & Y2_IS_IRQ_MAC2)
2150 sky2_mac_intr(hw, 1);
2151
cd28ab6a 2152 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e 2153
791917de 2154 spin_unlock(&hw->hw_lock);
793b883e 2155
cd28ab6a
SH		 2156 return IRQ_HANDLED;
2157}
2158
2159#ifdef CONFIG_NET_POLL_CONTROLLER
2160static void sky2_netpoll(struct net_device *dev)
2161{
2162 struct sky2_port *sky2 = netdev_priv(dev);
2163
793b883e 2164 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2165}
2166#endif
2167
2168/* Chip internal frequency for clock calculations */
fb17358f 2169static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2170{
793b883e 2171 switch (hw->chip_id) {
cd28ab6a 2172 case CHIP_ID_YUKON_EC:
5a5b1ea0 2173 case CHIP_ID_YUKON_EC_U:
fb17358f 2174 return 125; /* 125 Mhz */
cd28ab6a 2175 case CHIP_ID_YUKON_FE:
fb17358f 2176 return 100; /* 100 Mhz */
793b883e 2177 default: /* YUKON_XL */
fb17358f 2178 return 156; /* 156 Mhz */
cd28ab6a
SH		 2179 }
2180}
2181
fb17358f 2182static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2183{
fb17358f 2184 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2185}
2186
fb17358f 2187static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2188{
fb17358f 2189 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2190}
2191
fb17358f 2192
cd28ab6a
SH		 2193static int sky2_reset(struct sky2_hw *hw)
2194{
cd28ab6a
SH		 2195 u16 status;
2196 u8 t8, pmd_type;
56a645cc 2197 int i;
cd28ab6a 2198
cd28ab6a 2199 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2200
cd28ab6a
SH		 2201 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2202 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2203 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2204 pci_name(hw->pdev), hw->chip_id);
2205 return -EOPNOTSUPP;
2206 }
2207
290d4de5
SH		 2208 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2209
2210 /* This rev is really old, and requires untested workarounds */
2211 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2212 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2213 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2214 hw->chip_id, hw->chip_rev);
2215 return -EOPNOTSUPP;
2216 }
2217
2218 /* This chip is new and not tested yet */
2219 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2220 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2221 pci_name(hw->pdev));
2222 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2223 }
2224
cd28ab6a
SH		 2225 /* disable ASF */
2226 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2227 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2228 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2229 }
2230
2231 /* do a SW reset */
2232 sky2_write8(hw, B0_CTST, CS_RST_SET);
2233 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2234
2235 /* clear PCI errors, if any */
56a645cc 2236 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2237
cd28ab6a 2238 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2239 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2240
cd28ab6a
SH		 2241
2242 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2243
2244 /* clear any PEX errors */
56a645cc
SH		 2245 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2246 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2247
cd28ab6a
SH		 2248
2249 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2250 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2251
2252 hw->ports = 1;
2253 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2254 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2255 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2256 ++hw->ports;
2257 }
cd28ab6a 2258
5afa0a9c 2259 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2260
2261 for (i = 0; i < hw->ports; i++) {
2262 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2263 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2264 }
2265
2266 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2267
793b883e
SH		 2268 /* Clear I2C IRQ noise */
2269 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2270
2271 /* turn off hardware timer (unused) */
2272 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2273 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2274
cd28ab6a
SH		 2275 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2276
69634ee7
SH		 2277 /* Turn off descriptor polling */
2278 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2279
2280 /* Turn off receive timestamp */
2281 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2282 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2283
2284 /* enable the Tx Arbiters */
2285 for (i = 0; i < hw->ports; i++)
2286 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2287
2288 /* Initialize ram interface */
2289 for (i = 0; i < hw->ports; i++) {
793b883e 2290 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2291
2292 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2293 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2294 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2295 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2296 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2297 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2298 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2299 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2300 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2301 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2302 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2303 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2304 }
2305
cd28ab6a
SH		 2306 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2307
cd28ab6a
SH		 2308 for (i = 0; i < hw->ports; i++)
2309 sky2_phy_reset(hw, i);
cd28ab6a 2310
cd28ab6a
SH		 2311 memset(hw->st_le, 0, STATUS_LE_BYTES);
2312 hw->st_idx = 0;
2313
2314 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2315 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2316
2317 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2318 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2319
2320 /* Set the list last index */
793b883e 2321 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2322
793b883e 2323 /* These status setup values are copied from SysKonnect's driver */
290d4de5
SH		 2324 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2325 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2326
290d4de5
SH		 2327 /* set Status-FIFO ISR watermark */
2328 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2329 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2330 else
2331 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2332
290d4de5
SH		 2333 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2334 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 7));
cd28ab6a 2335
793b883e 2336 /* enable status unit */
cd28ab6a
SH		 2337 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2338
2339 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2340 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2341 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2342
2343 return 0;
2344}
2345
28bd181a 2346static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2347{
2348 u32 modes;
2349 if (hw->copper) {
793b883e
SH		 2350 modes = SUPPORTED_10baseT_Half
2351 | SUPPORTED_10baseT_Full
2352 | SUPPORTED_100baseT_Half
2353 | SUPPORTED_100baseT_Full
2354 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2355
2356 if (hw->chip_id != CHIP_ID_YUKON_FE)
2357 modes |= SUPPORTED_1000baseT_Half
793b883e 2358 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2359 } else
2360 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2361 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2362 return modes;
2363}
2364
793b883e 2365static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2366{
2367 struct sky2_port *sky2 = netdev_priv(dev);
2368 struct sky2_hw *hw = sky2->hw;
2369
2370 ecmd->transceiver = XCVR_INTERNAL;
2371 ecmd->supported = sky2_supported_modes(hw);
2372 ecmd->phy_address = PHY_ADDR_MARV;
2373 if (hw->copper) {
2374 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2375 | SUPPORTED_10baseT_Full
2376 | SUPPORTED_100baseT_Half
2377 | SUPPORTED_100baseT_Full
2378 | SUPPORTED_1000baseT_Half
2379 | SUPPORTED_1000baseT_Full
2380 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2381 ecmd->port = PORT_TP;
2382 } else
2383 ecmd->port = PORT_FIBRE;
2384
2385 ecmd->advertising = sky2->advertising;
2386 ecmd->autoneg = sky2->autoneg;
2387 ecmd->speed = sky2->speed;
2388 ecmd->duplex = sky2->duplex;
2389 return 0;
2390}
2391
2392static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2393{
2394 struct sky2_port *sky2 = netdev_priv(dev);
2395 const struct sky2_hw *hw = sky2->hw;
2396 u32 supported = sky2_supported_modes(hw);
2397
2398 if (ecmd->autoneg == AUTONEG_ENABLE) {
2399 ecmd->advertising = supported;
2400 sky2->duplex = -1;
2401 sky2->speed = -1;
2402 } else {
2403 u32 setting;
2404
793b883e 2405 switch (ecmd->speed) {
cd28ab6a
SH		 2406 case SPEED_1000:
2407 if (ecmd->duplex == DUPLEX_FULL)
2408 setting = SUPPORTED_1000baseT_Full;
2409 else if (ecmd->duplex == DUPLEX_HALF)
2410 setting = SUPPORTED_1000baseT_Half;
2411 else
2412 return -EINVAL;
2413 break;
2414 case SPEED_100:
2415 if (ecmd->duplex == DUPLEX_FULL)
2416 setting = SUPPORTED_100baseT_Full;
2417 else if (ecmd->duplex == DUPLEX_HALF)
2418 setting = SUPPORTED_100baseT_Half;
2419 else
2420 return -EINVAL;
2421 break;
2422
2423 case SPEED_10:
2424 if (ecmd->duplex == DUPLEX_FULL)
2425 setting = SUPPORTED_10baseT_Full;
2426 else if (ecmd->duplex == DUPLEX_HALF)
2427 setting = SUPPORTED_10baseT_Half;
2428 else
2429 return -EINVAL;
2430 break;
2431 default:
2432 return -EINVAL;
2433 }
2434
2435 if ((setting & supported) == 0)
2436 return -EINVAL;
2437
2438 sky2->speed = ecmd->speed;
2439 sky2->duplex = ecmd->duplex;
2440 }
2441
2442 sky2->autoneg = ecmd->autoneg;
2443 sky2->advertising = ecmd->advertising;
2444
1b537565
SH		 2445 if (netif_running(dev))
2446 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2447
2448 return 0;
2449}
2450
2451static void sky2_get_drvinfo(struct net_device *dev,
2452 struct ethtool_drvinfo *info)
2453{
2454 struct sky2_port *sky2 = netdev_priv(dev);
2455
2456 strcpy(info->driver, DRV_NAME);
2457 strcpy(info->version, DRV_VERSION);
2458 strcpy(info->fw_version, "N/A");
2459 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2460}
2461
2462static const struct sky2_stat {
793b883e
SH		 2463 char name[ETH_GSTRING_LEN];
2464 u16 offset;
cd28ab6a
SH		 2465} sky2_stats[] = {
2466 { "tx_bytes", GM_TXO_OK_HI },
2467 { "rx_bytes", GM_RXO_OK_HI },
2468 { "tx_broadcast", GM_TXF_BC_OK },
2469 { "rx_broadcast", GM_RXF_BC_OK },
2470 { "tx_multicast", GM_TXF_MC_OK },
2471 { "rx_multicast", GM_RXF_MC_OK },
2472 { "tx_unicast", GM_TXF_UC_OK },
2473 { "rx_unicast", GM_RXF_UC_OK },
2474 { "tx_mac_pause", GM_TXF_MPAUSE },
2475 { "rx_mac_pause", GM_RXF_MPAUSE },
2476 { "collisions", GM_TXF_SNG_COL },
2477 { "late_collision",GM_TXF_LAT_COL },
2478 { "aborted", GM_TXF_ABO_COL },
2479 { "multi_collisions", GM_TXF_MUL_COL },
2480 { "fifo_underrun", GM_TXE_FIFO_UR },
2481 { "fifo_overflow", GM_RXE_FIFO_OV },
2482 { "rx_toolong", GM_RXF_LNG_ERR },
2483 { "rx_jabber", GM_RXF_JAB_PKT },
2484 { "rx_runt", GM_RXE_FRAG },
2485 { "rx_too_long", GM_RXF_LNG_ERR },
2486 { "rx_fcs_error", GM_RXF_FCS_ERR },
2487};
2488
cd28ab6a
SH		 2489static u32 sky2_get_rx_csum(struct net_device *dev)
2490{
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492
2493 return sky2->rx_csum;
2494}
2495
2496static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2497{
2498 struct sky2_port *sky2 = netdev_priv(dev);
2499
2500 sky2->rx_csum = data;
793b883e 2501
cd28ab6a
SH		 2502 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2503 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2504
2505 return 0;
2506}
2507
2508static u32 sky2_get_msglevel(struct net_device *netdev)
2509{
2510 struct sky2_port *sky2 = netdev_priv(netdev);
2511 return sky2->msg_enable;
2512}
2513
9a7ae0a9
SH		 2514static int sky2_nway_reset(struct net_device *dev)
2515{
2516 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2517
2518 if (sky2->autoneg != AUTONEG_ENABLE)
2519 return -EINVAL;
2520
1b537565 2521 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2522
2523 return 0;
2524}
2525
793b883e 2526static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2527{
2528 struct sky2_hw *hw = sky2->hw;
2529 unsigned port = sky2->port;
2530 int i;
2531
2532 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2533 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2534 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2535 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2536
793b883e 2537 for (i = 2; i < count; i++)
cd28ab6a
SH		 2538 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2539}
2540
cd28ab6a
SH		 2541static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2542{
2543 struct sky2_port *sky2 = netdev_priv(netdev);
2544 sky2->msg_enable = value;
2545}
2546
2547static int sky2_get_stats_count(struct net_device *dev)
2548{
2549 return ARRAY_SIZE(sky2_stats);
2550}
2551
2552static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2553 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2554{
2555 struct sky2_port *sky2 = netdev_priv(dev);
2556
793b883e 2557 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2558}
2559
793b883e 2560static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2561{
2562 int i;
2563
2564 switch (stringset) {
2565 case ETH_SS_STATS:
2566 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2567 memcpy(data + i * ETH_GSTRING_LEN,
2568 sky2_stats[i].name, ETH_GSTRING_LEN);
2569 break;
2570 }
2571}
2572
2573/* Use hardware MIB variables for critical path statistics and
2574 * transmit feedback not reported at interrupt.
2575 * Other errors are accounted for in interrupt handler.
2576 */
2577static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2578{
2579 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2580 u64 data[13];
cd28ab6a 2581
793b883e 2582 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2583
2584 sky2->net_stats.tx_bytes = data[0];
2585 sky2->net_stats.rx_bytes = data[1];
2586 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2587 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2588 sky2->net_stats.multicast = data[5] + data[7];
2589 sky2->net_stats.collisions = data[10];
2590 sky2->net_stats.tx_aborted_errors = data[12];
2591
2592 return &sky2->net_stats;
2593}
2594
2595static int sky2_set_mac_address(struct net_device *dev, void *p)
2596{
2597 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2598 struct sky2_hw *hw = sky2->hw;
2599 unsigned port = sky2->port;
2600 const struct sockaddr *addr = p;
cd28ab6a
SH		 2601
2602 if (!is_valid_ether_addr(addr->sa_data))
2603 return -EADDRNOTAVAIL;
2604
cd28ab6a 2605 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2606 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2607 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2608 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2609 dev->dev_addr, ETH_ALEN);
1b537565 2610
a8ab1ec0
SH		 2611 /* virtual address for data */
2612 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2613
2614 /* physical address: used for pause frames */
2615 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2616
2617 return 0;
cd28ab6a
SH		 2618}
2619
2620static void sky2_set_multicast(struct net_device *dev)
2621{
2622 struct sky2_port *sky2 = netdev_priv(dev);
2623 struct sky2_hw *hw = sky2->hw;
2624 unsigned port = sky2->port;
2625 struct dev_mc_list *list = dev->mc_list;
2626 u16 reg;
2627 u8 filter[8];
2628
2629 memset(filter, 0, sizeof(filter));
2630
2631 reg = gma_read16(hw, port, GM_RX_CTRL);
2632 reg |= GM_RXCR_UCF_ENA;
2633
d571b694 2634 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2635 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2636 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2637 memset(filter, 0xff, sizeof(filter));
793b883e 2638 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2639 reg &= ~GM_RXCR_MCF_ENA;
2640 else {
2641 int i;
2642 reg |= GM_RXCR_MCF_ENA;
2643
2644 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2645 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2646 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2647 }
2648 }
2649
cd28ab6a 2650 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2651 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2652 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2653 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2654 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2655 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2656 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2657 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2658
2659 gma_write16(hw, port, GM_RX_CTRL, reg);
2660}
2661
2662/* Can have one global because blinking is controlled by
2663 * ethtool and that is always under RTNL mutex
2664 */
91c86df5 2665static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2666{
793b883e
SH		 2667 u16 pg;
2668
793b883e
SH		 2669 switch (hw->chip_id) {
2670 case CHIP_ID_YUKON_XL:
2671 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2672 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2673 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2674 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2675 PHY_M_LEDC_INIT_CTRL(7) |
2676 PHY_M_LEDC_STA1_CTRL(7) |
2677 PHY_M_LEDC_STA0_CTRL(7))
2678 : 0);
2679
2680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2681 break;
2682
2683 default:
2684 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2685 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2686 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2687 PHY_M_LED_MO_10(MO_LED_ON) |
2688 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2689 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2690 PHY_M_LED_MO_RX(MO_LED_ON)
2691 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2692 PHY_M_LED_MO_10(MO_LED_OFF) |
2693 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2694 PHY_M_LED_MO_1000(MO_LED_OFF) |
2695 PHY_M_LED_MO_RX(MO_LED_OFF));
2696
793b883e 2697 }
cd28ab6a
SH		 2698}
2699
2700/* blink LED's for finding board */
2701static int sky2_phys_id(struct net_device *dev, u32 data)
2702{
2703 struct sky2_port *sky2 = netdev_priv(dev);
2704 struct sky2_hw *hw = sky2->hw;
2705 unsigned port = sky2->port;
793b883e 2706 u16 ledctrl, ledover = 0;
cd28ab6a 2707 long ms;
91c86df5 2708 int interrupted;
cd28ab6a
SH		 2709 int onoff = 1;
2710
793b883e 2711 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2712 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2713 else
2714 ms = data * 1000;
2715
2716 /* save initial values */
91c86df5 2717 down(&sky2->phy_sema);
793b883e
SH		 2718 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2719 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2720 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2721 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2723 } else {
2724 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2725 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2726 }
cd28ab6a 2727
91c86df5
SH		 2728 interrupted = 0;
2729 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2730 sky2_led(hw, port, onoff);
2731 onoff = !onoff;
2732
91c86df5
SH		 2733 up(&sky2->phy_sema);
2734 interrupted = msleep_interruptible(250);
2735 down(&sky2->phy_sema);
2736
cd28ab6a
SH		 2737 ms -= 250;
2738 }
2739
2740 /* resume regularly scheduled programming */
793b883e
SH		 2741 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2742 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2743 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2745 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2746 } else {
2747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2748 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2749 }
91c86df5 2750 up(&sky2->phy_sema);
cd28ab6a
SH		 2751
2752 return 0;
2753}
2754
2755static void sky2_get_pauseparam(struct net_device *dev,
2756 struct ethtool_pauseparam *ecmd)
2757{
2758 struct sky2_port *sky2 = netdev_priv(dev);
2759
2760 ecmd->tx_pause = sky2->tx_pause;
2761 ecmd->rx_pause = sky2->rx_pause;
2762 ecmd->autoneg = sky2->autoneg;
2763}
2764
2765static int sky2_set_pauseparam(struct net_device *dev,
2766 struct ethtool_pauseparam *ecmd)
2767{
2768 struct sky2_port *sky2 = netdev_priv(dev);
2769 int err = 0;
2770
2771 sky2->autoneg = ecmd->autoneg;
2772 sky2->tx_pause = ecmd->tx_pause != 0;
2773 sky2->rx_pause = ecmd->rx_pause != 0;
2774
1b537565 2775 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2776
2777 return err;
2778}
2779
fb17358f
SH		 2780static int sky2_get_coalesce(struct net_device *dev,
2781 struct ethtool_coalesce *ecmd)
2782{
2783 struct sky2_port *sky2 = netdev_priv(dev);
2784 struct sky2_hw *hw = sky2->hw;
2785
2786 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2787 ecmd->tx_coalesce_usecs = 0;
2788 else {
2789 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2790 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2791 }
2792 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2793
2794 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2795 ecmd->rx_coalesce_usecs = 0;
2796 else {
2797 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2798 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2799 }
2800 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2801
2802 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2803 ecmd->rx_coalesce_usecs_irq = 0;
2804 else {
2805 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2806 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2807 }
2808
2809 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2810
2811 return 0;
2812}
2813
2814/* Note: this affect both ports */
2815static int sky2_set_coalesce(struct net_device *dev,
2816 struct ethtool_coalesce *ecmd)
2817{
2818 struct sky2_port *sky2 = netdev_priv(dev);
2819 struct sky2_hw *hw = sky2->hw;
2820 const u32 tmin = sky2_clk2us(hw, 1);
2821 const u32 tmax = 5000;
2822
2823 if (ecmd->tx_coalesce_usecs != 0 &&
2824 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2825 return -EINVAL;
2826
2827 if (ecmd->rx_coalesce_usecs != 0 &&
2828 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2829 return -EINVAL;
2830
2831 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2832 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2833 return -EINVAL;
2834
ff81fbbe 2835 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2836 return -EINVAL;
ff81fbbe 2837 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2838 return -EINVAL;
ff81fbbe 2839 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2840 return -EINVAL;
2841
2842 if (ecmd->tx_coalesce_usecs == 0)
2843 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2844 else {
2845 sky2_write32(hw, STAT_TX_TIMER_INI,
2846 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2847 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2848 }
2849 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2850
2851 if (ecmd->rx_coalesce_usecs == 0)
2852 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2853 else {
2854 sky2_write32(hw, STAT_LEV_TIMER_INI,
2855 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2856 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2857 }
2858 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2859
2860 if (ecmd->rx_coalesce_usecs_irq == 0)
2861 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2862 else {
d28d4870 2863 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2864 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2865 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2866 }
2867 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2868 return 0;
2869}
2870
793b883e
SH		 2871static void sky2_get_ringparam(struct net_device *dev,
2872 struct ethtool_ringparam *ering)
2873{
2874 struct sky2_port *sky2 = netdev_priv(dev);
2875
2876 ering->rx_max_pending = RX_MAX_PENDING;
2877 ering->rx_mini_max_pending = 0;
2878 ering->rx_jumbo_max_pending = 0;
2879 ering->tx_max_pending = TX_RING_SIZE - 1;
2880
2881 ering->rx_pending = sky2->rx_pending;
2882 ering->rx_mini_pending = 0;
2883 ering->rx_jumbo_pending = 0;
2884 ering->tx_pending = sky2->tx_pending;
2885}
2886
2887static int sky2_set_ringparam(struct net_device *dev,
2888 struct ethtool_ringparam *ering)
2889{
2890 struct sky2_port *sky2 = netdev_priv(dev);
2891 int err = 0;
2892
2893 if (ering->rx_pending > RX_MAX_PENDING ||
2894 ering->rx_pending < 8 ||
2895 ering->tx_pending < MAX_SKB_TX_LE ||
2896 ering->tx_pending > TX_RING_SIZE - 1)
2897 return -EINVAL;
2898
2899 if (netif_running(dev))
2900 sky2_down(dev);
2901
2902 sky2->rx_pending = ering->rx_pending;
2903 sky2->tx_pending = ering->tx_pending;
2904
1b537565 2905 if (netif_running(dev)) {
793b883e 2906 err = sky2_up(dev);
1b537565
SH		 2907 if (err)
2908 dev_close(dev);
6ed995bb
SH		 2909 else
2910 sky2_set_multicast(dev);
1b537565 2911 }
793b883e
SH		 2912
2913 return err;
2914}
2915
793b883e
SH		 2916static int sky2_get_regs_len(struct net_device *dev)
2917{
6e4cbb34 2918 return 0x4000;
793b883e
SH		 2919}
2920
2921/*
2922 * Returns copy of control register region
6e4cbb34 2923 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2924 */
2925static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2926 void *p)
2927{
2928 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2929 const void __iomem *io = sky2->hw->regs;
793b883e 2930
6e4cbb34 2931 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2932 regs->version = 1;
6e4cbb34 2933 memset(p, 0, regs->len);
793b883e 2934
6e4cbb34
SH		 2935 memcpy_fromio(p, io, B3_RAM_ADDR);
2936
2937 memcpy_fromio(p + B3_RI_WTO_R1,
2938 io + B3_RI_WTO_R1,
2939 regs->len - B3_RI_WTO_R1);
793b883e 2940}
cd28ab6a
SH		 2941
2942static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2943 .get_settings = sky2_get_settings,
2944 .set_settings = sky2_set_settings,
2945 .get_drvinfo = sky2_get_drvinfo,
2946 .get_msglevel = sky2_get_msglevel,
2947 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2948 .nway_reset = sky2_nway_reset,
793b883e
SH		 2949 .get_regs_len = sky2_get_regs_len,
2950 .get_regs = sky2_get_regs,
2951 .get_link = ethtool_op_get_link,
2952 .get_sg = ethtool_op_get_sg,
2953 .set_sg = ethtool_op_set_sg,
2954 .get_tx_csum = ethtool_op_get_tx_csum,
2955 .set_tx_csum = ethtool_op_set_tx_csum,
2956 .get_tso = ethtool_op_get_tso,
2957 .set_tso = ethtool_op_set_tso,
2958 .get_rx_csum = sky2_get_rx_csum,
2959 .set_rx_csum = sky2_set_rx_csum,
2960 .get_strings = sky2_get_strings,
fb17358f
SH		 2961 .get_coalesce = sky2_get_coalesce,
2962 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2963 .get_ringparam = sky2_get_ringparam,
2964 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2965 .get_pauseparam = sky2_get_pauseparam,
2966 .set_pauseparam = sky2_set_pauseparam,
793b883e 2967 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2968 .get_stats_count = sky2_get_stats_count,
2969 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2970 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2971};
2972
2973/* Initialize network device */
2974static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2975 unsigned port, int highmem)
2976{
2977 struct sky2_port *sky2;
2978 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2979
2980 if (!dev) {
2981 printk(KERN_ERR "sky2 etherdev alloc failed");
2982 return NULL;
2983 }
2984
2985 SET_MODULE_OWNER(dev);
2986 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2987 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2988 dev->open = sky2_up;
2989 dev->stop = sky2_down;
ef743d33 2990 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2991 dev->hard_start_xmit = sky2_xmit_frame;
2992 dev->get_stats = sky2_get_stats;
2993 dev->set_multicast_list = sky2_set_multicast;
2994 dev->set_mac_address = sky2_set_mac_address;
2995 dev->change_mtu = sky2_change_mtu;
2996 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2997 dev->tx_timeout = sky2_tx_timeout;
2998 dev->watchdog_timeo = TX_WATCHDOG;
2999 if (port == 0)
3000 dev->poll = sky2_poll;
3001 dev->weight = NAPI_WEIGHT;
3002#ifdef CONFIG_NET_POLL_CONTROLLER
3003 dev->poll_controller = sky2_netpoll;
3004#endif
cd28ab6a
SH		 3005
3006 sky2 = netdev_priv(dev);
3007 sky2->netdev = dev;
3008 sky2->hw = hw;
3009 sky2->msg_enable = netif_msg_init(debug, default_msg);
3010
3011 spin_lock_init(&sky2->tx_lock);
3012 /* Auto speed and flow control */
3013 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3014 sky2->tx_pause = 1;
cd28ab6a
SH		 3015 sky2->rx_pause = 1;
3016 sky2->duplex = -1;
3017 sky2->speed = -1;
3018 sky2->advertising = sky2_supported_modes(hw);
75d070c5
SH		 3019
3020 /* Receive checksum disabled for Yukon XL
3021 * because of observed problems with incorrect
3022 * values when multiple packets are received in one interrupt
3023 */
3024 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3025
91c86df5
SH		 3026 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3027 init_MUTEX(&sky2->phy_sema);
793b883e 3028 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3029 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3030 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3031
3032 hw->dev[port] = dev;
3033
3034 sky2->port = port;
3035
5a5b1ea0
SH		 3036 dev->features |= NETIF_F_LLTX;
3037 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3038 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3039 if (highmem)
3040 dev->features |= NETIF_F_HIGHDMA;
793b883e 3041 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3042
d1f13708
SH		 3043#ifdef SKY2_VLAN_TAG_USED
3044 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3045 dev->vlan_rx_register = sky2_vlan_rx_register;
3046 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3047#endif
3048
cd28ab6a 3049 /* read the mac address */
793b883e 3050 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3051 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3052
3053 /* device is off until link detection */
3054 netif_carrier_off(dev);
3055 netif_stop_queue(dev);
3056
3057 return dev;
3058}
3059
28bd181a 3060static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3061{
3062 const struct sky2_port *sky2 = netdev_priv(dev);
3063
3064 if (netif_msg_probe(sky2))
3065 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3066 dev->name,
3067 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3068 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3069}
3070
3071static int __devinit sky2_probe(struct pci_dev *pdev,
3072 const struct pci_device_id *ent)
3073{
793b883e 3074 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3075 struct sky2_hw *hw;
5afa0a9c 3076 int err, pm_cap, using_dac = 0;
cd28ab6a 3077
793b883e
SH		 3078 err = pci_enable_device(pdev);
3079 if (err) {
cd28ab6a
SH		 3080 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3081 pci_name(pdev));
3082 goto err_out;
3083 }
3084
793b883e
SH		 3085 err = pci_request_regions(pdev, DRV_NAME);
3086 if (err) {
cd28ab6a
SH		 3087 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3088 pci_name(pdev));
793b883e 3089 goto err_out;
cd28ab6a
SH		 3090 }
3091
3092 pci_set_master(pdev);
3093
5afa0a9c
SH		 3094 /* Find power-management capability. */
3095 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3096 if (pm_cap == 0) {
3097 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3098 "aborting.\n");
3099 err = -EIO;
3100 goto err_out_free_regions;
3101 }
3102
d1f3d4dd
SH		 3103 if (sizeof(dma_addr_t) > sizeof(u32) &&
3104 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3105 using_dac = 1;
3106 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3107 if (err < 0) {
3108 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3109 "for consistent allocations\n", pci_name(pdev));
3110 goto err_out_free_regions;
3111 }
cd28ab6a 3112
d1f3d4dd 3113 } else {
cd28ab6a
SH		 3114 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3115 if (err) {
3116 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3117 pci_name(pdev));
3118 goto err_out_free_regions;
3119 }
3120 }
d1f3d4dd 3121
cd28ab6a 3122 err = -ENOMEM;
6aad85d6 3123 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3124 if (!hw) {
3125 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3126 pci_name(pdev));
3127 goto err_out_free_regions;
3128 }
3129
cd28ab6a 3130 hw->pdev = pdev;
cd28ab6a
SH		 3131
3132 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3133 if (!hw->regs) {
3134 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3135 pci_name(pdev));
3136 goto err_out_free_hw;
3137 }
5afa0a9c 3138 hw->pm_cap = pm_cap;
791917de 3139 spin_lock_init(&hw->hw_lock);
cd28ab6a 3140
56a645cc
SH		 3141#ifdef __BIG_ENDIAN
3142 /* byte swap descriptors in hardware */
3143 {
3144 u32 reg;
3145
3146 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3147 reg |= PCI_REV_DESC;
3148 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3149 }
3150#endif
3151
08c06d8a
SH		 3152 /* ring for status responses */
3153 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3154 &hw->st_dma);
3155 if (!hw->st_le)
3156 goto err_out_iounmap;
3157
cd28ab6a
SH		 3158 err = sky2_reset(hw);
3159 if (err)
793b883e 3160 goto err_out_iounmap;
cd28ab6a 3161
5f4f9dc1
SH		 3162 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3163 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3164 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3165 hw->chip_id, hw->chip_rev);
cd28ab6a 3166
793b883e
SH		 3167 dev = sky2_init_netdev(hw, 0, using_dac);
3168 if (!dev)
cd28ab6a
SH		 3169 goto err_out_free_pci;
3170
793b883e
SH		 3171 err = register_netdev(dev);
3172 if (err) {
cd28ab6a
SH		 3173 printk(KERN_ERR PFX "%s: cannot register net device\n",
3174 pci_name(pdev));
3175 goto err_out_free_netdev;
3176 }
3177
3178 sky2_show_addr(dev);
3179
3180 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3181 if (register_netdev(dev1) == 0)
3182 sky2_show_addr(dev1);
3183 else {
3184 /* Failure to register second port need not be fatal */
793b883e
SH		 3185 printk(KERN_WARNING PFX
3186 "register of second port failed\n");
cd28ab6a
SH		 3187 hw->dev[1] = NULL;
3188 free_netdev(dev1);
3189 }
3190 }
3191
28a31860 3192 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
793b883e
SH		 3193 if (err) {
3194 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3195 pci_name(pdev), pdev->irq);
3196 goto err_out_unregister;
3197 }
3198
3199 hw->intr_mask = Y2_IS_BASE;
3200 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3201
3202 pci_set_drvdata(pdev, hw);
3203
cd28ab6a
SH		 3204 return 0;
3205
793b883e
SH		 3206err_out_unregister:
3207 if (dev1) {
3208 unregister_netdev(dev1);
3209 free_netdev(dev1);
3210 }
3211 unregister_netdev(dev);
cd28ab6a
SH		 3212err_out_free_netdev:
3213 free_netdev(dev);
cd28ab6a 3214err_out_free_pci:
793b883e 3215 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3216 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3217err_out_iounmap:
3218 iounmap(hw->regs);
3219err_out_free_hw:
3220 kfree(hw);
3221err_out_free_regions:
3222 pci_release_regions(pdev);
cd28ab6a 3223 pci_disable_device(pdev);
cd28ab6a
SH		 3224err_out:
3225 return err;
3226}
3227
3228static void __devexit sky2_remove(struct pci_dev *pdev)
3229{
793b883e 3230 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3231 struct net_device *dev0, *dev1;
3232
793b883e 3233 if (!hw)
cd28ab6a
SH		 3234 return;
3235
cd28ab6a 3236 dev0 = hw->dev[0];
793b883e
SH		 3237 dev1 = hw->dev[1];
3238 if (dev1)
3239 unregister_netdev(dev1);
cd28ab6a
SH		 3240 unregister_netdev(dev0);
3241
793b883e 3242 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3243 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3244 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3245 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3246 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3247
3248 free_irq(pdev->irq, hw);
793b883e 3249 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3250 pci_release_regions(pdev);
3251 pci_disable_device(pdev);
793b883e 3252
cd28ab6a
SH		 3253 if (dev1)
3254 free_netdev(dev1);
3255 free_netdev(dev0);
3256 iounmap(hw->regs);
3257 kfree(hw);
5afa0a9c 3258
cd28ab6a
SH		 3259 pci_set_drvdata(pdev, NULL);
3260}
3261
3262#ifdef CONFIG_PM
3263static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3264{
793b883e 3265 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3266 int i;
cd28ab6a
SH		 3267
3268 for (i = 0; i < 2; i++) {
3269 struct net_device *dev = hw->dev[i];
3270
3271 if (dev) {
5afa0a9c
SH		 3272 if (!netif_running(dev))
3273 continue;
3274
3275 sky2_down(dev);
cd28ab6a 3276 netif_device_detach(dev);
cd28ab6a
SH		 3277 }
3278 }
3279
5afa0a9c 3280 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3281}
3282
3283static int sky2_resume(struct pci_dev *pdev)
3284{
793b883e 3285 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3286 int i, err;
cd28ab6a 3287
cd28ab6a
SH		 3288 pci_restore_state(pdev);
3289 pci_enable_wake(pdev, PCI_D0, 0);
08c06d8a
SH		 3290 err = sky2_set_power_state(hw, PCI_D0);
3291 if (err)
3292 goto out;
cd28ab6a 3293
08c06d8a
SH		 3294 err = sky2_reset(hw);
3295 if (err)
3296 goto out;
cd28ab6a
SH		 3297
3298 for (i = 0; i < 2; i++) {
3299 struct net_device *dev = hw->dev[i];
08c06d8a
SH		 3300 if (dev && netif_running(dev)) {
3301 netif_device_attach(dev);
3302 err = sky2_up(dev);
3303 if (err) {
3304 printk(KERN_ERR PFX "%s: could not up: %d\n",
3305 dev->name, err);
3306 dev_close(dev);
3307 break;
5afa0a9c 3308 }
cd28ab6a
SH		 3309 }
3310 }
08c06d8a
SH		 3311out:
3312 return err;
cd28ab6a
SH		 3313}
3314#endif
3315
3316static struct pci_driver sky2_driver = {
793b883e
SH		 3317 .name = DRV_NAME,
3318 .id_table = sky2_id_table,
3319 .probe = sky2_probe,
3320 .remove = __devexit_p(sky2_remove),
cd28ab6a 3321#ifdef CONFIG_PM
793b883e
SH		 3322 .suspend = sky2_suspend,
3323 .resume = sky2_resume,
cd28ab6a
SH		 3324#endif
3325};
3326
3327static int __init sky2_init_module(void)
3328{
50241c4c 3329 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3330}
3331
3332static void __exit sky2_cleanup_module(void)
3333{
3334 pci_unregister_driver(&sky2_driver);
3335}
3336
3337module_init(sky2_init_module);
3338module_exit(sky2_cleanup_module);
3339
3340MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3341MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3342MODULE_LICENSE("GPL");
5f4f9dc1 3343MODULE_VERSION(DRV_VERSION);
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