]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/sky2.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: check for more work before leaving NAPI
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
c9bdd4b5 35#include <net/ip.h>
cd28ab6a
SH		 36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
3cf26753 42#include <linux/debugfs.h>
ef743d33 43#include <linux/mii.h>
cd28ab6a
SH		 44
45#include <asm/irq.h>
46
d1f13708
SH		 47#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48#define SKY2_VLAN_TAG_USED 1
49#endif
50
cd28ab6a
SH		 51#include "sky2.h"
52
53#define DRV_NAME "sky2"
a73b629b 54#define DRV_VERSION "1.15"
cd28ab6a
SH		 55#define PFX DRV_NAME " "
56
57/*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
14d0263f 60 * similar to Tigon3.
cd28ab6a
SH		 61 */
62
14d0263f 63#define RX_LE_SIZE 1024
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 65#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 77#define TX_WATCHDOG (5 * HZ)
78#define NAPI_WEIGHT 64
79#define PHY_RETRIES 1000
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
c59697e0 100static int idle_timeout = 100;
01bd7564 101module_param(idle_timeout, int, 0);
e561a83b 102MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 103
cd28ab6a 104static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 135 { 0 }
136};
793b883e 137
cd28ab6a
SH		 138MODULE_DEVICE_TABLE(pci, sky2_id_table);
139
140/* Avoid conditionals by using array */
141static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
142static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 143static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 144
92f965e8
SH		 145/* This driver supports yukon2 chipset only */
146static const char *yukon2_name[] = {
147 "XL", /* 0xb3 */
148 "EC Ultra", /* 0xb4 */
93745494 149 "Extreme", /* 0xb5 */
92f965e8
SH		 150 "EC", /* 0xb6 */
151 "FE", /* 0xb7 */
793b883e
SH		 152};
153
793b883e 154/* Access to external PHY */
ef743d33 155static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 156{
157 int i;
158
159 gma_write16(hw, port, GM_SMI_DATA, val);
160 gma_write16(hw, port, GM_SMI_CTRL,
161 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
162
163 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 164 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 165 return 0;
793b883e 166 udelay(1);
cd28ab6a 167 }
ef743d33 168
793b883e 169 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 170 return -ETIMEDOUT;
cd28ab6a
SH		 171}
172
ef743d33 173static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 174{
175 int i;
176
793b883e 177 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 178 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
179
180 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 181 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
182 *val = gma_read16(hw, port, GM_SMI_DATA);
183 return 0;
184 }
185
793b883e 186 udelay(1);
cd28ab6a
SH		 187 }
188
ef743d33
SH		 189 return -ETIMEDOUT;
190}
191
192static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
193{
194 u16 v;
195
196 if (__gm_phy_read(hw, port, reg, &v) != 0)
197 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
198 return v;
cd28ab6a
SH		 199}
200
5afa0a9c 201
ae306cca
SH		 202static void sky2_power_on(struct sky2_hw *hw)
203{
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 207
ae306cca
SH		 208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 210
ae306cca
SH		 211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
217 else
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 219
93745494 220 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
fc99fe06 221 u32 reg;
5afa0a9c 222
fc99fe06
SH		 223 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
224 /* set all bits to 0 except bits 15..12 and 8 */
225 reg &= P_ASPM_CONTROL_MSK;
226 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
227
228 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
229 /* set all bits to 0 except bits 28 & 27 */
230 reg &= P_CTL_TIM_VMAIN_AV_MSK;
231 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
232
233 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 234
235 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
236 reg = sky2_read32(hw, B2_GP_IO);
237 reg |= GLB_GPIO_STAT_RACE_DIS;
238 sky2_write32(hw, B2_GP_IO, reg);
5afa0a9c 239 }
ae306cca 240}
5afa0a9c 241
ae306cca
SH		 242static void sky2_power_aux(struct sky2_hw *hw)
243{
244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 258}
259
d3bcfbeb 260static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 261{
262 u16 reg;
263
264 /* disable all GMAC IRQ's */
265 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
266 /* disable PHY IRQs */
267 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 268
cd28ab6a
SH		 269 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
270 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
271 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
272 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
273
274 reg = gma_read16(hw, port, GM_RX_CTRL);
275 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
276 gma_write16(hw, port, GM_RX_CTRL, reg);
277}
278
16ad91e1
SH		 279/* flow control to advertise bits */
280static const u16 copper_fc_adv[] = {
281 [FC_NONE] = 0,
282 [FC_TX] = PHY_M_AN_ASP,
283 [FC_RX] = PHY_M_AN_PC,
284 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
285};
286
287/* flow control to advertise bits when using 1000BaseX */
288static const u16 fiber_fc_adv[] = {
289 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
290 [FC_TX] = PHY_M_P_ASYM_MD_X,
291 [FC_RX] = PHY_M_P_SYM_MD_X,
292 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
293};
294
295/* flow control to GMA disable bits */
296static const u16 gm_fc_disable[] = {
297 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
298 [FC_TX] = GM_GPCR_FC_RX_DIS,
299 [FC_RX] = GM_GPCR_FC_TX_DIS,
300 [FC_BOTH] = 0,
301};
302
303
cd28ab6a
SH		 304static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
305{
306 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 307 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 308
93745494
SH		 309 if (sky2->autoneg == AUTONEG_ENABLE
310 && !(hw->chip_id == CHIP_ID_YUKON_XL
311 || hw->chip_id == CHIP_ID_YUKON_EC_U
312 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 313 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
314
315 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 316 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 317 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
318
53419c68 319 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 320 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 321 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
323 else
53419c68
SH		 324 /* set master & slave downshift counter to 1x */
325 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 326
327 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
328 }
329
330 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 331 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 332 if (hw->chip_id == CHIP_ID_YUKON_FE) {
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
335 } else {
336 /* disable energy detect */
337 ctrl &= ~PHY_M_PC_EN_DET_MSK;
338
339 /* enable automatic crossover */
340 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
341
53419c68 342 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494
SH		 343 if (sky2->autoneg == AUTONEG_ENABLE
344 && (hw->chip_id == CHIP_ID_YUKON_XL
345 || hw->chip_id == CHIP_ID_YUKON_EC_U
346 || hw->chip_id == CHIP_ID_YUKON_EX)) {
53419c68 347 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 348 ctrl &= ~PHY_M_PC_DSC_MSK;
349 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
350 }
351 }
cd28ab6a
SH		 352 } else {
353 /* workaround for deviation #4.88 (CRC errors) */
354 /* disable Automatic Crossover */
355
356 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 357 }
cd28ab6a 358
b89165f2
SH		 359 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
360
361 /* special setup for PHY 88E1112 Fiber */
362 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
363 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 364
b89165f2
SH		 365 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
367 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
368 ctrl &= ~PHY_M_MAC_MD_MSK;
369 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
370 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
371
372 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 373 /* select page 1 to access Fiber registers */
374 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 375
376 /* for SFP-module set SIGDET polarity to low */
377 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
378 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 379 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 380 }
b89165f2
SH		 381
382 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 383 }
384
7800fddc 385 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 386 ct1000 = 0;
387 adv = PHY_AN_CSMA;
2eaba1a2 388 reg = 0;
cd28ab6a
SH		 389
390 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 391 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 ct1000 |= PHY_M_1000C_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 ct1000 |= PHY_M_1000C_AHD;
396 if (sky2->advertising & ADVERTISED_100baseT_Full)
397 adv |= PHY_M_AN_100_FD;
398 if (sky2->advertising & ADVERTISED_100baseT_Half)
399 adv |= PHY_M_AN_100_HD;
400 if (sky2->advertising & ADVERTISED_10baseT_Full)
401 adv |= PHY_M_AN_10_FD;
402 if (sky2->advertising & ADVERTISED_10baseT_Half)
403 adv |= PHY_M_AN_10_HD;
709c6e7b 404
16ad91e1 405 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 406 } else { /* special defines for FIBER (88E1040S only) */
407 if (sky2->advertising & ADVERTISED_1000baseT_Full)
408 adv |= PHY_M_AN_1000X_AFD;
409 if (sky2->advertising & ADVERTISED_1000baseT_Half)
410 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 411
16ad91e1 412 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 413 }
cd28ab6a
SH		 414
415 /* Restart Auto-negotiation */
416 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
417 } else {
418 /* forced speed/duplex settings */
419 ct1000 = PHY_M_1000C_MSE;
420
2eaba1a2
SH		 421 /* Disable auto update for duplex flow control and speed */
422 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 423
424 switch (sky2->speed) {
425 case SPEED_1000:
426 ctrl |= PHY_CT_SP1000;
2eaba1a2 427 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 428 break;
429 case SPEED_100:
430 ctrl |= PHY_CT_SP100;
2eaba1a2 431 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 432 break;
433 }
434
2eaba1a2
SH		 435 if (sky2->duplex == DUPLEX_FULL) {
436 reg |= GM_GPCR_DUP_FULL;
437 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 438 } else if (sky2->speed < SPEED_1000)
439 sky2->flow_mode = FC_NONE;
2eaba1a2 440
2eaba1a2 441
16ad91e1 442 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 443
444 /* Forward pause packets to GMAC? */
16ad91e1 445 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
447 else
448 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 449 }
450
2eaba1a2
SH		 451 gma_write16(hw, port, GM_GP_CTRL, reg);
452
cd28ab6a
SH		 453 if (hw->chip_id != CHIP_ID_YUKON_FE)
454 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
455
456 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
457 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
458
459 /* Setup Phy LED's */
460 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
461 ledover = 0;
462
463 switch (hw->chip_id) {
464 case CHIP_ID_YUKON_FE:
465 /* on 88E3082 these bits are at 11..9 (shifted left) */
466 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
467
468 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
469
470 /* delete ACT LED control bits */
471 ctrl &= ~PHY_M_FELP_LED1_MSK;
472 /* change ACT LED control to blink mode */
473 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
474 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
475 break;
476
477 case CHIP_ID_YUKON_XL:
793b883e 478 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 479
480 /* select page 3 to access LED control register */
481 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
482
483 /* set LED Function Control register */
ed6d32c7
SH		 484 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
485 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
486 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
487 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
488 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 489
490 /* set Polarity Control register */
491 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 492 (PHY_M_POLC_LS1_P_MIX(4) |
493 PHY_M_POLC_IS0_P_MIX(4) |
494 PHY_M_POLC_LOS_CTRL(2) |
495 PHY_M_POLC_INIT_CTRL(2) |
496 PHY_M_POLC_STA1_CTRL(2) |
497 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 498
499 /* restore page register */
793b883e 500 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 501 break;
93745494 502
ed6d32c7 503 case CHIP_ID_YUKON_EC_U:
93745494 504 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 505 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
506
507 /* select page 3 to access LED control register */
508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
509
510 /* set LED Function Control register */
511 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
512 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
513 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
514 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
515 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
516
517 /* set Blink Rate in LED Timer Control Register */
518 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
519 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
520 /* restore page register */
521 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
522 break;
cd28ab6a
SH		 523
524 default:
525 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
526 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
527 /* turn off the Rx LED (LED_RX) */
0efdf262 528 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 529 }
530
9467a8fc
SH		 531 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
532 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 533 /* apply fixes in PHY AFE */
ed6d32c7
SH		 534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
535
977bdf06 536 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 537 gm_phy_write(hw, port, 0x18, 0xaa99);
538 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 539
977bdf06 540 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 541 gm_phy_write(hw, port, 0x18, 0xa204);
542 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 543
544 /* set page register to 0 */
9467a8fc 545 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 546 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 547 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 548
977bdf06
SH		 549 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
550 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 551 ledover |= PHY_M_LED_MO_100;
977bdf06 552 }
cd28ab6a 553
977bdf06
SH		 554 if (ledover)
555 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
556
557 }
2eaba1a2 558
d571b694 559 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 560 if (sky2->autoneg == AUTONEG_ENABLE)
561 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
562 else
563 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
564}
565
d3bcfbeb
SH		 566static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
567{
568 u32 reg1;
569 static const u32 phy_power[]
570 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
571
572 /* looks like this XL is back asswards .. */
573 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
574 onoff = !onoff;
575
aed2cec4 576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 577 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 578 if (onoff)
579 /* Turn off phy power saving */
580 reg1 &= ~phy_power[port];
581 else
582 reg1 |= phy_power[port];
583
584 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 585 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 586 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 587 udelay(100);
588}
589
1b537565
SH		 590/* Force a renegotiation */
591static void sky2_phy_reinit(struct sky2_port *sky2)
592{
e07b1aa8 593 spin_lock_bh(&sky2->phy_lock);
1b537565 594 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 595 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 596}
597
e3173832
SH		 598/* Put device in state to listen for Wake On Lan */
599static void sky2_wol_init(struct sky2_port *sky2)
600{
601 struct sky2_hw *hw = sky2->hw;
602 unsigned port = sky2->port;
603 enum flow_control save_mode;
604 u16 ctrl;
605 u32 reg1;
606
607 /* Bring hardware out of reset */
608 sky2_write16(hw, B0_CTST, CS_RST_CLR);
609 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
610
611 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
612 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
613
614 /* Force to 10/100
615 * sky2_reset will re-enable on resume
616 */
617 save_mode = sky2->flow_mode;
618 ctrl = sky2->advertising;
619
620 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
621 sky2->flow_mode = FC_NONE;
622 sky2_phy_power(hw, port, 1);
623 sky2_phy_reinit(sky2);
624
625 sky2->flow_mode = save_mode;
626 sky2->advertising = ctrl;
627
628 /* Set GMAC to no flow control and auto update for speed/duplex */
629 gma_write16(hw, port, GM_GP_CTRL,
630 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
631 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
632
633 /* Set WOL address */
634 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
635 sky2->netdev->dev_addr, ETH_ALEN);
636
637 /* Turn on appropriate WOL control bits */
638 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
639 ctrl = 0;
640 if (sky2->wol & WAKE_PHY)
641 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
642 else
643 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
644
645 if (sky2->wol & WAKE_MAGIC)
646 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
647 else
648 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
649
650 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
651 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
652
653 /* Turn on legacy PCI-Express PME mode */
654 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
655 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
656 reg1 |= PCI_Y2_PME_LEGACY;
657 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
658 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
659
660 /* block receiver */
661 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
662
663}
664
69161611
SH		 665static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
666{
667 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev != CHIP_REV_YU_EX_A0) {
668 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
669 TX_STFW_ENA |
670 (hw->dev[port]->mtu > ETH_DATA_LEN) ? TX_JUMBO_ENA : TX_JUMBO_DIS);
671 } else {
672 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
673 /* set Tx GMAC FIFO Almost Empty Threshold */
674 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
675 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
676
677 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
678 TX_JUMBO_ENA | TX_STFW_DIS);
679
680 /* Can't do offload because of lack of store/forward */
681 hw->dev[port]->features &= ~(NETIF_F_TSO | NETIF_F_SG
682 | NETIF_F_ALL_CSUM);
683 } else
684 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
685 TX_JUMBO_DIS | TX_STFW_ENA);
686 }
687}
688
cd28ab6a
SH		 689static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
690{
691 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
692 u16 reg;
693 int i;
694 const u8 *addr = hw->dev[port]->dev_addr;
695
42eeea01 696 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
b4ed372b 697 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 698
699 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
700
793b883e 701 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 702 /* WA DEV_472 -- looks like crossed wires on port 2 */
703 /* clear GMAC 1 Control reset */
704 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
705 do {
706 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
707 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
708 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
709 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
710 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
711 }
712
793b883e 713 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 714
2eaba1a2
SH		 715 /* Enable Transmit FIFO Underrun */
716 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
717
e07b1aa8 718 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 719 sky2_phy_init(hw, port);
e07b1aa8 720 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 721
722 /* MIB clear */
723 reg = gma_read16(hw, port, GM_PHY_ADDR);
724 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
725
43f2f104
SH		 726 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
727 gma_read16(hw, port, i);
cd28ab6a
SH		 728 gma_write16(hw, port, GM_PHY_ADDR, reg);
729
730 /* transmit control */
731 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
732
733 /* receive control reg: unicast + multicast + no FCS */
734 gma_write16(hw, port, GM_RX_CTRL,
793b883e 735 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 736
737 /* transmit flow control */
738 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
739
740 /* transmit parameter */
741 gma_write16(hw, port, GM_TX_PARAM,
742 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
743 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
744 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
745 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
746
747 /* serial mode register */
748 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 749 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 750
6b1a3aef 751 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 752 reg |= GM_SMOD_JUMBO_ENA;
753
754 gma_write16(hw, port, GM_SERIAL_MODE, reg);
755
cd28ab6a
SH		 756 /* virtual address for data */
757 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
758
793b883e
SH		 759 /* physical address: used for pause frames */
760 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
761
762 /* ignore counter overflows */
cd28ab6a
SH		 763 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
764 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
765 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
766
767 /* Configure Rx MAC FIFO */
768 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
69161611
SH		 769 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
770 if (hw->chip_id == CHIP_ID_YUKON_EX)
771 reg |= GMF_RX_OVER_ON;
772
773 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
cd28ab6a 774
d571b694 775 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 776 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 777
8df9a876
SH		 778 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
779 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 780
781 /* Configure Tx MAC FIFO */
782 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
783 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 784
93745494 785 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 786 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 787 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 788
69161611 789 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 790 }
791
cd28ab6a
SH		 792}
793
67712901
SH		 794/* Assign Ram Buffer allocation to queue */
795static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 796{
67712901
SH		 797 u32 end;
798
799 /* convert from K bytes to qwords used for hw register */
800 start *= 1024/8;
801 space *= 1024/8;
802 end = start + space - 1;
793b883e 803
cd28ab6a
SH		 804 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
805 sky2_write32(hw, RB_ADDR(q, RB_START), start);
806 sky2_write32(hw, RB_ADDR(q, RB_END), end);
807 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
808 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
809
810 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 811 u32 tp = space - space/4;
793b883e 812
1c28f6ba
SH		 813 /* On receive queue's set the thresholds
814 * give receiver priority when > 3/4 full
815 * send pause when down to 2K
816 */
817 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
818 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 819
1c28f6ba
SH		 820 tp = space - 2048/8;
821 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
822 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 823 } else {
824 /* Enable store & forward on Tx queue's because
825 * Tx FIFO is only 1K on Yukon
826 */
827 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
828 }
829
830 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 831 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 832}
833
cd28ab6a 834/* Setup Bus Memory Interface */
af4ed7e6 835static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 836{
837 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
838 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
839 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 840 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 841}
842
cd28ab6a
SH		 843/* Setup prefetch unit registers. This is the interface between
844 * hardware and driver list elements
845 */
8cc048e3 846static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 847 u64 addr, u32 last)
848{
cd28ab6a
SH		 849 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
850 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
851 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
852 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
853 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
854 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 855
856 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 857}
858
793b883e
SH		 859static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
860{
861 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
862
cb5d9547 863 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 864 le->ctrl = 0;
793b883e
SH		 865 return le;
866}
cd28ab6a 867
291ea614
SH		 868static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
869 struct sky2_tx_le *le)
870{
871 return sky2->tx_ring + (le - sky2->tx_le);
872}
873
290d4de5
SH		 874/* Update chip's next pointer */
875static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 876{
50432cb5 877 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 878 wmb();
50432cb5
SH		 879 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
880
881 /* Synchronize I/O on since next processor may write to tail */
882 mmiowb();
cd28ab6a
SH		 883}
884
793b883e 885
cd28ab6a
SH		 886static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
887{
888 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 889 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 890 le->ctrl = 0;
cd28ab6a
SH		 891 return le;
892}
893
a018e330
SH		 894/* Return high part of DMA address (could be 32 or 64 bit) */
895static inline u32 high32(dma_addr_t a)
896{
a036119f 897 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 898}
899
14d0263f
SH		 900/* Build description to hardware for one receive segment */
901static void sky2_rx_add(struct sky2_port *sky2, u8 op,
902 dma_addr_t map, unsigned len)
cd28ab6a
SH		 903{
904 struct sky2_rx_le *le;
734d1868 905 u32 hi = high32(map);
cd28ab6a 906
793b883e 907 if (sky2->rx_addr64 != hi) {
cd28ab6a 908 le = sky2_next_rx(sky2);
793b883e 909 le->addr = cpu_to_le32(hi);
cd28ab6a 910 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 911 sky2->rx_addr64 = high32(map + len);
cd28ab6a 912 }
793b883e 913
cd28ab6a 914 le = sky2_next_rx(sky2);
734d1868
SH		 915 le->addr = cpu_to_le32((u32) map);
916 le->length = cpu_to_le16(len);
14d0263f 917 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 918}
919
14d0263f
SH		 920/* Build description to hardware for one possibly fragmented skb */
921static void sky2_rx_submit(struct sky2_port *sky2,
922 const struct rx_ring_info *re)
923{
924 int i;
925
926 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
927
928 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
929 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
930}
931
932
933static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
934 unsigned size)
935{
936 struct sk_buff *skb = re->skb;
937 int i;
938
939 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
940 pci_unmap_len_set(re, data_size, size);
941
942 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
943 re->frag_addr[i] = pci_map_page(pdev,
944 skb_shinfo(skb)->frags[i].page,
945 skb_shinfo(skb)->frags[i].page_offset,
946 skb_shinfo(skb)->frags[i].size,
947 PCI_DMA_FROMDEVICE);
948}
949
950static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
951{
952 struct sk_buff *skb = re->skb;
953 int i;
954
955 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
956 PCI_DMA_FROMDEVICE);
957
958 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
959 pci_unmap_page(pdev, re->frag_addr[i],
960 skb_shinfo(skb)->frags[i].size,
961 PCI_DMA_FROMDEVICE);
962}
793b883e 963
cd28ab6a
SH		 964/* Tell chip where to start receive checksum.
965 * Actually has two checksums, but set both same to avoid possible byte
966 * order problems.
967 */
793b883e 968static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 969{
970 struct sky2_rx_le *le;
971
69161611
SH		 972 if (sky2->hw->chip_id != CHIP_ID_YUKON_EX) {
973 le = sky2_next_rx(sky2);
974 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
975 le->ctrl = 0;
976 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 977
69161611
SH		 978 sky2_write32(sky2->hw,
979 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
980 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
981 }
cd28ab6a
SH		 982
983}
984
6b1a3aef
SH		 985/*
986 * The RX Stop command will not work for Yukon-2 if the BMU does not
987 * reach the end of packet and since we can't make sure that we have
988 * incoming data, we must reset the BMU while it is not doing a DMA
989 * transfer. Since it is possible that the RX path is still active,
990 * the RX RAM buffer will be stopped first, so any possible incoming
991 * data will not trigger a DMA. After the RAM buffer is stopped, the
992 * BMU is polled until any DMA in progress is ended and only then it
993 * will be reset.
994 */
995static void sky2_rx_stop(struct sky2_port *sky2)
996{
997 struct sky2_hw *hw = sky2->hw;
998 unsigned rxq = rxqaddr[sky2->port];
999 int i;
1000
1001 /* disable the RAM Buffer receive queue */
1002 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1003
1004 for (i = 0; i < 0xffff; i++)
1005 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1006 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1007 goto stopped;
1008
1009 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1010 sky2->netdev->name);
1011stopped:
1012 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1013
1014 /* reset the Rx prefetch unit */
1015 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1016 mmiowb();
6b1a3aef 1017}
793b883e 1018
d571b694 1019/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1020static void sky2_rx_clean(struct sky2_port *sky2)
1021{
1022 unsigned i;
1023
1024 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1025 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1026 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1027
1028 if (re->skb) {
14d0263f 1029 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1030 kfree_skb(re->skb);
1031 re->skb = NULL;
1032 }
1033 }
1034}
1035
ef743d33
SH		 1036/* Basic MII support */
1037static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1038{
1039 struct mii_ioctl_data *data = if_mii(ifr);
1040 struct sky2_port *sky2 = netdev_priv(dev);
1041 struct sky2_hw *hw = sky2->hw;
1042 int err = -EOPNOTSUPP;
1043
1044 if (!netif_running(dev))
1045 return -ENODEV; /* Phy still in reset */
1046
d89e1343 1047 switch (cmd) {
ef743d33
SH		 1048 case SIOCGMIIPHY:
1049 data->phy_id = PHY_ADDR_MARV;
1050
1051 /* fallthru */
1052 case SIOCGMIIREG: {
1053 u16 val = 0;
91c86df5 1054
e07b1aa8 1055 spin_lock_bh(&sky2->phy_lock);
ef743d33 1056 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1057 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1058
ef743d33
SH		 1059 data->val_out = val;
1060 break;
1061 }
1062
1063 case SIOCSMIIREG:
1064 if (!capable(CAP_NET_ADMIN))
1065 return -EPERM;
1066
e07b1aa8 1067 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1068 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1069 data->val_in);
e07b1aa8 1070 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1071 break;
1072 }
1073 return err;
1074}
1075
d1f13708
SH		 1076#ifdef SKY2_VLAN_TAG_USED
1077static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1078{
1079 struct sky2_port *sky2 = netdev_priv(dev);
1080 struct sky2_hw *hw = sky2->hw;
1081 u16 port = sky2->port;
d1f13708 1082
2bb8c262 1083 netif_tx_lock_bh(dev);
3d4e66f5 1084 netif_poll_disable(sky2->hw->dev[0]);
d1f13708 1085
d1f13708 1086 sky2->vlgrp = grp;
3d4e66f5
SH		 1087 if (grp) {
1088 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1089 RX_VLAN_STRIP_ON);
1090 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1091 TX_VLAN_TAG_ON);
1092 } else {
1093 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1094 RX_VLAN_STRIP_OFF);
1095 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1096 TX_VLAN_TAG_OFF);
1097 }
d1f13708 1098
3d4e66f5 1099 netif_poll_enable(sky2->hw->dev[0]);
2bb8c262 1100 netif_tx_unlock_bh(dev);
d1f13708
SH		 1101}
1102#endif
1103
82788c7a 1104/*
14d0263f
SH		 1105 * Allocate an skb for receiving. If the MTU is large enough
1106 * make the skb non-linear with a fragment list of pages.
1107 *
82788c7a
SH		 1108 * It appears the hardware has a bug in the FIFO logic that
1109 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1110 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1111 * aligned except if slab debugging is enabled.
82788c7a 1112 */
14d0263f 1113static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1114{
1115 struct sk_buff *skb;
14d0263f
SH		 1116 unsigned long p;
1117 int i;
82788c7a 1118
14d0263f
SH		 1119 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1120 if (!skb)
1121 goto nomem;
1122
1123 p = (unsigned long) skb->data;
1124 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1125
1126 for (i = 0; i < sky2->rx_nfrags; i++) {
1127 struct page *page = alloc_page(GFP_ATOMIC);
1128
1129 if (!page)
1130 goto free_partial;
1131 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1132 }
1133
1134 return skb;
14d0263f
SH		 1135free_partial:
1136 kfree_skb(skb);
1137nomem:
1138 return NULL;
82788c7a
SH		 1139}
1140
cd28ab6a
SH		 1141/*
1142 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1143 * Normal case this ends up creating one list element for skb
1144 * in the receive ring. Worst case if using large MTU and each
1145 * allocation falls on a different 64 bit region, that results
1146 * in 6 list elements per ring entry.
1147 * One element is used for checksum enable/disable, and one
1148 * extra to avoid wrap.
cd28ab6a 1149 */
6b1a3aef 1150static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1151{
6b1a3aef 1152 struct sky2_hw *hw = sky2->hw;
14d0263f 1153 struct rx_ring_info *re;
6b1a3aef 1154 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1155 unsigned i, size, space, thresh;
cd28ab6a 1156
6b1a3aef 1157 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1158 sky2_qset(hw, rxq);
977bdf06 1159
c3905bc4
SH		 1160 /* On PCI express lowering the watermark gives better performance */
1161 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1162 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1163
1164 /* These chips have no ram buffer?
1165 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1166 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1167 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1168 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1169 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1170
6b1a3aef
SH		 1171 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1172
1173 rx_set_checksum(sky2);
14d0263f
SH		 1174
1175 /* Space needed for frame data + headers rounded up */
1176 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1177 + 8;
1178
1179 /* Stopping point for hardware truncation */
1180 thresh = (size - 8) / sizeof(u32);
1181
1182 /* Account for overhead of skb - to avoid order > 0 allocation */
1183 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1184 + sizeof(struct skb_shared_info);
1185
1186 sky2->rx_nfrags = space >> PAGE_SHIFT;
1187 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1188
1189 if (sky2->rx_nfrags != 0) {
1190 /* Compute residue after pages */
1191 space = sky2->rx_nfrags << PAGE_SHIFT;
1192
1193 if (space < size)
1194 size -= space;
1195 else
1196 size = 0;
1197
1198 /* Optimize to handle small packets and headers */
1199 if (size < copybreak)
1200 size = copybreak;
1201 if (size < ETH_HLEN)
1202 size = ETH_HLEN;
1203 }
1204 sky2->rx_data_size = size;
1205
1206 /* Fill Rx ring */
793b883e 1207 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1208 re = sky2->rx_ring + i;
cd28ab6a 1209
14d0263f 1210 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1211 if (!re->skb)
1212 goto nomem;
1213
14d0263f
SH		 1214 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1215 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1216 }
1217
a1433ac4
SH		 1218 /*
1219 * The receiver hangs if it receives frames larger than the
1220 * packet buffer. As a workaround, truncate oversize frames, but
1221 * the register is limited to 9 bits, so if you do frames > 2052
1222 * you better get the MTU right!
1223 */
a1433ac4
SH		 1224 if (thresh > 0x1ff)
1225 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1226 else {
1227 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1228 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1229 }
1230
6b1a3aef 1231 /* Tell chip about available buffers */
50432cb5 1232 sky2_put_idx(hw, rxq, sky2->rx_put);
cd28ab6a
SH		 1233 return 0;
1234nomem:
1235 sky2_rx_clean(sky2);
1236 return -ENOMEM;
1237}
1238
1239/* Bring up network interface. */
1240static int sky2_up(struct net_device *dev)
1241{
1242 struct sky2_port *sky2 = netdev_priv(dev);
1243 struct sky2_hw *hw = sky2->hw;
1244 unsigned port = sky2->port;
67712901 1245 u32 ramsize, imask;
ee7abb04 1246 int cap, err = -ENOMEM;
843a46f4 1247 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1248
ee7abb04
SH		 1249 /*
1250 * On dual port PCI-X card, there is an problem where status
1251 * can be received out of order due to split transactions
843a46f4 1252 */
ee7abb04
SH		 1253 if (otherdev && netif_running(otherdev) &&
1254 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1255 struct sky2_port *osky2 = netdev_priv(otherdev);
1256 u16 cmd;
1257
1258 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1259 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1260 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1261
1262 sky2->rx_csum = 0;
1263 osky2->rx_csum = 0;
1264 }
843a46f4 1265
cd28ab6a
SH		 1266 if (netif_msg_ifup(sky2))
1267 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1268
55d7b4e6
SH		 1269 netif_carrier_off(dev);
1270
cd28ab6a
SH		 1271 /* must be power of 2 */
1272 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1273 TX_RING_SIZE *
1274 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1275 &sky2->tx_le_map);
1276 if (!sky2->tx_le)
1277 goto err_out;
1278
6cdbbdf3 1279 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1280 GFP_KERNEL);
1281 if (!sky2->tx_ring)
1282 goto err_out;
1283 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1284
1285 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1286 &sky2->rx_le_map);
1287 if (!sky2->rx_le)
1288 goto err_out;
1289 memset(sky2->rx_le, 0, RX_LE_BYTES);
1290
291ea614 1291 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1292 GFP_KERNEL);
1293 if (!sky2->rx_ring)
1294 goto err_out;
1295
d3bcfbeb
SH		 1296 sky2_phy_power(hw, port, 1);
1297
cd28ab6a
SH		 1298 sky2_mac_init(hw, port);
1299
67712901
SH		 1300 /* Register is number of 4K blocks on internal RAM buffer. */
1301 ramsize = sky2_read8(hw, B2_E_0) * 4;
1302 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1303
67712901
SH		 1304 if (ramsize > 0) {
1305 u32 rxspace;
cd28ab6a 1306
67712901
SH		 1307 if (ramsize < 16)
1308 rxspace = ramsize / 2;
1309 else
1310 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1311
67712901
SH		 1312 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1313 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1314
1315 /* Make sure SyncQ is disabled */
1316 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1317 RB_RST_SET);
1318 }
793b883e 1319
af4ed7e6 1320 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1321
69161611
SH		 1322 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1323 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1324 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1325
977bdf06 1326 /* Set almost empty threshold */
c2716fb4
SH		 1327 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1328 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1329 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1330
6b1a3aef
SH		 1331 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1332 TX_RING_SIZE - 1);
cd28ab6a 1333
6b1a3aef 1334 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1335 if (err)
1336 goto err_out;
1337
cd28ab6a 1338 /* Enable interrupts from phy/mac for port */
e07b1aa8 1339 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1340 imask |= portirq_msk[port];
e07b1aa8
SH		 1341 sky2_write32(hw, B0_IMSK, imask);
1342
cd28ab6a
SH		 1343 return 0;
1344
1345err_out:
1b537565 1346 if (sky2->rx_le) {
cd28ab6a
SH		 1347 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1348 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1349 sky2->rx_le = NULL;
1350 }
1351 if (sky2->tx_le) {
cd28ab6a
SH		 1352 pci_free_consistent(hw->pdev,
1353 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1354 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1355 sky2->tx_le = NULL;
1356 }
1357 kfree(sky2->tx_ring);
1358 kfree(sky2->rx_ring);
cd28ab6a 1359
1b537565
SH		 1360 sky2->tx_ring = NULL;
1361 sky2->rx_ring = NULL;
cd28ab6a
SH		 1362 return err;
1363}
1364
793b883e
SH		 1365/* Modular subtraction in ring */
1366static inline int tx_dist(unsigned tail, unsigned head)
1367{
cb5d9547 1368 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1369}
cd28ab6a 1370
793b883e
SH		 1371/* Number of list elements available for next tx */
1372static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1373{
793b883e 1374 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1375}
1376
793b883e 1377/* Estimate of number of transmit list elements required */
28bd181a 1378static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1379{
793b883e
SH		 1380 unsigned count;
1381
1382 count = sizeof(dma_addr_t) / sizeof(u32);
1383 count += skb_shinfo(skb)->nr_frags * count;
1384
89114afd 1385 if (skb_is_gso(skb))
793b883e
SH		 1386 ++count;
1387
84fa7933 1388 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1389 ++count;
1390
1391 return count;
cd28ab6a
SH		 1392}
1393
793b883e
SH		 1394/*
1395 * Put one packet in ring for transmit.
1396 * A single packet can generate multiple list elements, and
1397 * the number of ring elements will probably be less than the number
1398 * of list elements used.
1399 */
cd28ab6a
SH		 1400static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1401{
1402 struct sky2_port *sky2 = netdev_priv(dev);
1403 struct sky2_hw *hw = sky2->hw;
d1f13708 1404 struct sky2_tx_le *le = NULL;
6cdbbdf3 1405 struct tx_ring_info *re;
cd28ab6a
SH		 1406 unsigned i, len;
1407 dma_addr_t mapping;
1408 u32 addr64;
1409 u16 mss;
1410 u8 ctrl;
1411
2bb8c262
SH		 1412 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1413 return NETDEV_TX_BUSY;
cd28ab6a 1414
793b883e 1415 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1416 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1417 dev->name, sky2->tx_prod, skb->len);
1418
cd28ab6a
SH		 1419 len = skb_headlen(skb);
1420 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1421 addr64 = high32(mapping);
793b883e 1422
a018e330
SH		 1423 /* Send high bits if changed or crosses boundary */
1424 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1425 le = get_tx_le(sky2);
f65b138c 1426 le->addr = cpu_to_le32(addr64);
793b883e 1427 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1428 sky2->tx_addr64 = high32(mapping + len);
793b883e 1429 }
cd28ab6a
SH		 1430
1431 /* Check for TCP Segmentation Offload */
7967168c 1432 mss = skb_shinfo(skb)->gso_size;
793b883e 1433 if (mss != 0) {
69161611
SH		 1434 if (hw->chip_id != CHIP_ID_YUKON_EX)
1435 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1436
1437 if (mss != sky2->tx_last_mss) {
1438 le = get_tx_le(sky2);
1439 le->addr = cpu_to_le32(mss);
1440 if (hw->chip_id == CHIP_ID_YUKON_EX)
1441 le->opcode = OP_MSS | HW_OWNER;
1442 else
1443 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1444 sky2->tx_last_mss = mss;
1445 }
cd28ab6a
SH		 1446 }
1447
cd28ab6a 1448 ctrl = 0;
d1f13708
SH		 1449#ifdef SKY2_VLAN_TAG_USED
1450 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1451 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1452 if (!le) {
1453 le = get_tx_le(sky2);
f65b138c 1454 le->addr = 0;
d1f13708 1455 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1456 } else
1457 le->opcode |= OP_VLAN;
1458 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1459 ctrl |= INS_VLAN;
1460 }
1461#endif
1462
1463 /* Handle TCP checksum offload */
84fa7933 1464 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611
SH		 1465 /* On Yukon EX (some versions) encoding change. */
1466 if (hw->chip_id == CHIP_ID_YUKON_EX
1467 && hw->chip_rev != CHIP_REV_YU_EX_B0)
1468 ctrl |= CALSUM; /* auto checksum */
1469 else {
1470 const unsigned offset = skb_transport_offset(skb);
1471 u32 tcpsum;
1472
1473 tcpsum = offset << 16; /* sum start */
1474 tcpsum |= offset + skb->csum_offset; /* sum write */
1475
1476 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1477 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1478 ctrl |= UDPTCP;
1479
1480 if (tcpsum != sky2->tx_tcpsum) {
1481 sky2->tx_tcpsum = tcpsum;
1482
1483 le = get_tx_le(sky2);
1484 le->addr = cpu_to_le32(tcpsum);
1485 le->length = 0; /* initial checksum value */
1486 le->ctrl = 1; /* one packet */
1487 le->opcode = OP_TCPLISW | HW_OWNER;
1488 }
1d179332 1489 }
cd28ab6a
SH		 1490 }
1491
1492 le = get_tx_le(sky2);
f65b138c 1493 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1494 le->length = cpu_to_le16(len);
1495 le->ctrl = ctrl;
793b883e 1496 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1497
291ea614 1498 re = tx_le_re(sky2, le);
cd28ab6a 1499 re->skb = skb;
6cdbbdf3 1500 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1501 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1502
1503 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1504 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1505
1506 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1507 frag->size, PCI_DMA_TODEVICE);
a036119f 1508 addr64 = high32(mapping);
793b883e
SH		 1509 if (addr64 != sky2->tx_addr64) {
1510 le = get_tx_le(sky2);
f65b138c 1511 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1512 le->ctrl = 0;
1513 le->opcode = OP_ADDR64 | HW_OWNER;
1514 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1515 }
1516
1517 le = get_tx_le(sky2);
f65b138c 1518 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1519 le->length = cpu_to_le16(frag->size);
1520 le->ctrl = ctrl;
793b883e 1521 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1522
291ea614
SH		 1523 re = tx_le_re(sky2, le);
1524 re->skb = skb;
1525 pci_unmap_addr_set(re, mapaddr, mapping);
1526 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1527 }
6cdbbdf3 1528
cd28ab6a
SH		 1529 le->ctrl |= EOP;
1530
97bda706
SH		 1531 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1532 netif_stop_queue(dev);
b19666d9 1533
290d4de5 1534 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1535
cd28ab6a
SH		 1536 dev->trans_start = jiffies;
1537 return NETDEV_TX_OK;
1538}
1539
cd28ab6a 1540/*
793b883e
SH		 1541 * Free ring elements from starting at tx_cons until "done"
1542 *
1543 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1544 * buffers so make sure not to free skb to early.
cd28ab6a 1545 */
d11c13e7 1546static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1547{
d11c13e7 1548 struct net_device *dev = sky2->netdev;
af2a58ac 1549 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1550 unsigned idx;
cd28ab6a 1551
0e3ff6aa 1552 BUG_ON(done >= TX_RING_SIZE);
2224795d 1553
291ea614
SH		 1554 for (idx = sky2->tx_cons; idx != done;
1555 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1556 struct sky2_tx_le *le = sky2->tx_le + idx;
1557 struct tx_ring_info *re = sky2->tx_ring + idx;
1558
1559 switch(le->opcode & ~HW_OWNER) {
1560 case OP_LARGESEND:
1561 case OP_PACKET:
1562 pci_unmap_single(pdev,
1563 pci_unmap_addr(re, mapaddr),
1564 pci_unmap_len(re, maplen),
1565 PCI_DMA_TODEVICE);
af2a58ac 1566 break;
291ea614
SH		 1567 case OP_BUFFER:
1568 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1569 pci_unmap_len(re, maplen),
734d1868 1570 PCI_DMA_TODEVICE);
291ea614
SH		 1571 break;
1572 }
1573
1574 if (le->ctrl & EOP) {
1575 if (unlikely(netif_msg_tx_done(sky2)))
1576 printk(KERN_DEBUG "%s: tx done %u\n",
1577 dev->name, idx);
3cf26753 1578
2bf56fe2 1579 sky2->net_stats.tx_packets++;
1580 sky2->net_stats.tx_bytes += re->skb->len;
1581
794b2bd2 1582 dev_kfree_skb_any(re->skb);
3cf26753 1583 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1584 }
793b883e 1585 }
793b883e 1586
291ea614 1587 sky2->tx_cons = idx;
50432cb5
SH		 1588 smp_mb();
1589
22e11703 1590 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1591 netif_wake_queue(dev);
cd28ab6a
SH		 1592}
1593
1594/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1595static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1596{
2bb8c262
SH		 1597 struct sky2_port *sky2 = netdev_priv(dev);
1598
1599 netif_tx_lock_bh(dev);
d11c13e7 1600 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1601 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1602}
1603
1604/* Network shutdown */
1605static int sky2_down(struct net_device *dev)
1606{
1607 struct sky2_port *sky2 = netdev_priv(dev);
1608 struct sky2_hw *hw = sky2->hw;
1609 unsigned port = sky2->port;
1610 u16 ctrl;
e07b1aa8 1611 u32 imask;
cd28ab6a 1612
1b537565
SH		 1613 /* Never really got started! */
1614 if (!sky2->tx_le)
1615 return 0;
1616
cd28ab6a
SH		 1617 if (netif_msg_ifdown(sky2))
1618 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1619
018d1c66 1620 /* Stop more packets from being queued */
cd28ab6a
SH		 1621 netif_stop_queue(dev);
1622
ebc646f6
SH		 1623 /* Disable port IRQ */
1624 imask = sky2_read32(hw, B0_IMSK);
1625 imask &= ~portirq_msk[port];
1626 sky2_write32(hw, B0_IMSK, imask);
1627
d3bcfbeb 1628 sky2_gmac_reset(hw, port);
793b883e 1629
cd28ab6a
SH		 1630 /* Stop transmitter */
1631 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1632 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1633
1634 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1635 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1636
1637 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1638 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1639 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1640
1641 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1642
1643 /* Workaround shared GMAC reset */
793b883e
SH		 1644 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1645 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1646 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1647
1648 /* Disable Force Sync bit and Enable Alloc bit */
1649 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1650 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1651
1652 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1653 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1654 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1655
1656 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1657 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1658 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1659
1660 /* Reset the Tx prefetch units */
1661 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1662 PREF_UNIT_RST_SET);
1663
1664 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1665
6b1a3aef 1666 sky2_rx_stop(sky2);
cd28ab6a
SH		 1667
1668 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1669 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1670
d3bcfbeb
SH		 1671 sky2_phy_power(hw, port, 0);
1672
55d7b4e6
SH		 1673 netif_carrier_off(dev);
1674
d571b694 1675 /* turn off LED's */
cd28ab6a
SH		 1676 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1677
018d1c66
SH		 1678 synchronize_irq(hw->pdev->irq);
1679
2bb8c262 1680 sky2_tx_clean(dev);
cd28ab6a
SH		 1681 sky2_rx_clean(sky2);
1682
1683 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1684 sky2->rx_le, sky2->rx_le_map);
1685 kfree(sky2->rx_ring);
1686
1687 pci_free_consistent(hw->pdev,
1688 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1689 sky2->tx_le, sky2->tx_le_map);
1690 kfree(sky2->tx_ring);
1691
1b537565
SH		 1692 sky2->tx_le = NULL;
1693 sky2->rx_le = NULL;
1694
1695 sky2->rx_ring = NULL;
1696 sky2->tx_ring = NULL;
1697
cd28ab6a
SH		 1698 return 0;
1699}
1700
1701static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1702{
b89165f2 1703 if (!sky2_is_copper(hw))
793b883e
SH		 1704 return SPEED_1000;
1705
cd28ab6a
SH		 1706 if (hw->chip_id == CHIP_ID_YUKON_FE)
1707 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1708
1709 switch (aux & PHY_M_PS_SPEED_MSK) {
1710 case PHY_M_PS_SPEED_1000:
1711 return SPEED_1000;
1712 case PHY_M_PS_SPEED_100:
1713 return SPEED_100;
1714 default:
1715 return SPEED_10;
1716 }
1717}
1718
1719static void sky2_link_up(struct sky2_port *sky2)
1720{
1721 struct sky2_hw *hw = sky2->hw;
1722 unsigned port = sky2->port;
1723 u16 reg;
16ad91e1
SH		 1724 static const char *fc_name[] = {
1725 [FC_NONE] = "none",
1726 [FC_TX] = "tx",
1727 [FC_RX] = "rx",
1728 [FC_BOTH] = "both",
1729 };
cd28ab6a 1730
cd28ab6a 1731 /* enable Rx/Tx */
2eaba1a2 1732 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1733 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1734 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1735
1736 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1737
1738 netif_carrier_on(sky2->netdev);
cd28ab6a
SH		 1739
1740 /* Turn on link LED */
793b883e 1741 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1742 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1743
93745494
SH		 1744 if (hw->chip_id == CHIP_ID_YUKON_XL
1745 || hw->chip_id == CHIP_ID_YUKON_EC_U
1746 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1747 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1748 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1749
1750 switch(sky2->speed) {
1751 case SPEED_10:
1752 led |= PHY_M_LEDC_INIT_CTRL(7);
1753 break;
1754
1755 case SPEED_100:
1756 led |= PHY_M_LEDC_STA1_CTRL(7);
1757 break;
1758
1759 case SPEED_1000:
1760 led |= PHY_M_LEDC_STA0_CTRL(7);
1761 break;
1762 }
793b883e
SH		 1763
1764 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1765 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1766 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1767 }
1768
cd28ab6a
SH		 1769 if (netif_msg_link(sky2))
1770 printk(KERN_INFO PFX
d571b694 1771 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1772 sky2->netdev->name, sky2->speed,
1773 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1774 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1775}
1776
1777static void sky2_link_down(struct sky2_port *sky2)
1778{
1779 struct sky2_hw *hw = sky2->hw;
1780 unsigned port = sky2->port;
1781 u16 reg;
1782
1783 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1784
1785 reg = gma_read16(hw, port, GM_GP_CTRL);
1786 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1787 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1788
cd28ab6a 1789 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1790
1791 /* Turn on link LED */
1792 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1793
1794 if (netif_msg_link(sky2))
1795 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1796
cd28ab6a
SH		 1797 sky2_phy_init(hw, port);
1798}
1799
16ad91e1
SH		 1800static enum flow_control sky2_flow(int rx, int tx)
1801{
1802 if (rx)
1803 return tx ? FC_BOTH : FC_RX;
1804 else
1805 return tx ? FC_TX : FC_NONE;
1806}
1807
793b883e
SH		 1808static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1809{
1810 struct sky2_hw *hw = sky2->hw;
1811 unsigned port = sky2->port;
da4c1ff4 1812 u16 advert, lpa;
793b883e 1813
da4c1ff4 1814 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1815 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1816 if (lpa & PHY_M_AN_RF) {
1817 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1818 return -1;
1819 }
1820
793b883e
SH		 1821 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1822 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1823 sky2->netdev->name);
1824 return -1;
1825 }
1826
793b883e 1827 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1828 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1829
da4c1ff4
SH		 1830 /* Since the pause result bits seem to in different positions on
1831 * different chips. look at registers.
1832 */
1833 if (!sky2_is_copper(hw)) {
1834 /* Shift for bits in fiber PHY */
1835 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1836 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1837
1838 if (advert & ADVERTISE_1000XPAUSE)
1839 advert |= ADVERTISE_PAUSE_CAP;
1840 if (advert & ADVERTISE_1000XPSE_ASYM)
1841 advert |= ADVERTISE_PAUSE_ASYM;
1842 if (lpa & LPA_1000XPAUSE)
1843 lpa |= LPA_PAUSE_CAP;
1844 if (lpa & LPA_1000XPAUSE_ASYM)
1845 lpa |= LPA_PAUSE_ASYM;
1846 }
793b883e 1847
da4c1ff4
SH		 1848 sky2->flow_status = FC_NONE;
1849 if (advert & ADVERTISE_PAUSE_CAP) {
1850 if (lpa & LPA_PAUSE_CAP)
1851 sky2->flow_status = FC_BOTH;
1852 else if (advert & ADVERTISE_PAUSE_ASYM)
1853 sky2->flow_status = FC_RX;
1854 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1855 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1856 sky2->flow_status = FC_TX;
1857 }
793b883e 1858
16ad91e1 1859 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1860 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1861 sky2->flow_status = FC_NONE;
2eaba1a2 1862
da4c1ff4 1863 if (sky2->flow_status & FC_TX)
793b883e
SH		 1864 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1865 else
1866 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1867
1868 return 0;
1869}
cd28ab6a 1870
e07b1aa8
SH		 1871/* Interrupt from PHY */
1872static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1873{
e07b1aa8
SH		 1874 struct net_device *dev = hw->dev[port];
1875 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1876 u16 istatus, phystat;
1877
ebc646f6
SH		 1878 if (!netif_running(dev))
1879 return;
1880
e07b1aa8
SH		 1881 spin_lock(&sky2->phy_lock);
1882 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1883 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1884
cd28ab6a
SH		 1885 if (netif_msg_intr(sky2))
1886 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1887 sky2->netdev->name, istatus, phystat);
1888
2eaba1a2 1889 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1890 if (sky2_autoneg_done(sky2, phystat) == 0)
1891 sky2_link_up(sky2);
1892 goto out;
1893 }
cd28ab6a 1894
793b883e
SH		 1895 if (istatus & PHY_M_IS_LSP_CHANGE)
1896 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1897
793b883e
SH		 1898 if (istatus & PHY_M_IS_DUP_CHANGE)
1899 sky2->duplex =
1900 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1901
793b883e
SH		 1902 if (istatus & PHY_M_IS_LST_CHANGE) {
1903 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1904 sky2_link_up(sky2);
793b883e
SH		 1905 else
1906 sky2_link_down(sky2);
cd28ab6a 1907 }
793b883e 1908out:
e07b1aa8 1909 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1910}
1911
62335ab0 1912/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1913 * and tx queue is full (stopped).
1914 */
cd28ab6a
SH		 1915static void sky2_tx_timeout(struct net_device *dev)
1916{
1917 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1918 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1919
1920 if (netif_msg_timer(sky2))
1921 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1922
8f24664d 1923 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1924 dev->name, sky2->tx_cons, sky2->tx_prod,
1925 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1926 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1927
81906791
SH		 1928 /* can't restart safely under softirq */
1929 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1930}
1931
1932static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1933{
6b1a3aef
SH		 1934 struct sky2_port *sky2 = netdev_priv(dev);
1935 struct sky2_hw *hw = sky2->hw;
b628ed98 1936 unsigned port = sky2->port;
6b1a3aef
SH		 1937 int err;
1938 u16 ctl, mode;
e07b1aa8 1939 u32 imask;
cd28ab6a
SH		 1940
1941 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1942 return -EINVAL;
1943
d2adf4f6
SH		 1944 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1945 return -EINVAL;
1946
6b1a3aef
SH		 1947 if (!netif_running(dev)) {
1948 dev->mtu = new_mtu;
1949 return 0;
1950 }
1951
e07b1aa8 1952 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1953 sky2_write32(hw, B0_IMSK, 0);
1954
018d1c66
SH		 1955 dev->trans_start = jiffies; /* prevent tx timeout */
1956 netif_stop_queue(dev);
1957 netif_poll_disable(hw->dev[0]);
1958
e07b1aa8
SH		 1959 synchronize_irq(hw->pdev->irq);
1960
69161611
SH		 1961 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
1962 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 1963
1964 ctl = gma_read16(hw, port, GM_GP_CTRL);
1965 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 1966 sky2_rx_stop(sky2);
1967 sky2_rx_clean(sky2);
cd28ab6a
SH		 1968
1969 dev->mtu = new_mtu;
14d0263f 1970
6b1a3aef
SH		 1971 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1972 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1973
1974 if (dev->mtu > ETH_DATA_LEN)
1975 mode |= GM_SMOD_JUMBO_ENA;
1976
b628ed98 1977 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 1978
b628ed98 1979 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1980
6b1a3aef 1981 err = sky2_rx_start(sky2);
e07b1aa8 1982 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1983
1b537565
SH		 1984 if (err)
1985 dev_close(dev);
1986 else {
b628ed98 1987 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565
SH		 1988
1989 netif_poll_enable(hw->dev[0]);
1990 netif_wake_queue(dev);
1991 }
1992
cd28ab6a
SH		 1993 return err;
1994}
1995
14d0263f
SH		 1996/* For small just reuse existing skb for next receive */
1997static struct sk_buff *receive_copy(struct sky2_port *sky2,
1998 const struct rx_ring_info *re,
1999 unsigned length)
2000{
2001 struct sk_buff *skb;
2002
2003 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2004 if (likely(skb)) {
2005 skb_reserve(skb, 2);
2006 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2007 length, PCI_DMA_FROMDEVICE);
d626f62b 2008 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2009 skb->ip_summed = re->skb->ip_summed;
2010 skb->csum = re->skb->csum;
2011 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2012 length, PCI_DMA_FROMDEVICE);
2013 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2014 skb_put(skb, length);
14d0263f
SH		 2015 }
2016 return skb;
2017}
2018
2019/* Adjust length of skb with fragments to match received data */
2020static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2021 unsigned int length)
2022{
2023 int i, num_frags;
2024 unsigned int size;
2025
2026 /* put header into skb */
2027 size = min(length, hdr_space);
2028 skb->tail += size;
2029 skb->len += size;
2030 length -= size;
2031
2032 num_frags = skb_shinfo(skb)->nr_frags;
2033 for (i = 0; i < num_frags; i++) {
2034 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2035
2036 if (length == 0) {
2037 /* don't need this page */
2038 __free_page(frag->page);
2039 --skb_shinfo(skb)->nr_frags;
2040 } else {
2041 size = min(length, (unsigned) PAGE_SIZE);
2042
2043 frag->size = size;
2044 skb->data_len += size;
2045 skb->truesize += size;
2046 skb->len += size;
2047 length -= size;
2048 }
2049 }
2050}
2051
2052/* Normal packet - take skb from ring element and put in a new one */
2053static struct sk_buff *receive_new(struct sky2_port *sky2,
2054 struct rx_ring_info *re,
2055 unsigned int length)
2056{
2057 struct sk_buff *skb, *nskb;
2058 unsigned hdr_space = sky2->rx_data_size;
2059
2060 pr_debug(PFX "receive new length=%d\n", length);
2061
2062 /* Don't be tricky about reusing pages (yet) */
2063 nskb = sky2_rx_alloc(sky2);
2064 if (unlikely(!nskb))
2065 return NULL;
2066
2067 skb = re->skb;
2068 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2069
2070 prefetch(skb->data);
2071 re->skb = nskb;
2072 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2073
2074 if (skb_shinfo(skb)->nr_frags)
2075 skb_put_frags(skb, hdr_space, length);
2076 else
489b10c1 2077 skb_put(skb, length);
14d0263f
SH		 2078 return skb;
2079}
2080
cd28ab6a
SH		 2081/*
2082 * Receive one packet.
d571b694 2083 * For larger packets, get new buffer.
cd28ab6a 2084 */
497d7c86 2085static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2086 u16 length, u32 status)
2087{
497d7c86 2088 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2089 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2090 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2091
2092 if (unlikely(netif_msg_rx_status(sky2)))
2093 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2094 dev->name, sky2->rx_next, status, length);
cd28ab6a 2095
793b883e 2096 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2097 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2098
42eeea01 2099 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2100 goto error;
2101
42eeea01
SH		 2102 if (!(status & GMR_FS_RX_OK))
2103 goto resubmit;
2104
14d0263f
SH		 2105 if (length < copybreak)
2106 skb = receive_copy(sky2, re, length);
2107 else
2108 skb = receive_new(sky2, re, length);
793b883e 2109resubmit:
14d0263f 2110 sky2_rx_submit(sky2, re);
79e57d32 2111
cd28ab6a
SH		 2112 return skb;
2113
2114error:
6e15b712 2115 ++sky2->net_stats.rx_errors;
b6d77734 2116 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2117 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2118 goto resubmit;
2119 }
6e15b712 2120
3be92a70 2121 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2122 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2123 dev->name, status, length);
793b883e
SH		 2124
2125 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2126 sky2->net_stats.rx_length_errors++;
2127 if (status & GMR_FS_FRAGMENT)
2128 sky2->net_stats.rx_frame_errors++;
2129 if (status & GMR_FS_CRC_ERR)
2130 sky2->net_stats.rx_crc_errors++;
79e57d32 2131
793b883e 2132 goto resubmit;
cd28ab6a
SH		 2133}
2134
e07b1aa8
SH		 2135/* Transmit complete */
2136static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2137{
e07b1aa8 2138 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2139
e07b1aa8 2140 if (netif_running(dev)) {
2bb8c262 2141 netif_tx_lock(dev);
e07b1aa8 2142 sky2_tx_complete(sky2, last);
2bb8c262 2143 netif_tx_unlock(dev);
2224795d 2144 }
cd28ab6a
SH		 2145}
2146
e07b1aa8
SH		 2147/* Process status response ring */
2148static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2149{
22e11703 2150 struct sky2_port *sky2;
e07b1aa8 2151 int work_done = 0;
22e11703 2152 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2153 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2154
af2a58ac 2155 rmb();
bea86103 2156
e71ebd73 2157 while (hw->st_idx != hwidx) {
13210ce5 2158 struct sky2_status_le *le = hw->st_le + hw->st_idx;
69161611 2159 unsigned port = le->css & CSS_LINK_BIT;
13210ce5 2160 struct net_device *dev;
cd28ab6a 2161 struct sk_buff *skb;
cd28ab6a
SH		 2162 u32 status;
2163 u16 length;
2164
cb5d9547 2165 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2166
69161611 2167 dev = hw->dev[port];
13210ce5 2168 sky2 = netdev_priv(dev);
f65b138c
SH		 2169 length = le16_to_cpu(le->length);
2170 status = le32_to_cpu(le->status);
cd28ab6a 2171
e71ebd73 2172 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2173 case OP_RXSTAT:
497d7c86 2174 skb = sky2_receive(dev, length, status);
3225b919
SH		 2175 if (unlikely(!skb)) {
2176 sky2->net_stats.rx_dropped++;
5df79111 2177 goto force_update;
3225b919 2178 }
13210ce5 2179
69161611
SH		 2180 /* This chip reports checksum status differently */
2181 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2182 if (sky2->rx_csum &&
2183 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2184 (le->css & CSS_TCPUDPCSOK))
2185 skb->ip_summed = CHECKSUM_UNNECESSARY;
2186 else
2187 skb->ip_summed = CHECKSUM_NONE;
2188 }
2189
13210ce5 2190 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2191 sky2->net_stats.rx_packets++;
2192 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2193 dev->last_rx = jiffies;
2194
d1f13708
SH		 2195#ifdef SKY2_VLAN_TAG_USED
2196 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2197 vlan_hwaccel_receive_skb(skb,
2198 sky2->vlgrp,
2199 be16_to_cpu(sky2->rx_tag));
2200 } else
2201#endif
cd28ab6a 2202 netif_receive_skb(skb);
13210ce5 2203
22e11703 2204 /* Update receiver after 16 frames */
69161611 2205 if (++buf_write[port] == RX_BUF_WRITE) {
5df79111 2206force_update:
69161611
SH		 2207 sky2_put_idx(hw, rxqaddr[port], sky2->rx_put);
2208 buf_write[port] = 0;
22e11703
SH		 2209 }
2210
2211 /* Stop after net poll weight */
13210ce5
SH		 2212 if (++work_done >= to_do)
2213 goto exit_loop;
cd28ab6a
SH		 2214 break;
2215
d1f13708
SH		 2216#ifdef SKY2_VLAN_TAG_USED
2217 case OP_RXVLAN:
2218 sky2->rx_tag = length;
2219 break;
2220
2221 case OP_RXCHKSVLAN:
2222 sky2->rx_tag = length;
2223 /* fall through */
2224#endif
cd28ab6a 2225 case OP_RXCHKS:
87418307
SH		 2226 if (!sky2->rx_csum)
2227 break;
2228
69161611
SH		 2229 if (hw->chip_id == CHIP_ID_YUKON_EX)
2230 break;
2231
87418307
SH		 2232 /* Both checksum counters are programmed to start at
2233 * the same offset, so unless there is a problem they
2234 * should match. This failure is an early indication that
2235 * hardware receive checksumming won't work.
2236 */
2237 if (likely(status >> 16 == (status & 0xffff))) {
2238 skb = sky2->rx_ring[sky2->rx_next].skb;
2239 skb->ip_summed = CHECKSUM_COMPLETE;
2240 skb->csum = status & 0xffff;
2241 } else {
2242 printk(KERN_NOTICE PFX "%s: hardware receive "
2243 "checksum problem (status = %#x)\n",
2244 dev->name, status);
2245 sky2->rx_csum = 0;
2246 sky2_write32(sky2->hw,
69161611 2247 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2248 BMU_DIS_RX_CHKSUM);
2249 }
cd28ab6a
SH		 2250 break;
2251
2252 case OP_TXINDEXLE:
13b97b74 2253 /* TX index reports status for both ports */
f55925d7
SH		 2254 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2255 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2256 if (hw->dev[1])
2257 sky2_tx_done(hw->dev[1],
2258 ((status >> 24) & 0xff)
2259 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2260 break;
2261
cd28ab6a
SH		 2262 default:
2263 if (net_ratelimit())
793b883e 2264 printk(KERN_WARNING PFX
e71ebd73
SH		 2265 "unknown status opcode 0x%x\n", le->opcode);
2266 goto exit_loop;
cd28ab6a 2267 }
13210ce5 2268 }
cd28ab6a 2269
fe2a24df
SH		 2270 /* Fully processed status ring so clear irq */
2271 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
50432cb5 2272 mmiowb();
fe2a24df 2273
13210ce5 2274exit_loop:
22e11703
SH		 2275 if (buf_write[0]) {
2276 sky2 = netdev_priv(hw->dev[0]);
2277 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2278 }
2279
2280 if (buf_write[1]) {
2281 sky2 = netdev_priv(hw->dev[1]);
2282 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2283 }
2284
e07b1aa8 2285 return work_done;
cd28ab6a
SH		 2286}
2287
2288static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2289{
2290 struct net_device *dev = hw->dev[port];
2291
3be92a70
SH		 2292 if (net_ratelimit())
2293 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2294 dev->name, status);
cd28ab6a
SH		 2295
2296 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2297 if (net_ratelimit())
2298 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2299 dev->name);
cd28ab6a
SH		 2300 /* Clear IRQ */
2301 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2302 }
2303
2304 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2305 if (net_ratelimit())
2306 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2307 dev->name);
cd28ab6a
SH		 2308
2309 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2310 }
2311
2312 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2313 if (net_ratelimit())
2314 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2315 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2316 }
2317
2318 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2319 if (net_ratelimit())
2320 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2321 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2322 }
2323
2324 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2325 if (net_ratelimit())
2326 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2327 dev->name);
cd28ab6a
SH		 2328 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2329 }
2330}
2331
2332static void sky2_hw_intr(struct sky2_hw *hw)
2333{
2334 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2335
793b883e 2336 if (status & Y2_IS_TIST_OV)
cd28ab6a 2337 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2338
2339 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2340 u16 pci_err;
2341
56a645cc 2342 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2343 if (net_ratelimit())
b02a9258
SH		 2344 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2345 pci_err);
cd28ab6a
SH		 2346
2347 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2348 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2349 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2350 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2351 }
2352
2353 if (status & Y2_IS_PCI_EXP) {
d571b694 2354 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2355 u32 pex_err;
2356
7bd656d1 2357 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2358
3be92a70 2359 if (net_ratelimit())
b02a9258
SH		 2360 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2361 pex_err);
cd28ab6a
SH		 2362
2363 /* clear the interrupt */
2364 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2365 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2366 0xffffffffUL);
cd28ab6a
SH		 2367 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2368
7bd656d1 2369 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2370 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2371 hwmsk &= ~Y2_IS_PCI_EXP;
2372 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2373 }
2374 }
2375
2376 if (status & Y2_HWE_L1_MASK)
2377 sky2_hw_error(hw, 0, status);
2378 status >>= 8;
2379 if (status & Y2_HWE_L1_MASK)
2380 sky2_hw_error(hw, 1, status);
2381}
2382
2383static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2384{
2385 struct net_device *dev = hw->dev[port];
2386 struct sky2_port *sky2 = netdev_priv(dev);
2387 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2388
2389 if (netif_msg_intr(sky2))
2390 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2391 dev->name, status);
2392
a3caeada
SH		 2393 if (status & GM_IS_RX_CO_OV)
2394 gma_read16(hw, port, GM_RX_IRQ_SRC);
2395
2396 if (status & GM_IS_TX_CO_OV)
2397 gma_read16(hw, port, GM_TX_IRQ_SRC);
2398
cd28ab6a
SH		 2399 if (status & GM_IS_RX_FF_OR) {
2400 ++sky2->net_stats.rx_fifo_errors;
2401 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2402 }
2403
2404 if (status & GM_IS_TX_FF_UR) {
2405 ++sky2->net_stats.tx_fifo_errors;
2406 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2407 }
cd28ab6a
SH		 2408}
2409
40b01727
SH		 2410/* This should never happen it is a bug. */
2411static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2412 u16 q, unsigned ring_size)
d257924e
SH		 2413{
2414 struct net_device *dev = hw->dev[port];
2415 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2416 unsigned idx;
2417 const u64 *le = (q == Q_R1 || q == Q_R2)
2418 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2419
40b01727
SH		 2420 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2421 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2422 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2423 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2424
40b01727 2425 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2426}
cd28ab6a 2427
d27ed387
SH		 2428/* If idle then force a fake soft NAPI poll once a second
2429 * to work around cases where sharing an edge triggered interrupt.
2430 */
eb35cf60
SH		 2431static inline void sky2_idle_start(struct sky2_hw *hw)
2432{
2433 if (idle_timeout > 0)
2434 mod_timer(&hw->idle_timer,
2435 jiffies + msecs_to_jiffies(idle_timeout));
2436}
2437
d27ed387
SH		 2438static void sky2_idle(unsigned long arg)
2439{
01bd7564
SH		 2440 struct sky2_hw *hw = (struct sky2_hw *) arg;
2441 struct net_device *dev = hw->dev[0];
d27ed387 2442
d27ed387
SH		 2443 if (__netif_rx_schedule_prep(dev))
2444 __netif_rx_schedule(dev);
01bd7564
SH		 2445
2446 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2447}
2448
40b01727
SH		 2449/* Hardware/software error handling */
2450static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2451{
40b01727
SH		 2452 if (net_ratelimit())
2453 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2454
1e5f1283
SH		 2455 if (status & Y2_IS_HW_ERR)
2456 sky2_hw_intr(hw);
d257924e 2457
1e5f1283
SH		 2458 if (status & Y2_IS_IRQ_MAC1)
2459 sky2_mac_intr(hw, 0);
cd28ab6a 2460
1e5f1283
SH		 2461 if (status & Y2_IS_IRQ_MAC2)
2462 sky2_mac_intr(hw, 1);
cd28ab6a 2463
1e5f1283 2464 if (status & Y2_IS_CHK_RX1)
40b01727 2465 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2466
1e5f1283 2467 if (status & Y2_IS_CHK_RX2)
40b01727 2468 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2469
1e5f1283 2470 if (status & Y2_IS_CHK_TXA1)
40b01727 2471 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2472
1e5f1283 2473 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2474 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2475}
2476
2477static int sky2_poll(struct net_device *dev0, int *budget)
2478{
2479 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
5c11ce70 2480 int work_done;
40b01727
SH		 2481 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2482
2483 if (unlikely(status & Y2_IS_ERROR))
2484 sky2_err_intr(hw, status);
2485
2486 if (status & Y2_IS_IRQ_PHY1)
2487 sky2_phy_intr(hw, 0);
2488
2489 if (status & Y2_IS_IRQ_PHY2)
2490 sky2_phy_intr(hw, 1);
cd28ab6a 2491
5c11ce70
SH		 2492 work_done = sky2_status_intr(hw, min(dev0->quota, *budget));
2493 *budget -= work_done;
2494 dev0->quota -= work_done;
86fba634 2495
5c11ce70
SH		 2496 /* More work? */
2497 if (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX))
1e5f1283 2498 return 1;
5c11ce70
SH		 2499
2500 /* Bug/Errata workaround?
2501 * Need to kick the TX irq moderation timer.
2502 */
2503 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2504 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2505 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
fe2a24df 2506 }
5c11ce70
SH		 2507 netif_rx_complete(dev0);
2508
2509 sky2_read32(hw, B0_Y2_SP_LISR);
2510 return 0;
e07b1aa8
SH		 2511}
2512
7d12e780 2513static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2514{
2515 struct sky2_hw *hw = dev_id;
2516 struct net_device *dev0 = hw->dev[0];
2517 u32 status;
2518
2519 /* Reading this mask interrupts as side effect */
2520 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2521 if (status == 0 || status == ~0)
2522 return IRQ_NONE;
793b883e 2523
e07b1aa8
SH		 2524 prefetch(&hw->st_le[hw->st_idx]);
2525 if (likely(__netif_rx_schedule_prep(dev0)))
2526 __netif_rx_schedule(dev0);
793b883e 2527
cd28ab6a
SH		 2528 return IRQ_HANDLED;
2529}
2530
2531#ifdef CONFIG_NET_POLL_CONTROLLER
2532static void sky2_netpoll(struct net_device *dev)
2533{
2534 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2535 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2536
88d11360
SH		 2537 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2538 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2539}
2540#endif
2541
2542/* Chip internal frequency for clock calculations */
fb17358f 2543static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2544{
793b883e 2545 switch (hw->chip_id) {
cd28ab6a 2546 case CHIP_ID_YUKON_EC:
5a5b1ea0 2547 case CHIP_ID_YUKON_EC_U:
93745494 2548 case CHIP_ID_YUKON_EX:
fb17358f 2549 return 125; /* 125 Mhz */
cd28ab6a 2550 case CHIP_ID_YUKON_FE:
fb17358f 2551 return 100; /* 100 Mhz */
793b883e 2552 default: /* YUKON_XL */
fb17358f 2553 return 156; /* 156 Mhz */
cd28ab6a
SH		 2554 }
2555}
2556
fb17358f 2557static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2558{
fb17358f 2559 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2560}
2561
fb17358f 2562static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2563{
fb17358f 2564 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2565}
2566
fb17358f 2567
e3173832 2568static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2569{
b89165f2 2570 u8 t8;
cd28ab6a 2571
451af335
SH		 2572 /* Enable all clocks */
2573 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2574
cd28ab6a 2575 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2576
cd28ab6a
SH		 2577 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2578 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2579 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2580 hw->chip_id);
cd28ab6a
SH		 2581 return -EOPNOTSUPP;
2582 }
2583
290d4de5
SH		 2584 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2585
2586 /* This rev is really old, and requires untested workarounds */
2587 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2588 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2589 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2590 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2591 return -EOPNOTSUPP;
2592 }
2593
e3173832
SH		 2594 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2595 hw->ports = 1;
2596 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2597 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2598 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2599 ++hw->ports;
2600 }
2601
2602 return 0;
2603}
2604
2605static void sky2_reset(struct sky2_hw *hw)
2606{
2607 u16 status;
2608 int i;
2609
cd28ab6a 2610 /* disable ASF */
4f44d8ba
SH		 2611 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2612 status = sky2_read16(hw, HCU_CCSR);
2613 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2614 HCU_CCSR_UC_STATE_MSK);
2615 sky2_write16(hw, HCU_CCSR, status);
2616 } else
2617 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2618 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2619
2620 /* do a SW reset */
2621 sky2_write8(hw, B0_CTST, CS_RST_SET);
2622 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2623
2624 /* clear PCI errors, if any */
56a645cc 2625 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2626
cd28ab6a 2627 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2628 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2629
cd28ab6a
SH		 2630
2631 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2632
2633 /* clear any PEX errors */
7bd656d1
SH		 2634 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2635 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2636
cd28ab6a 2637
ae306cca 2638 sky2_power_on(hw);
cd28ab6a
SH		 2639
2640 for (i = 0; i < hw->ports; i++) {
2641 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2642 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611
SH		 2643
2644 if (hw->chip_id == CHIP_ID_YUKON_EX)
2645 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2646 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2647 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2648 }
2649
2650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2651
793b883e
SH		 2652 /* Clear I2C IRQ noise */
2653 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2654
2655 /* turn off hardware timer (unused) */
2656 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2657 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2658
cd28ab6a
SH		 2659 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2660
69634ee7
SH		 2661 /* Turn off descriptor polling */
2662 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2663
2664 /* Turn off receive timestamp */
2665 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2666 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2667
2668 /* enable the Tx Arbiters */
2669 for (i = 0; i < hw->ports; i++)
2670 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2671
2672 /* Initialize ram interface */
2673 for (i = 0; i < hw->ports; i++) {
793b883e 2674 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2675
2676 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2677 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2678 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2679 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2680 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2681 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2682 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2683 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2684 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2685 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2686 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2687 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2688 }
2689
7bd656d1 2690 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2691
cd28ab6a 2692 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2693 sky2_gmac_reset(hw, i);
cd28ab6a 2694
cd28ab6a
SH		 2695 memset(hw->st_le, 0, STATUS_LE_BYTES);
2696 hw->st_idx = 0;
2697
2698 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2699 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2700
2701 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2702 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2703
2704 /* Set the list last index */
793b883e 2705 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2706
290d4de5
SH		 2707 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2708 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2709
290d4de5
SH		 2710 /* set Status-FIFO ISR watermark */
2711 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2712 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2713 else
2714 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2715
290d4de5 2716 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2717 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2718 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2719
793b883e 2720 /* enable status unit */
cd28ab6a
SH		 2721 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2722
2723 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2724 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2725 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2726}
2727
81906791
SH		 2728static void sky2_restart(struct work_struct *work)
2729{
2730 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2731 struct net_device *dev;
2732 int i, err;
2733
2734 dev_dbg(&hw->pdev->dev, "restarting\n");
2735
2736 del_timer_sync(&hw->idle_timer);
2737
2738 rtnl_lock();
2739 sky2_write32(hw, B0_IMSK, 0);
2740 sky2_read32(hw, B0_IMSK);
2741
2742 netif_poll_disable(hw->dev[0]);
2743
2744 for (i = 0; i < hw->ports; i++) {
2745 dev = hw->dev[i];
2746 if (netif_running(dev))
2747 sky2_down(dev);
2748 }
2749
2750 sky2_reset(hw);
2751 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2752 netif_poll_enable(hw->dev[0]);
2753
2754 for (i = 0; i < hw->ports; i++) {
2755 dev = hw->dev[i];
2756 if (netif_running(dev)) {
2757 err = sky2_up(dev);
2758 if (err) {
2759 printk(KERN_INFO PFX "%s: could not restart %d\n",
2760 dev->name, err);
2761 dev_close(dev);
2762 }
2763 }
2764 }
2765
2766 sky2_idle_start(hw);
2767
2768 rtnl_unlock();
2769}
2770
e3173832
SH		 2771static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2772{
2773 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2774}
2775
2776static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2777{
2778 const struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 wol->supported = sky2_wol_supported(sky2->hw);
2781 wol->wolopts = sky2->wol;
2782}
2783
2784static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2785{
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2788
e3173832
SH		 2789 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2790 return -EOPNOTSUPP;
2791
2792 sky2->wol = wol->wolopts;
2793
69161611 2794 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX)
e3173832
SH		 2795 sky2_write32(hw, B0_CTST, sky2->wol
2796 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2797
2798 if (!netif_running(dev))
2799 sky2_wol_init(sky2);
cd28ab6a
SH		 2800 return 0;
2801}
2802
28bd181a 2803static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2804{
b89165f2
SH		 2805 if (sky2_is_copper(hw)) {
2806 u32 modes = SUPPORTED_10baseT_Half
2807 | SUPPORTED_10baseT_Full
2808 | SUPPORTED_100baseT_Half
2809 | SUPPORTED_100baseT_Full
2810 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2811
2812 if (hw->chip_id != CHIP_ID_YUKON_FE)
2813 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2814 | SUPPORTED_1000baseT_Full;
2815 return modes;
cd28ab6a 2816 } else
b89165f2
SH		 2817 return SUPPORTED_1000baseT_Half
2818 | SUPPORTED_1000baseT_Full
2819 | SUPPORTED_Autoneg
2820 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2821}
2822
793b883e 2823static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2824{
2825 struct sky2_port *sky2 = netdev_priv(dev);
2826 struct sky2_hw *hw = sky2->hw;
2827
2828 ecmd->transceiver = XCVR_INTERNAL;
2829 ecmd->supported = sky2_supported_modes(hw);
2830 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2831 if (sky2_is_copper(hw)) {
cd28ab6a 2832 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2833 | SUPPORTED_10baseT_Full
2834 | SUPPORTED_100baseT_Half
2835 | SUPPORTED_100baseT_Full
2836 | SUPPORTED_1000baseT_Half
2837 | SUPPORTED_1000baseT_Full
2838 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2839 ecmd->port = PORT_TP;
b89165f2
SH		 2840 ecmd->speed = sky2->speed;
2841 } else {
2842 ecmd->speed = SPEED_1000;
cd28ab6a 2843 ecmd->port = PORT_FIBRE;
b89165f2 2844 }
cd28ab6a
SH		 2845
2846 ecmd->advertising = sky2->advertising;
2847 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2848 ecmd->duplex = sky2->duplex;
2849 return 0;
2850}
2851
2852static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2853{
2854 struct sky2_port *sky2 = netdev_priv(dev);
2855 const struct sky2_hw *hw = sky2->hw;
2856 u32 supported = sky2_supported_modes(hw);
2857
2858 if (ecmd->autoneg == AUTONEG_ENABLE) {
2859 ecmd->advertising = supported;
2860 sky2->duplex = -1;
2861 sky2->speed = -1;
2862 } else {
2863 u32 setting;
2864
793b883e 2865 switch (ecmd->speed) {
cd28ab6a
SH		 2866 case SPEED_1000:
2867 if (ecmd->duplex == DUPLEX_FULL)
2868 setting = SUPPORTED_1000baseT_Full;
2869 else if (ecmd->duplex == DUPLEX_HALF)
2870 setting = SUPPORTED_1000baseT_Half;
2871 else
2872 return -EINVAL;
2873 break;
2874 case SPEED_100:
2875 if (ecmd->duplex == DUPLEX_FULL)
2876 setting = SUPPORTED_100baseT_Full;
2877 else if (ecmd->duplex == DUPLEX_HALF)
2878 setting = SUPPORTED_100baseT_Half;
2879 else
2880 return -EINVAL;
2881 break;
2882
2883 case SPEED_10:
2884 if (ecmd->duplex == DUPLEX_FULL)
2885 setting = SUPPORTED_10baseT_Full;
2886 else if (ecmd->duplex == DUPLEX_HALF)
2887 setting = SUPPORTED_10baseT_Half;
2888 else
2889 return -EINVAL;
2890 break;
2891 default:
2892 return -EINVAL;
2893 }
2894
2895 if ((setting & supported) == 0)
2896 return -EINVAL;
2897
2898 sky2->speed = ecmd->speed;
2899 sky2->duplex = ecmd->duplex;
2900 }
2901
2902 sky2->autoneg = ecmd->autoneg;
2903 sky2->advertising = ecmd->advertising;
2904
1b537565
SH		 2905 if (netif_running(dev))
2906 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2907
2908 return 0;
2909}
2910
2911static void sky2_get_drvinfo(struct net_device *dev,
2912 struct ethtool_drvinfo *info)
2913{
2914 struct sky2_port *sky2 = netdev_priv(dev);
2915
2916 strcpy(info->driver, DRV_NAME);
2917 strcpy(info->version, DRV_VERSION);
2918 strcpy(info->fw_version, "N/A");
2919 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2920}
2921
2922static const struct sky2_stat {
793b883e
SH		 2923 char name[ETH_GSTRING_LEN];
2924 u16 offset;
cd28ab6a
SH		 2925} sky2_stats[] = {
2926 { "tx_bytes", GM_TXO_OK_HI },
2927 { "rx_bytes", GM_RXO_OK_HI },
2928 { "tx_broadcast", GM_TXF_BC_OK },
2929 { "rx_broadcast", GM_RXF_BC_OK },
2930 { "tx_multicast", GM_TXF_MC_OK },
2931 { "rx_multicast", GM_RXF_MC_OK },
2932 { "tx_unicast", GM_TXF_UC_OK },
2933 { "rx_unicast", GM_RXF_UC_OK },
2934 { "tx_mac_pause", GM_TXF_MPAUSE },
2935 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2936 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2937 { "late_collision",GM_TXF_LAT_COL },
2938 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2939 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2940 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2941
d2604540 2942 { "rx_short", GM_RXF_SHT },
cd28ab6a 2943 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2944 { "rx_64_byte_packets", GM_RXF_64B },
2945 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2946 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2947 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2948 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2949 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2950 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2951 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2952 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2953 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2954 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2955
2956 { "tx_64_byte_packets", GM_TXF_64B },
2957 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2958 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2959 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2960 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2961 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2962 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2963 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2964};
2965
cd28ab6a
SH		 2966static u32 sky2_get_rx_csum(struct net_device *dev)
2967{
2968 struct sky2_port *sky2 = netdev_priv(dev);
2969
2970 return sky2->rx_csum;
2971}
2972
2973static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2974{
2975 struct sky2_port *sky2 = netdev_priv(dev);
2976
2977 sky2->rx_csum = data;
793b883e 2978
cd28ab6a
SH		 2979 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2980 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2981
2982 return 0;
2983}
2984
2985static u32 sky2_get_msglevel(struct net_device *netdev)
2986{
2987 struct sky2_port *sky2 = netdev_priv(netdev);
2988 return sky2->msg_enable;
2989}
2990
9a7ae0a9
SH		 2991static int sky2_nway_reset(struct net_device *dev)
2992{
2993 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2994
16ad91e1 2995 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2996 return -EINVAL;
2997
1b537565 2998 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2999
3000 return 0;
3001}
3002
793b883e 3003static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3004{
3005 struct sky2_hw *hw = sky2->hw;
3006 unsigned port = sky2->port;
3007 int i;
3008
3009 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3010 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3011 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3012 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3013
793b883e 3014 for (i = 2; i < count; i++)
cd28ab6a
SH		 3015 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3016}
3017
cd28ab6a
SH		 3018static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3019{
3020 struct sky2_port *sky2 = netdev_priv(netdev);
3021 sky2->msg_enable = value;
3022}
3023
3024static int sky2_get_stats_count(struct net_device *dev)
3025{
3026 return ARRAY_SIZE(sky2_stats);
3027}
3028
3029static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3030 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3031{
3032 struct sky2_port *sky2 = netdev_priv(dev);
3033
793b883e 3034 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3035}
3036
793b883e 3037static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3038{
3039 int i;
3040
3041 switch (stringset) {
3042 case ETH_SS_STATS:
3043 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3044 memcpy(data + i * ETH_GSTRING_LEN,
3045 sky2_stats[i].name, ETH_GSTRING_LEN);
3046 break;
3047 }
3048}
3049
cd28ab6a
SH		 3050static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3051{
3052 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3053 return &sky2->net_stats;
3054}
3055
3056static int sky2_set_mac_address(struct net_device *dev, void *p)
3057{
3058 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3059 struct sky2_hw *hw = sky2->hw;
3060 unsigned port = sky2->port;
3061 const struct sockaddr *addr = p;
cd28ab6a
SH		 3062
3063 if (!is_valid_ether_addr(addr->sa_data))
3064 return -EADDRNOTAVAIL;
3065
cd28ab6a 3066 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3067 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3068 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3069 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3070 dev->dev_addr, ETH_ALEN);
1b537565 3071
a8ab1ec0
SH		 3072 /* virtual address for data */
3073 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3074
3075 /* physical address: used for pause frames */
3076 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3077
3078 return 0;
cd28ab6a
SH		 3079}
3080
a052b52f
SH		 3081static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3082{
3083 u32 bit;
3084
3085 bit = ether_crc(ETH_ALEN, addr) & 63;
3086 filter[bit >> 3] |= 1 << (bit & 7);
3087}
3088
cd28ab6a
SH		 3089static void sky2_set_multicast(struct net_device *dev)
3090{
3091 struct sky2_port *sky2 = netdev_priv(dev);
3092 struct sky2_hw *hw = sky2->hw;
3093 unsigned port = sky2->port;
3094 struct dev_mc_list *list = dev->mc_list;
3095 u16 reg;
3096 u8 filter[8];
a052b52f
SH		 3097 int rx_pause;
3098 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3099
a052b52f 3100 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3101 memset(filter, 0, sizeof(filter));
3102
3103 reg = gma_read16(hw, port, GM_RX_CTRL);
3104 reg |= GM_RXCR_UCF_ENA;
3105
d571b694 3106 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3107 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3108 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3109 memset(filter, 0xff, sizeof(filter));
a052b52f 3110 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3111 reg &= ~GM_RXCR_MCF_ENA;
3112 else {
3113 int i;
3114 reg |= GM_RXCR_MCF_ENA;
3115
a052b52f
SH		 3116 if (rx_pause)
3117 sky2_add_filter(filter, pause_mc_addr);
3118
3119 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3120 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3121 }
3122
cd28ab6a 3123 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3124 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3125 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3126 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3127 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3128 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3129 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3130 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3131
3132 gma_write16(hw, port, GM_RX_CTRL, reg);
3133}
3134
3135/* Can have one global because blinking is controlled by
3136 * ethtool and that is always under RTNL mutex
3137 */
91c86df5 3138static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3139{
793b883e
SH		 3140 u16 pg;
3141
793b883e
SH		 3142 switch (hw->chip_id) {
3143 case CHIP_ID_YUKON_XL:
3144 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3145 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3146 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3147 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3148 PHY_M_LEDC_INIT_CTRL(7) |
3149 PHY_M_LEDC_STA1_CTRL(7) |
3150 PHY_M_LEDC_STA0_CTRL(7))
3151 : 0);
3152
3153 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3154 break;
3155
3156 default:
3157 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3158 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3159 on ? PHY_M_LED_ALL : 0);
793b883e 3160 }
cd28ab6a
SH		 3161}
3162
3163/* blink LED's for finding board */
3164static int sky2_phys_id(struct net_device *dev, u32 data)
3165{
3166 struct sky2_port *sky2 = netdev_priv(dev);
3167 struct sky2_hw *hw = sky2->hw;
3168 unsigned port = sky2->port;
793b883e 3169 u16 ledctrl, ledover = 0;
cd28ab6a 3170 long ms;
91c86df5 3171 int interrupted;
cd28ab6a
SH		 3172 int onoff = 1;
3173
793b883e 3174 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3175 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3176 else
3177 ms = data * 1000;
3178
3179 /* save initial values */
e07b1aa8 3180 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3181 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3182 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3183 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3184 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3185 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3186 } else {
3187 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3188 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3189 }
cd28ab6a 3190
91c86df5
SH		 3191 interrupted = 0;
3192 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3193 sky2_led(hw, port, onoff);
3194 onoff = !onoff;
3195
e07b1aa8 3196 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3197 interrupted = msleep_interruptible(250);
e07b1aa8 3198 spin_lock_bh(&sky2->phy_lock);
91c86df5 3199
cd28ab6a
SH		 3200 ms -= 250;
3201 }
3202
3203 /* resume regularly scheduled programming */
793b883e
SH		 3204 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3205 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3206 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3207 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3208 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3209 } else {
3210 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3211 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3212 }
e07b1aa8 3213 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3214
3215 return 0;
3216}
3217
3218static void sky2_get_pauseparam(struct net_device *dev,
3219 struct ethtool_pauseparam *ecmd)
3220{
3221 struct sky2_port *sky2 = netdev_priv(dev);
3222
16ad91e1
SH		 3223 switch (sky2->flow_mode) {
3224 case FC_NONE:
3225 ecmd->tx_pause = ecmd->rx_pause = 0;
3226 break;
3227 case FC_TX:
3228 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3229 break;
3230 case FC_RX:
3231 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3232 break;
3233 case FC_BOTH:
3234 ecmd->tx_pause = ecmd->rx_pause = 1;
3235 }
3236
cd28ab6a
SH		 3237 ecmd->autoneg = sky2->autoneg;
3238}
3239
3240static int sky2_set_pauseparam(struct net_device *dev,
3241 struct ethtool_pauseparam *ecmd)
3242{
3243 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3244
3245 sky2->autoneg = ecmd->autoneg;
16ad91e1 3246 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3247
16ad91e1
SH		 3248 if (netif_running(dev))
3249 sky2_phy_reinit(sky2);
cd28ab6a 3250
2eaba1a2 3251 return 0;
cd28ab6a
SH		 3252}
3253
fb17358f
SH		 3254static int sky2_get_coalesce(struct net_device *dev,
3255 struct ethtool_coalesce *ecmd)
3256{
3257 struct sky2_port *sky2 = netdev_priv(dev);
3258 struct sky2_hw *hw = sky2->hw;
3259
3260 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3261 ecmd->tx_coalesce_usecs = 0;
3262 else {
3263 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3264 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3265 }
3266 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3267
3268 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3269 ecmd->rx_coalesce_usecs = 0;
3270 else {
3271 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3272 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3273 }
3274 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3275
3276 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3277 ecmd->rx_coalesce_usecs_irq = 0;
3278 else {
3279 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3280 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3281 }
3282
3283 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3284
3285 return 0;
3286}
3287
3288/* Note: this affect both ports */
3289static int sky2_set_coalesce(struct net_device *dev,
3290 struct ethtool_coalesce *ecmd)
3291{
3292 struct sky2_port *sky2 = netdev_priv(dev);
3293 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3294 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3295
77b3d6a2
SH		 3296 if (ecmd->tx_coalesce_usecs > tmax ||
3297 ecmd->rx_coalesce_usecs > tmax ||
3298 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3299 return -EINVAL;
3300
ff81fbbe 3301 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3302 return -EINVAL;
ff81fbbe 3303 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3304 return -EINVAL;
ff81fbbe 3305 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3306 return -EINVAL;
3307
3308 if (ecmd->tx_coalesce_usecs == 0)
3309 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3310 else {
3311 sky2_write32(hw, STAT_TX_TIMER_INI,
3312 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3313 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3314 }
3315 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3316
3317 if (ecmd->rx_coalesce_usecs == 0)
3318 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3319 else {
3320 sky2_write32(hw, STAT_LEV_TIMER_INI,
3321 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3322 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3323 }
3324 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3325
3326 if (ecmd->rx_coalesce_usecs_irq == 0)
3327 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3328 else {
d28d4870 3329 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3330 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3331 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3332 }
3333 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3334 return 0;
3335}
3336
793b883e
SH		 3337static void sky2_get_ringparam(struct net_device *dev,
3338 struct ethtool_ringparam *ering)
3339{
3340 struct sky2_port *sky2 = netdev_priv(dev);
3341
3342 ering->rx_max_pending = RX_MAX_PENDING;
3343 ering->rx_mini_max_pending = 0;
3344 ering->rx_jumbo_max_pending = 0;
3345 ering->tx_max_pending = TX_RING_SIZE - 1;
3346
3347 ering->rx_pending = sky2->rx_pending;
3348 ering->rx_mini_pending = 0;
3349 ering->rx_jumbo_pending = 0;
3350 ering->tx_pending = sky2->tx_pending;
3351}
3352
3353static int sky2_set_ringparam(struct net_device *dev,
3354 struct ethtool_ringparam *ering)
3355{
3356 struct sky2_port *sky2 = netdev_priv(dev);
3357 int err = 0;
3358
3359 if (ering->rx_pending > RX_MAX_PENDING ||
3360 ering->rx_pending < 8 ||
3361 ering->tx_pending < MAX_SKB_TX_LE ||
3362 ering->tx_pending > TX_RING_SIZE - 1)
3363 return -EINVAL;
3364
3365 if (netif_running(dev))
3366 sky2_down(dev);
3367
3368 sky2->rx_pending = ering->rx_pending;
3369 sky2->tx_pending = ering->tx_pending;
3370
1b537565 3371 if (netif_running(dev)) {
793b883e 3372 err = sky2_up(dev);
1b537565
SH		 3373 if (err)
3374 dev_close(dev);
6ed995bb
SH		 3375 else
3376 sky2_set_multicast(dev);
1b537565 3377 }
793b883e
SH		 3378
3379 return err;
3380}
3381
793b883e
SH		 3382static int sky2_get_regs_len(struct net_device *dev)
3383{
6e4cbb34 3384 return 0x4000;
793b883e
SH		 3385}
3386
3387/*
3388 * Returns copy of control register region
3ead5db7 3389 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3390 */
3391static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3392 void *p)
3393{
3394 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3395 const void __iomem *io = sky2->hw->regs;
793b883e
SH		 3396
3397 regs->version = 1;
6e4cbb34 3398 memset(p, 0, regs->len);
793b883e 3399
6e4cbb34
SH		 3400 memcpy_fromio(p, io, B3_RAM_ADDR);
3401
3ead5db7
SH		 3402 /* skip diagnostic ram region */
3403 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, 0x2000 - B3_RI_WTO_R1);
3404
3405 /* copy GMAC registers */
3406 memcpy_fromio(p + BASE_GMAC_1, io + BASE_GMAC_1, 0x1000);
3407 if (sky2->hw->ports > 1)
3408 memcpy_fromio(p + BASE_GMAC_2, io + BASE_GMAC_2, 0x1000);
3409
793b883e 3410}
cd28ab6a 3411
b628ed98
SH		 3412/* In order to do Jumbo packets on these chips, need to turn off the
3413 * transmit store/forward. Therefore checksum offload won't work.
3414 */
3415static int no_tx_offload(struct net_device *dev)
3416{
3417 const struct sky2_port *sky2 = netdev_priv(dev);
3418 const struct sky2_hw *hw = sky2->hw;
3419
69161611 3420 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3421}
3422
3423static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3424{
3425 if (data && no_tx_offload(dev))
3426 return -EINVAL;
3427
3428 return ethtool_op_set_tx_csum(dev, data);
3429}
3430
3431
3432static int sky2_set_tso(struct net_device *dev, u32 data)
3433{
3434 if (data && no_tx_offload(dev))
3435 return -EINVAL;
3436
3437 return ethtool_op_set_tso(dev, data);
3438}
3439
7282d491 3440static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3441 .get_settings = sky2_get_settings,
3442 .set_settings = sky2_set_settings,
e3173832
SH		 3443 .get_drvinfo = sky2_get_drvinfo,
3444 .get_wol = sky2_get_wol,
3445 .set_wol = sky2_set_wol,
793b883e
SH		 3446 .get_msglevel = sky2_get_msglevel,
3447 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3448 .nway_reset = sky2_nway_reset,
793b883e
SH		 3449 .get_regs_len = sky2_get_regs_len,
3450 .get_regs = sky2_get_regs,
3451 .get_link = ethtool_op_get_link,
3452 .get_sg = ethtool_op_get_sg,
3453 .set_sg = ethtool_op_set_sg,
3454 .get_tx_csum = ethtool_op_get_tx_csum,
b628ed98 3455 .set_tx_csum = sky2_set_tx_csum,
793b883e 3456 .get_tso = ethtool_op_get_tso,
b628ed98 3457 .set_tso = sky2_set_tso,
793b883e
SH		 3458 .get_rx_csum = sky2_get_rx_csum,
3459 .set_rx_csum = sky2_set_rx_csum,
3460 .get_strings = sky2_get_strings,
fb17358f
SH		 3461 .get_coalesce = sky2_get_coalesce,
3462 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3463 .get_ringparam = sky2_get_ringparam,
3464 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3465 .get_pauseparam = sky2_get_pauseparam,
3466 .set_pauseparam = sky2_set_pauseparam,
793b883e 3467 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3468 .get_stats_count = sky2_get_stats_count,
3469 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3470 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3471};
3472
3cf26753
SH		 3473#ifdef CONFIG_SKY2_DEBUG
3474
3475static struct dentry *sky2_debug;
3476
3477static int sky2_debug_show(struct seq_file *seq, void *v)
3478{
3479 struct net_device *dev = seq->private;
3480 const struct sky2_port *sky2 = netdev_priv(dev);
3481 const struct sky2_hw *hw = sky2->hw;
3482 unsigned port = sky2->port;
3483 unsigned idx, last;
3484 int sop;
3485
3486 if (!netif_running(dev))
3487 return -ENETDOWN;
3488
3489 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3490 sky2_read32(hw, B0_ISRC),
3491 sky2_read32(hw, B0_IMSK),
3492 sky2_read32(hw, B0_Y2_SP_ICR));
3493
3494 netif_poll_disable(hw->dev[0]);
3495 last = sky2_read16(hw, STAT_PUT_IDX);
3496
3497 if (hw->st_idx == last)
3498 seq_puts(seq, "Status ring (empty)\n");
3499 else {
3500 seq_puts(seq, "Status ring\n");
3501 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3502 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3503 const struct sky2_status_le *le = hw->st_le + idx;
3504 seq_printf(seq, "[%d] %#x %d %#x\n",
3505 idx, le->opcode, le->length, le->status);
3506 }
3507 seq_puts(seq, "\n");
3508 }
3509
3510 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3511 sky2->tx_cons, sky2->tx_prod,
3512 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3513 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3514
3515 /* Dump contents of tx ring */
3516 sop = 1;
3517 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3518 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3519 const struct sky2_tx_le *le = sky2->tx_le + idx;
3520 u32 a = le32_to_cpu(le->addr);
3521
3522 if (sop)
3523 seq_printf(seq, "%u:", idx);
3524 sop = 0;
3525
3526 switch(le->opcode & ~HW_OWNER) {
3527 case OP_ADDR64:
3528 seq_printf(seq, " %#x:", a);
3529 break;
3530 case OP_LRGLEN:
3531 seq_printf(seq, " mtu=%d", a);
3532 break;
3533 case OP_VLAN:
3534 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3535 break;
3536 case OP_TCPLISW:
3537 seq_printf(seq, " csum=%#x", a);
3538 break;
3539 case OP_LARGESEND:
3540 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3541 break;
3542 case OP_PACKET:
3543 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3544 break;
3545 case OP_BUFFER:
3546 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3547 break;
3548 default:
3549 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3550 a, le16_to_cpu(le->length));
3551 }
3552
3553 if (le->ctrl & EOP) {
3554 seq_putc(seq, '\n');
3555 sop = 1;
3556 }
3557 }
3558
3559 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3560 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3561 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3562 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3563
3564 netif_poll_enable(hw->dev[0]);
3565 return 0;
3566}
3567
3568static int sky2_debug_open(struct inode *inode, struct file *file)
3569{
3570 return single_open(file, sky2_debug_show, inode->i_private);
3571}
3572
3573static const struct file_operations sky2_debug_fops = {
3574 .owner = THIS_MODULE,
3575 .open = sky2_debug_open,
3576 .read = seq_read,
3577 .llseek = seq_lseek,
3578 .release = single_release,
3579};
3580
3581/*
3582 * Use network device events to create/remove/rename
3583 * debugfs file entries
3584 */
3585static int sky2_device_event(struct notifier_block *unused,
3586 unsigned long event, void *ptr)
3587{
3588 struct net_device *dev = ptr;
3589
3590 if (dev->open == sky2_up) {
3591 struct sky2_port *sky2 = netdev_priv(dev);
3592
3593 switch(event) {
3594 case NETDEV_CHANGENAME:
3595 if (!netif_running(dev))
3596 break;
3597 /* fallthrough */
3598 case NETDEV_DOWN:
3599 case NETDEV_GOING_DOWN:
3600 if (sky2->debugfs) {
3601 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3602 dev->name);
3603 debugfs_remove(sky2->debugfs);
3604 sky2->debugfs = NULL;
3605 }
3606
3607 if (event != NETDEV_CHANGENAME)
3608 break;
3609 /* fallthrough for changename */
3610 case NETDEV_UP:
3611 if (sky2_debug) {
3612 struct dentry *d;
3613 d = debugfs_create_file(dev->name, S_IRUGO,
3614 sky2_debug, dev,
3615 &sky2_debug_fops);
3616 if (d == NULL || IS_ERR(d))
3617 printk(KERN_INFO PFX
3618 "%s: debugfs create failed\n",
3619 dev->name);
3620 else
3621 sky2->debugfs = d;
3622 }
3623 break;
3624 }
3625 }
3626
3627 return NOTIFY_DONE;
3628}
3629
3630static struct notifier_block sky2_notifier = {
3631 .notifier_call = sky2_device_event,
3632};
3633
3634
3635static __init void sky2_debug_init(void)
3636{
3637 struct dentry *ent;
3638
3639 ent = debugfs_create_dir("sky2", NULL);
3640 if (!ent || IS_ERR(ent))
3641 return;
3642
3643 sky2_debug = ent;
3644 register_netdevice_notifier(&sky2_notifier);
3645}
3646
3647static __exit void sky2_debug_cleanup(void)
3648{
3649 if (sky2_debug) {
3650 unregister_netdevice_notifier(&sky2_notifier);
3651 debugfs_remove(sky2_debug);
3652 sky2_debug = NULL;
3653 }
3654}
3655
3656#else
3657#define sky2_debug_init()
3658#define sky2_debug_cleanup()
3659#endif
3660
3661
cd28ab6a
SH		 3662/* Initialize network device */
3663static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3664 unsigned port,
3665 int highmem, int wol)
cd28ab6a
SH		 3666{
3667 struct sky2_port *sky2;
3668 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3669
3670 if (!dev) {
b02a9258 3671 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3672 return NULL;
3673 }
3674
3675 SET_MODULE_OWNER(dev);
3676 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3677 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3678 dev->open = sky2_up;
3679 dev->stop = sky2_down;
ef743d33 3680 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3681 dev->hard_start_xmit = sky2_xmit_frame;
3682 dev->get_stats = sky2_get_stats;
3683 dev->set_multicast_list = sky2_set_multicast;
3684 dev->set_mac_address = sky2_set_mac_address;
3685 dev->change_mtu = sky2_change_mtu;
3686 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3687 dev->tx_timeout = sky2_tx_timeout;
3688 dev->watchdog_timeo = TX_WATCHDOG;
3689 if (port == 0)
3690 dev->poll = sky2_poll;
3691 dev->weight = NAPI_WEIGHT;
3692#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3693 /* Network console (only works on port 0)
3694 * because netpoll makes assumptions about NAPI
3695 */
3696 if (port == 0)
3697 dev->poll_controller = sky2_netpoll;
cd28ab6a 3698#endif
cd28ab6a
SH		 3699
3700 sky2 = netdev_priv(dev);
3701 sky2->netdev = dev;
3702 sky2->hw = hw;
3703 sky2->msg_enable = netif_msg_init(debug, default_msg);
3704
cd28ab6a
SH		 3705 /* Auto speed and flow control */
3706 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3707 sky2->flow_mode = FC_BOTH;
3708
cd28ab6a
SH		 3709 sky2->duplex = -1;
3710 sky2->speed = -1;
3711 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3712 sky2->rx_csum = 1;
e3173832 3713 sky2->wol = wol;
75d070c5 3714
e07b1aa8 3715 spin_lock_init(&sky2->phy_lock);
793b883e 3716 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3717 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3718
3719 hw->dev[port] = dev;
3720
3721 sky2->port = port;
3722
4a50a876 3723 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3724 if (highmem)
3725 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3726
d1f13708
SH		 3727#ifdef SKY2_VLAN_TAG_USED
3728 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3729 dev->vlan_rx_register = sky2_vlan_rx_register;
d1f13708
SH		 3730#endif
3731
cd28ab6a 3732 /* read the mac address */
793b883e 3733 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3734 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 3735
cd28ab6a
SH		 3736 return dev;
3737}
3738
28bd181a 3739static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3740{
3741 const struct sky2_port *sky2 = netdev_priv(dev);
3742
3743 if (netif_msg_probe(sky2))
3744 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3745 dev->name,
3746 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3747 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3748}
3749
fb2690a9 3750/* Handle software interrupt used during MSI test */
7d12e780 3751static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3752{
3753 struct sky2_hw *hw = dev_id;
3754 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3755
3756 if (status == 0)
3757 return IRQ_NONE;
3758
3759 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3760 hw->msi = 1;
fb2690a9
SH		 3761 wake_up(&hw->msi_wait);
3762 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3763 }
3764 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3765
3766 return IRQ_HANDLED;
3767}
3768
3769/* Test interrupt path by forcing a a software IRQ */
3770static int __devinit sky2_test_msi(struct sky2_hw *hw)
3771{
3772 struct pci_dev *pdev = hw->pdev;
3773 int err;
3774
bb507fe1
SH		 3775 init_waitqueue_head (&hw->msi_wait);
3776
fb2690a9
SH		 3777 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3778
b0a20ded 3779 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3780 if (err) {
b02a9258 3781 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3782 return err;
3783 }
3784
fb2690a9 3785 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3786 sky2_read8(hw, B0_CTST);
fb2690a9 3787
b0a20ded 3788 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3789
b0a20ded 3790 if (!hw->msi) {
fb2690a9 3791 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3792 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3793 "switching to INTx mode.\n");
fb2690a9
SH		 3794
3795 err = -EOPNOTSUPP;
3796 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3797 }
3798
3799 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3800 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3801
3802 free_irq(pdev->irq, hw);
3803
3804 return err;
3805}
3806
e3173832
SH		 3807static int __devinit pci_wake_enabled(struct pci_dev *dev)
3808{
3809 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3810 u16 value;
3811
3812 if (!pm)
3813 return 0;
3814 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3815 return 0;
3816 return value & PCI_PM_CTRL_PME_ENABLE;
3817}
3818
cd28ab6a
SH		 3819static int __devinit sky2_probe(struct pci_dev *pdev,
3820 const struct pci_device_id *ent)
3821{
7f60c64b 3822 struct net_device *dev;
cd28ab6a 3823 struct sky2_hw *hw;
e3173832 3824 int err, using_dac = 0, wol_default;
cd28ab6a 3825
793b883e
SH		 3826 err = pci_enable_device(pdev);
3827 if (err) {
b02a9258 3828 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3829 goto err_out;
3830 }
3831
793b883e
SH		 3832 err = pci_request_regions(pdev, DRV_NAME);
3833 if (err) {
b02a9258 3834 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 3835 goto err_out_disable;
cd28ab6a
SH		 3836 }
3837
3838 pci_set_master(pdev);
3839
d1f3d4dd
SH		 3840 if (sizeof(dma_addr_t) > sizeof(u32) &&
3841 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3842 using_dac = 1;
3843 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3844 if (err < 0) {
b02a9258
SH		 3845 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3846 "for consistent allocations\n");
d1f3d4dd
SH		 3847 goto err_out_free_regions;
3848 }
d1f3d4dd 3849 } else {
cd28ab6a
SH		 3850 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3851 if (err) {
b02a9258 3852 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3853 goto err_out_free_regions;
3854 }
3855 }
d1f3d4dd 3856
e3173832
SH		 3857 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3858
cd28ab6a 3859 err = -ENOMEM;
6aad85d6 3860 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3861 if (!hw) {
b02a9258 3862 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3863 goto err_out_free_regions;
3864 }
3865
cd28ab6a 3866 hw->pdev = pdev;
cd28ab6a
SH		 3867
3868 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3869 if (!hw->regs) {
b02a9258 3870 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3871 goto err_out_free_hw;
3872 }
3873
56a645cc 3874#ifdef __BIG_ENDIAN
f65b138c
SH		 3875 /* The sk98lin vendor driver uses hardware byte swapping but
3876 * this driver uses software swapping.
3877 */
56a645cc
SH		 3878 {
3879 u32 reg;
56a645cc 3880 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3881 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3882 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3883 }
3884#endif
3885
08c06d8a
SH		 3886 /* ring for status responses */
3887 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3888 &hw->st_dma);
3889 if (!hw->st_le)
3890 goto err_out_iounmap;
3891
e3173832 3892 err = sky2_init(hw);
cd28ab6a 3893 if (err)
793b883e 3894 goto err_out_iounmap;
cd28ab6a 3895
b02a9258 3896 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3897 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3898 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3899 hw->chip_id, hw->chip_rev);
cd28ab6a 3900
e3173832
SH		 3901 sky2_reset(hw);
3902
3903 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3904 if (!dev) {
3905 err = -ENOMEM;
cd28ab6a 3906 goto err_out_free_pci;
7f60c64b 3907 }
cd28ab6a 3908
9fa1b1f3
SH		 3909 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3910 err = sky2_test_msi(hw);
3911 if (err == -EOPNOTSUPP)
3912 pci_disable_msi(pdev);
3913 else if (err)
3914 goto err_out_free_netdev;
3915 }
3916
793b883e
SH		 3917 err = register_netdev(dev);
3918 if (err) {
b02a9258 3919 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3920 goto err_out_free_netdev;
3921 }
3922
b0a20ded
SH		 3923 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3924 dev->name, hw);
9fa1b1f3 3925 if (err) {
b02a9258 3926 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3927 goto err_out_unregister;
3928 }
3929 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3930
cd28ab6a
SH		 3931 sky2_show_addr(dev);
3932
7f60c64b 3933 if (hw->ports > 1) {
3934 struct net_device *dev1;
3935
e3173832 3936 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3937 if (!dev1)
3938 dev_warn(&pdev->dev, "allocation for second device failed\n");
3939 else if ((err = register_netdev(dev1))) {
3940 dev_warn(&pdev->dev,
3941 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3942 hw->dev[1] = NULL;
3943 free_netdev(dev1);
b02a9258
SH		 3944 } else
3945 sky2_show_addr(dev1);
cd28ab6a
SH		 3946 }
3947
01bd7564 3948 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3949 INIT_WORK(&hw->restart_work, sky2_restart);
3950
eb35cf60 3951 sky2_idle_start(hw);
d27ed387 3952
793b883e
SH		 3953 pci_set_drvdata(pdev, hw);
3954
cd28ab6a
SH		 3955 return 0;
3956
793b883e 3957err_out_unregister:
b0a20ded
SH		 3958 if (hw->msi)
3959 pci_disable_msi(pdev);
793b883e 3960 unregister_netdev(dev);
cd28ab6a
SH		 3961err_out_free_netdev:
3962 free_netdev(dev);
cd28ab6a 3963err_out_free_pci:
793b883e 3964 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3965 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3966err_out_iounmap:
3967 iounmap(hw->regs);
3968err_out_free_hw:
3969 kfree(hw);
3970err_out_free_regions:
3971 pci_release_regions(pdev);
44a1d2e5 3972err_out_disable:
cd28ab6a 3973 pci_disable_device(pdev);
cd28ab6a 3974err_out:
549a68c3 3975 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 3976 return err;
3977}
3978
3979static void __devexit sky2_remove(struct pci_dev *pdev)
3980{
793b883e 3981 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3982 struct net_device *dev0, *dev1;
3983
793b883e 3984 if (!hw)
cd28ab6a
SH		 3985 return;
3986
d27ed387
SH		 3987 del_timer_sync(&hw->idle_timer);
3988
81906791
SH		 3989 flush_scheduled_work();
3990
d27ed387 3991 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3992 synchronize_irq(hw->pdev->irq);
3993
cd28ab6a 3994 dev0 = hw->dev[0];
793b883e
SH		 3995 dev1 = hw->dev[1];
3996 if (dev1)
3997 unregister_netdev(dev1);
cd28ab6a
SH		 3998 unregister_netdev(dev0);
3999
ae306cca
SH		 4000 sky2_power_aux(hw);
4001
cd28ab6a 4002 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4003 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4004 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4005
4006 free_irq(pdev->irq, hw);
b0a20ded
SH		 4007 if (hw->msi)
4008 pci_disable_msi(pdev);
793b883e 4009 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4010 pci_release_regions(pdev);
4011 pci_disable_device(pdev);
793b883e 4012
cd28ab6a
SH		 4013 if (dev1)
4014 free_netdev(dev1);
4015 free_netdev(dev0);
4016 iounmap(hw->regs);
4017 kfree(hw);
5afa0a9c 4018
cd28ab6a
SH		 4019 pci_set_drvdata(pdev, NULL);
4020}
4021
4022#ifdef CONFIG_PM
4023static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4024{
793b883e 4025 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4026 int i, wol = 0;
cd28ab6a 4027
549a68c3
SH		 4028 if (!hw)
4029 return 0;
4030
eb35cf60 4031 del_timer_sync(&hw->idle_timer);
6a5706b9 4032 netif_poll_disable(hw->dev[0]);
eb35cf60 4033
f05267e7 4034 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4035 struct net_device *dev = hw->dev[i];
e3173832 4036 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4037
e3173832 4038 if (netif_running(dev))
5afa0a9c 4039 sky2_down(dev);
e3173832
SH		 4040
4041 if (sky2->wol)
4042 sky2_wol_init(sky2);
4043
4044 wol |= sky2->wol;
cd28ab6a
SH		 4045 }
4046
8ab8fca2 4047 sky2_write32(hw, B0_IMSK, 0);
ae306cca 4048 sky2_power_aux(hw);
e3173832 4049
d374c1c1 4050 pci_save_state(pdev);
e3173832 4051 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 4052 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4053
2ccc99b7 4054 return 0;
cd28ab6a
SH		 4055}
4056
4057static int sky2_resume(struct pci_dev *pdev)
4058{
793b883e 4059 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4060 int i, err;
cd28ab6a 4061
549a68c3
SH		 4062 if (!hw)
4063 return 0;
4064
ae306cca
SH		 4065 err = pci_set_power_state(pdev, PCI_D0);
4066 if (err)
4067 goto out;
4068
4069 err = pci_restore_state(pdev);
4070 if (err)
4071 goto out;
4072
cd28ab6a 4073 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4074
4075 /* Re-enable all clocks */
4076 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
4077 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4078
e3173832 4079 sky2_reset(hw);
cd28ab6a 4080
8ab8fca2
SH		 4081 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4082
f05267e7 4083 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4084 struct net_device *dev = hw->dev[i];
6a5706b9 4085 if (netif_running(dev)) {
08c06d8a
SH		 4086 err = sky2_up(dev);
4087 if (err) {
4088 printk(KERN_ERR PFX "%s: could not up: %d\n",
4089 dev->name, err);
4090 dev_close(dev);
eb35cf60 4091 goto out;
5afa0a9c 4092 }
cd28ab6a
SH		 4093 }
4094 }
eb35cf60 4095
6a5706b9 4096 netif_poll_enable(hw->dev[0]);
eb35cf60 4097 sky2_idle_start(hw);
ae306cca 4098 return 0;
08c06d8a 4099out:
b02a9258 4100 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4101 pci_disable_device(pdev);
08c06d8a 4102 return err;
cd28ab6a
SH		 4103}
4104#endif
4105
e3173832
SH		 4106static void sky2_shutdown(struct pci_dev *pdev)
4107{
4108 struct sky2_hw *hw = pci_get_drvdata(pdev);
4109 int i, wol = 0;
4110
549a68c3
SH		 4111 if (!hw)
4112 return;
4113
e3173832
SH		 4114 del_timer_sync(&hw->idle_timer);
4115 netif_poll_disable(hw->dev[0]);
4116
4117 for (i = 0; i < hw->ports; i++) {
4118 struct net_device *dev = hw->dev[i];
4119 struct sky2_port *sky2 = netdev_priv(dev);
4120
4121 if (sky2->wol) {
4122 wol = 1;
4123 sky2_wol_init(sky2);
4124 }
4125 }
4126
4127 if (wol)
4128 sky2_power_aux(hw);
4129
4130 pci_enable_wake(pdev, PCI_D3hot, wol);
4131 pci_enable_wake(pdev, PCI_D3cold, wol);
4132
4133 pci_disable_device(pdev);
4134 pci_set_power_state(pdev, PCI_D3hot);
4135
4136}
4137
cd28ab6a 4138static struct pci_driver sky2_driver = {
793b883e
SH		 4139 .name = DRV_NAME,
4140 .id_table = sky2_id_table,
4141 .probe = sky2_probe,
4142 .remove = __devexit_p(sky2_remove),
cd28ab6a 4143#ifdef CONFIG_PM
793b883e
SH		 4144 .suspend = sky2_suspend,
4145 .resume = sky2_resume,
cd28ab6a 4146#endif
e3173832 4147 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4148};
4149
4150static int __init sky2_init_module(void)
4151{
3cf26753 4152 sky2_debug_init();
50241c4c 4153 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4154}
4155
4156static void __exit sky2_cleanup_module(void)
4157{
4158 pci_unregister_driver(&sky2_driver);
3cf26753 4159 sky2_debug_cleanup();
cd28ab6a
SH		 4160}
4161
4162module_init(sky2_init_module);
4163module_exit(sky2_cleanup_module);
4164
4165MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4166MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4167MODULE_LICENSE("GPL");
5f4f9dc1 4168MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree