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[PATCH] sky2: turn on tx flow control
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
d70cd51a 48#include <linux/prefetch.h>
ef743d33 49#include <linux/mii.h>
cd28ab6a
SH		 50
51#include <asm/irq.h>
52
d1f13708
SH		 53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define SKY2_VLAN_TAG_USED 1
55#endif
56
cd28ab6a
SH		 57#include "sky2.h"
58
59#define DRV_NAME "sky2"
5f4f9dc1 60#define DRV_VERSION "0.9"
cd28ab6a
SH		 61#define PFX DRV_NAME " "
62
63/*
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
68 */
69
cd28ab6a 70#define is_ec_a1(hw) \
21437643
SH		 71 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
72 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 73
13210ce5 74#define RX_LE_SIZE 512
cd28ab6a 75#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 76#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 77#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 78
79#define TX_RING_SIZE 512
80#define TX_DEF_PENDING (TX_RING_SIZE - 1)
81#define TX_MIN_PENDING 64
82#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 83
793b883e 84#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 85#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
86#define ETH_JUMBO_MTU 9000
87#define TX_WATCHDOG (5 * HZ)
88#define NAPI_WEIGHT 64
89#define PHY_RETRIES 1000
90
91static const u32 default_msg =
793b883e
SH		 92 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
93 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
94 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 95
793b883e 96static int debug = -1; /* defaults above */
cd28ab6a
SH		 97module_param(debug, int, 0);
98MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
99
bdb5c58e
SH		 100static int copybreak __read_mostly = 256;
101module_param(copybreak, int, 0);
102MODULE_PARM_DESC(copybreak, "Receive copy threshold");
103
cd28ab6a 104static const struct pci_device_id sky2_id_table[] = {
793b883e 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 124 { 0 }
125};
793b883e 126
cd28ab6a
SH		 127MODULE_DEVICE_TABLE(pci, sky2_id_table);
128
129/* Avoid conditionals by using array */
130static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
132
92f965e8
SH		 133/* This driver supports yukon2 chipset only */
134static const char *yukon2_name[] = {
135 "XL", /* 0xb3 */
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
138 "EC", /* 0xb6 */
139 "FE", /* 0xb7 */
793b883e
SH		 140};
141
793b883e 142/* Access to external PHY */
ef743d33 143static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 153 return 0;
793b883e 154 udelay(1);
cd28ab6a 155 }
ef743d33 156
793b883e 157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 158 return -ETIMEDOUT;
cd28ab6a
SH		 159}
160
ef743d33 161static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 162{
163 int i;
164
793b883e 165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
167
168 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
171 return 0;
172 }
173
793b883e 174 udelay(1);
cd28ab6a
SH		 175 }
176
ef743d33
SH		 177 return -ETIMEDOUT;
178}
179
180static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
181{
182 u16 v;
183
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
186 return v;
cd28ab6a
SH		 187}
188
5afa0a9c
SH		 189static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190{
191 u16 power_control;
192 u32 reg1;
193 int vaux;
194 int ret = 0;
195
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
198
199 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
200 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 (power_control & PCI_PM_CAP_PME_D3cold);
202
203 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
204
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
207
208 switch (state) {
209 case PCI_D0:
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
213
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
216
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
223 else
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
225
226 /* Turn off phy power saving */
227 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
229
d571b694 230 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
233 if (hw->ports > 1)
234 reg1 |= PCI_Y2_PHY2_COMA;
235 }
236 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
237 break;
238
239 case PCI_D3hot:
240 case PCI_D3cold:
241 /* Turn on phy power saving */
242 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
245 else
246 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
248
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
251 else
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
257
258 /* switch power to VAUX */
259 if (vaux && state != PCI_D3cold)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
263 break;
264 default:
265 printk(KERN_ERR PFX "Unknown power state %d\n", state);
266 ret = -1;
267 }
268
269 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
270 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
271 return ret;
272}
273
cd28ab6a
SH		 274static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
275{
276 u16 reg;
277
278 /* disable all GMAC IRQ's */
279 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
280 /* disable PHY IRQs */
281 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 282
cd28ab6a
SH		 283 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
284 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
287
288 reg = gma_read16(hw, port, GM_RX_CTRL);
289 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
290 gma_write16(hw, port, GM_RX_CTRL, reg);
291}
292
293static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
294{
295 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 296 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 297
793b883e 298 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 299 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
300
301 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 302 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 303 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
304
305 if (hw->chip_id == CHIP_ID_YUKON_EC)
306 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
307 else
308 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
309
310 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
311 }
312
313 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
314 if (hw->copper) {
315 if (hw->chip_id == CHIP_ID_YUKON_FE) {
316 /* enable automatic crossover */
317 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
318 } else {
319 /* disable energy detect */
320 ctrl &= ~PHY_M_PC_EN_DET_MSK;
321
322 /* enable automatic crossover */
323 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
324
325 if (sky2->autoneg == AUTONEG_ENABLE &&
326 hw->chip_id == CHIP_ID_YUKON_XL) {
327 ctrl &= ~PHY_M_PC_DSC_MSK;
328 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
329 }
330 }
331 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
332 } else {
333 /* workaround for deviation #4.88 (CRC errors) */
334 /* disable Automatic Crossover */
335
336 ctrl &= ~PHY_M_PC_MDIX_MSK;
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
338
339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
340 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
342 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
343 ctrl &= ~PHY_M_MAC_MD_MSK;
344 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
349 }
cd28ab6a
SH		 350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
353 if (sky2->autoneg == AUTONEG_DISABLE)
354 ctrl &= ~PHY_CT_ANE;
355 else
356 ctrl |= PHY_CT_ANE;
357
358 ctrl |= PHY_CT_RESET;
359 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
360
361 ctrl = 0;
362 ct1000 = 0;
363 adv = PHY_AN_CSMA;
364
365 if (sky2->autoneg == AUTONEG_ENABLE) {
366 if (hw->copper) {
367 if (sky2->advertising & ADVERTISED_1000baseT_Full)
368 ct1000 |= PHY_M_1000C_AFD;
369 if (sky2->advertising & ADVERTISED_1000baseT_Half)
370 ct1000 |= PHY_M_1000C_AHD;
371 if (sky2->advertising & ADVERTISED_100baseT_Full)
372 adv |= PHY_M_AN_100_FD;
373 if (sky2->advertising & ADVERTISED_100baseT_Half)
374 adv |= PHY_M_AN_100_HD;
375 if (sky2->advertising & ADVERTISED_10baseT_Full)
376 adv |= PHY_M_AN_10_FD;
377 if (sky2->advertising & ADVERTISED_10baseT_Half)
378 adv |= PHY_M_AN_10_HD;
793b883e 379 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 380 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
381
382 /* Set Flow-control capabilities */
383 if (sky2->tx_pause && sky2->rx_pause)
793b883e 384 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 385 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 386 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 387 else if (!sky2->rx_pause && sky2->tx_pause)
388 adv |= PHY_AN_PAUSE_ASYM; /* local */
389
390 /* Restart Auto-negotiation */
391 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
392 } else {
393 /* forced speed/duplex settings */
394 ct1000 = PHY_M_1000C_MSE;
395
396 if (sky2->duplex == DUPLEX_FULL)
397 ctrl |= PHY_CT_DUP_MD;
398
399 switch (sky2->speed) {
400 case SPEED_1000:
401 ctrl |= PHY_CT_SP1000;
402 break;
403 case SPEED_100:
404 ctrl |= PHY_CT_SP100;
405 break;
406 }
407
408 ctrl |= PHY_CT_RESET;
409 }
410
411 if (hw->chip_id != CHIP_ID_YUKON_FE)
412 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
413
414 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
415 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
416
417 /* Setup Phy LED's */
418 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
419 ledover = 0;
420
421 switch (hw->chip_id) {
422 case CHIP_ID_YUKON_FE:
423 /* on 88E3082 these bits are at 11..9 (shifted left) */
424 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
425
426 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
427
428 /* delete ACT LED control bits */
429 ctrl &= ~PHY_M_FELP_LED1_MSK;
430 /* change ACT LED control to blink mode */
431 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
432 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
433 break;
434
435 case CHIP_ID_YUKON_XL:
793b883e 436 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 437
438 /* select page 3 to access LED control register */
439 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
440
441 /* set LED Function Control register */
793b883e
SH		 442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 446
447 /* set Polarity Control register */
448 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 449 (PHY_M_POLC_LS1_P_MIX(4) |
450 PHY_M_POLC_IS0_P_MIX(4) |
451 PHY_M_POLC_LOS_CTRL(2) |
452 PHY_M_POLC_INIT_CTRL(2) |
453 PHY_M_POLC_STA1_CTRL(2) |
454 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 455
456 /* restore page register */
793b883e 457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 458 break;
459
460 default:
461 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
463 /* turn off the Rx LED (LED_RX) */
464 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
465 }
466
467 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
468
469 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
470 /* turn on 100 Mbps LED (LED_LINK100) */
471 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
472 }
473
474 if (ledover)
475 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
476
d571b694 477 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 478 if (sky2->autoneg == AUTONEG_ENABLE)
479 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
480 else
481 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
482}
483
484static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
485{
486 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
487 u16 reg;
488 int i;
489 const u8 *addr = hw->dev[port]->dev_addr;
490
42eeea01
SH		 491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
492 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 493
494 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
495
793b883e 496 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 497 /* WA DEV_472 -- looks like crossed wires on port 2 */
498 /* clear GMAC 1 Control reset */
499 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
500 do {
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
502 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
503 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
504 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
505 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
506 }
507
cd28ab6a
SH		 508 if (sky2->autoneg == AUTONEG_DISABLE) {
509 reg = gma_read16(hw, port, GM_GP_CTRL);
510 reg |= GM_GPCR_AU_ALL_DIS;
511 gma_write16(hw, port, GM_GP_CTRL, reg);
512 gma_read16(hw, port, GM_GP_CTRL);
513
cd28ab6a
SH		 514 switch (sky2->speed) {
515 case SPEED_1000:
516 reg |= GM_GPCR_SPEED_1000;
517 /* fallthru */
518 case SPEED_100:
519 reg |= GM_GPCR_SPEED_100;
520 }
521
522 if (sky2->duplex == DUPLEX_FULL)
523 reg |= GM_GPCR_DUP_FULL;
524 } else
525 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
526
527 if (!sky2->tx_pause && !sky2->rx_pause) {
528 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 529 reg |=
530 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
531 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 532 /* disable Rx flow-control */
533 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
534 }
535
536 gma_write16(hw, port, GM_GP_CTRL, reg);
537
793b883e 538 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 539
91c86df5 540 down(&sky2->phy_sema);
cd28ab6a 541 sky2_phy_init(hw, port);
91c86df5 542 up(&sky2->phy_sema);
cd28ab6a
SH		 543
544 /* MIB clear */
545 reg = gma_read16(hw, port, GM_PHY_ADDR);
546 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
547
548 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 549 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 550 gma_write16(hw, port, GM_PHY_ADDR, reg);
551
552 /* transmit control */
553 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
554
555 /* receive control reg: unicast + multicast + no FCS */
556 gma_write16(hw, port, GM_RX_CTRL,
793b883e 557 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 558
559 /* transmit flow control */
560 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
561
562 /* transmit parameter */
563 gma_write16(hw, port, GM_TX_PARAM,
564 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
565 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
566 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
567 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
568
569 /* serial mode register */
570 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 571 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 572
6b1a3aef 573 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 574 reg |= GM_SMOD_JUMBO_ENA;
575
576 gma_write16(hw, port, GM_SERIAL_MODE, reg);
577
cd28ab6a
SH		 578 /* virtual address for data */
579 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
580
793b883e
SH		 581 /* physical address: used for pause frames */
582 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
583
584 /* ignore counter overflows */
cd28ab6a
SH		 585 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
587 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
588
589 /* Configure Rx MAC FIFO */
590 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 591 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 592 GMF_RX_CTRL_DEF);
cd28ab6a 593
d571b694 594 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 595 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 596
793b883e
SH		 597 /* Set threshold to 0xa (64 bytes)
598 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 599 */
600 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
601
602 /* Configure Tx MAC FIFO */
603 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
604 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 605
606 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
607 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
608 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
609 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
610 /* set Tx GMAC FIFO Almost Empty Threshold */
611 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
612 /* Disable Store & Forward mode for TX */
613 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
614 }
615 }
616
cd28ab6a
SH		 617}
618
619static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
620{
621 u32 end;
622
623 start /= 8;
624 len /= 8;
625 end = start + len - 1;
793b883e 626
cd28ab6a
SH		 627 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
628 sky2_write32(hw, RB_ADDR(q, RB_START), start);
629 sky2_write32(hw, RB_ADDR(q, RB_END), end);
630 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
631 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
632
633 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 634 u32 rxup, rxlo;
635
636 rxlo = len/2;
637 rxup = rxlo + len/4;
793b883e 638
cd28ab6a 639 /* Set thresholds on receive queue's */
793b883e
SH		 640 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
641 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 642 } else {
643 /* Enable store & forward on Tx queue's because
644 * Tx FIFO is only 1K on Yukon
645 */
646 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
647 }
648
649 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 650 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 651}
652
cd28ab6a 653/* Setup Bus Memory Interface */
af4ed7e6 654static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 655{
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
658 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 659 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 660}
661
cd28ab6a
SH		 662/* Setup prefetch unit registers. This is the interface between
663 * hardware and driver list elements
664 */
8cc048e3 665static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 666 u64 addr, u32 last)
667{
cd28ab6a
SH		 668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
671 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
672 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
673 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 674
675 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 676}
677
793b883e
SH		 678static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
679{
680 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
681
682 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
683 return le;
684}
cd28ab6a
SH		 685
686/*
d571b694 687 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 688 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 689 */
690static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
691 u16 idx, u16 *last, u16 size)
cd28ab6a 692{
cd28ab6a
SH		 693 if (is_ec_a1(hw) && idx < *last) {
694 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
695
696 if (hwget == 0) {
697 /* Start prefetching again */
793b883e 698 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 699 goto setnew;
700 }
701
793b883e 702 if (hwget == size - 1) {
cd28ab6a
SH		 703 /* set watermark to one list element */
704 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
705
706 /* set put index to first list element */
707 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 708 } else /* have hardware go to end of list */
709 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
710 size - 1);
cd28ab6a 711 } else {
793b883e 712setnew:
cd28ab6a 713 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 714 }
bea86103 715 *last = idx;
cd28ab6a
SH		 716}
717
793b883e 718
cd28ab6a
SH		 719static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
720{
721 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
722 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
723 return le;
724}
725
a018e330
SH		 726/* Return high part of DMA address (could be 32 or 64 bit) */
727static inline u32 high32(dma_addr_t a)
728{
729 return (a >> 16) >> 16;
730}
731
793b883e 732/* Build description to hardware about buffer */
734d1868 733static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 734{
735 struct sky2_rx_le *le;
734d1868
SH		 736 u32 hi = high32(map);
737 u16 len = sky2->rx_bufsize;
cd28ab6a 738
793b883e 739 if (sky2->rx_addr64 != hi) {
cd28ab6a 740 le = sky2_next_rx(sky2);
793b883e 741 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 742 le->ctrl = 0;
743 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 744 sky2->rx_addr64 = high32(map + len);
cd28ab6a 745 }
793b883e 746
cd28ab6a 747 le = sky2_next_rx(sky2);
734d1868
SH		 748 le->addr = cpu_to_le32((u32) map);
749 le->length = cpu_to_le16(len);
cd28ab6a
SH		 750 le->ctrl = 0;
751 le->opcode = OP_PACKET | HW_OWNER;
752}
753
793b883e 754
cd28ab6a
SH		 755/* Tell chip where to start receive checksum.
756 * Actually has two checksums, but set both same to avoid possible byte
757 * order problems.
758 */
793b883e 759static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 760{
761 struct sky2_rx_le *le;
762
cd28ab6a 763 le = sky2_next_rx(sky2);
793b883e 764 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 765 le->ctrl = 0;
766 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 767
793b883e
SH		 768 sky2_write32(sky2->hw,
769 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
770 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 771
772}
773
6b1a3aef
SH		 774/*
775 * The RX Stop command will not work for Yukon-2 if the BMU does not
776 * reach the end of packet and since we can't make sure that we have
777 * incoming data, we must reset the BMU while it is not doing a DMA
778 * transfer. Since it is possible that the RX path is still active,
779 * the RX RAM buffer will be stopped first, so any possible incoming
780 * data will not trigger a DMA. After the RAM buffer is stopped, the
781 * BMU is polled until any DMA in progress is ended and only then it
782 * will be reset.
783 */
784static void sky2_rx_stop(struct sky2_port *sky2)
785{
786 struct sky2_hw *hw = sky2->hw;
787 unsigned rxq = rxqaddr[sky2->port];
788 int i;
789
790 /* disable the RAM Buffer receive queue */
791 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
792
793 for (i = 0; i < 0xffff; i++)
794 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
795 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
796 goto stopped;
797
798 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
799 sky2->netdev->name);
800stopped:
801 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
802
803 /* reset the Rx prefetch unit */
804 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
805}
793b883e 806
d571b694 807/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 808static void sky2_rx_clean(struct sky2_port *sky2)
809{
810 unsigned i;
811
812 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 813 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 814 struct ring_info *re = sky2->rx_ring + i;
815
816 if (re->skb) {
793b883e 817 pci_unmap_single(sky2->hw->pdev,
734d1868 818 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 819 PCI_DMA_FROMDEVICE);
820 kfree_skb(re->skb);
821 re->skb = NULL;
822 }
823 }
824}
825
ef743d33
SH		 826/* Basic MII support */
827static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
828{
829 struct mii_ioctl_data *data = if_mii(ifr);
830 struct sky2_port *sky2 = netdev_priv(dev);
831 struct sky2_hw *hw = sky2->hw;
832 int err = -EOPNOTSUPP;
833
834 if (!netif_running(dev))
835 return -ENODEV; /* Phy still in reset */
836
837 switch(cmd) {
838 case SIOCGMIIPHY:
839 data->phy_id = PHY_ADDR_MARV;
840
841 /* fallthru */
842 case SIOCGMIIREG: {
843 u16 val = 0;
91c86df5
SH		 844
845 down(&sky2->phy_sema);
ef743d33 846 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 847 up(&sky2->phy_sema);
848
ef743d33
SH		 849 data->val_out = val;
850 break;
851 }
852
853 case SIOCSMIIREG:
854 if (!capable(CAP_NET_ADMIN))
855 return -EPERM;
856
91c86df5 857 down(&sky2->phy_sema);
ef743d33
SH		 858 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
859 data->val_in);
91c86df5 860 up(&sky2->phy_sema);
ef743d33
SH		 861 break;
862 }
863 return err;
864}
865
d1f13708
SH		 866#ifdef SKY2_VLAN_TAG_USED
867static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
868{
869 struct sky2_port *sky2 = netdev_priv(dev);
870 struct sky2_hw *hw = sky2->hw;
871 u16 port = sky2->port;
d1f13708 872
f2e46561 873 spin_lock(&sky2->tx_lock);
d1f13708
SH		 874
875 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
876 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
877 sky2->vlgrp = grp;
878
f2e46561 879 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 880}
881
882static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
883{
884 struct sky2_port *sky2 = netdev_priv(dev);
885 struct sky2_hw *hw = sky2->hw;
886 u16 port = sky2->port;
d1f13708 887
f2e46561 888 spin_lock(&sky2->tx_lock);
d1f13708
SH		 889
890 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
891 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
892 if (sky2->vlgrp)
893 sky2->vlgrp->vlan_devices[vid] = NULL;
894
f2e46561 895 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 896}
897#endif
898
cd28ab6a
SH		 899/*
900 * Allocate and setup receiver buffer pool.
901 * In case of 64 bit dma, there are 2X as many list elements
902 * available as ring entries
903 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 904 *
905 * It appears the hardware has a bug in the FIFO logic that
906 * cause it to hang if the FIFO gets overrun and the receive buffer
907 * is not aligned. This means we can't use skb_reserve to align
908 * the IP header.
cd28ab6a 909 */
6b1a3aef 910static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 911{
6b1a3aef 912 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 913 unsigned rxq = rxqaddr[sky2->port];
914 int i;
cd28ab6a 915
6b1a3aef 916 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 917 sky2_qset(hw, rxq);
6b1a3aef
SH		 918 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
919
920 rx_set_checksum(sky2);
793b883e 921 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 922 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 923
734d1868 924 re->skb = dev_alloc_skb(sky2->rx_bufsize);
cd28ab6a
SH		 925 if (!re->skb)
926 goto nomem;
927
6b1a3aef 928 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 929 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
930 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 931 }
932
6b1a3aef
SH		 933 /* Tell chip about available buffers */
934 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
935 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 936 return 0;
937nomem:
938 sky2_rx_clean(sky2);
939 return -ENOMEM;
940}
941
942/* Bring up network interface. */
943static int sky2_up(struct net_device *dev)
944{
945 struct sky2_port *sky2 = netdev_priv(dev);
946 struct sky2_hw *hw = sky2->hw;
947 unsigned port = sky2->port;
948 u32 ramsize, rxspace;
949 int err = -ENOMEM;
950
951 if (netif_msg_ifup(sky2))
952 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
953
954 /* must be power of 2 */
955 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 956 TX_RING_SIZE *
957 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 958 &sky2->tx_le_map);
959 if (!sky2->tx_le)
960 goto err_out;
961
6cdbbdf3 962 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 963 GFP_KERNEL);
964 if (!sky2->tx_ring)
965 goto err_out;
966 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 967
968 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
969 &sky2->rx_le_map);
970 if (!sky2->rx_le)
971 goto err_out;
972 memset(sky2->rx_le, 0, RX_LE_BYTES);
973
6cdbbdf3 974 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 975 GFP_KERNEL);
976 if (!sky2->rx_ring)
977 goto err_out;
978
979 sky2_mac_init(hw, port);
980
981 /* Configure RAM buffers */
982 if (hw->chip_id == CHIP_ID_YUKON_FE ||
983 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
984 ramsize = 4096;
985 else {
793b883e
SH		 986 u8 e0 = sky2_read8(hw, B2_E_0);
987 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 988 }
989
990 /* 2/3 for Rx */
991 rxspace = (2 * ramsize) / 3;
992 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
993 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
994
793b883e
SH		 995 /* Make sure SyncQ is disabled */
996 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
997 RB_RST_SET);
998
af4ed7e6 999 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 1000 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1001 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1002
1003
6b1a3aef
SH		 1004 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1005 TX_RING_SIZE - 1);
cd28ab6a 1006
6b1a3aef 1007 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1008 if (err)
1009 goto err_out;
1010
cd28ab6a
SH		 1011 /* Enable interrupts from phy/mac for port */
1012 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1013 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1014 return 0;
1015
1016err_out:
1017 if (sky2->rx_le)
1018 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1019 sky2->rx_le, sky2->rx_le_map);
1020 if (sky2->tx_le)
1021 pci_free_consistent(hw->pdev,
1022 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1023 sky2->tx_le, sky2->tx_le_map);
1024 if (sky2->tx_ring)
1025 kfree(sky2->tx_ring);
1026 if (sky2->rx_ring)
1027 kfree(sky2->rx_ring);
1028
1029 return err;
1030}
1031
793b883e
SH		 1032/* Modular subtraction in ring */
1033static inline int tx_dist(unsigned tail, unsigned head)
1034{
129372d0 1035 return (head - tail) % TX_RING_SIZE;
793b883e 1036}
cd28ab6a 1037
793b883e
SH		 1038/* Number of list elements available for next tx */
1039static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1040{
793b883e 1041 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1042}
1043
793b883e
SH		 1044/* Estimate of number of transmit list elements required */
1045static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1046{
793b883e
SH		 1047 unsigned count;
1048
1049 count = sizeof(dma_addr_t) / sizeof(u32);
1050 count += skb_shinfo(skb)->nr_frags * count;
1051
1052 if (skb_shinfo(skb)->tso_size)
1053 ++count;
1054
0e3ff6aa 1055 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1056 ++count;
1057
1058 return count;
cd28ab6a
SH		 1059}
1060
793b883e
SH		 1061/*
1062 * Put one packet in ring for transmit.
1063 * A single packet can generate multiple list elements, and
1064 * the number of ring elements will probably be less than the number
1065 * of list elements used.
f2e46561
SH		 1066 *
1067 * No BH disabling for tx_lock here (like tg3)
793b883e 1068 */
cd28ab6a
SH		 1069static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1070{
1071 struct sky2_port *sky2 = netdev_priv(dev);
1072 struct sky2_hw *hw = sky2->hw;
d1f13708 1073 struct sky2_tx_le *le = NULL;
6cdbbdf3 1074 struct tx_ring_info *re;
cd28ab6a
SH		 1075 unsigned i, len;
1076 dma_addr_t mapping;
1077 u32 addr64;
1078 u16 mss;
1079 u8 ctrl;
1080
f2e46561 1081 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1082 return NETDEV_TX_LOCKED;
1083
793b883e 1084 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1085 /* There is a known but harmless race with lockless tx
1086 * and netif_stop_queue.
1087 */
1088 if (!netif_queue_stopped(dev)) {
1089 netif_stop_queue(dev);
1090 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1091 dev->name);
1092 }
f2e46561 1093 spin_unlock(&sky2->tx_lock);
cd28ab6a 1094
cd28ab6a
SH		 1095 return NETDEV_TX_BUSY;
1096 }
1097
793b883e 1098 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1099 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1100 dev->name, sky2->tx_prod, skb->len);
1101
cd28ab6a
SH		 1102 len = skb_headlen(skb);
1103 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1104 addr64 = high32(mapping);
793b883e
SH		 1105
1106 re = sky2->tx_ring + sky2->tx_prod;
1107
a018e330
SH		 1108 /* Send high bits if changed or crosses boundary */
1109 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1110 le = get_tx_le(sky2);
1111 le->tx.addr = cpu_to_le32(addr64);
1112 le->ctrl = 0;
1113 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1114 sky2->tx_addr64 = high32(mapping + len);
793b883e 1115 }
cd28ab6a
SH		 1116
1117 /* Check for TCP Segmentation Offload */
1118 mss = skb_shinfo(skb)->tso_size;
793b883e 1119 if (mss != 0) {
cd28ab6a
SH		 1120 /* just drop the packet if non-linear expansion fails */
1121 if (skb_header_cloned(skb) &&
1122 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1123 dev_kfree_skb_any(skb);
1124 goto out_unlock;
cd28ab6a
SH		 1125 }
1126
1127 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1128 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1129 mss += ETH_HLEN;
793b883e 1130 }
cd28ab6a 1131
793b883e 1132 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1133 le = get_tx_le(sky2);
1134 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1135 le->tx.tso.rsvd = 0;
cd28ab6a 1136 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1137 le->ctrl = 0;
793b883e 1138 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1139 }
1140
cd28ab6a 1141 ctrl = 0;
d1f13708
SH		 1142#ifdef SKY2_VLAN_TAG_USED
1143 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1144 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1145 if (!le) {
1146 le = get_tx_le(sky2);
1147 le->tx.addr = 0;
1148 le->opcode = OP_VLAN|HW_OWNER;
1149 le->ctrl = 0;
1150 } else
1151 le->opcode |= OP_VLAN;
1152 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1153 ctrl |= INS_VLAN;
1154 }
1155#endif
1156
1157 /* Handle TCP checksum offload */
cd28ab6a 1158 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1159 u16 hdr = skb->h.raw - skb->data;
1160 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1161
1162 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1163 if (skb->nh.iph->protocol == IPPROTO_UDP)
1164 ctrl |= UDPTCP;
1165
1166 le = get_tx_le(sky2);
1167 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1168 le->tx.csum.offset = cpu_to_le16(offset);
1169 le->length = 0; /* initial checksum value */
cd28ab6a 1170 le->ctrl = 1; /* one packet */
793b883e 1171 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1172 }
1173
1174 le = get_tx_le(sky2);
1175 le->tx.addr = cpu_to_le32((u32) mapping);
1176 le->length = cpu_to_le16(len);
1177 le->ctrl = ctrl;
793b883e 1178 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1179
793b883e 1180 /* Record the transmit mapping info */
cd28ab6a 1181 re->skb = skb;
6cdbbdf3 1182 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1183
1184 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1185 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1186 struct tx_ring_info *fre;
cd28ab6a
SH		 1187
1188 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1189 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1190 addr64 = (mapping >> 16) >> 16;
1191 if (addr64 != sky2->tx_addr64) {
1192 le = get_tx_le(sky2);
1193 le->tx.addr = cpu_to_le32(addr64);
1194 le->ctrl = 0;
1195 le->opcode = OP_ADDR64 | HW_OWNER;
1196 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1197 }
1198
1199 le = get_tx_le(sky2);
1200 le->tx.addr = cpu_to_le32((u32) mapping);
1201 le->length = cpu_to_le16(frag->size);
1202 le->ctrl = ctrl;
793b883e 1203 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1204
793b883e
SH		 1205 fre = sky2->tx_ring
1206 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
6cdbbdf3 1207 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1208 }
6cdbbdf3 1209
793b883e 1210 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1211 le->ctrl |= EOP;
1212
724bca3c 1213 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1214 &sky2->tx_last_put, TX_RING_SIZE);
1215
0e3ff6aa 1216 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
cd28ab6a 1217 netif_stop_queue(dev);
793b883e
SH		 1218
1219out_unlock:
1220 mmiowb();
f2e46561 1221 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1222
1223 dev->trans_start = jiffies;
1224 return NETDEV_TX_OK;
1225}
1226
cd28ab6a 1227/*
793b883e
SH		 1228 * Free ring elements from starting at tx_cons until "done"
1229 *
1230 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1231 * buffers; these are deferred until completion.
cd28ab6a 1232 */
d11c13e7 1233static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1234{
d11c13e7 1235 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1236 struct pci_dev *pdev = sky2->hw->pdev;
1237 u16 nxt, put;
793b883e 1238 unsigned i;
cd28ab6a 1239
0e3ff6aa 1240 BUG_ON(done >= TX_RING_SIZE);
2224795d 1241
d11c13e7 1242 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1243 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1244 dev->name, done);
cd28ab6a 1245
af2a58ac
SH		 1246 for (put = sky2->tx_cons; put != done; put = nxt) {
1247 struct tx_ring_info *re = sky2->tx_ring + put;
1248 struct sk_buff *skb = re->skb;
cd28ab6a 1249
af2a58ac
SH		 1250 nxt = re->idx;
1251 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1252 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1253
793b883e 1254 /* Check for partial status */
af2a58ac
SH		 1255 if (tx_dist(put, done) < tx_dist(put, nxt))
1256 break;
793b883e
SH		 1257
1258 skb = re->skb;
af2a58ac 1259 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1260 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1261
1262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1263 struct tx_ring_info *fre;
af2a58ac
SH		 1264 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1265 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1266 skb_shinfo(skb)->frags[i].size,
734d1868 1267 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1268 }
1269
cd28ab6a 1270 dev_kfree_skb_any(skb);
793b883e 1271 }
793b883e 1272
af2a58ac
SH		 1273 spin_lock(&sky2->tx_lock);
1274 sky2->tx_cons = put;
793b883e 1275 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1276 netif_wake_queue(dev);
1277 spin_unlock(&sky2->tx_lock);
1278}
1279
1280/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1281static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1282{
d11c13e7 1283 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1284}
1285
1286/* Network shutdown */
1287static int sky2_down(struct net_device *dev)
1288{
1289 struct sky2_port *sky2 = netdev_priv(dev);
1290 struct sky2_hw *hw = sky2->hw;
1291 unsigned port = sky2->port;
1292 u16 ctrl;
cd28ab6a
SH		 1293
1294 if (netif_msg_ifdown(sky2))
1295 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1296
018d1c66 1297 /* Stop more packets from being queued */
cd28ab6a
SH		 1298 netif_stop_queue(dev);
1299
018d1c66
SH		 1300 /* Disable port IRQ */
1301 local_irq_disable();
1302 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1303 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1304 local_irq_enable();
1305
91c86df5 1306 flush_scheduled_work();
018d1c66 1307
793b883e
SH		 1308 sky2_phy_reset(hw, port);
1309
cd28ab6a
SH		 1310 /* Stop transmitter */
1311 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1312 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1313
1314 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1315 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1316
1317 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1318 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1319 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1320
1321 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1322
1323 /* Workaround shared GMAC reset */
793b883e
SH		 1324 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1325 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1326 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1327
1328 /* Disable Force Sync bit and Enable Alloc bit */
1329 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1330 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1331
1332 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1333 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1334 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1335
1336 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1337 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1338 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1339
1340 /* Reset the Tx prefetch units */
1341 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1342 PREF_UNIT_RST_SET);
1343
1344 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1345
6b1a3aef 1346 sky2_rx_stop(sky2);
cd28ab6a
SH		 1347
1348 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1349 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1350
d571b694 1351 /* turn off LED's */
cd28ab6a
SH		 1352 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1353
018d1c66
SH		 1354 synchronize_irq(hw->pdev->irq);
1355
cd28ab6a
SH		 1356 sky2_tx_clean(sky2);
1357 sky2_rx_clean(sky2);
1358
1359 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1360 sky2->rx_le, sky2->rx_le_map);
1361 kfree(sky2->rx_ring);
1362
1363 pci_free_consistent(hw->pdev,
1364 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1365 sky2->tx_le, sky2->tx_le_map);
1366 kfree(sky2->tx_ring);
1367
1368 return 0;
1369}
1370
1371static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1372{
793b883e
SH		 1373 if (!hw->copper)
1374 return SPEED_1000;
1375
cd28ab6a
SH		 1376 if (hw->chip_id == CHIP_ID_YUKON_FE)
1377 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1378
1379 switch (aux & PHY_M_PS_SPEED_MSK) {
1380 case PHY_M_PS_SPEED_1000:
1381 return SPEED_1000;
1382 case PHY_M_PS_SPEED_100:
1383 return SPEED_100;
1384 default:
1385 return SPEED_10;
1386 }
1387}
1388
1389static void sky2_link_up(struct sky2_port *sky2)
1390{
1391 struct sky2_hw *hw = sky2->hw;
1392 unsigned port = sky2->port;
1393 u16 reg;
1394
1395 /* Enable Transmit FIFO Underrun */
793b883e 1396 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1397
1398 reg = gma_read16(hw, port, GM_GP_CTRL);
1399 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1400 reg |= GM_GPCR_DUP_FULL;
1401
cd28ab6a
SH		 1402 /* enable Rx/Tx */
1403 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1404 gma_write16(hw, port, GM_GP_CTRL, reg);
1405 gma_read16(hw, port, GM_GP_CTRL);
1406
1407 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1408
1409 netif_carrier_on(sky2->netdev);
1410 netif_wake_queue(sky2->netdev);
1411
1412 /* Turn on link LED */
793b883e 1413 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1414 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1415
793b883e
SH		 1416 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1417 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1418
1419 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1420 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1421 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1422 SPEED_10 ? 7 : 0) |
1423 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1424 SPEED_100 ? 7 : 0) |
1425 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1426 SPEED_1000 ? 7 : 0));
1427 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1428 }
1429
cd28ab6a
SH		 1430 if (netif_msg_link(sky2))
1431 printk(KERN_INFO PFX
d571b694 1432 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1433 sky2->netdev->name, sky2->speed,
1434 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1435 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1436 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1437}
1438
1439static void sky2_link_down(struct sky2_port *sky2)
1440{
1441 struct sky2_hw *hw = sky2->hw;
1442 unsigned port = sky2->port;
1443 u16 reg;
1444
1445 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1446
1447 reg = gma_read16(hw, port, GM_GP_CTRL);
1448 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1449 gma_write16(hw, port, GM_GP_CTRL, reg);
1450 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1451
1452 if (sky2->rx_pause && !sky2->tx_pause) {
1453 /* restore Asymmetric Pause bit */
1454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1455 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1456 | PHY_M_AN_ASP);
cd28ab6a
SH		 1457 }
1458
1459 sky2_phy_reset(hw, port);
1460
1461 netif_carrier_off(sky2->netdev);
1462 netif_stop_queue(sky2->netdev);
1463
1464 /* Turn on link LED */
1465 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1466
1467 if (netif_msg_link(sky2))
1468 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1469 sky2_phy_init(hw, port);
1470}
1471
793b883e
SH		 1472static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1473{
1474 struct sky2_hw *hw = sky2->hw;
1475 unsigned port = sky2->port;
1476 u16 lpa;
1477
1478 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1479
1480 if (lpa & PHY_M_AN_RF) {
1481 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1482 return -1;
1483 }
1484
1485 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1486 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1487 printk(KERN_ERR PFX "%s: master/slave fault",
1488 sky2->netdev->name);
1489 return -1;
1490 }
1491
1492 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1493 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1494 sky2->netdev->name);
1495 return -1;
1496 }
1497
1498 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1499
1500 sky2->speed = sky2_phy_speed(hw, aux);
1501
1502 /* Pause bits are offset (9..8) */
1503 if (hw->chip_id == CHIP_ID_YUKON_XL)
1504 aux >>= 6;
1505
1506 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1507 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1508
1509 if ((sky2->tx_pause || sky2->rx_pause)
1510 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1511 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1512 else
1513 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1514
1515 return 0;
1516}
cd28ab6a
SH		 1517
1518/*
91c86df5 1519 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1520 * because accessing phy registers requires spin wait which might
1521 * cause excess interrupt latency.
1522 */
91c86df5 1523static void sky2_phy_task(void *arg)
cd28ab6a 1524{
91c86df5 1525 struct sky2_port *sky2 = arg;
cd28ab6a 1526 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1527 u16 istatus, phystat;
1528
91c86df5 1529 down(&sky2->phy_sema);
793b883e
SH		 1530 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1531 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1532
1533 if (netif_msg_intr(sky2))
1534 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1535 sky2->netdev->name, istatus, phystat);
1536
1537 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1538 if (sky2_autoneg_done(sky2, phystat) == 0)
1539 sky2_link_up(sky2);
1540 goto out;
1541 }
cd28ab6a 1542
793b883e
SH		 1543 if (istatus & PHY_M_IS_LSP_CHANGE)
1544 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1545
793b883e
SH		 1546 if (istatus & PHY_M_IS_DUP_CHANGE)
1547 sky2->duplex =
1548 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1549
793b883e
SH		 1550 if (istatus & PHY_M_IS_LST_CHANGE) {
1551 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1552 sky2_link_up(sky2);
793b883e
SH		 1553 else
1554 sky2_link_down(sky2);
cd28ab6a 1555 }
793b883e 1556out:
91c86df5 1557 up(&sky2->phy_sema);
cd28ab6a
SH		 1558
1559 local_irq_disable();
793b883e 1560 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1561 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1562 local_irq_enable();
1563}
1564
1565static void sky2_tx_timeout(struct net_device *dev)
1566{
1567 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1568 struct sky2_hw *hw = sky2->hw;
1569 unsigned txq = txqaddr[sky2->port];
cd28ab6a
SH		 1570
1571 if (netif_msg_timer(sky2))
1572 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1573
8cc048e3
SH		 1574 netif_stop_queue(dev);
1575
1576 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1577 sky2_read32(hw, Q_ADDR(txq, Q_CSR));
1578
1579 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
cd28ab6a
SH		 1580
1581 sky2_tx_clean(sky2);
8cc048e3
SH		 1582
1583 sky2_qset(hw, txq);
1584 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1585
1586 netif_wake_queue(dev);
cd28ab6a
SH		 1587}
1588
734d1868
SH		 1589
1590#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1591/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1592static inline unsigned sky2_buf_size(int mtu)
1593{
1594 return roundup(mtu + ETH_HLEN + 4, 8);
1595}
1596
cd28ab6a
SH		 1597static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1598{
6b1a3aef
SH		 1599 struct sky2_port *sky2 = netdev_priv(dev);
1600 struct sky2_hw *hw = sky2->hw;
1601 int err;
1602 u16 ctl, mode;
cd28ab6a
SH		 1603
1604 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1605 return -EINVAL;
1606
5a5b1ea0
SH		 1607 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1608 return -EINVAL;
1609
6b1a3aef
SH		 1610 if (!netif_running(dev)) {
1611 dev->mtu = new_mtu;
1612 return 0;
1613 }
1614
6b1a3aef
SH		 1615 sky2_write32(hw, B0_IMSK, 0);
1616
018d1c66
SH		 1617 dev->trans_start = jiffies; /* prevent tx timeout */
1618 netif_stop_queue(dev);
1619 netif_poll_disable(hw->dev[0]);
1620
6b1a3aef
SH		 1621 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1622 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1623 sky2_rx_stop(sky2);
1624 sky2_rx_clean(sky2);
cd28ab6a
SH		 1625
1626 dev->mtu = new_mtu;
734d1868 1627 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1628 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1629 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1630
1631 if (dev->mtu > ETH_DATA_LEN)
1632 mode |= GM_SMOD_JUMBO_ENA;
1633
1634 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1635
6b1a3aef 1636 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1637
6b1a3aef
SH		 1638 err = sky2_rx_start(sky2);
1639 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1640
018d1c66
SH		 1641 netif_poll_disable(hw->dev[0]);
1642 netif_wake_queue(dev);
6b1a3aef 1643 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1644
cd28ab6a
SH		 1645 return err;
1646}
1647
1648/*
1649 * Receive one packet.
1650 * For small packets or errors, just reuse existing skb.
d571b694 1651 * For larger packets, get new buffer.
cd28ab6a 1652 */
d11c13e7 1653static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1654 u16 length, u32 status)
1655{
cd28ab6a 1656 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1657 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1658
1659 if (unlikely(netif_msg_rx_status(sky2)))
1660 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1661 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1662
793b883e 1663 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1664 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1665
42eeea01 1666 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1667 goto error;
1668
42eeea01
SH		 1669 if (!(status & GMR_FS_RX_OK))
1670 goto resubmit;
1671
bdb5c58e 1672 if (length < copybreak) {
79e57d32
SH		 1673 skb = alloc_skb(length + 2, GFP_ATOMIC);
1674 if (!skb)
793b883e
SH		 1675 goto resubmit;
1676
79e57d32 1677 skb_reserve(skb, 2);
793b883e
SH		 1678 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1679 length, PCI_DMA_FROMDEVICE);
79e57d32 1680 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1681 skb->ip_summed = re->skb->ip_summed;
1682 skb->csum = re->skb->csum;
793b883e
SH		 1683 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1684 length, PCI_DMA_FROMDEVICE);
793b883e 1685 } else {
79e57d32
SH		 1686 struct sk_buff *nskb;
1687
734d1868 1688 nskb = dev_alloc_skb(sky2->rx_bufsize);
793b883e
SH		 1689 if (!nskb)
1690 goto resubmit;
cd28ab6a 1691
793b883e 1692 skb = re->skb;
79e57d32 1693 re->skb = nskb;
793b883e 1694 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1695 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1696 prefetch(skb->data);
cd28ab6a 1697
793b883e 1698 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1699 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1700 }
cd28ab6a 1701
79e57d32 1702 skb_put(skb, length);
793b883e 1703resubmit:
d11c13e7 1704 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1705 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1706
bea86103
SH		 1707 /* Tell receiver about new buffers. */
1708 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1709 &sky2->rx_last_put, RX_LE_SIZE);
1710
cd28ab6a
SH		 1711 return skb;
1712
1713error:
1714 if (netif_msg_rx_err(sky2))
1715 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1716 sky2->netdev->name, status, length);
793b883e
SH		 1717
1718 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1719 sky2->net_stats.rx_length_errors++;
1720 if (status & GMR_FS_FRAGMENT)
1721 sky2->net_stats.rx_frame_errors++;
1722 if (status & GMR_FS_CRC_ERR)
1723 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1724 if (status & GMR_FS_RX_FF_OV)
1725 sky2->net_stats.rx_fifo_errors++;
79e57d32 1726
793b883e 1727 goto resubmit;
cd28ab6a
SH		 1728}
1729
2224795d
SH		 1730/*
1731 * Check for transmit complete
793b883e 1732 */
13b97b74 1733#define TX_NO_STATUS 0xffff
2224795d 1734
13b97b74
SH		 1735static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1736{
1737 if (last != TX_NO_STATUS) {
1738 struct net_device *dev = hw->dev[port];
1739 if (dev && netif_running(dev)) {
1740 struct sky2_port *sky2 = netdev_priv(dev);
1741 sky2_tx_complete(sky2, last);
1742 }
2224795d 1743 }
cd28ab6a
SH		 1744}
1745
1746/*
cd28ab6a
SH		 1747 * Both ports share the same status interrupt, therefore there is only
1748 * one poll routine.
cd28ab6a 1749 */
d11c13e7 1750static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1751{
d11c13e7
SH		 1752 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1753 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1754 unsigned int work_done = 0;
793b883e 1755 u16 hwidx;
13b97b74 1756 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
cd28ab6a 1757
793b883e 1758 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1759 BUG_ON(hwidx >= STATUS_RING_SIZE);
af2a58ac 1760 rmb();
bea86103 1761
13210ce5
SH		 1762 while (hwidx != hw->st_idx) {
1763 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1764 struct net_device *dev;
d11c13e7 1765 struct sky2_port *sky2;
cd28ab6a 1766 struct sk_buff *skb;
cd28ab6a
SH		 1767 u32 status;
1768 u16 length;
13210ce5 1769 u8 op;
cd28ab6a 1770
13210ce5 1771 le = hw->st_le + hw->st_idx;
bea86103 1772 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1773 prefetch(hw->st_le + hw->st_idx);
bea86103 1774
13210ce5
SH		 1775 BUG_ON(le->link >= 2);
1776 dev = hw->dev[le->link];
1777 if (dev == NULL || !netif_running(dev))
1778 continue;
1779
1780 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1781 status = le32_to_cpu(le->status);
1782 length = le16_to_cpu(le->length);
13210ce5
SH		 1783 op = le->opcode & ~HW_OWNER;
1784 le->opcode = 0;
cd28ab6a 1785
13210ce5 1786 switch (op) {
cd28ab6a 1787 case OP_RXSTAT:
d11c13e7 1788 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1789 if (!skb)
1790 break;
13210ce5
SH		 1791
1792 skb->dev = dev;
1793 skb->protocol = eth_type_trans(skb, dev);
1794 dev->last_rx = jiffies;
1795
d1f13708
SH		 1796#ifdef SKY2_VLAN_TAG_USED
1797 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1798 vlan_hwaccel_receive_skb(skb,
1799 sky2->vlgrp,
1800 be16_to_cpu(sky2->rx_tag));
1801 } else
1802#endif
cd28ab6a 1803 netif_receive_skb(skb);
13210ce5
SH		 1804
1805 if (++work_done >= to_do)
1806 goto exit_loop;
cd28ab6a
SH		 1807 break;
1808
d1f13708
SH		 1809#ifdef SKY2_VLAN_TAG_USED
1810 case OP_RXVLAN:
1811 sky2->rx_tag = length;
1812 break;
1813
1814 case OP_RXCHKSVLAN:
1815 sky2->rx_tag = length;
1816 /* fall through */
1817#endif
cd28ab6a 1818 case OP_RXCHKS:
d11c13e7
SH		 1819 skb = sky2->rx_ring[sky2->rx_next].skb;
1820 skb->ip_summed = CHECKSUM_HW;
1821 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1822 break;
1823
1824 case OP_TXINDEXLE:
13b97b74
SH		 1825 /* TX index reports status for both ports */
1826 tx_done[0] = status & 0xffff;
1827 tx_done[1] = ((status >> 24) & 0xff)
1828 | (u16)(length & 0xf) << 8;
cd28ab6a
SH		 1829 break;
1830
cd28ab6a
SH		 1831 default:
1832 if (net_ratelimit())
793b883e 1833 printk(KERN_WARNING PFX
13210ce5 1834 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1835 break;
1836 }
13210ce5 1837 }
cd28ab6a 1838
13210ce5 1839exit_loop:
3e4b32e1 1840 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e
SH		 1841 mmiowb();
1842
13b97b74
SH		 1843 sky2_tx_check(hw, 0, tx_done[0]);
1844 sky2_tx_check(hw, 1, tx_done[1]);
1845
3e4b32e1 1846 if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
13b97b74 1847 /* need to restart TX timer */
cd28ab6a
SH		 1848 if (is_ec_a1(hw)) {
1849 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1850 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1851 }
1852
bea86103 1853 netif_rx_complete(dev0);
cd28ab6a
SH		 1854 hw->intr_mask |= Y2_IS_STAT_BMU;
1855 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1856 mmiowb();
1857 return 0;
1858 } else {
1859 *budget -= work_done;
1860 dev0->quota -= work_done;
1861 return 1;
cd28ab6a 1862 }
cd28ab6a
SH		 1863}
1864
1865static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1866{
1867 struct net_device *dev = hw->dev[port];
1868
1869 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1870 dev->name, status);
1871
1872 if (status & Y2_IS_PAR_RD1) {
1873 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1874 dev->name);
1875 /* Clear IRQ */
1876 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1877 }
1878
1879 if (status & Y2_IS_PAR_WR1) {
1880 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1881 dev->name);
1882
1883 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1884 }
1885
1886 if (status & Y2_IS_PAR_MAC1) {
1887 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1888 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1889 }
1890
1891 if (status & Y2_IS_PAR_RX1) {
1892 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1893 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1894 }
1895
1896 if (status & Y2_IS_TCP_TXA1) {
1897 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1898 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1899 }
1900}
1901
1902static void sky2_hw_intr(struct sky2_hw *hw)
1903{
1904 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1905
793b883e 1906 if (status & Y2_IS_TIST_OV)
cd28ab6a 1907 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1908
1909 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1910 u16 pci_err;
1911
1912 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1913 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1914 pci_name(hw->pdev), pci_err);
1915
1916 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1917 pci_write_config_word(hw->pdev, PCI_STATUS,
1918 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1919 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1920 }
1921
1922 if (status & Y2_IS_PCI_EXP) {
d571b694 1923 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1924 u32 pex_err;
1925
1926 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1927
cd28ab6a
SH		 1928 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1929 pci_name(hw->pdev), pex_err);
1930
1931 /* clear the interrupt */
1932 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1933 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1934 0xffffffffUL);
cd28ab6a
SH		 1935 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1936
1937 if (pex_err & PEX_FATAL_ERRORS) {
1938 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1939 hwmsk &= ~Y2_IS_PCI_EXP;
1940 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1941 }
1942 }
1943
1944 if (status & Y2_HWE_L1_MASK)
1945 sky2_hw_error(hw, 0, status);
1946 status >>= 8;
1947 if (status & Y2_HWE_L1_MASK)
1948 sky2_hw_error(hw, 1, status);
1949}
1950
1951static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1952{
1953 struct net_device *dev = hw->dev[port];
1954 struct sky2_port *sky2 = netdev_priv(dev);
1955 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1956
1957 if (netif_msg_intr(sky2))
1958 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1959 dev->name, status);
1960
1961 if (status & GM_IS_RX_FF_OR) {
1962 ++sky2->net_stats.rx_fifo_errors;
1963 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1964 }
1965
1966 if (status & GM_IS_TX_FF_UR) {
1967 ++sky2->net_stats.tx_fifo_errors;
1968 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1969 }
cd28ab6a
SH		 1970}
1971
1972static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1973{
1974 struct net_device *dev = hw->dev[port];
1975 struct sky2_port *sky2 = netdev_priv(dev);
1976
1977 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1978 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 1979 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 1980}
1981
1982static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1983{
1984 struct sky2_hw *hw = dev_id;
bea86103 1985 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 1986 u32 status;
1987
1988 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1989 if (status == 0 || status == ~0)
cd28ab6a
SH		 1990 return IRQ_NONE;
1991
1992 if (status & Y2_IS_HW_ERR)
1993 sky2_hw_intr(hw);
1994
793b883e 1995 /* Do NAPI for Rx and Tx status */
bea86103 1996 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 1997 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1998 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 1999
0a122576
SH		 2000 if (likely(__netif_rx_schedule_prep(dev0))) {
2001 prefetch(&hw->st_le[hw->st_idx]);
bea86103 2002 __netif_rx_schedule(dev0);
0a122576 2003 }
cd28ab6a
SH		 2004 }
2005
793b883e 2006 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 2007 sky2_phy_intr(hw, 0);
2008
2009 if (status & Y2_IS_IRQ_PHY2)
2010 sky2_phy_intr(hw, 1);
2011
2012 if (status & Y2_IS_IRQ_MAC1)
2013 sky2_mac_intr(hw, 0);
2014
2015 if (status & Y2_IS_IRQ_MAC2)
2016 sky2_mac_intr(hw, 1);
2017
cd28ab6a 2018 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2019
2020 sky2_read32(hw, B0_IMSK);
2021
cd28ab6a
SH		 2022 return IRQ_HANDLED;
2023}
2024
2025#ifdef CONFIG_NET_POLL_CONTROLLER
2026static void sky2_netpoll(struct net_device *dev)
2027{
2028 struct sky2_port *sky2 = netdev_priv(dev);
2029
793b883e 2030 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2031}
2032#endif
2033
2034/* Chip internal frequency for clock calculations */
fb17358f 2035static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2036{
793b883e 2037 switch (hw->chip_id) {
cd28ab6a 2038 case CHIP_ID_YUKON_EC:
5a5b1ea0 2039 case CHIP_ID_YUKON_EC_U:
fb17358f 2040 return 125; /* 125 Mhz */
cd28ab6a 2041 case CHIP_ID_YUKON_FE:
fb17358f 2042 return 100; /* 100 Mhz */
793b883e 2043 default: /* YUKON_XL */
fb17358f 2044 return 156; /* 156 Mhz */
cd28ab6a
SH		 2045 }
2046}
2047
fb17358f 2048static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2049{
fb17358f 2050 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2051}
2052
fb17358f 2053static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2054{
fb17358f 2055 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2056}
2057
fb17358f 2058
cd28ab6a
SH		 2059static int sky2_reset(struct sky2_hw *hw)
2060{
5afa0a9c 2061 u32 ctst;
cd28ab6a
SH		 2062 u16 status;
2063 u8 t8, pmd_type;
2064 int i;
2065
2066 ctst = sky2_read32(hw, B0_CTST);
2067
2068 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2069 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2070 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2071 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2072 pci_name(hw->pdev), hw->chip_id);
2073 return -EOPNOTSUPP;
2074 }
2075
793b883e
SH		 2076 /* ring for status responses */
2077 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2078 &hw->st_dma);
2079 if (!hw->st_le)
2080 return -ENOMEM;
2081
cd28ab6a
SH		 2082 /* disable ASF */
2083 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2084 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2085 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2086 }
2087
2088 /* do a SW reset */
2089 sky2_write8(hw, B0_CTST, CS_RST_SET);
2090 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2091
2092 /* clear PCI errors, if any */
793b883e 2093 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2094 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2095 pci_write_config_word(hw->pdev, PCI_STATUS,
2096 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2097
2098 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2099
2100 /* clear any PEX errors */
2101 if (is_pciex(hw)) {
793b883e
SH		 2102 u16 lstat;
2103 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2104 0xffffffffUL);
2105 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2106 }
2107
2108 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2109 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2110
2111 hw->ports = 1;
2112 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2113 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2114 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2115 ++hw->ports;
2116 }
2117 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2118
5afa0a9c 2119 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2120
2121 for (i = 0; i < hw->ports; i++) {
2122 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2123 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2124 }
2125
2126 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2127
793b883e
SH		 2128 /* Clear I2C IRQ noise */
2129 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2130
2131 /* turn off hardware timer (unused) */
2132 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2133 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2134
cd28ab6a
SH		 2135 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2136
69634ee7
SH		 2137 /* Turn off descriptor polling */
2138 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2139
2140 /* Turn off receive timestamp */
2141 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2142 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2143
2144 /* enable the Tx Arbiters */
2145 for (i = 0; i < hw->ports; i++)
2146 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2147
2148 /* Initialize ram interface */
2149 for (i = 0; i < hw->ports; i++) {
793b883e 2150 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2151
2152 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2153 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2154 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2155 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2156 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2157 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2158 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2159 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2160 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2161 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2162 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2163 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2164 }
2165
cd28ab6a
SH		 2166 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2167
cd28ab6a
SH		 2168 for (i = 0; i < hw->ports; i++)
2169 sky2_phy_reset(hw, i);
cd28ab6a 2170
cd28ab6a
SH		 2171 memset(hw->st_le, 0, STATUS_LE_BYTES);
2172 hw->st_idx = 0;
2173
2174 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2175 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2176
2177 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2178 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2179
2180 /* Set the list last index */
793b883e 2181 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2182
793b883e 2183 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2184 if (is_ec_a1(hw)) {
2185 /* WA for dev. #4.3 */
793b883e 2186 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2187
2188 /* set Status-FIFO watermark */
2189 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2190
2191 /* set Status-FIFO ISR watermark */
793b883e 2192 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
69634ee7 2193 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
cd28ab6a 2194 } else {
69634ee7
SH		 2195 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2196 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a
SH		 2197
2198 /* set Status-FIFO ISR watermark */
2199 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
69634ee7
SH		 2200 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2201 else
2202 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2203
69634ee7
SH		 2204 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2205 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2206 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
cd28ab6a
SH		 2207 }
2208
793b883e 2209 /* enable status unit */
cd28ab6a
SH		 2210 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2211
2212 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2213 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2214 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2215
2216 return 0;
2217}
2218
2219static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2220{
2221 u32 modes;
2222 if (hw->copper) {
793b883e
SH		 2223 modes = SUPPORTED_10baseT_Half
2224 | SUPPORTED_10baseT_Full
2225 | SUPPORTED_100baseT_Half
2226 | SUPPORTED_100baseT_Full
2227 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2228
2229 if (hw->chip_id != CHIP_ID_YUKON_FE)
2230 modes |= SUPPORTED_1000baseT_Half
793b883e 2231 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2232 } else
2233 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2234 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2235 return modes;
2236}
2237
793b883e 2238static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2239{
2240 struct sky2_port *sky2 = netdev_priv(dev);
2241 struct sky2_hw *hw = sky2->hw;
2242
2243 ecmd->transceiver = XCVR_INTERNAL;
2244 ecmd->supported = sky2_supported_modes(hw);
2245 ecmd->phy_address = PHY_ADDR_MARV;
2246 if (hw->copper) {
2247 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2248 | SUPPORTED_10baseT_Full
2249 | SUPPORTED_100baseT_Half
2250 | SUPPORTED_100baseT_Full
2251 | SUPPORTED_1000baseT_Half
2252 | SUPPORTED_1000baseT_Full
2253 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2254 ecmd->port = PORT_TP;
2255 } else
2256 ecmd->port = PORT_FIBRE;
2257
2258 ecmd->advertising = sky2->advertising;
2259 ecmd->autoneg = sky2->autoneg;
2260 ecmd->speed = sky2->speed;
2261 ecmd->duplex = sky2->duplex;
2262 return 0;
2263}
2264
2265static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2266{
2267 struct sky2_port *sky2 = netdev_priv(dev);
2268 const struct sky2_hw *hw = sky2->hw;
2269 u32 supported = sky2_supported_modes(hw);
2270
2271 if (ecmd->autoneg == AUTONEG_ENABLE) {
2272 ecmd->advertising = supported;
2273 sky2->duplex = -1;
2274 sky2->speed = -1;
2275 } else {
2276 u32 setting;
2277
793b883e 2278 switch (ecmd->speed) {
cd28ab6a
SH		 2279 case SPEED_1000:
2280 if (ecmd->duplex == DUPLEX_FULL)
2281 setting = SUPPORTED_1000baseT_Full;
2282 else if (ecmd->duplex == DUPLEX_HALF)
2283 setting = SUPPORTED_1000baseT_Half;
2284 else
2285 return -EINVAL;
2286 break;
2287 case SPEED_100:
2288 if (ecmd->duplex == DUPLEX_FULL)
2289 setting = SUPPORTED_100baseT_Full;
2290 else if (ecmd->duplex == DUPLEX_HALF)
2291 setting = SUPPORTED_100baseT_Half;
2292 else
2293 return -EINVAL;
2294 break;
2295
2296 case SPEED_10:
2297 if (ecmd->duplex == DUPLEX_FULL)
2298 setting = SUPPORTED_10baseT_Full;
2299 else if (ecmd->duplex == DUPLEX_HALF)
2300 setting = SUPPORTED_10baseT_Half;
2301 else
2302 return -EINVAL;
2303 break;
2304 default:
2305 return -EINVAL;
2306 }
2307
2308 if ((setting & supported) == 0)
2309 return -EINVAL;
2310
2311 sky2->speed = ecmd->speed;
2312 sky2->duplex = ecmd->duplex;
2313 }
2314
2315 sky2->autoneg = ecmd->autoneg;
2316 sky2->advertising = ecmd->advertising;
2317
2318 if (netif_running(dev)) {
2319 sky2_down(dev);
2320 sky2_up(dev);
2321 }
2322
2323 return 0;
2324}
2325
2326static void sky2_get_drvinfo(struct net_device *dev,
2327 struct ethtool_drvinfo *info)
2328{
2329 struct sky2_port *sky2 = netdev_priv(dev);
2330
2331 strcpy(info->driver, DRV_NAME);
2332 strcpy(info->version, DRV_VERSION);
2333 strcpy(info->fw_version, "N/A");
2334 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2335}
2336
2337static const struct sky2_stat {
793b883e
SH		 2338 char name[ETH_GSTRING_LEN];
2339 u16 offset;
cd28ab6a
SH		 2340} sky2_stats[] = {
2341 { "tx_bytes", GM_TXO_OK_HI },
2342 { "rx_bytes", GM_RXO_OK_HI },
2343 { "tx_broadcast", GM_TXF_BC_OK },
2344 { "rx_broadcast", GM_RXF_BC_OK },
2345 { "tx_multicast", GM_TXF_MC_OK },
2346 { "rx_multicast", GM_RXF_MC_OK },
2347 { "tx_unicast", GM_TXF_UC_OK },
2348 { "rx_unicast", GM_RXF_UC_OK },
2349 { "tx_mac_pause", GM_TXF_MPAUSE },
2350 { "rx_mac_pause", GM_RXF_MPAUSE },
2351 { "collisions", GM_TXF_SNG_COL },
2352 { "late_collision",GM_TXF_LAT_COL },
2353 { "aborted", GM_TXF_ABO_COL },
2354 { "multi_collisions", GM_TXF_MUL_COL },
2355 { "fifo_underrun", GM_TXE_FIFO_UR },
2356 { "fifo_overflow", GM_RXE_FIFO_OV },
2357 { "rx_toolong", GM_RXF_LNG_ERR },
2358 { "rx_jabber", GM_RXF_JAB_PKT },
2359 { "rx_runt", GM_RXE_FRAG },
2360 { "rx_too_long", GM_RXF_LNG_ERR },
2361 { "rx_fcs_error", GM_RXF_FCS_ERR },
2362};
2363
cd28ab6a
SH		 2364static u32 sky2_get_rx_csum(struct net_device *dev)
2365{
2366 struct sky2_port *sky2 = netdev_priv(dev);
2367
2368 return sky2->rx_csum;
2369}
2370
2371static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2372{
2373 struct sky2_port *sky2 = netdev_priv(dev);
2374
2375 sky2->rx_csum = data;
793b883e 2376
cd28ab6a
SH		 2377 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2378 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2379
2380 return 0;
2381}
2382
2383static u32 sky2_get_msglevel(struct net_device *netdev)
2384{
2385 struct sky2_port *sky2 = netdev_priv(netdev);
2386 return sky2->msg_enable;
2387}
2388
9a7ae0a9
SH		 2389static int sky2_nway_reset(struct net_device *dev)
2390{
2391 struct sky2_port *sky2 = netdev_priv(dev);
2392 struct sky2_hw *hw = sky2->hw;
2393
2394 if (sky2->autoneg != AUTONEG_ENABLE)
2395 return -EINVAL;
2396
2397 netif_stop_queue(dev);
2398
91c86df5 2399 down(&sky2->phy_sema);
9a7ae0a9
SH		 2400 sky2_phy_reset(hw, sky2->port);
2401 sky2_phy_init(hw, sky2->port);
91c86df5 2402 up(&sky2->phy_sema);
9a7ae0a9
SH		 2403
2404 return 0;
2405}
2406
793b883e 2407static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2408{
2409 struct sky2_hw *hw = sky2->hw;
2410 unsigned port = sky2->port;
2411 int i;
2412
2413 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2414 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2415 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2416 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2417
793b883e 2418 for (i = 2; i < count; i++)
cd28ab6a
SH		 2419 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2420}
2421
cd28ab6a
SH		 2422static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2423{
2424 struct sky2_port *sky2 = netdev_priv(netdev);
2425 sky2->msg_enable = value;
2426}
2427
2428static int sky2_get_stats_count(struct net_device *dev)
2429{
2430 return ARRAY_SIZE(sky2_stats);
2431}
2432
2433static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2434 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2435{
2436 struct sky2_port *sky2 = netdev_priv(dev);
2437
793b883e 2438 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2439}
2440
793b883e 2441static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2442{
2443 int i;
2444
2445 switch (stringset) {
2446 case ETH_SS_STATS:
2447 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2448 memcpy(data + i * ETH_GSTRING_LEN,
2449 sky2_stats[i].name, ETH_GSTRING_LEN);
2450 break;
2451 }
2452}
2453
2454/* Use hardware MIB variables for critical path statistics and
2455 * transmit feedback not reported at interrupt.
2456 * Other errors are accounted for in interrupt handler.
2457 */
2458static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2459{
2460 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2461 u64 data[13];
cd28ab6a 2462
793b883e 2463 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2464
2465 sky2->net_stats.tx_bytes = data[0];
2466 sky2->net_stats.rx_bytes = data[1];
2467 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2468 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2469 sky2->net_stats.multicast = data[5] + data[7];
2470 sky2->net_stats.collisions = data[10];
2471 sky2->net_stats.tx_aborted_errors = data[12];
2472
2473 return &sky2->net_stats;
2474}
2475
2476static int sky2_set_mac_address(struct net_device *dev, void *p)
2477{
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479 struct sockaddr *addr = p;
2480 int err = 0;
2481
2482 if (!is_valid_ether_addr(addr->sa_data))
2483 return -EADDRNOTAVAIL;
2484
2485 sky2_down(dev);
2486 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2487 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2488 dev->dev_addr, ETH_ALEN);
793b883e 2489 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2490 dev->dev_addr, ETH_ALEN);
2491 if (dev->flags & IFF_UP)
2492 err = sky2_up(dev);
2493 return err;
2494}
2495
2496static void sky2_set_multicast(struct net_device *dev)
2497{
2498 struct sky2_port *sky2 = netdev_priv(dev);
2499 struct sky2_hw *hw = sky2->hw;
2500 unsigned port = sky2->port;
2501 struct dev_mc_list *list = dev->mc_list;
2502 u16 reg;
2503 u8 filter[8];
2504
2505 memset(filter, 0, sizeof(filter));
2506
2507 reg = gma_read16(hw, port, GM_RX_CTRL);
2508 reg |= GM_RXCR_UCF_ENA;
2509
d571b694 2510 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2511 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2512 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2513 memset(filter, 0xff, sizeof(filter));
793b883e 2514 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2515 reg &= ~GM_RXCR_MCF_ENA;
2516 else {
2517 int i;
2518 reg |= GM_RXCR_MCF_ENA;
2519
2520 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2521 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2522 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2523 }
2524 }
2525
cd28ab6a 2526 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2527 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2528 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2529 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2530 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2531 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2532 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2533 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2534
2535 gma_write16(hw, port, GM_RX_CTRL, reg);
2536}
2537
2538/* Can have one global because blinking is controlled by
2539 * ethtool and that is always under RTNL mutex
2540 */
91c86df5 2541static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2542{
793b883e
SH		 2543 u16 pg;
2544
793b883e
SH		 2545 switch (hw->chip_id) {
2546 case CHIP_ID_YUKON_XL:
2547 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2549 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2550 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2551 PHY_M_LEDC_INIT_CTRL(7) |
2552 PHY_M_LEDC_STA1_CTRL(7) |
2553 PHY_M_LEDC_STA0_CTRL(7))
2554 : 0);
2555
2556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2557 break;
2558
2559 default:
2560 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2561 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2562 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2563 PHY_M_LED_MO_10(MO_LED_ON) |
2564 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2565 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2566 PHY_M_LED_MO_RX(MO_LED_ON)
2567 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2568 PHY_M_LED_MO_10(MO_LED_OFF) |
2569 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2570 PHY_M_LED_MO_1000(MO_LED_OFF) |
2571 PHY_M_LED_MO_RX(MO_LED_OFF));
2572
793b883e 2573 }
cd28ab6a
SH		 2574}
2575
2576/* blink LED's for finding board */
2577static int sky2_phys_id(struct net_device *dev, u32 data)
2578{
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 struct sky2_hw *hw = sky2->hw;
2581 unsigned port = sky2->port;
793b883e 2582 u16 ledctrl, ledover = 0;
cd28ab6a 2583 long ms;
91c86df5 2584 int interrupted;
cd28ab6a
SH		 2585 int onoff = 1;
2586
793b883e 2587 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2588 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2589 else
2590 ms = data * 1000;
2591
2592 /* save initial values */
91c86df5 2593 down(&sky2->phy_sema);
793b883e
SH		 2594 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2595 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2596 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2597 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2598 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2599 } else {
2600 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2601 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2602 }
cd28ab6a 2603
91c86df5
SH		 2604 interrupted = 0;
2605 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2606 sky2_led(hw, port, onoff);
2607 onoff = !onoff;
2608
91c86df5
SH		 2609 up(&sky2->phy_sema);
2610 interrupted = msleep_interruptible(250);
2611 down(&sky2->phy_sema);
2612
cd28ab6a
SH		 2613 ms -= 250;
2614 }
2615
2616 /* resume regularly scheduled programming */
793b883e
SH		 2617 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2618 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2620 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2621 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2622 } else {
2623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2624 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2625 }
91c86df5 2626 up(&sky2->phy_sema);
cd28ab6a
SH		 2627
2628 return 0;
2629}
2630
2631static void sky2_get_pauseparam(struct net_device *dev,
2632 struct ethtool_pauseparam *ecmd)
2633{
2634 struct sky2_port *sky2 = netdev_priv(dev);
2635
2636 ecmd->tx_pause = sky2->tx_pause;
2637 ecmd->rx_pause = sky2->rx_pause;
2638 ecmd->autoneg = sky2->autoneg;
2639}
2640
2641static int sky2_set_pauseparam(struct net_device *dev,
2642 struct ethtool_pauseparam *ecmd)
2643{
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645 int err = 0;
2646
2647 sky2->autoneg = ecmd->autoneg;
2648 sky2->tx_pause = ecmd->tx_pause != 0;
2649 sky2->rx_pause = ecmd->rx_pause != 0;
2650
2651 if (netif_running(dev)) {
2652 sky2_down(dev);
2653 err = sky2_up(dev);
2654 }
2655
2656 return err;
2657}
2658
2659#ifdef CONFIG_PM
2660static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2661{
2662 struct sky2_port *sky2 = netdev_priv(dev);
2663
2664 wol->supported = WAKE_MAGIC;
2665 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2666}
2667
2668static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2669{
2670 struct sky2_port *sky2 = netdev_priv(dev);
2671 struct sky2_hw *hw = sky2->hw;
2672
2673 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2674 return -EOPNOTSUPP;
2675
2676 sky2->wol = wol->wolopts == WAKE_MAGIC;
2677
2678 if (sky2->wol) {
2679 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2680
2681 sky2_write16(hw, WOL_CTRL_STAT,
2682 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2683 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2684 } else
2685 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2686
2687 return 0;
2688}
2689#endif
2690
fb17358f
SH		 2691static int sky2_get_coalesce(struct net_device *dev,
2692 struct ethtool_coalesce *ecmd)
2693{
2694 struct sky2_port *sky2 = netdev_priv(dev);
2695 struct sky2_hw *hw = sky2->hw;
2696
2697 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2698 ecmd->tx_coalesce_usecs = 0;
2699 else {
2700 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2701 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2702 }
2703 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2704
2705 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2706 ecmd->rx_coalesce_usecs = 0;
2707 else {
2708 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2709 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2710 }
2711 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2712
2713 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2714 ecmd->rx_coalesce_usecs_irq = 0;
2715 else {
2716 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2717 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2718 }
2719
2720 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2721
2722 return 0;
2723}
2724
2725/* Note: this affect both ports */
2726static int sky2_set_coalesce(struct net_device *dev,
2727 struct ethtool_coalesce *ecmd)
2728{
2729 struct sky2_port *sky2 = netdev_priv(dev);
2730 struct sky2_hw *hw = sky2->hw;
2731 const u32 tmin = sky2_clk2us(hw, 1);
2732 const u32 tmax = 5000;
2733
2734 if (ecmd->tx_coalesce_usecs != 0 &&
2735 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2736 return -EINVAL;
2737
2738 if (ecmd->rx_coalesce_usecs != 0 &&
2739 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2740 return -EINVAL;
2741
2742 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2743 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2744 return -EINVAL;
2745
2746 if (ecmd->tx_max_coalesced_frames > 0xffff)
2747 return -EINVAL;
2748 if (ecmd->rx_max_coalesced_frames > 0xff)
2749 return -EINVAL;
2750 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2751 return -EINVAL;
2752
2753 if (ecmd->tx_coalesce_usecs == 0)
2754 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2755 else {
2756 sky2_write32(hw, STAT_TX_TIMER_INI,
2757 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2758 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2759 }
2760 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2761
2762 if (ecmd->rx_coalesce_usecs == 0)
2763 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2764 else {
2765 sky2_write32(hw, STAT_LEV_TIMER_INI,
2766 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2767 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2768 }
2769 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2770
2771 if (ecmd->rx_coalesce_usecs_irq == 0)
2772 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2773 else {
2774 sky2_write32(hw, STAT_TX_TIMER_INI,
2775 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2776 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2777 }
2778 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2779 return 0;
2780}
2781
793b883e
SH		 2782static void sky2_get_ringparam(struct net_device *dev,
2783 struct ethtool_ringparam *ering)
2784{
2785 struct sky2_port *sky2 = netdev_priv(dev);
2786
2787 ering->rx_max_pending = RX_MAX_PENDING;
2788 ering->rx_mini_max_pending = 0;
2789 ering->rx_jumbo_max_pending = 0;
2790 ering->tx_max_pending = TX_RING_SIZE - 1;
2791
2792 ering->rx_pending = sky2->rx_pending;
2793 ering->rx_mini_pending = 0;
2794 ering->rx_jumbo_pending = 0;
2795 ering->tx_pending = sky2->tx_pending;
2796}
2797
2798static int sky2_set_ringparam(struct net_device *dev,
2799 struct ethtool_ringparam *ering)
2800{
2801 struct sky2_port *sky2 = netdev_priv(dev);
2802 int err = 0;
2803
2804 if (ering->rx_pending > RX_MAX_PENDING ||
2805 ering->rx_pending < 8 ||
2806 ering->tx_pending < MAX_SKB_TX_LE ||
2807 ering->tx_pending > TX_RING_SIZE - 1)
2808 return -EINVAL;
2809
2810 if (netif_running(dev))
2811 sky2_down(dev);
2812
2813 sky2->rx_pending = ering->rx_pending;
2814 sky2->tx_pending = ering->tx_pending;
2815
2816 if (netif_running(dev))
2817 err = sky2_up(dev);
2818
2819 return err;
2820}
2821
793b883e
SH		 2822static int sky2_get_regs_len(struct net_device *dev)
2823{
6e4cbb34 2824 return 0x4000;
793b883e
SH		 2825}
2826
2827/*
2828 * Returns copy of control register region
6e4cbb34 2829 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2830 */
2831static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2832 void *p)
2833{
2834 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2835 const void __iomem *io = sky2->hw->regs;
793b883e 2836
6e4cbb34 2837 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2838 regs->version = 1;
6e4cbb34 2839 memset(p, 0, regs->len);
793b883e 2840
6e4cbb34
SH		 2841 memcpy_fromio(p, io, B3_RAM_ADDR);
2842
2843 memcpy_fromio(p + B3_RI_WTO_R1,
2844 io + B3_RI_WTO_R1,
2845 regs->len - B3_RI_WTO_R1);
793b883e 2846}
cd28ab6a
SH		 2847
2848static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2849 .get_settings = sky2_get_settings,
2850 .set_settings = sky2_set_settings,
2851 .get_drvinfo = sky2_get_drvinfo,
2852 .get_msglevel = sky2_get_msglevel,
2853 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2854 .nway_reset = sky2_nway_reset,
793b883e
SH		 2855 .get_regs_len = sky2_get_regs_len,
2856 .get_regs = sky2_get_regs,
2857 .get_link = ethtool_op_get_link,
2858 .get_sg = ethtool_op_get_sg,
2859 .set_sg = ethtool_op_set_sg,
2860 .get_tx_csum = ethtool_op_get_tx_csum,
2861 .set_tx_csum = ethtool_op_set_tx_csum,
2862 .get_tso = ethtool_op_get_tso,
2863 .set_tso = ethtool_op_set_tso,
2864 .get_rx_csum = sky2_get_rx_csum,
2865 .set_rx_csum = sky2_set_rx_csum,
2866 .get_strings = sky2_get_strings,
fb17358f
SH		 2867 .get_coalesce = sky2_get_coalesce,
2868 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2869 .get_ringparam = sky2_get_ringparam,
2870 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2871 .get_pauseparam = sky2_get_pauseparam,
2872 .set_pauseparam = sky2_set_pauseparam,
2873#ifdef CONFIG_PM
793b883e
SH		 2874 .get_wol = sky2_get_wol,
2875 .set_wol = sky2_set_wol,
cd28ab6a 2876#endif
793b883e 2877 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2878 .get_stats_count = sky2_get_stats_count,
2879 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2880 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2881};
2882
2883/* Initialize network device */
2884static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2885 unsigned port, int highmem)
2886{
2887 struct sky2_port *sky2;
2888 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2889
2890 if (!dev) {
2891 printk(KERN_ERR "sky2 etherdev alloc failed");
2892 return NULL;
2893 }
2894
2895 SET_MODULE_OWNER(dev);
2896 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2897 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2898 dev->open = sky2_up;
2899 dev->stop = sky2_down;
ef743d33 2900 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2901 dev->hard_start_xmit = sky2_xmit_frame;
2902 dev->get_stats = sky2_get_stats;
2903 dev->set_multicast_list = sky2_set_multicast;
2904 dev->set_mac_address = sky2_set_mac_address;
2905 dev->change_mtu = sky2_change_mtu;
2906 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2907 dev->tx_timeout = sky2_tx_timeout;
2908 dev->watchdog_timeo = TX_WATCHDOG;
2909 if (port == 0)
2910 dev->poll = sky2_poll;
2911 dev->weight = NAPI_WEIGHT;
2912#ifdef CONFIG_NET_POLL_CONTROLLER
2913 dev->poll_controller = sky2_netpoll;
2914#endif
cd28ab6a
SH		 2915
2916 sky2 = netdev_priv(dev);
2917 sky2->netdev = dev;
2918 sky2->hw = hw;
2919 sky2->msg_enable = netif_msg_init(debug, default_msg);
2920
2921 spin_lock_init(&sky2->tx_lock);
2922 /* Auto speed and flow control */
2923 sky2->autoneg = AUTONEG_ENABLE;
585b5601 2924 sky2->tx_pause = 1;
cd28ab6a
SH		 2925 sky2->rx_pause = 1;
2926 sky2->duplex = -1;
2927 sky2->speed = -1;
2928 sky2->advertising = sky2_supported_modes(hw);
2929 sky2->rx_csum = 1;
91c86df5
SH		 2930 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2931 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2932 sky2->tx_pending = TX_DEF_PENDING;
2933 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
734d1868 2934 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 2935
2936 hw->dev[port] = dev;
2937
2938 sky2->port = port;
2939
5a5b1ea0
SH		 2940 dev->features |= NETIF_F_LLTX;
2941 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2942 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2943 if (highmem)
2944 dev->features |= NETIF_F_HIGHDMA;
793b883e 2945 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2946
d1f13708
SH		 2947#ifdef SKY2_VLAN_TAG_USED
2948 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2949 dev->vlan_rx_register = sky2_vlan_rx_register;
2950 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2951#endif
2952
cd28ab6a 2953 /* read the mac address */
793b883e 2954 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2955 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2956
2957 /* device is off until link detection */
2958 netif_carrier_off(dev);
2959 netif_stop_queue(dev);
2960
2961 return dev;
2962}
2963
2964static inline void sky2_show_addr(struct net_device *dev)
2965{
2966 const struct sky2_port *sky2 = netdev_priv(dev);
2967
2968 if (netif_msg_probe(sky2))
2969 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2970 dev->name,
2971 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2972 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2973}
2974
2975static int __devinit sky2_probe(struct pci_dev *pdev,
2976 const struct pci_device_id *ent)
2977{
793b883e 2978 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2979 struct sky2_hw *hw;
5afa0a9c 2980 int err, pm_cap, using_dac = 0;
cd28ab6a 2981
793b883e
SH		 2982 err = pci_enable_device(pdev);
2983 if (err) {
cd28ab6a
SH		 2984 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2985 pci_name(pdev));
2986 goto err_out;
2987 }
2988
793b883e
SH		 2989 err = pci_request_regions(pdev, DRV_NAME);
2990 if (err) {
cd28ab6a
SH		 2991 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2992 pci_name(pdev));
793b883e 2993 goto err_out;
cd28ab6a
SH		 2994 }
2995
2996 pci_set_master(pdev);
2997
5afa0a9c
SH		 2998 /* Find power-management capability. */
2999 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3000 if (pm_cap == 0) {
3001 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3002 "aborting.\n");
3003 err = -EIO;
3004 goto err_out_free_regions;
3005 }
3006
cd28ab6a
SH		 3007 if (sizeof(dma_addr_t) > sizeof(u32)) {
3008 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3009 if (!err)
3010 using_dac = 1;
3011 }
3012
3013 if (!using_dac) {
3014 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3015 if (err) {
3016 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3017 pci_name(pdev));
3018 goto err_out_free_regions;
3019 }
3020 }
cd28ab6a 3021#ifdef __BIG_ENDIAN
d571b694 3022 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3023 {
3024 u32 reg;
3025
3026 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3027 reg |= PCI_REV_DESC;
3028 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3029 }
3030#endif
3031
3032 err = -ENOMEM;
3033 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3034 if (!hw) {
3035 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3036 pci_name(pdev));
3037 goto err_out_free_regions;
3038 }
3039
3040 memset(hw, 0, sizeof(*hw));
3041 hw->pdev = pdev;
cd28ab6a
SH		 3042
3043 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3044 if (!hw->regs) {
3045 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3046 pci_name(pdev));
3047 goto err_out_free_hw;
3048 }
5afa0a9c 3049 hw->pm_cap = pm_cap;
cd28ab6a 3050
cd28ab6a
SH		 3051 err = sky2_reset(hw);
3052 if (err)
793b883e 3053 goto err_out_iounmap;
cd28ab6a 3054
5f4f9dc1
SH		 3055 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3056 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3057 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3058 hw->chip_id, hw->chip_rev);
cd28ab6a 3059
793b883e
SH		 3060 dev = sky2_init_netdev(hw, 0, using_dac);
3061 if (!dev)
cd28ab6a
SH		 3062 goto err_out_free_pci;
3063
793b883e
SH		 3064 err = register_netdev(dev);
3065 if (err) {
cd28ab6a
SH		 3066 printk(KERN_ERR PFX "%s: cannot register net device\n",
3067 pci_name(pdev));
3068 goto err_out_free_netdev;
3069 }
3070
3071 sky2_show_addr(dev);
3072
3073 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3074 if (register_netdev(dev1) == 0)
3075 sky2_show_addr(dev1);
3076 else {
3077 /* Failure to register second port need not be fatal */
793b883e
SH		 3078 printk(KERN_WARNING PFX
3079 "register of second port failed\n");
cd28ab6a
SH		 3080 hw->dev[1] = NULL;
3081 free_netdev(dev1);
3082 }
3083 }
3084
793b883e
SH		 3085 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3086 if (err) {
3087 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3088 pci_name(pdev), pdev->irq);
3089 goto err_out_unregister;
3090 }
3091
3092 hw->intr_mask = Y2_IS_BASE;
3093 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3094
3095 pci_set_drvdata(pdev, hw);
3096
cd28ab6a
SH		 3097 return 0;
3098
793b883e
SH		 3099err_out_unregister:
3100 if (dev1) {
3101 unregister_netdev(dev1);
3102 free_netdev(dev1);
3103 }
3104 unregister_netdev(dev);
cd28ab6a
SH		 3105err_out_free_netdev:
3106 free_netdev(dev);
cd28ab6a 3107err_out_free_pci:
793b883e 3108 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3109 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3110err_out_iounmap:
3111 iounmap(hw->regs);
3112err_out_free_hw:
3113 kfree(hw);
3114err_out_free_regions:
3115 pci_release_regions(pdev);
cd28ab6a 3116 pci_disable_device(pdev);
cd28ab6a
SH		 3117err_out:
3118 return err;
3119}
3120
3121static void __devexit sky2_remove(struct pci_dev *pdev)
3122{
793b883e 3123 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3124 struct net_device *dev0, *dev1;
3125
793b883e 3126 if (!hw)
cd28ab6a
SH		 3127 return;
3128
cd28ab6a 3129 dev0 = hw->dev[0];
793b883e
SH		 3130 dev1 = hw->dev[1];
3131 if (dev1)
3132 unregister_netdev(dev1);
cd28ab6a
SH		 3133 unregister_netdev(dev0);
3134
793b883e 3135 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3136 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3137 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3138 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3139 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3140
3141 free_irq(pdev->irq, hw);
793b883e 3142 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3143 pci_release_regions(pdev);
3144 pci_disable_device(pdev);
793b883e 3145
cd28ab6a
SH		 3146 if (dev1)
3147 free_netdev(dev1);
3148 free_netdev(dev0);
3149 iounmap(hw->regs);
3150 kfree(hw);
5afa0a9c 3151
cd28ab6a
SH		 3152 pci_set_drvdata(pdev, NULL);
3153}
3154
3155#ifdef CONFIG_PM
3156static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3157{
793b883e 3158 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3159 int i;
cd28ab6a
SH		 3160
3161 for (i = 0; i < 2; i++) {
3162 struct net_device *dev = hw->dev[i];
3163
3164 if (dev) {
5afa0a9c
SH		 3165 if (!netif_running(dev))
3166 continue;
3167
3168 sky2_down(dev);
cd28ab6a 3169 netif_device_detach(dev);
cd28ab6a
SH		 3170 }
3171 }
3172
5afa0a9c 3173 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3174}
3175
3176static int sky2_resume(struct pci_dev *pdev)
3177{
793b883e 3178 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3179 int i;
3180
cd28ab6a
SH		 3181 pci_restore_state(pdev);
3182 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3183 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3184
3185 sky2_reset(hw);
3186
3187 for (i = 0; i < 2; i++) {
3188 struct net_device *dev = hw->dev[i];
3189 if (dev) {
5afa0a9c
SH		 3190 if (netif_running(dev)) {
3191 netif_device_attach(dev);
cd28ab6a 3192 sky2_up(dev);
5afa0a9c 3193 }
cd28ab6a
SH		 3194 }
3195 }
3196 return 0;
3197}
3198#endif
3199
3200static struct pci_driver sky2_driver = {
793b883e
SH		 3201 .name = DRV_NAME,
3202 .id_table = sky2_id_table,
3203 .probe = sky2_probe,
3204 .remove = __devexit_p(sky2_remove),
cd28ab6a 3205#ifdef CONFIG_PM
793b883e
SH		 3206 .suspend = sky2_suspend,
3207 .resume = sky2_resume,
cd28ab6a
SH		 3208#endif
3209};
3210
3211static int __init sky2_init_module(void)
3212{
50241c4c 3213 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3214}
3215
3216static void __exit sky2_cleanup_module(void)
3217{
3218 pci_unregister_driver(&sky2_driver);
3219}
3220
3221module_init(sky2_init_module);
3222module_exit(sky2_cleanup_module);
3223
3224MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3225MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3226MODULE_LICENSE("GPL");
5f4f9dc1 3227MODULE_VERSION(DRV_VERSION);
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