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dma-mapping: replace all DMA_32BIT_MASK macro with DMA_BIT_MASK(32)
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a 26#include <linux/kernel.h>
cd28ab6a
SH		 27#include <linux/module.h>
28#include <linux/netdevice.h>
d0bbccfa 29#include <linux/dma-mapping.h>
cd28ab6a
SH		 30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/pci.h>
33#include <linux/ip.h>
c9bdd4b5 34#include <net/ip.h>
cd28ab6a
SH		 35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
3cf26753 41#include <linux/debugfs.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
743d32ad 53#define DRV_VERSION "1.22"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 66
67#define TX_RING_SIZE 512
68#define TX_DEF_PENDING (TX_RING_SIZE - 1)
69#define TX_MIN_PENDING 64
b19666d9 70#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 71
793b883e 72#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 73#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 74#define TX_WATCHDOG (5 * HZ)
75#define NAPI_WEIGHT 64
76#define PHY_RETRIES 1000
77
f4331a6d
SH		 78#define SKY2_EEPROM_MAGIC 0x9955aabb
79
80
cb5d9547
SH		 81#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
cd28ab6a 83static const u32 default_msg =
793b883e
SH		 84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 87
793b883e 88static int debug = -1; /* defaults above */
cd28ab6a
SH		 89module_param(debug, int, 0);
90MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
14d0263f 92static int copybreak __read_mostly = 128;
bdb5c58e
SH		 93module_param(copybreak, int, 0);
94MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
fb2690a9
SH		 96static int disable_msi = 0;
97module_param(disable_msi, int, 0);
98MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
e6cac9ba 100static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 103 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
cd28ab6a
SH		 140 { 0 }
141};
793b883e 142
cd28ab6a
SH		 143MODULE_DEVICE_TABLE(pci, sky2_id_table);
144
145/* Avoid conditionals by using array */
146static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
147static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 148static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 149
d1b139c0
SH		 150static void sky2_set_multicast(struct net_device *dev);
151
af043aa5 152/* Access to PHY via serial interconnect */
ef743d33 153static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 154{
155 int i;
156
157 gma_write16(hw, port, GM_SMI_DATA, val);
158 gma_write16(hw, port, GM_SMI_CTRL,
159 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
160
161 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 162 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
163 if (ctrl == 0xffff)
164 goto io_error;
165
166 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 167 return 0;
af043aa5
SH		 168
169 udelay(10);
cd28ab6a 170 }
ef743d33 171
af043aa5 172 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 173 return -ETIMEDOUT;
af043aa5
SH		 174
175io_error:
176 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
177 return -EIO;
cd28ab6a
SH		 178}
179
ef743d33 180static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 181{
182 int i;
183
793b883e 184 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 185 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
186
187 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 188 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
189 if (ctrl == 0xffff)
190 goto io_error;
191
192 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 193 *val = gma_read16(hw, port, GM_SMI_DATA);
194 return 0;
195 }
196
af043aa5 197 udelay(10);
cd28ab6a
SH		 198 }
199
af043aa5 200 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 201 return -ETIMEDOUT;
af043aa5
SH		 202io_error:
203 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
204 return -EIO;
ef743d33
SH		 205}
206
af043aa5 207static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 208{
209 u16 v;
af043aa5 210 __gm_phy_read(hw, port, reg, &v);
ef743d33 211 return v;
cd28ab6a
SH		 212}
213
5afa0a9c 214
ae306cca
SH		 215static void sky2_power_on(struct sky2_hw *hw)
216{
217 /* switch power to VCC (WA for VAUX problem) */
218 sky2_write8(hw, B0_POWER_CTRL,
219 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 220
ae306cca
SH		 221 /* disable Core Clock Division, */
222 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 223
ae306cca
SH		 224 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
225 /* enable bits are inverted */
226 sky2_write8(hw, B2_Y2_CLK_GATE,
227 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
228 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
229 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
230 else
231 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 232
ea76e635 233 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 234 u32 reg;
5afa0a9c 235
b32f40c4 236 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 237
b32f40c4 238 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 239 /* set all bits to 0 except bits 15..12 and 8 */
240 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 244 /* set all bits to 0 except bits 28 & 27 */
245 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 247
b32f40c4 248 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f
SH		 249
250 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
251 reg = sky2_read32(hw, B2_GP_IO);
252 reg |= GLB_GPIO_STAT_RACE_DIS;
253 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 254
255 sky2_read32(hw, B2_GP_IO);
5afa0a9c 256 }
ae306cca 257}
5afa0a9c 258
ae306cca
SH		 259static void sky2_power_aux(struct sky2_hw *hw)
260{
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
263 else
264 /* enable bits are inverted */
265 sky2_write8(hw, B2_Y2_CLK_GATE,
266 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
269
270 /* switch power to VAUX */
271 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
272 sky2_write8(hw, B0_POWER_CTRL,
273 (PC_VAUX_ENA | PC_VCC_ENA |
274 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 275}
276
d3bcfbeb 277static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 278{
279 u16 reg;
280
281 /* disable all GMAC IRQ's */
282 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 283
cd28ab6a
SH		 284 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
285 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288
289 reg = gma_read16(hw, port, GM_RX_CTRL);
290 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
291 gma_write16(hw, port, GM_RX_CTRL, reg);
292}
293
16ad91e1
SH		 294/* flow control to advertise bits */
295static const u16 copper_fc_adv[] = {
296 [FC_NONE] = 0,
297 [FC_TX] = PHY_M_AN_ASP,
298 [FC_RX] = PHY_M_AN_PC,
299 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
300};
301
302/* flow control to advertise bits when using 1000BaseX */
303static const u16 fiber_fc_adv[] = {
df3fe1f3 304 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 305 [FC_TX] = PHY_M_P_ASYM_MD_X,
306 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 307 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 308};
309
310/* flow control to GMA disable bits */
311static const u16 gm_fc_disable[] = {
312 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
313 [FC_TX] = GM_GPCR_FC_RX_DIS,
314 [FC_RX] = GM_GPCR_FC_TX_DIS,
315 [FC_BOTH] = 0,
316};
317
318
cd28ab6a
SH		 319static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
320{
321 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 322 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 323
ea76e635
SH		 324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 326 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
327
328 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 329 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 330 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
331
53419c68 332 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 333 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 334 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 335 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
336 else
53419c68
SH		 337 /* set master & slave downshift counter to 1x */
338 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 339
340 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
341 }
342
343 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 344 if (sky2_is_copper(hw)) {
05745c4a 345 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 346 /* enable automatic crossover */
347 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 348
349 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
350 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
351 u16 spec;
352
353 /* Enable Class A driver for FE+ A0 */
354 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
355 spec |= PHY_M_FESC_SEL_CL_A;
356 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
357 }
cd28ab6a
SH		 358 } else {
359 /* disable energy detect */
360 ctrl &= ~PHY_M_PC_EN_DET_MSK;
361
362 /* enable automatic crossover */
363 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
364
53419c68 365 /* downshift on PHY 88E1112 and 88E1149 is changed */
93745494 366 if (sky2->autoneg == AUTONEG_ENABLE
ea76e635 367 && (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 368 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 369 ctrl &= ~PHY_M_PC_DSC_MSK;
370 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
371 }
372 }
cd28ab6a
SH		 373 } else {
374 /* workaround for deviation #4.88 (CRC errors) */
375 /* disable Automatic Crossover */
376
377 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 378 }
cd28ab6a 379
b89165f2
SH		 380 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
381
382 /* special setup for PHY 88E1112 Fiber */
ea76e635 383 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 384 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 385
b89165f2
SH		 386 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
387 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
388 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
389 ctrl &= ~PHY_M_MAC_MD_MSK;
390 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392
393 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 394 /* select page 1 to access Fiber registers */
395 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 396
397 /* for SFP-module set SIGDET polarity to low */
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 401 }
b89165f2
SH		 402
403 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 404 }
405
7800fddc 406 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 407 ct1000 = 0;
408 adv = PHY_AN_CSMA;
2eaba1a2 409 reg = 0;
cd28ab6a
SH		 410
411 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 412 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 413 if (sky2->advertising & ADVERTISED_1000baseT_Full)
414 ct1000 |= PHY_M_1000C_AFD;
415 if (sky2->advertising & ADVERTISED_1000baseT_Half)
416 ct1000 |= PHY_M_1000C_AHD;
417 if (sky2->advertising & ADVERTISED_100baseT_Full)
418 adv |= PHY_M_AN_100_FD;
419 if (sky2->advertising & ADVERTISED_100baseT_Half)
420 adv |= PHY_M_AN_100_HD;
421 if (sky2->advertising & ADVERTISED_10baseT_Full)
422 adv |= PHY_M_AN_10_FD;
423 if (sky2->advertising & ADVERTISED_10baseT_Half)
424 adv |= PHY_M_AN_10_HD;
709c6e7b 425
16ad91e1 426 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 427 } else { /* special defines for FIBER (88E1040S only) */
428 if (sky2->advertising & ADVERTISED_1000baseT_Full)
429 adv |= PHY_M_AN_1000X_AFD;
430 if (sky2->advertising & ADVERTISED_1000baseT_Half)
431 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 432
16ad91e1 433 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 434 }
cd28ab6a
SH		 435
436 /* Restart Auto-negotiation */
437 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
438 } else {
439 /* forced speed/duplex settings */
440 ct1000 = PHY_M_1000C_MSE;
441
2eaba1a2
SH		 442 /* Disable auto update for duplex flow control and speed */
443 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 444
445 switch (sky2->speed) {
446 case SPEED_1000:
447 ctrl |= PHY_CT_SP1000;
2eaba1a2 448 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 449 break;
450 case SPEED_100:
451 ctrl |= PHY_CT_SP100;
2eaba1a2 452 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 453 break;
454 }
455
2eaba1a2
SH		 456 if (sky2->duplex == DUPLEX_FULL) {
457 reg |= GM_GPCR_DUP_FULL;
458 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 459 } else if (sky2->speed < SPEED_1000)
460 sky2->flow_mode = FC_NONE;
2eaba1a2 461
2eaba1a2 462
16ad91e1 463 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 464
465 /* Forward pause packets to GMAC? */
16ad91e1 466 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 467 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
468 else
469 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 470 }
471
2eaba1a2
SH		 472 gma_write16(hw, port, GM_GP_CTRL, reg);
473
05745c4a 474 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 475 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
476
477 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
478 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
479
480 /* Setup Phy LED's */
481 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
482 ledover = 0;
483
484 switch (hw->chip_id) {
485 case CHIP_ID_YUKON_FE:
486 /* on 88E3082 these bits are at 11..9 (shifted left) */
487 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
488
489 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
490
491 /* delete ACT LED control bits */
492 ctrl &= ~PHY_M_FELP_LED1_MSK;
493 /* change ACT LED control to blink mode */
494 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
495 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
496 break;
497
05745c4a
SH		 498 case CHIP_ID_YUKON_FE_P:
499 /* Enable Link Partner Next Page */
500 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
501 ctrl |= PHY_M_PC_ENA_LIP_NP;
502
503 /* disable Energy Detect and enable scrambler */
504 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
505 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
506
507 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
508 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
509 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
510 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
511
512 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 break;
514
cd28ab6a 515 case CHIP_ID_YUKON_XL:
793b883e 516 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 517
518 /* select page 3 to access LED control register */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
520
521 /* set LED Function Control register */
ed6d32c7
SH		 522 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
523 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
524 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
525 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
526 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 527
528 /* set Polarity Control register */
529 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 530 (PHY_M_POLC_LS1_P_MIX(4) |
531 PHY_M_POLC_IS0_P_MIX(4) |
532 PHY_M_POLC_LOS_CTRL(2) |
533 PHY_M_POLC_INIT_CTRL(2) |
534 PHY_M_POLC_STA1_CTRL(2) |
535 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 536
537 /* restore page register */
793b883e 538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 539 break;
93745494 540
ed6d32c7 541 case CHIP_ID_YUKON_EC_U:
93745494 542 case CHIP_ID_YUKON_EX:
ed4d4161 543 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 544 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
545
546 /* select page 3 to access LED control register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
548
549 /* set LED Function Control register */
550 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
551 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
552 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
553 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
554 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
555
556 /* set Blink Rate in LED Timer Control Register */
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
558 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
559 /* restore page register */
560 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
561 break;
cd28ab6a
SH		 562
563 default:
564 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
565 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 566
cd28ab6a 567 /* turn off the Rx LED (LED_RX) */
a84d0a3d 568 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 569 }
570
0ce8b98d 571 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 572 /* apply fixes in PHY AFE */
ed6d32c7
SH		 573 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
574
977bdf06 575 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 576 gm_phy_write(hw, port, 0x18, 0xaa99);
577 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 578
0ce8b98d
SH		 579 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
580 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
581 gm_phy_write(hw, port, 0x18, 0xa204);
582 gm_phy_write(hw, port, 0x17, 0x2002);
583 }
977bdf06
SH		 584
585 /* set page register to 0 */
9467a8fc 586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 587 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
588 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
589 /* apply workaround for integrated resistors calibration */
590 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
591 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
e1a74b37
SH		 592 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
593 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 594 /* no effect on Yukon-XL */
977bdf06 595 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 596
977bdf06
SH		 597 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
598 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 599 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 600 }
cd28ab6a 601
977bdf06
SH		 602 if (ledover)
603 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
604
605 }
2eaba1a2 606
d571b694 607 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 608 if (sky2->autoneg == AUTONEG_ENABLE)
609 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
610 else
611 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
612}
613
b96936da
SH		 614static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
615static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
616
617static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 618{
619 u32 reg1;
d3bcfbeb 620
82637e80 621 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 622 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 623 reg1 &= ~phy_power[port];
d3bcfbeb 624
b96936da 625 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
ff35164e
SH		 626 reg1 |= coma_mode[port];
627
b32f40c4 628 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
82637e80
SH		 629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
630 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 631
632 if (hw->chip_id == CHIP_ID_YUKON_FE)
633 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
634 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
635 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 636}
167f53d0 637
b96936da
SH		 638static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
639{
640 u32 reg1;
db99b988
SH		 641 u16 ctrl;
642
643 /* release GPHY Control reset */
644 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
645
646 /* release GMAC reset */
647 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
648
649 if (hw->flags & SKY2_HW_NEWER_PHY) {
650 /* select page 2 to access MAC control register */
651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
652
653 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
654 /* allow GMII Power Down */
655 ctrl &= ~PHY_M_MAC_GMIF_PUP;
656 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
657
658 /* set page register back to 0 */
659 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
660 }
661
662 /* setup General Purpose Control Register */
663 gma_write16(hw, port, GM_GP_CTRL,
664 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
665
666 if (hw->chip_id != CHIP_ID_YUKON_EC) {
667 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 668 /* select page 2 to access MAC control register */
669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 670
e484d5f5 671 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 672 /* enable Power Down */
673 ctrl |= PHY_M_PC_POW_D_ENA;
674 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 675
676 /* set page register back to 0 */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 678 }
679
680 /* set IEEE compatible Power Down Mode (dev. #4.99) */
681 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
682 }
b96936da
SH		 683
684 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
685 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 686 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da
SH		 687 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
688 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 689}
690
1b537565
SH		 691/* Force a renegotiation */
692static void sky2_phy_reinit(struct sky2_port *sky2)
693{
e07b1aa8 694 spin_lock_bh(&sky2->phy_lock);
1b537565 695 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 696 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 697}
698
e3173832
SH		 699/* Put device in state to listen for Wake On Lan */
700static void sky2_wol_init(struct sky2_port *sky2)
701{
702 struct sky2_hw *hw = sky2->hw;
703 unsigned port = sky2->port;
704 enum flow_control save_mode;
705 u16 ctrl;
706 u32 reg1;
707
708 /* Bring hardware out of reset */
709 sky2_write16(hw, B0_CTST, CS_RST_CLR);
710 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
711
712 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
713 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
714
715 /* Force to 10/100
716 * sky2_reset will re-enable on resume
717 */
718 save_mode = sky2->flow_mode;
719 ctrl = sky2->advertising;
720
721 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
722 sky2->flow_mode = FC_NONE;
b96936da
SH		 723
724 spin_lock_bh(&sky2->phy_lock);
725 sky2_phy_power_up(hw, port);
726 sky2_phy_init(hw, port);
727 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 728
729 sky2->flow_mode = save_mode;
730 sky2->advertising = ctrl;
731
732 /* Set GMAC to no flow control and auto update for speed/duplex */
733 gma_write16(hw, port, GM_GP_CTRL,
734 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
735 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
736
737 /* Set WOL address */
738 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
739 sky2->netdev->dev_addr, ETH_ALEN);
740
741 /* Turn on appropriate WOL control bits */
742 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
743 ctrl = 0;
744 if (sky2->wol & WAKE_PHY)
745 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
746 else
747 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
748
749 if (sky2->wol & WAKE_MAGIC)
750 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
751 else
752 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
753
754 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
755 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
756
757 /* Turn on legacy PCI-Express PME mode */
b32f40c4 758 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
e3173832 759 reg1 |= PCI_Y2_PME_LEGACY;
b32f40c4 760 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
e3173832
SH		 761
762 /* block receiver */
763 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
764
765}
766
69161611
SH		 767static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
768{
05745c4a
SH		 769 struct net_device *dev = hw->dev[port];
770
ed4d4161
SH		 771 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
772 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
773 hw->chip_id == CHIP_ID_YUKON_FE_P ||
774 hw->chip_id == CHIP_ID_YUKON_SUPR) {
775 /* Yukon-Extreme B0 and further Extreme devices */
776 /* enable Store & Forward mode for TX */
05745c4a 777
ed4d4161
SH		 778 if (dev->mtu <= ETH_DATA_LEN)
779 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
780 TX_JUMBO_DIS | TX_STFW_ENA);
69161611 781
ed4d4161
SH		 782 else
783 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
784 TX_JUMBO_ENA| TX_STFW_ENA);
785 } else {
786 if (dev->mtu <= ETH_DATA_LEN)
787 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
788 else {
789 /* set Tx GMAC FIFO Almost Empty Threshold */
790 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
791 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
69161611 792
ed4d4161
SH		 793 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
794
795 /* Can't do offload because of lack of store/forward */
796 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
797 }
69161611
SH		 798 }
799}
800
cd28ab6a
SH		 801static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
802{
803 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
804 u16 reg;
25cccecc 805 u32 rx_reg;
cd28ab6a
SH		 806 int i;
807 const u8 *addr = hw->dev[port]->dev_addr;
808
f350339c
SH		 809 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
810 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 811
812 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
813
793b883e 814 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 815 /* WA DEV_472 -- looks like crossed wires on port 2 */
816 /* clear GMAC 1 Control reset */
817 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
818 do {
819 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
820 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
821 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
822 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
823 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
824 }
825
793b883e 826 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 827
2eaba1a2
SH		 828 /* Enable Transmit FIFO Underrun */
829 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
830
e07b1aa8 831 spin_lock_bh(&sky2->phy_lock);
b96936da 832 sky2_phy_power_up(hw, port);
cd28ab6a 833 sky2_phy_init(hw, port);
e07b1aa8 834 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 835
836 /* MIB clear */
837 reg = gma_read16(hw, port, GM_PHY_ADDR);
838 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
839
43f2f104
SH		 840 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
841 gma_read16(hw, port, i);
cd28ab6a
SH		 842 gma_write16(hw, port, GM_PHY_ADDR, reg);
843
844 /* transmit control */
845 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
846
847 /* receive control reg: unicast + multicast + no FCS */
848 gma_write16(hw, port, GM_RX_CTRL,
793b883e 849 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 850
851 /* transmit flow control */
852 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
853
854 /* transmit parameter */
855 gma_write16(hw, port, GM_TX_PARAM,
856 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
857 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
858 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
859 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
860
861 /* serial mode register */
862 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 863 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 864
6b1a3aef 865 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 866 reg |= GM_SMOD_JUMBO_ENA;
867
868 gma_write16(hw, port, GM_SERIAL_MODE, reg);
869
cd28ab6a
SH		 870 /* virtual address for data */
871 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
872
793b883e
SH		 873 /* physical address: used for pause frames */
874 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
875
876 /* ignore counter overflows */
cd28ab6a
SH		 877 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
878 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
879 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
880
881 /* Configure Rx MAC FIFO */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 883 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 884 if (hw->chip_id == CHIP_ID_YUKON_EX ||
885 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 886 rx_reg |= GMF_RX_OVER_ON;
69161611 887
25cccecc 888 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 889
798fdd07
SH		 890 if (hw->chip_id == CHIP_ID_YUKON_XL) {
891 /* Hardware errata - clear flush mask */
892 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
893 } else {
894 /* Flush Rx MAC FIFO on any flow control or error */
895 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
896 }
cd28ab6a 897
8df9a876 898 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 899 reg = RX_GMF_FL_THR_DEF + 1;
900 /* Another magic mystery workaround from sk98lin */
901 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
902 hw->chip_rev == CHIP_REV_YU_FE2_A0)
903 reg = 0x178;
904 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 905
906 /* Configure Tx MAC FIFO */
907 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
908 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 909
e0c28116 910 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 911 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
8df9a876 912 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0 913 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
b628ed98 914
69161611 915 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 916 }
917
e970d1f8
SH		 918 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
919 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
920 /* disable dynamic watermark */
921 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
922 reg &= ~TX_DYN_WM_ENA;
923 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
924 }
cd28ab6a
SH		 925}
926
67712901
SH		 927/* Assign Ram Buffer allocation to queue */
928static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 929{
67712901
SH		 930 u32 end;
931
932 /* convert from K bytes to qwords used for hw register */
933 start *= 1024/8;
934 space *= 1024/8;
935 end = start + space - 1;
793b883e 936
cd28ab6a
SH		 937 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
938 sky2_write32(hw, RB_ADDR(q, RB_START), start);
939 sky2_write32(hw, RB_ADDR(q, RB_END), end);
940 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
941 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
942
943 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 944 u32 tp = space - space/4;
793b883e 945
1c28f6ba
SH		 946 /* On receive queue's set the thresholds
947 * give receiver priority when > 3/4 full
948 * send pause when down to 2K
949 */
950 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
951 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 952
1c28f6ba
SH		 953 tp = space - 2048/8;
954 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
955 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 956 } else {
957 /* Enable store & forward on Tx queue's because
958 * Tx FIFO is only 1K on Yukon
959 */
960 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
961 }
962
963 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 964 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 965}
966
cd28ab6a 967/* Setup Bus Memory Interface */
af4ed7e6 968static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 969{
970 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
971 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
972 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 973 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 974}
975
cd28ab6a
SH		 976/* Setup prefetch unit registers. This is the interface between
977 * hardware and driver list elements
978 */
8cc048e3 979static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 980 u64 addr, u32 last)
981{
cd28ab6a
SH		 982 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
983 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
984 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
985 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
986 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
987 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 988
989 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 990}
991
793b883e
SH		 992static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
993{
994 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
995
cb5d9547 996 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 997 le->ctrl = 0;
793b883e
SH		 998 return le;
999}
cd28ab6a 1000
88f5f0ca
SH		 1001static void tx_init(struct sky2_port *sky2)
1002{
1003 struct sky2_tx_le *le;
1004
1005 sky2->tx_prod = sky2->tx_cons = 0;
1006 sky2->tx_tcpsum = 0;
1007 sky2->tx_last_mss = 0;
1008
1009 le = get_tx_le(sky2);
1010 le->addr = 0;
1011 le->opcode = OP_ADDR64 | HW_OWNER;
88f5f0ca
SH		 1012}
1013
291ea614
SH		 1014static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
1015 struct sky2_tx_le *le)
1016{
1017 return sky2->tx_ring + (le - sky2->tx_le);
1018}
1019
290d4de5
SH		 1020/* Update chip's next pointer */
1021static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1022{
50432cb5 1023 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1024 wmb();
50432cb5
SH		 1025 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1026
1027 /* Synchronize I/O on since next processor may write to tail */
1028 mmiowb();
cd28ab6a
SH		 1029}
1030
793b883e 1031
cd28ab6a
SH		 1032static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1033{
1034 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1035 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1036 le->ctrl = 0;
cd28ab6a
SH		 1037 return le;
1038}
1039
14d0263f
SH		 1040/* Build description to hardware for one receive segment */
1041static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1042 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1043{
1044 struct sky2_rx_le *le;
1045
86c6887e 1046 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1047 le = sky2_next_rx(sky2);
86c6887e 1048 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 }
793b883e 1051
cd28ab6a 1052 le = sky2_next_rx(sky2);
734d1868
SH		 1053 le->addr = cpu_to_le32((u32) map);
1054 le->length = cpu_to_le16(len);
14d0263f 1055 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1056}
1057
14d0263f
SH		 1058/* Build description to hardware for one possibly fragmented skb */
1059static void sky2_rx_submit(struct sky2_port *sky2,
1060 const struct rx_ring_info *re)
1061{
1062 int i;
1063
1064 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1065
1066 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1067 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1068}
1069
1070
454e6cb6 1071static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1072 unsigned size)
1073{
1074 struct sk_buff *skb = re->skb;
1075 int i;
1076
1077 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
454e6cb6
SH		 1078 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1079 return -EIO;
1080
14d0263f
SH		 1081 pci_unmap_len_set(re, data_size, size);
1082
1083 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1084 re->frag_addr[i] = pci_map_page(pdev,
1085 skb_shinfo(skb)->frags[i].page,
1086 skb_shinfo(skb)->frags[i].page_offset,
1087 skb_shinfo(skb)->frags[i].size,
1088 PCI_DMA_FROMDEVICE);
454e6cb6 1089 return 0;
14d0263f
SH		 1090}
1091
1092static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1093{
1094 struct sk_buff *skb = re->skb;
1095 int i;
1096
1097 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1098 PCI_DMA_FROMDEVICE);
1099
1100 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1101 pci_unmap_page(pdev, re->frag_addr[i],
1102 skb_shinfo(skb)->frags[i].size,
1103 PCI_DMA_FROMDEVICE);
1104}
793b883e 1105
cd28ab6a
SH		 1106/* Tell chip where to start receive checksum.
1107 * Actually has two checksums, but set both same to avoid possible byte
1108 * order problems.
1109 */
793b883e 1110static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1111{
ea76e635 1112 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1113
ea76e635
SH		 1114 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1115 le->ctrl = 0;
1116 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1117
ea76e635
SH		 1118 sky2_write32(sky2->hw,
1119 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1120 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1121}
1122
6b1a3aef
SH		 1123/*
1124 * The RX Stop command will not work for Yukon-2 if the BMU does not
1125 * reach the end of packet and since we can't make sure that we have
1126 * incoming data, we must reset the BMU while it is not doing a DMA
1127 * transfer. Since it is possible that the RX path is still active,
1128 * the RX RAM buffer will be stopped first, so any possible incoming
1129 * data will not trigger a DMA. After the RAM buffer is stopped, the
1130 * BMU is polled until any DMA in progress is ended and only then it
1131 * will be reset.
1132 */
1133static void sky2_rx_stop(struct sky2_port *sky2)
1134{
1135 struct sky2_hw *hw = sky2->hw;
1136 unsigned rxq = rxqaddr[sky2->port];
1137 int i;
1138
1139 /* disable the RAM Buffer receive queue */
1140 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1141
1142 for (i = 0; i < 0xffff; i++)
1143 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1144 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1145 goto stopped;
1146
1147 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1148 sky2->netdev->name);
1149stopped:
1150 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1151
1152 /* reset the Rx prefetch unit */
1153 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
50432cb5 1154 mmiowb();
6b1a3aef 1155}
793b883e 1156
d571b694 1157/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1158static void sky2_rx_clean(struct sky2_port *sky2)
1159{
1160 unsigned i;
1161
1162 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1163 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1164 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1165
1166 if (re->skb) {
14d0263f 1167 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1168 kfree_skb(re->skb);
1169 re->skb = NULL;
1170 }
1171 }
1172}
1173
ef743d33
SH		 1174/* Basic MII support */
1175static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1176{
1177 struct mii_ioctl_data *data = if_mii(ifr);
1178 struct sky2_port *sky2 = netdev_priv(dev);
1179 struct sky2_hw *hw = sky2->hw;
1180 int err = -EOPNOTSUPP;
1181
1182 if (!netif_running(dev))
1183 return -ENODEV; /* Phy still in reset */
1184
d89e1343 1185 switch (cmd) {
ef743d33
SH		 1186 case SIOCGMIIPHY:
1187 data->phy_id = PHY_ADDR_MARV;
1188
1189 /* fallthru */
1190 case SIOCGMIIREG: {
1191 u16 val = 0;
91c86df5 1192
e07b1aa8 1193 spin_lock_bh(&sky2->phy_lock);
ef743d33 1194 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1195 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1196
ef743d33
SH		 1197 data->val_out = val;
1198 break;
1199 }
1200
1201 case SIOCSMIIREG:
1202 if (!capable(CAP_NET_ADMIN))
1203 return -EPERM;
1204
e07b1aa8 1205 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1206 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1207 data->val_in);
e07b1aa8 1208 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1209 break;
1210 }
1211 return err;
1212}
1213
d1f13708 1214#ifdef SKY2_VLAN_TAG_USED
d494eacd 1215static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1216{
d494eacd 1217 if (onoff) {
3d4e66f5
SH		 1218 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1219 RX_VLAN_STRIP_ON);
1220 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1221 TX_VLAN_TAG_ON);
1222 } else {
1223 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1224 RX_VLAN_STRIP_OFF);
1225 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1226 TX_VLAN_TAG_OFF);
1227 }
d494eacd
SH		 1228}
1229
1230static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1231{
1232 struct sky2_port *sky2 = netdev_priv(dev);
1233 struct sky2_hw *hw = sky2->hw;
1234 u16 port = sky2->port;
1235
1236 netif_tx_lock_bh(dev);
1237 napi_disable(&hw->napi);
1238
1239 sky2->vlgrp = grp;
1240 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1241
d1d08d12 1242 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1243 napi_enable(&hw->napi);
2bb8c262 1244 netif_tx_unlock_bh(dev);
d1f13708
SH		 1245}
1246#endif
1247
82788c7a 1248/*
14d0263f
SH		 1249 * Allocate an skb for receiving. If the MTU is large enough
1250 * make the skb non-linear with a fragment list of pages.
82788c7a 1251 */
14d0263f 1252static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1253{
1254 struct sk_buff *skb;
14d0263f 1255 int i;
82788c7a 1256
39dbd958 1257 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1258 unsigned char *start;
1259 /*
1260 * Workaround for a bug in FIFO that cause hang
1261 * if the FIFO if the receive buffer is not 64 byte aligned.
1262 * The buffer returned from netdev_alloc_skb is
1263 * aligned except if slab debugging is enabled.
1264 */
1265 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1266 if (!skb)
1267 goto nomem;
1268 start = PTR_ALIGN(skb->data, 8);
1269 skb_reserve(skb, start - skb->data);
1270 } else {
1271 skb = netdev_alloc_skb(sky2->netdev,
1272 sky2->rx_data_size + NET_IP_ALIGN);
1273 if (!skb)
1274 goto nomem;
1275 skb_reserve(skb, NET_IP_ALIGN);
1276 }
14d0263f
SH		 1277
1278 for (i = 0; i < sky2->rx_nfrags; i++) {
1279 struct page *page = alloc_page(GFP_ATOMIC);
1280
1281 if (!page)
1282 goto free_partial;
1283 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1284 }
1285
1286 return skb;
14d0263f
SH		 1287free_partial:
1288 kfree_skb(skb);
1289nomem:
1290 return NULL;
82788c7a
SH		 1291}
1292
55c9dd35
SH		 1293static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1294{
1295 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1296}
1297
cd28ab6a
SH		 1298/*
1299 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1300 * Normal case this ends up creating one list element for skb
1301 * in the receive ring. Worst case if using large MTU and each
1302 * allocation falls on a different 64 bit region, that results
1303 * in 6 list elements per ring entry.
1304 * One element is used for checksum enable/disable, and one
1305 * extra to avoid wrap.
cd28ab6a 1306 */
6b1a3aef 1307static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1308{
6b1a3aef 1309 struct sky2_hw *hw = sky2->hw;
14d0263f 1310 struct rx_ring_info *re;
6b1a3aef 1311 unsigned rxq = rxqaddr[sky2->port];
5f06eba4 1312 unsigned i, size, thresh;
cd28ab6a 1313
6b1a3aef 1314 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1315 sky2_qset(hw, rxq);
977bdf06 1316
c3905bc4
SH		 1317 /* On PCI express lowering the watermark gives better performance */
1318 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1319 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1320
1321 /* These chips have no ram buffer?
1322 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1323 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1324 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1325 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
f449c7c1 1326 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1327
6b1a3aef
SH		 1328 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1329
ea76e635
SH		 1330 if (!(hw->flags & SKY2_HW_NEW_LE))
1331 rx_set_checksum(sky2);
14d0263f
SH		 1332
1333 /* Space needed for frame data + headers rounded up */
f957da2a 1334 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
14d0263f
SH		 1335
1336 /* Stopping point for hardware truncation */
1337 thresh = (size - 8) / sizeof(u32);
1338
5f06eba4 1339 sky2->rx_nfrags = size >> PAGE_SHIFT;
14d0263f
SH		 1340 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1341
5f06eba4
SH		 1342 /* Compute residue after pages */
1343 size -= sky2->rx_nfrags << PAGE_SHIFT;
14d0263f 1344
5f06eba4
SH		 1345 /* Optimize to handle small packets and headers */
1346 if (size < copybreak)
1347 size = copybreak;
1348 if (size < ETH_HLEN)
1349 size = ETH_HLEN;
14d0263f 1350
14d0263f
SH		 1351 sky2->rx_data_size = size;
1352
1353 /* Fill Rx ring */
793b883e 1354 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1355 re = sky2->rx_ring + i;
cd28ab6a 1356
14d0263f 1357 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1358 if (!re->skb)
1359 goto nomem;
1360
454e6cb6
SH		 1361 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1362 dev_kfree_skb(re->skb);
1363 re->skb = NULL;
1364 goto nomem;
1365 }
1366
14d0263f 1367 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1368 }
1369
a1433ac4
SH		 1370 /*
1371 * The receiver hangs if it receives frames larger than the
1372 * packet buffer. As a workaround, truncate oversize frames, but
1373 * the register is limited to 9 bits, so if you do frames > 2052
1374 * you better get the MTU right!
1375 */
a1433ac4
SH		 1376 if (thresh > 0x1ff)
1377 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1378 else {
1379 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1380 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1381 }
1382
6b1a3aef 1383 /* Tell chip about available buffers */
55c9dd35 1384 sky2_rx_update(sky2, rxq);
cd28ab6a
SH		 1385 return 0;
1386nomem:
1387 sky2_rx_clean(sky2);
1388 return -ENOMEM;
1389}
1390
1391/* Bring up network interface. */
1392static int sky2_up(struct net_device *dev)
1393{
1394 struct sky2_port *sky2 = netdev_priv(dev);
1395 struct sky2_hw *hw = sky2->hw;
1396 unsigned port = sky2->port;
e0c28116 1397 u32 imask, ramsize;
ee7abb04 1398 int cap, err = -ENOMEM;
843a46f4 1399 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1400
ee7abb04
SH		 1401 /*
1402 * On dual port PCI-X card, there is an problem where status
1403 * can be received out of order due to split transactions
843a46f4 1404 */
ee7abb04
SH		 1405 if (otherdev && netif_running(otherdev) &&
1406 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1407 u16 cmd;
1408
b32f40c4 1409 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1410 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4
SH		 1411 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1412
ee7abb04 1413 }
843a46f4 1414
55d7b4e6
SH		 1415 netif_carrier_off(dev);
1416
cd28ab6a
SH		 1417 /* must be power of 2 */
1418 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1419 TX_RING_SIZE *
1420 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1421 &sky2->tx_le_map);
1422 if (!sky2->tx_le)
1423 goto err_out;
1424
6cdbbdf3 1425 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1426 GFP_KERNEL);
1427 if (!sky2->tx_ring)
1428 goto err_out;
88f5f0ca
SH		 1429
1430 tx_init(sky2);
cd28ab6a
SH		 1431
1432 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1433 &sky2->rx_le_map);
1434 if (!sky2->rx_le)
1435 goto err_out;
1436 memset(sky2->rx_le, 0, RX_LE_BYTES);
1437
291ea614 1438 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1439 GFP_KERNEL);
1440 if (!sky2->rx_ring)
1441 goto err_out;
1442
1443 sky2_mac_init(hw, port);
1444
e0c28116
SH		 1445 /* Register is number of 4K blocks on internal RAM buffer. */
1446 ramsize = sky2_read8(hw, B2_E_0) * 4;
1447 if (ramsize > 0) {
67712901 1448 u32 rxspace;
cd28ab6a 1449
39dbd958 1450 hw->flags |= SKY2_HW_RAM_BUFFER;
e0c28116 1451 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
67712901
SH		 1452 if (ramsize < 16)
1453 rxspace = ramsize / 2;
1454 else
1455 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1456
67712901
SH		 1457 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1458 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1459
1460 /* Make sure SyncQ is disabled */
1461 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1462 RB_RST_SET);
1463 }
793b883e 1464
af4ed7e6 1465 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1466
69161611
SH		 1467 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1468 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1469 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1470
977bdf06 1471 /* Set almost empty threshold */
c2716fb4
SH		 1472 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1473 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1474 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1475
6b1a3aef
SH		 1476 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1477 TX_RING_SIZE - 1);
cd28ab6a 1478
d494eacd
SH		 1479#ifdef SKY2_VLAN_TAG_USED
1480 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1481#endif
1482
6b1a3aef 1483 err = sky2_rx_start(sky2);
6de16237 1484 if (err)
cd28ab6a
SH		 1485 goto err_out;
1486
cd28ab6a 1487 /* Enable interrupts from phy/mac for port */
e07b1aa8 1488 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1489 imask |= portirq_msk[port];
e07b1aa8
SH		 1490 sky2_write32(hw, B0_IMSK, imask);
1491
a7bffe72 1492 sky2_set_multicast(dev);
a11da890
AD		 1493
1494 if (netif_msg_ifup(sky2))
1495 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
cd28ab6a
SH		 1496 return 0;
1497
1498err_out:
1b537565 1499 if (sky2->rx_le) {
cd28ab6a
SH		 1500 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1501 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1502 sky2->rx_le = NULL;
1503 }
1504 if (sky2->tx_le) {
cd28ab6a
SH		 1505 pci_free_consistent(hw->pdev,
1506 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1507 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1508 sky2->tx_le = NULL;
1509 }
1510 kfree(sky2->tx_ring);
1511 kfree(sky2->rx_ring);
cd28ab6a 1512
1b537565
SH		 1513 sky2->tx_ring = NULL;
1514 sky2->rx_ring = NULL;
cd28ab6a
SH		 1515 return err;
1516}
1517
793b883e
SH		 1518/* Modular subtraction in ring */
1519static inline int tx_dist(unsigned tail, unsigned head)
1520{
cb5d9547 1521 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1522}
cd28ab6a 1523
793b883e
SH		 1524/* Number of list elements available for next tx */
1525static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1526{
793b883e 1527 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1528}
1529
793b883e 1530/* Estimate of number of transmit list elements required */
28bd181a 1531static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1532{
793b883e
SH		 1533 unsigned count;
1534
1535 count = sizeof(dma_addr_t) / sizeof(u32);
1536 count += skb_shinfo(skb)->nr_frags * count;
1537
89114afd 1538 if (skb_is_gso(skb))
793b883e
SH		 1539 ++count;
1540
84fa7933 1541 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1542 ++count;
1543
1544 return count;
cd28ab6a
SH		 1545}
1546
793b883e
SH		 1547/*
1548 * Put one packet in ring for transmit.
1549 * A single packet can generate multiple list elements, and
1550 * the number of ring elements will probably be less than the number
1551 * of list elements used.
1552 */
cd28ab6a
SH		 1553static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1554{
1555 struct sky2_port *sky2 = netdev_priv(dev);
1556 struct sky2_hw *hw = sky2->hw;
d1f13708 1557 struct sky2_tx_le *le = NULL;
6cdbbdf3 1558 struct tx_ring_info *re;
454e6cb6 1559 unsigned i, len, first_slot;
cd28ab6a 1560 dma_addr_t mapping;
cd28ab6a
SH		 1561 u16 mss;
1562 u8 ctrl;
1563
2bb8c262
SH		 1564 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1565 return NETDEV_TX_BUSY;
cd28ab6a 1566
cd28ab6a
SH		 1567 len = skb_headlen(skb);
1568 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1569
454e6cb6
SH		 1570 if (pci_dma_mapping_error(hw->pdev, mapping))
1571 goto mapping_error;
1572
1573 first_slot = sky2->tx_prod;
1574 if (unlikely(netif_msg_tx_queued(sky2)))
1575 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1576 dev->name, first_slot, skb->len);
1577
86c6887e
SH		 1578 /* Send high bits if needed */
1579 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1580 le = get_tx_le(sky2);
86c6887e 1581 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e 1582 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1583 }
cd28ab6a
SH		 1584
1585 /* Check for TCP Segmentation Offload */
7967168c 1586 mss = skb_shinfo(skb)->gso_size;
793b883e 1587 if (mss != 0) {
ea76e635
SH		 1588
1589 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1590 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1591
1592 if (mss != sky2->tx_last_mss) {
1593 le = get_tx_le(sky2);
1594 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1595
1596 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1597 le->opcode = OP_MSS | HW_OWNER;
1598 else
1599 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1600 sky2->tx_last_mss = mss;
1601 }
cd28ab6a
SH		 1602 }
1603
cd28ab6a 1604 ctrl = 0;
d1f13708
SH		 1605#ifdef SKY2_VLAN_TAG_USED
1606 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1607 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1608 if (!le) {
1609 le = get_tx_le(sky2);
f65b138c 1610 le->addr = 0;
d1f13708 1611 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1612 } else
1613 le->opcode |= OP_VLAN;
1614 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1615 ctrl |= INS_VLAN;
1616 }
1617#endif
1618
1619 /* Handle TCP checksum offload */
84fa7933 1620 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1621 /* On Yukon EX (some versions) encoding change. */
ea76e635 1622 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1623 ctrl |= CALSUM; /* auto checksum */
1624 else {
1625 const unsigned offset = skb_transport_offset(skb);
1626 u32 tcpsum;
1627
1628 tcpsum = offset << 16; /* sum start */
1629 tcpsum |= offset + skb->csum_offset; /* sum write */
1630
1631 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1632 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1633 ctrl |= UDPTCP;
1634
1635 if (tcpsum != sky2->tx_tcpsum) {
1636 sky2->tx_tcpsum = tcpsum;
1637
1638 le = get_tx_le(sky2);
1639 le->addr = cpu_to_le32(tcpsum);
1640 le->length = 0; /* initial checksum value */
1641 le->ctrl = 1; /* one packet */
1642 le->opcode = OP_TCPLISW | HW_OWNER;
1643 }
1d179332 1644 }
cd28ab6a
SH		 1645 }
1646
1647 le = get_tx_le(sky2);
f65b138c 1648 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1649 le->length = cpu_to_le16(len);
1650 le->ctrl = ctrl;
793b883e 1651 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1652
291ea614 1653 re = tx_le_re(sky2, le);
cd28ab6a 1654 re->skb = skb;
6cdbbdf3 1655 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1656 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1657
1658 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1659 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1660
1661 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1662 frag->size, PCI_DMA_TODEVICE);
86c6887e 1663
454e6cb6
SH		 1664 if (pci_dma_mapping_error(hw->pdev, mapping))
1665 goto mapping_unwind;
1666
86c6887e 1667 if (sizeof(dma_addr_t) > sizeof(u32)) {
793b883e 1668 le = get_tx_le(sky2);
86c6887e 1669 le->addr = cpu_to_le32(upper_32_bits(mapping));
793b883e
SH		 1670 le->ctrl = 0;
1671 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1672 }
1673
1674 le = get_tx_le(sky2);
f65b138c 1675 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1676 le->length = cpu_to_le16(frag->size);
1677 le->ctrl = ctrl;
793b883e 1678 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1679
291ea614
SH		 1680 re = tx_le_re(sky2, le);
1681 re->skb = skb;
1682 pci_unmap_addr_set(re, mapaddr, mapping);
1683 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1684 }
6cdbbdf3 1685
cd28ab6a
SH		 1686 le->ctrl |= EOP;
1687
97bda706
SH		 1688 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1689 netif_stop_queue(dev);
b19666d9 1690
290d4de5 1691 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1692
cd28ab6a
SH		 1693 dev->trans_start = jiffies;
1694 return NETDEV_TX_OK;
454e6cb6
SH		 1695
1696mapping_unwind:
1697 for (i = first_slot; i != sky2->tx_prod; i = RING_NEXT(i, TX_RING_SIZE)) {
1698 le = sky2->tx_le + i;
1699 re = sky2->tx_ring + i;
1700
1701 switch(le->opcode & ~HW_OWNER) {
1702 case OP_LARGESEND:
1703 case OP_PACKET:
1704 pci_unmap_single(hw->pdev,
1705 pci_unmap_addr(re, mapaddr),
1706 pci_unmap_len(re, maplen),
1707 PCI_DMA_TODEVICE);
1708 break;
1709 case OP_BUFFER:
1710 pci_unmap_page(hw->pdev, pci_unmap_addr(re, mapaddr),
1711 pci_unmap_len(re, maplen),
1712 PCI_DMA_TODEVICE);
1713 break;
1714 }
1715 }
1716
1717 sky2->tx_prod = first_slot;
1718mapping_error:
1719 if (net_ratelimit())
1720 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1721 dev_kfree_skb(skb);
1722 return NETDEV_TX_OK;
cd28ab6a
SH		 1723}
1724
cd28ab6a 1725/*
793b883e
SH		 1726 * Free ring elements from starting at tx_cons until "done"
1727 *
1728 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1729 * buffers so make sure not to free skb to early.
cd28ab6a 1730 */
d11c13e7 1731static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1732{
d11c13e7 1733 struct net_device *dev = sky2->netdev;
af2a58ac 1734 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1735 unsigned idx;
cd28ab6a 1736
0e3ff6aa 1737 BUG_ON(done >= TX_RING_SIZE);
2224795d 1738
291ea614
SH		 1739 for (idx = sky2->tx_cons; idx != done;
1740 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1741 struct sky2_tx_le *le = sky2->tx_le + idx;
1742 struct tx_ring_info *re = sky2->tx_ring + idx;
1743
1744 switch(le->opcode & ~HW_OWNER) {
1745 case OP_LARGESEND:
1746 case OP_PACKET:
1747 pci_unmap_single(pdev,
1748 pci_unmap_addr(re, mapaddr),
1749 pci_unmap_len(re, maplen),
1750 PCI_DMA_TODEVICE);
af2a58ac 1751 break;
291ea614
SH		 1752 case OP_BUFFER:
1753 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1754 pci_unmap_len(re, maplen),
734d1868 1755 PCI_DMA_TODEVICE);
291ea614
SH		 1756 break;
1757 }
1758
1759 if (le->ctrl & EOP) {
1760 if (unlikely(netif_msg_tx_done(sky2)))
1761 printk(KERN_DEBUG "%s: tx done %u\n",
1762 dev->name, idx);
3cf26753 1763
7138a0f5
SH		 1764 dev->stats.tx_packets++;
1765 dev->stats.tx_bytes += re->skb->len;
2bf56fe2 1766
794b2bd2 1767 dev_kfree_skb_any(re->skb);
3cf26753 1768 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
cd28ab6a 1769 }
793b883e 1770 }
793b883e 1771
291ea614 1772 sky2->tx_cons = idx;
50432cb5
SH		 1773 smp_mb();
1774
22e11703 1775 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1776 netif_wake_queue(dev);
cd28ab6a
SH		 1777}
1778
1779/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1780static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1781{
2bb8c262
SH		 1782 struct sky2_port *sky2 = netdev_priv(dev);
1783
1784 netif_tx_lock_bh(dev);
d11c13e7 1785 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1786 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1787}
1788
1789/* Network shutdown */
1790static int sky2_down(struct net_device *dev)
1791{
1792 struct sky2_port *sky2 = netdev_priv(dev);
1793 struct sky2_hw *hw = sky2->hw;
1794 unsigned port = sky2->port;
1795 u16 ctrl;
e07b1aa8 1796 u32 imask;
cd28ab6a 1797
1b537565
SH		 1798 /* Never really got started! */
1799 if (!sky2->tx_le)
1800 return 0;
1801
cd28ab6a
SH		 1802 if (netif_msg_ifdown(sky2))
1803 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1804
ebc646f6
SH		 1805 /* Disable port IRQ */
1806 imask = sky2_read32(hw, B0_IMSK);
1807 imask &= ~portirq_msk[port];
1808 sky2_write32(hw, B0_IMSK, imask);
1809
6de16237
SH		 1810 synchronize_irq(hw->pdev->irq);
1811
d3bcfbeb 1812 sky2_gmac_reset(hw, port);
793b883e 1813
cd28ab6a
SH		 1814 /* Stop transmitter */
1815 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1816 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1817
1818 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1819 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1820
1821 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1822 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1823 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1824
6de16237
SH		 1825 /* Make sure no packets are pending */
1826 napi_synchronize(&hw->napi);
1827
cd28ab6a
SH		 1828 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1829
1830 /* Workaround shared GMAC reset */
793b883e
SH		 1831 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1832 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1833 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1834
1835 /* Disable Force Sync bit and Enable Alloc bit */
1836 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1837 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1838
1839 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1840 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1841 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1842
1843 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1844 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1845 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1846
1847 /* Reset the Tx prefetch units */
1848 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1849 PREF_UNIT_RST_SET);
1850
1851 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1852
6b1a3aef 1853 sky2_rx_stop(sky2);
cd28ab6a
SH		 1854
1855 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1856 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1857
b96936da 1858 sky2_phy_power_down(hw, port);
d3bcfbeb 1859
d571b694 1860 /* turn off LED's */
cd28ab6a
SH		 1861 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1862
2bb8c262 1863 sky2_tx_clean(dev);
cd28ab6a
SH		 1864 sky2_rx_clean(sky2);
1865
1866 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1867 sky2->rx_le, sky2->rx_le_map);
1868 kfree(sky2->rx_ring);
1869
1870 pci_free_consistent(hw->pdev,
1871 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1872 sky2->tx_le, sky2->tx_le_map);
1873 kfree(sky2->tx_ring);
1874
1b537565
SH		 1875 sky2->tx_le = NULL;
1876 sky2->rx_le = NULL;
1877
1878 sky2->rx_ring = NULL;
1879 sky2->tx_ring = NULL;
1880
cd28ab6a
SH		 1881 return 0;
1882}
1883
1884static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1885{
ea76e635 1886 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 1887 return SPEED_1000;
1888
05745c4a
SH		 1889 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1890 if (aux & PHY_M_PS_SPEED_100)
1891 return SPEED_100;
1892 else
1893 return SPEED_10;
1894 }
cd28ab6a
SH		 1895
1896 switch (aux & PHY_M_PS_SPEED_MSK) {
1897 case PHY_M_PS_SPEED_1000:
1898 return SPEED_1000;
1899 case PHY_M_PS_SPEED_100:
1900 return SPEED_100;
1901 default:
1902 return SPEED_10;
1903 }
1904}
1905
1906static void sky2_link_up(struct sky2_port *sky2)
1907{
1908 struct sky2_hw *hw = sky2->hw;
1909 unsigned port = sky2->port;
1910 u16 reg;
16ad91e1
SH		 1911 static const char *fc_name[] = {
1912 [FC_NONE] = "none",
1913 [FC_TX] = "tx",
1914 [FC_RX] = "rx",
1915 [FC_BOTH] = "both",
1916 };
cd28ab6a 1917
cd28ab6a 1918 /* enable Rx/Tx */
2eaba1a2 1919 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1920 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1921 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1922
1923 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1924
1925 netif_carrier_on(sky2->netdev);
cd28ab6a 1926
75e80683 1927 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 1928
cd28ab6a 1929 /* Turn on link LED */
793b883e 1930 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1931 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1932
1933 if (netif_msg_link(sky2))
1934 printk(KERN_INFO PFX
d571b694 1935 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1936 sky2->netdev->name, sky2->speed,
1937 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1938 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1939}
1940
1941static void sky2_link_down(struct sky2_port *sky2)
1942{
1943 struct sky2_hw *hw = sky2->hw;
1944 unsigned port = sky2->port;
1945 u16 reg;
1946
1947 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1948
1949 reg = gma_read16(hw, port, GM_GP_CTRL);
1950 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1951 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1952
cd28ab6a 1953 netif_carrier_off(sky2->netdev);
cd28ab6a
SH		 1954
1955 /* Turn on link LED */
1956 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1957
1958 if (netif_msg_link(sky2))
1959 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1960
cd28ab6a
SH		 1961 sky2_phy_init(hw, port);
1962}
1963
16ad91e1
SH		 1964static enum flow_control sky2_flow(int rx, int tx)
1965{
1966 if (rx)
1967 return tx ? FC_BOTH : FC_RX;
1968 else
1969 return tx ? FC_TX : FC_NONE;
1970}
1971
793b883e
SH		 1972static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1973{
1974 struct sky2_hw *hw = sky2->hw;
1975 unsigned port = sky2->port;
da4c1ff4 1976 u16 advert, lpa;
793b883e 1977
da4c1ff4 1978 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1979 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1980 if (lpa & PHY_M_AN_RF) {
1981 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1982 return -1;
1983 }
1984
793b883e
SH		 1985 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1986 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1987 sky2->netdev->name);
1988 return -1;
1989 }
1990
793b883e 1991 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1992 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1993
da4c1ff4
SH		 1994 /* Since the pause result bits seem to in different positions on
1995 * different chips. look at registers.
1996 */
ea76e635 1997 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 1998 /* Shift for bits in fiber PHY */
1999 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2000 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2001
2002 if (advert & ADVERTISE_1000XPAUSE)
2003 advert |= ADVERTISE_PAUSE_CAP;
2004 if (advert & ADVERTISE_1000XPSE_ASYM)
2005 advert |= ADVERTISE_PAUSE_ASYM;
2006 if (lpa & LPA_1000XPAUSE)
2007 lpa |= LPA_PAUSE_CAP;
2008 if (lpa & LPA_1000XPAUSE_ASYM)
2009 lpa |= LPA_PAUSE_ASYM;
2010 }
793b883e 2011
da4c1ff4
SH		 2012 sky2->flow_status = FC_NONE;
2013 if (advert & ADVERTISE_PAUSE_CAP) {
2014 if (lpa & LPA_PAUSE_CAP)
2015 sky2->flow_status = FC_BOTH;
2016 else if (advert & ADVERTISE_PAUSE_ASYM)
2017 sky2->flow_status = FC_RX;
2018 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2019 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2020 sky2->flow_status = FC_TX;
2021 }
793b883e 2022
16ad91e1 2023 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 2024 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2025 sky2->flow_status = FC_NONE;
2eaba1a2 2026
da4c1ff4 2027 if (sky2->flow_status & FC_TX)
793b883e
SH		 2028 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2029 else
2030 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2031
2032 return 0;
2033}
cd28ab6a 2034
e07b1aa8
SH		 2035/* Interrupt from PHY */
2036static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2037{
e07b1aa8
SH		 2038 struct net_device *dev = hw->dev[port];
2039 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2040 u16 istatus, phystat;
2041
ebc646f6
SH		 2042 if (!netif_running(dev))
2043 return;
2044
e07b1aa8
SH		 2045 spin_lock(&sky2->phy_lock);
2046 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2047 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2048
cd28ab6a
SH		 2049 if (netif_msg_intr(sky2))
2050 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2051 sky2->netdev->name, istatus, phystat);
2052
2eaba1a2 2053 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 2054 if (sky2_autoneg_done(sky2, phystat) == 0)
2055 sky2_link_up(sky2);
2056 goto out;
2057 }
cd28ab6a 2058
793b883e
SH		 2059 if (istatus & PHY_M_IS_LSP_CHANGE)
2060 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2061
793b883e
SH		 2062 if (istatus & PHY_M_IS_DUP_CHANGE)
2063 sky2->duplex =
2064 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2065
793b883e
SH		 2066 if (istatus & PHY_M_IS_LST_CHANGE) {
2067 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2068 sky2_link_up(sky2);
793b883e
SH		 2069 else
2070 sky2_link_down(sky2);
cd28ab6a 2071 }
793b883e 2072out:
e07b1aa8 2073 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2074}
2075
62335ab0 2076/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2077 * and tx queue is full (stopped).
2078 */
cd28ab6a
SH		 2079static void sky2_tx_timeout(struct net_device *dev)
2080{
2081 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2082 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 2083
2084 if (netif_msg_timer(sky2))
2085 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2086
8f24664d 2087 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 2088 dev->name, sky2->tx_cons, sky2->tx_prod,
2089 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2090 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2091
81906791
SH		 2092 /* can't restart safely under softirq */
2093 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2094}
2095
2096static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2097{
6b1a3aef
SH		 2098 struct sky2_port *sky2 = netdev_priv(dev);
2099 struct sky2_hw *hw = sky2->hw;
b628ed98 2100 unsigned port = sky2->port;
6b1a3aef
SH		 2101 int err;
2102 u16 ctl, mode;
e07b1aa8 2103 u32 imask;
cd28ab6a
SH		 2104
2105 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2106 return -EINVAL;
2107
05745c4a
SH		 2108 if (new_mtu > ETH_DATA_LEN &&
2109 (hw->chip_id == CHIP_ID_YUKON_FE ||
2110 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2111 return -EINVAL;
2112
6b1a3aef
SH		 2113 if (!netif_running(dev)) {
2114 dev->mtu = new_mtu;
2115 return 0;
2116 }
2117
e07b1aa8 2118 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2119 sky2_write32(hw, B0_IMSK, 0);
2120
018d1c66
SH		 2121 dev->trans_start = jiffies; /* prevent tx timeout */
2122 netif_stop_queue(dev);
bea3348e 2123 napi_disable(&hw->napi);
018d1c66 2124
e07b1aa8
SH		 2125 synchronize_irq(hw->pdev->irq);
2126
39dbd958 2127 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2128 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2129
2130 ctl = gma_read16(hw, port, GM_GP_CTRL);
2131 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2132 sky2_rx_stop(sky2);
2133 sky2_rx_clean(sky2);
cd28ab6a
SH		 2134
2135 dev->mtu = new_mtu;
14d0263f 2136
6b1a3aef
SH		 2137 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2138 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2139
2140 if (dev->mtu > ETH_DATA_LEN)
2141 mode |= GM_SMOD_JUMBO_ENA;
2142
b628ed98 2143 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2144
b628ed98 2145 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2146
6b1a3aef 2147 err = sky2_rx_start(sky2);
e07b1aa8 2148 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2149
d1d08d12 2150 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2151 napi_enable(&hw->napi);
2152
1b537565
SH		 2153 if (err)
2154 dev_close(dev);
2155 else {
b628ed98 2156 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2157
1b537565
SH		 2158 netif_wake_queue(dev);
2159 }
2160
cd28ab6a
SH		 2161 return err;
2162}
2163
14d0263f
SH		 2164/* For small just reuse existing skb for next receive */
2165static struct sk_buff *receive_copy(struct sky2_port *sky2,
2166 const struct rx_ring_info *re,
2167 unsigned length)
2168{
2169 struct sk_buff *skb;
2170
2171 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2172 if (likely(skb)) {
2173 skb_reserve(skb, 2);
2174 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2175 length, PCI_DMA_FROMDEVICE);
d626f62b 2176 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2177 skb->ip_summed = re->skb->ip_summed;
2178 skb->csum = re->skb->csum;
2179 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2180 length, PCI_DMA_FROMDEVICE);
2181 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2182 skb_put(skb, length);
14d0263f
SH		 2183 }
2184 return skb;
2185}
2186
2187/* Adjust length of skb with fragments to match received data */
2188static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2189 unsigned int length)
2190{
2191 int i, num_frags;
2192 unsigned int size;
2193
2194 /* put header into skb */
2195 size = min(length, hdr_space);
2196 skb->tail += size;
2197 skb->len += size;
2198 length -= size;
2199
2200 num_frags = skb_shinfo(skb)->nr_frags;
2201 for (i = 0; i < num_frags; i++) {
2202 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2203
2204 if (length == 0) {
2205 /* don't need this page */
2206 __free_page(frag->page);
2207 --skb_shinfo(skb)->nr_frags;
2208 } else {
2209 size = min(length, (unsigned) PAGE_SIZE);
2210
2211 frag->size = size;
2212 skb->data_len += size;
2213 skb->truesize += size;
2214 skb->len += size;
2215 length -= size;
2216 }
2217 }
2218}
2219
2220/* Normal packet - take skb from ring element and put in a new one */
2221static struct sk_buff *receive_new(struct sky2_port *sky2,
2222 struct rx_ring_info *re,
2223 unsigned int length)
2224{
2225 struct sk_buff *skb, *nskb;
2226 unsigned hdr_space = sky2->rx_data_size;
2227
14d0263f
SH		 2228 /* Don't be tricky about reusing pages (yet) */
2229 nskb = sky2_rx_alloc(sky2);
2230 if (unlikely(!nskb))
2231 return NULL;
2232
2233 skb = re->skb;
2234 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2235
2236 prefetch(skb->data);
2237 re->skb = nskb;
454e6cb6
SH		 2238 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2239 dev_kfree_skb(nskb);
2240 re->skb = skb;
2241 return NULL;
2242 }
14d0263f
SH		 2243
2244 if (skb_shinfo(skb)->nr_frags)
2245 skb_put_frags(skb, hdr_space, length);
2246 else
489b10c1 2247 skb_put(skb, length);
14d0263f
SH		 2248 return skb;
2249}
2250
cd28ab6a
SH		 2251/*
2252 * Receive one packet.
d571b694 2253 * For larger packets, get new buffer.
cd28ab6a 2254 */
497d7c86 2255static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2256 u16 length, u32 status)
2257{
497d7c86 2258 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2259 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2260 struct sk_buff *skb = NULL;
d6532232
SH		 2261 u16 count = (status & GMR_FS_LEN) >> 16;
2262
2263#ifdef SKY2_VLAN_TAG_USED
2264 /* Account for vlan tag */
2265 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2266 count -= VLAN_HLEN;
2267#endif
cd28ab6a
SH		 2268
2269 if (unlikely(netif_msg_rx_status(sky2)))
2270 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2271 dev->name, sky2->rx_next, status, length);
cd28ab6a 2272
793b883e 2273 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2274 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2275
3b12e014
SH		 2276 /* This chip has hardware problems that generates bogus status.
2277 * So do only marginal checking and expect higher level protocols
2278 * to handle crap frames.
2279 */
2280 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2281 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2282 length != count)
2283 goto okay;
2284
42eeea01 2285 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2286 goto error;
2287
42eeea01
SH		 2288 if (!(status & GMR_FS_RX_OK))
2289 goto resubmit;
2290
d6532232
SH		 2291 /* if length reported by DMA does not match PHY, packet was truncated */
2292 if (length != count)
3b12e014 2293 goto len_error;
71749531 2294
3b12e014 2295okay:
14d0263f
SH		 2296 if (length < copybreak)
2297 skb = receive_copy(sky2, re, length);
2298 else
2299 skb = receive_new(sky2, re, length);
793b883e 2300resubmit:
14d0263f 2301 sky2_rx_submit(sky2, re);
79e57d32 2302
cd28ab6a
SH		 2303 return skb;
2304
3b12e014 2305len_error:
71749531
SH		 2306 /* Truncation of overlength packets
2307 causes PHY length to not match MAC length */
7138a0f5 2308 ++dev->stats.rx_length_errors;
d6532232 2309 if (netif_msg_rx_err(sky2) && net_ratelimit())
3b12e014
SH		 2310 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2311 dev->name, status, length);
d6532232 2312 goto resubmit;
71749531 2313
cd28ab6a 2314error:
7138a0f5 2315 ++dev->stats.rx_errors;
b6d77734 2316 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2317 dev->stats.rx_over_errors++;
b6d77734
SH		 2318 goto resubmit;
2319 }
6e15b712 2320
3be92a70 2321 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2322 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2323 dev->name, status, length);
793b883e
SH		 2324
2325 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2326 dev->stats.rx_length_errors++;
cd28ab6a 2327 if (status & GMR_FS_FRAGMENT)
7138a0f5 2328 dev->stats.rx_frame_errors++;
cd28ab6a 2329 if (status & GMR_FS_CRC_ERR)
7138a0f5 2330 dev->stats.rx_crc_errors++;
79e57d32 2331
793b883e 2332 goto resubmit;
cd28ab6a
SH		 2333}
2334
e07b1aa8
SH		 2335/* Transmit complete */
2336static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2337{
e07b1aa8 2338 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2339
e07b1aa8 2340 if (netif_running(dev)) {
2bb8c262 2341 netif_tx_lock(dev);
e07b1aa8 2342 sky2_tx_complete(sky2, last);
2bb8c262 2343 netif_tx_unlock(dev);
2224795d 2344 }
cd28ab6a
SH		 2345}
2346
e07b1aa8 2347/* Process status response ring */
26691830 2348static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2349{
e07b1aa8 2350 int work_done = 0;
55c9dd35 2351 unsigned rx[2] = { 0, 0 };
a8fd6266 2352
af2a58ac 2353 rmb();
26691830 2354 do {
55c9dd35 2355 struct sky2_port *sky2;
13210ce5 2356 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2357 unsigned port;
13210ce5 2358 struct net_device *dev;
cd28ab6a 2359 struct sk_buff *skb;
cd28ab6a
SH		 2360 u32 status;
2361 u16 length;
ab5adecb
SH		 2362 u8 opcode = le->opcode;
2363
2364 if (!(opcode & HW_OWNER))
2365 break;
cd28ab6a 2366
cb5d9547 2367 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2368
ab5adecb 2369 port = le->css & CSS_LINK_BIT;
69161611 2370 dev = hw->dev[port];
13210ce5 2371 sky2 = netdev_priv(dev);
f65b138c
SH		 2372 length = le16_to_cpu(le->length);
2373 status = le32_to_cpu(le->status);
cd28ab6a 2374
ab5adecb
SH		 2375 le->opcode = 0;
2376 switch (opcode & ~HW_OWNER) {
cd28ab6a 2377 case OP_RXSTAT:
55c9dd35 2378 ++rx[port];
497d7c86 2379 skb = sky2_receive(dev, length, status);
3225b919 2380 if (unlikely(!skb)) {
7138a0f5 2381 dev->stats.rx_dropped++;
55c9dd35 2382 break;
3225b919 2383 }
13210ce5 2384
69161611 2385 /* This chip reports checksum status differently */
05745c4a 2386 if (hw->flags & SKY2_HW_NEW_LE) {
69161611
SH		 2387 if (sky2->rx_csum &&
2388 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2389 (le->css & CSS_TCPUDPCSOK))
2390 skb->ip_summed = CHECKSUM_UNNECESSARY;
2391 else
2392 skb->ip_summed = CHECKSUM_NONE;
2393 }
2394
13210ce5 2395 skb->protocol = eth_type_trans(skb, dev);
7138a0f5
SH		 2396 dev->stats.rx_packets++;
2397 dev->stats.rx_bytes += skb->len;
13210ce5
SH		 2398 dev->last_rx = jiffies;
2399
d1f13708
SH		 2400#ifdef SKY2_VLAN_TAG_USED
2401 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2402 vlan_hwaccel_receive_skb(skb,
2403 sky2->vlgrp,
2404 be16_to_cpu(sky2->rx_tag));
2405 } else
2406#endif
cd28ab6a 2407 netif_receive_skb(skb);
13210ce5 2408
22e11703 2409 /* Stop after net poll weight */
13210ce5
SH		 2410 if (++work_done >= to_do)
2411 goto exit_loop;
cd28ab6a
SH		 2412 break;
2413
d1f13708
SH		 2414#ifdef SKY2_VLAN_TAG_USED
2415 case OP_RXVLAN:
2416 sky2->rx_tag = length;
2417 break;
2418
2419 case OP_RXCHKSVLAN:
2420 sky2->rx_tag = length;
2421 /* fall through */
2422#endif
cd28ab6a 2423 case OP_RXCHKS:
87418307
SH		 2424 if (!sky2->rx_csum)
2425 break;
2426
05745c4a
SH		 2427 /* If this happens then driver assuming wrong format */
2428 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2429 if (net_ratelimit())
2430 printk(KERN_NOTICE "%s: unexpected"
2431 " checksum status\n",
2432 dev->name);
69161611 2433 break;
05745c4a 2434 }
69161611 2435
87418307
SH		 2436 /* Both checksum counters are programmed to start at
2437 * the same offset, so unless there is a problem they
2438 * should match. This failure is an early indication that
2439 * hardware receive checksumming won't work.
2440 */
2441 if (likely(status >> 16 == (status & 0xffff))) {
2442 skb = sky2->rx_ring[sky2->rx_next].skb;
2443 skb->ip_summed = CHECKSUM_COMPLETE;
2444 skb->csum = status & 0xffff;
2445 } else {
2446 printk(KERN_NOTICE PFX "%s: hardware receive "
2447 "checksum problem (status = %#x)\n",
2448 dev->name, status);
2449 sky2->rx_csum = 0;
2450 sky2_write32(sky2->hw,
69161611 2451 Q_ADDR(rxqaddr[port], Q_CSR),
87418307
SH		 2452 BMU_DIS_RX_CHKSUM);
2453 }
cd28ab6a
SH		 2454 break;
2455
2456 case OP_TXINDEXLE:
13b97b74 2457 /* TX index reports status for both ports */
f55925d7
SH		 2458 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2459 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2460 if (hw->dev[1])
2461 sky2_tx_done(hw->dev[1],
2462 ((status >> 24) & 0xff)
2463 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2464 break;
2465
cd28ab6a
SH		 2466 default:
2467 if (net_ratelimit())
793b883e 2468 printk(KERN_WARNING PFX
ab5adecb 2469 "unknown status opcode 0x%x\n", opcode);
cd28ab6a 2470 }
26691830 2471 } while (hw->st_idx != idx);
cd28ab6a 2472
fe2a24df
SH		 2473 /* Fully processed status ring so clear irq */
2474 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2475
13210ce5 2476exit_loop:
55c9dd35
SH		 2477 if (rx[0])
2478 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
22e11703 2479
55c9dd35
SH		 2480 if (rx[1])
2481 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
22e11703 2482
e07b1aa8 2483 return work_done;
cd28ab6a
SH		 2484}
2485
2486static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2487{
2488 struct net_device *dev = hw->dev[port];
2489
3be92a70
SH		 2490 if (net_ratelimit())
2491 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2492 dev->name, status);
cd28ab6a
SH		 2493
2494 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2495 if (net_ratelimit())
2496 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2497 dev->name);
cd28ab6a
SH		 2498 /* Clear IRQ */
2499 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2500 }
2501
2502 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2503 if (net_ratelimit())
2504 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2505 dev->name);
cd28ab6a
SH		 2506
2507 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2508 }
2509
2510 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2511 if (net_ratelimit())
2512 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2513 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2514 }
2515
2516 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2517 if (net_ratelimit())
2518 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2519 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2520 }
2521
2522 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2523 if (net_ratelimit())
2524 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2525 dev->name);
cd28ab6a
SH		 2526 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2527 }
2528}
2529
2530static void sky2_hw_intr(struct sky2_hw *hw)
2531{
555382cb 2532 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2533 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2534 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2535
2536 status &= hwmsk;
cd28ab6a 2537
793b883e 2538 if (status & Y2_IS_TIST_OV)
cd28ab6a 2539 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2540
2541 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2542 u16 pci_err;
2543
82637e80 2544 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2545 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2546 if (net_ratelimit())
555382cb 2547 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2548 pci_err);
cd28ab6a 2549
b32f40c4 2550 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2551 pci_err | PCI_STATUS_ERROR_BITS);
82637e80 2552 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2553 }
2554
2555 if (status & Y2_IS_PCI_EXP) {
d571b694 2556 /* PCI-Express uncorrectable Error occurred */
555382cb 2557 u32 err;
cd28ab6a 2558
82637e80 2559 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2560 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2561 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2562 0xfffffffful);
3be92a70 2563 if (net_ratelimit())
555382cb 2564 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2565
7782c8c4 2566 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
82637e80 2567 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2568 }
2569
2570 if (status & Y2_HWE_L1_MASK)
2571 sky2_hw_error(hw, 0, status);
2572 status >>= 8;
2573 if (status & Y2_HWE_L1_MASK)
2574 sky2_hw_error(hw, 1, status);
2575}
2576
2577static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2578{
2579 struct net_device *dev = hw->dev[port];
2580 struct sky2_port *sky2 = netdev_priv(dev);
2581 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2582
2583 if (netif_msg_intr(sky2))
2584 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2585 dev->name, status);
2586
a3caeada
SH		 2587 if (status & GM_IS_RX_CO_OV)
2588 gma_read16(hw, port, GM_RX_IRQ_SRC);
2589
2590 if (status & GM_IS_TX_CO_OV)
2591 gma_read16(hw, port, GM_TX_IRQ_SRC);
2592
cd28ab6a 2593 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2594 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2595 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2596 }
2597
2598 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2599 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2600 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2601 }
cd28ab6a
SH		 2602}
2603
40b01727
SH		 2604/* This should never happen it is a bug. */
2605static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2606 u16 q, unsigned ring_size)
d257924e
SH		 2607{
2608 struct net_device *dev = hw->dev[port];
2609 struct sky2_port *sky2 = netdev_priv(dev);
40b01727
SH		 2610 unsigned idx;
2611 const u64 *le = (q == Q_R1 || q == Q_R2)
2612 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
d257924e 2613
40b01727
SH		 2614 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2615 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2616 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2617 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2618
40b01727 2619 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2620}
cd28ab6a 2621
75e80683
SH		 2622static int sky2_rx_hung(struct net_device *dev)
2623{
2624 struct sky2_port *sky2 = netdev_priv(dev);
2625 struct sky2_hw *hw = sky2->hw;
2626 unsigned port = sky2->port;
2627 unsigned rxq = rxqaddr[port];
2628 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2629 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2630 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2631 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2632
2633 /* If idle and MAC or PCI is stuck */
2634 if (sky2->check.last == dev->last_rx &&
2635 ((mac_rp == sky2->check.mac_rp &&
2636 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2637 /* Check if the PCI RX hang */
2638 (fifo_rp == sky2->check.fifo_rp &&
2639 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2640 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2641 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2642 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2643 return 1;
2644 } else {
2645 sky2->check.last = dev->last_rx;
2646 sky2->check.mac_rp = mac_rp;
2647 sky2->check.mac_lev = mac_lev;
2648 sky2->check.fifo_rp = fifo_rp;
2649 sky2->check.fifo_lev = fifo_lev;
2650 return 0;
2651 }
2652}
2653
32c2c300 2654static void sky2_watchdog(unsigned long arg)
d27ed387 2655{
01bd7564 2656 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2657
75e80683 2658 /* Check for lost IRQ once a second */
32c2c300 2659 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2660 napi_schedule(&hw->napi);
75e80683
SH		 2661 } else {
2662 int i, active = 0;
2663
2664 for (i = 0; i < hw->ports; i++) {
bea3348e 2665 struct net_device *dev = hw->dev[i];
75e80683
SH		 2666 if (!netif_running(dev))
2667 continue;
2668 ++active;
2669
2670 /* For chips with Rx FIFO, check if stuck */
39dbd958 2671 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683
SH		 2672 sky2_rx_hung(dev)) {
2673 pr_info(PFX "%s: receiver hang detected\n",
2674 dev->name);
2675 schedule_work(&hw->restart_work);
2676 return;
2677 }
2678 }
2679
2680 if (active == 0)
2681 return;
32c2c300 2682 }
01bd7564 2683
75e80683 2684 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2685}
2686
40b01727
SH		 2687/* Hardware/software error handling */
2688static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2689{
40b01727
SH		 2690 if (net_ratelimit())
2691 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2692
1e5f1283
SH		 2693 if (status & Y2_IS_HW_ERR)
2694 sky2_hw_intr(hw);
d257924e 2695
1e5f1283
SH		 2696 if (status & Y2_IS_IRQ_MAC1)
2697 sky2_mac_intr(hw, 0);
cd28ab6a 2698
1e5f1283
SH		 2699 if (status & Y2_IS_IRQ_MAC2)
2700 sky2_mac_intr(hw, 1);
cd28ab6a 2701
1e5f1283 2702 if (status & Y2_IS_CHK_RX1)
40b01727 2703 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
d257924e 2704
1e5f1283 2705 if (status & Y2_IS_CHK_RX2)
40b01727 2706 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
d257924e 2707
1e5f1283 2708 if (status & Y2_IS_CHK_TXA1)
40b01727 2709 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
d257924e 2710
1e5f1283 2711 if (status & Y2_IS_CHK_TXA2)
40b01727
SH		 2712 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2713}
2714
bea3348e 2715static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2716{
bea3348e 2717 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2718 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2719 int work_done = 0;
26691830 2720 u16 idx;
40b01727
SH		 2721
2722 if (unlikely(status & Y2_IS_ERROR))
2723 sky2_err_intr(hw, status);
2724
2725 if (status & Y2_IS_IRQ_PHY1)
2726 sky2_phy_intr(hw, 0);
2727
2728 if (status & Y2_IS_IRQ_PHY2)
2729 sky2_phy_intr(hw, 1);
cd28ab6a 2730
26691830
SH		 2731 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2732 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2733
2734 if (work_done >= work_limit)
26691830
SH		 2735 goto done;
2736 }
6f535763 2737
26691830
SH		 2738 napi_complete(napi);
2739 sky2_read32(hw, B0_Y2_SP_LISR);
2740done:
6f535763 2741
bea3348e 2742 return work_done;
e07b1aa8
SH		 2743}
2744
7d12e780 2745static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2746{
2747 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2748 u32 status;
2749
2750 /* Reading this mask interrupts as side effect */
2751 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2752 if (status == 0 || status == ~0)
2753 return IRQ_NONE;
793b883e 2754
e07b1aa8 2755 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2756
2757 napi_schedule(&hw->napi);
793b883e 2758
cd28ab6a
SH		 2759 return IRQ_HANDLED;
2760}
2761
2762#ifdef CONFIG_NET_POLL_CONTROLLER
2763static void sky2_netpoll(struct net_device *dev)
2764{
2765 struct sky2_port *sky2 = netdev_priv(dev);
2766
bea3348e 2767 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2768}
2769#endif
2770
2771/* Chip internal frequency for clock calculations */
05745c4a 2772static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2773{
793b883e 2774 switch (hw->chip_id) {
cd28ab6a 2775 case CHIP_ID_YUKON_EC:
5a5b1ea0 2776 case CHIP_ID_YUKON_EC_U:
93745494 2777 case CHIP_ID_YUKON_EX:
ed4d4161 2778 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2779 case CHIP_ID_YUKON_UL_2:
05745c4a
SH		 2780 return 125;
2781
cd28ab6a 2782 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2783 return 100;
2784
2785 case CHIP_ID_YUKON_FE_P:
2786 return 50;
2787
2788 case CHIP_ID_YUKON_XL:
2789 return 156;
2790
2791 default:
2792 BUG();
cd28ab6a
SH		 2793 }
2794}
2795
fb17358f 2796static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2797{
fb17358f 2798 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2799}
2800
fb17358f 2801static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2802{
fb17358f 2803 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2804}
2805
fb17358f 2806
e3173832 2807static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2808{
b89165f2 2809 u8 t8;
cd28ab6a 2810
167f53d0 2811 /* Enable all clocks and check for bad PCI access */
b32f40c4 2812 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 2813
cd28ab6a 2814 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2815
cd28ab6a 2816 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 2817 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2818
2819 switch(hw->chip_id) {
2820 case CHIP_ID_YUKON_XL:
39dbd958 2821 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
ea76e635
SH		 2822 break;
2823
2824 case CHIP_ID_YUKON_EC_U:
2825 hw->flags = SKY2_HW_GIGABIT
2826 | SKY2_HW_NEWER_PHY
2827 | SKY2_HW_ADV_POWER_CTL;
2828 break;
2829
2830 case CHIP_ID_YUKON_EX:
2831 hw->flags = SKY2_HW_GIGABIT
2832 | SKY2_HW_NEWER_PHY
2833 | SKY2_HW_NEW_LE
2834 | SKY2_HW_ADV_POWER_CTL;
2835
2836 /* New transmit checksum */
2837 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2838 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2839 break;
2840
2841 case CHIP_ID_YUKON_EC:
2842 /* This rev is really old, and requires untested workarounds */
2843 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2844 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2845 return -EOPNOTSUPP;
2846 }
39dbd958 2847 hw->flags = SKY2_HW_GIGABIT;
ea76e635
SH		 2848 break;
2849
2850 case CHIP_ID_YUKON_FE:
ea76e635
SH		 2851 break;
2852
05745c4a
SH		 2853 case CHIP_ID_YUKON_FE_P:
2854 hw->flags = SKY2_HW_NEWER_PHY
2855 | SKY2_HW_NEW_LE
2856 | SKY2_HW_AUTO_TX_SUM
2857 | SKY2_HW_ADV_POWER_CTL;
2858 break;
ed4d4161
SH		 2859
2860 case CHIP_ID_YUKON_SUPR:
2861 hw->flags = SKY2_HW_GIGABIT
2862 | SKY2_HW_NEWER_PHY
2863 | SKY2_HW_NEW_LE
2864 | SKY2_HW_AUTO_TX_SUM
2865 | SKY2_HW_ADV_POWER_CTL;
2866 break;
2867
0ce8b98d
SH		 2868 case CHIP_ID_YUKON_UL_2:
2869 hw->flags = SKY2_HW_GIGABIT
2870 | SKY2_HW_ADV_POWER_CTL;
2871 break;
2872
ea76e635 2873 default:
b02a9258
SH		 2874 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2875 hw->chip_id);
cd28ab6a
SH		 2876 return -EOPNOTSUPP;
2877 }
2878
ea76e635
SH		 2879 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2880 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2881 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 2882
e3173832
SH		 2883 hw->ports = 1;
2884 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2885 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2886 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2887 ++hw->ports;
2888 }
2889
2890 return 0;
2891}
2892
2893static void sky2_reset(struct sky2_hw *hw)
2894{
555382cb 2895 struct pci_dev *pdev = hw->pdev;
e3173832 2896 u16 status;
555382cb
SH		 2897 int i, cap;
2898 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 2899
cd28ab6a 2900 /* disable ASF */
4f44d8ba
SH		 2901 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2902 status = sky2_read16(hw, HCU_CCSR);
2903 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2904 HCU_CCSR_UC_STATE_MSK);
2905 sky2_write16(hw, HCU_CCSR, status);
2906 } else
2907 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2908 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 2909
2910 /* do a SW reset */
2911 sky2_write8(hw, B0_CTST, CS_RST_SET);
2912 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2913
ac93a394
SH		 2914 /* allow writes to PCI config */
2915 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2916
cd28ab6a 2917 /* clear PCI errors, if any */
b32f40c4 2918 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 2919 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 2920 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 2921
2922 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2923
555382cb
SH		 2924 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2925 if (cap) {
7782c8c4
SH		 2926 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2927 0xfffffffful);
555382cb
SH		 2928
2929 /* If error bit is stuck on ignore it */
2930 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2931 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 2932 else
555382cb
SH		 2933 hwe_mask |= Y2_IS_PCI_EXP;
2934 }
cd28ab6a 2935
ae306cca 2936 sky2_power_on(hw);
82637e80 2937 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2938
2939 for (i = 0; i < hw->ports; i++) {
2940 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2941 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 2942
ed4d4161
SH		 2943 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2944 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 2945 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2946 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2947 | GMC_BYP_RETR_ON);
cd28ab6a
SH		 2948 }
2949
793b883e
SH		 2950 /* Clear I2C IRQ noise */
2951 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2952
2953 /* turn off hardware timer (unused) */
2954 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2955 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2956
cd28ab6a
SH		 2957 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2958
69634ee7
SH		 2959 /* Turn off descriptor polling */
2960 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2961
2962 /* Turn off receive timestamp */
2963 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2964 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2965
2966 /* enable the Tx Arbiters */
2967 for (i = 0; i < hw->ports; i++)
2968 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2969
2970 /* Initialize ram interface */
2971 for (i = 0; i < hw->ports; i++) {
793b883e 2972 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2973
2974 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2975 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2976 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2977 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2978 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2979 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2980 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2981 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2982 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2983 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2984 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2985 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2986 }
2987
555382cb 2988 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 2989
cd28ab6a 2990 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2991 sky2_gmac_reset(hw, i);
cd28ab6a 2992
cd28ab6a
SH		 2993 memset(hw->st_le, 0, STATUS_LE_BYTES);
2994 hw->st_idx = 0;
2995
2996 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2997 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2998
2999 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3000 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3001
3002 /* Set the list last index */
793b883e 3003 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 3004
290d4de5
SH		 3005 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3006 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3007
290d4de5
SH		 3008 /* set Status-FIFO ISR watermark */
3009 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3010 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3011 else
3012 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3013
290d4de5 3014 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3015 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3016 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3017
793b883e 3018 /* enable status unit */
cd28ab6a
SH		 3019 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3020
3021 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3022 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3023 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3024}
3025
81906791
SH		 3026static void sky2_restart(struct work_struct *work)
3027{
3028 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3029 struct net_device *dev;
3030 int i, err;
3031
81906791 3032 rtnl_lock();
81906791
SH		 3033 for (i = 0; i < hw->ports; i++) {
3034 dev = hw->dev[i];
3035 if (netif_running(dev))
3036 sky2_down(dev);
3037 }
3038
8cfcbe99
SH		 3039 napi_disable(&hw->napi);
3040 sky2_write32(hw, B0_IMSK, 0);
81906791
SH		 3041 sky2_reset(hw);
3042 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 3043 napi_enable(&hw->napi);
81906791
SH		 3044
3045 for (i = 0; i < hw->ports; i++) {
3046 dev = hw->dev[i];
3047 if (netif_running(dev)) {
3048 err = sky2_up(dev);
3049 if (err) {
3050 printk(KERN_INFO PFX "%s: could not restart %d\n",
3051 dev->name, err);
3052 dev_close(dev);
3053 }
3054 }
3055 }
3056
81906791
SH		 3057 rtnl_unlock();
3058}
3059
e3173832
SH		 3060static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3061{
3062 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3063}
3064
3065static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3066{
3067 const struct sky2_port *sky2 = netdev_priv(dev);
3068
3069 wol->supported = sky2_wol_supported(sky2->hw);
3070 wol->wolopts = sky2->wol;
3071}
3072
3073static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3074{
3075 struct sky2_port *sky2 = netdev_priv(dev);
3076 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3077
9d731d77
RW		 3078 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw))
3079 || !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3080 return -EOPNOTSUPP;
3081
3082 sky2->wol = wol->wolopts;
3083
05745c4a
SH		 3084 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3085 hw->chip_id == CHIP_ID_YUKON_EX ||
3086 hw->chip_id == CHIP_ID_YUKON_FE_P)
e3173832
SH		 3087 sky2_write32(hw, B0_CTST, sky2->wol
3088 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3089
9d731d77
RW		 3090 device_set_wakeup_enable(&hw->pdev->dev, sky2->wol);
3091
e3173832
SH		 3092 if (!netif_running(dev))
3093 sky2_wol_init(sky2);
cd28ab6a
SH		 3094 return 0;
3095}
3096
28bd181a 3097static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3098{
b89165f2
SH		 3099 if (sky2_is_copper(hw)) {
3100 u32 modes = SUPPORTED_10baseT_Half
3101 | SUPPORTED_10baseT_Full
3102 | SUPPORTED_100baseT_Half
3103 | SUPPORTED_100baseT_Full
3104 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3105
ea76e635 3106 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3107 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3108 | SUPPORTED_1000baseT_Full;
3109 return modes;
cd28ab6a 3110 } else
b89165f2
SH		 3111 return SUPPORTED_1000baseT_Half
3112 | SUPPORTED_1000baseT_Full
3113 | SUPPORTED_Autoneg
3114 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3115}
3116
793b883e 3117static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3118{
3119 struct sky2_port *sky2 = netdev_priv(dev);
3120 struct sky2_hw *hw = sky2->hw;
3121
3122 ecmd->transceiver = XCVR_INTERNAL;
3123 ecmd->supported = sky2_supported_modes(hw);
3124 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3125 if (sky2_is_copper(hw)) {
cd28ab6a 3126 ecmd->port = PORT_TP;
b89165f2
SH		 3127 ecmd->speed = sky2->speed;
3128 } else {
3129 ecmd->speed = SPEED_1000;
cd28ab6a 3130 ecmd->port = PORT_FIBRE;
b89165f2 3131 }
cd28ab6a
SH		 3132
3133 ecmd->advertising = sky2->advertising;
3134 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 3135 ecmd->duplex = sky2->duplex;
3136 return 0;
3137}
3138
3139static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3140{
3141 struct sky2_port *sky2 = netdev_priv(dev);
3142 const struct sky2_hw *hw = sky2->hw;
3143 u32 supported = sky2_supported_modes(hw);
3144
3145 if (ecmd->autoneg == AUTONEG_ENABLE) {
3146 ecmd->advertising = supported;
3147 sky2->duplex = -1;
3148 sky2->speed = -1;
3149 } else {
3150 u32 setting;
3151
793b883e 3152 switch (ecmd->speed) {
cd28ab6a
SH		 3153 case SPEED_1000:
3154 if (ecmd->duplex == DUPLEX_FULL)
3155 setting = SUPPORTED_1000baseT_Full;
3156 else if (ecmd->duplex == DUPLEX_HALF)
3157 setting = SUPPORTED_1000baseT_Half;
3158 else
3159 return -EINVAL;
3160 break;
3161 case SPEED_100:
3162 if (ecmd->duplex == DUPLEX_FULL)
3163 setting = SUPPORTED_100baseT_Full;
3164 else if (ecmd->duplex == DUPLEX_HALF)
3165 setting = SUPPORTED_100baseT_Half;
3166 else
3167 return -EINVAL;
3168 break;
3169
3170 case SPEED_10:
3171 if (ecmd->duplex == DUPLEX_FULL)
3172 setting = SUPPORTED_10baseT_Full;
3173 else if (ecmd->duplex == DUPLEX_HALF)
3174 setting = SUPPORTED_10baseT_Half;
3175 else
3176 return -EINVAL;
3177 break;
3178 default:
3179 return -EINVAL;
3180 }
3181
3182 if ((setting & supported) == 0)
3183 return -EINVAL;
3184
3185 sky2->speed = ecmd->speed;
3186 sky2->duplex = ecmd->duplex;
3187 }
3188
3189 sky2->autoneg = ecmd->autoneg;
3190 sky2->advertising = ecmd->advertising;
3191
d1b139c0 3192 if (netif_running(dev)) {
1b537565 3193 sky2_phy_reinit(sky2);
d1b139c0
SH		 3194 sky2_set_multicast(dev);
3195 }
cd28ab6a
SH		 3196
3197 return 0;
3198}
3199
3200static void sky2_get_drvinfo(struct net_device *dev,
3201 struct ethtool_drvinfo *info)
3202{
3203 struct sky2_port *sky2 = netdev_priv(dev);
3204
3205 strcpy(info->driver, DRV_NAME);
3206 strcpy(info->version, DRV_VERSION);
3207 strcpy(info->fw_version, "N/A");
3208 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3209}
3210
3211static const struct sky2_stat {
793b883e
SH		 3212 char name[ETH_GSTRING_LEN];
3213 u16 offset;
cd28ab6a
SH		 3214} sky2_stats[] = {
3215 { "tx_bytes", GM_TXO_OK_HI },
3216 { "rx_bytes", GM_RXO_OK_HI },
3217 { "tx_broadcast", GM_TXF_BC_OK },
3218 { "rx_broadcast", GM_RXF_BC_OK },
3219 { "tx_multicast", GM_TXF_MC_OK },
3220 { "rx_multicast", GM_RXF_MC_OK },
3221 { "tx_unicast", GM_TXF_UC_OK },
3222 { "rx_unicast", GM_RXF_UC_OK },
3223 { "tx_mac_pause", GM_TXF_MPAUSE },
3224 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3225 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3226 { "late_collision",GM_TXF_LAT_COL },
3227 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3228 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3229 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3230
d2604540 3231 { "rx_short", GM_RXF_SHT },
cd28ab6a 3232 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3233 { "rx_64_byte_packets", GM_RXF_64B },
3234 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3235 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3236 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3237 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3238 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3239 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3240 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3241 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3242 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3243 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3244
3245 { "tx_64_byte_packets", GM_TXF_64B },
3246 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3247 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3248 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3249 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3250 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3251 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3252 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3253};
3254
cd28ab6a
SH		 3255static u32 sky2_get_rx_csum(struct net_device *dev)
3256{
3257 struct sky2_port *sky2 = netdev_priv(dev);
3258
3259 return sky2->rx_csum;
3260}
3261
3262static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3263{
3264 struct sky2_port *sky2 = netdev_priv(dev);
3265
3266 sky2->rx_csum = data;
793b883e 3267
cd28ab6a
SH		 3268 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3269 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3270
3271 return 0;
3272}
3273
3274static u32 sky2_get_msglevel(struct net_device *netdev)
3275{
3276 struct sky2_port *sky2 = netdev_priv(netdev);
3277 return sky2->msg_enable;
3278}
3279
9a7ae0a9
SH		 3280static int sky2_nway_reset(struct net_device *dev)
3281{
3282 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3283
16ad91e1 3284 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 3285 return -EINVAL;
3286
1b537565 3287 sky2_phy_reinit(sky2);
d1b139c0 3288 sky2_set_multicast(dev);
9a7ae0a9
SH		 3289
3290 return 0;
3291}
3292
793b883e 3293static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3294{
3295 struct sky2_hw *hw = sky2->hw;
3296 unsigned port = sky2->port;
3297 int i;
3298
3299 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3300 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3301 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3302 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3303
793b883e 3304 for (i = 2; i < count; i++)
cd28ab6a
SH		 3305 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3306}
3307
cd28ab6a
SH		 3308static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3309{
3310 struct sky2_port *sky2 = netdev_priv(netdev);
3311 sky2->msg_enable = value;
3312}
3313
b9f2c044 3314static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3315{
b9f2c044
JG		 3316 switch (sset) {
3317 case ETH_SS_STATS:
3318 return ARRAY_SIZE(sky2_stats);
3319 default:
3320 return -EOPNOTSUPP;
3321 }
cd28ab6a
SH		 3322}
3323
3324static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3325 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3326{
3327 struct sky2_port *sky2 = netdev_priv(dev);
3328
793b883e 3329 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3330}
3331
793b883e 3332static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3333{
3334 int i;
3335
3336 switch (stringset) {
3337 case ETH_SS_STATS:
3338 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3339 memcpy(data + i * ETH_GSTRING_LEN,
3340 sky2_stats[i].name, ETH_GSTRING_LEN);
3341 break;
3342 }
3343}
3344
cd28ab6a
SH		 3345static int sky2_set_mac_address(struct net_device *dev, void *p)
3346{
3347 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3348 struct sky2_hw *hw = sky2->hw;
3349 unsigned port = sky2->port;
3350 const struct sockaddr *addr = p;
cd28ab6a
SH		 3351
3352 if (!is_valid_ether_addr(addr->sa_data))
3353 return -EADDRNOTAVAIL;
3354
cd28ab6a 3355 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3356 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3357 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3358 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3359 dev->dev_addr, ETH_ALEN);
1b537565 3360
a8ab1ec0
SH		 3361 /* virtual address for data */
3362 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3363
3364 /* physical address: used for pause frames */
3365 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3366
3367 return 0;
cd28ab6a
SH		 3368}
3369
a052b52f
SH		 3370static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3371{
3372 u32 bit;
3373
3374 bit = ether_crc(ETH_ALEN, addr) & 63;
3375 filter[bit >> 3] |= 1 << (bit & 7);
3376}
3377
cd28ab6a
SH		 3378static void sky2_set_multicast(struct net_device *dev)
3379{
3380 struct sky2_port *sky2 = netdev_priv(dev);
3381 struct sky2_hw *hw = sky2->hw;
3382 unsigned port = sky2->port;
3383 struct dev_mc_list *list = dev->mc_list;
3384 u16 reg;
3385 u8 filter[8];
a052b52f
SH		 3386 int rx_pause;
3387 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3388
a052b52f 3389 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3390 memset(filter, 0, sizeof(filter));
3391
3392 reg = gma_read16(hw, port, GM_RX_CTRL);
3393 reg |= GM_RXCR_UCF_ENA;
3394
d571b694 3395 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3396 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3397 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3398 memset(filter, 0xff, sizeof(filter));
a052b52f 3399 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3400 reg &= ~GM_RXCR_MCF_ENA;
3401 else {
3402 int i;
3403 reg |= GM_RXCR_MCF_ENA;
3404
a052b52f
SH		 3405 if (rx_pause)
3406 sky2_add_filter(filter, pause_mc_addr);
3407
3408 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3409 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3410 }
3411
cd28ab6a 3412 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3413 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3414 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3415 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3416 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3417 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3418 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3419 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3420
3421 gma_write16(hw, port, GM_RX_CTRL, reg);
3422}
3423
3424/* Can have one global because blinking is controlled by
3425 * ethtool and that is always under RTNL mutex
3426 */
a84d0a3d 3427static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3428{
a84d0a3d
SH		 3429 struct sky2_hw *hw = sky2->hw;
3430 unsigned port = sky2->port;
793b883e 3431
a84d0a3d
SH		 3432 spin_lock_bh(&sky2->phy_lock);
3433 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3434 hw->chip_id == CHIP_ID_YUKON_EX ||
3435 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3436 u16 pg;
793b883e
SH		 3437 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3439
a84d0a3d
SH		 3440 switch (mode) {
3441 case MO_LED_OFF:
3442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3443 PHY_M_LEDC_LOS_CTRL(8) |
3444 PHY_M_LEDC_INIT_CTRL(8) |
3445 PHY_M_LEDC_STA1_CTRL(8) |
3446 PHY_M_LEDC_STA0_CTRL(8));
3447 break;
3448 case MO_LED_ON:
3449 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3450 PHY_M_LEDC_LOS_CTRL(9) |
3451 PHY_M_LEDC_INIT_CTRL(9) |
3452 PHY_M_LEDC_STA1_CTRL(9) |
3453 PHY_M_LEDC_STA0_CTRL(9));
3454 break;
3455 case MO_LED_BLINK:
3456 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3457 PHY_M_LEDC_LOS_CTRL(0xa) |
3458 PHY_M_LEDC_INIT_CTRL(0xa) |
3459 PHY_M_LEDC_STA1_CTRL(0xa) |
3460 PHY_M_LEDC_STA0_CTRL(0xa));
3461 break;
3462 case MO_LED_NORM:
3463 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3464 PHY_M_LEDC_LOS_CTRL(1) |
3465 PHY_M_LEDC_INIT_CTRL(8) |
3466 PHY_M_LEDC_STA1_CTRL(7) |
3467 PHY_M_LEDC_STA0_CTRL(7));
3468 }
793b883e 3469
a84d0a3d
SH		 3470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3471 } else
7d2e3cb7 3472 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3473 PHY_M_LED_MO_DUP(mode) |
3474 PHY_M_LED_MO_10(mode) |
3475 PHY_M_LED_MO_100(mode) |
3476 PHY_M_LED_MO_1000(mode) |
3477 PHY_M_LED_MO_RX(mode) |
3478 PHY_M_LED_MO_TX(mode));
3479
3480 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3481}
3482
3483/* blink LED's for finding board */
3484static int sky2_phys_id(struct net_device *dev, u32 data)
3485{
3486 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3487 unsigned int i;
cd28ab6a 3488
a84d0a3d
SH		 3489 if (data == 0)
3490 data = UINT_MAX;
cd28ab6a 3491
a84d0a3d
SH		 3492 for (i = 0; i < data; i++) {
3493 sky2_led(sky2, MO_LED_ON);
3494 if (msleep_interruptible(500))
3495 break;
3496 sky2_led(sky2, MO_LED_OFF);
3497 if (msleep_interruptible(500))
3498 break;
793b883e 3499 }
a84d0a3d 3500 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3501
3502 return 0;
3503}
3504
3505static void sky2_get_pauseparam(struct net_device *dev,
3506 struct ethtool_pauseparam *ecmd)
3507{
3508 struct sky2_port *sky2 = netdev_priv(dev);
3509
16ad91e1
SH		 3510 switch (sky2->flow_mode) {
3511 case FC_NONE:
3512 ecmd->tx_pause = ecmd->rx_pause = 0;
3513 break;
3514 case FC_TX:
3515 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3516 break;
3517 case FC_RX:
3518 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3519 break;
3520 case FC_BOTH:
3521 ecmd->tx_pause = ecmd->rx_pause = 1;
3522 }
3523
cd28ab6a
SH		 3524 ecmd->autoneg = sky2->autoneg;
3525}
3526
3527static int sky2_set_pauseparam(struct net_device *dev,
3528 struct ethtool_pauseparam *ecmd)
3529{
3530 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3531
3532 sky2->autoneg = ecmd->autoneg;
16ad91e1 3533 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3534
16ad91e1
SH		 3535 if (netif_running(dev))
3536 sky2_phy_reinit(sky2);
cd28ab6a 3537
2eaba1a2 3538 return 0;
cd28ab6a
SH		 3539}
3540
fb17358f
SH		 3541static int sky2_get_coalesce(struct net_device *dev,
3542 struct ethtool_coalesce *ecmd)
3543{
3544 struct sky2_port *sky2 = netdev_priv(dev);
3545 struct sky2_hw *hw = sky2->hw;
3546
3547 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3548 ecmd->tx_coalesce_usecs = 0;
3549 else {
3550 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3551 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3552 }
3553 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3554
3555 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3556 ecmd->rx_coalesce_usecs = 0;
3557 else {
3558 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3559 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3560 }
3561 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3562
3563 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3564 ecmd->rx_coalesce_usecs_irq = 0;
3565 else {
3566 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3567 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3568 }
3569
3570 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3571
3572 return 0;
3573}
3574
3575/* Note: this affect both ports */
3576static int sky2_set_coalesce(struct net_device *dev,
3577 struct ethtool_coalesce *ecmd)
3578{
3579 struct sky2_port *sky2 = netdev_priv(dev);
3580 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3581 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3582
77b3d6a2
SH		 3583 if (ecmd->tx_coalesce_usecs > tmax ||
3584 ecmd->rx_coalesce_usecs > tmax ||
3585 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3586 return -EINVAL;
3587
ff81fbbe 3588 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3589 return -EINVAL;
ff81fbbe 3590 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3591 return -EINVAL;
ff81fbbe 3592 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3593 return -EINVAL;
3594
3595 if (ecmd->tx_coalesce_usecs == 0)
3596 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3597 else {
3598 sky2_write32(hw, STAT_TX_TIMER_INI,
3599 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3600 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3601 }
3602 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3603
3604 if (ecmd->rx_coalesce_usecs == 0)
3605 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3606 else {
3607 sky2_write32(hw, STAT_LEV_TIMER_INI,
3608 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3609 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3610 }
3611 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3612
3613 if (ecmd->rx_coalesce_usecs_irq == 0)
3614 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3615 else {
d28d4870 3616 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3617 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3618 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3619 }
3620 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3621 return 0;
3622}
3623
793b883e
SH		 3624static void sky2_get_ringparam(struct net_device *dev,
3625 struct ethtool_ringparam *ering)
3626{
3627 struct sky2_port *sky2 = netdev_priv(dev);
3628
3629 ering->rx_max_pending = RX_MAX_PENDING;
3630 ering->rx_mini_max_pending = 0;
3631 ering->rx_jumbo_max_pending = 0;
3632 ering->tx_max_pending = TX_RING_SIZE - 1;
3633
3634 ering->rx_pending = sky2->rx_pending;
3635 ering->rx_mini_pending = 0;
3636 ering->rx_jumbo_pending = 0;
3637 ering->tx_pending = sky2->tx_pending;
3638}
3639
3640static int sky2_set_ringparam(struct net_device *dev,
3641 struct ethtool_ringparam *ering)
3642{
3643 struct sky2_port *sky2 = netdev_priv(dev);
3644 int err = 0;
3645
3646 if (ering->rx_pending > RX_MAX_PENDING ||
3647 ering->rx_pending < 8 ||
3648 ering->tx_pending < MAX_SKB_TX_LE ||
3649 ering->tx_pending > TX_RING_SIZE - 1)
3650 return -EINVAL;
3651
3652 if (netif_running(dev))
3653 sky2_down(dev);
3654
3655 sky2->rx_pending = ering->rx_pending;
3656 sky2->tx_pending = ering->tx_pending;
3657
1b537565 3658 if (netif_running(dev)) {
793b883e 3659 err = sky2_up(dev);
1b537565
SH		 3660 if (err)
3661 dev_close(dev);
3662 }
793b883e
SH		 3663
3664 return err;
3665}
3666
793b883e
SH		 3667static int sky2_get_regs_len(struct net_device *dev)
3668{
6e4cbb34 3669 return 0x4000;
793b883e
SH		 3670}
3671
3672/*
3673 * Returns copy of control register region
3ead5db7 3674 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 3675 */
3676static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3677 void *p)
3678{
3679 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3680 const void __iomem *io = sky2->hw->regs;
295b54c4 3681 unsigned int b;
793b883e
SH		 3682
3683 regs->version = 1;
793b883e 3684
295b54c4
SH		 3685 for (b = 0; b < 128; b++) {
3686 /* This complicated switch statement is to make sure and
3687 * only access regions that are unreserved.
3688 * Some blocks are only valid on dual port cards.
3689 * and block 3 has some special diagnostic registers that
3690 * are poison.
3691 */
3692 switch (b) {
3693 case 3:
3694 /* skip diagnostic ram region */
3695 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3696 break;
3ead5db7 3697
295b54c4
SH		 3698 /* dual port cards only */
3699 case 5: /* Tx Arbiter 2 */
3700 case 9: /* RX2 */
3701 case 14 ... 15: /* TX2 */
3702 case 17: case 19: /* Ram Buffer 2 */
3703 case 22 ... 23: /* Tx Ram Buffer 2 */
3704 case 25: /* Rx MAC Fifo 1 */
3705 case 27: /* Tx MAC Fifo 2 */
3706 case 31: /* GPHY 2 */
3707 case 40 ... 47: /* Pattern Ram 2 */
3708 case 52: case 54: /* TCP Segmentation 2 */
3709 case 112 ... 116: /* GMAC 2 */
3710 if (sky2->hw->ports == 1)
3711 goto reserved;
3712 /* fall through */
3713 case 0: /* Control */
3714 case 2: /* Mac address */
3715 case 4: /* Tx Arbiter 1 */
3716 case 7: /* PCI express reg */
3717 case 8: /* RX1 */
3718 case 12 ... 13: /* TX1 */
3719 case 16: case 18:/* Rx Ram Buffer 1 */
3720 case 20 ... 21: /* Tx Ram Buffer 1 */
3721 case 24: /* Rx MAC Fifo 1 */
3722 case 26: /* Tx MAC Fifo 1 */
3723 case 28 ... 29: /* Descriptor and status unit */
3724 case 30: /* GPHY 1*/
3725 case 32 ... 39: /* Pattern Ram 1 */
3726 case 48: case 50: /* TCP Segmentation 1 */
3727 case 56 ... 60: /* PCI space */
3728 case 80 ... 84: /* GMAC 1 */
3729 memcpy_fromio(p, io, 128);
3730 break;
3731 default:
3732reserved:
3733 memset(p, 0, 128);
3734 }
3ead5db7 3735
295b54c4
SH		 3736 p += 128;
3737 io += 128;
3738 }
793b883e 3739}
cd28ab6a 3740
b628ed98
SH		 3741/* In order to do Jumbo packets on these chips, need to turn off the
3742 * transmit store/forward. Therefore checksum offload won't work.
3743 */
3744static int no_tx_offload(struct net_device *dev)
3745{
3746 const struct sky2_port *sky2 = netdev_priv(dev);
3747 const struct sky2_hw *hw = sky2->hw;
3748
69161611 3749 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 3750}
3751
3752static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3753{
3754 if (data && no_tx_offload(dev))
3755 return -EINVAL;
3756
3757 return ethtool_op_set_tx_csum(dev, data);
3758}
3759
3760
3761static int sky2_set_tso(struct net_device *dev, u32 data)
3762{
3763 if (data && no_tx_offload(dev))
3764 return -EINVAL;
3765
3766 return ethtool_op_set_tso(dev, data);
3767}
3768
f4331a6d
SH		 3769static int sky2_get_eeprom_len(struct net_device *dev)
3770{
3771 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 3772 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 3773 u16 reg2;
3774
b32f40c4 3775 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 3776 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3777}
3778
1413235c 3779static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 3780{
1413235c 3781 unsigned long start = jiffies;
f4331a6d 3782
1413235c
SH		 3783 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3784 /* Can take up to 10.6 ms for write */
3785 if (time_after(jiffies, start + HZ/4)) {
3786 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3787 return -ETIMEDOUT;
3788 }
3789 mdelay(1);
3790 }
167f53d0 3791
1413235c
SH		 3792 return 0;
3793}
167f53d0 3794
1413235c
SH		 3795static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3796 u16 offset, size_t length)
3797{
3798 int rc = 0;
3799
3800 while (length > 0) {
3801 u32 val;
3802
3803 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3804 rc = sky2_vpd_wait(hw, cap, 0);
3805 if (rc)
3806 break;
3807
3808 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3809
3810 memcpy(data, &val, min(sizeof(val), length));
3811 offset += sizeof(u32);
3812 data += sizeof(u32);
3813 length -= sizeof(u32);
3814 }
3815
3816 return rc;
f4331a6d
SH		 3817}
3818
1413235c
SH		 3819static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
3820 u16 offset, unsigned int length)
f4331a6d 3821{
1413235c
SH		 3822 unsigned int i;
3823 int rc = 0;
3824
3825 for (i = 0; i < length; i += sizeof(u32)) {
3826 u32 val = *(u32 *)(data + i);
3827
3828 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
3829 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3830
3831 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
3832 if (rc)
3833 break;
3834 }
3835 return rc;
f4331a6d
SH		 3836}
3837
3838static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3839 u8 *data)
3840{
3841 struct sky2_port *sky2 = netdev_priv(dev);
3842 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3843
3844 if (!cap)
3845 return -EINVAL;
3846
3847 eeprom->magic = SKY2_EEPROM_MAGIC;
3848
1413235c 3849 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3850}
3851
3852static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3853 u8 *data)
3854{
3855 struct sky2_port *sky2 = netdev_priv(dev);
3856 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 3857
3858 if (!cap)
3859 return -EINVAL;
3860
3861 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3862 return -EINVAL;
3863
1413235c
SH		 3864 /* Partial writes not supported */
3865 if ((eeprom->offset & 3) || (eeprom->len & 3))
3866 return -EINVAL;
f4331a6d 3867
1413235c 3868 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 3869}
3870
3871
7282d491 3872static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 3873 .get_settings = sky2_get_settings,
3874 .set_settings = sky2_set_settings,
3875 .get_drvinfo = sky2_get_drvinfo,
3876 .get_wol = sky2_get_wol,
3877 .set_wol = sky2_set_wol,
3878 .get_msglevel = sky2_get_msglevel,
3879 .set_msglevel = sky2_set_msglevel,
3880 .nway_reset = sky2_nway_reset,
3881 .get_regs_len = sky2_get_regs_len,
3882 .get_regs = sky2_get_regs,
3883 .get_link = ethtool_op_get_link,
3884 .get_eeprom_len = sky2_get_eeprom_len,
3885 .get_eeprom = sky2_get_eeprom,
3886 .set_eeprom = sky2_set_eeprom,
f4331a6d 3887 .set_sg = ethtool_op_set_sg,
f4331a6d 3888 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 3889 .set_tso = sky2_set_tso,
3890 .get_rx_csum = sky2_get_rx_csum,
3891 .set_rx_csum = sky2_set_rx_csum,
3892 .get_strings = sky2_get_strings,
3893 .get_coalesce = sky2_get_coalesce,
3894 .set_coalesce = sky2_set_coalesce,
3895 .get_ringparam = sky2_get_ringparam,
3896 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3897 .get_pauseparam = sky2_get_pauseparam,
3898 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 3899 .phys_id = sky2_phys_id,
b9f2c044 3900 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 3901 .get_ethtool_stats = sky2_get_ethtool_stats,
3902};
3903
3cf26753
SH		 3904#ifdef CONFIG_SKY2_DEBUG
3905
3906static struct dentry *sky2_debug;
3907
e4c2abe2
SH		 3908
3909/*
3910 * Read and parse the first part of Vital Product Data
3911 */
3912#define VPD_SIZE 128
3913#define VPD_MAGIC 0x82
3914
3915static const struct vpd_tag {
3916 char tag[2];
3917 char *label;
3918} vpd_tags[] = {
3919 { "PN", "Part Number" },
3920 { "EC", "Engineering Level" },
3921 { "MN", "Manufacturer" },
3922 { "SN", "Serial Number" },
3923 { "YA", "Asset Tag" },
3924 { "VL", "First Error Log Message" },
3925 { "VF", "Second Error Log Message" },
3926 { "VB", "Boot Agent ROM Configuration" },
3927 { "VE", "EFI UNDI Configuration" },
3928};
3929
3930static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
3931{
3932 size_t vpd_size;
3933 loff_t offs;
3934 u8 len;
3935 unsigned char *buf;
3936 u16 reg2;
3937
3938 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3939 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3940
3941 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
3942 buf = kmalloc(vpd_size, GFP_KERNEL);
3943 if (!buf) {
3944 seq_puts(seq, "no memory!\n");
3945 return;
3946 }
3947
3948 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
3949 seq_puts(seq, "VPD read failed\n");
3950 goto out;
3951 }
3952
3953 if (buf[0] != VPD_MAGIC) {
3954 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
3955 goto out;
3956 }
3957 len = buf[1];
3958 if (len == 0 || len > vpd_size - 4) {
3959 seq_printf(seq, "Invalid id length: %d\n", len);
3960 goto out;
3961 }
3962
3963 seq_printf(seq, "%.*s\n", len, buf + 3);
3964 offs = len + 3;
3965
3966 while (offs < vpd_size - 4) {
3967 int i;
3968
3969 if (!memcmp("RW", buf + offs, 2)) /* end marker */
3970 break;
3971 len = buf[offs + 2];
3972 if (offs + len + 3 >= vpd_size)
3973 break;
3974
3975 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
3976 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
3977 seq_printf(seq, " %s: %.*s\n",
3978 vpd_tags[i].label, len, buf + offs + 3);
3979 break;
3980 }
3981 }
3982 offs += len + 3;
3983 }
3984out:
3985 kfree(buf);
3986}
3987
3cf26753
SH		 3988static int sky2_debug_show(struct seq_file *seq, void *v)
3989{
3990 struct net_device *dev = seq->private;
3991 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 3992 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 3993 unsigned port = sky2->port;
3994 unsigned idx, last;
3995 int sop;
3996
e4c2abe2 3997 sky2_show_vpd(seq, hw);
3cf26753 3998
e4c2abe2 3999 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4000 sky2_read32(hw, B0_ISRC),
4001 sky2_read32(hw, B0_IMSK),
4002 sky2_read32(hw, B0_Y2_SP_ICR));
4003
e4c2abe2
SH		 4004 if (!netif_running(dev)) {
4005 seq_printf(seq, "network not running\n");
4006 return 0;
4007 }
4008
bea3348e 4009 napi_disable(&hw->napi);
3cf26753
SH		 4010 last = sky2_read16(hw, STAT_PUT_IDX);
4011
4012 if (hw->st_idx == last)
4013 seq_puts(seq, "Status ring (empty)\n");
4014 else {
4015 seq_puts(seq, "Status ring\n");
4016 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4017 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4018 const struct sky2_status_le *le = hw->st_le + idx;
4019 seq_printf(seq, "[%d] %#x %d %#x\n",
4020 idx, le->opcode, le->length, le->status);
4021 }
4022 seq_puts(seq, "\n");
4023 }
4024
4025 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4026 sky2->tx_cons, sky2->tx_prod,
4027 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4028 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4029
4030 /* Dump contents of tx ring */
4031 sop = 1;
4032 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
4033 idx = RING_NEXT(idx, TX_RING_SIZE)) {
4034 const struct sky2_tx_le *le = sky2->tx_le + idx;
4035 u32 a = le32_to_cpu(le->addr);
4036
4037 if (sop)
4038 seq_printf(seq, "%u:", idx);
4039 sop = 0;
4040
4041 switch(le->opcode & ~HW_OWNER) {
4042 case OP_ADDR64:
4043 seq_printf(seq, " %#x:", a);
4044 break;
4045 case OP_LRGLEN:
4046 seq_printf(seq, " mtu=%d", a);
4047 break;
4048 case OP_VLAN:
4049 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4050 break;
4051 case OP_TCPLISW:
4052 seq_printf(seq, " csum=%#x", a);
4053 break;
4054 case OP_LARGESEND:
4055 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4056 break;
4057 case OP_PACKET:
4058 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4059 break;
4060 case OP_BUFFER:
4061 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4062 break;
4063 default:
4064 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4065 a, le16_to_cpu(le->length));
4066 }
4067
4068 if (le->ctrl & EOP) {
4069 seq_putc(seq, '\n');
4070 sop = 1;
4071 }
4072 }
4073
4074 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4075 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4076 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4077 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4078
d1d08d12 4079 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4080 napi_enable(&hw->napi);
3cf26753
SH		 4081 return 0;
4082}
4083
4084static int sky2_debug_open(struct inode *inode, struct file *file)
4085{
4086 return single_open(file, sky2_debug_show, inode->i_private);
4087}
4088
4089static const struct file_operations sky2_debug_fops = {
4090 .owner = THIS_MODULE,
4091 .open = sky2_debug_open,
4092 .read = seq_read,
4093 .llseek = seq_lseek,
4094 .release = single_release,
4095};
4096
4097/*
4098 * Use network device events to create/remove/rename
4099 * debugfs file entries
4100 */
4101static int sky2_device_event(struct notifier_block *unused,
4102 unsigned long event, void *ptr)
4103{
4104 struct net_device *dev = ptr;
5b296bc9 4105 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4106
1436b301 4107 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4108 return NOTIFY_DONE;
3cf26753 4109
5b296bc9
SH		 4110 switch(event) {
4111 case NETDEV_CHANGENAME:
4112 if (sky2->debugfs) {
4113 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4114 sky2_debug, dev->name);
4115 }
4116 break;
3cf26753 4117
5b296bc9
SH		 4118 case NETDEV_GOING_DOWN:
4119 if (sky2->debugfs) {
4120 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4121 dev->name);
4122 debugfs_remove(sky2->debugfs);
4123 sky2->debugfs = NULL;
3cf26753 4124 }
5b296bc9
SH		 4125 break;
4126
4127 case NETDEV_UP:
4128 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4129 sky2_debug, dev,
4130 &sky2_debug_fops);
4131 if (IS_ERR(sky2->debugfs))
4132 sky2->debugfs = NULL;
3cf26753
SH		 4133 }
4134
4135 return NOTIFY_DONE;
4136}
4137
4138static struct notifier_block sky2_notifier = {
4139 .notifier_call = sky2_device_event,
4140};
4141
4142
4143static __init void sky2_debug_init(void)
4144{
4145 struct dentry *ent;
4146
4147 ent = debugfs_create_dir("sky2", NULL);
4148 if (!ent || IS_ERR(ent))
4149 return;
4150
4151 sky2_debug = ent;
4152 register_netdevice_notifier(&sky2_notifier);
4153}
4154
4155static __exit void sky2_debug_cleanup(void)
4156{
4157 if (sky2_debug) {
4158 unregister_netdevice_notifier(&sky2_notifier);
4159 debugfs_remove(sky2_debug);
4160 sky2_debug = NULL;
4161 }
4162}
4163
4164#else
4165#define sky2_debug_init()
4166#define sky2_debug_cleanup()
4167#endif
4168
1436b301
SH		 4169/* Two copies of network device operations to handle special case of
4170 not allowing netpoll on second port */
4171static const struct net_device_ops sky2_netdev_ops[2] = {
4172 {
4173 .ndo_open = sky2_up,
4174 .ndo_stop = sky2_down,
00829823 4175 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4176 .ndo_do_ioctl = sky2_ioctl,
4177 .ndo_validate_addr = eth_validate_addr,
4178 .ndo_set_mac_address = sky2_set_mac_address,
4179 .ndo_set_multicast_list = sky2_set_multicast,
4180 .ndo_change_mtu = sky2_change_mtu,
4181 .ndo_tx_timeout = sky2_tx_timeout,
4182#ifdef SKY2_VLAN_TAG_USED
4183 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4184#endif
4185#ifdef CONFIG_NET_POLL_CONTROLLER
4186 .ndo_poll_controller = sky2_netpoll,
4187#endif
4188 },
4189 {
4190 .ndo_open = sky2_up,
4191 .ndo_stop = sky2_down,
00829823 4192 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4193 .ndo_do_ioctl = sky2_ioctl,
4194 .ndo_validate_addr = eth_validate_addr,
4195 .ndo_set_mac_address = sky2_set_mac_address,
4196 .ndo_set_multicast_list = sky2_set_multicast,
4197 .ndo_change_mtu = sky2_change_mtu,
4198 .ndo_tx_timeout = sky2_tx_timeout,
4199#ifdef SKY2_VLAN_TAG_USED
4200 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4201#endif
4202 },
4203};
3cf26753 4204
cd28ab6a
SH		 4205/* Initialize network device */
4206static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4207 unsigned port,
be63a21c 4208 int highmem, int wol)
cd28ab6a
SH		 4209{
4210 struct sky2_port *sky2;
4211 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4212
4213 if (!dev) {
898eb71c 4214 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4215 return NULL;
4216 }
4217
cd28ab6a 4218 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4219 dev->irq = hw->pdev->irq;
cd28ab6a 4220 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4221 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4222 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4223
4224 sky2 = netdev_priv(dev);
4225 sky2->netdev = dev;
4226 sky2->hw = hw;
4227 sky2->msg_enable = netif_msg_init(debug, default_msg);
4228
cd28ab6a
SH		 4229 /* Auto speed and flow control */
4230 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 4231 sky2->flow_mode = FC_BOTH;
4232
cd28ab6a
SH		 4233 sky2->duplex = -1;
4234 sky2->speed = -1;
4235 sky2->advertising = sky2_supported_modes(hw);
8b31cfbc 4236 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
be63a21c 4237 sky2->wol = wol;
75d070c5 4238
e07b1aa8 4239 spin_lock_init(&sky2->phy_lock);
793b883e 4240 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 4241 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4242
4243 hw->dev[port] = dev;
4244
4245 sky2->port = port;
4246
4a50a876 4247 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4248 if (highmem)
4249 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4250
d1f13708 4251#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4252 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4253 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4254 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4255 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4256 }
d1f13708
SH		 4257#endif
4258
cd28ab6a 4259 /* read the mac address */
793b883e 4260 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4261 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4262
cd28ab6a
SH		 4263 return dev;
4264}
4265
28bd181a 4266static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4267{
4268 const struct sky2_port *sky2 = netdev_priv(dev);
4269
4270 if (netif_msg_probe(sky2))
e174961c
JB		 4271 printk(KERN_INFO PFX "%s: addr %pM\n",
4272 dev->name, dev->dev_addr);
cd28ab6a
SH		 4273}
4274
fb2690a9 4275/* Handle software interrupt used during MSI test */
7d12e780 4276static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4277{
4278 struct sky2_hw *hw = dev_id;
4279 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4280
4281 if (status == 0)
4282 return IRQ_NONE;
4283
4284 if (status & Y2_IS_IRQ_SW) {
ea76e635 4285 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4286 wake_up(&hw->msi_wait);
4287 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4288 }
4289 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4290
4291 return IRQ_HANDLED;
4292}
4293
4294/* Test interrupt path by forcing a a software IRQ */
4295static int __devinit sky2_test_msi(struct sky2_hw *hw)
4296{
4297 struct pci_dev *pdev = hw->pdev;
4298 int err;
4299
bb507fe1
SH		 4300 init_waitqueue_head (&hw->msi_wait);
4301
fb2690a9
SH		 4302 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4303
b0a20ded 4304 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4305 if (err) {
b02a9258 4306 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4307 return err;
4308 }
4309
fb2690a9 4310 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4311 sky2_read8(hw, B0_CTST);
fb2690a9 4312
ea76e635 4313 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4314
ea76e635 4315 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4316 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4317 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4318 "switching to INTx mode.\n");
fb2690a9
SH		 4319
4320 err = -EOPNOTSUPP;
4321 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4322 }
4323
4324 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4325 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4326
4327 free_irq(pdev->irq, hw);
4328
4329 return err;
4330}
4331
c7127a34
SH		 4332/* This driver supports yukon2 chipset only */
4333static const char *sky2_name(u8 chipid, char *buf, int sz)
4334{
4335 const char *name[] = {
4336 "XL", /* 0xb3 */
4337 "EC Ultra", /* 0xb4 */
4338 "Extreme", /* 0xb5 */
4339 "EC", /* 0xb6 */
4340 "FE", /* 0xb7 */
4341 "FE+", /* 0xb8 */
4342 "Supreme", /* 0xb9 */
0ce8b98d 4343 "UL 2", /* 0xba */
c7127a34
SH		 4344 };
4345
0ce8b98d 4346 if (chipid >= CHIP_ID_YUKON_XL && chipid < CHIP_ID_YUKON_UL_2)
c7127a34
SH		 4347 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4348 else
4349 snprintf(buf, sz, "(chip %#x)", chipid);
4350 return buf;
4351}
4352
cd28ab6a
SH		 4353static int __devinit sky2_probe(struct pci_dev *pdev,
4354 const struct pci_device_id *ent)
4355{
7f60c64b 4356 struct net_device *dev;
cd28ab6a 4357 struct sky2_hw *hw;
be63a21c 4358 int err, using_dac = 0, wol_default;
3834507d 4359 u32 reg;
c7127a34 4360 char buf1[16];
cd28ab6a 4361
793b883e
SH		 4362 err = pci_enable_device(pdev);
4363 if (err) {
b02a9258 4364 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4365 goto err_out;
4366 }
4367
793b883e
SH		 4368 err = pci_request_regions(pdev, DRV_NAME);
4369 if (err) {
b02a9258 4370 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4371 goto err_out_disable;
cd28ab6a
SH		 4372 }
4373
4374 pci_set_master(pdev);
4375
d1f3d4dd 4376 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4377 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4378 using_dac = 1;
6a35528a 4379 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4380 if (err < 0) {
b02a9258
SH		 4381 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4382 "for consistent allocations\n");
d1f3d4dd
SH		 4383 goto err_out_free_regions;
4384 }
d1f3d4dd 4385 } else {
284901a9 4386 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4387 if (err) {
b02a9258 4388 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4389 goto err_out_free_regions;
4390 }
4391 }
d1f3d4dd 4392
3834507d
SH		 4393 /* Get configuration information
4394 * Note: only regular PCI config access once to test for HW issues
4395 * other PCI access through shared memory for speed and to
4396 * avoid MMCONFIG problems.
4397 */
4398 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4399 if (err) {
4400 dev_err(&pdev->dev, "PCI read config failed\n");
4401 goto err_out_free_regions;
4402 }
4403
4404 /* size of available VPD, only impact sysfs */
4405 err = pci_vpd_truncate(pdev, 1ul << (((reg & PCI_VPD_ROM_SZ) >> 14) + 8));
4406 if (err)
4407 dev_warn(&pdev->dev, "Can't set VPD size\n");
4408
4409#ifdef __BIG_ENDIAN
4410 /* The sk98lin vendor driver uses hardware byte swapping but
4411 * this driver uses software swapping.
4412 */
4413 reg &= ~PCI_REV_DESC;
4414 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4415 if (err) {
4416 dev_err(&pdev->dev, "PCI write config failed\n");
4417 goto err_out_free_regions;
4418 }
4419#endif
4420
9d731d77 4421 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4422
cd28ab6a 4423 err = -ENOMEM;
6aad85d6 4424 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 4425 if (!hw) {
b02a9258 4426 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4427 goto err_out_free_regions;
4428 }
4429
cd28ab6a 4430 hw->pdev = pdev;
cd28ab6a
SH		 4431
4432 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4433 if (!hw->regs) {
b02a9258 4434 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4435 goto err_out_free_hw;
4436 }
4437
08c06d8a 4438 /* ring for status responses */
167f53d0 4439 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
08c06d8a
SH		 4440 if (!hw->st_le)
4441 goto err_out_iounmap;
4442
e3173832 4443 err = sky2_init(hw);
cd28ab6a 4444 if (err)
793b883e 4445 goto err_out_iounmap;
cd28ab6a 4446
c844d483
SH		 4447 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4448 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4449
e3173832
SH		 4450 sky2_reset(hw);
4451
be63a21c 4452 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4453 if (!dev) {
4454 err = -ENOMEM;
cd28ab6a 4455 goto err_out_free_pci;
7f60c64b 4456 }
cd28ab6a 4457
9fa1b1f3
SH		 4458 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4459 err = sky2_test_msi(hw);
4460 if (err == -EOPNOTSUPP)
4461 pci_disable_msi(pdev);
4462 else if (err)
4463 goto err_out_free_netdev;
4464 }
4465
793b883e
SH		 4466 err = register_netdev(dev);
4467 if (err) {
b02a9258 4468 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4469 goto err_out_free_netdev;
4470 }
4471
6de16237
SH		 4472 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4473
ea76e635
SH		 4474 err = request_irq(pdev->irq, sky2_intr,
4475 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
b0a20ded 4476 dev->name, hw);
9fa1b1f3 4477 if (err) {
b02a9258 4478 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4479 goto err_out_unregister;
4480 }
4481 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4482 napi_enable(&hw->napi);
9fa1b1f3 4483
cd28ab6a
SH		 4484 sky2_show_addr(dev);
4485
7f60c64b 4486 if (hw->ports > 1) {
4487 struct net_device *dev1;
4488
be63a21c 4489 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 4490 if (!dev1)
4491 dev_warn(&pdev->dev, "allocation for second device failed\n");
4492 else if ((err = register_netdev(dev1))) {
4493 dev_warn(&pdev->dev,
4494 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 4495 hw->dev[1] = NULL;
4496 free_netdev(dev1);
b02a9258
SH		 4497 } else
4498 sky2_show_addr(dev1);
cd28ab6a
SH		 4499 }
4500
32c2c300 4501 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4502 INIT_WORK(&hw->restart_work, sky2_restart);
4503
793b883e
SH		 4504 pci_set_drvdata(pdev, hw);
4505
cd28ab6a
SH		 4506 return 0;
4507
793b883e 4508err_out_unregister:
ea76e635 4509 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4510 pci_disable_msi(pdev);
793b883e 4511 unregister_netdev(dev);
cd28ab6a
SH		 4512err_out_free_netdev:
4513 free_netdev(dev);
cd28ab6a 4514err_out_free_pci:
793b883e 4515 sky2_write8(hw, B0_CTST, CS_RST_SET);
167f53d0 4516 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4517err_out_iounmap:
4518 iounmap(hw->regs);
4519err_out_free_hw:
4520 kfree(hw);
4521err_out_free_regions:
4522 pci_release_regions(pdev);
44a1d2e5 4523err_out_disable:
cd28ab6a 4524 pci_disable_device(pdev);
cd28ab6a 4525err_out:
549a68c3 4526 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4527 return err;
4528}
4529
4530static void __devexit sky2_remove(struct pci_dev *pdev)
4531{
793b883e 4532 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4533 int i;
cd28ab6a 4534
793b883e 4535 if (!hw)
cd28ab6a
SH		 4536 return;
4537
32c2c300 4538 del_timer_sync(&hw->watchdog_timer);
6de16237 4539 cancel_work_sync(&hw->restart_work);
d27ed387 4540
b877fe28 4541 for (i = hw->ports-1; i >= 0; --i)
6de16237 4542 unregister_netdev(hw->dev[i]);
81906791 4543
d27ed387 4544 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4545
ae306cca
SH		 4546 sky2_power_aux(hw);
4547
cd28ab6a 4548 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 4549 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4550 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4551
4552 free_irq(pdev->irq, hw);
ea76e635 4553 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4554 pci_disable_msi(pdev);
793b883e 4555 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 4556 pci_release_regions(pdev);
4557 pci_disable_device(pdev);
793b883e 4558
b877fe28 4559 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4560 free_netdev(hw->dev[i]);
4561
cd28ab6a
SH		 4562 iounmap(hw->regs);
4563 kfree(hw);
5afa0a9c 4564
cd28ab6a
SH		 4565 pci_set_drvdata(pdev, NULL);
4566}
4567
4568#ifdef CONFIG_PM
4569static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4570{
793b883e 4571 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4572 int i, wol = 0;
cd28ab6a 4573
549a68c3
SH		 4574 if (!hw)
4575 return 0;
4576
063a0b38
SH		 4577 del_timer_sync(&hw->watchdog_timer);
4578 cancel_work_sync(&hw->restart_work);
4579
f05267e7 4580 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4581 struct net_device *dev = hw->dev[i];
e3173832 4582 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4583
063a0b38 4584 netif_device_detach(dev);
e3173832 4585 if (netif_running(dev))
5afa0a9c 4586 sky2_down(dev);
e3173832
SH		 4587
4588 if (sky2->wol)
4589 sky2_wol_init(sky2);
4590
4591 wol |= sky2->wol;
cd28ab6a
SH		 4592 }
4593
8ab8fca2 4594 sky2_write32(hw, B0_IMSK, 0);
6de16237 4595 napi_disable(&hw->napi);
ae306cca 4596 sky2_power_aux(hw);
e3173832 4597
d374c1c1 4598 pci_save_state(pdev);
e3173832 4599 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4600 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4601
2ccc99b7 4602 return 0;
cd28ab6a
SH		 4603}
4604
4605static int sky2_resume(struct pci_dev *pdev)
4606{
793b883e 4607 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4608 int i, err;
cd28ab6a 4609
549a68c3
SH		 4610 if (!hw)
4611 return 0;
4612
f71eb1a2
SH		 4613 err = pci_set_power_state(pdev, PCI_D0);
4614 if (err)
4615 goto out;
ae306cca
SH		 4616
4617 err = pci_restore_state(pdev);
4618 if (err)
4619 goto out;
4620
cd28ab6a 4621 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4622
4623 /* Re-enable all clocks */
05745c4a
SH		 4624 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4625 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4626 hw->chip_id == CHIP_ID_YUKON_FE_P)
b32f40c4 4627 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
1ad5b4a5 4628
e3173832 4629 sky2_reset(hw);
8ab8fca2 4630 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4631 napi_enable(&hw->napi);
8ab8fca2 4632
f05267e7 4633 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4634 struct net_device *dev = hw->dev[i];
063a0b38
SH		 4635
4636 netif_device_attach(dev);
6a5706b9 4637 if (netif_running(dev)) {
08c06d8a
SH		 4638 err = sky2_up(dev);
4639 if (err) {
4640 printk(KERN_ERR PFX "%s: could not up: %d\n",
4641 dev->name, err);
68c28898 4642 rtnl_lock();
08c06d8a 4643 dev_close(dev);
68c28898 4644 rtnl_unlock();
eb35cf60 4645 goto out;
5afa0a9c 4646 }
cd28ab6a
SH		 4647 }
4648 }
eb35cf60 4649
ae306cca 4650 return 0;
08c06d8a 4651out:
b02a9258 4652 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4653 pci_disable_device(pdev);
08c06d8a 4654 return err;
cd28ab6a
SH		 4655}
4656#endif
4657
e3173832
SH		 4658static void sky2_shutdown(struct pci_dev *pdev)
4659{
4660 struct sky2_hw *hw = pci_get_drvdata(pdev);
4661 int i, wol = 0;
4662
549a68c3
SH		 4663 if (!hw)
4664 return;
4665
5c0d6b34 4666 del_timer_sync(&hw->watchdog_timer);
e3173832
SH		 4667
4668 for (i = 0; i < hw->ports; i++) {
4669 struct net_device *dev = hw->dev[i];
4670 struct sky2_port *sky2 = netdev_priv(dev);
4671
4672 if (sky2->wol) {
4673 wol = 1;
4674 sky2_wol_init(sky2);
4675 }
4676 }
4677
4678 if (wol)
4679 sky2_power_aux(hw);
4680
4681 pci_enable_wake(pdev, PCI_D3hot, wol);
4682 pci_enable_wake(pdev, PCI_D3cold, wol);
4683
4684 pci_disable_device(pdev);
f71eb1a2 4685 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 4686}
4687
cd28ab6a 4688static struct pci_driver sky2_driver = {
793b883e
SH		 4689 .name = DRV_NAME,
4690 .id_table = sky2_id_table,
4691 .probe = sky2_probe,
4692 .remove = __devexit_p(sky2_remove),
cd28ab6a 4693#ifdef CONFIG_PM
793b883e
SH		 4694 .suspend = sky2_suspend,
4695 .resume = sky2_resume,
cd28ab6a 4696#endif
e3173832 4697 .shutdown = sky2_shutdown,
cd28ab6a
SH		 4698};
4699
4700static int __init sky2_init_module(void)
4701{
c844d483
SH		 4702 pr_info(PFX "driver version " DRV_VERSION "\n");
4703
3cf26753 4704 sky2_debug_init();
50241c4c 4705 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 4706}
4707
4708static void __exit sky2_cleanup_module(void)
4709{
4710 pci_unregister_driver(&sky2_driver);
3cf26753 4711 sky2_debug_cleanup();
cd28ab6a
SH		 4712}
4713
4714module_init(sky2_init_module);
4715module_exit(sky2_cleanup_module);
4716
4717MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 4718MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 4719MODULE_LICENSE("GPL");
5f4f9dc1 4720MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree