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bnx2x: Remove two prefetch()
[net-next-2.6.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
5a0e3ad6 36#include <linux/slab.h>
c9bdd4b5 37#include <net/ip.h>
cd28ab6a
SH		 38#include <linux/tcp.h>
39#include <linux/in.h>
40#include <linux/delay.h>
91c86df5 41#include <linux/workqueue.h>
d1f13708 42#include <linux/if_vlan.h>
d70cd51a 43#include <linux/prefetch.h>
3cf26753 44#include <linux/debugfs.h>
ef743d33 45#include <linux/mii.h>
cd28ab6a
SH		 46
47#include <asm/irq.h>
48
d1f13708
SH		 49#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50#define SKY2_VLAN_TAG_USED 1
51#endif
52
cd28ab6a
SH		 53#include "sky2.h"
54
55#define DRV_NAME "sky2"
cfc0861b 56#define DRV_VERSION "1.27"
cd28ab6a
SH		 57
58/*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
14d0263f 61 * similar to Tigon3.
cd28ab6a
SH		 62 */
63
14d0263f 64#define RX_LE_SIZE 1024
cd28ab6a 65#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 66#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 67#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 68
ee5f68fe 69/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 72#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 73#define TX_MAX_PENDING 1024
ee5f68fe 74#define TX_DEF_PENDING 127
cd28ab6a 75
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
f4331a6d
SH		 80#define SKY2_EEPROM_MAGIC 0x9955aabb
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
14d0263f 93static int copybreak __read_mostly = 128;
bdb5c58e
SH		 94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
e6cac9ba 101static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 143 { 0 }
144};
793b883e 145
cd28ab6a
SH		 146MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148/* Avoid conditionals by using array */
149static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 151static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 152
d1b139c0
SH		 153static void sky2_set_multicast(struct net_device *dev);
154
af043aa5 155/* Access to PHY via serial interconnect */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 170 return 0;
af043aa5
SH		 171
172 udelay(10);
cd28ab6a 173 }
ef743d33 174
af043aa5 175 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 176 return -ETIMEDOUT;
af043aa5
SH		 177
178io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
cd28ab6a
SH		 181}
182
ef743d33 183static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 184{
185 int i;
186
793b883e 187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33
SH		 196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
af043aa5 200 udelay(10);
cd28ab6a
SH		 201 }
202
af043aa5 203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 204 return -ETIMEDOUT;
af043aa5
SH		 205io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
ef743d33
SH		 208}
209
af043aa5 210static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33
SH		 211{
212 u16 v;
af043aa5 213 __gm_phy_read(hw, port, reg, &v);
ef743d33 214 return v;
cd28ab6a
SH		 215}
216
5afa0a9c 217
ae306cca
SH		 218static void sky2_power_on(struct sky2_hw *hw)
219{
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 223
ae306cca
SH		 224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 226
4b7c47aa 227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 235
ea76e635 236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 237 u32 reg;
5afa0a9c 238
b32f40c4 239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 240
b32f40c4 241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 245
b32f40c4 246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 250
b32f40c4 251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 252
5f8ae5c5 253 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
254
8f70920f
SH		 255 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
256 reg = sky2_read32(hw, B2_GP_IO);
257 reg |= GLB_GPIO_STAT_RACE_DIS;
258 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 259
260 sky2_read32(hw, B2_GP_IO);
5afa0a9c 261 }
10547ae2
SH		 262
263 /* Turn on "driver loaded" LED */
264 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 265}
5afa0a9c 266
ae306cca
SH		 267static void sky2_power_aux(struct sky2_hw *hw)
268{
4b7c47aa 269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
c23ddf8f
SH		 278 /* switch power to VAUX if supported and PME from D3cold */
279 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
280 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 284
285 /* turn off "driver loaded LED" */
286 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c
SH		 287}
288
d3bcfbeb 289static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 290{
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 295
cd28ab6a
SH		 296 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
297 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300
301 reg = gma_read16(hw, port, GM_RX_CTRL);
302 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
303 gma_write16(hw, port, GM_RX_CTRL, reg);
304}
305
16ad91e1
SH		 306/* flow control to advertise bits */
307static const u16 copper_fc_adv[] = {
308 [FC_NONE] = 0,
309 [FC_TX] = PHY_M_AN_ASP,
310 [FC_RX] = PHY_M_AN_PC,
311 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312};
313
314/* flow control to advertise bits when using 1000BaseX */
315static const u16 fiber_fc_adv[] = {
df3fe1f3 316 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 317 [FC_TX] = PHY_M_P_ASYM_MD_X,
318 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 319 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 320};
321
322/* flow control to GMA disable bits */
323static const u16 gm_fc_disable[] = {
324 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
325 [FC_TX] = GM_GPCR_FC_RX_DIS,
326 [FC_RX] = GM_GPCR_FC_TX_DIS,
327 [FC_BOTH] = 0,
328};
329
330
cd28ab6a
SH		 331static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332{
333 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 334 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 335
0ea065e5 336 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 337 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 338 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339
340 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 341 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 342 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343
53419c68 344 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 345 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 346 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 347 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 else
53419c68
SH		 349 /* set master & slave downshift counter to 1x */
350 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 351
352 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 356 if (sky2_is_copper(hw)) {
05745c4a 357 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 358 /* enable automatic crossover */
359 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 360
361 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
362 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 u16 spec;
364
365 /* Enable Class A driver for FE+ A0 */
366 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
367 spec |= PHY_M_FESC_SEL_CL_A;
368 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 }
cd28ab6a
SH		 370 } else {
371 /* disable energy detect */
372 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373
374 /* enable automatic crossover */
375 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376
53419c68 377 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 378 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
379 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 380 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 381 ctrl &= ~PHY_M_PC_DSC_MSK;
382 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 }
384 }
cd28ab6a
SH		 385 } else {
386 /* workaround for deviation #4.88 (CRC errors) */
387 /* disable Automatic Crossover */
388
389 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 390 }
cd28ab6a 391
b89165f2
SH		 392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393
394 /* special setup for PHY 88E1112 Fiber */
ea76e635 395 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 397
b89165f2
SH		 398 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
399 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl &= ~PHY_M_MAC_MD_MSK;
402 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404
405 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 406 /* select page 1 to access Fiber registers */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 408
409 /* for SFP-module set SIGDET polarity to low */
410 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
411 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 413 }
b89165f2
SH		 414
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 416 }
417
7800fddc 418 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 419 ct1000 = 0;
420 adv = PHY_AN_CSMA;
2eaba1a2 421 reg = 0;
cd28ab6a 422
0ea065e5 423 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 424 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 425 if (sky2->advertising & ADVERTISED_1000baseT_Full)
426 ct1000 |= PHY_M_1000C_AFD;
427 if (sky2->advertising & ADVERTISED_1000baseT_Half)
428 ct1000 |= PHY_M_1000C_AHD;
429 if (sky2->advertising & ADVERTISED_100baseT_Full)
430 adv |= PHY_M_AN_100_FD;
431 if (sky2->advertising & ADVERTISED_100baseT_Half)
432 adv |= PHY_M_AN_100_HD;
433 if (sky2->advertising & ADVERTISED_10baseT_Full)
434 adv |= PHY_M_AN_10_FD;
435 if (sky2->advertising & ADVERTISED_10baseT_Half)
436 adv |= PHY_M_AN_10_HD;
709c6e7b 437
b89165f2
SH		 438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 443 }
cd28ab6a
SH		 444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
0ea065e5
SH		 451 /* Disable auto update for duplex flow control and duplex */
452 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
2eaba1a2 457 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
2eaba1a2 461 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 462 break;
463 }
464
2eaba1a2
SH		 465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
0ea065e5 470 }
2eaba1a2 471
0ea065e5
SH		 472 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
473 if (sky2_is_copper(hw))
474 adv |= copper_fc_adv[sky2->flow_mode];
475 else
476 adv |= fiber_fc_adv[sky2->flow_mode];
477 } else {
478 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 479 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 480
481 /* Forward pause packets to GMAC? */
16ad91e1 482 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 else
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 486 }
487
2eaba1a2
SH		 488 gma_write16(hw, port, GM_GP_CTRL, reg);
489
05745c4a 490 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 491 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492
493 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
494 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495
496 /* Setup Phy LED's */
497 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
498 ledover = 0;
499
500 switch (hw->chip_id) {
501 case CHIP_ID_YUKON_FE:
502 /* on 88E3082 these bits are at 11..9 (shifted left) */
503 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504
505 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506
507 /* delete ACT LED control bits */
508 ctrl &= ~PHY_M_FELP_LED1_MSK;
509 /* change ACT LED control to blink mode */
510 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
511 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
512 break;
513
05745c4a
SH		 514 case CHIP_ID_YUKON_FE_P:
515 /* Enable Link Partner Next Page */
516 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
517 ctrl |= PHY_M_PC_ENA_LIP_NP;
518
519 /* disable Energy Detect and enable scrambler */
520 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522
523 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
524 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
525 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
526 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527
528 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
529 break;
530
cd28ab6a 531 case CHIP_ID_YUKON_XL:
793b883e 532 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 533
534 /* select page 3 to access LED control register */
535 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536
537 /* set LED Function Control register */
ed6d32c7
SH		 538 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
539 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
540 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
541 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
542 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 543
544 /* set Polarity Control register */
545 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 546 (PHY_M_POLC_LS1_P_MIX(4) |
547 PHY_M_POLC_IS0_P_MIX(4) |
548 PHY_M_POLC_LOS_CTRL(2) |
549 PHY_M_POLC_INIT_CTRL(2) |
550 PHY_M_POLC_STA1_CTRL(2) |
551 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 552
553 /* restore page register */
793b883e 554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 555 break;
93745494 556
ed6d32c7 557 case CHIP_ID_YUKON_EC_U:
93745494 558 case CHIP_ID_YUKON_EX:
ed4d4161 559 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 560 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561
562 /* select page 3 to access LED control register */
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564
565 /* set LED Function Control register */
566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
567 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
568 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
569 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
570 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571
572 /* set Blink Rate in LED Timer Control Register */
573 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
574 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
575 /* restore page register */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 break;
cd28ab6a
SH		 578
579 default:
580 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
581 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 582
cd28ab6a 583 /* turn off the Rx LED (LED_RX) */
a84d0a3d 584 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 585 }
586
0ce8b98d 587 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 588 /* apply fixes in PHY AFE */
ed6d32c7
SH		 589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590
977bdf06 591 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 592 gm_phy_write(hw, port, 0x18, 0xaa99);
593 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 594
0ce8b98d
SH		 595 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
596 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xa204);
598 gm_phy_write(hw, port, 0x17, 0x2002);
599 }
977bdf06
SH		 600
601 /* set page register to 0 */
9467a8fc 602 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 603 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
604 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
605 /* apply workaround for integrated resistors calibration */
606 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
607 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 608 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
609 /* apply fixes in PHY AFE */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611
612 /* apply RDAC termination workaround */
613 gm_phy_write(hw, port, 24, 0x2800);
614 gm_phy_write(hw, port, 23, 0x2001);
615
616 /* set page register back to 0 */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 618 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
619 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 620 /* no effect on Yukon-XL */
977bdf06 621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 622
8e95a202
JP		 623 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
624 sky2->speed == SPEED_100) {
977bdf06 625 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 627 }
cd28ab6a 628
977bdf06
SH		 629 if (ledover)
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
631
632 }
2eaba1a2 633
d571b694 634 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 635 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 else
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
639}
640
b96936da
SH		 641static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
642static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643
644static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb
SH		 645{
646 u32 reg1;
d3bcfbeb 647
a40ccc68 648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 650 reg1 &= ~phy_power[port];
d3bcfbeb 651
4b7c47aa 652 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 653 reg1 |= coma_mode[port];
654
b32f40c4 655 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 657 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 658
659 if (hw->chip_id == CHIP_ID_YUKON_FE)
660 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
661 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 663}
167f53d0 664
b96936da
SH		 665static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
666{
667 u32 reg1;
db99b988
SH		 668 u16 ctrl;
669
670 /* release GPHY Control reset */
671 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
672
673 /* release GMAC reset */
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675
676 if (hw->flags & SKY2_HW_NEWER_PHY) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
679
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* allow GMII Power Down */
682 ctrl &= ~PHY_M_MAC_GMIF_PUP;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
684
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
687 }
688
689 /* setup General Purpose Control Register */
690 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 691 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
692 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
693 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 694
695 if (hw->chip_id != CHIP_ID_YUKON_EC) {
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 697 /* select page 2 to access MAC control register */
698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 699
e484d5f5 700 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 701 /* enable Power Down */
702 ctrl |= PHY_M_PC_POW_D_ENA;
703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 704
705 /* set page register back to 0 */
706 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 707 }
708
709 /* set IEEE compatible Power Down Mode (dev. #4.99) */
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
711 }
b96936da 712
a40ccc68 713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 715 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 718}
719
1b537565
SH		 720/* Force a renegotiation */
721static void sky2_phy_reinit(struct sky2_port *sky2)
722{
e07b1aa8 723 spin_lock_bh(&sky2->phy_lock);
1b537565 724 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 725 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 726}
727
e3173832
SH		 728/* Put device in state to listen for Wake On Lan */
729static void sky2_wol_init(struct sky2_port *sky2)
730{
731 struct sky2_hw *hw = sky2->hw;
732 unsigned port = sky2->port;
733 enum flow_control save_mode;
734 u16 ctrl;
e3173832
SH		 735
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
739
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
742
743 /* Force to 10/100
744 * sky2_reset will re-enable on resume
745 */
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
748
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
b96936da
SH		 751
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 756
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
759
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
764
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
768
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
771 ctrl = 0;
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
774 else
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
776
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
779 else
a419aef8 780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 781
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
784
5f8ae5c5 785 /* Disable PiG firmware */
786 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
787
e3173832
SH		 788 /* block receiver */
789 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
e3173832
SH		 790}
791
69161611
SH		 792static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
793{
05745c4a
SH		 794 struct net_device *dev = hw->dev[port];
795
ed4d4161
SH		 796 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
797 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 798 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 799 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
801 } else if (dev->mtu > ETH_DATA_LEN) {
802 /* set Tx GMAC FIFO Almost Empty Threshold */
803 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
804 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 805
44dde56d 806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
807 } else
808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 809}
810
cd28ab6a
SH		 811static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
812{
813 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
814 u16 reg;
25cccecc 815 u32 rx_reg;
cd28ab6a
SH		 816 int i;
817 const u8 *addr = hw->dev[port]->dev_addr;
818
f350339c
SH		 819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 821
822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
823
4b7c47aa 824 if (hw->chip_id == CHIP_ID_YUKON_XL &&
825 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
826 port == 1) {
cd28ab6a
SH		 827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
830 do {
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
833 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
834 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
835 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
836 }
837
793b883e 838 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 839
2eaba1a2
SH		 840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
842
e07b1aa8 843 spin_lock_bh(&sky2->phy_lock);
b96936da 844 sky2_phy_power_up(hw, port);
cd28ab6a 845 sky2_phy_init(hw, port);
e07b1aa8 846 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 847
848 /* MIB clear */
849 reg = gma_read16(hw, port, GM_PHY_ADDR);
850 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
851
43f2f104
SH		 852 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
853 gma_read16(hw, port, i);
cd28ab6a
SH		 854 gma_write16(hw, port, GM_PHY_ADDR, reg);
855
856 /* transmit control */
857 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
858
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw, port, GM_RX_CTRL,
793b883e 861 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 862
863 /* transmit flow control */
864 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
865
866 /* transmit parameter */
867 gma_write16(hw, port, GM_TX_PARAM,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
872
873 /* serial mode register */
874 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 875 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 876
6b1a3aef 877 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 878 reg |= GM_SMOD_JUMBO_ENA;
879
c1cd0a85 880 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
881 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
882 reg |= GM_NEW_FLOW_CTRL;
883
cd28ab6a
SH		 884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
885
cd28ab6a
SH		 886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
888
793b883e
SH		 889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
891
892 /* ignore counter overflows */
cd28ab6a
SH		 893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
896
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 902 rx_reg |= GMF_RX_OVER_ON;
69161611 903
25cccecc 904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 905
798fdd07
SH		 906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
909 } else {
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
912 }
cd28ab6a 913
8df9a876 914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
919 reg = 0x178;
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 921
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 925
e0c28116 926 /* On chips without ram buffer, pause is controled by MAC level */
39dbd958 927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 928 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 929 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
930 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 931 reg = 1568 / 8;
932 else
933 reg = 1024 / 8;
934 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
935 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 936
69161611 937 sky2_set_tx_stfwd(hw, port);
5a5b1ea0
SH		 938 }
939
e970d1f8
SH		 940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
942 /* disable dynamic watermark */
943 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
944 reg &= ~TX_DYN_WM_ENA;
945 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
946 }
cd28ab6a
SH		 947}
948
67712901
SH		 949/* Assign Ram Buffer allocation to queue */
950static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 951{
67712901
SH		 952 u32 end;
953
954 /* convert from K bytes to qwords used for hw register */
955 start *= 1024/8;
956 space *= 1024/8;
957 end = start + space - 1;
793b883e 958
cd28ab6a
SH		 959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
960 sky2_write32(hw, RB_ADDR(q, RB_START), start);
961 sky2_write32(hw, RB_ADDR(q, RB_END), end);
962 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
963 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
964
965 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 966 u32 tp = space - space/4;
793b883e 967
1c28f6ba
SH		 968 /* On receive queue's set the thresholds
969 * give receiver priority when > 3/4 full
970 * send pause when down to 2K
971 */
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 974
1c28f6ba
SH		 975 tp = space - 2048/8;
976 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
977 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 978 } else {
979 /* Enable store & forward on Tx queue's because
980 * Tx FIFO is only 1K on Yukon
981 */
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
983 }
984
985 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 986 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 987}
988
cd28ab6a 989/* Setup Bus Memory Interface */
af4ed7e6 990static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 991{
992 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 995 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 996}
997
cd28ab6a
SH		 998/* Setup prefetch unit registers. This is the interface between
999 * hardware and driver list elements
1000 */
8cc048e3 1001static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1002 dma_addr_t addr, u32 last)
cd28ab6a 1003{
cd28ab6a
SH		 1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1008 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1010
1011 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1012}
1013
9b289c33 1014static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1015{
9b289c33 1016 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1017
ee5f68fe 1018 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1019 le->ctrl = 0;
793b883e
SH		 1020 return le;
1021}
cd28ab6a 1022
88f5f0ca
SH		 1023static void tx_init(struct sky2_port *sky2)
1024{
1025 struct sky2_tx_le *le;
1026
1027 sky2->tx_prod = sky2->tx_cons = 0;
1028 sky2->tx_tcpsum = 0;
1029 sky2->tx_last_mss = 0;
1030
9b289c33 1031 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1032 le->addr = 0;
1033 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1034 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1035}
1036
290d4de5
SH		 1037/* Update chip's next pointer */
1038static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1039{
50432cb5 1040 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1041 wmb();
50432cb5
SH		 1042 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1043
1044 /* Synchronize I/O on since next processor may write to tail */
1045 mmiowb();
cd28ab6a
SH		 1046}
1047
793b883e 1048
cd28ab6a
SH		 1049static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1050{
1051 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1052 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1053 le->ctrl = 0;
cd28ab6a
SH		 1054 return le;
1055}
1056
39ef110b
MM		 1057static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1058{
1059 unsigned size;
1060
1061 /* Space needed for frame data + headers rounded up */
1062 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1063
1064 /* Stopping point for hardware truncation */
1065 return (size - 8) / sizeof(u32);
1066}
1067
1068static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1069{
1070 struct rx_ring_info *re;
1071 unsigned size;
1072
1073 /* Space needed for frame data + headers rounded up */
1074 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1075
1076 sky2->rx_nfrags = size >> PAGE_SHIFT;
1077 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1078
1079 /* Compute residue after pages */
1080 size -= sky2->rx_nfrags << PAGE_SHIFT;
1081
1082 /* Optimize to handle small packets and headers */
1083 if (size < copybreak)
1084 size = copybreak;
1085 if (size < ETH_HLEN)
1086 size = ETH_HLEN;
1087
1088 return size;
1089}
1090
14d0263f
SH		 1091/* Build description to hardware for one receive segment */
1092static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1093 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1094{
1095 struct sky2_rx_le *le;
1096
86c6887e 1097 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1098 le = sky2_next_rx(sky2);
86c6887e 1099 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1100 le->opcode = OP_ADDR64 | HW_OWNER;
1101 }
793b883e 1102
cd28ab6a 1103 le = sky2_next_rx(sky2);
d6e74b6b 1104 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1105 le->length = cpu_to_le16(len);
14d0263f 1106 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1107}
1108
14d0263f
SH		 1109/* Build description to hardware for one possibly fragmented skb */
1110static void sky2_rx_submit(struct sky2_port *sky2,
1111 const struct rx_ring_info *re)
1112{
1113 int i;
1114
1115 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1116
1117 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1118 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1119}
1120
1121
454e6cb6 1122static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1123 unsigned size)
1124{
1125 struct sk_buff *skb = re->skb;
1126 int i;
1127
1128 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1129 if (pci_dma_mapping_error(pdev, re->data_addr))
1130 goto mapping_error;
454e6cb6 1131
14d0263f
SH		 1132 pci_unmap_len_set(re, data_size, size);
1133
3fbd9187 1134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1136
1137 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1138 frag->page_offset,
1139 frag->size,
14d0263f 1140 PCI_DMA_FROMDEVICE);
3fbd9187 1141
1142 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1143 goto map_page_error;
1144 }
454e6cb6 1145 return 0;
3fbd9187 1146
1147map_page_error:
1148 while (--i >= 0) {
1149 pci_unmap_page(pdev, re->frag_addr[i],
1150 skb_shinfo(skb)->frags[i].size,
1151 PCI_DMA_FROMDEVICE);
1152 }
1153
1154 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1155 PCI_DMA_FROMDEVICE);
1156
1157mapping_error:
1158 if (net_ratelimit())
1159 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1160 skb->dev->name);
1161 return -EIO;
14d0263f
SH		 1162}
1163
1164static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1165{
1166 struct sk_buff *skb = re->skb;
1167 int i;
1168
1169 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1170 PCI_DMA_FROMDEVICE);
1171
1172 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1173 pci_unmap_page(pdev, re->frag_addr[i],
1174 skb_shinfo(skb)->frags[i].size,
1175 PCI_DMA_FROMDEVICE);
1176}
793b883e 1177
cd28ab6a
SH		 1178/* Tell chip where to start receive checksum.
1179 * Actually has two checksums, but set both same to avoid possible byte
1180 * order problems.
1181 */
793b883e 1182static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1183{
ea76e635 1184 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1185
ea76e635
SH		 1186 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1187 le->ctrl = 0;
1188 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1189
ea76e635
SH		 1190 sky2_write32(sky2->hw,
1191 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
0ea065e5
SH		 1192 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1193 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1194}
1195
bf73130d
SH		 1196/* Enable/disable receive hash calculation (RSS) */
1197static void rx_set_rss(struct net_device *dev)
1198{
1199 struct sky2_port *sky2 = netdev_priv(dev);
1200 struct sky2_hw *hw = sky2->hw;
1201 int i, nkeys = 4;
1202
1203 /* Supports IPv6 and other modes */
1204 if (hw->flags & SKY2_HW_NEW_LE) {
1205 nkeys = 10;
1206 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1207 }
1208
1209 /* Program RSS initial values */
1210 if (dev->features & NETIF_F_RXHASH) {
1211 u32 key[nkeys];
1212
1213 get_random_bytes(key, nkeys * sizeof(u32));
1214 for (i = 0; i < nkeys; i++)
1215 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1216 key[i]);
1217
1218 /* Need to turn on (undocumented) flag to make hashing work */
1219 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1220 RX_STFW_ENA);
1221
1222 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1223 BMU_ENA_RX_RSS_HASH);
1224 } else
1225 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1226 BMU_DIS_RX_RSS_HASH);
1227}
1228
6b1a3aef
SH		 1229/*
1230 * The RX Stop command will not work for Yukon-2 if the BMU does not
1231 * reach the end of packet and since we can't make sure that we have
1232 * incoming data, we must reset the BMU while it is not doing a DMA
1233 * transfer. Since it is possible that the RX path is still active,
1234 * the RX RAM buffer will be stopped first, so any possible incoming
1235 * data will not trigger a DMA. After the RAM buffer is stopped, the
1236 * BMU is polled until any DMA in progress is ended and only then it
1237 * will be reset.
1238 */
1239static void sky2_rx_stop(struct sky2_port *sky2)
1240{
1241 struct sky2_hw *hw = sky2->hw;
1242 unsigned rxq = rxqaddr[sky2->port];
1243 int i;
1244
1245 /* disable the RAM Buffer receive queue */
1246 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1247
1248 for (i = 0; i < 0xffff; i++)
1249 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1250 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1251 goto stopped;
1252
ada1db5c 1253 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef
SH		 1254stopped:
1255 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1256
1257 /* reset the Rx prefetch unit */
1258 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1259 mmiowb();
6b1a3aef 1260}
793b883e 1261
d571b694 1262/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1263static void sky2_rx_clean(struct sky2_port *sky2)
1264{
1265 unsigned i;
1266
1267 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1268 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1269 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1270
1271 if (re->skb) {
14d0263f 1272 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1273 kfree_skb(re->skb);
1274 re->skb = NULL;
1275 }
1276 }
1277}
1278
ef743d33
SH		 1279/* Basic MII support */
1280static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1281{
1282 struct mii_ioctl_data *data = if_mii(ifr);
1283 struct sky2_port *sky2 = netdev_priv(dev);
1284 struct sky2_hw *hw = sky2->hw;
1285 int err = -EOPNOTSUPP;
1286
1287 if (!netif_running(dev))
1288 return -ENODEV; /* Phy still in reset */
1289
d89e1343 1290 switch (cmd) {
ef743d33
SH		 1291 case SIOCGMIIPHY:
1292 data->phy_id = PHY_ADDR_MARV;
1293
1294 /* fallthru */
1295 case SIOCGMIIREG: {
1296 u16 val = 0;
91c86df5 1297
e07b1aa8 1298 spin_lock_bh(&sky2->phy_lock);
ef743d33 1299 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1300 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1301
ef743d33
SH		 1302 data->val_out = val;
1303 break;
1304 }
1305
1306 case SIOCSMIIREG:
e07b1aa8 1307 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1308 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1309 data->val_in);
e07b1aa8 1310 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1311 break;
1312 }
1313 return err;
1314}
1315
d1f13708 1316#ifdef SKY2_VLAN_TAG_USED
d494eacd 1317static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
d1f13708 1318{
d494eacd 1319 if (onoff) {
3d4e66f5
SH		 1320 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1321 RX_VLAN_STRIP_ON);
1322 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1323 TX_VLAN_TAG_ON);
1324 } else {
1325 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1326 RX_VLAN_STRIP_OFF);
1327 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1328 TX_VLAN_TAG_OFF);
1329 }
d494eacd
SH		 1330}
1331
1332static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1333{
1334 struct sky2_port *sky2 = netdev_priv(dev);
1335 struct sky2_hw *hw = sky2->hw;
1336 u16 port = sky2->port;
1337
1338 netif_tx_lock_bh(dev);
1339 napi_disable(&hw->napi);
1340
1341 sky2->vlgrp = grp;
1342 sky2_set_vlan_mode(hw, port, grp != NULL);
d1f13708 1343
d1d08d12 1344 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 1345 napi_enable(&hw->napi);
2bb8c262 1346 netif_tx_unlock_bh(dev);
d1f13708
SH		 1347}
1348#endif
1349
bd1c6869
SH		 1350/* Amount of required worst case padding in rx buffer */
1351static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1352{
1353 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1354}
1355
82788c7a 1356/*
14d0263f
SH		 1357 * Allocate an skb for receiving. If the MTU is large enough
1358 * make the skb non-linear with a fragment list of pages.
82788c7a 1359 */
14d0263f 1360static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1361{
1362 struct sk_buff *skb;
14d0263f 1363 int i;
82788c7a 1364
724b6942
SH		 1365 skb = netdev_alloc_skb(sky2->netdev,
1366 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
bd1c6869
SH		 1367 if (!skb)
1368 goto nomem;
1369
39dbd958 1370 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1371 unsigned char *start;
1372 /*
1373 * Workaround for a bug in FIFO that cause hang
1374 * if the FIFO if the receive buffer is not 64 byte aligned.
1375 * The buffer returned from netdev_alloc_skb is
1376 * aligned except if slab debugging is enabled.
1377 */
f03b8654
SH		 1378 start = PTR_ALIGN(skb->data, 8);
1379 skb_reserve(skb, start - skb->data);
bd1c6869 1380 } else
f03b8654 1381 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1382
1383 for (i = 0; i < sky2->rx_nfrags; i++) {
1384 struct page *page = alloc_page(GFP_ATOMIC);
1385
1386 if (!page)
1387 goto free_partial;
1388 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1389 }
1390
1391 return skb;
14d0263f
SH		 1392free_partial:
1393 kfree_skb(skb);
1394nomem:
1395 return NULL;
82788c7a
SH		 1396}
1397
55c9dd35
SH		 1398static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1399{
1400 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1401}
1402
200ac492
MM		 1403static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1404{
1405 struct sky2_hw *hw = sky2->hw;
1406 unsigned i;
1407
1408 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1409
1410 /* Fill Rx ring */
1411 for (i = 0; i < sky2->rx_pending; i++) {
1412 struct rx_ring_info *re = sky2->rx_ring + i;
1413
1414 re->skb = sky2_rx_alloc(sky2);
1415 if (!re->skb)
1416 return -ENOMEM;
1417
1418 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1419 dev_kfree_skb(re->skb);
1420 re->skb = NULL;
1421 return -ENOMEM;
1422 }
1423 }
1424 return 0;
1425}
1426
cd28ab6a 1427/*
200ac492 1428 * Setup receiver buffer pool.
14d0263f
SH		 1429 * Normal case this ends up creating one list element for skb
1430 * in the receive ring. Worst case if using large MTU and each
1431 * allocation falls on a different 64 bit region, that results
1432 * in 6 list elements per ring entry.
1433 * One element is used for checksum enable/disable, and one
1434 * extra to avoid wrap.
cd28ab6a 1435 */
200ac492 1436static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1437{
6b1a3aef 1438 struct sky2_hw *hw = sky2->hw;
14d0263f 1439 struct rx_ring_info *re;
6b1a3aef 1440 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1441 unsigned i, thresh;
cd28ab6a 1442
6b1a3aef 1443 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1444 sky2_qset(hw, rxq);
977bdf06 1445
c3905bc4
SH		 1446 /* On PCI express lowering the watermark gives better performance */
1447 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1448 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1449
1450 /* These chips have no ram buffer?
1451 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1452 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1453 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1454 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1455
6b1a3aef
SH		 1456 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1457
ea76e635
SH		 1458 if (!(hw->flags & SKY2_HW_NEW_LE))
1459 rx_set_checksum(sky2);
14d0263f 1460
bf73130d
SH		 1461 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1462 rx_set_rss(sky2->netdev);
1463
200ac492 1464 /* submit Rx ring */
793b883e 1465 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1466 re = sky2->rx_ring + i;
14d0263f 1467 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1468 }
1469
a1433ac4
SH		 1470 /*
1471 * The receiver hangs if it receives frames larger than the
1472 * packet buffer. As a workaround, truncate oversize frames, but
1473 * the register is limited to 9 bits, so if you do frames > 2052
1474 * you better get the MTU right!
1475 */
39ef110b 1476 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1477 if (thresh > 0x1ff)
1478 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1479 else {
1480 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1481 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1482 }
1483
6b1a3aef 1484 /* Tell chip about available buffers */
55c9dd35 1485 sky2_rx_update(sky2, rxq);
877c8570
SH		 1486
1487 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1488 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1489 /*
1490 * Disable flushing of non ASF packets;
1491 * must be done after initializing the BMUs;
1492 * drivers without ASF support should do this too, otherwise
1493 * it may happen that they cannot run on ASF devices;
1494 * remember that the MAC FIFO isn't reset during initialization.
1495 */
1496 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1497 }
1498
1499 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1500 /* Enable RX Home Address & Routing Header checksum fix */
1501 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1502 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1503
1504 /* Enable TX Home Address & Routing Header checksum fix */
1505 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1506 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1507 }
cd28ab6a
SH		 1508}
1509
90bbebb4
MM		 1510static int sky2_alloc_buffers(struct sky2_port *sky2)
1511{
1512 struct sky2_hw *hw = sky2->hw;
1513
1514 /* must be power of 2 */
1515 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1516 sky2->tx_ring_size *
1517 sizeof(struct sky2_tx_le),
1518 &sky2->tx_le_map);
1519 if (!sky2->tx_le)
1520 goto nomem;
1521
1522 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1523 GFP_KERNEL);
1524 if (!sky2->tx_ring)
1525 goto nomem;
1526
1527 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1528 &sky2->rx_le_map);
1529 if (!sky2->rx_le)
1530 goto nomem;
1531 memset(sky2->rx_le, 0, RX_LE_BYTES);
1532
1533 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1534 GFP_KERNEL);
1535 if (!sky2->rx_ring)
1536 goto nomem;
1537
200ac492 1538 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1539nomem:
1540 return -ENOMEM;
1541}
1542
1543static void sky2_free_buffers(struct sky2_port *sky2)
1544{
1545 struct sky2_hw *hw = sky2->hw;
1546
200ac492
MM		 1547 sky2_rx_clean(sky2);
1548
90bbebb4
MM		 1549 if (sky2->rx_le) {
1550 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1551 sky2->rx_le, sky2->rx_le_map);
1552 sky2->rx_le = NULL;
1553 }
1554 if (sky2->tx_le) {
1555 pci_free_consistent(hw->pdev,
1556 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1557 sky2->tx_le, sky2->tx_le_map);
1558 sky2->tx_le = NULL;
1559 }
1560 kfree(sky2->tx_ring);
1561 kfree(sky2->rx_ring);
1562
1563 sky2->tx_ring = NULL;
1564 sky2->rx_ring = NULL;
1565}
1566
ea0f71e5 1567static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1568{
cd28ab6a
SH		 1569 struct sky2_hw *hw = sky2->hw;
1570 unsigned port = sky2->port;
ea0f71e5
MM		 1571 u32 ramsize;
1572 int cap;
843a46f4 1573 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1574
ea0f71e5
MM		 1575 tx_init(sky2);
1576
ee7abb04
SH		 1577 /*
1578 * On dual port PCI-X card, there is an problem where status
1579 * can be received out of order due to split transactions
843a46f4 1580 */
ee7abb04
SH		 1581 if (otherdev && netif_running(otherdev) &&
1582 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1583 u16 cmd;
1584
b32f40c4 1585 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1586 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1587 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1588 }
cd28ab6a 1589
cd28ab6a
SH		 1590 sky2_mac_init(hw, port);
1591
e0c28116
SH		 1592 /* Register is number of 4K blocks on internal RAM buffer. */
1593 ramsize = sky2_read8(hw, B2_E_0) * 4;
1594 if (ramsize > 0) {
67712901 1595 u32 rxspace;
cd28ab6a 1596
ada1db5c 1597 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1598 if (ramsize < 16)
1599 rxspace = ramsize / 2;
1600 else
1601 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1602
67712901
SH		 1603 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1604 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1605
1606 /* Make sure SyncQ is disabled */
1607 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1608 RB_RST_SET);
1609 }
793b883e 1610
af4ed7e6 1611 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1612
69161611
SH		 1613 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1614 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1615 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1616
977bdf06 1617 /* Set almost empty threshold */
8e95a202
JP		 1618 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1619 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1620 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1621
6b1a3aef 1622 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1623 sky2->tx_ring_size - 1);
cd28ab6a 1624
d494eacd
SH		 1625#ifdef SKY2_VLAN_TAG_USED
1626 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1627#endif
1628
200ac492 1629 sky2_rx_start(sky2);
ea0f71e5
MM		 1630}
1631
1632/* Bring up network interface. */
1633static int sky2_up(struct net_device *dev)
1634{
1635 struct sky2_port *sky2 = netdev_priv(dev);
1636 struct sky2_hw *hw = sky2->hw;
1637 unsigned port = sky2->port;
1638 u32 imask;
1639 int err;
1640
1641 netif_carrier_off(dev);
1642
1643 err = sky2_alloc_buffers(sky2);
1644 if (err)
1645 goto err_out;
1646
1647 sky2_hw_up(sky2);
cd28ab6a 1648
cd28ab6a 1649 /* Enable interrupts from phy/mac for port */
e07b1aa8 1650 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1651 imask |= portirq_msk[port];
e07b1aa8 1652 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1653 sky2_read32(hw, B0_IMSK);
e07b1aa8 1654
6c35abae 1655 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1656
cd28ab6a
SH		 1657 return 0;
1658
1659err_out:
90bbebb4 1660 sky2_free_buffers(sky2);
cd28ab6a
SH		 1661 return err;
1662}
1663
793b883e 1664/* Modular subtraction in ring */
ee5f68fe 1665static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1666{
ee5f68fe 1667 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1668}
cd28ab6a 1669
793b883e
SH		 1670/* Number of list elements available for next tx */
1671static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1672{
ee5f68fe 1673 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1674}
1675
793b883e 1676/* Estimate of number of transmit list elements required */
28bd181a 1677static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1678{
793b883e
SH		 1679 unsigned count;
1680
07e31637
SH		 1681 count = (skb_shinfo(skb)->nr_frags + 1)
1682 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1683
89114afd 1684 if (skb_is_gso(skb))
793b883e 1685 ++count;
07e31637
SH		 1686 else if (sizeof(dma_addr_t) == sizeof(u32))
1687 ++count; /* possible vlan */
793b883e 1688
84fa7933 1689 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1690 ++count;
1691
1692 return count;
cd28ab6a
SH		 1693}
1694
f6815077 1695static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1696{
1697 if (re->flags & TX_MAP_SINGLE)
1698 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1699 pci_unmap_len(re, maplen),
1700 PCI_DMA_TODEVICE);
1701 else if (re->flags & TX_MAP_PAGE)
1702 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1703 pci_unmap_len(re, maplen),
1704 PCI_DMA_TODEVICE);
f6815077 1705 re->flags = 0;
6b84daca
SH		 1706}
1707
793b883e
SH		 1708/*
1709 * Put one packet in ring for transmit.
1710 * A single packet can generate multiple list elements, and
1711 * the number of ring elements will probably be less than the number
1712 * of list elements used.
1713 */
61357325
SH		 1714static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1715 struct net_device *dev)
cd28ab6a
SH		 1716{
1717 struct sky2_port *sky2 = netdev_priv(dev);
1718 struct sky2_hw *hw = sky2->hw;
d1f13708 1719 struct sky2_tx_le *le = NULL;
6cdbbdf3 1720 struct tx_ring_info *re;
9b289c33 1721 unsigned i, len;
cd28ab6a 1722 dma_addr_t mapping;
5dce95e5
SH		 1723 u32 upper;
1724 u16 slot;
cd28ab6a
SH		 1725 u16 mss;
1726 u8 ctrl;
1727
2bb8c262
SH		 1728 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1729 return NETDEV_TX_BUSY;
cd28ab6a 1730
cd28ab6a
SH		 1731 len = skb_headlen(skb);
1732 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1733
454e6cb6
SH		 1734 if (pci_dma_mapping_error(hw->pdev, mapping))
1735 goto mapping_error;
1736
9b289c33 1737 slot = sky2->tx_prod;
6c35abae
JP		 1738 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1739 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1740
86c6887e 1741 /* Send high bits if needed */
5dce95e5
SH		 1742 upper = upper_32_bits(mapping);
1743 if (upper != sky2->tx_last_upper) {
9b289c33 1744 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1745 le->addr = cpu_to_le32(upper);
1746 sky2->tx_last_upper = upper;
793b883e 1747 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1748 }
cd28ab6a
SH		 1749
1750 /* Check for TCP Segmentation Offload */
7967168c 1751 mss = skb_shinfo(skb)->gso_size;
793b883e 1752 if (mss != 0) {
ea76e635
SH		 1753
1754 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1755 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1756
1757 if (mss != sky2->tx_last_mss) {
9b289c33 1758 le = get_tx_le(sky2, &slot);
69161611 1759 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1760
1761 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1762 le->opcode = OP_MSS | HW_OWNER;
1763 else
1764 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1765 sky2->tx_last_mss = mss;
1766 }
cd28ab6a
SH		 1767 }
1768
cd28ab6a 1769 ctrl = 0;
d1f13708
SH		 1770#ifdef SKY2_VLAN_TAG_USED
1771 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1772 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1773 if (!le) {
9b289c33 1774 le = get_tx_le(sky2, &slot);
f65b138c 1775 le->addr = 0;
d1f13708 1776 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1777 } else
1778 le->opcode |= OP_VLAN;
1779 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1780 ctrl |= INS_VLAN;
1781 }
1782#endif
1783
1784 /* Handle TCP checksum offload */
84fa7933 1785 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1786 /* On Yukon EX (some versions) encoding change. */
ea76e635 1787 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1788 ctrl |= CALSUM; /* auto checksum */
1789 else {
1790 const unsigned offset = skb_transport_offset(skb);
1791 u32 tcpsum;
1792
1793 tcpsum = offset << 16; /* sum start */
1794 tcpsum |= offset + skb->csum_offset; /* sum write */
1795
1796 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1797 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1798 ctrl |= UDPTCP;
1799
1800 if (tcpsum != sky2->tx_tcpsum) {
1801 sky2->tx_tcpsum = tcpsum;
1802
9b289c33 1803 le = get_tx_le(sky2, &slot);
69161611
SH		 1804 le->addr = cpu_to_le32(tcpsum);
1805 le->length = 0; /* initial checksum value */
1806 le->ctrl = 1; /* one packet */
1807 le->opcode = OP_TCPLISW | HW_OWNER;
1808 }
1d179332 1809 }
cd28ab6a
SH		 1810 }
1811
6b84daca
SH		 1812 re = sky2->tx_ring + slot;
1813 re->flags = TX_MAP_SINGLE;
1814 pci_unmap_addr_set(re, mapaddr, mapping);
1815 pci_unmap_len_set(re, maplen, len);
1816
9b289c33 1817 le = get_tx_le(sky2, &slot);
d6e74b6b 1818 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1819 le->length = cpu_to_le16(len);
1820 le->ctrl = ctrl;
793b883e 1821 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1822
cd28ab6a
SH		 1823
1824 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1825 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1826
1827 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1828 frag->size, PCI_DMA_TODEVICE);
86c6887e 1829
454e6cb6
SH		 1830 if (pci_dma_mapping_error(hw->pdev, mapping))
1831 goto mapping_unwind;
1832
5dce95e5
SH		 1833 upper = upper_32_bits(mapping);
1834 if (upper != sky2->tx_last_upper) {
9b289c33 1835 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1836 le->addr = cpu_to_le32(upper);
1837 sky2->tx_last_upper = upper;
793b883e 1838 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1839 }
1840
6b84daca
SH		 1841 re = sky2->tx_ring + slot;
1842 re->flags = TX_MAP_PAGE;
1843 pci_unmap_addr_set(re, mapaddr, mapping);
1844 pci_unmap_len_set(re, maplen, frag->size);
1845
9b289c33 1846 le = get_tx_le(sky2, &slot);
d6e74b6b 1847 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1848 le->length = cpu_to_le16(frag->size);
1849 le->ctrl = ctrl;
793b883e 1850 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1851 }
6cdbbdf3 1852
6b84daca 1853 re->skb = skb;
cd28ab6a
SH		 1854 le->ctrl |= EOP;
1855
9b289c33
MM		 1856 sky2->tx_prod = slot;
1857
97bda706
SH		 1858 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1859 netif_stop_queue(dev);
b19666d9 1860
290d4de5 1861 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1862
cd28ab6a 1863 return NETDEV_TX_OK;
454e6cb6
SH		 1864
1865mapping_unwind:
ee5f68fe 1866 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1867 re = sky2->tx_ring + i;
1868
6b84daca 1869 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1870 }
1871
454e6cb6
SH		 1872mapping_error:
1873 if (net_ratelimit())
1874 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1875 dev_kfree_skb(skb);
1876 return NETDEV_TX_OK;
cd28ab6a
SH		 1877}
1878
cd28ab6a 1879/*
793b883e
SH		 1880 * Free ring elements from starting at tx_cons until "done"
1881 *
481cea4a
SH		 1882 * NB:
1883 * 1. The hardware will tell us about partial completion of multi-part
291ea614 1884 * buffers so make sure not to free skb to early.
481cea4a
SH		 1885 * 2. This may run in parallel start_xmit because the it only
1886 * looks at the tail of the queue of FIFO (tx_cons), not
1887 * the head (tx_prod)
cd28ab6a 1888 */
d11c13e7 1889static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1890{
d11c13e7 1891 struct net_device *dev = sky2->netdev;
291ea614 1892 unsigned idx;
cd28ab6a 1893
ee5f68fe 1894 BUG_ON(done >= sky2->tx_ring_size);
2224795d 1895
291ea614 1896 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 1897 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 1898 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 1899 struct sk_buff *skb = re->skb;
291ea614 1900
6b84daca 1901 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 1902
6b84daca 1903 if (skb) {
6c35abae
JP		 1904 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1905 "tx done %u\n", idx);
3cf26753 1906
7138a0f5 1907 dev->stats.tx_packets++;
bd1c6869
SH		 1908 dev->stats.tx_bytes += skb->len;
1909
f6815077 1910 re->skb = NULL;
724b6942 1911 dev_kfree_skb_any(skb);
2bf56fe2 1912
ee5f68fe 1913 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 1914 }
793b883e 1915 }
793b883e 1916
291ea614 1917 sky2->tx_cons = idx;
50432cb5 1918 smp_mb();
cd28ab6a
SH		 1919}
1920
264bb4fa 1921static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 1922{
a510996b
MM		 1923 /* Disable Force Sync bit and Enable Alloc bit */
1924 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1925 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1926
1927 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1928 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1929 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1930
1931 /* Reset the PCI FIFO of the async Tx queue */
1932 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1933 BMU_RST_SET | BMU_FIFO_RST);
1934
1935 /* Reset the Tx prefetch units */
1936 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1937 PREF_UNIT_RST_SET);
1938
1939 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1940 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1941}
1942
f2b31cb3 1943static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 1944{
cd28ab6a
SH		 1945 struct sky2_hw *hw = sky2->hw;
1946 unsigned port = sky2->port;
f2b31cb3 1947 u16 ctrl;
cd28ab6a 1948
d104acaf
SH		 1949 /* Force flow control off */
1950 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 1951
cd28ab6a
SH		 1952 /* Stop transmitter */
1953 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1954 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1955
1956 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1957 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1958
1959 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1960 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1961 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1962
1963 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1964
1965 /* Workaround shared GMAC reset */
8e95a202
JP		 1966 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1967 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1968 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1969
cd28ab6a 1970 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 1971
6c83504f
SH		 1972 /* Force any delayed status interrrupt and NAPI */
1973 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1974 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1975 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1976 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1977
a947a39d
MM		 1978 sky2_rx_stop(sky2);
1979
0da6d7b3 1980 spin_lock_bh(&sky2->phy_lock);
b96936da 1981 sky2_phy_power_down(hw, port);
0da6d7b3 1982 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 1983
264bb4fa
MM		 1984 sky2_tx_reset(hw, port);
1985
481cea4a
SH		 1986 /* Free any pending frames stuck in HW queue */
1987 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 1988}
1989
1990/* Network shutdown */
1991static int sky2_down(struct net_device *dev)
1992{
1993 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 1994 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 1995
1996 /* Never really got started! */
1997 if (!sky2->tx_le)
1998 return 0;
1999
6c35abae 2000 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2001
8a0c9228
MM		 2002 /* Disable port IRQ */
2003 sky2_write32(hw, B0_IMSK,
2004 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2005 sky2_read32(hw, B0_IMSK);
2006
2007 synchronize_irq(hw->pdev->irq);
2008 napi_synchronize(&hw->napi);
2009
f2b31cb3 2010 sky2_hw_down(sky2);
481cea4a 2011
90bbebb4 2012 sky2_free_buffers(sky2);
1b537565 2013
cd28ab6a
SH		 2014 return 0;
2015}
2016
2017static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2018{
ea76e635 2019 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2020 return SPEED_1000;
2021
05745c4a
SH		 2022 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2023 if (aux & PHY_M_PS_SPEED_100)
2024 return SPEED_100;
2025 else
2026 return SPEED_10;
2027 }
cd28ab6a
SH		 2028
2029 switch (aux & PHY_M_PS_SPEED_MSK) {
2030 case PHY_M_PS_SPEED_1000:
2031 return SPEED_1000;
2032 case PHY_M_PS_SPEED_100:
2033 return SPEED_100;
2034 default:
2035 return SPEED_10;
2036 }
2037}
2038
2039static void sky2_link_up(struct sky2_port *sky2)
2040{
2041 struct sky2_hw *hw = sky2->hw;
2042 unsigned port = sky2->port;
2043 u16 reg;
16ad91e1
SH		 2044 static const char *fc_name[] = {
2045 [FC_NONE] = "none",
2046 [FC_TX] = "tx",
2047 [FC_RX] = "rx",
2048 [FC_BOTH] = "both",
2049 };
cd28ab6a 2050
cd28ab6a 2051 /* enable Rx/Tx */
2eaba1a2 2052 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 2053 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2054 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 2055
2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2057
2058 netif_carrier_on(sky2->netdev);
cd28ab6a 2059
75e80683 2060 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2061
cd28ab6a 2062 /* Turn on link LED */
793b883e 2063 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2064 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2065
6c35abae
JP		 2066 netif_info(sky2, link, sky2->netdev,
2067 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2068 sky2->speed,
2069 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2070 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2071}
2072
2073static void sky2_link_down(struct sky2_port *sky2)
2074{
2075 struct sky2_hw *hw = sky2->hw;
2076 unsigned port = sky2->port;
2077 u16 reg;
2078
2079 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2080
2081 reg = gma_read16(hw, port, GM_GP_CTRL);
2082 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2083 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2084
cd28ab6a 2085 netif_carrier_off(sky2->netdev);
cd28ab6a 2086
809aaaae 2087 /* Turn off link LED */
cd28ab6a
SH		 2088 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2089
6c35abae 2090 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2091
cd28ab6a
SH		 2092 sky2_phy_init(hw, port);
2093}
2094
16ad91e1
SH		 2095static enum flow_control sky2_flow(int rx, int tx)
2096{
2097 if (rx)
2098 return tx ? FC_BOTH : FC_RX;
2099 else
2100 return tx ? FC_TX : FC_NONE;
2101}
2102
793b883e
SH		 2103static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2104{
2105 struct sky2_hw *hw = sky2->hw;
2106 unsigned port = sky2->port;
da4c1ff4 2107 u16 advert, lpa;
793b883e 2108
da4c1ff4 2109 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2110 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2111 if (lpa & PHY_M_AN_RF) {
ada1db5c 2112 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2113 return -1;
2114 }
2115
793b883e 2116 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2117 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2118 return -1;
2119 }
2120
793b883e 2121 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2122 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2123
da4c1ff4
SH		 2124 /* Since the pause result bits seem to in different positions on
2125 * different chips. look at registers.
2126 */
ea76e635 2127 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2128 /* Shift for bits in fiber PHY */
2129 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2130 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2131
2132 if (advert & ADVERTISE_1000XPAUSE)
2133 advert |= ADVERTISE_PAUSE_CAP;
2134 if (advert & ADVERTISE_1000XPSE_ASYM)
2135 advert |= ADVERTISE_PAUSE_ASYM;
2136 if (lpa & LPA_1000XPAUSE)
2137 lpa |= LPA_PAUSE_CAP;
2138 if (lpa & LPA_1000XPAUSE_ASYM)
2139 lpa |= LPA_PAUSE_ASYM;
2140 }
793b883e 2141
da4c1ff4
SH		 2142 sky2->flow_status = FC_NONE;
2143 if (advert & ADVERTISE_PAUSE_CAP) {
2144 if (lpa & LPA_PAUSE_CAP)
2145 sky2->flow_status = FC_BOTH;
2146 else if (advert & ADVERTISE_PAUSE_ASYM)
2147 sky2->flow_status = FC_RX;
2148 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2149 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2150 sky2->flow_status = FC_TX;
2151 }
793b883e 2152
8e95a202
JP		 2153 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2154 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2155 sky2->flow_status = FC_NONE;
2eaba1a2 2156
da4c1ff4 2157 if (sky2->flow_status & FC_TX)
793b883e
SH		 2158 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2159 else
2160 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2161
2162 return 0;
2163}
cd28ab6a 2164
e07b1aa8
SH		 2165/* Interrupt from PHY */
2166static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2167{
e07b1aa8
SH		 2168 struct net_device *dev = hw->dev[port];
2169 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2170 u16 istatus, phystat;
2171
ebc646f6
SH		 2172 if (!netif_running(dev))
2173 return;
2174
e07b1aa8
SH		 2175 spin_lock(&sky2->phy_lock);
2176 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2177 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2178
6c35abae
JP		 2179 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2180 istatus, phystat);
cd28ab6a 2181
0ea065e5 2182 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2183 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2184 !netif_carrier_ok(dev))
793b883e
SH		 2185 sky2_link_up(sky2);
2186 goto out;
2187 }
cd28ab6a 2188
793b883e
SH		 2189 if (istatus & PHY_M_IS_LSP_CHANGE)
2190 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2191
793b883e
SH		 2192 if (istatus & PHY_M_IS_DUP_CHANGE)
2193 sky2->duplex =
2194 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2195
793b883e
SH		 2196 if (istatus & PHY_M_IS_LST_CHANGE) {
2197 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2198 sky2_link_up(sky2);
793b883e
SH		 2199 else
2200 sky2_link_down(sky2);
cd28ab6a 2201 }
793b883e 2202out:
e07b1aa8 2203 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2204}
2205
0f5aac70
SH		 2206/* Special quick link interrupt (Yukon-2 Optima only) */
2207static void sky2_qlink_intr(struct sky2_hw *hw)
2208{
2209 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2210 u32 imask;
2211 u16 phy;
2212
2213 /* disable irq */
2214 imask = sky2_read32(hw, B0_IMSK);
2215 imask &= ~Y2_IS_PHY_QLNK;
2216 sky2_write32(hw, B0_IMSK, imask);
2217
2218 /* reset PHY Link Detect */
2219 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2220 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2221 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2222 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2223
2224 sky2_link_up(sky2);
2225}
2226
62335ab0 2227/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2228 * and tx queue is full (stopped).
2229 */
cd28ab6a
SH		 2230static void sky2_tx_timeout(struct net_device *dev)
2231{
2232 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2233 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2234
6c35abae 2235 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2236
ada1db5c
JP		 2237 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2238 sky2->tx_cons, sky2->tx_prod,
2239 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2240 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2241
81906791
SH		 2242 /* can't restart safely under softirq */
2243 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2244}
2245
2246static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2247{
6b1a3aef
SH		 2248 struct sky2_port *sky2 = netdev_priv(dev);
2249 struct sky2_hw *hw = sky2->hw;
b628ed98 2250 unsigned port = sky2->port;
6b1a3aef
SH		 2251 int err;
2252 u16 ctl, mode;
e07b1aa8 2253 u32 imask;
cd28ab6a 2254
44dde56d 2255 /* MTU size outside the spec */
cd28ab6a
SH		 2256 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2257 return -EINVAL;
2258
44dde56d 2259 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2260 if (new_mtu > ETH_DATA_LEN &&
2261 (hw->chip_id == CHIP_ID_YUKON_FE ||
2262 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2263 return -EINVAL;
2264
44dde56d 2265 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2266 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2267 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2268
6b1a3aef
SH		 2269 if (!netif_running(dev)) {
2270 dev->mtu = new_mtu;
2271 return 0;
2272 }
2273
e07b1aa8 2274 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 2275 sky2_write32(hw, B0_IMSK, 0);
2276
018d1c66
SH		 2277 dev->trans_start = jiffies; /* prevent tx timeout */
2278 netif_stop_queue(dev);
bea3348e 2279 napi_disable(&hw->napi);
018d1c66 2280
e07b1aa8
SH		 2281 synchronize_irq(hw->pdev->irq);
2282
39dbd958 2283 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2284 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2285
2286 ctl = gma_read16(hw, port, GM_GP_CTRL);
2287 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef
SH		 2288 sky2_rx_stop(sky2);
2289 sky2_rx_clean(sky2);
cd28ab6a
SH		 2290
2291 dev->mtu = new_mtu;
14d0263f 2292
6b1a3aef
SH		 2293 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2294 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2295
2296 if (dev->mtu > ETH_DATA_LEN)
2297 mode |= GM_SMOD_JUMBO_ENA;
2298
b628ed98 2299 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2300
b628ed98 2301 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2302
200ac492
MM		 2303 err = sky2_alloc_rx_skbs(sky2);
2304 if (!err)
2305 sky2_rx_start(sky2);
2306 else
2307 sky2_rx_clean(sky2);
e07b1aa8 2308 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2309
d1d08d12 2310 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2311 napi_enable(&hw->napi);
2312
1b537565
SH		 2313 if (err)
2314 dev_close(dev);
2315 else {
b628ed98 2316 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2317
1b537565
SH		 2318 netif_wake_queue(dev);
2319 }
2320
cd28ab6a
SH		 2321 return err;
2322}
2323
14d0263f
SH		 2324/* For small just reuse existing skb for next receive */
2325static struct sk_buff *receive_copy(struct sky2_port *sky2,
2326 const struct rx_ring_info *re,
2327 unsigned length)
2328{
2329 struct sk_buff *skb;
2330
89d71a66 2331 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2332 if (likely(skb)) {
14d0263f
SH		 2333 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2334 length, PCI_DMA_FROMDEVICE);
d626f62b 2335 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2336 skb->ip_summed = re->skb->ip_summed;
2337 skb->csum = re->skb->csum;
2338 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2339 length, PCI_DMA_FROMDEVICE);
2340 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2341 skb_put(skb, length);
14d0263f
SH		 2342 }
2343 return skb;
2344}
2345
2346/* Adjust length of skb with fragments to match received data */
2347static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2348 unsigned int length)
2349{
2350 int i, num_frags;
2351 unsigned int size;
2352
2353 /* put header into skb */
2354 size = min(length, hdr_space);
2355 skb->tail += size;
2356 skb->len += size;
2357 length -= size;
2358
2359 num_frags = skb_shinfo(skb)->nr_frags;
2360 for (i = 0; i < num_frags; i++) {
2361 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2362
2363 if (length == 0) {
2364 /* don't need this page */
2365 __free_page(frag->page);
2366 --skb_shinfo(skb)->nr_frags;
2367 } else {
2368 size = min(length, (unsigned) PAGE_SIZE);
2369
2370 frag->size = size;
2371 skb->data_len += size;
2372 skb->truesize += size;
2373 skb->len += size;
2374 length -= size;
2375 }
2376 }
2377}
2378
2379/* Normal packet - take skb from ring element and put in a new one */
2380static struct sk_buff *receive_new(struct sky2_port *sky2,
2381 struct rx_ring_info *re,
2382 unsigned int length)
2383{
3fbd9187 2384 struct sk_buff *skb;
2385 struct rx_ring_info nre;
14d0263f
SH		 2386 unsigned hdr_space = sky2->rx_data_size;
2387
3fbd9187 2388 nre.skb = sky2_rx_alloc(sky2);
2389 if (unlikely(!nre.skb))
2390 goto nobuf;
2391
2392 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2393 goto nomap;
14d0263f
SH		 2394
2395 skb = re->skb;
2396 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2397 prefetch(skb->data);
3fbd9187 2398 *re = nre;
14d0263f
SH		 2399
2400 if (skb_shinfo(skb)->nr_frags)
2401 skb_put_frags(skb, hdr_space, length);
2402 else
489b10c1 2403 skb_put(skb, length);
14d0263f 2404 return skb;
3fbd9187 2405
2406nomap:
2407 dev_kfree_skb(nre.skb);
2408nobuf:
2409 return NULL;
14d0263f
SH		 2410}
2411
cd28ab6a
SH		 2412/*
2413 * Receive one packet.
d571b694 2414 * For larger packets, get new buffer.
cd28ab6a 2415 */
497d7c86 2416static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2417 u16 length, u32 status)
2418{
497d7c86 2419 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2420 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2421 struct sk_buff *skb = NULL;
d6532232
SH		 2422 u16 count = (status & GMR_FS_LEN) >> 16;
2423
2424#ifdef SKY2_VLAN_TAG_USED
2425 /* Account for vlan tag */
2426 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2427 count -= VLAN_HLEN;
2428#endif
cd28ab6a 2429
6c35abae
JP		 2430 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2431 "rx slot %u status 0x%x len %d\n",
2432 sky2->rx_next, status, length);
cd28ab6a 2433
793b883e 2434 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2435 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2436
3b12e014
SH		 2437 /* This chip has hardware problems that generates bogus status.
2438 * So do only marginal checking and expect higher level protocols
2439 * to handle crap frames.
2440 */
2441 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2442 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2443 length != count)
2444 goto okay;
2445
42eeea01 2446 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2447 goto error;
2448
42eeea01
SH		 2449 if (!(status & GMR_FS_RX_OK))
2450 goto resubmit;
2451
d6532232
SH		 2452 /* if length reported by DMA does not match PHY, packet was truncated */
2453 if (length != count)
3b12e014 2454 goto len_error;
71749531 2455
3b12e014 2456okay:
14d0263f
SH		 2457 if (length < copybreak)
2458 skb = receive_copy(sky2, re, length);
2459 else
2460 skb = receive_new(sky2, re, length);
90c30335
SH		 2461
2462 dev->stats.rx_dropped += (skb == NULL);
2463
793b883e 2464resubmit:
14d0263f 2465 sky2_rx_submit(sky2, re);
79e57d32 2466
cd28ab6a
SH		 2467 return skb;
2468
3b12e014 2469len_error:
71749531
SH		 2470 /* Truncation of overlength packets
2471 causes PHY length to not match MAC length */
7138a0f5 2472 ++dev->stats.rx_length_errors;
6c35abae
JP		 2473 if (net_ratelimit())
2474 netif_info(sky2, rx_err, dev,
2475 "rx length error: status %#x length %d\n",
2476 status, length);
d6532232 2477 goto resubmit;
71749531 2478
cd28ab6a 2479error:
7138a0f5 2480 ++dev->stats.rx_errors;
b6d77734 2481 if (status & GMR_FS_RX_FF_OV) {
7138a0f5 2482 dev->stats.rx_over_errors++;
b6d77734
SH		 2483 goto resubmit;
2484 }
6e15b712 2485
6c35abae
JP		 2486 if (net_ratelimit())
2487 netif_info(sky2, rx_err, dev,
2488 "rx error, status 0x%x length %d\n", status, length);
793b883e
SH		 2489
2490 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
7138a0f5 2491 dev->stats.rx_length_errors++;
cd28ab6a 2492 if (status & GMR_FS_FRAGMENT)
7138a0f5 2493 dev->stats.rx_frame_errors++;
cd28ab6a 2494 if (status & GMR_FS_CRC_ERR)
7138a0f5 2495 dev->stats.rx_crc_errors++;
79e57d32 2496
793b883e 2497 goto resubmit;
cd28ab6a
SH		 2498}
2499
e07b1aa8
SH		 2500/* Transmit complete */
2501static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2502{
e07b1aa8 2503 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2504
8a0c9228 2505 if (netif_running(dev)) {
e07b1aa8 2506 sky2_tx_complete(sky2, last);
8a0c9228
MM		 2507
2508 /* Wake unless it's detached, and called e.g. from sky2_down() */
2509 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2510 netif_wake_queue(dev);
2511 }
cd28ab6a
SH		 2512}
2513
37e5a243
SH		 2514static inline void sky2_skb_rx(const struct sky2_port *sky2,
2515 u32 status, struct sk_buff *skb)
2516{
2517#ifdef SKY2_VLAN_TAG_USED
2518 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2519 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2520 if (skb->ip_summed == CHECKSUM_NONE)
2521 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2522 else
2523 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2524 vlan_tag, skb);
2525 return;
2526 }
2527#endif
2528 if (skb->ip_summed == CHECKSUM_NONE)
2529 netif_receive_skb(skb);
2530 else
2531 napi_gro_receive(&sky2->hw->napi, skb);
2532}
2533
bf15fe99
SH		 2534static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2535 unsigned packets, unsigned bytes)
2536{
2537 if (packets) {
2538 struct net_device *dev = hw->dev[port];
2539
2540 dev->stats.rx_packets += packets;
2541 dev->stats.rx_bytes += bytes;
2542 dev->last_rx = jiffies;
2543 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2544 }
2545}
2546
375c5688 2547static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2548{
2549 /* If this happens then driver assuming wrong format for chip type */
2550 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2551
2552 /* Both checksum counters are programmed to start at
2553 * the same offset, so unless there is a problem they
2554 * should match. This failure is an early indication that
2555 * hardware receive checksumming won't work.
2556 */
2557 if (likely((u16)(status >> 16) == (u16)status)) {
2558 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2559 skb->ip_summed = CHECKSUM_COMPLETE;
2560 skb->csum = le16_to_cpu(status);
2561 } else {
2562 dev_notice(&sky2->hw->pdev->dev,
2563 "%s: receive checksum problem (status = %#x)\n",
2564 sky2->netdev->name, status);
2565
2566 /* Disable checksum offload */
2567 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2568 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2569 BMU_DIS_RX_CHKSUM);
2570 }
2571}
2572
bf73130d
SH		 2573static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2574{
2575 struct sk_buff *skb;
2576
2577 skb = sky2->rx_ring[sky2->rx_next].skb;
2578 skb->rxhash = le32_to_cpu(status);
2579}
2580
e07b1aa8 2581/* Process status response ring */
26691830 2582static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2583{
e07b1aa8 2584 int work_done = 0;
bf15fe99
SH		 2585 unsigned int total_bytes[2] = { 0 };
2586 unsigned int total_packets[2] = { 0 };
a8fd6266 2587
af2a58ac 2588 rmb();
26691830 2589 do {
55c9dd35 2590 struct sky2_port *sky2;
13210ce5 2591 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2592 unsigned port;
13210ce5 2593 struct net_device *dev;
cd28ab6a 2594 struct sk_buff *skb;
cd28ab6a
SH		 2595 u32 status;
2596 u16 length;
ab5adecb
SH		 2597 u8 opcode = le->opcode;
2598
2599 if (!(opcode & HW_OWNER))
2600 break;
cd28ab6a 2601
efe91932 2602 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2603
ab5adecb 2604 port = le->css & CSS_LINK_BIT;
69161611 2605 dev = hw->dev[port];
13210ce5 2606 sky2 = netdev_priv(dev);
f65b138c
SH		 2607 length = le16_to_cpu(le->length);
2608 status = le32_to_cpu(le->status);
cd28ab6a 2609
ab5adecb
SH		 2610 le->opcode = 0;
2611 switch (opcode & ~HW_OWNER) {
cd28ab6a 2612 case OP_RXSTAT:
bf15fe99
SH		 2613 total_packets[port]++;
2614 total_bytes[port] += length;
90c30335 2615
497d7c86 2616 skb = sky2_receive(dev, length, status);
90c30335 2617 if (!skb)
55c9dd35 2618 break;
13210ce5 2619
69161611 2620 /* This chip reports checksum status differently */
05745c4a 2621 if (hw->flags & SKY2_HW_NEW_LE) {
0ea065e5 2622 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
69161611
SH		 2623 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2624 (le->css & CSS_TCPUDPCSOK))
2625 skb->ip_summed = CHECKSUM_UNNECESSARY;
2626 else
2627 skb->ip_summed = CHECKSUM_NONE;
2628 }
2629
13210ce5 2630 skb->protocol = eth_type_trans(skb, dev);
13210ce5 2631
37e5a243 2632 sky2_skb_rx(sky2, status, skb);
13210ce5 2633
22e11703 2634 /* Stop after net poll weight */
13210ce5
SH		 2635 if (++work_done >= to_do)
2636 goto exit_loop;
cd28ab6a
SH		 2637 break;
2638
d1f13708
SH		 2639#ifdef SKY2_VLAN_TAG_USED
2640 case OP_RXVLAN:
2641 sky2->rx_tag = length;
2642 break;
2643
2644 case OP_RXCHKSVLAN:
2645 sky2->rx_tag = length;
2646 /* fall through */
2647#endif
cd28ab6a 2648 case OP_RXCHKS:
375c5688 2649 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2650 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2651 break;
2652
bf73130d
SH		 2653 case OP_RSS_HASH:
2654 sky2_rx_hash(sky2, status);
2655 break;
2656
cd28ab6a 2657 case OP_TXINDEXLE:
13b97b74 2658 /* TX index reports status for both ports */
f55925d7 2659 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2660 if (hw->dev[1])
2661 sky2_tx_done(hw->dev[1],
2662 ((status >> 24) & 0xff)
2663 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2664 break;
2665
cd28ab6a
SH		 2666 default:
2667 if (net_ratelimit())
ada1db5c 2668 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2669 }
26691830 2670 } while (hw->st_idx != idx);
cd28ab6a 2671
fe2a24df
SH		 2672 /* Fully processed status ring so clear irq */
2673 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2674
13210ce5 2675exit_loop:
bf15fe99
SH		 2676 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2677 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2678
e07b1aa8 2679 return work_done;
cd28ab6a
SH		 2680}
2681
2682static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2683{
2684 struct net_device *dev = hw->dev[port];
2685
3be92a70 2686 if (net_ratelimit())
ada1db5c 2687 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2688
2689 if (status & Y2_IS_PAR_RD1) {
3be92a70 2690 if (net_ratelimit())
ada1db5c 2691 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2692 /* Clear IRQ */
2693 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2694 }
2695
2696 if (status & Y2_IS_PAR_WR1) {
3be92a70 2697 if (net_ratelimit())
ada1db5c 2698 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2699
2700 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2701 }
2702
2703 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2704 if (net_ratelimit())
ada1db5c 2705 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2706 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2707 }
2708
2709 if (status & Y2_IS_PAR_RX1) {
3be92a70 2710 if (net_ratelimit())
ada1db5c 2711 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2712 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2713 }
2714
2715 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2716 if (net_ratelimit())
ada1db5c 2717 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2718 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2719 }
2720}
2721
2722static void sky2_hw_intr(struct sky2_hw *hw)
2723{
555382cb 2724 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2725 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2726 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2727
2728 status &= hwmsk;
cd28ab6a 2729
793b883e 2730 if (status & Y2_IS_TIST_OV)
cd28ab6a 2731 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2732
2733 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2734 u16 pci_err;
2735
a40ccc68 2736 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2737 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2738 if (net_ratelimit())
555382cb 2739 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2740 pci_err);
cd28ab6a 2741
b32f40c4 2742 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2743 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2744 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2745 }
2746
2747 if (status & Y2_IS_PCI_EXP) {
d571b694 2748 /* PCI-Express uncorrectable Error occurred */
555382cb 2749 u32 err;
cd28ab6a 2750
a40ccc68 2751 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2752 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2753 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2754 0xfffffffful);
3be92a70 2755 if (net_ratelimit())
555382cb 2756 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2757
7782c8c4 2758 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2759 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2760 }
2761
2762 if (status & Y2_HWE_L1_MASK)
2763 sky2_hw_error(hw, 0, status);
2764 status >>= 8;
2765 if (status & Y2_HWE_L1_MASK)
2766 sky2_hw_error(hw, 1, status);
2767}
2768
2769static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2770{
2771 struct net_device *dev = hw->dev[port];
2772 struct sky2_port *sky2 = netdev_priv(dev);
2773 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2774
6c35abae 2775 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2776
a3caeada
SH		 2777 if (status & GM_IS_RX_CO_OV)
2778 gma_read16(hw, port, GM_RX_IRQ_SRC);
2779
2780 if (status & GM_IS_TX_CO_OV)
2781 gma_read16(hw, port, GM_TX_IRQ_SRC);
2782
cd28ab6a 2783 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2784 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2785 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2786 }
2787
2788 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2789 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2790 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2791 }
cd28ab6a
SH		 2792}
2793
40b01727 2794/* This should never happen it is a bug. */
c119731d 2795static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2796{
2797 struct net_device *dev = hw->dev[port];
c119731d 2798 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2799
ada1db5c 2800 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2801 dev->name, (unsigned) q, (unsigned) idx,
2802 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2803
40b01727 2804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2805}
cd28ab6a 2806
75e80683
SH		 2807static int sky2_rx_hung(struct net_device *dev)
2808{
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810 struct sky2_hw *hw = sky2->hw;
2811 unsigned port = sky2->port;
2812 unsigned rxq = rxqaddr[port];
2813 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2814 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2815 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2816 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2817
2818 /* If idle and MAC or PCI is stuck */
2819 if (sky2->check.last == dev->last_rx &&
2820 ((mac_rp == sky2->check.mac_rp &&
2821 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2822 /* Check if the PCI RX hang */
2823 (fifo_rp == sky2->check.fifo_rp &&
2824 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2825 netdev_printk(KERN_DEBUG, dev,
2826 "hung mac %d:%d fifo %d (%d:%d)\n",
2827 mac_lev, mac_rp, fifo_lev,
2828 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2829 return 1;
2830 } else {
2831 sky2->check.last = dev->last_rx;
2832 sky2->check.mac_rp = mac_rp;
2833 sky2->check.mac_lev = mac_lev;
2834 sky2->check.fifo_rp = fifo_rp;
2835 sky2->check.fifo_lev = fifo_lev;
2836 return 0;
2837 }
2838}
2839
32c2c300 2840static void sky2_watchdog(unsigned long arg)
d27ed387 2841{
01bd7564 2842 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2843
75e80683 2844 /* Check for lost IRQ once a second */
32c2c300 2845 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2846 napi_schedule(&hw->napi);
75e80683
SH		 2847 } else {
2848 int i, active = 0;
2849
2850 for (i = 0; i < hw->ports; i++) {
bea3348e 2851 struct net_device *dev = hw->dev[i];
75e80683
SH		 2852 if (!netif_running(dev))
2853 continue;
2854 ++active;
2855
2856 /* For chips with Rx FIFO, check if stuck */
39dbd958 2857 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 2858 sky2_rx_hung(dev)) {
ada1db5c 2859 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 2860 schedule_work(&hw->restart_work);
2861 return;
2862 }
2863 }
2864
2865 if (active == 0)
2866 return;
32c2c300 2867 }
01bd7564 2868
75e80683 2869 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 2870}
2871
40b01727
SH		 2872/* Hardware/software error handling */
2873static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 2874{
40b01727
SH		 2875 if (net_ratelimit())
2876 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 2877
1e5f1283
SH		 2878 if (status & Y2_IS_HW_ERR)
2879 sky2_hw_intr(hw);
d257924e 2880
1e5f1283
SH		 2881 if (status & Y2_IS_IRQ_MAC1)
2882 sky2_mac_intr(hw, 0);
cd28ab6a 2883
1e5f1283
SH		 2884 if (status & Y2_IS_IRQ_MAC2)
2885 sky2_mac_intr(hw, 1);
cd28ab6a 2886
1e5f1283 2887 if (status & Y2_IS_CHK_RX1)
c119731d 2888 sky2_le_error(hw, 0, Q_R1);
d257924e 2889
1e5f1283 2890 if (status & Y2_IS_CHK_RX2)
c119731d 2891 sky2_le_error(hw, 1, Q_R2);
d257924e 2892
1e5f1283 2893 if (status & Y2_IS_CHK_TXA1)
c119731d 2894 sky2_le_error(hw, 0, Q_XA1);
d257924e 2895
1e5f1283 2896 if (status & Y2_IS_CHK_TXA2)
c119731d 2897 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 2898}
2899
bea3348e 2900static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 2901{
bea3348e 2902 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 2903 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 2904 int work_done = 0;
26691830 2905 u16 idx;
40b01727
SH		 2906
2907 if (unlikely(status & Y2_IS_ERROR))
2908 sky2_err_intr(hw, status);
2909
2910 if (status & Y2_IS_IRQ_PHY1)
2911 sky2_phy_intr(hw, 0);
2912
2913 if (status & Y2_IS_IRQ_PHY2)
2914 sky2_phy_intr(hw, 1);
cd28ab6a 2915
0f5aac70
SH		 2916 if (status & Y2_IS_PHY_QLNK)
2917 sky2_qlink_intr(hw);
2918
26691830
SH		 2919 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2920 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 2921
2922 if (work_done >= work_limit)
26691830
SH		 2923 goto done;
2924 }
6f535763 2925
26691830
SH		 2926 napi_complete(napi);
2927 sky2_read32(hw, B0_Y2_SP_LISR);
2928done:
6f535763 2929
bea3348e 2930 return work_done;
e07b1aa8
SH		 2931}
2932
7d12e780 2933static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2934{
2935 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 2936 u32 status;
2937
2938 /* Reading this mask interrupts as side effect */
2939 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2940 if (status == 0 || status == ~0)
2941 return IRQ_NONE;
793b883e 2942
e07b1aa8 2943 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 2944
2945 napi_schedule(&hw->napi);
793b883e 2946
cd28ab6a
SH		 2947 return IRQ_HANDLED;
2948}
2949
2950#ifdef CONFIG_NET_POLL_CONTROLLER
2951static void sky2_netpoll(struct net_device *dev)
2952{
2953 struct sky2_port *sky2 = netdev_priv(dev);
2954
bea3348e 2955 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 2956}
2957#endif
2958
2959/* Chip internal frequency for clock calculations */
05745c4a 2960static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2961{
793b883e 2962 switch (hw->chip_id) {
cd28ab6a 2963 case CHIP_ID_YUKON_EC:
5a5b1ea0 2964 case CHIP_ID_YUKON_EC_U:
93745494 2965 case CHIP_ID_YUKON_EX:
ed4d4161 2966 case CHIP_ID_YUKON_SUPR:
0ce8b98d 2967 case CHIP_ID_YUKON_UL_2:
0f5aac70 2968 case CHIP_ID_YUKON_OPT:
05745c4a
SH		 2969 return 125;
2970
cd28ab6a 2971 case CHIP_ID_YUKON_FE:
05745c4a
SH		 2972 return 100;
2973
2974 case CHIP_ID_YUKON_FE_P:
2975 return 50;
2976
2977 case CHIP_ID_YUKON_XL:
2978 return 156;
2979
2980 default:
2981 BUG();
cd28ab6a
SH		 2982 }
2983}
2984
fb17358f 2985static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2986{
fb17358f 2987 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2988}
2989
fb17358f 2990static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2991{
fb17358f 2992 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2993}
2994
fb17358f 2995
e3173832 2996static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2997{
b89165f2 2998 u8 t8;
cd28ab6a 2999
167f53d0 3000 /* Enable all clocks and check for bad PCI access */
b32f40c4 3001 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3002
cd28ab6a 3003 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3004
cd28ab6a 3005 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3006 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3007
3008 switch(hw->chip_id) {
3009 case CHIP_ID_YUKON_XL:
39dbd958 3010 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3011 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3012 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3013 break;
3014
3015 case CHIP_ID_YUKON_EC_U:
3016 hw->flags = SKY2_HW_GIGABIT
3017 | SKY2_HW_NEWER_PHY
3018 | SKY2_HW_ADV_POWER_CTL;
3019 break;
3020
3021 case CHIP_ID_YUKON_EX:
3022 hw->flags = SKY2_HW_GIGABIT
3023 | SKY2_HW_NEWER_PHY
3024 | SKY2_HW_NEW_LE
3025 | SKY2_HW_ADV_POWER_CTL;
3026
3027 /* New transmit checksum */
3028 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3029 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3030 break;
3031
3032 case CHIP_ID_YUKON_EC:
3033 /* This rev is really old, and requires untested workarounds */
3034 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3035 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3036 return -EOPNOTSUPP;
3037 }
bf73130d 3038 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3039 break;
3040
3041 case CHIP_ID_YUKON_FE:
bf73130d 3042 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3043 break;
3044
05745c4a
SH		 3045 case CHIP_ID_YUKON_FE_P:
3046 hw->flags = SKY2_HW_NEWER_PHY
3047 | SKY2_HW_NEW_LE
3048 | SKY2_HW_AUTO_TX_SUM
3049 | SKY2_HW_ADV_POWER_CTL;
3050 break;
ed4d4161
SH		 3051
3052 case CHIP_ID_YUKON_SUPR:
3053 hw->flags = SKY2_HW_GIGABIT
3054 | SKY2_HW_NEWER_PHY
3055 | SKY2_HW_NEW_LE
3056 | SKY2_HW_AUTO_TX_SUM
3057 | SKY2_HW_ADV_POWER_CTL;
3058 break;
3059
0ce8b98d 3060 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3061 hw->flags = SKY2_HW_GIGABIT
3062 | SKY2_HW_ADV_POWER_CTL;
3063 break;
3064
0f5aac70 3065 case CHIP_ID_YUKON_OPT:
0ce8b98d 3066 hw->flags = SKY2_HW_GIGABIT
b338682d 3067 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3068 | SKY2_HW_ADV_POWER_CTL;
3069 break;
3070
ea76e635 3071 default:
b02a9258
SH		 3072 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3073 hw->chip_id);
cd28ab6a
SH		 3074 return -EOPNOTSUPP;
3075 }
3076
ea76e635
SH		 3077 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3078 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3079 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3080
e3173832
SH		 3081 hw->ports = 1;
3082 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3083 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3084 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3085 ++hw->ports;
3086 }
3087
74a61ebf
MM		 3088 if (sky2_read8(hw, B2_E_0))
3089 hw->flags |= SKY2_HW_RAM_BUFFER;
3090
e3173832
SH		 3091 return 0;
3092}
3093
3094static void sky2_reset(struct sky2_hw *hw)
3095{
555382cb 3096 struct pci_dev *pdev = hw->pdev;
e3173832 3097 u16 status;
555382cb
SH		 3098 int i, cap;
3099 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3100
cd28ab6a 3101 /* disable ASF */
acd12dde 3102 if (hw->chip_id == CHIP_ID_YUKON_EX
3103 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3104 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3105 status = sky2_read16(hw, HCU_CCSR);
3106 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3107 HCU_CCSR_UC_STATE_MSK);
acd12dde 3108 /*
3109 * CPU clock divider shouldn't be used because
3110 * - ASF firmware may malfunction
3111 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3112 */
3113 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3114 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3115 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3116 } else
3117 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3118 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3119
3120 /* do a SW reset */
3121 sky2_write8(hw, B0_CTST, CS_RST_SET);
3122 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3123
ac93a394
SH		 3124 /* allow writes to PCI config */
3125 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3126
cd28ab6a 3127 /* clear PCI errors, if any */
b32f40c4 3128 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3129 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3130 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3131
3132 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3133
555382cb
SH		 3134 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3135 if (cap) {
7782c8c4
SH		 3136 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3137 0xfffffffful);
555382cb
SH		 3138
3139 /* If error bit is stuck on ignore it */
3140 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3141 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3142 else
555382cb
SH		 3143 hwe_mask |= Y2_IS_PCI_EXP;
3144 }
cd28ab6a 3145
ae306cca 3146 sky2_power_on(hw);
a40ccc68 3147 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3148
3149 for (i = 0; i < hw->ports; i++) {
3150 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3151 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3152
ed4d4161
SH		 3153 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3154 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3155 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3156 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3157 | GMC_BYP_RETR_ON);
877c8570
SH		 3158
3159 }
3160
3161 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3162 /* enable MACSec clock gating */
3163 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3164 }
3165
0f5aac70
SH		 3166 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3167 u16 reg;
3168 u32 msk;
3169
3170 if (hw->chip_rev == 0) {
3171 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3172 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3173
3174 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3175 reg = 10;
3176 } else {
3177 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3178 reg = 3;
3179 }
3180
3181 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3182
3183 /* reset PHY Link Detect */
a40ccc68 3184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3185 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3186 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3187 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3188
3189
3190 /* enable PHY Quick Link */
3191 msk = sky2_read32(hw, B0_IMSK);
3192 msk |= Y2_IS_PHY_QLNK;
3193 sky2_write32(hw, B0_IMSK, msk);
3194
3195 /* check if PSMv2 was running before */
3196 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3197 if (reg & PCI_EXP_LNKCTL_ASPMC) {
8b055431 3198 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
0f5aac70
SH		 3199 /* restore the PCIe Link Control register */
3200 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3201 }
a40ccc68 3202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3203
3204 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3205 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3206 }
3207
793b883e
SH		 3208 /* Clear I2C IRQ noise */
3209 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3210
3211 /* turn off hardware timer (unused) */
3212 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3213 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3214
69634ee7
SH		 3215 /* Turn off descriptor polling */
3216 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3217
3218 /* Turn off receive timestamp */
3219 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3220 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3221
3222 /* enable the Tx Arbiters */
3223 for (i = 0; i < hw->ports; i++)
3224 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3225
3226 /* Initialize ram interface */
3227 for (i = 0; i < hw->ports; i++) {
793b883e 3228 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3229
3230 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3231 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3233 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3238 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3242 }
3243
555382cb 3244 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3245
cd28ab6a 3246 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3247 sky2_gmac_reset(hw, i);
cd28ab6a 3248
efe91932 3249 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3250 hw->st_idx = 0;
3251
3252 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3253 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3254
3255 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3256 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3257
3258 /* Set the list last index */
efe91932 3259 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3260
290d4de5
SH		 3261 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3262 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3263
290d4de5
SH		 3264 /* set Status-FIFO ISR watermark */
3265 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3266 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3267 else
3268 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3269
290d4de5 3270 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3271 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3272 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3273
793b883e 3274 /* enable status unit */
cd28ab6a
SH		 3275 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3276
3277 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3278 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3279 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3280}
3281
af18d8b8
SH		 3282/* Take device down (offline).
3283 * Equivalent to doing dev_stop() but this does not
3284 * inform upper layers of the transistion.
3285 */
3286static void sky2_detach(struct net_device *dev)
3287{
3288 if (netif_running(dev)) {
c36531b9 3289 netif_tx_lock(dev);
af18d8b8 3290 netif_device_detach(dev); /* stop txq */
c36531b9 3291 netif_tx_unlock(dev);
af18d8b8
SH		 3292 sky2_down(dev);
3293 }
3294}
3295
3296/* Bring device back after doing sky2_detach */
3297static int sky2_reattach(struct net_device *dev)
3298{
3299 int err = 0;
3300
3301 if (netif_running(dev)) {
3302 err = sky2_up(dev);
3303 if (err) {
ada1db5c 3304 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3305 dev_close(dev);
3306 } else {
3307 netif_device_attach(dev);
3308 sky2_set_multicast(dev);
3309 }
3310 }
3311
3312 return err;
3313}
3314
81906791
SH		 3315static void sky2_restart(struct work_struct *work)
3316{
3317 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
8a0c9228 3318 u32 imask;
af18d8b8 3319 int i;
81906791 3320
81906791 3321 rtnl_lock();
81906791 3322
8cfcbe99 3323 napi_disable(&hw->napi);
8a0c9228
MM		 3324 synchronize_irq(hw->pdev->irq);
3325 imask = sky2_read32(hw, B0_IMSK);
8cfcbe99 3326 sky2_write32(hw, B0_IMSK, 0);
8a0c9228
MM		 3327
3328 for (i = 0; i < hw->ports; i++) {
3329 struct net_device *dev = hw->dev[i];
3330 struct sky2_port *sky2 = netdev_priv(dev);
3331
3332 if (!netif_running(dev))
3333 continue;
3334
3335 netif_carrier_off(dev);
3336 netif_tx_disable(dev);
3337 sky2_hw_down(sky2);
3338 }
3339
81906791 3340 sky2_reset(hw);
81906791 3341
8a0c9228
MM		 3342 for (i = 0; i < hw->ports; i++) {
3343 struct net_device *dev = hw->dev[i];
3344 struct sky2_port *sky2 = netdev_priv(dev);
3345
3346 if (!netif_running(dev))
3347 continue;
3348
3349 sky2_hw_up(sky2);
3350 netif_wake_queue(dev);
3351 }
3352
3353 sky2_write32(hw, B0_IMSK, imask);
3354 sky2_read32(hw, B0_IMSK);
3355
3356 sky2_read32(hw, B0_Y2_SP_LISR);
3357 napi_enable(&hw->napi);
81906791 3358
81906791
SH		 3359 rtnl_unlock();
3360}
3361
e3173832
SH		 3362static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3363{
3364 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3365}
3366
3367static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3368{
3369 const struct sky2_port *sky2 = netdev_priv(dev);
3370
3371 wol->supported = sky2_wol_supported(sky2->hw);
3372 wol->wolopts = sky2->wol;
3373}
3374
3375static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3376{
3377 struct sky2_port *sky2 = netdev_priv(dev);
3378 struct sky2_hw *hw = sky2->hw;
cd28ab6a 3379
8e95a202
JP		 3380 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3381 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3382 return -EOPNOTSUPP;
3383
3384 sky2->wol = wol->wolopts;
cd28ab6a
SH		 3385 return 0;
3386}
3387
28bd181a 3388static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3389{
b89165f2
SH		 3390 if (sky2_is_copper(hw)) {
3391 u32 modes = SUPPORTED_10baseT_Half
3392 | SUPPORTED_10baseT_Full
3393 | SUPPORTED_100baseT_Half
3394 | SUPPORTED_100baseT_Full
3395 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 3396
ea76e635 3397 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3398 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3399 | SUPPORTED_1000baseT_Full;
3400 return modes;
cd28ab6a 3401 } else
b89165f2
SH		 3402 return SUPPORTED_1000baseT_Half
3403 | SUPPORTED_1000baseT_Full
3404 | SUPPORTED_Autoneg
3405 | SUPPORTED_FIBRE;
cd28ab6a
SH		 3406}
3407
793b883e 3408static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3409{
3410 struct sky2_port *sky2 = netdev_priv(dev);
3411 struct sky2_hw *hw = sky2->hw;
3412
3413 ecmd->transceiver = XCVR_INTERNAL;
3414 ecmd->supported = sky2_supported_modes(hw);
3415 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3416 if (sky2_is_copper(hw)) {
cd28ab6a 3417 ecmd->port = PORT_TP;
b89165f2
SH		 3418 ecmd->speed = sky2->speed;
3419 } else {
3420 ecmd->speed = SPEED_1000;
cd28ab6a 3421 ecmd->port = PORT_FIBRE;
b89165f2 3422 }
cd28ab6a
SH		 3423
3424 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3425 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3426 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3427 ecmd->duplex = sky2->duplex;
3428 return 0;
3429}
3430
3431static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3432{
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 const struct sky2_hw *hw = sky2->hw;
3435 u32 supported = sky2_supported_modes(hw);
3436
3437 if (ecmd->autoneg == AUTONEG_ENABLE) {
0ea065e5 3438 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3439 ecmd->advertising = supported;
3440 sky2->duplex = -1;
3441 sky2->speed = -1;
3442 } else {
3443 u32 setting;
3444
793b883e 3445 switch (ecmd->speed) {
cd28ab6a
SH		 3446 case SPEED_1000:
3447 if (ecmd->duplex == DUPLEX_FULL)
3448 setting = SUPPORTED_1000baseT_Full;
3449 else if (ecmd->duplex == DUPLEX_HALF)
3450 setting = SUPPORTED_1000baseT_Half;
3451 else
3452 return -EINVAL;
3453 break;
3454 case SPEED_100:
3455 if (ecmd->duplex == DUPLEX_FULL)
3456 setting = SUPPORTED_100baseT_Full;
3457 else if (ecmd->duplex == DUPLEX_HALF)
3458 setting = SUPPORTED_100baseT_Half;
3459 else
3460 return -EINVAL;
3461 break;
3462
3463 case SPEED_10:
3464 if (ecmd->duplex == DUPLEX_FULL)
3465 setting = SUPPORTED_10baseT_Full;
3466 else if (ecmd->duplex == DUPLEX_HALF)
3467 setting = SUPPORTED_10baseT_Half;
3468 else
3469 return -EINVAL;
3470 break;
3471 default:
3472 return -EINVAL;
3473 }
3474
3475 if ((setting & supported) == 0)
3476 return -EINVAL;
3477
3478 sky2->speed = ecmd->speed;
3479 sky2->duplex = ecmd->duplex;
0ea065e5 3480 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3481 }
3482
cd28ab6a
SH		 3483 sky2->advertising = ecmd->advertising;
3484
d1b139c0 3485 if (netif_running(dev)) {
1b537565 3486 sky2_phy_reinit(sky2);
d1b139c0
SH		 3487 sky2_set_multicast(dev);
3488 }
cd28ab6a
SH		 3489
3490 return 0;
3491}
3492
3493static void sky2_get_drvinfo(struct net_device *dev,
3494 struct ethtool_drvinfo *info)
3495{
3496 struct sky2_port *sky2 = netdev_priv(dev);
3497
3498 strcpy(info->driver, DRV_NAME);
3499 strcpy(info->version, DRV_VERSION);
3500 strcpy(info->fw_version, "N/A");
3501 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3502}
3503
3504static const struct sky2_stat {
793b883e
SH		 3505 char name[ETH_GSTRING_LEN];
3506 u16 offset;
cd28ab6a
SH		 3507} sky2_stats[] = {
3508 { "tx_bytes", GM_TXO_OK_HI },
3509 { "rx_bytes", GM_RXO_OK_HI },
3510 { "tx_broadcast", GM_TXF_BC_OK },
3511 { "rx_broadcast", GM_RXF_BC_OK },
3512 { "tx_multicast", GM_TXF_MC_OK },
3513 { "rx_multicast", GM_RXF_MC_OK },
3514 { "tx_unicast", GM_TXF_UC_OK },
3515 { "rx_unicast", GM_RXF_UC_OK },
3516 { "tx_mac_pause", GM_TXF_MPAUSE },
3517 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3518 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3519 { "late_collision",GM_TXF_LAT_COL },
3520 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3521 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3522 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3523
d2604540 3524 { "rx_short", GM_RXF_SHT },
cd28ab6a 3525 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3526 { "rx_64_byte_packets", GM_RXF_64B },
3527 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3528 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3529 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3530 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3531 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3532 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3533 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3534 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3535 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3536 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3537
3538 { "tx_64_byte_packets", GM_TXF_64B },
3539 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3540 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3541 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3542 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3543 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3544 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3545 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3546};
3547
cd28ab6a
SH		 3548static u32 sky2_get_rx_csum(struct net_device *dev)
3549{
3550 struct sky2_port *sky2 = netdev_priv(dev);
3551
0ea065e5 3552 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
cd28ab6a
SH		 3553}
3554
3555static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3556{
3557 struct sky2_port *sky2 = netdev_priv(dev);
3558
0ea065e5
SH		 3559 if (data)
3560 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3561 else
3562 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
793b883e 3563
cd28ab6a
SH		 3564 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3565 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3566
3567 return 0;
3568}
3569
3570static u32 sky2_get_msglevel(struct net_device *netdev)
3571{
3572 struct sky2_port *sky2 = netdev_priv(netdev);
3573 return sky2->msg_enable;
3574}
3575
9a7ae0a9
SH		 3576static int sky2_nway_reset(struct net_device *dev)
3577{
3578 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3579
0ea065e5 3580 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3581 return -EINVAL;
3582
1b537565 3583 sky2_phy_reinit(sky2);
d1b139c0 3584 sky2_set_multicast(dev);
9a7ae0a9
SH		 3585
3586 return 0;
3587}
3588
793b883e 3589static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3590{
3591 struct sky2_hw *hw = sky2->hw;
3592 unsigned port = sky2->port;
3593 int i;
3594
3595 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 3596 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 3597 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 3598 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 3599
793b883e 3600 for (i = 2; i < count; i++)
cd28ab6a
SH		 3601 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3602}
3603
cd28ab6a
SH		 3604static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3605{
3606 struct sky2_port *sky2 = netdev_priv(netdev);
3607 sky2->msg_enable = value;
3608}
3609
b9f2c044 3610static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3611{
b9f2c044
JG		 3612 switch (sset) {
3613 case ETH_SS_STATS:
3614 return ARRAY_SIZE(sky2_stats);
3615 default:
3616 return -EOPNOTSUPP;
3617 }
cd28ab6a
SH		 3618}
3619
3620static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3621 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3622{
3623 struct sky2_port *sky2 = netdev_priv(dev);
3624
793b883e 3625 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3626}
3627
793b883e 3628static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3629{
3630 int i;
3631
3632 switch (stringset) {
3633 case ETH_SS_STATS:
3634 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3635 memcpy(data + i * ETH_GSTRING_LEN,
3636 sky2_stats[i].name, ETH_GSTRING_LEN);
3637 break;
3638 }
3639}
3640
cd28ab6a
SH		 3641static int sky2_set_mac_address(struct net_device *dev, void *p)
3642{
3643 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3644 struct sky2_hw *hw = sky2->hw;
3645 unsigned port = sky2->port;
3646 const struct sockaddr *addr = p;
cd28ab6a
SH		 3647
3648 if (!is_valid_ether_addr(addr->sa_data))
3649 return -EADDRNOTAVAIL;
3650
cd28ab6a 3651 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3652 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3653 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3654 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3655 dev->dev_addr, ETH_ALEN);
1b537565 3656
a8ab1ec0
SH		 3657 /* virtual address for data */
3658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3659
3660 /* physical address: used for pause frames */
3661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3662
3663 return 0;
cd28ab6a
SH		 3664}
3665
a052b52f
SH		 3666static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3667{
3668 u32 bit;
3669
3670 bit = ether_crc(ETH_ALEN, addr) & 63;
3671 filter[bit >> 3] |= 1 << (bit & 7);
3672}
3673
cd28ab6a
SH		 3674static void sky2_set_multicast(struct net_device *dev)
3675{
3676 struct sky2_port *sky2 = netdev_priv(dev);
3677 struct sky2_hw *hw = sky2->hw;
3678 unsigned port = sky2->port;
22bedad3 3679 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3680 u16 reg;
3681 u8 filter[8];
a052b52f
SH		 3682 int rx_pause;
3683 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3684
a052b52f 3685 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3686 memset(filter, 0, sizeof(filter));
3687
3688 reg = gma_read16(hw, port, GM_RX_CTRL);
3689 reg |= GM_RXCR_UCF_ENA;
3690
d571b694 3691 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3692 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3693 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3694 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3695 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3696 reg &= ~GM_RXCR_MCF_ENA;
3697 else {
cd28ab6a
SH		 3698 reg |= GM_RXCR_MCF_ENA;
3699
a052b52f
SH		 3700 if (rx_pause)
3701 sky2_add_filter(filter, pause_mc_addr);
3702
22bedad3
JP		 3703 netdev_for_each_mc_addr(ha, dev)
3704 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3705 }
3706
cd28ab6a 3707 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3708 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3709 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3710 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3711 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3712 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3713 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3714 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3715
3716 gma_write16(hw, port, GM_RX_CTRL, reg);
3717}
3718
3719/* Can have one global because blinking is controlled by
3720 * ethtool and that is always under RTNL mutex
3721 */
a84d0a3d 3722static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3723{
a84d0a3d
SH		 3724 struct sky2_hw *hw = sky2->hw;
3725 unsigned port = sky2->port;
793b883e 3726
a84d0a3d
SH		 3727 spin_lock_bh(&sky2->phy_lock);
3728 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3729 hw->chip_id == CHIP_ID_YUKON_EX ||
3730 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3731 u16 pg;
793b883e
SH		 3732 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3734
a84d0a3d
SH		 3735 switch (mode) {
3736 case MO_LED_OFF:
3737 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3738 PHY_M_LEDC_LOS_CTRL(8) |
3739 PHY_M_LEDC_INIT_CTRL(8) |
3740 PHY_M_LEDC_STA1_CTRL(8) |
3741 PHY_M_LEDC_STA0_CTRL(8));
3742 break;
3743 case MO_LED_ON:
3744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3745 PHY_M_LEDC_LOS_CTRL(9) |
3746 PHY_M_LEDC_INIT_CTRL(9) |
3747 PHY_M_LEDC_STA1_CTRL(9) |
3748 PHY_M_LEDC_STA0_CTRL(9));
3749 break;
3750 case MO_LED_BLINK:
3751 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3752 PHY_M_LEDC_LOS_CTRL(0xa) |
3753 PHY_M_LEDC_INIT_CTRL(0xa) |
3754 PHY_M_LEDC_STA1_CTRL(0xa) |
3755 PHY_M_LEDC_STA0_CTRL(0xa));
3756 break;
3757 case MO_LED_NORM:
3758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3759 PHY_M_LEDC_LOS_CTRL(1) |
3760 PHY_M_LEDC_INIT_CTRL(8) |
3761 PHY_M_LEDC_STA1_CTRL(7) |
3762 PHY_M_LEDC_STA0_CTRL(7));
3763 }
793b883e 3764
a84d0a3d
SH		 3765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3766 } else
7d2e3cb7 3767 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3768 PHY_M_LED_MO_DUP(mode) |
3769 PHY_M_LED_MO_10(mode) |
3770 PHY_M_LED_MO_100(mode) |
3771 PHY_M_LED_MO_1000(mode) |
3772 PHY_M_LED_MO_RX(mode) |
3773 PHY_M_LED_MO_TX(mode));
3774
3775 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3776}
3777
3778/* blink LED's for finding board */
3779static int sky2_phys_id(struct net_device *dev, u32 data)
3780{
3781 struct sky2_port *sky2 = netdev_priv(dev);
a84d0a3d 3782 unsigned int i;
cd28ab6a 3783
a84d0a3d
SH		 3784 if (data == 0)
3785 data = UINT_MAX;
cd28ab6a 3786
a84d0a3d
SH		 3787 for (i = 0; i < data; i++) {
3788 sky2_led(sky2, MO_LED_ON);
3789 if (msleep_interruptible(500))
3790 break;
3791 sky2_led(sky2, MO_LED_OFF);
3792 if (msleep_interruptible(500))
3793 break;
793b883e 3794 }
a84d0a3d 3795 sky2_led(sky2, MO_LED_NORM);
cd28ab6a
SH		 3796
3797 return 0;
3798}
3799
3800static void sky2_get_pauseparam(struct net_device *dev,
3801 struct ethtool_pauseparam *ecmd)
3802{
3803 struct sky2_port *sky2 = netdev_priv(dev);
3804
16ad91e1
SH		 3805 switch (sky2->flow_mode) {
3806 case FC_NONE:
3807 ecmd->tx_pause = ecmd->rx_pause = 0;
3808 break;
3809 case FC_TX:
3810 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3811 break;
3812 case FC_RX:
3813 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3814 break;
3815 case FC_BOTH:
3816 ecmd->tx_pause = ecmd->rx_pause = 1;
3817 }
3818
0ea065e5
SH		 3819 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3820 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3821}
3822
3823static int sky2_set_pauseparam(struct net_device *dev,
3824 struct ethtool_pauseparam *ecmd)
3825{
3826 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3827
0ea065e5
SH		 3828 if (ecmd->autoneg == AUTONEG_ENABLE)
3829 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3830 else
3831 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3832
16ad91e1 3833 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3834
16ad91e1
SH		 3835 if (netif_running(dev))
3836 sky2_phy_reinit(sky2);
cd28ab6a 3837
2eaba1a2 3838 return 0;
cd28ab6a
SH		 3839}
3840
fb17358f
SH		 3841static int sky2_get_coalesce(struct net_device *dev,
3842 struct ethtool_coalesce *ecmd)
3843{
3844 struct sky2_port *sky2 = netdev_priv(dev);
3845 struct sky2_hw *hw = sky2->hw;
3846
3847 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3848 ecmd->tx_coalesce_usecs = 0;
3849 else {
3850 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3851 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3852 }
3853 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3854
3855 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3856 ecmd->rx_coalesce_usecs = 0;
3857 else {
3858 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3859 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3860 }
3861 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3862
3863 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3864 ecmd->rx_coalesce_usecs_irq = 0;
3865 else {
3866 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3867 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3868 }
3869
3870 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3871
3872 return 0;
3873}
3874
3875/* Note: this affect both ports */
3876static int sky2_set_coalesce(struct net_device *dev,
3877 struct ethtool_coalesce *ecmd)
3878{
3879 struct sky2_port *sky2 = netdev_priv(dev);
3880 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3881 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3882
77b3d6a2
SH		 3883 if (ecmd->tx_coalesce_usecs > tmax ||
3884 ecmd->rx_coalesce_usecs > tmax ||
3885 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3886 return -EINVAL;
3887
ee5f68fe 3888 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 3889 return -EINVAL;
ff81fbbe 3890 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3891 return -EINVAL;
ff81fbbe 3892 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3893 return -EINVAL;
3894
3895 if (ecmd->tx_coalesce_usecs == 0)
3896 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3897 else {
3898 sky2_write32(hw, STAT_TX_TIMER_INI,
3899 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3900 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3901 }
3902 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3903
3904 if (ecmd->rx_coalesce_usecs == 0)
3905 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3906 else {
3907 sky2_write32(hw, STAT_LEV_TIMER_INI,
3908 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3909 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3910 }
3911 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3912
3913 if (ecmd->rx_coalesce_usecs_irq == 0)
3914 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3915 else {
d28d4870 3916 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3917 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3918 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3919 }
3920 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3921 return 0;
3922}
3923
793b883e
SH		 3924static void sky2_get_ringparam(struct net_device *dev,
3925 struct ethtool_ringparam *ering)
3926{
3927 struct sky2_port *sky2 = netdev_priv(dev);
3928
3929 ering->rx_max_pending = RX_MAX_PENDING;
3930 ering->rx_mini_max_pending = 0;
3931 ering->rx_jumbo_max_pending = 0;
ee5f68fe 3932 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 3933
3934 ering->rx_pending = sky2->rx_pending;
3935 ering->rx_mini_pending = 0;
3936 ering->rx_jumbo_pending = 0;
3937 ering->tx_pending = sky2->tx_pending;
3938}
3939
3940static int sky2_set_ringparam(struct net_device *dev,
3941 struct ethtool_ringparam *ering)
3942{
3943 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 3944
3945 if (ering->rx_pending > RX_MAX_PENDING ||
3946 ering->rx_pending < 8 ||
ee5f68fe
SH		 3947 ering->tx_pending < TX_MIN_PENDING ||
3948 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 3949 return -EINVAL;
3950
af18d8b8 3951 sky2_detach(dev);
793b883e
SH		 3952
3953 sky2->rx_pending = ering->rx_pending;
3954 sky2->tx_pending = ering->tx_pending;
ee5f68fe 3955 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
793b883e 3956
af18d8b8 3957 return sky2_reattach(dev);
793b883e
SH		 3958}
3959
793b883e
SH		 3960static int sky2_get_regs_len(struct net_device *dev)
3961{
6e4cbb34 3962 return 0x4000;
793b883e
SH		 3963}
3964
c32bbff8
MM		 3965static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3966{
3967 /* This complicated switch statement is to make sure and
3968 * only access regions that are unreserved.
3969 * Some blocks are only valid on dual port cards.
3970 */
3971 switch (b) {
3972 /* second port */
3973 case 5: /* Tx Arbiter 2 */
3974 case 9: /* RX2 */
3975 case 14 ... 15: /* TX2 */
3976 case 17: case 19: /* Ram Buffer 2 */
3977 case 22 ... 23: /* Tx Ram Buffer 2 */
3978 case 25: /* Rx MAC Fifo 1 */
3979 case 27: /* Tx MAC Fifo 2 */
3980 case 31: /* GPHY 2 */
3981 case 40 ... 47: /* Pattern Ram 2 */
3982 case 52: case 54: /* TCP Segmentation 2 */
3983 case 112 ... 116: /* GMAC 2 */
3984 return hw->ports > 1;
3985
3986 case 0: /* Control */
3987 case 2: /* Mac address */
3988 case 4: /* Tx Arbiter 1 */
3989 case 7: /* PCI express reg */
3990 case 8: /* RX1 */
3991 case 12 ... 13: /* TX1 */
3992 case 16: case 18:/* Rx Ram Buffer 1 */
3993 case 20 ... 21: /* Tx Ram Buffer 1 */
3994 case 24: /* Rx MAC Fifo 1 */
3995 case 26: /* Tx MAC Fifo 1 */
3996 case 28 ... 29: /* Descriptor and status unit */
3997 case 30: /* GPHY 1*/
3998 case 32 ... 39: /* Pattern Ram 1 */
3999 case 48: case 50: /* TCP Segmentation 1 */
4000 case 56 ... 60: /* PCI space */
4001 case 80 ... 84: /* GMAC 1 */
4002 return 1;
4003
4004 default:
4005 return 0;
4006 }
4007}
4008
793b883e
SH		 4009/*
4010 * Returns copy of control register region
3ead5db7 4011 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4012 */
4013static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4014 void *p)
4015{
4016 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4017 const void __iomem *io = sky2->hw->regs;
295b54c4 4018 unsigned int b;
793b883e
SH		 4019
4020 regs->version = 1;
793b883e 4021
295b54c4 4022 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4023 /* skip poisonous diagnostic ram region in block 3 */
4024 if (b == 3)
295b54c4 4025 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4026 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4027 memcpy_fromio(p, io, 128);
c32bbff8 4028 else
295b54c4 4029 memset(p, 0, 128);
3ead5db7 4030
295b54c4
SH		 4031 p += 128;
4032 io += 128;
4033 }
793b883e 4034}
cd28ab6a 4035
b628ed98
SH		 4036/* In order to do Jumbo packets on these chips, need to turn off the
4037 * transmit store/forward. Therefore checksum offload won't work.
4038 */
4039static int no_tx_offload(struct net_device *dev)
4040{
4041 const struct sky2_port *sky2 = netdev_priv(dev);
4042 const struct sky2_hw *hw = sky2->hw;
4043
69161611 4044 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
b628ed98
SH		 4045}
4046
4047static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4048{
4049 if (data && no_tx_offload(dev))
4050 return -EINVAL;
4051
4052 return ethtool_op_set_tx_csum(dev, data);
4053}
4054
4055
4056static int sky2_set_tso(struct net_device *dev, u32 data)
4057{
4058 if (data && no_tx_offload(dev))
4059 return -EINVAL;
4060
4061 return ethtool_op_set_tso(dev, data);
4062}
4063
f4331a6d
SH		 4064static int sky2_get_eeprom_len(struct net_device *dev)
4065{
4066 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4067 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4068 u16 reg2;
4069
b32f40c4 4070 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4071 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4072}
4073
1413235c 4074static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4075{
1413235c 4076 unsigned long start = jiffies;
f4331a6d 4077
1413235c
SH		 4078 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4079 /* Can take up to 10.6 ms for write */
4080 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4081 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4082 return -ETIMEDOUT;
4083 }
4084 mdelay(1);
4085 }
167f53d0 4086
1413235c
SH		 4087 return 0;
4088}
167f53d0 4089
1413235c
SH		 4090static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4091 u16 offset, size_t length)
4092{
4093 int rc = 0;
4094
4095 while (length > 0) {
4096 u32 val;
4097
4098 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4099 rc = sky2_vpd_wait(hw, cap, 0);
4100 if (rc)
4101 break;
4102
4103 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4104
4105 memcpy(data, &val, min(sizeof(val), length));
4106 offset += sizeof(u32);
4107 data += sizeof(u32);
4108 length -= sizeof(u32);
4109 }
4110
4111 return rc;
f4331a6d
SH		 4112}
4113
1413235c
SH		 4114static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4115 u16 offset, unsigned int length)
f4331a6d 4116{
1413235c
SH		 4117 unsigned int i;
4118 int rc = 0;
4119
4120 for (i = 0; i < length; i += sizeof(u32)) {
4121 u32 val = *(u32 *)(data + i);
4122
4123 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4124 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4125
4126 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4127 if (rc)
4128 break;
4129 }
4130 return rc;
f4331a6d
SH		 4131}
4132
4133static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4134 u8 *data)
4135{
4136 struct sky2_port *sky2 = netdev_priv(dev);
4137 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4138
4139 if (!cap)
4140 return -EINVAL;
4141
4142 eeprom->magic = SKY2_EEPROM_MAGIC;
4143
1413235c 4144 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4145}
4146
4147static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4148 u8 *data)
4149{
4150 struct sky2_port *sky2 = netdev_priv(dev);
4151 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4152
4153 if (!cap)
4154 return -EINVAL;
4155
4156 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4157 return -EINVAL;
4158
1413235c
SH		 4159 /* Partial writes not supported */
4160 if ((eeprom->offset & 3) || (eeprom->len & 3))
4161 return -EINVAL;
f4331a6d 4162
1413235c 4163 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4164}
4165
bf73130d
SH		 4166static int sky2_set_flags(struct net_device *dev, u32 data)
4167{
4168 struct sky2_port *sky2 = netdev_priv(dev);
4169
4170 if (data & ~ETH_FLAG_RXHASH)
4171 return -EOPNOTSUPP;
4172
4173 if (data & ETH_FLAG_RXHASH) {
4174 if (sky2->hw->flags & SKY2_HW_RSS_BROKEN)
4175 return -EINVAL;
4176
4177 dev->features |= NETIF_F_RXHASH;
4178 } else
4179 dev->features &= ~NETIF_F_RXHASH;
4180
4181 rx_set_rss(dev);
4182
4183 return 0;
4184}
f4331a6d 4185
7282d491 4186static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4187 .get_settings = sky2_get_settings,
4188 .set_settings = sky2_set_settings,
4189 .get_drvinfo = sky2_get_drvinfo,
4190 .get_wol = sky2_get_wol,
4191 .set_wol = sky2_set_wol,
4192 .get_msglevel = sky2_get_msglevel,
4193 .set_msglevel = sky2_set_msglevel,
4194 .nway_reset = sky2_nway_reset,
4195 .get_regs_len = sky2_get_regs_len,
4196 .get_regs = sky2_get_regs,
4197 .get_link = ethtool_op_get_link,
4198 .get_eeprom_len = sky2_get_eeprom_len,
4199 .get_eeprom = sky2_get_eeprom,
4200 .set_eeprom = sky2_set_eeprom,
f4331a6d 4201 .set_sg = ethtool_op_set_sg,
f4331a6d 4202 .set_tx_csum = sky2_set_tx_csum,
f4331a6d
SH		 4203 .set_tso = sky2_set_tso,
4204 .get_rx_csum = sky2_get_rx_csum,
4205 .set_rx_csum = sky2_set_rx_csum,
4206 .get_strings = sky2_get_strings,
4207 .get_coalesce = sky2_get_coalesce,
4208 .set_coalesce = sky2_set_coalesce,
4209 .get_ringparam = sky2_get_ringparam,
4210 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4211 .get_pauseparam = sky2_get_pauseparam,
4212 .set_pauseparam = sky2_set_pauseparam,
f4331a6d 4213 .phys_id = sky2_phys_id,
b9f2c044 4214 .get_sset_count = sky2_get_sset_count,
cd28ab6a 4215 .get_ethtool_stats = sky2_get_ethtool_stats,
bf73130d 4216 .set_flags = sky2_set_flags,
cd28ab6a
SH		 4217};
4218
3cf26753
SH		 4219#ifdef CONFIG_SKY2_DEBUG
4220
4221static struct dentry *sky2_debug;
4222
e4c2abe2
SH		 4223
4224/*
4225 * Read and parse the first part of Vital Product Data
4226 */
4227#define VPD_SIZE 128
4228#define VPD_MAGIC 0x82
4229
4230static const struct vpd_tag {
4231 char tag[2];
4232 char *label;
4233} vpd_tags[] = {
4234 { "PN", "Part Number" },
4235 { "EC", "Engineering Level" },
4236 { "MN", "Manufacturer" },
4237 { "SN", "Serial Number" },
4238 { "YA", "Asset Tag" },
4239 { "VL", "First Error Log Message" },
4240 { "VF", "Second Error Log Message" },
4241 { "VB", "Boot Agent ROM Configuration" },
4242 { "VE", "EFI UNDI Configuration" },
4243};
4244
4245static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4246{
4247 size_t vpd_size;
4248 loff_t offs;
4249 u8 len;
4250 unsigned char *buf;
4251 u16 reg2;
4252
4253 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4254 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4255
4256 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4257 buf = kmalloc(vpd_size, GFP_KERNEL);
4258 if (!buf) {
4259 seq_puts(seq, "no memory!\n");
4260 return;
4261 }
4262
4263 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4264 seq_puts(seq, "VPD read failed\n");
4265 goto out;
4266 }
4267
4268 if (buf[0] != VPD_MAGIC) {
4269 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4270 goto out;
4271 }
4272 len = buf[1];
4273 if (len == 0 || len > vpd_size - 4) {
4274 seq_printf(seq, "Invalid id length: %d\n", len);
4275 goto out;
4276 }
4277
4278 seq_printf(seq, "%.*s\n", len, buf + 3);
4279 offs = len + 3;
4280
4281 while (offs < vpd_size - 4) {
4282 int i;
4283
4284 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4285 break;
4286 len = buf[offs + 2];
4287 if (offs + len + 3 >= vpd_size)
4288 break;
4289
4290 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4291 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4292 seq_printf(seq, " %s: %.*s\n",
4293 vpd_tags[i].label, len, buf + offs + 3);
4294 break;
4295 }
4296 }
4297 offs += len + 3;
4298 }
4299out:
4300 kfree(buf);
4301}
4302
3cf26753
SH		 4303static int sky2_debug_show(struct seq_file *seq, void *v)
4304{
4305 struct net_device *dev = seq->private;
4306 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4307 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4308 unsigned port = sky2->port;
4309 unsigned idx, last;
4310 int sop;
4311
e4c2abe2 4312 sky2_show_vpd(seq, hw);
3cf26753 4313
e4c2abe2 4314 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4315 sky2_read32(hw, B0_ISRC),
4316 sky2_read32(hw, B0_IMSK),
4317 sky2_read32(hw, B0_Y2_SP_ICR));
4318
e4c2abe2
SH		 4319 if (!netif_running(dev)) {
4320 seq_printf(seq, "network not running\n");
4321 return 0;
4322 }
4323
bea3348e 4324 napi_disable(&hw->napi);
3cf26753
SH		 4325 last = sky2_read16(hw, STAT_PUT_IDX);
4326
efe91932 4327 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4328 if (hw->st_idx == last)
4329 seq_puts(seq, "Status ring (empty)\n");
4330 else {
4331 seq_puts(seq, "Status ring\n");
efe91932 4332 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4333 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4334 const struct sky2_status_le *le = hw->st_le + idx;
4335 seq_printf(seq, "[%d] %#x %d %#x\n",
4336 idx, le->opcode, le->length, le->status);
4337 }
4338 seq_puts(seq, "\n");
4339 }
4340
4341 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4342 sky2->tx_cons, sky2->tx_prod,
4343 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4344 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4345
4346 /* Dump contents of tx ring */
4347 sop = 1;
ee5f68fe
SH		 4348 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4349 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4350 const struct sky2_tx_le *le = sky2->tx_le + idx;
4351 u32 a = le32_to_cpu(le->addr);
4352
4353 if (sop)
4354 seq_printf(seq, "%u:", idx);
4355 sop = 0;
4356
4357 switch(le->opcode & ~HW_OWNER) {
4358 case OP_ADDR64:
4359 seq_printf(seq, " %#x:", a);
4360 break;
4361 case OP_LRGLEN:
4362 seq_printf(seq, " mtu=%d", a);
4363 break;
4364 case OP_VLAN:
4365 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4366 break;
4367 case OP_TCPLISW:
4368 seq_printf(seq, " csum=%#x", a);
4369 break;
4370 case OP_LARGESEND:
4371 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4372 break;
4373 case OP_PACKET:
4374 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4375 break;
4376 case OP_BUFFER:
4377 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4378 break;
4379 default:
4380 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4381 a, le16_to_cpu(le->length));
4382 }
4383
4384 if (le->ctrl & EOP) {
4385 seq_putc(seq, '\n');
4386 sop = 1;
4387 }
4388 }
4389
4390 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4391 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4392 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4393 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4394
d1d08d12 4395 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4396 napi_enable(&hw->napi);
3cf26753
SH		 4397 return 0;
4398}
4399
4400static int sky2_debug_open(struct inode *inode, struct file *file)
4401{
4402 return single_open(file, sky2_debug_show, inode->i_private);
4403}
4404
4405static const struct file_operations sky2_debug_fops = {
4406 .owner = THIS_MODULE,
4407 .open = sky2_debug_open,
4408 .read = seq_read,
4409 .llseek = seq_lseek,
4410 .release = single_release,
4411};
4412
4413/*
4414 * Use network device events to create/remove/rename
4415 * debugfs file entries
4416 */
4417static int sky2_device_event(struct notifier_block *unused,
4418 unsigned long event, void *ptr)
4419{
4420 struct net_device *dev = ptr;
5b296bc9 4421 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4422
1436b301 4423 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
5b296bc9 4424 return NOTIFY_DONE;
3cf26753 4425
5b296bc9
SH		 4426 switch(event) {
4427 case NETDEV_CHANGENAME:
4428 if (sky2->debugfs) {
4429 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4430 sky2_debug, dev->name);
4431 }
4432 break;
3cf26753 4433
5b296bc9
SH		 4434 case NETDEV_GOING_DOWN:
4435 if (sky2->debugfs) {
ada1db5c 4436 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4437 debugfs_remove(sky2->debugfs);
4438 sky2->debugfs = NULL;
3cf26753 4439 }
5b296bc9
SH		 4440 break;
4441
4442 case NETDEV_UP:
4443 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4444 sky2_debug, dev,
4445 &sky2_debug_fops);
4446 if (IS_ERR(sky2->debugfs))
4447 sky2->debugfs = NULL;
3cf26753
SH		 4448 }
4449
4450 return NOTIFY_DONE;
4451}
4452
4453static struct notifier_block sky2_notifier = {
4454 .notifier_call = sky2_device_event,
4455};
4456
4457
4458static __init void sky2_debug_init(void)
4459{
4460 struct dentry *ent;
4461
4462 ent = debugfs_create_dir("sky2", NULL);
4463 if (!ent || IS_ERR(ent))
4464 return;
4465
4466 sky2_debug = ent;
4467 register_netdevice_notifier(&sky2_notifier);
4468}
4469
4470static __exit void sky2_debug_cleanup(void)
4471{
4472 if (sky2_debug) {
4473 unregister_netdevice_notifier(&sky2_notifier);
4474 debugfs_remove(sky2_debug);
4475 sky2_debug = NULL;
4476 }
4477}
4478
4479#else
4480#define sky2_debug_init()
4481#define sky2_debug_cleanup()
4482#endif
4483
1436b301
SH		 4484/* Two copies of network device operations to handle special case of
4485 not allowing netpoll on second port */
4486static const struct net_device_ops sky2_netdev_ops[2] = {
4487 {
4488 .ndo_open = sky2_up,
4489 .ndo_stop = sky2_down,
00829823 4490 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4491 .ndo_do_ioctl = sky2_ioctl,
4492 .ndo_validate_addr = eth_validate_addr,
4493 .ndo_set_mac_address = sky2_set_mac_address,
4494 .ndo_set_multicast_list = sky2_set_multicast,
4495 .ndo_change_mtu = sky2_change_mtu,
4496 .ndo_tx_timeout = sky2_tx_timeout,
4497#ifdef SKY2_VLAN_TAG_USED
4498 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4499#endif
4500#ifdef CONFIG_NET_POLL_CONTROLLER
4501 .ndo_poll_controller = sky2_netpoll,
4502#endif
4503 },
4504 {
4505 .ndo_open = sky2_up,
4506 .ndo_stop = sky2_down,
00829823 4507 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4508 .ndo_do_ioctl = sky2_ioctl,
4509 .ndo_validate_addr = eth_validate_addr,
4510 .ndo_set_mac_address = sky2_set_mac_address,
4511 .ndo_set_multicast_list = sky2_set_multicast,
4512 .ndo_change_mtu = sky2_change_mtu,
4513 .ndo_tx_timeout = sky2_tx_timeout,
4514#ifdef SKY2_VLAN_TAG_USED
4515 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4516#endif
4517 },
4518};
3cf26753 4519
cd28ab6a
SH		 4520/* Initialize network device */
4521static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4522 unsigned port,
be63a21c 4523 int highmem, int wol)
cd28ab6a
SH		 4524{
4525 struct sky2_port *sky2;
4526 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4527
4528 if (!dev) {
898eb71c 4529 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
cd28ab6a
SH		 4530 return NULL;
4531 }
4532
cd28ab6a 4533 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4534 dev->irq = hw->pdev->irq;
cd28ab6a 4535 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4536 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4537 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4538
4539 sky2 = netdev_priv(dev);
4540 sky2->netdev = dev;
4541 sky2->hw = hw;
4542 sky2->msg_enable = netif_msg_init(debug, default_msg);
4543
cd28ab6a 4544 /* Auto speed and flow control */
0ea065e5
SH		 4545 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4546 if (hw->chip_id != CHIP_ID_YUKON_XL)
4547 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4548
16ad91e1
SH		 4549 sky2->flow_mode = FC_BOTH;
4550
cd28ab6a
SH		 4551 sky2->duplex = -1;
4552 sky2->speed = -1;
4553 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4554 sky2->wol = wol;
75d070c5 4555
e07b1aa8 4556 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4557
793b883e 4558 sky2->tx_pending = TX_DEF_PENDING;
ee5f68fe 4559 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
290d4de5 4560 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4561
4562 hw->dev[port] = dev;
4563
4564 sky2->port = port;
4565
4a50a876 4566 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 4567 if (highmem)
4568 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4569
bf73130d
SH		 4570 /* Enable receive hashing unless hardware is known broken */
4571 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4572 dev->features |= NETIF_F_RXHASH;
4573
d1f13708 4574#ifdef SKY2_VLAN_TAG_USED
d6c9bc1e
SH		 4575 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4576 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4577 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4578 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
d6c9bc1e 4579 }
d1f13708
SH		 4580#endif
4581
cd28ab6a 4582 /* read the mac address */
793b883e 4583 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4584 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4585
cd28ab6a
SH		 4586 return dev;
4587}
4588
28bd181a 4589static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4590{
4591 const struct sky2_port *sky2 = netdev_priv(dev);
4592
6c35abae 4593 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4594}
4595
fb2690a9 4596/* Handle software interrupt used during MSI test */
7d12e780 4597static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4598{
4599 struct sky2_hw *hw = dev_id;
4600 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4601
4602 if (status == 0)
4603 return IRQ_NONE;
4604
4605 if (status & Y2_IS_IRQ_SW) {
ea76e635 4606 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4607 wake_up(&hw->msi_wait);
4608 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4609 }
4610 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4611
4612 return IRQ_HANDLED;
4613}
4614
4615/* Test interrupt path by forcing a a software IRQ */
4616static int __devinit sky2_test_msi(struct sky2_hw *hw)
4617{
4618 struct pci_dev *pdev = hw->pdev;
4619 int err;
4620
bb507fe1
SH		 4621 init_waitqueue_head (&hw->msi_wait);
4622
fb2690a9
SH		 4623 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4624
b0a20ded 4625 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4626 if (err) {
b02a9258 4627 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4628 return err;
4629 }
4630
fb2690a9 4631 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4632 sky2_read8(hw, B0_CTST);
fb2690a9 4633
ea76e635 4634 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4635
ea76e635 4636 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4637 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4638 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4639 "switching to INTx mode.\n");
fb2690a9
SH		 4640
4641 err = -EOPNOTSUPP;
4642 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4643 }
4644
4645 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4646 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4647
4648 free_irq(pdev->irq, hw);
4649
4650 return err;
4651}
4652
c7127a34
SH		 4653/* This driver supports yukon2 chipset only */
4654static const char *sky2_name(u8 chipid, char *buf, int sz)
4655{
4656 const char *name[] = {
4657 "XL", /* 0xb3 */
4658 "EC Ultra", /* 0xb4 */
4659 "Extreme", /* 0xb5 */
4660 "EC", /* 0xb6 */
4661 "FE", /* 0xb7 */
4662 "FE+", /* 0xb8 */
4663 "Supreme", /* 0xb9 */
0ce8b98d 4664 "UL 2", /* 0xba */
0f5aac70
SH		 4665 "Unknown", /* 0xbb */
4666 "Optima", /* 0xbc */
c7127a34
SH		 4667 };
4668
dae3a511 4669 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
c7127a34
SH		 4670 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4671 else
4672 snprintf(buf, sz, "(chip %#x)", chipid);
4673 return buf;
4674}
4675
cd28ab6a
SH		 4676static int __devinit sky2_probe(struct pci_dev *pdev,
4677 const struct pci_device_id *ent)
4678{
7f60c64b 4679 struct net_device *dev;
cd28ab6a 4680 struct sky2_hw *hw;
be63a21c 4681 int err, using_dac = 0, wol_default;
3834507d 4682 u32 reg;
c7127a34 4683 char buf1[16];
cd28ab6a 4684
793b883e
SH		 4685 err = pci_enable_device(pdev);
4686 if (err) {
b02a9258 4687 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4688 goto err_out;
4689 }
4690
6cc90a5a
SH		 4691 /* Get configuration information
4692 * Note: only regular PCI config access once to test for HW issues
4693 * other PCI access through shared memory for speed and to
4694 * avoid MMCONFIG problems.
4695 */
4696 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4697 if (err) {
4698 dev_err(&pdev->dev, "PCI read config failed\n");
4699 goto err_out;
4700 }
4701
4702 if (~reg == 0) {
4703 dev_err(&pdev->dev, "PCI configuration read error\n");
4704 goto err_out;
4705 }
4706
793b883e
SH		 4707 err = pci_request_regions(pdev, DRV_NAME);
4708 if (err) {
b02a9258 4709 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4710 goto err_out_disable;
cd28ab6a
SH		 4711 }
4712
4713 pci_set_master(pdev);
4714
d1f3d4dd 4715 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4716 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4717 using_dac = 1;
6a35528a 4718 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4719 if (err < 0) {
b02a9258
SH		 4720 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4721 "for consistent allocations\n");
d1f3d4dd
SH		 4722 goto err_out_free_regions;
4723 }
d1f3d4dd 4724 } else {
284901a9 4725 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4726 if (err) {
b02a9258 4727 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4728 goto err_out_free_regions;
4729 }
4730 }
d1f3d4dd 4731
3834507d
SH		 4732
4733#ifdef __BIG_ENDIAN
4734 /* The sk98lin vendor driver uses hardware byte swapping but
4735 * this driver uses software swapping.
4736 */
4737 reg &= ~PCI_REV_DESC;
4738 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4739 if (err) {
4740 dev_err(&pdev->dev, "PCI write config failed\n");
4741 goto err_out_free_regions;
4742 }
4743#endif
4744
9d731d77 4745 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4746
cd28ab6a 4747 err = -ENOMEM;
66466797
SH		 4748
4749 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4750 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4751 if (!hw) {
b02a9258 4752 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4753 goto err_out_free_regions;
4754 }
4755
cd28ab6a 4756 hw->pdev = pdev;
66466797 4757 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4758
4759 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4760 if (!hw->regs) {
b02a9258 4761 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4762 goto err_out_free_hw;
4763 }
4764
e3173832 4765 err = sky2_init(hw);
cd28ab6a 4766 if (err)
793b883e 4767 goto err_out_iounmap;
cd28ab6a 4768
efe91932 4769 /* ring for status responses */
bf73130d 4770 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4771 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4772 &hw->st_dma);
4773 if (!hw->st_le)
4774 goto err_out_reset;
4775
c844d483
SH		 4776 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4777 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4778
e3173832
SH		 4779 sky2_reset(hw);
4780
be63a21c 4781 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4782 if (!dev) {
4783 err = -ENOMEM;
cd28ab6a 4784 goto err_out_free_pci;
7f60c64b 4785 }
cd28ab6a 4786
9fa1b1f3
SH		 4787 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4788 err = sky2_test_msi(hw);
4789 if (err == -EOPNOTSUPP)
4790 pci_disable_msi(pdev);
4791 else if (err)
4792 goto err_out_free_netdev;
4793 }
4794
793b883e
SH		 4795 err = register_netdev(dev);
4796 if (err) {
b02a9258 4797 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 4798 goto err_out_free_netdev;
4799 }
4800
33cb7d33
BP		 4801 netif_carrier_off(dev);
4802
6de16237
SH		 4803 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4804
ea76e635
SH		 4805 err = request_irq(pdev->irq, sky2_intr,
4806 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
66466797 4807 hw->irq_name, hw);
9fa1b1f3 4808 if (err) {
b02a9258 4809 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 4810 goto err_out_unregister;
4811 }
4812 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4813 napi_enable(&hw->napi);
9fa1b1f3 4814
cd28ab6a
SH		 4815 sky2_show_addr(dev);
4816
7f60c64b 4817 if (hw->ports > 1) {
4818 struct net_device *dev1;
4819
ca519274 4820 err = -ENOMEM;
be63a21c 4821 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
ca519274
SH		 4822 if (dev1 && (err = register_netdev(dev1)) == 0)
4823 sky2_show_addr(dev1);
4824 else {
b02a9258
SH		 4825 dev_warn(&pdev->dev,
4826 "register of second port failed (%d)\n", err);
cd28ab6a 4827 hw->dev[1] = NULL;
ca519274
SH		 4828 hw->ports = 1;
4829 if (dev1)
4830 free_netdev(dev1);
4831 }
cd28ab6a
SH		 4832 }
4833
32c2c300 4834 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 4835 INIT_WORK(&hw->restart_work, sky2_restart);
4836
793b883e 4837 pci_set_drvdata(pdev, hw);
1ae861e6 4838 pdev->d3_delay = 150;
793b883e 4839
cd28ab6a
SH		 4840 return 0;
4841
793b883e 4842err_out_unregister:
ea76e635 4843 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4844 pci_disable_msi(pdev);
793b883e 4845 unregister_netdev(dev);
cd28ab6a
SH		 4846err_out_free_netdev:
4847 free_netdev(dev);
cd28ab6a 4848err_out_free_pci:
efe91932 4849 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4850 hw->st_le, hw->st_dma);
4851err_out_reset:
793b883e 4852 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 4853err_out_iounmap:
4854 iounmap(hw->regs);
4855err_out_free_hw:
4856 kfree(hw);
4857err_out_free_regions:
4858 pci_release_regions(pdev);
44a1d2e5 4859err_out_disable:
cd28ab6a 4860 pci_disable_device(pdev);
cd28ab6a 4861err_out:
549a68c3 4862 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 4863 return err;
4864}
4865
4866static void __devexit sky2_remove(struct pci_dev *pdev)
4867{
793b883e 4868 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 4869 int i;
cd28ab6a 4870
793b883e 4871 if (!hw)
cd28ab6a
SH		 4872 return;
4873
32c2c300 4874 del_timer_sync(&hw->watchdog_timer);
6de16237 4875 cancel_work_sync(&hw->restart_work);
d27ed387 4876
b877fe28 4877 for (i = hw->ports-1; i >= 0; --i)
6de16237 4878 unregister_netdev(hw->dev[i]);
81906791 4879
d27ed387 4880 sky2_write32(hw, B0_IMSK, 0);
cd28ab6a 4881
ae306cca
SH		 4882 sky2_power_aux(hw);
4883
793b883e 4884 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 4885 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 4886
4887 free_irq(pdev->irq, hw);
ea76e635 4888 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 4889 pci_disable_msi(pdev);
efe91932 4890 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4891 hw->st_le, hw->st_dma);
cd28ab6a
SH		 4892 pci_release_regions(pdev);
4893 pci_disable_device(pdev);
793b883e 4894
b877fe28 4895 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 4896 free_netdev(hw->dev[i]);
4897
cd28ab6a
SH		 4898 iounmap(hw->regs);
4899 kfree(hw);
5afa0a9c 4900
cd28ab6a
SH		 4901 pci_set_drvdata(pdev, NULL);
4902}
4903
cd28ab6a
SH		 4904static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4905{
793b883e 4906 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 4907 int i, wol = 0;
cd28ab6a 4908
549a68c3
SH		 4909 if (!hw)
4910 return 0;
4911
063a0b38
SH		 4912 del_timer_sync(&hw->watchdog_timer);
4913 cancel_work_sync(&hw->restart_work);
4914
19720737 4915 rtnl_lock();
f05267e7 4916 for (i = 0; i < hw->ports; i++) {
cd28ab6a 4917 struct net_device *dev = hw->dev[i];
e3173832 4918 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4919
af18d8b8 4920 sky2_detach(dev);
e3173832
SH		 4921
4922 if (sky2->wol)
4923 sky2_wol_init(sky2);
4924
4925 wol |= sky2->wol;
cd28ab6a
SH		 4926 }
4927
5f8ae5c5 4928 device_set_wakeup_enable(&pdev->dev, wol != 0);
4929
8ab8fca2 4930 sky2_write32(hw, B0_IMSK, 0);
6de16237 4931 napi_disable(&hw->napi);
ae306cca 4932 sky2_power_aux(hw);
19720737 4933 rtnl_unlock();
e3173832 4934
d374c1c1 4935 pci_save_state(pdev);
e3173832 4936 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
f71eb1a2 4937 pci_set_power_state(pdev, pci_choose_state(pdev, state));
ae306cca 4938
2ccc99b7 4939 return 0;
cd28ab6a
SH		 4940}
4941
5f8ae5c5 4942#ifdef CONFIG_PM
cd28ab6a
SH		 4943static int sky2_resume(struct pci_dev *pdev)
4944{
793b883e 4945 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 4946 int i, err;
cd28ab6a 4947
549a68c3
SH		 4948 if (!hw)
4949 return 0;
4950
2a400189 4951 rtnl_lock();
f71eb1a2
SH		 4952 err = pci_set_power_state(pdev, PCI_D0);
4953 if (err)
4954 goto out;
ae306cca
SH		 4955
4956 err = pci_restore_state(pdev);
4957 if (err)
4958 goto out;
4959
cd28ab6a 4960 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 4961
4962 /* Re-enable all clocks */
a0db28b8 4963 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4964 if (err) {
4965 dev_err(&pdev->dev, "PCI write config failed\n");
4966 goto out;
4967 }
1ad5b4a5 4968
e3173832 4969 sky2_reset(hw);
8ab8fca2 4970 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
6de16237 4971 napi_enable(&hw->napi);
8ab8fca2 4972
f05267e7 4973 for (i = 0; i < hw->ports; i++) {
af18d8b8
SH		 4974 err = sky2_reattach(hw->dev[i]);
4975 if (err)
4976 goto out;
cd28ab6a 4977 }
af18d8b8 4978 rtnl_unlock();
eb35cf60 4979
ae306cca 4980 return 0;
08c06d8a 4981out:
af18d8b8
SH		 4982 rtnl_unlock();
4983
b02a9258 4984 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 4985 pci_disable_device(pdev);
08c06d8a 4986 return err;
cd28ab6a
SH		 4987}
4988#endif
4989
e3173832
SH		 4990static void sky2_shutdown(struct pci_dev *pdev)
4991{
5f8ae5c5 4992 sky2_suspend(pdev, PMSG_SUSPEND);
e3173832
SH		 4993}
4994
cd28ab6a 4995static struct pci_driver sky2_driver = {
793b883e
SH		 4996 .name = DRV_NAME,
4997 .id_table = sky2_id_table,
4998 .probe = sky2_probe,
4999 .remove = __devexit_p(sky2_remove),
cd28ab6a 5000#ifdef CONFIG_PM
793b883e
SH		 5001 .suspend = sky2_suspend,
5002 .resume = sky2_resume,
cd28ab6a 5003#endif
e3173832 5004 .shutdown = sky2_shutdown,
cd28ab6a
SH		 5005};
5006
5007static int __init sky2_init_module(void)
5008{
ada1db5c 5009 pr_info("driver version " DRV_VERSION "\n");
c844d483 5010
3cf26753 5011 sky2_debug_init();
50241c4c 5012 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5013}
5014
5015static void __exit sky2_cleanup_module(void)
5016{
5017 pci_unregister_driver(&sky2_driver);
3cf26753 5018 sky2_debug_cleanup();
cd28ab6a
SH		 5019}
5020
5021module_init(sky2_init_module);
5022module_exit(sky2_cleanup_module);
5023
5024MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5025MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5026MODULE_LICENSE("GPL");
5f4f9dc1 5027MODULE_VERSION(DRV_VERSION);
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