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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
52c89cac 52#define DRV_VERSION "1.10"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
e5b74c7d
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 196{
197 u16 power_control;
5afa0a9c 198 int vaux;
5afa0a9c
SH		 199
200 pr_debug("sky2_set_power_state %d\n", state);
201 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
202
56a645cc 203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 204 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 205 (power_control & PCI_PM_CAP_PME_D3cold);
206
56a645cc 207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 208
209 power_control |= PCI_PM_CTRL_PME_STATUS;
210 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
211
212 switch (state) {
213 case PCI_D0:
214 /* switch power to VCC (WA for VAUX problem) */
215 sky2_write8(hw, B0_POWER_CTRL,
216 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
217
218 /* disable Core Clock Division, */
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
220
221 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
222 /* enable bits are inverted */
223 sky2_write8(hw, B2_Y2_CLK_GATE,
224 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
225 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
226 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
227 else
228 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
229
977bdf06 230 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 231 u32 reg1;
232
56a645cc
SH		 233 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
234 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 235 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 236 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
237 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 238 }
239
5afa0a9c
SH		 240 break;
241
242 case PCI_D3hot:
243 case PCI_D3cold:
5afa0a9c
SH		 244 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
245 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
246 else
247 /* enable bits are inverted */
248 sky2_write8(hw, B2_Y2_CLK_GATE,
249 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
250 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
251 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
252
253 /* switch power to VAUX */
254 if (vaux && state != PCI_D3cold)
255 sky2_write8(hw, B0_POWER_CTRL,
256 (PC_VAUX_ENA | PC_VCC_ENA |
257 PC_VAUX_ON | PC_VCC_OFF));
258 break;
259 default:
260 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 261 }
262
56a645cc 263 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 264 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 265}
266
d3bcfbeb 267static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 268{
269 u16 reg;
270
271 /* disable all GMAC IRQ's */
272 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
273 /* disable PHY IRQs */
274 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 275
cd28ab6a
SH		 276 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
277 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
278 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
280
281 reg = gma_read16(hw, port, GM_RX_CTRL);
282 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
283 gma_write16(hw, port, GM_RX_CTRL, reg);
284}
285
16ad91e1
SH		 286/* flow control to advertise bits */
287static const u16 copper_fc_adv[] = {
288 [FC_NONE] = 0,
289 [FC_TX] = PHY_M_AN_ASP,
290 [FC_RX] = PHY_M_AN_PC,
291 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
292};
293
294/* flow control to advertise bits when using 1000BaseX */
295static const u16 fiber_fc_adv[] = {
296 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
297 [FC_TX] = PHY_M_P_ASYM_MD_X,
298 [FC_RX] = PHY_M_P_SYM_MD_X,
299 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
300};
301
302/* flow control to GMA disable bits */
303static const u16 gm_fc_disable[] = {
304 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
305 [FC_TX] = GM_GPCR_FC_RX_DIS,
306 [FC_RX] = GM_GPCR_FC_TX_DIS,
307 [FC_BOTH] = 0,
308};
309
310
cd28ab6a
SH		 311static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
312{
313 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 314 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 315
ed6d32c7 316 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 317 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 318 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
319
320 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 321 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 322 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
323
324 if (hw->chip_id == CHIP_ID_YUKON_EC)
325 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
326 else
327 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
328
329 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
330 }
331
332 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 333 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 334 if (hw->chip_id == CHIP_ID_YUKON_FE) {
335 /* enable automatic crossover */
336 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
337 } else {
338 /* disable energy detect */
339 ctrl &= ~PHY_M_PC_EN_DET_MSK;
340
341 /* enable automatic crossover */
342 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
343
344 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 345 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 346 ctrl &= ~PHY_M_PC_DSC_MSK;
347 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
348 }
349 }
cd28ab6a
SH		 350 } else {
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
353
354 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 355 }
cd28ab6a 356
b89165f2
SH		 357 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358
359 /* special setup for PHY 88E1112 Fiber */
360 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
361 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 362
b89165f2
SH		 363 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
364 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
365 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
366 ctrl &= ~PHY_M_MAC_MD_MSK;
367 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
368 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
369
370 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 371 /* select page 1 to access Fiber registers */
372 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 373
374 /* for SFP-module set SIGDET polarity to low */
375 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
376 ctrl |= PHY_M_FIB_SIGD_POL;
377 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 378 }
b89165f2
SH		 379
380 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 381 }
382
7800fddc 383 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 384 ct1000 = 0;
385 adv = PHY_AN_CSMA;
2eaba1a2 386 reg = 0;
cd28ab6a
SH		 387
388 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 389 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 390 if (sky2->advertising & ADVERTISED_1000baseT_Full)
391 ct1000 |= PHY_M_1000C_AFD;
392 if (sky2->advertising & ADVERTISED_1000baseT_Half)
393 ct1000 |= PHY_M_1000C_AHD;
394 if (sky2->advertising & ADVERTISED_100baseT_Full)
395 adv |= PHY_M_AN_100_FD;
396 if (sky2->advertising & ADVERTISED_100baseT_Half)
397 adv |= PHY_M_AN_100_HD;
398 if (sky2->advertising & ADVERTISED_10baseT_Full)
399 adv |= PHY_M_AN_10_FD;
400 if (sky2->advertising & ADVERTISED_10baseT_Half)
401 adv |= PHY_M_AN_10_HD;
709c6e7b 402
16ad91e1 403 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 404 } else { /* special defines for FIBER (88E1040S only) */
405 if (sky2->advertising & ADVERTISED_1000baseT_Full)
406 adv |= PHY_M_AN_1000X_AFD;
407 if (sky2->advertising & ADVERTISED_1000baseT_Half)
408 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 409
16ad91e1 410 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 411 }
cd28ab6a
SH		 412
413 /* Restart Auto-negotiation */
414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
415 } else {
416 /* forced speed/duplex settings */
417 ct1000 = PHY_M_1000C_MSE;
418
2eaba1a2
SH		 419 /* Disable auto update for duplex flow control and speed */
420 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 421
422 switch (sky2->speed) {
423 case SPEED_1000:
424 ctrl |= PHY_CT_SP1000;
2eaba1a2 425 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 426 break;
427 case SPEED_100:
428 ctrl |= PHY_CT_SP100;
2eaba1a2 429 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 430 break;
431 }
432
2eaba1a2
SH		 433 if (sky2->duplex == DUPLEX_FULL) {
434 reg |= GM_GPCR_DUP_FULL;
435 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 436 } else if (sky2->speed < SPEED_1000)
437 sky2->flow_mode = FC_NONE;
2eaba1a2 438
2eaba1a2 439
16ad91e1 440 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 441
442 /* Forward pause packets to GMAC? */
16ad91e1 443 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 444 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
445 else
446 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 447 }
448
2eaba1a2
SH		 449 gma_write16(hw, port, GM_GP_CTRL, reg);
450
cd28ab6a
SH		 451 if (hw->chip_id != CHIP_ID_YUKON_FE)
452 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
453
454 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
455 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
456
457 /* Setup Phy LED's */
458 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
459 ledover = 0;
460
461 switch (hw->chip_id) {
462 case CHIP_ID_YUKON_FE:
463 /* on 88E3082 these bits are at 11..9 (shifted left) */
464 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
465
466 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
467
468 /* delete ACT LED control bits */
469 ctrl &= ~PHY_M_FELP_LED1_MSK;
470 /* change ACT LED control to blink mode */
471 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
472 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
473 break;
474
475 case CHIP_ID_YUKON_XL:
793b883e 476 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 477
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480
481 /* set LED Function Control register */
ed6d32c7
SH		 482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 487
488 /* set Polarity Control register */
489 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 490 (PHY_M_POLC_LS1_P_MIX(4) |
491 PHY_M_POLC_IS0_P_MIX(4) |
492 PHY_M_POLC_LOS_CTRL(2) |
493 PHY_M_POLC_INIT_CTRL(2) |
494 PHY_M_POLC_STA1_CTRL(2) |
495 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 496
497 /* restore page register */
793b883e 498 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 499 break;
ed6d32c7
SH		 500 case CHIP_ID_YUKON_EC_U:
501 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
502
503 /* select page 3 to access LED control register */
504 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
505
506 /* set LED Function Control register */
507 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
508 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
509 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
510 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
511 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
512
513 /* set Blink Rate in LED Timer Control Register */
514 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
515 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
516 /* restore page register */
517 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
518 break;
cd28ab6a
SH		 519
520 default:
521 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
522 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
523 /* turn off the Rx LED (LED_RX) */
0efdf262 524 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 525 }
526
ed6d32c7 527 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 528 /* apply fixes in PHY AFE */
ed6d32c7
SH		 529 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
531
977bdf06 532 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 533 gm_phy_write(hw, port, 0x18, 0xaa99);
534 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 535
977bdf06 536 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 537 gm_phy_write(hw, port, 0x18, 0xa204);
538 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 539
540 /* set page register to 0 */
ed6d32c7 541 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 542 } else {
543 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 544
977bdf06
SH		 545 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
546 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 547 ledover |= PHY_M_LED_MO_100;
977bdf06 548 }
cd28ab6a 549
977bdf06
SH		 550 if (ledover)
551 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
552
553 }
2eaba1a2 554
d571b694 555 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 556 if (sky2->autoneg == AUTONEG_ENABLE)
557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
558 else
559 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
560}
561
d3bcfbeb
SH		 562static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
563{
564 u32 reg1;
565 static const u32 phy_power[]
566 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
567
568 /* looks like this XL is back asswards .. */
569 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
570 onoff = !onoff;
571
aed2cec4 572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 573 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 574 if (onoff)
575 /* Turn off phy power saving */
576 reg1 &= ~phy_power[port];
577 else
578 reg1 |= phy_power[port];
579
580 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 581 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 582 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 583 udelay(100);
584}
585
1b537565
SH		 586/* Force a renegotiation */
587static void sky2_phy_reinit(struct sky2_port *sky2)
588{
e07b1aa8 589 spin_lock_bh(&sky2->phy_lock);
1b537565 590 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 591 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 592}
593
cd28ab6a
SH		 594static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
595{
596 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 u16 reg;
598 int i;
599 const u8 *addr = hw->dev[port]->dev_addr;
600
42eeea01
SH		 601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 603
604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
605
793b883e 606 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 607 /* WA DEV_472 -- looks like crossed wires on port 2 */
608 /* clear GMAC 1 Control reset */
609 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
610 do {
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
613 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
614 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
615 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 }
617
793b883e 618 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 619
2eaba1a2
SH		 620 /* Enable Transmit FIFO Underrun */
621 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
622
e07b1aa8 623 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 624 sky2_phy_init(hw, port);
e07b1aa8 625 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 626
627 /* MIB clear */
628 reg = gma_read16(hw, port, GM_PHY_ADDR);
629 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
630
43f2f104
SH		 631 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
632 gma_read16(hw, port, i);
cd28ab6a
SH		 633 gma_write16(hw, port, GM_PHY_ADDR, reg);
634
635 /* transmit control */
636 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
637
638 /* receive control reg: unicast + multicast + no FCS */
639 gma_write16(hw, port, GM_RX_CTRL,
793b883e 640 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 641
642 /* transmit flow control */
643 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
644
645 /* transmit parameter */
646 gma_write16(hw, port, GM_TX_PARAM,
647 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
648 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
649 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
650 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
651
652 /* serial mode register */
653 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 654 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 655
6b1a3aef 656 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 657 reg |= GM_SMOD_JUMBO_ENA;
658
659 gma_write16(hw, port, GM_SERIAL_MODE, reg);
660
cd28ab6a
SH		 661 /* virtual address for data */
662 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
663
793b883e
SH		 664 /* physical address: used for pause frames */
665 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
666
667 /* ignore counter overflows */
cd28ab6a
SH		 668 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
671
672 /* Configure Rx MAC FIFO */
673 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 674 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
675 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 676
d571b694 677 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 679
8df9a876
SH		 680 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
681 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 682
683 /* Configure Tx MAC FIFO */
684 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
685 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 686
687 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
8df9a876 688 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 689 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
690 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
691 /* set Tx GMAC FIFO Almost Empty Threshold */
692 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
693 /* Disable Store & Forward mode for TX */
694 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
695 }
696 }
697
cd28ab6a
SH		 698}
699
67712901
SH		 700/* Assign Ram Buffer allocation to queue */
701static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 702{
67712901
SH		 703 u32 end;
704
705 /* convert from K bytes to qwords used for hw register */
706 start *= 1024/8;
707 space *= 1024/8;
708 end = start + space - 1;
793b883e 709
cd28ab6a
SH		 710 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
711 sky2_write32(hw, RB_ADDR(q, RB_START), start);
712 sky2_write32(hw, RB_ADDR(q, RB_END), end);
713 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
714 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
715
716 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 717 u32 tp = space - space/4;
793b883e 718
1c28f6ba
SH		 719 /* On receive queue's set the thresholds
720 * give receiver priority when > 3/4 full
721 * send pause when down to 2K
722 */
723 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
724 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 725
1c28f6ba
SH		 726 tp = space - 2048/8;
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 729 } else {
730 /* Enable store & forward on Tx queue's because
731 * Tx FIFO is only 1K on Yukon
732 */
733 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
734 }
735
736 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 737 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 738}
739
cd28ab6a 740/* Setup Bus Memory Interface */
af4ed7e6 741static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 742{
743 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
744 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
745 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 746 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 747}
748
cd28ab6a
SH		 749/* Setup prefetch unit registers. This is the interface between
750 * hardware and driver list elements
751 */
8cc048e3 752static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 753 u64 addr, u32 last)
754{
cd28ab6a
SH		 755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
756 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
757 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
758 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
759 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 761
762 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 763}
764
793b883e
SH		 765static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
766{
767 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
768
cb5d9547 769 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 770 le->ctrl = 0;
793b883e
SH		 771 return le;
772}
cd28ab6a 773
291ea614
SH		 774static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
775 struct sky2_tx_le *le)
776{
777 return sky2->tx_ring + (le - sky2->tx_le);
778}
779
290d4de5
SH		 780/* Update chip's next pointer */
781static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 782{
98232f85 783 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 784 wmb();
98232f85
SH		 785 sky2_write16(hw, q, idx);
786 sky2_read16(hw, q);
cd28ab6a
SH		 787}
788
793b883e 789
cd28ab6a
SH		 790static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
791{
792 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 793 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 794 le->ctrl = 0;
cd28ab6a
SH		 795 return le;
796}
797
a018e330
SH		 798/* Return high part of DMA address (could be 32 or 64 bit) */
799static inline u32 high32(dma_addr_t a)
800{
a036119f 801 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 802}
803
14d0263f
SH		 804/* Build description to hardware for one receive segment */
805static void sky2_rx_add(struct sky2_port *sky2, u8 op,
806 dma_addr_t map, unsigned len)
cd28ab6a
SH		 807{
808 struct sky2_rx_le *le;
734d1868 809 u32 hi = high32(map);
cd28ab6a 810
793b883e 811 if (sky2->rx_addr64 != hi) {
cd28ab6a 812 le = sky2_next_rx(sky2);
793b883e 813 le->addr = cpu_to_le32(hi);
cd28ab6a 814 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 815 sky2->rx_addr64 = high32(map + len);
cd28ab6a 816 }
793b883e 817
cd28ab6a 818 le = sky2_next_rx(sky2);
734d1868
SH		 819 le->addr = cpu_to_le32((u32) map);
820 le->length = cpu_to_le16(len);
14d0263f 821 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 822}
823
14d0263f
SH		 824/* Build description to hardware for one possibly fragmented skb */
825static void sky2_rx_submit(struct sky2_port *sky2,
826 const struct rx_ring_info *re)
827{
828 int i;
829
830 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
831
832 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
833 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
834}
835
836
837static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
838 unsigned size)
839{
840 struct sk_buff *skb = re->skb;
841 int i;
842
843 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
844 pci_unmap_len_set(re, data_size, size);
845
846 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
847 re->frag_addr[i] = pci_map_page(pdev,
848 skb_shinfo(skb)->frags[i].page,
849 skb_shinfo(skb)->frags[i].page_offset,
850 skb_shinfo(skb)->frags[i].size,
851 PCI_DMA_FROMDEVICE);
852}
853
854static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
855{
856 struct sk_buff *skb = re->skb;
857 int i;
858
859 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
860 PCI_DMA_FROMDEVICE);
861
862 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
863 pci_unmap_page(pdev, re->frag_addr[i],
864 skb_shinfo(skb)->frags[i].size,
865 PCI_DMA_FROMDEVICE);
866}
793b883e 867
cd28ab6a
SH		 868/* Tell chip where to start receive checksum.
869 * Actually has two checksums, but set both same to avoid possible byte
870 * order problems.
871 */
793b883e 872static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 873{
874 struct sky2_rx_le *le;
875
cd28ab6a 876 le = sky2_next_rx(sky2);
f65b138c 877 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 878 le->ctrl = 0;
879 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 880
793b883e
SH		 881 sky2_write32(sky2->hw,
882 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
883 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 884
885}
886
6b1a3aef
SH		 887/*
888 * The RX Stop command will not work for Yukon-2 if the BMU does not
889 * reach the end of packet and since we can't make sure that we have
890 * incoming data, we must reset the BMU while it is not doing a DMA
891 * transfer. Since it is possible that the RX path is still active,
892 * the RX RAM buffer will be stopped first, so any possible incoming
893 * data will not trigger a DMA. After the RAM buffer is stopped, the
894 * BMU is polled until any DMA in progress is ended and only then it
895 * will be reset.
896 */
897static void sky2_rx_stop(struct sky2_port *sky2)
898{
899 struct sky2_hw *hw = sky2->hw;
900 unsigned rxq = rxqaddr[sky2->port];
901 int i;
902
903 /* disable the RAM Buffer receive queue */
904 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
905
906 for (i = 0; i < 0xffff; i++)
907 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
908 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
909 goto stopped;
910
911 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
912 sky2->netdev->name);
913stopped:
914 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
915
916 /* reset the Rx prefetch unit */
917 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
918}
793b883e 919
d571b694 920/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 921static void sky2_rx_clean(struct sky2_port *sky2)
922{
923 unsigned i;
924
925 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 926 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 927 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 928
929 if (re->skb) {
14d0263f 930 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 931 kfree_skb(re->skb);
932 re->skb = NULL;
933 }
934 }
935}
936
ef743d33
SH		 937/* Basic MII support */
938static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
939{
940 struct mii_ioctl_data *data = if_mii(ifr);
941 struct sky2_port *sky2 = netdev_priv(dev);
942 struct sky2_hw *hw = sky2->hw;
943 int err = -EOPNOTSUPP;
944
945 if (!netif_running(dev))
946 return -ENODEV; /* Phy still in reset */
947
d89e1343 948 switch (cmd) {
ef743d33
SH		 949 case SIOCGMIIPHY:
950 data->phy_id = PHY_ADDR_MARV;
951
952 /* fallthru */
953 case SIOCGMIIREG: {
954 u16 val = 0;
91c86df5 955
e07b1aa8 956 spin_lock_bh(&sky2->phy_lock);
ef743d33 957 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 958 spin_unlock_bh(&sky2->phy_lock);
91c86df5 959
ef743d33
SH		 960 data->val_out = val;
961 break;
962 }
963
964 case SIOCSMIIREG:
965 if (!capable(CAP_NET_ADMIN))
966 return -EPERM;
967
e07b1aa8 968 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 969 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
970 data->val_in);
e07b1aa8 971 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 972 break;
973 }
974 return err;
975}
976
d1f13708
SH		 977#ifdef SKY2_VLAN_TAG_USED
978static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
979{
980 struct sky2_port *sky2 = netdev_priv(dev);
981 struct sky2_hw *hw = sky2->hw;
982 u16 port = sky2->port;
d1f13708 983
2bb8c262 984 netif_tx_lock_bh(dev);
d1f13708
SH		 985
986 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
987 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
988 sky2->vlgrp = grp;
989
2bb8c262 990 netif_tx_unlock_bh(dev);
d1f13708
SH		 991}
992
993static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
994{
995 struct sky2_port *sky2 = netdev_priv(dev);
996 struct sky2_hw *hw = sky2->hw;
997 u16 port = sky2->port;
d1f13708 998
2bb8c262 999 netif_tx_lock_bh(dev);
d1f13708
SH		 1000
1001 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1002 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1003 if (sky2->vlgrp)
1004 sky2->vlgrp->vlan_devices[vid] = NULL;
1005
2bb8c262 1006 netif_tx_unlock_bh(dev);
d1f13708
SH		 1007}
1008#endif
1009
82788c7a 1010/*
14d0263f
SH		 1011 * Allocate an skb for receiving. If the MTU is large enough
1012 * make the skb non-linear with a fragment list of pages.
1013 *
82788c7a
SH		 1014 * It appears the hardware has a bug in the FIFO logic that
1015 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1016 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1017 * aligned except if slab debugging is enabled.
82788c7a 1018 */
14d0263f 1019static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1020{
1021 struct sk_buff *skb;
14d0263f
SH		 1022 unsigned long p;
1023 int i;
82788c7a 1024
14d0263f
SH		 1025 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1026 if (!skb)
1027 goto nomem;
1028
1029 p = (unsigned long) skb->data;
1030 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1031
1032 for (i = 0; i < sky2->rx_nfrags; i++) {
1033 struct page *page = alloc_page(GFP_ATOMIC);
1034
1035 if (!page)
1036 goto free_partial;
1037 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1038 }
1039
1040 return skb;
14d0263f
SH		 1041free_partial:
1042 kfree_skb(skb);
1043nomem:
1044 return NULL;
82788c7a
SH		 1045}
1046
cd28ab6a
SH		 1047/*
1048 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1049 * Normal case this ends up creating one list element for skb
1050 * in the receive ring. Worst case if using large MTU and each
1051 * allocation falls on a different 64 bit region, that results
1052 * in 6 list elements per ring entry.
1053 * One element is used for checksum enable/disable, and one
1054 * extra to avoid wrap.
cd28ab6a 1055 */
6b1a3aef 1056static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1057{
6b1a3aef 1058 struct sky2_hw *hw = sky2->hw;
14d0263f 1059 struct rx_ring_info *re;
6b1a3aef 1060 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1061 unsigned i, size, space, thresh;
cd28ab6a 1062
6b1a3aef 1063 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1064 sky2_qset(hw, rxq);
977bdf06 1065
c3905bc4
SH		 1066 /* On PCI express lowering the watermark gives better performance */
1067 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1068 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1069
1070 /* These chips have no ram buffer?
1071 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1072 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1073 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1074 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1075 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1076
6b1a3aef
SH		 1077 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1078
1079 rx_set_checksum(sky2);
14d0263f
SH		 1080
1081 /* Space needed for frame data + headers rounded up */
1082 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1083 + 8;
1084
1085 /* Stopping point for hardware truncation */
1086 thresh = (size - 8) / sizeof(u32);
1087
1088 /* Account for overhead of skb - to avoid order > 0 allocation */
1089 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1090 + sizeof(struct skb_shared_info);
1091
1092 sky2->rx_nfrags = space >> PAGE_SHIFT;
1093 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1094
1095 if (sky2->rx_nfrags != 0) {
1096 /* Compute residue after pages */
1097 space = sky2->rx_nfrags << PAGE_SHIFT;
1098
1099 if (space < size)
1100 size -= space;
1101 else
1102 size = 0;
1103
1104 /* Optimize to handle small packets and headers */
1105 if (size < copybreak)
1106 size = copybreak;
1107 if (size < ETH_HLEN)
1108 size = ETH_HLEN;
1109 }
1110 sky2->rx_data_size = size;
1111
1112 /* Fill Rx ring */
793b883e 1113 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1114 re = sky2->rx_ring + i;
cd28ab6a 1115
14d0263f 1116 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1117 if (!re->skb)
1118 goto nomem;
1119
14d0263f
SH		 1120 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1121 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1122 }
1123
a1433ac4
SH		 1124 /*
1125 * The receiver hangs if it receives frames larger than the
1126 * packet buffer. As a workaround, truncate oversize frames, but
1127 * the register is limited to 9 bits, so if you do frames > 2052
1128 * you better get the MTU right!
1129 */
a1433ac4
SH		 1130 if (thresh > 0x1ff)
1131 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1132 else {
1133 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1134 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1135 }
1136
6b1a3aef
SH		 1137 /* Tell chip about available buffers */
1138 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1139 return 0;
1140nomem:
1141 sky2_rx_clean(sky2);
1142 return -ENOMEM;
1143}
1144
1145/* Bring up network interface. */
1146static int sky2_up(struct net_device *dev)
1147{
1148 struct sky2_port *sky2 = netdev_priv(dev);
1149 struct sky2_hw *hw = sky2->hw;
1150 unsigned port = sky2->port;
67712901 1151 u32 ramsize, imask;
ee7abb04 1152 int cap, err = -ENOMEM;
843a46f4 1153 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1154
ee7abb04
SH		 1155 /*
1156 * On dual port PCI-X card, there is an problem where status
1157 * can be received out of order due to split transactions
843a46f4 1158 */
ee7abb04
SH		 1159 if (otherdev && netif_running(otherdev) &&
1160 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1161 struct sky2_port *osky2 = netdev_priv(otherdev);
1162 u16 cmd;
1163
1164 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1165 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1166 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1167
1168 sky2->rx_csum = 0;
1169 osky2->rx_csum = 0;
1170 }
843a46f4 1171
cd28ab6a
SH		 1172 if (netif_msg_ifup(sky2))
1173 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1174
1175 /* must be power of 2 */
1176 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1177 TX_RING_SIZE *
1178 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1179 &sky2->tx_le_map);
1180 if (!sky2->tx_le)
1181 goto err_out;
1182
6cdbbdf3 1183 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1184 GFP_KERNEL);
1185 if (!sky2->tx_ring)
1186 goto err_out;
1187 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1188
1189 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1190 &sky2->rx_le_map);
1191 if (!sky2->rx_le)
1192 goto err_out;
1193 memset(sky2->rx_le, 0, RX_LE_BYTES);
1194
291ea614 1195 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1196 GFP_KERNEL);
1197 if (!sky2->rx_ring)
1198 goto err_out;
1199
d3bcfbeb
SH		 1200 sky2_phy_power(hw, port, 1);
1201
cd28ab6a
SH		 1202 sky2_mac_init(hw, port);
1203
67712901
SH		 1204 /* Register is number of 4K blocks on internal RAM buffer. */
1205 ramsize = sky2_read8(hw, B2_E_0) * 4;
1206 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1207
67712901
SH		 1208 if (ramsize > 0) {
1209 u32 rxspace;
cd28ab6a 1210
67712901
SH		 1211 if (ramsize < 16)
1212 rxspace = ramsize / 2;
1213 else
1214 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1215
67712901
SH		 1216 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1217 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1218
1219 /* Make sure SyncQ is disabled */
1220 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1221 RB_RST_SET);
1222 }
793b883e 1223
af4ed7e6 1224 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1225
977bdf06 1226 /* Set almost empty threshold */
c2716fb4
SH		 1227 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1228 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1229 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1230
6b1a3aef
SH		 1231 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1232 TX_RING_SIZE - 1);
cd28ab6a 1233
6b1a3aef 1234 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1235 if (err)
1236 goto err_out;
1237
cd28ab6a 1238 /* Enable interrupts from phy/mac for port */
e07b1aa8 1239 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1240 imask |= portirq_msk[port];
e07b1aa8
SH		 1241 sky2_write32(hw, B0_IMSK, imask);
1242
cd28ab6a
SH		 1243 return 0;
1244
1245err_out:
1b537565 1246 if (sky2->rx_le) {
cd28ab6a
SH		 1247 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1248 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1249 sky2->rx_le = NULL;
1250 }
1251 if (sky2->tx_le) {
cd28ab6a
SH		 1252 pci_free_consistent(hw->pdev,
1253 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1254 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1255 sky2->tx_le = NULL;
1256 }
1257 kfree(sky2->tx_ring);
1258 kfree(sky2->rx_ring);
cd28ab6a 1259
1b537565
SH		 1260 sky2->tx_ring = NULL;
1261 sky2->rx_ring = NULL;
cd28ab6a
SH		 1262 return err;
1263}
1264
793b883e
SH		 1265/* Modular subtraction in ring */
1266static inline int tx_dist(unsigned tail, unsigned head)
1267{
cb5d9547 1268 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1269}
cd28ab6a 1270
793b883e
SH		 1271/* Number of list elements available for next tx */
1272static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1273{
793b883e 1274 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1275}
1276
793b883e 1277/* Estimate of number of transmit list elements required */
28bd181a 1278static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1279{
793b883e
SH		 1280 unsigned count;
1281
1282 count = sizeof(dma_addr_t) / sizeof(u32);
1283 count += skb_shinfo(skb)->nr_frags * count;
1284
89114afd 1285 if (skb_is_gso(skb))
793b883e
SH		 1286 ++count;
1287
84fa7933 1288 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1289 ++count;
1290
1291 return count;
cd28ab6a
SH		 1292}
1293
793b883e
SH		 1294/*
1295 * Put one packet in ring for transmit.
1296 * A single packet can generate multiple list elements, and
1297 * the number of ring elements will probably be less than the number
1298 * of list elements used.
1299 */
cd28ab6a
SH		 1300static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1301{
1302 struct sky2_port *sky2 = netdev_priv(dev);
1303 struct sky2_hw *hw = sky2->hw;
d1f13708 1304 struct sky2_tx_le *le = NULL;
6cdbbdf3 1305 struct tx_ring_info *re;
cd28ab6a
SH		 1306 unsigned i, len;
1307 dma_addr_t mapping;
1308 u32 addr64;
1309 u16 mss;
1310 u8 ctrl;
1311
2bb8c262
SH		 1312 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1313 return NETDEV_TX_BUSY;
cd28ab6a 1314
793b883e 1315 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1316 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1317 dev->name, sky2->tx_prod, skb->len);
1318
cd28ab6a
SH		 1319 len = skb_headlen(skb);
1320 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1321 addr64 = high32(mapping);
793b883e 1322
a018e330
SH		 1323 /* Send high bits if changed or crosses boundary */
1324 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1325 le = get_tx_le(sky2);
f65b138c 1326 le->addr = cpu_to_le32(addr64);
793b883e 1327 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1328 sky2->tx_addr64 = high32(mapping + len);
793b883e 1329 }
cd28ab6a
SH		 1330
1331 /* Check for TCP Segmentation Offload */
7967168c 1332 mss = skb_shinfo(skb)->gso_size;
793b883e 1333 if (mss != 0) {
cd28ab6a
SH		 1334 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1335 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1336 mss += ETH_HLEN;
1337
e07560cd
SH		 1338 if (mss != sky2->tx_last_mss) {
1339 le = get_tx_le(sky2);
f65b138c 1340 le->addr = cpu_to_le32(mss);
e07560cd 1341 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1342 sky2->tx_last_mss = mss;
1343 }
cd28ab6a
SH		 1344 }
1345
cd28ab6a 1346 ctrl = 0;
d1f13708
SH		 1347#ifdef SKY2_VLAN_TAG_USED
1348 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1349 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1350 if (!le) {
1351 le = get_tx_le(sky2);
f65b138c 1352 le->addr = 0;
d1f13708 1353 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1354 } else
1355 le->opcode |= OP_VLAN;
1356 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1357 ctrl |= INS_VLAN;
1358 }
1359#endif
1360
1361 /* Handle TCP checksum offload */
84fa7933 1362 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1363 unsigned offset = skb->h.raw - skb->data;
1364 u32 tcpsum;
1365
1366 tcpsum = offset << 16; /* sum start */
ff1dcadb 1367 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1368
1369 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1370 if (skb->nh.iph->protocol == IPPROTO_UDP)
1371 ctrl |= UDPTCP;
1372
f65b138c
SH		 1373 if (tcpsum != sky2->tx_tcpsum) {
1374 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1375
1376 le = get_tx_le(sky2);
f65b138c 1377 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1378 le->length = 0; /* initial checksum value */
1379 le->ctrl = 1; /* one packet */
1380 le->opcode = OP_TCPLISW | HW_OWNER;
1381 }
cd28ab6a
SH		 1382 }
1383
1384 le = get_tx_le(sky2);
f65b138c 1385 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1386 le->length = cpu_to_le16(len);
1387 le->ctrl = ctrl;
793b883e 1388 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1389
291ea614 1390 re = tx_le_re(sky2, le);
cd28ab6a 1391 re->skb = skb;
6cdbbdf3 1392 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1393 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1394
1395 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1396 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1397
1398 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1399 frag->size, PCI_DMA_TODEVICE);
a036119f 1400 addr64 = high32(mapping);
793b883e
SH		 1401 if (addr64 != sky2->tx_addr64) {
1402 le = get_tx_le(sky2);
f65b138c 1403 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1404 le->ctrl = 0;
1405 le->opcode = OP_ADDR64 | HW_OWNER;
1406 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1407 }
1408
1409 le = get_tx_le(sky2);
f65b138c 1410 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1411 le->length = cpu_to_le16(frag->size);
1412 le->ctrl = ctrl;
793b883e 1413 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1414
291ea614
SH		 1415 re = tx_le_re(sky2, le);
1416 re->skb = skb;
1417 pci_unmap_addr_set(re, mapaddr, mapping);
1418 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1419 }
6cdbbdf3 1420
cd28ab6a
SH		 1421 le->ctrl |= EOP;
1422
97bda706
SH		 1423 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1424 netif_stop_queue(dev);
b19666d9 1425
290d4de5 1426 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1427
cd28ab6a
SH		 1428 dev->trans_start = jiffies;
1429 return NETDEV_TX_OK;
1430}
1431
cd28ab6a 1432/*
793b883e
SH		 1433 * Free ring elements from starting at tx_cons until "done"
1434 *
1435 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1436 * buffers so make sure not to free skb to early.
cd28ab6a 1437 */
d11c13e7 1438static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1439{
d11c13e7 1440 struct net_device *dev = sky2->netdev;
af2a58ac 1441 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1442 unsigned idx;
cd28ab6a 1443
0e3ff6aa 1444 BUG_ON(done >= TX_RING_SIZE);
2224795d 1445
291ea614
SH		 1446 for (idx = sky2->tx_cons; idx != done;
1447 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1448 struct sky2_tx_le *le = sky2->tx_le + idx;
1449 struct tx_ring_info *re = sky2->tx_ring + idx;
1450
1451 switch(le->opcode & ~HW_OWNER) {
1452 case OP_LARGESEND:
1453 case OP_PACKET:
1454 pci_unmap_single(pdev,
1455 pci_unmap_addr(re, mapaddr),
1456 pci_unmap_len(re, maplen),
1457 PCI_DMA_TODEVICE);
af2a58ac 1458 break;
291ea614
SH		 1459 case OP_BUFFER:
1460 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1461 pci_unmap_len(re, maplen),
734d1868 1462 PCI_DMA_TODEVICE);
291ea614
SH		 1463 break;
1464 }
1465
1466 if (le->ctrl & EOP) {
1467 if (unlikely(netif_msg_tx_done(sky2)))
1468 printk(KERN_DEBUG "%s: tx done %u\n",
1469 dev->name, idx);
794b2bd2 1470 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1471 }
1472
291ea614 1473 le->opcode = 0; /* paranoia */
793b883e 1474 }
793b883e 1475
291ea614 1476 sky2->tx_cons = idx;
22e11703 1477 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1478 netif_wake_queue(dev);
cd28ab6a
SH		 1479}
1480
1481/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1482static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1483{
2bb8c262
SH		 1484 struct sky2_port *sky2 = netdev_priv(dev);
1485
1486 netif_tx_lock_bh(dev);
d11c13e7 1487 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1488 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1489}
1490
1491/* Network shutdown */
1492static int sky2_down(struct net_device *dev)
1493{
1494 struct sky2_port *sky2 = netdev_priv(dev);
1495 struct sky2_hw *hw = sky2->hw;
1496 unsigned port = sky2->port;
1497 u16 ctrl;
e07b1aa8 1498 u32 imask;
cd28ab6a 1499
1b537565
SH		 1500 /* Never really got started! */
1501 if (!sky2->tx_le)
1502 return 0;
1503
cd28ab6a
SH		 1504 if (netif_msg_ifdown(sky2))
1505 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1506
018d1c66 1507 /* Stop more packets from being queued */
cd28ab6a
SH		 1508 netif_stop_queue(dev);
1509
ebc646f6
SH		 1510 /* Disable port IRQ */
1511 imask = sky2_read32(hw, B0_IMSK);
1512 imask &= ~portirq_msk[port];
1513 sky2_write32(hw, B0_IMSK, imask);
1514
25d82d7a
SH		 1515 /*
1516 * Both ports share the NAPI poll on port 0, so if necessary undo the
1517 * the disable that is done in dev_close.
1518 */
1519 if (sky2->port == 0 && hw->ports > 1)
1520 netif_poll_enable(dev);
1521
d3bcfbeb 1522 sky2_gmac_reset(hw, port);
793b883e 1523
cd28ab6a
SH		 1524 /* Stop transmitter */
1525 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1526 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1527
1528 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1529 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1530
c2716fb4
SH		 1531 /* WA for dev. #4.209 */
1532 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1533 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1534 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1535 sky2->speed != SPEED_1000 ?
1536 TX_STFW_ENA : TX_STFW_DIS);
1537
cd28ab6a 1538 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1539 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1540 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1541
1542 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1543
1544 /* Workaround shared GMAC reset */
793b883e
SH		 1545 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1546 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1547 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1548
1549 /* Disable Force Sync bit and Enable Alloc bit */
1550 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1551 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1552
1553 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1554 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1555 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1556
1557 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1558 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1559 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1560
1561 /* Reset the Tx prefetch units */
1562 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1563 PREF_UNIT_RST_SET);
1564
1565 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1566
6b1a3aef 1567 sky2_rx_stop(sky2);
cd28ab6a
SH		 1568
1569 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1570 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1571
d3bcfbeb
SH		 1572 sky2_phy_power(hw, port, 0);
1573
d571b694 1574 /* turn off LED's */
cd28ab6a
SH		 1575 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1576
018d1c66
SH		 1577 synchronize_irq(hw->pdev->irq);
1578
2bb8c262 1579 sky2_tx_clean(dev);
cd28ab6a
SH		 1580 sky2_rx_clean(sky2);
1581
1582 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1583 sky2->rx_le, sky2->rx_le_map);
1584 kfree(sky2->rx_ring);
1585
1586 pci_free_consistent(hw->pdev,
1587 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1588 sky2->tx_le, sky2->tx_le_map);
1589 kfree(sky2->tx_ring);
1590
1b537565
SH		 1591 sky2->tx_le = NULL;
1592 sky2->rx_le = NULL;
1593
1594 sky2->rx_ring = NULL;
1595 sky2->tx_ring = NULL;
1596
cd28ab6a
SH		 1597 return 0;
1598}
1599
1600static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1601{
b89165f2 1602 if (!sky2_is_copper(hw))
793b883e
SH		 1603 return SPEED_1000;
1604
cd28ab6a
SH		 1605 if (hw->chip_id == CHIP_ID_YUKON_FE)
1606 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1607
1608 switch (aux & PHY_M_PS_SPEED_MSK) {
1609 case PHY_M_PS_SPEED_1000:
1610 return SPEED_1000;
1611 case PHY_M_PS_SPEED_100:
1612 return SPEED_100;
1613 default:
1614 return SPEED_10;
1615 }
1616}
1617
1618static void sky2_link_up(struct sky2_port *sky2)
1619{
1620 struct sky2_hw *hw = sky2->hw;
1621 unsigned port = sky2->port;
1622 u16 reg;
16ad91e1
SH		 1623 static const char *fc_name[] = {
1624 [FC_NONE] = "none",
1625 [FC_TX] = "tx",
1626 [FC_RX] = "rx",
1627 [FC_BOTH] = "both",
1628 };
cd28ab6a 1629
cd28ab6a 1630 /* enable Rx/Tx */
2eaba1a2 1631 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1632 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1633 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1634
1635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1636
1637 netif_carrier_on(sky2->netdev);
1638 netif_wake_queue(sky2->netdev);
1639
1640 /* Turn on link LED */
793b883e 1641 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1642 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1643
ed6d32c7 1644 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1645 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1646 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1647
1648 switch(sky2->speed) {
1649 case SPEED_10:
1650 led |= PHY_M_LEDC_INIT_CTRL(7);
1651 break;
1652
1653 case SPEED_100:
1654 led |= PHY_M_LEDC_STA1_CTRL(7);
1655 break;
1656
1657 case SPEED_1000:
1658 led |= PHY_M_LEDC_STA0_CTRL(7);
1659 break;
1660 }
793b883e
SH		 1661
1662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1663 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1664 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1665 }
1666
cd28ab6a
SH		 1667 if (netif_msg_link(sky2))
1668 printk(KERN_INFO PFX
d571b694 1669 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1670 sky2->netdev->name, sky2->speed,
1671 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1672 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1673}
1674
1675static void sky2_link_down(struct sky2_port *sky2)
1676{
1677 struct sky2_hw *hw = sky2->hw;
1678 unsigned port = sky2->port;
1679 u16 reg;
1680
1681 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1682
1683 reg = gma_read16(hw, port, GM_GP_CTRL);
1684 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1685 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1686
16ad91e1 1687 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1688 /* restore Asymmetric Pause bit */
1689 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1690 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1691 | PHY_M_AN_ASP);
cd28ab6a
SH		 1692 }
1693
cd28ab6a
SH		 1694 netif_carrier_off(sky2->netdev);
1695 netif_stop_queue(sky2->netdev);
1696
1697 /* Turn on link LED */
1698 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1699
1700 if (netif_msg_link(sky2))
1701 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1702
cd28ab6a
SH		 1703 sky2_phy_init(hw, port);
1704}
1705
16ad91e1
SH		 1706static enum flow_control sky2_flow(int rx, int tx)
1707{
1708 if (rx)
1709 return tx ? FC_BOTH : FC_RX;
1710 else
1711 return tx ? FC_TX : FC_NONE;
1712}
1713
793b883e
SH		 1714static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1715{
1716 struct sky2_hw *hw = sky2->hw;
1717 unsigned port = sky2->port;
1718 u16 lpa;
1719
1720 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1721
1722 if (lpa & PHY_M_AN_RF) {
1723 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1724 return -1;
1725 }
1726
793b883e
SH		 1727 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1728 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1729 sky2->netdev->name);
1730 return -1;
1731 }
1732
793b883e 1733 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1734 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1735
1736 /* Pause bits are offset (9..8) */
ed6d32c7 1737 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1738 aux >>= 6;
1739
16ad91e1
SH		 1740 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1741 aux & PHY_M_PS_TX_P_EN);
793b883e 1742
16ad91e1 1743 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1744 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1745 sky2->flow_status = FC_NONE;
2eaba1a2 1746
16ad91e1 1747 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1748 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1749 else
1750 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1751
1752 return 0;
1753}
cd28ab6a 1754
e07b1aa8
SH		 1755/* Interrupt from PHY */
1756static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1757{
e07b1aa8
SH		 1758 struct net_device *dev = hw->dev[port];
1759 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1760 u16 istatus, phystat;
1761
ebc646f6
SH		 1762 if (!netif_running(dev))
1763 return;
1764
e07b1aa8
SH		 1765 spin_lock(&sky2->phy_lock);
1766 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1767 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1768
cd28ab6a
SH		 1769 if (netif_msg_intr(sky2))
1770 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1771 sky2->netdev->name, istatus, phystat);
1772
2eaba1a2 1773 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1774 if (sky2_autoneg_done(sky2, phystat) == 0)
1775 sky2_link_up(sky2);
1776 goto out;
1777 }
cd28ab6a 1778
793b883e
SH		 1779 if (istatus & PHY_M_IS_LSP_CHANGE)
1780 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1781
793b883e
SH		 1782 if (istatus & PHY_M_IS_DUP_CHANGE)
1783 sky2->duplex =
1784 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1785
793b883e
SH		 1786 if (istatus & PHY_M_IS_LST_CHANGE) {
1787 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1788 sky2_link_up(sky2);
793b883e
SH		 1789 else
1790 sky2_link_down(sky2);
cd28ab6a 1791 }
793b883e 1792out:
e07b1aa8 1793 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1794}
1795
302d1252
SH		 1796
1797/* Transmit timeout is only called if we are running, carries is up
1798 * and tx queue is full (stopped).
1799 */
cd28ab6a
SH		 1800static void sky2_tx_timeout(struct net_device *dev)
1801{
1802 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1803 struct sky2_hw *hw = sky2->hw;
1804 unsigned txq = txqaddr[sky2->port];
8f24664d 1805 u16 report, done;
cd28ab6a
SH		 1806
1807 if (netif_msg_timer(sky2))
1808 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1809
8f24664d
SH		 1810 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1811 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1812
8f24664d
SH		 1813 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1814 dev->name,
1815 sky2->tx_cons, sky2->tx_prod, report, done);
1816
1817 if (report != done) {
1818 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1819
1820 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1821 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1822 } else if (report != sky2->tx_cons) {
1823 printk(KERN_INFO PFX "status report lost?\n");
1824
2bb8c262 1825 netif_tx_lock_bh(dev);
8f24664d 1826 sky2_tx_complete(sky2, report);
2bb8c262 1827 netif_tx_unlock_bh(dev);
8f24664d
SH		 1828 } else {
1829 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1830
8f24664d
SH		 1831 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1832 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1833
2bb8c262 1834 sky2_tx_clean(dev);
8f24664d
SH		 1835
1836 sky2_qset(hw, txq);
1837 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1838 }
cd28ab6a
SH		 1839}
1840
1841static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1842{
6b1a3aef
SH		 1843 struct sky2_port *sky2 = netdev_priv(dev);
1844 struct sky2_hw *hw = sky2->hw;
1845 int err;
1846 u16 ctl, mode;
e07b1aa8 1847 u32 imask;
cd28ab6a
SH		 1848
1849 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1850 return -EINVAL;
1851
5a5b1ea0
SH		 1852 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1853 return -EINVAL;
1854
6b1a3aef
SH		 1855 if (!netif_running(dev)) {
1856 dev->mtu = new_mtu;
1857 return 0;
1858 }
1859
e07b1aa8 1860 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1861 sky2_write32(hw, B0_IMSK, 0);
1862
018d1c66
SH		 1863 dev->trans_start = jiffies; /* prevent tx timeout */
1864 netif_stop_queue(dev);
1865 netif_poll_disable(hw->dev[0]);
1866
e07b1aa8
SH		 1867 synchronize_irq(hw->pdev->irq);
1868
6b1a3aef
SH		 1869 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1870 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1871 sky2_rx_stop(sky2);
1872 sky2_rx_clean(sky2);
cd28ab6a
SH		 1873
1874 dev->mtu = new_mtu;
14d0263f 1875
6b1a3aef
SH		 1876 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1877 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1878
1879 if (dev->mtu > ETH_DATA_LEN)
1880 mode |= GM_SMOD_JUMBO_ENA;
1881
1882 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1883
6b1a3aef 1884 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1885
6b1a3aef 1886 err = sky2_rx_start(sky2);
e07b1aa8 1887 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1888
1b537565
SH		 1889 if (err)
1890 dev_close(dev);
1891 else {
1892 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1893
1894 netif_poll_enable(hw->dev[0]);
1895 netif_wake_queue(dev);
1896 }
1897
cd28ab6a
SH		 1898 return err;
1899}
1900
14d0263f
SH		 1901/* For small just reuse existing skb for next receive */
1902static struct sk_buff *receive_copy(struct sky2_port *sky2,
1903 const struct rx_ring_info *re,
1904 unsigned length)
1905{
1906 struct sk_buff *skb;
1907
1908 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1909 if (likely(skb)) {
1910 skb_reserve(skb, 2);
1911 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1912 length, PCI_DMA_FROMDEVICE);
1913 memcpy(skb->data, re->skb->data, length);
1914 skb->ip_summed = re->skb->ip_summed;
1915 skb->csum = re->skb->csum;
1916 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1917 length, PCI_DMA_FROMDEVICE);
1918 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1919 skb_put(skb, length);
14d0263f
SH		 1920 }
1921 return skb;
1922}
1923
1924/* Adjust length of skb with fragments to match received data */
1925static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1926 unsigned int length)
1927{
1928 int i, num_frags;
1929 unsigned int size;
1930
1931 /* put header into skb */
1932 size = min(length, hdr_space);
1933 skb->tail += size;
1934 skb->len += size;
1935 length -= size;
1936
1937 num_frags = skb_shinfo(skb)->nr_frags;
1938 for (i = 0; i < num_frags; i++) {
1939 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1940
1941 if (length == 0) {
1942 /* don't need this page */
1943 __free_page(frag->page);
1944 --skb_shinfo(skb)->nr_frags;
1945 } else {
1946 size = min(length, (unsigned) PAGE_SIZE);
1947
1948 frag->size = size;
1949 skb->data_len += size;
1950 skb->truesize += size;
1951 skb->len += size;
1952 length -= size;
1953 }
1954 }
1955}
1956
1957/* Normal packet - take skb from ring element and put in a new one */
1958static struct sk_buff *receive_new(struct sky2_port *sky2,
1959 struct rx_ring_info *re,
1960 unsigned int length)
1961{
1962 struct sk_buff *skb, *nskb;
1963 unsigned hdr_space = sky2->rx_data_size;
1964
1965 pr_debug(PFX "receive new length=%d\n", length);
1966
1967 /* Don't be tricky about reusing pages (yet) */
1968 nskb = sky2_rx_alloc(sky2);
1969 if (unlikely(!nskb))
1970 return NULL;
1971
1972 skb = re->skb;
1973 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1974
1975 prefetch(skb->data);
1976 re->skb = nskb;
1977 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1978
1979 if (skb_shinfo(skb)->nr_frags)
1980 skb_put_frags(skb, hdr_space, length);
1981 else
489b10c1 1982 skb_put(skb, length);
14d0263f
SH		 1983 return skb;
1984}
1985
cd28ab6a
SH		 1986/*
1987 * Receive one packet.
d571b694 1988 * For larger packets, get new buffer.
cd28ab6a 1989 */
497d7c86 1990static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1991 u16 length, u32 status)
1992{
497d7c86 1993 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1994 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1995 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1996
1997 if (unlikely(netif_msg_rx_status(sky2)))
1998 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1999 dev->name, sky2->rx_next, status, length);
cd28ab6a 2000
793b883e 2001 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2002 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2003
42eeea01 2004 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2005 goto error;
2006
42eeea01
SH		 2007 if (!(status & GMR_FS_RX_OK))
2008 goto resubmit;
2009
497d7c86 2010 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2011 goto oversize;
2012
14d0263f
SH		 2013 if (length < copybreak)
2014 skb = receive_copy(sky2, re, length);
2015 else
2016 skb = receive_new(sky2, re, length);
793b883e 2017resubmit:
14d0263f 2018 sky2_rx_submit(sky2, re);
79e57d32 2019
cd28ab6a
SH		 2020 return skb;
2021
6e15b712
SH		 2022oversize:
2023 ++sky2->net_stats.rx_over_errors;
2024 goto resubmit;
2025
cd28ab6a 2026error:
6e15b712 2027 ++sky2->net_stats.rx_errors;
b6d77734
SH		 2028 if (status & GMR_FS_RX_FF_OV) {
2029 sky2->net_stats.rx_fifo_errors++;
2030 goto resubmit;
2031 }
6e15b712 2032
3be92a70 2033 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2034 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2035 dev->name, status, length);
793b883e
SH		 2036
2037 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2038 sky2->net_stats.rx_length_errors++;
2039 if (status & GMR_FS_FRAGMENT)
2040 sky2->net_stats.rx_frame_errors++;
2041 if (status & GMR_FS_CRC_ERR)
2042 sky2->net_stats.rx_crc_errors++;
79e57d32 2043
793b883e 2044 goto resubmit;
cd28ab6a
SH		 2045}
2046
e07b1aa8
SH		 2047/* Transmit complete */
2048static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2049{
e07b1aa8 2050 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2051
e07b1aa8 2052 if (netif_running(dev)) {
2bb8c262 2053 netif_tx_lock(dev);
e07b1aa8 2054 sky2_tx_complete(sky2, last);
2bb8c262 2055 netif_tx_unlock(dev);
2224795d 2056 }
cd28ab6a
SH		 2057}
2058
e07b1aa8
SH		 2059/* Process status response ring */
2060static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2061{
22e11703 2062 struct sky2_port *sky2;
e07b1aa8 2063 int work_done = 0;
22e11703 2064 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2065 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2066
af2a58ac 2067 rmb();
bea86103 2068
e71ebd73 2069 while (hw->st_idx != hwidx) {
13210ce5
SH		 2070 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2071 struct net_device *dev;
cd28ab6a 2072 struct sk_buff *skb;
cd28ab6a
SH		 2073 u32 status;
2074 u16 length;
2075
cb5d9547 2076 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2077
e71ebd73
SH		 2078 BUG_ON(le->link >= 2);
2079 dev = hw->dev[le->link];
13210ce5
SH		 2080
2081 sky2 = netdev_priv(dev);
f65b138c
SH		 2082 length = le16_to_cpu(le->length);
2083 status = le32_to_cpu(le->status);
cd28ab6a 2084
e71ebd73 2085 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2086 case OP_RXSTAT:
497d7c86 2087 skb = sky2_receive(dev, length, status);
d1f13708 2088 if (!skb)
5df79111 2089 goto force_update;
13210ce5 2090
13210ce5
SH		 2091 skb->protocol = eth_type_trans(skb, dev);
2092 dev->last_rx = jiffies;
2093
d1f13708
SH		 2094#ifdef SKY2_VLAN_TAG_USED
2095 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2096 vlan_hwaccel_receive_skb(skb,
2097 sky2->vlgrp,
2098 be16_to_cpu(sky2->rx_tag));
2099 } else
2100#endif
cd28ab6a 2101 netif_receive_skb(skb);
13210ce5 2102
22e11703
SH		 2103 /* Update receiver after 16 frames */
2104 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2105force_update:
2106 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2107 buf_write[le->link] = 0;
2108 }
2109
2110 /* Stop after net poll weight */
13210ce5
SH		 2111 if (++work_done >= to_do)
2112 goto exit_loop;
cd28ab6a
SH		 2113 break;
2114
d1f13708
SH		 2115#ifdef SKY2_VLAN_TAG_USED
2116 case OP_RXVLAN:
2117 sky2->rx_tag = length;
2118 break;
2119
2120 case OP_RXCHKSVLAN:
2121 sky2->rx_tag = length;
2122 /* fall through */
2123#endif
cd28ab6a 2124 case OP_RXCHKS:
d11c13e7 2125 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2126 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2127 skb->csum = status & 0xffff;
cd28ab6a
SH		 2128 break;
2129
2130 case OP_TXINDEXLE:
13b97b74 2131 /* TX index reports status for both ports */
f55925d7
SH		 2132 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2133 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2134 if (hw->dev[1])
2135 sky2_tx_done(hw->dev[1],
2136 ((status >> 24) & 0xff)
2137 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2138 break;
2139
cd28ab6a
SH		 2140 default:
2141 if (net_ratelimit())
793b883e 2142 printk(KERN_WARNING PFX
e71ebd73
SH		 2143 "unknown status opcode 0x%x\n", le->opcode);
2144 goto exit_loop;
cd28ab6a 2145 }
13210ce5 2146 }
cd28ab6a 2147
fe2a24df
SH		 2148 /* Fully processed status ring so clear irq */
2149 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2150
13210ce5 2151exit_loop:
22e11703
SH		 2152 if (buf_write[0]) {
2153 sky2 = netdev_priv(hw->dev[0]);
2154 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2155 }
2156
2157 if (buf_write[1]) {
2158 sky2 = netdev_priv(hw->dev[1]);
2159 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2160 }
2161
e07b1aa8 2162 return work_done;
cd28ab6a
SH		 2163}
2164
2165static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2166{
2167 struct net_device *dev = hw->dev[port];
2168
3be92a70
SH		 2169 if (net_ratelimit())
2170 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2171 dev->name, status);
cd28ab6a
SH		 2172
2173 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2174 if (net_ratelimit())
2175 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2176 dev->name);
cd28ab6a
SH		 2177 /* Clear IRQ */
2178 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2179 }
2180
2181 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2182 if (net_ratelimit())
2183 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2184 dev->name);
cd28ab6a
SH		 2185
2186 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2187 }
2188
2189 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2190 if (net_ratelimit())
2191 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2192 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2193 }
2194
2195 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2196 if (net_ratelimit())
2197 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2198 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2199 }
2200
2201 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2202 if (net_ratelimit())
2203 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2204 dev->name);
cd28ab6a
SH		 2205 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2206 }
2207}
2208
2209static void sky2_hw_intr(struct sky2_hw *hw)
2210{
2211 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2212
793b883e 2213 if (status & Y2_IS_TIST_OV)
cd28ab6a 2214 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2215
2216 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2217 u16 pci_err;
2218
56a645cc 2219 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2220 if (net_ratelimit())
2221 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2222 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2223
2224 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2225 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2226 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2227 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2228 }
2229
2230 if (status & Y2_IS_PCI_EXP) {
d571b694 2231 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2232 u32 pex_err;
2233
7bd656d1 2234 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2235
3be92a70
SH		 2236 if (net_ratelimit())
2237 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2238 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2239
2240 /* clear the interrupt */
2241 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2242 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2243 0xffffffffUL);
cd28ab6a
SH		 2244 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2245
7bd656d1 2246 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2247 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2248 hwmsk &= ~Y2_IS_PCI_EXP;
2249 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2250 }
2251 }
2252
2253 if (status & Y2_HWE_L1_MASK)
2254 sky2_hw_error(hw, 0, status);
2255 status >>= 8;
2256 if (status & Y2_HWE_L1_MASK)
2257 sky2_hw_error(hw, 1, status);
2258}
2259
2260static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2261{
2262 struct net_device *dev = hw->dev[port];
2263 struct sky2_port *sky2 = netdev_priv(dev);
2264 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2265
2266 if (netif_msg_intr(sky2))
2267 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2268 dev->name, status);
2269
2270 if (status & GM_IS_RX_FF_OR) {
2271 ++sky2->net_stats.rx_fifo_errors;
2272 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2273 }
2274
2275 if (status & GM_IS_TX_FF_UR) {
2276 ++sky2->net_stats.tx_fifo_errors;
2277 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2278 }
cd28ab6a
SH		 2279}
2280
d257924e
SH		 2281/* This should never happen it is a fatal situation */
2282static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2283 const char *rxtx, u32 mask)
2284{
2285 struct net_device *dev = hw->dev[port];
2286 struct sky2_port *sky2 = netdev_priv(dev);
2287 u32 imask;
2288
2289 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2290 dev ? dev->name : "<not registered>", rxtx);
2291
2292 imask = sky2_read32(hw, B0_IMSK);
2293 imask &= ~mask;
2294 sky2_write32(hw, B0_IMSK, imask);
2295
2296 if (dev) {
2297 spin_lock(&sky2->phy_lock);
2298 sky2_link_down(sky2);
2299 spin_unlock(&sky2->phy_lock);
2300 }
2301}
cd28ab6a 2302
d27ed387
SH		 2303/* If idle then force a fake soft NAPI poll once a second
2304 * to work around cases where sharing an edge triggered interrupt.
2305 */
eb35cf60
SH		 2306static inline void sky2_idle_start(struct sky2_hw *hw)
2307{
2308 if (idle_timeout > 0)
2309 mod_timer(&hw->idle_timer,
2310 jiffies + msecs_to_jiffies(idle_timeout));
2311}
2312
d27ed387
SH		 2313static void sky2_idle(unsigned long arg)
2314{
01bd7564
SH		 2315 struct sky2_hw *hw = (struct sky2_hw *) arg;
2316 struct net_device *dev = hw->dev[0];
d27ed387 2317
d27ed387
SH		 2318 if (__netif_rx_schedule_prep(dev))
2319 __netif_rx_schedule(dev);
01bd7564
SH		 2320
2321 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2322}
2323
2324
e07b1aa8 2325static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2326{
e07b1aa8
SH		 2327 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2328 int work_limit = min(dev0->quota, *budget);
2329 int work_done = 0;
fb2690a9 2330 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2331
1e5f1283
SH		 2332 if (status & Y2_IS_HW_ERR)
2333 sky2_hw_intr(hw);
d257924e 2334
1e5f1283
SH		 2335 if (status & Y2_IS_IRQ_PHY1)
2336 sky2_phy_intr(hw, 0);
cd28ab6a 2337
1e5f1283
SH		 2338 if (status & Y2_IS_IRQ_PHY2)
2339 sky2_phy_intr(hw, 1);
cd28ab6a 2340
1e5f1283
SH		 2341 if (status & Y2_IS_IRQ_MAC1)
2342 sky2_mac_intr(hw, 0);
cd28ab6a 2343
1e5f1283
SH		 2344 if (status & Y2_IS_IRQ_MAC2)
2345 sky2_mac_intr(hw, 1);
cd28ab6a 2346
1e5f1283
SH		 2347 if (status & Y2_IS_CHK_RX1)
2348 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2349
1e5f1283
SH		 2350 if (status & Y2_IS_CHK_RX2)
2351 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2352
1e5f1283
SH		 2353 if (status & Y2_IS_CHK_TXA1)
2354 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2355
1e5f1283
SH		 2356 if (status & Y2_IS_CHK_TXA2)
2357 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2358
1e5f1283 2359 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2360 if (work_done < work_limit) {
2361 netif_rx_complete(dev0);
86fba634 2362
fe2a24df
SH		 2363 sky2_read32(hw, B0_Y2_SP_LISR);
2364 return 0;
2365 } else {
2366 *budget -= work_done;
2367 dev0->quota -= work_done;
1e5f1283 2368 return 1;
fe2a24df 2369 }
e07b1aa8
SH		 2370}
2371
7d12e780 2372static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2373{
2374 struct sky2_hw *hw = dev_id;
2375 struct net_device *dev0 = hw->dev[0];
2376 u32 status;
2377
2378 /* Reading this mask interrupts as side effect */
2379 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2380 if (status == 0 || status == ~0)
2381 return IRQ_NONE;
793b883e 2382
e07b1aa8
SH		 2383 prefetch(&hw->st_le[hw->st_idx]);
2384 if (likely(__netif_rx_schedule_prep(dev0)))
2385 __netif_rx_schedule(dev0);
793b883e 2386
cd28ab6a
SH		 2387 return IRQ_HANDLED;
2388}
2389
2390#ifdef CONFIG_NET_POLL_CONTROLLER
2391static void sky2_netpoll(struct net_device *dev)
2392{
2393 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2394 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2395
88d11360
SH		 2396 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2397 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2398}
2399#endif
2400
2401/* Chip internal frequency for clock calculations */
fb17358f 2402static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2403{
793b883e 2404 switch (hw->chip_id) {
cd28ab6a 2405 case CHIP_ID_YUKON_EC:
5a5b1ea0 2406 case CHIP_ID_YUKON_EC_U:
fb17358f 2407 return 125; /* 125 Mhz */
cd28ab6a 2408 case CHIP_ID_YUKON_FE:
fb17358f 2409 return 100; /* 100 Mhz */
793b883e 2410 default: /* YUKON_XL */
fb17358f 2411 return 156; /* 156 Mhz */
cd28ab6a
SH		 2412 }
2413}
2414
fb17358f 2415static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2416{
fb17358f 2417 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2418}
2419
fb17358f 2420static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2421{
fb17358f 2422 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2423}
2424
fb17358f 2425
59139528 2426static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2427{
cd28ab6a 2428 u16 status;
b89165f2 2429 u8 t8;
56a645cc 2430 int i;
cd28ab6a 2431
cd28ab6a 2432 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2433
cd28ab6a
SH		 2434 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2435 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2436 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2437 pci_name(hw->pdev), hw->chip_id);
2438 return -EOPNOTSUPP;
2439 }
2440
290d4de5
SH		 2441 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2442
2443 /* This rev is really old, and requires untested workarounds */
2444 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2445 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2446 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2447 hw->chip_id, hw->chip_rev);
2448 return -EOPNOTSUPP;
2449 }
2450
cd28ab6a
SH		 2451 /* disable ASF */
2452 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2453 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2454 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2455 }
2456
2457 /* do a SW reset */
2458 sky2_write8(hw, B0_CTST, CS_RST_SET);
2459 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2460
2461 /* clear PCI errors, if any */
56a645cc 2462 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2463
cd28ab6a 2464 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2465 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2466
cd28ab6a
SH		 2467
2468 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2469
2470 /* clear any PEX errors */
7bd656d1
SH		 2471 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2472 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2473
cd28ab6a 2474
b89165f2 2475 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2476 hw->ports = 1;
2477 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2478 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2479 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2480 ++hw->ports;
2481 }
cd28ab6a 2482
5afa0a9c 2483 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2484
2485 for (i = 0; i < hw->ports; i++) {
2486 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2487 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2488 }
2489
2490 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2491
793b883e
SH		 2492 /* Clear I2C IRQ noise */
2493 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2494
2495 /* turn off hardware timer (unused) */
2496 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2497 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2498
cd28ab6a
SH		 2499 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2500
69634ee7
SH		 2501 /* Turn off descriptor polling */
2502 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2503
2504 /* Turn off receive timestamp */
2505 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2506 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2507
2508 /* enable the Tx Arbiters */
2509 for (i = 0; i < hw->ports; i++)
2510 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2511
2512 /* Initialize ram interface */
2513 for (i = 0; i < hw->ports; i++) {
793b883e 2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2515
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2517 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2518 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2519 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2520 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2521 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2522 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2523 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2524 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2525 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2526 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2527 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2528 }
2529
7bd656d1 2530 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2531
cd28ab6a 2532 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2533 sky2_gmac_reset(hw, i);
cd28ab6a 2534
cd28ab6a
SH		 2535 memset(hw->st_le, 0, STATUS_LE_BYTES);
2536 hw->st_idx = 0;
2537
2538 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2539 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2540
2541 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2542 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2543
2544 /* Set the list last index */
793b883e 2545 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2546
290d4de5
SH		 2547 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2548 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2549
290d4de5
SH		 2550 /* set Status-FIFO ISR watermark */
2551 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2552 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2553 else
2554 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2555
290d4de5 2556 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2557 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2558 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2559
793b883e 2560 /* enable status unit */
cd28ab6a
SH		 2561 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2562
2563 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2564 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2565 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2566
2567 return 0;
2568}
2569
28bd181a 2570static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2571{
b89165f2
SH		 2572 if (sky2_is_copper(hw)) {
2573 u32 modes = SUPPORTED_10baseT_Half
2574 | SUPPORTED_10baseT_Full
2575 | SUPPORTED_100baseT_Half
2576 | SUPPORTED_100baseT_Full
2577 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2578
2579 if (hw->chip_id != CHIP_ID_YUKON_FE)
2580 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2581 | SUPPORTED_1000baseT_Full;
2582 return modes;
cd28ab6a 2583 } else
b89165f2
SH		 2584 return SUPPORTED_1000baseT_Half
2585 | SUPPORTED_1000baseT_Full
2586 | SUPPORTED_Autoneg
2587 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2588}
2589
793b883e 2590static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2591{
2592 struct sky2_port *sky2 = netdev_priv(dev);
2593 struct sky2_hw *hw = sky2->hw;
2594
2595 ecmd->transceiver = XCVR_INTERNAL;
2596 ecmd->supported = sky2_supported_modes(hw);
2597 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2598 if (sky2_is_copper(hw)) {
cd28ab6a 2599 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2600 | SUPPORTED_10baseT_Full
2601 | SUPPORTED_100baseT_Half
2602 | SUPPORTED_100baseT_Full
2603 | SUPPORTED_1000baseT_Half
2604 | SUPPORTED_1000baseT_Full
2605 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2606 ecmd->port = PORT_TP;
b89165f2
SH		 2607 ecmd->speed = sky2->speed;
2608 } else {
2609 ecmd->speed = SPEED_1000;
cd28ab6a 2610 ecmd->port = PORT_FIBRE;
b89165f2 2611 }
cd28ab6a
SH		 2612
2613 ecmd->advertising = sky2->advertising;
2614 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2615 ecmd->duplex = sky2->duplex;
2616 return 0;
2617}
2618
2619static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2620{
2621 struct sky2_port *sky2 = netdev_priv(dev);
2622 const struct sky2_hw *hw = sky2->hw;
2623 u32 supported = sky2_supported_modes(hw);
2624
2625 if (ecmd->autoneg == AUTONEG_ENABLE) {
2626 ecmd->advertising = supported;
2627 sky2->duplex = -1;
2628 sky2->speed = -1;
2629 } else {
2630 u32 setting;
2631
793b883e 2632 switch (ecmd->speed) {
cd28ab6a
SH		 2633 case SPEED_1000:
2634 if (ecmd->duplex == DUPLEX_FULL)
2635 setting = SUPPORTED_1000baseT_Full;
2636 else if (ecmd->duplex == DUPLEX_HALF)
2637 setting = SUPPORTED_1000baseT_Half;
2638 else
2639 return -EINVAL;
2640 break;
2641 case SPEED_100:
2642 if (ecmd->duplex == DUPLEX_FULL)
2643 setting = SUPPORTED_100baseT_Full;
2644 else if (ecmd->duplex == DUPLEX_HALF)
2645 setting = SUPPORTED_100baseT_Half;
2646 else
2647 return -EINVAL;
2648 break;
2649
2650 case SPEED_10:
2651 if (ecmd->duplex == DUPLEX_FULL)
2652 setting = SUPPORTED_10baseT_Full;
2653 else if (ecmd->duplex == DUPLEX_HALF)
2654 setting = SUPPORTED_10baseT_Half;
2655 else
2656 return -EINVAL;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661
2662 if ((setting & supported) == 0)
2663 return -EINVAL;
2664
2665 sky2->speed = ecmd->speed;
2666 sky2->duplex = ecmd->duplex;
2667 }
2668
2669 sky2->autoneg = ecmd->autoneg;
2670 sky2->advertising = ecmd->advertising;
2671
1b537565
SH		 2672 if (netif_running(dev))
2673 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2674
2675 return 0;
2676}
2677
2678static void sky2_get_drvinfo(struct net_device *dev,
2679 struct ethtool_drvinfo *info)
2680{
2681 struct sky2_port *sky2 = netdev_priv(dev);
2682
2683 strcpy(info->driver, DRV_NAME);
2684 strcpy(info->version, DRV_VERSION);
2685 strcpy(info->fw_version, "N/A");
2686 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2687}
2688
2689static const struct sky2_stat {
793b883e
SH		 2690 char name[ETH_GSTRING_LEN];
2691 u16 offset;
cd28ab6a
SH		 2692} sky2_stats[] = {
2693 { "tx_bytes", GM_TXO_OK_HI },
2694 { "rx_bytes", GM_RXO_OK_HI },
2695 { "tx_broadcast", GM_TXF_BC_OK },
2696 { "rx_broadcast", GM_RXF_BC_OK },
2697 { "tx_multicast", GM_TXF_MC_OK },
2698 { "rx_multicast", GM_RXF_MC_OK },
2699 { "tx_unicast", GM_TXF_UC_OK },
2700 { "rx_unicast", GM_RXF_UC_OK },
2701 { "tx_mac_pause", GM_TXF_MPAUSE },
2702 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2703 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2704 { "late_collision",GM_TXF_LAT_COL },
2705 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2706 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2707 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2708
d2604540 2709 { "rx_short", GM_RXF_SHT },
cd28ab6a 2710 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2711 { "rx_64_byte_packets", GM_RXF_64B },
2712 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2713 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2714 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2715 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2716 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2717 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2718 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2719 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2720 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2721 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2722
2723 { "tx_64_byte_packets", GM_TXF_64B },
2724 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2725 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2726 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2727 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2728 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2729 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2730 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2731};
2732
cd28ab6a
SH		 2733static u32 sky2_get_rx_csum(struct net_device *dev)
2734{
2735 struct sky2_port *sky2 = netdev_priv(dev);
2736
2737 return sky2->rx_csum;
2738}
2739
2740static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2741{
2742 struct sky2_port *sky2 = netdev_priv(dev);
2743
2744 sky2->rx_csum = data;
793b883e 2745
cd28ab6a
SH		 2746 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2747 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2748
2749 return 0;
2750}
2751
2752static u32 sky2_get_msglevel(struct net_device *netdev)
2753{
2754 struct sky2_port *sky2 = netdev_priv(netdev);
2755 return sky2->msg_enable;
2756}
2757
9a7ae0a9
SH		 2758static int sky2_nway_reset(struct net_device *dev)
2759{
2760 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2761
16ad91e1 2762 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2763 return -EINVAL;
2764
1b537565 2765 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2766
2767 return 0;
2768}
2769
793b883e 2770static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2771{
2772 struct sky2_hw *hw = sky2->hw;
2773 unsigned port = sky2->port;
2774 int i;
2775
2776 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2777 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2778 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2779 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2780
793b883e 2781 for (i = 2; i < count; i++)
cd28ab6a
SH		 2782 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2783}
2784
cd28ab6a
SH		 2785static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2786{
2787 struct sky2_port *sky2 = netdev_priv(netdev);
2788 sky2->msg_enable = value;
2789}
2790
2791static int sky2_get_stats_count(struct net_device *dev)
2792{
2793 return ARRAY_SIZE(sky2_stats);
2794}
2795
2796static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2797 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2798{
2799 struct sky2_port *sky2 = netdev_priv(dev);
2800
793b883e 2801 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2802}
2803
793b883e 2804static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2805{
2806 int i;
2807
2808 switch (stringset) {
2809 case ETH_SS_STATS:
2810 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2811 memcpy(data + i * ETH_GSTRING_LEN,
2812 sky2_stats[i].name, ETH_GSTRING_LEN);
2813 break;
2814 }
2815}
2816
2817/* Use hardware MIB variables for critical path statistics and
2818 * transmit feedback not reported at interrupt.
2819 * Other errors are accounted for in interrupt handler.
2820 */
2821static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2822{
2823 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2824 u64 data[13];
cd28ab6a 2825
793b883e 2826 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2827
2828 sky2->net_stats.tx_bytes = data[0];
2829 sky2->net_stats.rx_bytes = data[1];
2830 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2831 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2832 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2833 sky2->net_stats.collisions = data[10];
2834 sky2->net_stats.tx_aborted_errors = data[12];
2835
2836 return &sky2->net_stats;
2837}
2838
2839static int sky2_set_mac_address(struct net_device *dev, void *p)
2840{
2841 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2842 struct sky2_hw *hw = sky2->hw;
2843 unsigned port = sky2->port;
2844 const struct sockaddr *addr = p;
cd28ab6a
SH		 2845
2846 if (!is_valid_ether_addr(addr->sa_data))
2847 return -EADDRNOTAVAIL;
2848
cd28ab6a 2849 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2850 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2851 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2852 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2853 dev->dev_addr, ETH_ALEN);
1b537565 2854
a8ab1ec0
SH		 2855 /* virtual address for data */
2856 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2857
2858 /* physical address: used for pause frames */
2859 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2860
2861 return 0;
cd28ab6a
SH		 2862}
2863
a052b52f
SH		 2864static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
2865{
2866 u32 bit;
2867
2868 bit = ether_crc(ETH_ALEN, addr) & 63;
2869 filter[bit >> 3] |= 1 << (bit & 7);
2870}
2871
cd28ab6a
SH		 2872static void sky2_set_multicast(struct net_device *dev)
2873{
2874 struct sky2_port *sky2 = netdev_priv(dev);
2875 struct sky2_hw *hw = sky2->hw;
2876 unsigned port = sky2->port;
2877 struct dev_mc_list *list = dev->mc_list;
2878 u16 reg;
2879 u8 filter[8];
a052b52f
SH		 2880 int rx_pause;
2881 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 2882
a052b52f 2883 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 2884 memset(filter, 0, sizeof(filter));
2885
2886 reg = gma_read16(hw, port, GM_RX_CTRL);
2887 reg |= GM_RXCR_UCF_ENA;
2888
d571b694 2889 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2890 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 2891 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 2892 memset(filter, 0xff, sizeof(filter));
a052b52f 2893 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 2894 reg &= ~GM_RXCR_MCF_ENA;
2895 else {
2896 int i;
2897 reg |= GM_RXCR_MCF_ENA;
2898
a052b52f
SH		 2899 if (rx_pause)
2900 sky2_add_filter(filter, pause_mc_addr);
2901
2902 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2903 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 2904 }
2905
cd28ab6a 2906 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2907 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2908 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2909 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2910 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2911 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2912 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2913 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2914
2915 gma_write16(hw, port, GM_RX_CTRL, reg);
2916}
2917
2918/* Can have one global because blinking is controlled by
2919 * ethtool and that is always under RTNL mutex
2920 */
91c86df5 2921static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2922{
793b883e
SH		 2923 u16 pg;
2924
793b883e
SH		 2925 switch (hw->chip_id) {
2926 case CHIP_ID_YUKON_XL:
2927 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2928 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2929 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2930 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2931 PHY_M_LEDC_INIT_CTRL(7) |
2932 PHY_M_LEDC_STA1_CTRL(7) |
2933 PHY_M_LEDC_STA0_CTRL(7))
2934 : 0);
2935
2936 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2937 break;
2938
2939 default:
2940 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 2941 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2942 on ? PHY_M_LED_ALL : 0);
793b883e 2943 }
cd28ab6a
SH		 2944}
2945
2946/* blink LED's for finding board */
2947static int sky2_phys_id(struct net_device *dev, u32 data)
2948{
2949 struct sky2_port *sky2 = netdev_priv(dev);
2950 struct sky2_hw *hw = sky2->hw;
2951 unsigned port = sky2->port;
793b883e 2952 u16 ledctrl, ledover = 0;
cd28ab6a 2953 long ms;
91c86df5 2954 int interrupted;
cd28ab6a
SH		 2955 int onoff = 1;
2956
793b883e 2957 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2958 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2959 else
2960 ms = data * 1000;
2961
2962 /* save initial values */
e07b1aa8 2963 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2964 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2965 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2966 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2967 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2968 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2969 } else {
2970 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2971 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2972 }
cd28ab6a 2973
91c86df5
SH		 2974 interrupted = 0;
2975 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2976 sky2_led(hw, port, onoff);
2977 onoff = !onoff;
2978
e07b1aa8 2979 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2980 interrupted = msleep_interruptible(250);
e07b1aa8 2981 spin_lock_bh(&sky2->phy_lock);
91c86df5 2982
cd28ab6a
SH		 2983 ms -= 250;
2984 }
2985
2986 /* resume regularly scheduled programming */
793b883e
SH		 2987 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2988 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2989 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2990 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2991 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2992 } else {
2993 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2994 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2995 }
e07b1aa8 2996 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2997
2998 return 0;
2999}
3000
3001static void sky2_get_pauseparam(struct net_device *dev,
3002 struct ethtool_pauseparam *ecmd)
3003{
3004 struct sky2_port *sky2 = netdev_priv(dev);
3005
16ad91e1
SH		 3006 switch (sky2->flow_mode) {
3007 case FC_NONE:
3008 ecmd->tx_pause = ecmd->rx_pause = 0;
3009 break;
3010 case FC_TX:
3011 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3012 break;
3013 case FC_RX:
3014 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3015 break;
3016 case FC_BOTH:
3017 ecmd->tx_pause = ecmd->rx_pause = 1;
3018 }
3019
cd28ab6a
SH		 3020 ecmd->autoneg = sky2->autoneg;
3021}
3022
3023static int sky2_set_pauseparam(struct net_device *dev,
3024 struct ethtool_pauseparam *ecmd)
3025{
3026 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3027
3028 sky2->autoneg = ecmd->autoneg;
16ad91e1 3029 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3030
16ad91e1
SH		 3031 if (netif_running(dev))
3032 sky2_phy_reinit(sky2);
cd28ab6a 3033
2eaba1a2 3034 return 0;
cd28ab6a
SH		 3035}
3036
fb17358f
SH		 3037static int sky2_get_coalesce(struct net_device *dev,
3038 struct ethtool_coalesce *ecmd)
3039{
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 struct sky2_hw *hw = sky2->hw;
3042
3043 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3044 ecmd->tx_coalesce_usecs = 0;
3045 else {
3046 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3047 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3048 }
3049 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3050
3051 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3052 ecmd->rx_coalesce_usecs = 0;
3053 else {
3054 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3055 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3056 }
3057 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3058
3059 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3060 ecmd->rx_coalesce_usecs_irq = 0;
3061 else {
3062 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3063 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3064 }
3065
3066 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3067
3068 return 0;
3069}
3070
3071/* Note: this affect both ports */
3072static int sky2_set_coalesce(struct net_device *dev,
3073 struct ethtool_coalesce *ecmd)
3074{
3075 struct sky2_port *sky2 = netdev_priv(dev);
3076 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3077 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3078
77b3d6a2
SH		 3079 if (ecmd->tx_coalesce_usecs > tmax ||
3080 ecmd->rx_coalesce_usecs > tmax ||
3081 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3082 return -EINVAL;
3083
ff81fbbe 3084 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3085 return -EINVAL;
ff81fbbe 3086 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3087 return -EINVAL;
ff81fbbe 3088 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3089 return -EINVAL;
3090
3091 if (ecmd->tx_coalesce_usecs == 0)
3092 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3093 else {
3094 sky2_write32(hw, STAT_TX_TIMER_INI,
3095 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3096 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3097 }
3098 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3099
3100 if (ecmd->rx_coalesce_usecs == 0)
3101 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3102 else {
3103 sky2_write32(hw, STAT_LEV_TIMER_INI,
3104 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3105 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3106 }
3107 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3108
3109 if (ecmd->rx_coalesce_usecs_irq == 0)
3110 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3111 else {
d28d4870 3112 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3113 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3114 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3115 }
3116 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3117 return 0;
3118}
3119
793b883e
SH		 3120static void sky2_get_ringparam(struct net_device *dev,
3121 struct ethtool_ringparam *ering)
3122{
3123 struct sky2_port *sky2 = netdev_priv(dev);
3124
3125 ering->rx_max_pending = RX_MAX_PENDING;
3126 ering->rx_mini_max_pending = 0;
3127 ering->rx_jumbo_max_pending = 0;
3128 ering->tx_max_pending = TX_RING_SIZE - 1;
3129
3130 ering->rx_pending = sky2->rx_pending;
3131 ering->rx_mini_pending = 0;
3132 ering->rx_jumbo_pending = 0;
3133 ering->tx_pending = sky2->tx_pending;
3134}
3135
3136static int sky2_set_ringparam(struct net_device *dev,
3137 struct ethtool_ringparam *ering)
3138{
3139 struct sky2_port *sky2 = netdev_priv(dev);
3140 int err = 0;
3141
3142 if (ering->rx_pending > RX_MAX_PENDING ||
3143 ering->rx_pending < 8 ||
3144 ering->tx_pending < MAX_SKB_TX_LE ||
3145 ering->tx_pending > TX_RING_SIZE - 1)
3146 return -EINVAL;
3147
3148 if (netif_running(dev))
3149 sky2_down(dev);
3150
3151 sky2->rx_pending = ering->rx_pending;
3152 sky2->tx_pending = ering->tx_pending;
3153
1b537565 3154 if (netif_running(dev)) {
793b883e 3155 err = sky2_up(dev);
1b537565
SH		 3156 if (err)
3157 dev_close(dev);
6ed995bb
SH		 3158 else
3159 sky2_set_multicast(dev);
1b537565 3160 }
793b883e
SH		 3161
3162 return err;
3163}
3164
793b883e
SH		 3165static int sky2_get_regs_len(struct net_device *dev)
3166{
6e4cbb34 3167 return 0x4000;
793b883e
SH		 3168}
3169
3170/*
3171 * Returns copy of control register region
6e4cbb34 3172 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3173 */
3174static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3175 void *p)
3176{
3177 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3178 const void __iomem *io = sky2->hw->regs;
793b883e 3179
6e4cbb34 3180 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3181 regs->version = 1;
6e4cbb34 3182 memset(p, 0, regs->len);
793b883e 3183
6e4cbb34
SH		 3184 memcpy_fromio(p, io, B3_RAM_ADDR);
3185
3186 memcpy_fromio(p + B3_RI_WTO_R1,
3187 io + B3_RI_WTO_R1,
3188 regs->len - B3_RI_WTO_R1);
793b883e 3189}
cd28ab6a 3190
7282d491 3191static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3192 .get_settings = sky2_get_settings,
3193 .set_settings = sky2_set_settings,
3194 .get_drvinfo = sky2_get_drvinfo,
3195 .get_msglevel = sky2_get_msglevel,
3196 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3197 .nway_reset = sky2_nway_reset,
793b883e
SH		 3198 .get_regs_len = sky2_get_regs_len,
3199 .get_regs = sky2_get_regs,
3200 .get_link = ethtool_op_get_link,
3201 .get_sg = ethtool_op_get_sg,
3202 .set_sg = ethtool_op_set_sg,
3203 .get_tx_csum = ethtool_op_get_tx_csum,
3204 .set_tx_csum = ethtool_op_set_tx_csum,
3205 .get_tso = ethtool_op_get_tso,
3206 .set_tso = ethtool_op_set_tso,
3207 .get_rx_csum = sky2_get_rx_csum,
3208 .set_rx_csum = sky2_set_rx_csum,
3209 .get_strings = sky2_get_strings,
fb17358f
SH		 3210 .get_coalesce = sky2_get_coalesce,
3211 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3212 .get_ringparam = sky2_get_ringparam,
3213 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3214 .get_pauseparam = sky2_get_pauseparam,
3215 .set_pauseparam = sky2_set_pauseparam,
793b883e 3216 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3217 .get_stats_count = sky2_get_stats_count,
3218 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3219 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3220};
3221
3222/* Initialize network device */
3223static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3224 unsigned port, int highmem)
3225{
3226 struct sky2_port *sky2;
3227 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3228
3229 if (!dev) {
3230 printk(KERN_ERR "sky2 etherdev alloc failed");
3231 return NULL;
3232 }
3233
3234 SET_MODULE_OWNER(dev);
3235 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3236 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3237 dev->open = sky2_up;
3238 dev->stop = sky2_down;
ef743d33 3239 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3240 dev->hard_start_xmit = sky2_xmit_frame;
3241 dev->get_stats = sky2_get_stats;
3242 dev->set_multicast_list = sky2_set_multicast;
3243 dev->set_mac_address = sky2_set_mac_address;
3244 dev->change_mtu = sky2_change_mtu;
3245 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3246 dev->tx_timeout = sky2_tx_timeout;
3247 dev->watchdog_timeo = TX_WATCHDOG;
3248 if (port == 0)
3249 dev->poll = sky2_poll;
3250 dev->weight = NAPI_WEIGHT;
3251#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3252 /* Network console (only works on port 0)
3253 * because netpoll makes assumptions about NAPI
3254 */
3255 if (port == 0)
3256 dev->poll_controller = sky2_netpoll;
cd28ab6a 3257#endif
cd28ab6a
SH		 3258
3259 sky2 = netdev_priv(dev);
3260 sky2->netdev = dev;
3261 sky2->hw = hw;
3262 sky2->msg_enable = netif_msg_init(debug, default_msg);
3263
cd28ab6a
SH		 3264 /* Auto speed and flow control */
3265 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3266 sky2->flow_mode = FC_BOTH;
3267
cd28ab6a
SH		 3268 sky2->duplex = -1;
3269 sky2->speed = -1;
3270 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3271 sky2->rx_csum = 1;
75d070c5 3272
e07b1aa8 3273 spin_lock_init(&sky2->phy_lock);
793b883e 3274 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3275 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3276
3277 hw->dev[port] = dev;
3278
3279 sky2->port = port;
3280
5a5b1ea0
SH		 3281 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3282 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3283 if (highmem)
3284 dev->features |= NETIF_F_HIGHDMA;
793b883e 3285 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3286
d1f13708
SH		 3287#ifdef SKY2_VLAN_TAG_USED
3288 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3289 dev->vlan_rx_register = sky2_vlan_rx_register;
3290 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3291#endif
3292
cd28ab6a 3293 /* read the mac address */
793b883e 3294 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3295 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3296
3297 /* device is off until link detection */
3298 netif_carrier_off(dev);
3299 netif_stop_queue(dev);
3300
3301 return dev;
3302}
3303
28bd181a 3304static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3305{
3306 const struct sky2_port *sky2 = netdev_priv(dev);
3307
3308 if (netif_msg_probe(sky2))
3309 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3310 dev->name,
3311 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3312 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3313}
3314
fb2690a9 3315/* Handle software interrupt used during MSI test */
7d12e780 3316static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3317{
3318 struct sky2_hw *hw = dev_id;
3319 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3320
3321 if (status == 0)
3322 return IRQ_NONE;
3323
3324 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3325 hw->msi = 1;
fb2690a9
SH		 3326 wake_up(&hw->msi_wait);
3327 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3328 }
3329 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3330
3331 return IRQ_HANDLED;
3332}
3333
3334/* Test interrupt path by forcing a a software IRQ */
3335static int __devinit sky2_test_msi(struct sky2_hw *hw)
3336{
3337 struct pci_dev *pdev = hw->pdev;
3338 int err;
3339
bb507fe1
SH		 3340 init_waitqueue_head (&hw->msi_wait);
3341
fb2690a9
SH		 3342 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3343
b0a20ded 3344 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9
SH		 3345 if (err) {
3346 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3347 pci_name(pdev), pdev->irq);
3348 return err;
3349 }
3350
fb2690a9 3351 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3352 sky2_read8(hw, B0_CTST);
fb2690a9 3353
b0a20ded 3354 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3355
b0a20ded 3356 if (!hw->msi) {
fb2690a9 3357 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3358 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3359 "switching to INTx mode.\n",
fb2690a9
SH		 3360 pci_name(pdev));
3361
3362 err = -EOPNOTSUPP;
3363 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3364 }
3365
3366 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3367 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3368
3369 free_irq(pdev->irq, hw);
3370
3371 return err;
3372}
3373
cd28ab6a
SH		 3374static int __devinit sky2_probe(struct pci_dev *pdev,
3375 const struct pci_device_id *ent)
3376{
793b883e 3377 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3378 struct sky2_hw *hw;
5afa0a9c 3379 int err, pm_cap, using_dac = 0;
cd28ab6a 3380
793b883e
SH		 3381 err = pci_enable_device(pdev);
3382 if (err) {
cd28ab6a
SH		 3383 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3384 pci_name(pdev));
3385 goto err_out;
3386 }
3387
793b883e
SH		 3388 err = pci_request_regions(pdev, DRV_NAME);
3389 if (err) {
cd28ab6a
SH		 3390 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3391 pci_name(pdev));
793b883e 3392 goto err_out;
cd28ab6a
SH		 3393 }
3394
3395 pci_set_master(pdev);
3396
5afa0a9c
SH		 3397 /* Find power-management capability. */
3398 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3399 if (pm_cap == 0) {
3400 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3401 "aborting.\n");
3402 err = -EIO;
3403 goto err_out_free_regions;
3404 }
3405
d1f3d4dd
SH		 3406 if (sizeof(dma_addr_t) > sizeof(u32) &&
3407 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3408 using_dac = 1;
3409 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3410 if (err < 0) {
3411 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3412 "for consistent allocations\n", pci_name(pdev));
3413 goto err_out_free_regions;
3414 }
cd28ab6a 3415
d1f3d4dd 3416 } else {
cd28ab6a
SH		 3417 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3418 if (err) {
3419 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3420 pci_name(pdev));
3421 goto err_out_free_regions;
3422 }
3423 }
d1f3d4dd 3424
cd28ab6a 3425 err = -ENOMEM;
6aad85d6 3426 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3427 if (!hw) {
3428 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3429 pci_name(pdev));
3430 goto err_out_free_regions;
3431 }
3432
cd28ab6a 3433 hw->pdev = pdev;
cd28ab6a
SH		 3434
3435 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3436 if (!hw->regs) {
3437 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3438 pci_name(pdev));
3439 goto err_out_free_hw;
3440 }
5afa0a9c 3441 hw->pm_cap = pm_cap;
cd28ab6a 3442
56a645cc 3443#ifdef __BIG_ENDIAN
f65b138c
SH		 3444 /* The sk98lin vendor driver uses hardware byte swapping but
3445 * this driver uses software swapping.
3446 */
56a645cc
SH		 3447 {
3448 u32 reg;
56a645cc 3449 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3450 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3451 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3452 }
3453#endif
3454
08c06d8a
SH		 3455 /* ring for status responses */
3456 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3457 &hw->st_dma);
3458 if (!hw->st_le)
3459 goto err_out_iounmap;
3460
cd28ab6a
SH		 3461 err = sky2_reset(hw);
3462 if (err)
793b883e 3463 goto err_out_iounmap;
cd28ab6a 3464
7c7459d1
GKH		 3465 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3466 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3467 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3468 hw->chip_id, hw->chip_rev);
cd28ab6a 3469
793b883e
SH		 3470 dev = sky2_init_netdev(hw, 0, using_dac);
3471 if (!dev)
cd28ab6a
SH		 3472 goto err_out_free_pci;
3473
9fa1b1f3
SH		 3474 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3475 err = sky2_test_msi(hw);
3476 if (err == -EOPNOTSUPP)
3477 pci_disable_msi(pdev);
3478 else if (err)
3479 goto err_out_free_netdev;
3480 }
3481
793b883e
SH		 3482 err = register_netdev(dev);
3483 if (err) {
cd28ab6a
SH		 3484 printk(KERN_ERR PFX "%s: cannot register net device\n",
3485 pci_name(pdev));
3486 goto err_out_free_netdev;
3487 }
3488
b0a20ded
SH		 3489 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3490 dev->name, hw);
9fa1b1f3
SH		 3491 if (err) {
3492 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3493 pci_name(pdev), pdev->irq);
3494 goto err_out_unregister;
3495 }
3496 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3497
cd28ab6a
SH		 3498 sky2_show_addr(dev);
3499
3500 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3501 if (register_netdev(dev1) == 0)
3502 sky2_show_addr(dev1);
3503 else {
3504 /* Failure to register second port need not be fatal */
793b883e
SH		 3505 printk(KERN_WARNING PFX
3506 "register of second port failed\n");
cd28ab6a
SH		 3507 hw->dev[1] = NULL;
3508 free_netdev(dev1);
3509 }
3510 }
3511
01bd7564 3512 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3513 sky2_idle_start(hw);
d27ed387 3514
793b883e
SH		 3515 pci_set_drvdata(pdev, hw);
3516
cd28ab6a
SH		 3517 return 0;
3518
793b883e 3519err_out_unregister:
b0a20ded
SH		 3520 if (hw->msi)
3521 pci_disable_msi(pdev);
793b883e 3522 unregister_netdev(dev);
cd28ab6a
SH		 3523err_out_free_netdev:
3524 free_netdev(dev);
cd28ab6a 3525err_out_free_pci:
793b883e 3526 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3527 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3528err_out_iounmap:
3529 iounmap(hw->regs);
3530err_out_free_hw:
3531 kfree(hw);
3532err_out_free_regions:
3533 pci_release_regions(pdev);
cd28ab6a 3534 pci_disable_device(pdev);
cd28ab6a
SH		 3535err_out:
3536 return err;
3537}
3538
3539static void __devexit sky2_remove(struct pci_dev *pdev)
3540{
793b883e 3541 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3542 struct net_device *dev0, *dev1;
3543
793b883e 3544 if (!hw)
cd28ab6a
SH		 3545 return;
3546
d27ed387
SH		 3547 del_timer_sync(&hw->idle_timer);
3548
3549 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3550 synchronize_irq(hw->pdev->irq);
3551
cd28ab6a 3552 dev0 = hw->dev[0];
793b883e
SH		 3553 dev1 = hw->dev[1];
3554 if (dev1)
3555 unregister_netdev(dev1);
cd28ab6a
SH		 3556 unregister_netdev(dev0);
3557
5afa0a9c 3558 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3559 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3560 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3561 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3562
3563 free_irq(pdev->irq, hw);
b0a20ded
SH		 3564 if (hw->msi)
3565 pci_disable_msi(pdev);
793b883e 3566 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3567 pci_release_regions(pdev);
3568 pci_disable_device(pdev);
793b883e 3569
cd28ab6a
SH		 3570 if (dev1)
3571 free_netdev(dev1);
3572 free_netdev(dev0);
3573 iounmap(hw->regs);
3574 kfree(hw);
5afa0a9c 3575
cd28ab6a
SH		 3576 pci_set_drvdata(pdev, NULL);
3577}
3578
3579#ifdef CONFIG_PM
3580static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3581{
793b883e 3582 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3583 int i;
2ccc99b7
SH		 3584 pci_power_t pstate = pci_choose_state(pdev, state);
3585
3586 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3587 return -EINVAL;
cd28ab6a 3588
eb35cf60 3589 del_timer_sync(&hw->idle_timer);
6a5706b9 3590 netif_poll_disable(hw->dev[0]);
eb35cf60 3591
f05267e7 3592 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3593 struct net_device *dev = hw->dev[i];
3594
6a5706b9 3595 if (netif_running(dev)) {
5afa0a9c 3596 sky2_down(dev);
cd28ab6a 3597 netif_device_detach(dev);
cd28ab6a
SH		 3598 }
3599 }
3600
8ab8fca2 3601 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3602 pci_save_state(pdev);
2ccc99b7
SH		 3603 sky2_set_power_state(hw, pstate);
3604 return 0;
cd28ab6a
SH		 3605}
3606
3607static int sky2_resume(struct pci_dev *pdev)
3608{
793b883e 3609 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3610 int i, err;
cd28ab6a 3611
cd28ab6a
SH		 3612 pci_restore_state(pdev);
3613 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3614 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3615
08c06d8a
SH		 3616 err = sky2_reset(hw);
3617 if (err)
3618 goto out;
cd28ab6a 3619
8ab8fca2
SH		 3620 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3621
f05267e7 3622 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3623 struct net_device *dev = hw->dev[i];
6a5706b9 3624 if (netif_running(dev)) {
08c06d8a 3625 netif_device_attach(dev);
88d11360 3626
08c06d8a
SH		 3627 err = sky2_up(dev);
3628 if (err) {
3629 printk(KERN_ERR PFX "%s: could not up: %d\n",
3630 dev->name, err);
3631 dev_close(dev);
eb35cf60 3632 goto out;
5afa0a9c 3633 }
cd28ab6a
SH		 3634 }
3635 }
eb35cf60 3636
6a5706b9 3637 netif_poll_enable(hw->dev[0]);
eb35cf60 3638 sky2_idle_start(hw);
08c06d8a
SH		 3639out:
3640 return err;
cd28ab6a
SH		 3641}
3642#endif
3643
3644static struct pci_driver sky2_driver = {
793b883e
SH		 3645 .name = DRV_NAME,
3646 .id_table = sky2_id_table,
3647 .probe = sky2_probe,
3648 .remove = __devexit_p(sky2_remove),
cd28ab6a 3649#ifdef CONFIG_PM
793b883e
SH		 3650 .suspend = sky2_suspend,
3651 .resume = sky2_resume,
cd28ab6a
SH		 3652#endif
3653};
3654
3655static int __init sky2_init_module(void)
3656{
50241c4c 3657 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3658}
3659
3660static void __exit sky2_cleanup_module(void)
3661{
3662 pci_unregister_driver(&sky2_driver);
3663}
3664
3665module_init(sky2_init_module);
3666module_exit(sky2_cleanup_module);
3667
3668MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3669MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3670MODULE_LICENSE("GPL");
5f4f9dc1 3671MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree