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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
fe2a24df 53#define DRV_VERSION "1.6"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
13210ce5 63#define RX_LE_SIZE 512
cd28ab6a 64#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 65#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 66#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 67#define RX_SKB_ALIGN 8
22e11703 68#define RX_BUF_WRITE 16
793b883e
SH		 69
70#define TX_RING_SIZE 512
71#define TX_DEF_PENDING (TX_RING_SIZE - 1)
72#define TX_MIN_PENDING 64
b19666d9 73#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 74
793b883e 75#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 76#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77#define ETH_JUMBO_MTU 9000
78#define TX_WATCHDOG (5 * HZ)
79#define NAPI_WEIGHT 64
80#define PHY_RETRIES 1000
81
cb5d9547
SH		 82#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
cd28ab6a 84static const u32 default_msg =
793b883e
SH		 85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 88
793b883e 89static int debug = -1; /* defaults above */
cd28ab6a
SH		 90module_param(debug, int, 0);
91MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
bdb5c58e
SH		 93static int copybreak __read_mostly = 256;
94module_param(copybreak, int, 0);
95MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
fb2690a9
SH		 97static int disable_msi = 0;
98module_param(disable_msi, int, 0);
99MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
01bd7564
SH		 101static int idle_timeout = 100;
102module_param(idle_timeout, int, 0);
103MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
cd28ab6a 105static const struct pci_device_id sky2_id_table[] = {
793b883e 106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
cd28ab6a
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
cd28ab6a
SH		 129 { 0 }
130};
793b883e 131
cd28ab6a
SH		 132MODULE_DEVICE_TABLE(pci, sky2_id_table);
133
134/* Avoid conditionals by using array */
135static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
136static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 137static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 138
92f965e8
SH		 139/* This driver supports yukon2 chipset only */
140static const char *yukon2_name[] = {
141 "XL", /* 0xb3 */
142 "EC Ultra", /* 0xb4 */
143 "UNKNOWN", /* 0xb5 */
144 "EC", /* 0xb6 */
145 "FE", /* 0xb7 */
793b883e
SH		 146};
147
793b883e 148/* Access to external PHY */
ef743d33 149static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 150{
151 int i;
152
153 gma_write16(hw, port, GM_SMI_DATA, val);
154 gma_write16(hw, port, GM_SMI_CTRL,
155 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
156
157 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 158 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 159 return 0;
793b883e 160 udelay(1);
cd28ab6a 161 }
ef743d33 162
793b883e 163 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 164 return -ETIMEDOUT;
cd28ab6a
SH		 165}
166
ef743d33 167static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 168{
169 int i;
170
793b883e 171 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 172 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
173
174 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 175 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
176 *val = gma_read16(hw, port, GM_SMI_DATA);
177 return 0;
178 }
179
793b883e 180 udelay(1);
cd28ab6a
SH		 181 }
182
ef743d33
SH		 183 return -ETIMEDOUT;
184}
185
186static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
187{
188 u16 v;
189
190 if (__gm_phy_read(hw, port, reg, &v) != 0)
191 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
192 return v;
cd28ab6a
SH		 193}
194
2ccc99b7 195static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 196{
197 u16 power_control;
198 u32 reg1;
199 int vaux;
5afa0a9c
SH		 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
231 /* Turn off phy power saving */
56a645cc 232 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 233 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
234
d571b694 235 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 236 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
237 reg1 |= PCI_Y2_PHY1_COMA;
238 if (hw->ports > 1)
239 reg1 |= PCI_Y2_PHY2_COMA;
240 }
8d3d35b4
SH		 241 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
242 udelay(100);
977bdf06
SH		 243
244 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
56a645cc
SH		 245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 247 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 248 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
249 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 250 }
251
5afa0a9c
SH		 252 break;
253
254 case PCI_D3hot:
255 case PCI_D3cold:
256 /* Turn on phy power saving */
56a645cc 257 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
5afa0a9c
SH		 258 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
259 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
260 else
261 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
56a645cc 262 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
afa195da 263 udelay(100);
5afa0a9c
SH		 264
265 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
266 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
267 else
268 /* enable bits are inverted */
269 sky2_write8(hw, B2_Y2_CLK_GATE,
270 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
271 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
272 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
273
274 /* switch power to VAUX */
275 if (vaux && state != PCI_D3cold)
276 sky2_write8(hw, B0_POWER_CTRL,
277 (PC_VAUX_ENA | PC_VCC_ENA |
278 PC_VAUX_ON | PC_VCC_OFF));
279 break;
280 default:
281 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 282 }
283
56a645cc 284 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 285 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 286}
287
cd28ab6a
SH		 288static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
289{
290 u16 reg;
291
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294 /* disable PHY IRQs */
295 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 296
cd28ab6a
SH		 297 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
298 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301
302 reg = gma_read16(hw, port, GM_RX_CTRL);
303 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
304 gma_write16(hw, port, GM_RX_CTRL, reg);
305}
306
307static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
308{
309 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 310 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 311
ed6d32c7 312 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 313 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 314 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
315
316 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 317 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 318 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
319
320 if (hw->chip_id == CHIP_ID_YUKON_EC)
321 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
322 else
323 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
324
325 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
326 }
327
328 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
329 if (hw->copper) {
330 if (hw->chip_id == CHIP_ID_YUKON_FE) {
331 /* enable automatic crossover */
332 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
333 } else {
334 /* disable energy detect */
335 ctrl &= ~PHY_M_PC_EN_DET_MSK;
336
337 /* enable automatic crossover */
338 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
339
340 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 341 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 342 ctrl &= ~PHY_M_PC_DSC_MSK;
343 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
344 }
345 }
346 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347 } else {
348 /* workaround for deviation #4.88 (CRC errors) */
349 /* disable Automatic Crossover */
350
351 ctrl &= ~PHY_M_PC_MDIX_MSK;
352 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
353
354 if (hw->chip_id == CHIP_ID_YUKON_XL) {
355 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
358 ctrl &= ~PHY_M_MAC_MD_MSK;
359 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
360 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
361
362 /* select page 1 to access Fiber registers */
363 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
364 }
cd28ab6a
SH		 365 }
366
367 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
368 if (sky2->autoneg == AUTONEG_DISABLE)
369 ctrl &= ~PHY_CT_ANE;
370 else
371 ctrl |= PHY_CT_ANE;
372
373 ctrl |= PHY_CT_RESET;
374 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
375
376 ctrl = 0;
377 ct1000 = 0;
378 adv = PHY_AN_CSMA;
379
380 if (sky2->autoneg == AUTONEG_ENABLE) {
381 if (hw->copper) {
382 if (sky2->advertising & ADVERTISED_1000baseT_Full)
383 ct1000 |= PHY_M_1000C_AFD;
384 if (sky2->advertising & ADVERTISED_1000baseT_Half)
385 ct1000 |= PHY_M_1000C_AHD;
386 if (sky2->advertising & ADVERTISED_100baseT_Full)
387 adv |= PHY_M_AN_100_FD;
388 if (sky2->advertising & ADVERTISED_100baseT_Half)
389 adv |= PHY_M_AN_100_HD;
390 if (sky2->advertising & ADVERTISED_10baseT_Full)
391 adv |= PHY_M_AN_10_FD;
392 if (sky2->advertising & ADVERTISED_10baseT_Half)
393 adv |= PHY_M_AN_10_HD;
793b883e 394 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 395 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
396
397 /* Set Flow-control capabilities */
398 if (sky2->tx_pause && sky2->rx_pause)
793b883e 399 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 400 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 401 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 402 else if (!sky2->rx_pause && sky2->tx_pause)
403 adv |= PHY_AN_PAUSE_ASYM; /* local */
404
405 /* Restart Auto-negotiation */
406 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
407 } else {
408 /* forced speed/duplex settings */
409 ct1000 = PHY_M_1000C_MSE;
410
411 if (sky2->duplex == DUPLEX_FULL)
412 ctrl |= PHY_CT_DUP_MD;
413
414 switch (sky2->speed) {
415 case SPEED_1000:
416 ctrl |= PHY_CT_SP1000;
417 break;
418 case SPEED_100:
419 ctrl |= PHY_CT_SP100;
420 break;
421 }
422
423 ctrl |= PHY_CT_RESET;
424 }
425
426 if (hw->chip_id != CHIP_ID_YUKON_FE)
427 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
428
429 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
430 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
431
432 /* Setup Phy LED's */
433 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
434 ledover = 0;
435
436 switch (hw->chip_id) {
437 case CHIP_ID_YUKON_FE:
438 /* on 88E3082 these bits are at 11..9 (shifted left) */
439 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
440
441 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
442
443 /* delete ACT LED control bits */
444 ctrl &= ~PHY_M_FELP_LED1_MSK;
445 /* change ACT LED control to blink mode */
446 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
447 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
448 break;
449
450 case CHIP_ID_YUKON_XL:
793b883e 451 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 452
453 /* select page 3 to access LED control register */
454 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
455
456 /* set LED Function Control register */
ed6d32c7
SH		 457 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
458 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
459 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
460 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
461 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 462
463 /* set Polarity Control register */
464 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 465 (PHY_M_POLC_LS1_P_MIX(4) |
466 PHY_M_POLC_IS0_P_MIX(4) |
467 PHY_M_POLC_LOS_CTRL(2) |
468 PHY_M_POLC_INIT_CTRL(2) |
469 PHY_M_POLC_STA1_CTRL(2) |
470 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 471
472 /* restore page register */
793b883e 473 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 474 break;
ed6d32c7
SH		 475 case CHIP_ID_YUKON_EC_U:
476 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
477
478 /* select page 3 to access LED control register */
479 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
480
481 /* set LED Function Control register */
482 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
483 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
484 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
485 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
486 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
487
488 /* set Blink Rate in LED Timer Control Register */
489 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
490 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
491 /* restore page register */
492 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
493 break;
cd28ab6a
SH		 494
495 default:
496 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
498 /* turn off the Rx LED (LED_RX) */
499 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
500 }
501
ed6d32c7 502 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 503 /* apply fixes in PHY AFE */
ed6d32c7
SH		 504 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
506
977bdf06 507 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 508 gm_phy_write(hw, port, 0x18, 0xaa99);
509 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 510
977bdf06 511 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 512 gm_phy_write(hw, port, 0x18, 0xa204);
513 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 514
515 /* set page register to 0 */
ed6d32c7 516 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 517 } else {
518 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 519
977bdf06
SH		 520 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
521 /* turn on 100 Mbps LED (LED_LINK100) */
522 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
523 }
cd28ab6a 524
977bdf06
SH		 525 if (ledover)
526 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
527
528 }
d571b694 529 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 530 if (sky2->autoneg == AUTONEG_ENABLE)
531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
532 else
533 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
534}
535
1b537565
SH		 536/* Force a renegotiation */
537static void sky2_phy_reinit(struct sky2_port *sky2)
538{
e07b1aa8 539 spin_lock_bh(&sky2->phy_lock);
1b537565 540 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 541 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 542}
543
cd28ab6a
SH		 544static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
545{
546 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
547 u16 reg;
548 int i;
549 const u8 *addr = hw->dev[port]->dev_addr;
550
42eeea01
SH		 551 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
552 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 553
554 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
555
793b883e 556 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 557 /* WA DEV_472 -- looks like crossed wires on port 2 */
558 /* clear GMAC 1 Control reset */
559 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
560 do {
561 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
562 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
563 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
564 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
565 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
566 }
567
cd28ab6a
SH		 568 if (sky2->autoneg == AUTONEG_DISABLE) {
569 reg = gma_read16(hw, port, GM_GP_CTRL);
570 reg |= GM_GPCR_AU_ALL_DIS;
571 gma_write16(hw, port, GM_GP_CTRL, reg);
572 gma_read16(hw, port, GM_GP_CTRL);
573
cd28ab6a
SH		 574 switch (sky2->speed) {
575 case SPEED_1000:
6f4c56b2 576 reg &= ~GM_GPCR_SPEED_100;
cd28ab6a 577 reg |= GM_GPCR_SPEED_1000;
6f4c56b2 578 break;
cd28ab6a 579 case SPEED_100:
6f4c56b2 580 reg &= ~GM_GPCR_SPEED_1000;
cd28ab6a 581 reg |= GM_GPCR_SPEED_100;
6f4c56b2
SH		 582 break;
583 case SPEED_10:
584 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
585 break;
cd28ab6a
SH		 586 }
587
588 if (sky2->duplex == DUPLEX_FULL)
589 reg |= GM_GPCR_DUP_FULL;
ed6d32c7
SH		 590
591 /* turn off pause in 10/100mbps half duplex */
592 else if (sky2->speed != SPEED_1000 &&
593 hw->chip_id != CHIP_ID_YUKON_EC_U)
594 sky2->tx_pause = sky2->rx_pause = 0;
cd28ab6a
SH		 595 } else
596 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
597
598 if (!sky2->tx_pause && !sky2->rx_pause) {
599 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 600 reg |=
601 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
602 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 603 /* disable Rx flow-control */
604 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
605 }
606
607 gma_write16(hw, port, GM_GP_CTRL, reg);
608
793b883e 609 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 610
e07b1aa8 611 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 612 sky2_phy_init(hw, port);
e07b1aa8 613 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 614
615 /* MIB clear */
616 reg = gma_read16(hw, port, GM_PHY_ADDR);
617 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
618
43f2f104
SH		 619 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
620 gma_read16(hw, port, i);
cd28ab6a
SH		 621 gma_write16(hw, port, GM_PHY_ADDR, reg);
622
623 /* transmit control */
624 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
625
626 /* receive control reg: unicast + multicast + no FCS */
627 gma_write16(hw, port, GM_RX_CTRL,
793b883e 628 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 629
630 /* transmit flow control */
631 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
632
633 /* transmit parameter */
634 gma_write16(hw, port, GM_TX_PARAM,
635 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
636 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
637 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
638 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
639
640 /* serial mode register */
641 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 642 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 643
6b1a3aef 644 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 645 reg |= GM_SMOD_JUMBO_ENA;
646
647 gma_write16(hw, port, GM_SERIAL_MODE, reg);
648
cd28ab6a
SH		 649 /* virtual address for data */
650 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
651
793b883e
SH		 652 /* physical address: used for pause frames */
653 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
654
655 /* ignore counter overflows */
cd28ab6a
SH		 656 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
657 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
658 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
659
660 /* Configure Rx MAC FIFO */
661 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 662 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
663 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 664
d571b694 665 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 666 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 667
793b883e
SH		 668 /* Set threshold to 0xa (64 bytes)
669 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 670 */
671 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
672
673 /* Configure Tx MAC FIFO */
674 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
675 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 676
677 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
678 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
679 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
680 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
681 /* set Tx GMAC FIFO Almost Empty Threshold */
682 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
683 /* Disable Store & Forward mode for TX */
684 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
685 }
686 }
687
cd28ab6a
SH		 688}
689
1c28f6ba
SH		 690/* Assign Ram Buffer allocation.
691 * start and end are in units of 4k bytes
692 * ram registers are in units of 64bit words
693 */
694static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 695{
1c28f6ba 696 u32 start, end;
cd28ab6a 697
1c28f6ba
SH		 698 start = startk * 4096/8;
699 end = (endk * 4096/8) - 1;
793b883e 700
cd28ab6a
SH		 701 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
702 sky2_write32(hw, RB_ADDR(q, RB_START), start);
703 sky2_write32(hw, RB_ADDR(q, RB_END), end);
704 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
705 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
706
707 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 708 u32 space = (endk - startk) * 4096/8;
709 u32 tp = space - space/4;
793b883e 710
1c28f6ba
SH		 711 /* On receive queue's set the thresholds
712 * give receiver priority when > 3/4 full
713 * send pause when down to 2K
714 */
715 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
716 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 717
1c28f6ba
SH		 718 tp = space - 2048/8;
719 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
720 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 721 } else {
722 /* Enable store & forward on Tx queue's because
723 * Tx FIFO is only 1K on Yukon
724 */
725 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
726 }
727
728 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 729 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 730}
731
cd28ab6a 732/* Setup Bus Memory Interface */
af4ed7e6 733static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 734{
735 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
736 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
737 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 738 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 739}
740
cd28ab6a
SH		 741/* Setup prefetch unit registers. This is the interface between
742 * hardware and driver list elements
743 */
8cc048e3 744static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 745 u64 addr, u32 last)
746{
cd28ab6a
SH		 747 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
749 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
751 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 753
754 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 755}
756
793b883e
SH		 757static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
758{
759 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
760
cb5d9547 761 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
793b883e
SH		 762 return le;
763}
cd28ab6a 764
290d4de5
SH		 765/* Update chip's next pointer */
766static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 767{
762c2de2 768 wmb();
290d4de5 769 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
762c2de2 770 mmiowb();
cd28ab6a
SH		 771}
772
793b883e 773
cd28ab6a
SH		 774static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
775{
776 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 777 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
cd28ab6a
SH		 778 return le;
779}
780
a018e330
SH		 781/* Return high part of DMA address (could be 32 or 64 bit) */
782static inline u32 high32(dma_addr_t a)
783{
a036119f 784 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 785}
786
793b883e 787/* Build description to hardware about buffer */
28bd181a 788static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
cd28ab6a
SH		 789{
790 struct sky2_rx_le *le;
734d1868
SH		 791 u32 hi = high32(map);
792 u16 len = sky2->rx_bufsize;
cd28ab6a 793
793b883e 794 if (sky2->rx_addr64 != hi) {
cd28ab6a 795 le = sky2_next_rx(sky2);
793b883e 796 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 797 le->ctrl = 0;
798 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 799 sky2->rx_addr64 = high32(map + len);
cd28ab6a 800 }
793b883e 801
cd28ab6a 802 le = sky2_next_rx(sky2);
734d1868
SH		 803 le->addr = cpu_to_le32((u32) map);
804 le->length = cpu_to_le16(len);
cd28ab6a
SH		 805 le->ctrl = 0;
806 le->opcode = OP_PACKET | HW_OWNER;
807}
808
793b883e 809
cd28ab6a
SH		 810/* Tell chip where to start receive checksum.
811 * Actually has two checksums, but set both same to avoid possible byte
812 * order problems.
813 */
793b883e 814static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 815{
816 struct sky2_rx_le *le;
817
cd28ab6a 818 le = sky2_next_rx(sky2);
793b883e 819 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 820 le->ctrl = 0;
821 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 822
793b883e
SH		 823 sky2_write32(sky2->hw,
824 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
825 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 826
827}
828
6b1a3aef
SH		 829/*
830 * The RX Stop command will not work for Yukon-2 if the BMU does not
831 * reach the end of packet and since we can't make sure that we have
832 * incoming data, we must reset the BMU while it is not doing a DMA
833 * transfer. Since it is possible that the RX path is still active,
834 * the RX RAM buffer will be stopped first, so any possible incoming
835 * data will not trigger a DMA. After the RAM buffer is stopped, the
836 * BMU is polled until any DMA in progress is ended and only then it
837 * will be reset.
838 */
839static void sky2_rx_stop(struct sky2_port *sky2)
840{
841 struct sky2_hw *hw = sky2->hw;
842 unsigned rxq = rxqaddr[sky2->port];
843 int i;
844
845 /* disable the RAM Buffer receive queue */
846 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
847
848 for (i = 0; i < 0xffff; i++)
849 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
850 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
851 goto stopped;
852
853 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
854 sky2->netdev->name);
855stopped:
856 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
857
858 /* reset the Rx prefetch unit */
859 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
860}
793b883e 861
d571b694 862/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 863static void sky2_rx_clean(struct sky2_port *sky2)
864{
865 unsigned i;
866
867 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 868 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 869 struct ring_info *re = sky2->rx_ring + i;
870
871 if (re->skb) {
793b883e 872 pci_unmap_single(sky2->hw->pdev,
734d1868 873 re->mapaddr, sky2->rx_bufsize,
cd28ab6a
SH		 874 PCI_DMA_FROMDEVICE);
875 kfree_skb(re->skb);
876 re->skb = NULL;
877 }
878 }
879}
880
ef743d33
SH		 881/* Basic MII support */
882static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
883{
884 struct mii_ioctl_data *data = if_mii(ifr);
885 struct sky2_port *sky2 = netdev_priv(dev);
886 struct sky2_hw *hw = sky2->hw;
887 int err = -EOPNOTSUPP;
888
889 if (!netif_running(dev))
890 return -ENODEV; /* Phy still in reset */
891
d89e1343 892 switch (cmd) {
ef743d33
SH		 893 case SIOCGMIIPHY:
894 data->phy_id = PHY_ADDR_MARV;
895
896 /* fallthru */
897 case SIOCGMIIREG: {
898 u16 val = 0;
91c86df5 899
e07b1aa8 900 spin_lock_bh(&sky2->phy_lock);
ef743d33 901 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 902 spin_unlock_bh(&sky2->phy_lock);
91c86df5 903
ef743d33
SH		 904 data->val_out = val;
905 break;
906 }
907
908 case SIOCSMIIREG:
909 if (!capable(CAP_NET_ADMIN))
910 return -EPERM;
911
e07b1aa8 912 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 913 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
914 data->val_in);
e07b1aa8 915 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 916 break;
917 }
918 return err;
919}
920
d1f13708
SH		 921#ifdef SKY2_VLAN_TAG_USED
922static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
923{
924 struct sky2_port *sky2 = netdev_priv(dev);
925 struct sky2_hw *hw = sky2->hw;
926 u16 port = sky2->port;
d1f13708 927
302d1252 928 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 929
930 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
931 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
932 sky2->vlgrp = grp;
933
302d1252 934 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 935}
936
937static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
938{
939 struct sky2_port *sky2 = netdev_priv(dev);
940 struct sky2_hw *hw = sky2->hw;
941 u16 port = sky2->port;
d1f13708 942
302d1252 943 spin_lock_bh(&sky2->tx_lock);
d1f13708
SH		 944
945 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
946 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
947 if (sky2->vlgrp)
948 sky2->vlgrp->vlan_devices[vid] = NULL;
949
302d1252 950 spin_unlock_bh(&sky2->tx_lock);
d1f13708
SH		 951}
952#endif
953
82788c7a
SH		 954/*
955 * It appears the hardware has a bug in the FIFO logic that
956 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 957 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
958 * aligned except if slab debugging is enabled.
82788c7a 959 */
497d7c86
SH		 960static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev,
961 unsigned int length,
962 gfp_t gfp_mask)
82788c7a
SH		 963{
964 struct sk_buff *skb;
965
497d7c86 966 skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask);
82788c7a
SH		 967 if (likely(skb)) {
968 unsigned long p = (unsigned long) skb->data;
4a15d56f 969 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
82788c7a
SH		 970 }
971
972 return skb;
973}
974
cd28ab6a
SH		 975/*
976 * Allocate and setup receiver buffer pool.
977 * In case of 64 bit dma, there are 2X as many list elements
978 * available as ring entries
979 * and need to reserve one list element so we don't wrap around.
980 */
6b1a3aef 981static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 982{
6b1a3aef 983 struct sky2_hw *hw = sky2->hw;
6b1a3aef
SH		 984 unsigned rxq = rxqaddr[sky2->port];
985 int i;
a1433ac4 986 unsigned thresh;
cd28ab6a 987
6b1a3aef 988 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 989 sky2_qset(hw, rxq);
977bdf06
SH		 990
991 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
992 /* MAC Rx RAM Read is controlled by hardware */
993 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
994 }
995
6b1a3aef
SH		 996 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
997
998 rx_set_checksum(sky2);
793b883e 999 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 1000 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 1001
497d7c86
SH		 1002 re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize,
1003 GFP_KERNEL);
cd28ab6a
SH		 1004 if (!re->skb)
1005 goto nomem;
1006
6b1a3aef 1007 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
734d1868
SH		 1008 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1009 sky2_rx_add(sky2, re->mapaddr);
cd28ab6a
SH		 1010 }
1011
a1433ac4
SH		 1012
1013 /*
1014 * The receiver hangs if it receives frames larger than the
1015 * packet buffer. As a workaround, truncate oversize frames, but
1016 * the register is limited to 9 bits, so if you do frames > 2052
1017 * you better get the MTU right!
1018 */
1019 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1020 if (thresh > 0x1ff)
1021 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1022 else {
1023 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1024 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1025 }
1026
70f1be48 1027
6b1a3aef
SH		 1028 /* Tell chip about available buffers */
1029 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1030 return 0;
1031nomem:
1032 sky2_rx_clean(sky2);
1033 return -ENOMEM;
1034}
1035
1036/* Bring up network interface. */
1037static int sky2_up(struct net_device *dev)
1038{
1039 struct sky2_port *sky2 = netdev_priv(dev);
1040 struct sky2_hw *hw = sky2->hw;
1041 unsigned port = sky2->port;
e07b1aa8 1042 u32 ramsize, rxspace, imask;
ee7abb04 1043 int cap, err = -ENOMEM;
843a46f4 1044 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1045
ee7abb04
SH		 1046 /*
1047 * On dual port PCI-X card, there is an problem where status
1048 * can be received out of order due to split transactions
843a46f4 1049 */
ee7abb04
SH		 1050 if (otherdev && netif_running(otherdev) &&
1051 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1052 struct sky2_port *osky2 = netdev_priv(otherdev);
1053 u16 cmd;
1054
1055 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1056 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1057 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1058
1059 sky2->rx_csum = 0;
1060 osky2->rx_csum = 0;
1061 }
843a46f4 1062
cd28ab6a
SH		 1063 if (netif_msg_ifup(sky2))
1064 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1065
1066 /* must be power of 2 */
1067 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1068 TX_RING_SIZE *
1069 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1070 &sky2->tx_le_map);
1071 if (!sky2->tx_le)
1072 goto err_out;
1073
6cdbbdf3 1074 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1075 GFP_KERNEL);
1076 if (!sky2->tx_ring)
1077 goto err_out;
1078 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1079
1080 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1081 &sky2->rx_le_map);
1082 if (!sky2->rx_le)
1083 goto err_out;
1084 memset(sky2->rx_le, 0, RX_LE_BYTES);
1085
6cdbbdf3 1086 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
cd28ab6a
SH		 1087 GFP_KERNEL);
1088 if (!sky2->rx_ring)
1089 goto err_out;
1090
1091 sky2_mac_init(hw, port);
1092
1c28f6ba
SH		 1093 /* Determine available ram buffer space (in 4K blocks).
1094 * Note: not sure about the FE setting below yet
1095 */
1096 if (hw->chip_id == CHIP_ID_YUKON_FE)
1097 ramsize = 4;
1098 else
1099 ramsize = sky2_read8(hw, B2_E_0);
1100
1101 /* Give transmitter one third (rounded up) */
1102 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1103
cd28ab6a 1104 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1105 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1106
793b883e
SH		 1107 /* Make sure SyncQ is disabled */
1108 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1109 RB_RST_SET);
1110
af4ed7e6 1111 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1112
977bdf06
SH		 1113 /* Set almost empty threshold */
1114 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1115 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1116
6b1a3aef
SH		 1117 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1118 TX_RING_SIZE - 1);
cd28ab6a 1119
6b1a3aef 1120 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1121 if (err)
1122 goto err_out;
1123
cd28ab6a 1124 /* Enable interrupts from phy/mac for port */
e07b1aa8 1125 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1126 imask |= portirq_msk[port];
e07b1aa8
SH		 1127 sky2_write32(hw, B0_IMSK, imask);
1128
cd28ab6a
SH		 1129 return 0;
1130
1131err_out:
1b537565 1132 if (sky2->rx_le) {
cd28ab6a
SH		 1133 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1134 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1135 sky2->rx_le = NULL;
1136 }
1137 if (sky2->tx_le) {
cd28ab6a
SH		 1138 pci_free_consistent(hw->pdev,
1139 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1140 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1141 sky2->tx_le = NULL;
1142 }
1143 kfree(sky2->tx_ring);
1144 kfree(sky2->rx_ring);
cd28ab6a 1145
1b537565
SH		 1146 sky2->tx_ring = NULL;
1147 sky2->rx_ring = NULL;
cd28ab6a
SH		 1148 return err;
1149}
1150
793b883e
SH		 1151/* Modular subtraction in ring */
1152static inline int tx_dist(unsigned tail, unsigned head)
1153{
cb5d9547 1154 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1155}
cd28ab6a 1156
793b883e
SH		 1157/* Number of list elements available for next tx */
1158static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1159{
793b883e 1160 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1161}
1162
793b883e 1163/* Estimate of number of transmit list elements required */
28bd181a 1164static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1165{
793b883e
SH		 1166 unsigned count;
1167
1168 count = sizeof(dma_addr_t) / sizeof(u32);
1169 count += skb_shinfo(skb)->nr_frags * count;
1170
89114afd 1171 if (skb_is_gso(skb))
793b883e
SH		 1172 ++count;
1173
0e3ff6aa 1174 if (skb->ip_summed == CHECKSUM_HW)
793b883e
SH		 1175 ++count;
1176
1177 return count;
cd28ab6a
SH		 1178}
1179
793b883e
SH		 1180/*
1181 * Put one packet in ring for transmit.
1182 * A single packet can generate multiple list elements, and
1183 * the number of ring elements will probably be less than the number
1184 * of list elements used.
f2e46561
SH		 1185 *
1186 * No BH disabling for tx_lock here (like tg3)
793b883e 1187 */
cd28ab6a
SH		 1188static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1189{
1190 struct sky2_port *sky2 = netdev_priv(dev);
1191 struct sky2_hw *hw = sky2->hw;
d1f13708 1192 struct sky2_tx_le *le = NULL;
6cdbbdf3 1193 struct tx_ring_info *re;
cd28ab6a
SH		 1194 unsigned i, len;
1195 dma_addr_t mapping;
1196 u32 addr64;
1197 u16 mss;
1198 u8 ctrl;
1199
302d1252
SH		 1200 /* No BH disabling for tx_lock here. We are running in BH disabled
1201 * context and TX reclaim runs via poll inside of a software
1202 * interrupt, and no related locks in IRQ processing.
1203 */
f2e46561 1204 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1205 return NETDEV_TX_LOCKED;
1206
793b883e 1207 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
8c463ef7
SH		 1208 /* There is a known but harmless race with lockless tx
1209 * and netif_stop_queue.
1210 */
1211 if (!netif_queue_stopped(dev)) {
1212 netif_stop_queue(dev);
3be92a70
SH		 1213 if (net_ratelimit())
1214 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1215 dev->name);
8c463ef7 1216 }
f2e46561 1217 spin_unlock(&sky2->tx_lock);
cd28ab6a 1218
cd28ab6a
SH		 1219 return NETDEV_TX_BUSY;
1220 }
1221
793b883e 1222 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1223 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1224 dev->name, sky2->tx_prod, skb->len);
1225
cd28ab6a
SH		 1226 len = skb_headlen(skb);
1227 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1228 addr64 = high32(mapping);
793b883e
SH		 1229
1230 re = sky2->tx_ring + sky2->tx_prod;
1231
a018e330
SH		 1232 /* Send high bits if changed or crosses boundary */
1233 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1234 le = get_tx_le(sky2);
1235 le->tx.addr = cpu_to_le32(addr64);
1236 le->ctrl = 0;
1237 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1238 sky2->tx_addr64 = high32(mapping + len);
793b883e 1239 }
cd28ab6a
SH		 1240
1241 /* Check for TCP Segmentation Offload */
7967168c 1242 mss = skb_shinfo(skb)->gso_size;
793b883e 1243 if (mss != 0) {
cd28ab6a
SH		 1244 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1245 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1246 mss += ETH_HLEN;
1247
e07560cd
SH		 1248 if (mss != sky2->tx_last_mss) {
1249 le = get_tx_le(sky2);
1250 le->tx.tso.size = cpu_to_le16(mss);
1251 le->tx.tso.rsvd = 0;
1252 le->opcode = OP_LRGLEN | HW_OWNER;
1253 le->ctrl = 0;
1254 sky2->tx_last_mss = mss;
1255 }
cd28ab6a
SH		 1256 }
1257
cd28ab6a 1258 ctrl = 0;
d1f13708
SH		 1259#ifdef SKY2_VLAN_TAG_USED
1260 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1261 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1262 if (!le) {
1263 le = get_tx_le(sky2);
1264 le->tx.addr = 0;
1265 le->opcode = OP_VLAN|HW_OWNER;
1266 le->ctrl = 0;
1267 } else
1268 le->opcode |= OP_VLAN;
1269 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1270 ctrl |= INS_VLAN;
1271 }
1272#endif
1273
1274 /* Handle TCP checksum offload */
cd28ab6a 1275 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1276 u16 hdr = skb->h.raw - skb->data;
1277 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1278
1279 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1280 if (skb->nh.iph->protocol == IPPROTO_UDP)
1281 ctrl |= UDPTCP;
1282
1d179332
SH		 1283 if (hdr != sky2->tx_csum_start || offset != sky2->tx_csum_offset) {
1284 sky2->tx_csum_start = hdr;
1285 sky2->tx_csum_offset = offset;
1286
1287 le = get_tx_le(sky2);
1288 le->tx.csum.start = cpu_to_le16(hdr);
1289 le->tx.csum.offset = cpu_to_le16(offset);
1290 le->length = 0; /* initial checksum value */
1291 le->ctrl = 1; /* one packet */
1292 le->opcode = OP_TCPLISW | HW_OWNER;
1293 }
cd28ab6a
SH		 1294 }
1295
1296 le = get_tx_le(sky2);
1297 le->tx.addr = cpu_to_le32((u32) mapping);
1298 le->length = cpu_to_le16(len);
1299 le->ctrl = ctrl;
793b883e 1300 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1301
793b883e 1302 /* Record the transmit mapping info */
cd28ab6a 1303 re->skb = skb;
6cdbbdf3 1304 pci_unmap_addr_set(re, mapaddr, mapping);
cd28ab6a
SH		 1305
1306 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1307 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6cdbbdf3 1308 struct tx_ring_info *fre;
cd28ab6a
SH		 1309
1310 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1311 frag->size, PCI_DMA_TODEVICE);
a036119f 1312 addr64 = high32(mapping);
793b883e
SH		 1313 if (addr64 != sky2->tx_addr64) {
1314 le = get_tx_le(sky2);
1315 le->tx.addr = cpu_to_le32(addr64);
1316 le->ctrl = 0;
1317 le->opcode = OP_ADDR64 | HW_OWNER;
1318 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1319 }
1320
1321 le = get_tx_le(sky2);
1322 le->tx.addr = cpu_to_le32((u32) mapping);
1323 le->length = cpu_to_le16(frag->size);
1324 le->ctrl = ctrl;
793b883e 1325 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1326
793b883e 1327 fre = sky2->tx_ring
e07560cd 1328 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
6cdbbdf3 1329 pci_unmap_addr_set(fre, mapaddr, mapping);
cd28ab6a 1330 }
6cdbbdf3 1331
793b883e 1332 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1333 le->ctrl |= EOP;
1334
97bda706
SH		 1335 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1336 netif_stop_queue(dev);
b19666d9 1337
290d4de5 1338 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1339
f2e46561 1340 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1341
1342 dev->trans_start = jiffies;
1343 return NETDEV_TX_OK;
1344}
1345
cd28ab6a 1346/*
793b883e
SH		 1347 * Free ring elements from starting at tx_cons until "done"
1348 *
1349 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1350 * buffers; these are deferred until completion.
cd28ab6a 1351 */
d11c13e7 1352static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1353{
d11c13e7 1354 struct net_device *dev = sky2->netdev;
af2a58ac
SH		 1355 struct pci_dev *pdev = sky2->hw->pdev;
1356 u16 nxt, put;
793b883e 1357 unsigned i;
cd28ab6a 1358
0e3ff6aa 1359 BUG_ON(done >= TX_RING_SIZE);
2224795d 1360
d11c13e7 1361 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1362 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1363 dev->name, done);
cd28ab6a 1364
af2a58ac
SH		 1365 for (put = sky2->tx_cons; put != done; put = nxt) {
1366 struct tx_ring_info *re = sky2->tx_ring + put;
1367 struct sk_buff *skb = re->skb;
cd28ab6a 1368
d89e1343 1369 nxt = re->idx;
af2a58ac 1370 BUG_ON(nxt >= TX_RING_SIZE);
d70cd51a 1371 prefetch(sky2->tx_ring + nxt);
cd28ab6a 1372
793b883e 1373 /* Check for partial status */
af2a58ac
SH		 1374 if (tx_dist(put, done) < tx_dist(put, nxt))
1375 break;
793b883e
SH		 1376
1377 skb = re->skb;
af2a58ac 1378 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
734d1868 1379 skb_headlen(skb), PCI_DMA_TODEVICE);
793b883e
SH		 1380
1381 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6cdbbdf3 1382 struct tx_ring_info *fre;
cb5d9547 1383 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
af2a58ac 1384 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
d89e1343 1385 skb_shinfo(skb)->frags[i].size,
734d1868 1386 PCI_DMA_TODEVICE);
cd28ab6a
SH		 1387 }
1388
15240072 1389 dev_kfree_skb(skb);
793b883e 1390 }
793b883e 1391
af2a58ac 1392 sky2->tx_cons = put;
22e11703 1393 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1394 netif_wake_queue(dev);
cd28ab6a
SH		 1395}
1396
1397/* Cleanup all untransmitted buffers, assume transmitter not running */
13b97b74 1398static void sky2_tx_clean(struct sky2_port *sky2)
cd28ab6a 1399{
302d1252 1400 spin_lock_bh(&sky2->tx_lock);
d11c13e7 1401 sky2_tx_complete(sky2, sky2->tx_prod);
302d1252 1402 spin_unlock_bh(&sky2->tx_lock);
cd28ab6a
SH		 1403}
1404
1405/* Network shutdown */
1406static int sky2_down(struct net_device *dev)
1407{
1408 struct sky2_port *sky2 = netdev_priv(dev);
1409 struct sky2_hw *hw = sky2->hw;
1410 unsigned port = sky2->port;
1411 u16 ctrl;
e07b1aa8 1412 u32 imask;
cd28ab6a 1413
1b537565
SH		 1414 /* Never really got started! */
1415 if (!sky2->tx_le)
1416 return 0;
1417
cd28ab6a
SH		 1418 if (netif_msg_ifdown(sky2))
1419 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1420
018d1c66 1421 /* Stop more packets from being queued */
cd28ab6a
SH		 1422 netif_stop_queue(dev);
1423
793b883e
SH		 1424 sky2_phy_reset(hw, port);
1425
cd28ab6a
SH		 1426 /* Stop transmitter */
1427 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1428 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1429
1430 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1431 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1432
1433 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1434 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1435 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1436
1437 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1438
1439 /* Workaround shared GMAC reset */
793b883e
SH		 1440 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1441 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1442 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1443
1444 /* Disable Force Sync bit and Enable Alloc bit */
1445 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1446 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1447
1448 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1449 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1450 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1451
1452 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1453 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1454 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1455
1456 /* Reset the Tx prefetch units */
1457 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1458 PREF_UNIT_RST_SET);
1459
1460 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1461
6b1a3aef 1462 sky2_rx_stop(sky2);
cd28ab6a
SH		 1463
1464 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1465 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1466
e07b1aa8
SH		 1467 /* Disable port IRQ */
1468 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1469 imask &= ~portirq_msk[port];
e07b1aa8
SH		 1470 sky2_write32(hw, B0_IMSK, imask);
1471
d571b694 1472 /* turn off LED's */
cd28ab6a
SH		 1473 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1474
018d1c66
SH		 1475 synchronize_irq(hw->pdev->irq);
1476
cd28ab6a
SH		 1477 sky2_tx_clean(sky2);
1478 sky2_rx_clean(sky2);
1479
1480 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1481 sky2->rx_le, sky2->rx_le_map);
1482 kfree(sky2->rx_ring);
1483
1484 pci_free_consistent(hw->pdev,
1485 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1486 sky2->tx_le, sky2->tx_le_map);
1487 kfree(sky2->tx_ring);
1488
1b537565
SH		 1489 sky2->tx_le = NULL;
1490 sky2->rx_le = NULL;
1491
1492 sky2->rx_ring = NULL;
1493 sky2->tx_ring = NULL;
1494
cd28ab6a
SH		 1495 return 0;
1496}
1497
1498static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1499{
793b883e
SH		 1500 if (!hw->copper)
1501 return SPEED_1000;
1502
cd28ab6a
SH		 1503 if (hw->chip_id == CHIP_ID_YUKON_FE)
1504 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1505
1506 switch (aux & PHY_M_PS_SPEED_MSK) {
1507 case PHY_M_PS_SPEED_1000:
1508 return SPEED_1000;
1509 case PHY_M_PS_SPEED_100:
1510 return SPEED_100;
1511 default:
1512 return SPEED_10;
1513 }
1514}
1515
1516static void sky2_link_up(struct sky2_port *sky2)
1517{
1518 struct sky2_hw *hw = sky2->hw;
1519 unsigned port = sky2->port;
1520 u16 reg;
1521
1522 /* Enable Transmit FIFO Underrun */
793b883e 1523 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1524
1525 reg = gma_read16(hw, port, GM_GP_CTRL);
6f4c56b2
SH		 1526 if (sky2->autoneg == AUTONEG_DISABLE) {
1527 reg |= GM_GPCR_AU_ALL_DIS;
1528
1529 /* Is write/read necessary? Copied from sky2_mac_init */
1530 gma_write16(hw, port, GM_GP_CTRL, reg);
1531 gma_read16(hw, port, GM_GP_CTRL);
1532
1533 switch (sky2->speed) {
1534 case SPEED_1000:
1535 reg &= ~GM_GPCR_SPEED_100;
1536 reg |= GM_GPCR_SPEED_1000;
1537 break;
1538 case SPEED_100:
1539 reg &= ~GM_GPCR_SPEED_1000;
1540 reg |= GM_GPCR_SPEED_100;
1541 break;
1542 case SPEED_10:
1543 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1544 break;
1545 }
1546 } else
1547 reg &= ~GM_GPCR_AU_ALL_DIS;
1548
cd28ab6a
SH		 1549 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1550 reg |= GM_GPCR_DUP_FULL;
1551
cd28ab6a
SH		 1552 /* enable Rx/Tx */
1553 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1554 gma_write16(hw, port, GM_GP_CTRL, reg);
1555 gma_read16(hw, port, GM_GP_CTRL);
1556
1557 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1558
1559 netif_carrier_on(sky2->netdev);
1560 netif_wake_queue(sky2->netdev);
1561
1562 /* Turn on link LED */
793b883e 1563 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1564 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1565
ed6d32c7 1566 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1567 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1568 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1569
1570 switch(sky2->speed) {
1571 case SPEED_10:
1572 led |= PHY_M_LEDC_INIT_CTRL(7);
1573 break;
1574
1575 case SPEED_100:
1576 led |= PHY_M_LEDC_STA1_CTRL(7);
1577 break;
1578
1579 case SPEED_1000:
1580 led |= PHY_M_LEDC_STA0_CTRL(7);
1581 break;
1582 }
793b883e
SH		 1583
1584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1585 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1587 }
1588
cd28ab6a
SH		 1589 if (netif_msg_link(sky2))
1590 printk(KERN_INFO PFX
d571b694 1591 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1592 sky2->netdev->name, sky2->speed,
1593 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1594 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1595 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1596}
1597
1598static void sky2_link_down(struct sky2_port *sky2)
1599{
1600 struct sky2_hw *hw = sky2->hw;
1601 unsigned port = sky2->port;
1602 u16 reg;
1603
1604 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1605
1606 reg = gma_read16(hw, port, GM_GP_CTRL);
1607 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1608 gma_write16(hw, port, GM_GP_CTRL, reg);
1609 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1610
1611 if (sky2->rx_pause && !sky2->tx_pause) {
1612 /* restore Asymmetric Pause bit */
1613 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1614 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1615 | PHY_M_AN_ASP);
cd28ab6a
SH		 1616 }
1617
cd28ab6a
SH		 1618 netif_carrier_off(sky2->netdev);
1619 netif_stop_queue(sky2->netdev);
1620
1621 /* Turn on link LED */
1622 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1623
1624 if (netif_msg_link(sky2))
1625 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1626 sky2_phy_init(hw, port);
1627}
1628
793b883e
SH		 1629static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1630{
1631 struct sky2_hw *hw = sky2->hw;
1632 unsigned port = sky2->port;
1633 u16 lpa;
1634
1635 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1636
1637 if (lpa & PHY_M_AN_RF) {
1638 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1639 return -1;
1640 }
1641
1642 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1643 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1644 printk(KERN_ERR PFX "%s: master/slave fault",
1645 sky2->netdev->name);
1646 return -1;
1647 }
1648
1649 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1650 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1651 sky2->netdev->name);
1652 return -1;
1653 }
1654
1655 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1656
1657 sky2->speed = sky2_phy_speed(hw, aux);
1658
1659 /* Pause bits are offset (9..8) */
ed6d32c7 1660 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1661 aux >>= 6;
1662
1663 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1664 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1665
1666 if ((sky2->tx_pause || sky2->rx_pause)
1667 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1668 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1669 else
1670 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1671
1672 return 0;
1673}
cd28ab6a 1674
e07b1aa8
SH		 1675/* Interrupt from PHY */
1676static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1677{
e07b1aa8
SH		 1678 struct net_device *dev = hw->dev[port];
1679 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1680 u16 istatus, phystat;
1681
e07b1aa8
SH		 1682 spin_lock(&sky2->phy_lock);
1683 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1684 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1685
1686 if (!netif_running(dev))
1687 goto out;
cd28ab6a
SH		 1688
1689 if (netif_msg_intr(sky2))
1690 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1691 sky2->netdev->name, istatus, phystat);
1692
1693 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1694 if (sky2_autoneg_done(sky2, phystat) == 0)
1695 sky2_link_up(sky2);
1696 goto out;
1697 }
cd28ab6a 1698
793b883e
SH		 1699 if (istatus & PHY_M_IS_LSP_CHANGE)
1700 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1701
793b883e
SH		 1702 if (istatus & PHY_M_IS_DUP_CHANGE)
1703 sky2->duplex =
1704 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1705
793b883e
SH		 1706 if (istatus & PHY_M_IS_LST_CHANGE) {
1707 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1708 sky2_link_up(sky2);
793b883e
SH		 1709 else
1710 sky2_link_down(sky2);
cd28ab6a 1711 }
793b883e 1712out:
e07b1aa8 1713 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1714}
1715
302d1252
SH		 1716
1717/* Transmit timeout is only called if we are running, carries is up
1718 * and tx queue is full (stopped).
1719 */
cd28ab6a
SH		 1720static void sky2_tx_timeout(struct net_device *dev)
1721{
1722 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1723 struct sky2_hw *hw = sky2->hw;
1724 unsigned txq = txqaddr[sky2->port];
8f24664d 1725 u16 report, done;
cd28ab6a
SH		 1726
1727 if (netif_msg_timer(sky2))
1728 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1729
8f24664d
SH		 1730 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1731 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1732
8f24664d
SH		 1733 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1734 dev->name,
1735 sky2->tx_cons, sky2->tx_prod, report, done);
1736
1737 if (report != done) {
1738 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1739
1740 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1741 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1742 } else if (report != sky2->tx_cons) {
1743 printk(KERN_INFO PFX "status report lost?\n");
1744
1745 spin_lock_bh(&sky2->tx_lock);
1746 sky2_tx_complete(sky2, report);
1747 spin_unlock_bh(&sky2->tx_lock);
1748 } else {
1749 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1750
8f24664d
SH		 1751 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1752 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1753
1754 sky2_tx_clean(sky2);
1755
1756 sky2_qset(hw, txq);
1757 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1758 }
cd28ab6a
SH		 1759}
1760
734d1868 1761
70f1be48
SH		 1762/* Want receive buffer size to be multiple of 64 bits
1763 * and incl room for vlan and truncation
1764 */
734d1868
SH		 1765static inline unsigned sky2_buf_size(int mtu)
1766{
4a15d56f 1767 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
734d1868
SH		 1768}
1769
cd28ab6a
SH		 1770static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1771{
6b1a3aef
SH		 1772 struct sky2_port *sky2 = netdev_priv(dev);
1773 struct sky2_hw *hw = sky2->hw;
1774 int err;
1775 u16 ctl, mode;
e07b1aa8 1776 u32 imask;
cd28ab6a
SH		 1777
1778 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1779 return -EINVAL;
1780
5a5b1ea0
SH		 1781 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1782 return -EINVAL;
1783
6b1a3aef
SH		 1784 if (!netif_running(dev)) {
1785 dev->mtu = new_mtu;
1786 return 0;
1787 }
1788
e07b1aa8 1789 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1790 sky2_write32(hw, B0_IMSK, 0);
1791
018d1c66
SH		 1792 dev->trans_start = jiffies; /* prevent tx timeout */
1793 netif_stop_queue(dev);
1794 netif_poll_disable(hw->dev[0]);
1795
e07b1aa8
SH		 1796 synchronize_irq(hw->pdev->irq);
1797
6b1a3aef
SH		 1798 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1799 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1800 sky2_rx_stop(sky2);
1801 sky2_rx_clean(sky2);
cd28ab6a
SH		 1802
1803 dev->mtu = new_mtu;
734d1868 1804 sky2->rx_bufsize = sky2_buf_size(new_mtu);
6b1a3aef
SH		 1805 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1806 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1807
1808 if (dev->mtu > ETH_DATA_LEN)
1809 mode |= GM_SMOD_JUMBO_ENA;
1810
1811 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1812
6b1a3aef 1813 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1814
6b1a3aef 1815 err = sky2_rx_start(sky2);
e07b1aa8 1816 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1817
1b537565
SH		 1818 if (err)
1819 dev_close(dev);
1820 else {
1821 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1822
1823 netif_poll_enable(hw->dev[0]);
1824 netif_wake_queue(dev);
1825 }
1826
cd28ab6a
SH		 1827 return err;
1828}
1829
1830/*
1831 * Receive one packet.
1832 * For small packets or errors, just reuse existing skb.
d571b694 1833 * For larger packets, get new buffer.
cd28ab6a 1834 */
497d7c86 1835static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1836 u16 length, u32 status)
1837{
497d7c86 1838 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 1839 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1840 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1841
1842 if (unlikely(netif_msg_rx_status(sky2)))
1843 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1844 dev->name, sky2->rx_next, status, length);
cd28ab6a 1845
793b883e 1846 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1847 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1848
42eeea01 1849 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1850 goto error;
1851
42eeea01
SH		 1852 if (!(status & GMR_FS_RX_OK))
1853 goto resubmit;
1854
497d7c86 1855 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 1856 goto oversize;
1857
bdb5c58e 1858 if (length < copybreak) {
497d7c86 1859 skb = netdev_alloc_skb(dev, length + 2);
79e57d32 1860 if (!skb)
793b883e
SH		 1861 goto resubmit;
1862
79e57d32 1863 skb_reserve(skb, 2);
793b883e
SH		 1864 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1865 length, PCI_DMA_FROMDEVICE);
79e57d32 1866 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1867 skb->ip_summed = re->skb->ip_summed;
1868 skb->csum = re->skb->csum;
793b883e
SH		 1869 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1870 length, PCI_DMA_FROMDEVICE);
793b883e 1871 } else {
79e57d32
SH		 1872 struct sk_buff *nskb;
1873
497d7c86 1874 nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC);
793b883e
SH		 1875 if (!nskb)
1876 goto resubmit;
cd28ab6a 1877
793b883e 1878 skb = re->skb;
79e57d32 1879 re->skb = nskb;
793b883e 1880 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
734d1868 1881 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1882 prefetch(skb->data);
cd28ab6a 1883
793b883e 1884 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
734d1868 1885 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
793b883e 1886 }
cd28ab6a 1887
79e57d32 1888 skb_put(skb, length);
793b883e 1889resubmit:
d11c13e7 1890 re->skb->ip_summed = CHECKSUM_NONE;
734d1868 1891 sky2_rx_add(sky2, re->mapaddr);
79e57d32 1892
cd28ab6a
SH		 1893 return skb;
1894
6e15b712
SH		 1895oversize:
1896 ++sky2->net_stats.rx_over_errors;
1897 goto resubmit;
1898
cd28ab6a 1899error:
6e15b712
SH		 1900 ++sky2->net_stats.rx_errors;
1901
3be92a70 1902 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 1903 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 1904 dev->name, status, length);
793b883e
SH		 1905
1906 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1907 sky2->net_stats.rx_length_errors++;
1908 if (status & GMR_FS_FRAGMENT)
1909 sky2->net_stats.rx_frame_errors++;
1910 if (status & GMR_FS_CRC_ERR)
1911 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1912 if (status & GMR_FS_RX_FF_OV)
1913 sky2->net_stats.rx_fifo_errors++;
79e57d32 1914
793b883e 1915 goto resubmit;
cd28ab6a
SH		 1916}
1917
e07b1aa8
SH		 1918/* Transmit complete */
1919static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 1920{
e07b1aa8 1921 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 1922
e07b1aa8
SH		 1923 if (netif_running(dev)) {
1924 spin_lock(&sky2->tx_lock);
1925 sky2_tx_complete(sky2, last);
1926 spin_unlock(&sky2->tx_lock);
2224795d 1927 }
cd28ab6a
SH		 1928}
1929
e07b1aa8
SH		 1930/* Process status response ring */
1931static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 1932{
22e11703 1933 struct sky2_port *sky2;
e07b1aa8 1934 int work_done = 0;
22e11703 1935 unsigned buf_write[2] = { 0, 0 };
e71ebd73 1936 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 1937
af2a58ac 1938 rmb();
bea86103 1939
e71ebd73 1940 while (hw->st_idx != hwidx) {
13210ce5
SH		 1941 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1942 struct net_device *dev;
cd28ab6a 1943 struct sk_buff *skb;
cd28ab6a
SH		 1944 u32 status;
1945 u16 length;
1946
cb5d9547 1947 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 1948
e71ebd73
SH		 1949 BUG_ON(le->link >= 2);
1950 dev = hw->dev[le->link];
13210ce5
SH		 1951
1952 sky2 = netdev_priv(dev);
e07b1aa8
SH		 1953 length = le->length;
1954 status = le->status;
cd28ab6a 1955
e71ebd73 1956 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 1957 case OP_RXSTAT:
497d7c86 1958 skb = sky2_receive(dev, length, status);
d1f13708
SH		 1959 if (!skb)
1960 break;
13210ce5 1961
13210ce5
SH		 1962 skb->protocol = eth_type_trans(skb, dev);
1963 dev->last_rx = jiffies;
1964
d1f13708
SH		 1965#ifdef SKY2_VLAN_TAG_USED
1966 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1967 vlan_hwaccel_receive_skb(skb,
1968 sky2->vlgrp,
1969 be16_to_cpu(sky2->rx_tag));
1970 } else
1971#endif
cd28ab6a 1972 netif_receive_skb(skb);
13210ce5 1973
22e11703
SH		 1974 /* Update receiver after 16 frames */
1975 if (++buf_write[le->link] == RX_BUF_WRITE) {
1976 sky2_put_idx(hw, rxqaddr[le->link],
1977 sky2->rx_put);
1978 buf_write[le->link] = 0;
1979 }
1980
1981 /* Stop after net poll weight */
13210ce5
SH		 1982 if (++work_done >= to_do)
1983 goto exit_loop;
cd28ab6a
SH		 1984 break;
1985
d1f13708
SH		 1986#ifdef SKY2_VLAN_TAG_USED
1987 case OP_RXVLAN:
1988 sky2->rx_tag = length;
1989 break;
1990
1991 case OP_RXCHKSVLAN:
1992 sky2->rx_tag = length;
1993 /* fall through */
1994#endif
cd28ab6a 1995 case OP_RXCHKS:
d11c13e7
SH		 1996 skb = sky2->rx_ring[sky2->rx_next].skb;
1997 skb->ip_summed = CHECKSUM_HW;
1998 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1999 break;
2000
2001 case OP_TXINDEXLE:
13b97b74 2002 /* TX index reports status for both ports */
f55925d7
SH		 2003 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2004 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2005 if (hw->dev[1])
2006 sky2_tx_done(hw->dev[1],
2007 ((status >> 24) & 0xff)
2008 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2009 break;
2010
cd28ab6a
SH		 2011 default:
2012 if (net_ratelimit())
793b883e 2013 printk(KERN_WARNING PFX
e71ebd73
SH		 2014 "unknown status opcode 0x%x\n", le->opcode);
2015 goto exit_loop;
cd28ab6a 2016 }
13210ce5 2017 }
cd28ab6a 2018
fe2a24df
SH		 2019 /* Fully processed status ring so clear irq */
2020 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2021
13210ce5 2022exit_loop:
22e11703
SH		 2023 if (buf_write[0]) {
2024 sky2 = netdev_priv(hw->dev[0]);
2025 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2026 }
2027
2028 if (buf_write[1]) {
2029 sky2 = netdev_priv(hw->dev[1]);
2030 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2031 }
2032
e07b1aa8 2033 return work_done;
cd28ab6a
SH		 2034}
2035
2036static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2037{
2038 struct net_device *dev = hw->dev[port];
2039
3be92a70
SH		 2040 if (net_ratelimit())
2041 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2042 dev->name, status);
cd28ab6a
SH		 2043
2044 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2045 if (net_ratelimit())
2046 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2047 dev->name);
cd28ab6a
SH		 2048 /* Clear IRQ */
2049 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2050 }
2051
2052 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2053 if (net_ratelimit())
2054 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2055 dev->name);
cd28ab6a
SH		 2056
2057 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2058 }
2059
2060 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2061 if (net_ratelimit())
2062 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2063 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2064 }
2065
2066 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2067 if (net_ratelimit())
2068 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2069 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2070 }
2071
2072 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2073 if (net_ratelimit())
2074 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2075 dev->name);
cd28ab6a
SH		 2076 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2077 }
2078}
2079
2080static void sky2_hw_intr(struct sky2_hw *hw)
2081{
2082 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2083
793b883e 2084 if (status & Y2_IS_TIST_OV)
cd28ab6a 2085 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2086
2087 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2088 u16 pci_err;
2089
56a645cc 2090 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2091 if (net_ratelimit())
2092 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2093 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2094
2095 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2096 sky2_pci_write16(hw, PCI_STATUS,
793b883e 2097 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2098 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2099 }
2100
2101 if (status & Y2_IS_PCI_EXP) {
d571b694 2102 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2103 u32 pex_err;
2104
56a645cc 2105 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2106
3be92a70
SH		 2107 if (net_ratelimit())
2108 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2109 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2110
2111 /* clear the interrupt */
2112 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2113 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
793b883e 2114 0xffffffffUL);
cd28ab6a
SH		 2115 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2116
2117 if (pex_err & PEX_FATAL_ERRORS) {
2118 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2119 hwmsk &= ~Y2_IS_PCI_EXP;
2120 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2121 }
2122 }
2123
2124 if (status & Y2_HWE_L1_MASK)
2125 sky2_hw_error(hw, 0, status);
2126 status >>= 8;
2127 if (status & Y2_HWE_L1_MASK)
2128 sky2_hw_error(hw, 1, status);
2129}
2130
2131static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2132{
2133 struct net_device *dev = hw->dev[port];
2134 struct sky2_port *sky2 = netdev_priv(dev);
2135 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2136
2137 if (netif_msg_intr(sky2))
2138 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2139 dev->name, status);
2140
2141 if (status & GM_IS_RX_FF_OR) {
2142 ++sky2->net_stats.rx_fifo_errors;
2143 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2144 }
2145
2146 if (status & GM_IS_TX_FF_UR) {
2147 ++sky2->net_stats.tx_fifo_errors;
2148 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2149 }
cd28ab6a
SH		 2150}
2151
d257924e
SH		 2152/* This should never happen it is a fatal situation */
2153static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2154 const char *rxtx, u32 mask)
2155{
2156 struct net_device *dev = hw->dev[port];
2157 struct sky2_port *sky2 = netdev_priv(dev);
2158 u32 imask;
2159
2160 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2161 dev ? dev->name : "<not registered>", rxtx);
2162
2163 imask = sky2_read32(hw, B0_IMSK);
2164 imask &= ~mask;
2165 sky2_write32(hw, B0_IMSK, imask);
2166
2167 if (dev) {
2168 spin_lock(&sky2->phy_lock);
2169 sky2_link_down(sky2);
2170 spin_unlock(&sky2->phy_lock);
2171 }
2172}
cd28ab6a 2173
d27ed387
SH		 2174/* If idle then force a fake soft NAPI poll once a second
2175 * to work around cases where sharing an edge triggered interrupt.
2176 */
eb35cf60
SH		 2177static inline void sky2_idle_start(struct sky2_hw *hw)
2178{
2179 if (idle_timeout > 0)
2180 mod_timer(&hw->idle_timer,
2181 jiffies + msecs_to_jiffies(idle_timeout));
2182}
2183
d27ed387
SH		 2184static void sky2_idle(unsigned long arg)
2185{
01bd7564
SH		 2186 struct sky2_hw *hw = (struct sky2_hw *) arg;
2187 struct net_device *dev = hw->dev[0];
d27ed387 2188
d27ed387
SH		 2189 if (__netif_rx_schedule_prep(dev))
2190 __netif_rx_schedule(dev);
01bd7564
SH		 2191
2192 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2193}
2194
2195
e07b1aa8 2196static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2197{
e07b1aa8
SH		 2198 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2199 int work_limit = min(dev0->quota, *budget);
2200 int work_done = 0;
fb2690a9 2201 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2202
1e5f1283
SH		 2203 if (status & Y2_IS_HW_ERR)
2204 sky2_hw_intr(hw);
d257924e 2205
1e5f1283
SH		 2206 if (status & Y2_IS_IRQ_PHY1)
2207 sky2_phy_intr(hw, 0);
cd28ab6a 2208
1e5f1283
SH		 2209 if (status & Y2_IS_IRQ_PHY2)
2210 sky2_phy_intr(hw, 1);
cd28ab6a 2211
1e5f1283
SH		 2212 if (status & Y2_IS_IRQ_MAC1)
2213 sky2_mac_intr(hw, 0);
cd28ab6a 2214
1e5f1283
SH		 2215 if (status & Y2_IS_IRQ_MAC2)
2216 sky2_mac_intr(hw, 1);
cd28ab6a 2217
1e5f1283
SH		 2218 if (status & Y2_IS_CHK_RX1)
2219 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2220
1e5f1283
SH		 2221 if (status & Y2_IS_CHK_RX2)
2222 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2223
1e5f1283
SH		 2224 if (status & Y2_IS_CHK_TXA1)
2225 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2226
1e5f1283
SH		 2227 if (status & Y2_IS_CHK_TXA2)
2228 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2229
1e5f1283 2230 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2231 if (work_done < work_limit) {
2232 netif_rx_complete(dev0);
86fba634 2233
fe2a24df
SH		 2234 sky2_read32(hw, B0_Y2_SP_LISR);
2235 return 0;
2236 } else {
2237 *budget -= work_done;
2238 dev0->quota -= work_done;
1e5f1283 2239 return 1;
fe2a24df 2240 }
e07b1aa8
SH		 2241}
2242
2243static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2244{
2245 struct sky2_hw *hw = dev_id;
2246 struct net_device *dev0 = hw->dev[0];
2247 u32 status;
2248
2249 /* Reading this mask interrupts as side effect */
2250 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2251 if (status == 0 || status == ~0)
2252 return IRQ_NONE;
793b883e 2253
e07b1aa8
SH		 2254 prefetch(&hw->st_le[hw->st_idx]);
2255 if (likely(__netif_rx_schedule_prep(dev0)))
2256 __netif_rx_schedule(dev0);
793b883e 2257
cd28ab6a
SH		 2258 return IRQ_HANDLED;
2259}
2260
2261#ifdef CONFIG_NET_POLL_CONTROLLER
2262static void sky2_netpoll(struct net_device *dev)
2263{
2264 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2265 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2266
88d11360
SH		 2267 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2268 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2269}
2270#endif
2271
2272/* Chip internal frequency for clock calculations */
fb17358f 2273static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2274{
793b883e 2275 switch (hw->chip_id) {
cd28ab6a 2276 case CHIP_ID_YUKON_EC:
5a5b1ea0 2277 case CHIP_ID_YUKON_EC_U:
fb17358f 2278 return 125; /* 125 Mhz */
cd28ab6a 2279 case CHIP_ID_YUKON_FE:
fb17358f 2280 return 100; /* 100 Mhz */
793b883e 2281 default: /* YUKON_XL */
fb17358f 2282 return 156; /* 156 Mhz */
cd28ab6a
SH		 2283 }
2284}
2285
fb17358f 2286static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2287{
fb17358f 2288 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2289}
2290
fb17358f 2291static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2292{
fb17358f 2293 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2294}
2295
fb17358f 2296
59139528 2297static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2298{
cd28ab6a
SH		 2299 u16 status;
2300 u8 t8, pmd_type;
56a645cc 2301 int i;
cd28ab6a 2302
cd28ab6a 2303 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2304
cd28ab6a
SH		 2305 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2306 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2307 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2308 pci_name(hw->pdev), hw->chip_id);
2309 return -EOPNOTSUPP;
2310 }
2311
290d4de5
SH		 2312 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2313
2314 /* This rev is really old, and requires untested workarounds */
2315 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2316 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2317 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2318 hw->chip_id, hw->chip_rev);
2319 return -EOPNOTSUPP;
2320 }
2321
cd28ab6a
SH		 2322 /* disable ASF */
2323 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2324 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2325 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2326 }
2327
2328 /* do a SW reset */
2329 sky2_write8(hw, B0_CTST, CS_RST_SET);
2330 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2331
2332 /* clear PCI errors, if any */
56a645cc 2333 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2334
cd28ab6a 2335 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2336 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2337
cd28ab6a
SH		 2338
2339 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2340
2341 /* clear any PEX errors */
d89e1343 2342 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
56a645cc
SH		 2343 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2344
cd28ab6a
SH		 2345
2346 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2347 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2348
2349 hw->ports = 1;
2350 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2351 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2352 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2353 ++hw->ports;
2354 }
cd28ab6a 2355
5afa0a9c 2356 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2357
2358 for (i = 0; i < hw->ports; i++) {
2359 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2360 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2361 }
2362
2363 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2364
793b883e
SH		 2365 /* Clear I2C IRQ noise */
2366 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2367
2368 /* turn off hardware timer (unused) */
2369 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2370 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2371
cd28ab6a
SH		 2372 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2373
69634ee7
SH		 2374 /* Turn off descriptor polling */
2375 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2376
2377 /* Turn off receive timestamp */
2378 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2379 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2380
2381 /* enable the Tx Arbiters */
2382 for (i = 0; i < hw->ports; i++)
2383 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2384
2385 /* Initialize ram interface */
2386 for (i = 0; i < hw->ports; i++) {
793b883e 2387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2388
2389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2392 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2393 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2394 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2395 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2396 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2397 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2398 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2399 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2400 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2401 }
2402
cd28ab6a
SH		 2403 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2404
cd28ab6a
SH		 2405 for (i = 0; i < hw->ports; i++)
2406 sky2_phy_reset(hw, i);
cd28ab6a 2407
cd28ab6a
SH		 2408 memset(hw->st_le, 0, STATUS_LE_BYTES);
2409 hw->st_idx = 0;
2410
2411 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2412 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2413
2414 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2415 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2416
2417 /* Set the list last index */
793b883e 2418 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2419
290d4de5
SH		 2420 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2421 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2422
290d4de5
SH		 2423 /* set Status-FIFO ISR watermark */
2424 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2425 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2426 else
2427 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2428
290d4de5 2429 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2430 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2431 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2432
793b883e 2433 /* enable status unit */
cd28ab6a
SH		 2434 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2435
2436 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2437 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2438 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2439
2440 return 0;
2441}
2442
28bd181a 2443static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a
SH		 2444{
2445 u32 modes;
2446 if (hw->copper) {
793b883e
SH		 2447 modes = SUPPORTED_10baseT_Half
2448 | SUPPORTED_10baseT_Full
2449 | SUPPORTED_100baseT_Half
2450 | SUPPORTED_100baseT_Full
2451 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2452
2453 if (hw->chip_id != CHIP_ID_YUKON_FE)
2454 modes |= SUPPORTED_1000baseT_Half
793b883e 2455 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2456 } else
2457 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2458 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2459 return modes;
2460}
2461
793b883e 2462static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2463{
2464 struct sky2_port *sky2 = netdev_priv(dev);
2465 struct sky2_hw *hw = sky2->hw;
2466
2467 ecmd->transceiver = XCVR_INTERNAL;
2468 ecmd->supported = sky2_supported_modes(hw);
2469 ecmd->phy_address = PHY_ADDR_MARV;
2470 if (hw->copper) {
2471 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2472 | SUPPORTED_10baseT_Full
2473 | SUPPORTED_100baseT_Half
2474 | SUPPORTED_100baseT_Full
2475 | SUPPORTED_1000baseT_Half
2476 | SUPPORTED_1000baseT_Full
2477 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2478 ecmd->port = PORT_TP;
2479 } else
2480 ecmd->port = PORT_FIBRE;
2481
2482 ecmd->advertising = sky2->advertising;
2483 ecmd->autoneg = sky2->autoneg;
2484 ecmd->speed = sky2->speed;
2485 ecmd->duplex = sky2->duplex;
2486 return 0;
2487}
2488
2489static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2490{
2491 struct sky2_port *sky2 = netdev_priv(dev);
2492 const struct sky2_hw *hw = sky2->hw;
2493 u32 supported = sky2_supported_modes(hw);
2494
2495 if (ecmd->autoneg == AUTONEG_ENABLE) {
2496 ecmd->advertising = supported;
2497 sky2->duplex = -1;
2498 sky2->speed = -1;
2499 } else {
2500 u32 setting;
2501
793b883e 2502 switch (ecmd->speed) {
cd28ab6a
SH		 2503 case SPEED_1000:
2504 if (ecmd->duplex == DUPLEX_FULL)
2505 setting = SUPPORTED_1000baseT_Full;
2506 else if (ecmd->duplex == DUPLEX_HALF)
2507 setting = SUPPORTED_1000baseT_Half;
2508 else
2509 return -EINVAL;
2510 break;
2511 case SPEED_100:
2512 if (ecmd->duplex == DUPLEX_FULL)
2513 setting = SUPPORTED_100baseT_Full;
2514 else if (ecmd->duplex == DUPLEX_HALF)
2515 setting = SUPPORTED_100baseT_Half;
2516 else
2517 return -EINVAL;
2518 break;
2519
2520 case SPEED_10:
2521 if (ecmd->duplex == DUPLEX_FULL)
2522 setting = SUPPORTED_10baseT_Full;
2523 else if (ecmd->duplex == DUPLEX_HALF)
2524 setting = SUPPORTED_10baseT_Half;
2525 else
2526 return -EINVAL;
2527 break;
2528 default:
2529 return -EINVAL;
2530 }
2531
2532 if ((setting & supported) == 0)
2533 return -EINVAL;
2534
2535 sky2->speed = ecmd->speed;
2536 sky2->duplex = ecmd->duplex;
2537 }
2538
2539 sky2->autoneg = ecmd->autoneg;
2540 sky2->advertising = ecmd->advertising;
2541
1b537565
SH		 2542 if (netif_running(dev))
2543 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2544
2545 return 0;
2546}
2547
2548static void sky2_get_drvinfo(struct net_device *dev,
2549 struct ethtool_drvinfo *info)
2550{
2551 struct sky2_port *sky2 = netdev_priv(dev);
2552
2553 strcpy(info->driver, DRV_NAME);
2554 strcpy(info->version, DRV_VERSION);
2555 strcpy(info->fw_version, "N/A");
2556 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2557}
2558
2559static const struct sky2_stat {
793b883e
SH		 2560 char name[ETH_GSTRING_LEN];
2561 u16 offset;
cd28ab6a
SH		 2562} sky2_stats[] = {
2563 { "tx_bytes", GM_TXO_OK_HI },
2564 { "rx_bytes", GM_RXO_OK_HI },
2565 { "tx_broadcast", GM_TXF_BC_OK },
2566 { "rx_broadcast", GM_RXF_BC_OK },
2567 { "tx_multicast", GM_TXF_MC_OK },
2568 { "rx_multicast", GM_RXF_MC_OK },
2569 { "tx_unicast", GM_TXF_UC_OK },
2570 { "rx_unicast", GM_RXF_UC_OK },
2571 { "tx_mac_pause", GM_TXF_MPAUSE },
2572 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2573 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2574 { "late_collision",GM_TXF_LAT_COL },
2575 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2576 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2577 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2578
d2604540 2579 { "rx_short", GM_RXF_SHT },
cd28ab6a 2580 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2581 { "rx_64_byte_packets", GM_RXF_64B },
2582 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2583 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2584 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2585 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2586 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2587 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2588 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2589 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2590 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2591 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2592
2593 { "tx_64_byte_packets", GM_TXF_64B },
2594 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2595 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2596 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2597 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2598 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2599 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2600 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2601};
2602
cd28ab6a
SH		 2603static u32 sky2_get_rx_csum(struct net_device *dev)
2604{
2605 struct sky2_port *sky2 = netdev_priv(dev);
2606
2607 return sky2->rx_csum;
2608}
2609
2610static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2611{
2612 struct sky2_port *sky2 = netdev_priv(dev);
2613
2614 sky2->rx_csum = data;
793b883e 2615
cd28ab6a
SH		 2616 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2617 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2618
2619 return 0;
2620}
2621
2622static u32 sky2_get_msglevel(struct net_device *netdev)
2623{
2624 struct sky2_port *sky2 = netdev_priv(netdev);
2625 return sky2->msg_enable;
2626}
2627
9a7ae0a9
SH		 2628static int sky2_nway_reset(struct net_device *dev)
2629{
2630 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2631
2632 if (sky2->autoneg != AUTONEG_ENABLE)
2633 return -EINVAL;
2634
1b537565 2635 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2636
2637 return 0;
2638}
2639
793b883e 2640static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2641{
2642 struct sky2_hw *hw = sky2->hw;
2643 unsigned port = sky2->port;
2644 int i;
2645
2646 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2647 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2648 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2649 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2650
793b883e 2651 for (i = 2; i < count; i++)
cd28ab6a
SH		 2652 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2653}
2654
cd28ab6a
SH		 2655static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2656{
2657 struct sky2_port *sky2 = netdev_priv(netdev);
2658 sky2->msg_enable = value;
2659}
2660
2661static int sky2_get_stats_count(struct net_device *dev)
2662{
2663 return ARRAY_SIZE(sky2_stats);
2664}
2665
2666static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2667 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2668{
2669 struct sky2_port *sky2 = netdev_priv(dev);
2670
793b883e 2671 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2672}
2673
793b883e 2674static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2675{
2676 int i;
2677
2678 switch (stringset) {
2679 case ETH_SS_STATS:
2680 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2681 memcpy(data + i * ETH_GSTRING_LEN,
2682 sky2_stats[i].name, ETH_GSTRING_LEN);
2683 break;
2684 }
2685}
2686
2687/* Use hardware MIB variables for critical path statistics and
2688 * transmit feedback not reported at interrupt.
2689 * Other errors are accounted for in interrupt handler.
2690 */
2691static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2692{
2693 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2694 u64 data[13];
cd28ab6a 2695
793b883e 2696 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2697
2698 sky2->net_stats.tx_bytes = data[0];
2699 sky2->net_stats.rx_bytes = data[1];
2700 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2701 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2702 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2703 sky2->net_stats.collisions = data[10];
2704 sky2->net_stats.tx_aborted_errors = data[12];
2705
2706 return &sky2->net_stats;
2707}
2708
2709static int sky2_set_mac_address(struct net_device *dev, void *p)
2710{
2711 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2712 struct sky2_hw *hw = sky2->hw;
2713 unsigned port = sky2->port;
2714 const struct sockaddr *addr = p;
cd28ab6a
SH		 2715
2716 if (!is_valid_ether_addr(addr->sa_data))
2717 return -EADDRNOTAVAIL;
2718
cd28ab6a 2719 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2720 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2721 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2722 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2723 dev->dev_addr, ETH_ALEN);
1b537565 2724
a8ab1ec0
SH		 2725 /* virtual address for data */
2726 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2727
2728 /* physical address: used for pause frames */
2729 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2730
2731 return 0;
cd28ab6a
SH		 2732}
2733
2734static void sky2_set_multicast(struct net_device *dev)
2735{
2736 struct sky2_port *sky2 = netdev_priv(dev);
2737 struct sky2_hw *hw = sky2->hw;
2738 unsigned port = sky2->port;
2739 struct dev_mc_list *list = dev->mc_list;
2740 u16 reg;
2741 u8 filter[8];
2742
2743 memset(filter, 0, sizeof(filter));
2744
2745 reg = gma_read16(hw, port, GM_RX_CTRL);
2746 reg |= GM_RXCR_UCF_ENA;
2747
d571b694 2748 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2749 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2750 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2751 memset(filter, 0xff, sizeof(filter));
793b883e 2752 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2753 reg &= ~GM_RXCR_MCF_ENA;
2754 else {
2755 int i;
2756 reg |= GM_RXCR_MCF_ENA;
2757
2758 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2759 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2760 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2761 }
2762 }
2763
cd28ab6a 2764 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2765 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2766 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2767 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2768 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2769 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2770 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2771 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2772
2773 gma_write16(hw, port, GM_RX_CTRL, reg);
2774}
2775
2776/* Can have one global because blinking is controlled by
2777 * ethtool and that is always under RTNL mutex
2778 */
91c86df5 2779static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2780{
793b883e
SH		 2781 u16 pg;
2782
793b883e
SH		 2783 switch (hw->chip_id) {
2784 case CHIP_ID_YUKON_XL:
2785 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2786 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2787 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2788 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2789 PHY_M_LEDC_INIT_CTRL(7) |
2790 PHY_M_LEDC_STA1_CTRL(7) |
2791 PHY_M_LEDC_STA0_CTRL(7))
2792 : 0);
2793
2794 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2795 break;
2796
2797 default:
2798 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2799 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2800 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2801 PHY_M_LED_MO_10(MO_LED_ON) |
2802 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2803 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2804 PHY_M_LED_MO_RX(MO_LED_ON)
2805 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2806 PHY_M_LED_MO_10(MO_LED_OFF) |
2807 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2808 PHY_M_LED_MO_1000(MO_LED_OFF) |
2809 PHY_M_LED_MO_RX(MO_LED_OFF));
2810
793b883e 2811 }
cd28ab6a
SH		 2812}
2813
2814/* blink LED's for finding board */
2815static int sky2_phys_id(struct net_device *dev, u32 data)
2816{
2817 struct sky2_port *sky2 = netdev_priv(dev);
2818 struct sky2_hw *hw = sky2->hw;
2819 unsigned port = sky2->port;
793b883e 2820 u16 ledctrl, ledover = 0;
cd28ab6a 2821 long ms;
91c86df5 2822 int interrupted;
cd28ab6a
SH		 2823 int onoff = 1;
2824
793b883e 2825 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2826 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2827 else
2828 ms = data * 1000;
2829
2830 /* save initial values */
e07b1aa8 2831 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2832 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2833 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2834 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2835 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2836 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2837 } else {
2838 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2839 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2840 }
cd28ab6a 2841
91c86df5
SH		 2842 interrupted = 0;
2843 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2844 sky2_led(hw, port, onoff);
2845 onoff = !onoff;
2846
e07b1aa8 2847 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2848 interrupted = msleep_interruptible(250);
e07b1aa8 2849 spin_lock_bh(&sky2->phy_lock);
91c86df5 2850
cd28ab6a
SH		 2851 ms -= 250;
2852 }
2853
2854 /* resume regularly scheduled programming */
793b883e
SH		 2855 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2856 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2857 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2858 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2859 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2860 } else {
2861 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2862 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2863 }
e07b1aa8 2864 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2865
2866 return 0;
2867}
2868
2869static void sky2_get_pauseparam(struct net_device *dev,
2870 struct ethtool_pauseparam *ecmd)
2871{
2872 struct sky2_port *sky2 = netdev_priv(dev);
2873
2874 ecmd->tx_pause = sky2->tx_pause;
2875 ecmd->rx_pause = sky2->rx_pause;
2876 ecmd->autoneg = sky2->autoneg;
2877}
2878
2879static int sky2_set_pauseparam(struct net_device *dev,
2880 struct ethtool_pauseparam *ecmd)
2881{
2882 struct sky2_port *sky2 = netdev_priv(dev);
2883 int err = 0;
2884
2885 sky2->autoneg = ecmd->autoneg;
2886 sky2->tx_pause = ecmd->tx_pause != 0;
2887 sky2->rx_pause = ecmd->rx_pause != 0;
2888
1b537565 2889 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2890
2891 return err;
2892}
2893
fb17358f
SH		 2894static int sky2_get_coalesce(struct net_device *dev,
2895 struct ethtool_coalesce *ecmd)
2896{
2897 struct sky2_port *sky2 = netdev_priv(dev);
2898 struct sky2_hw *hw = sky2->hw;
2899
2900 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2901 ecmd->tx_coalesce_usecs = 0;
2902 else {
2903 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2904 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2905 }
2906 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2907
2908 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2909 ecmd->rx_coalesce_usecs = 0;
2910 else {
2911 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2912 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2913 }
2914 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2915
2916 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2917 ecmd->rx_coalesce_usecs_irq = 0;
2918 else {
2919 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2920 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2921 }
2922
2923 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2924
2925 return 0;
2926}
2927
2928/* Note: this affect both ports */
2929static int sky2_set_coalesce(struct net_device *dev,
2930 struct ethtool_coalesce *ecmd)
2931{
2932 struct sky2_port *sky2 = netdev_priv(dev);
2933 struct sky2_hw *hw = sky2->hw;
77b3d6a2 2934 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 2935
77b3d6a2
SH		 2936 if (ecmd->tx_coalesce_usecs > tmax ||
2937 ecmd->rx_coalesce_usecs > tmax ||
2938 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 2939 return -EINVAL;
2940
ff81fbbe 2941 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 2942 return -EINVAL;
ff81fbbe 2943 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 2944 return -EINVAL;
ff81fbbe 2945 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 2946 return -EINVAL;
2947
2948 if (ecmd->tx_coalesce_usecs == 0)
2949 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2950 else {
2951 sky2_write32(hw, STAT_TX_TIMER_INI,
2952 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2953 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2954 }
2955 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2956
2957 if (ecmd->rx_coalesce_usecs == 0)
2958 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2959 else {
2960 sky2_write32(hw, STAT_LEV_TIMER_INI,
2961 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2962 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2963 }
2964 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2965
2966 if (ecmd->rx_coalesce_usecs_irq == 0)
2967 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2968 else {
d28d4870 2969 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 2970 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2971 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2972 }
2973 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2974 return 0;
2975}
2976
793b883e
SH		 2977static void sky2_get_ringparam(struct net_device *dev,
2978 struct ethtool_ringparam *ering)
2979{
2980 struct sky2_port *sky2 = netdev_priv(dev);
2981
2982 ering->rx_max_pending = RX_MAX_PENDING;
2983 ering->rx_mini_max_pending = 0;
2984 ering->rx_jumbo_max_pending = 0;
2985 ering->tx_max_pending = TX_RING_SIZE - 1;
2986
2987 ering->rx_pending = sky2->rx_pending;
2988 ering->rx_mini_pending = 0;
2989 ering->rx_jumbo_pending = 0;
2990 ering->tx_pending = sky2->tx_pending;
2991}
2992
2993static int sky2_set_ringparam(struct net_device *dev,
2994 struct ethtool_ringparam *ering)
2995{
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 int err = 0;
2998
2999 if (ering->rx_pending > RX_MAX_PENDING ||
3000 ering->rx_pending < 8 ||
3001 ering->tx_pending < MAX_SKB_TX_LE ||
3002 ering->tx_pending > TX_RING_SIZE - 1)
3003 return -EINVAL;
3004
3005 if (netif_running(dev))
3006 sky2_down(dev);
3007
3008 sky2->rx_pending = ering->rx_pending;
3009 sky2->tx_pending = ering->tx_pending;
3010
1b537565 3011 if (netif_running(dev)) {
793b883e 3012 err = sky2_up(dev);
1b537565
SH		 3013 if (err)
3014 dev_close(dev);
6ed995bb
SH		 3015 else
3016 sky2_set_multicast(dev);
1b537565 3017 }
793b883e
SH		 3018
3019 return err;
3020}
3021
793b883e
SH		 3022static int sky2_get_regs_len(struct net_device *dev)
3023{
6e4cbb34 3024 return 0x4000;
793b883e
SH		 3025}
3026
3027/*
3028 * Returns copy of control register region
6e4cbb34 3029 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3030 */
3031static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3032 void *p)
3033{
3034 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3035 const void __iomem *io = sky2->hw->regs;
793b883e 3036
6e4cbb34 3037 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3038 regs->version = 1;
6e4cbb34 3039 memset(p, 0, regs->len);
793b883e 3040
6e4cbb34
SH		 3041 memcpy_fromio(p, io, B3_RAM_ADDR);
3042
3043 memcpy_fromio(p + B3_RI_WTO_R1,
3044 io + B3_RI_WTO_R1,
3045 regs->len - B3_RI_WTO_R1);
793b883e 3046}
cd28ab6a
SH		 3047
3048static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3049 .get_settings = sky2_get_settings,
3050 .set_settings = sky2_set_settings,
3051 .get_drvinfo = sky2_get_drvinfo,
3052 .get_msglevel = sky2_get_msglevel,
3053 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3054 .nway_reset = sky2_nway_reset,
793b883e
SH		 3055 .get_regs_len = sky2_get_regs_len,
3056 .get_regs = sky2_get_regs,
3057 .get_link = ethtool_op_get_link,
3058 .get_sg = ethtool_op_get_sg,
3059 .set_sg = ethtool_op_set_sg,
3060 .get_tx_csum = ethtool_op_get_tx_csum,
3061 .set_tx_csum = ethtool_op_set_tx_csum,
3062 .get_tso = ethtool_op_get_tso,
3063 .set_tso = ethtool_op_set_tso,
3064 .get_rx_csum = sky2_get_rx_csum,
3065 .set_rx_csum = sky2_set_rx_csum,
3066 .get_strings = sky2_get_strings,
fb17358f
SH		 3067 .get_coalesce = sky2_get_coalesce,
3068 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3069 .get_ringparam = sky2_get_ringparam,
3070 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3071 .get_pauseparam = sky2_get_pauseparam,
3072 .set_pauseparam = sky2_set_pauseparam,
793b883e 3073 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3074 .get_stats_count = sky2_get_stats_count,
3075 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3076 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3077};
3078
3079/* Initialize network device */
3080static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3081 unsigned port, int highmem)
3082{
3083 struct sky2_port *sky2;
3084 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3085
3086 if (!dev) {
3087 printk(KERN_ERR "sky2 etherdev alloc failed");
3088 return NULL;
3089 }
3090
3091 SET_MODULE_OWNER(dev);
3092 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3093 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3094 dev->open = sky2_up;
3095 dev->stop = sky2_down;
ef743d33 3096 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3097 dev->hard_start_xmit = sky2_xmit_frame;
3098 dev->get_stats = sky2_get_stats;
3099 dev->set_multicast_list = sky2_set_multicast;
3100 dev->set_mac_address = sky2_set_mac_address;
3101 dev->change_mtu = sky2_change_mtu;
3102 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3103 dev->tx_timeout = sky2_tx_timeout;
3104 dev->watchdog_timeo = TX_WATCHDOG;
3105 if (port == 0)
3106 dev->poll = sky2_poll;
3107 dev->weight = NAPI_WEIGHT;
3108#ifdef CONFIG_NET_POLL_CONTROLLER
3109 dev->poll_controller = sky2_netpoll;
3110#endif
cd28ab6a
SH		 3111
3112 sky2 = netdev_priv(dev);
3113 sky2->netdev = dev;
3114 sky2->hw = hw;
3115 sky2->msg_enable = netif_msg_init(debug, default_msg);
3116
3117 spin_lock_init(&sky2->tx_lock);
3118 /* Auto speed and flow control */
3119 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3120 sky2->tx_pause = 1;
cd28ab6a
SH		 3121 sky2->rx_pause = 1;
3122 sky2->duplex = -1;
3123 sky2->speed = -1;
3124 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3125 sky2->rx_csum = 1;
75d070c5 3126
e07b1aa8 3127 spin_lock_init(&sky2->phy_lock);
793b883e 3128 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3129 sky2->rx_pending = RX_DEF_PENDING;
734d1868 3130 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
cd28ab6a
SH		 3131
3132 hw->dev[port] = dev;
3133
3134 sky2->port = port;
3135
5a5b1ea0
SH		 3136 dev->features |= NETIF_F_LLTX;
3137 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3138 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3139 if (highmem)
3140 dev->features |= NETIF_F_HIGHDMA;
793b883e 3141 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3142
d1f13708
SH		 3143#ifdef SKY2_VLAN_TAG_USED
3144 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3145 dev->vlan_rx_register = sky2_vlan_rx_register;
3146 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3147#endif
3148
cd28ab6a 3149 /* read the mac address */
793b883e 3150 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3151 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3152
3153 /* device is off until link detection */
3154 netif_carrier_off(dev);
3155 netif_stop_queue(dev);
3156
3157 return dev;
3158}
3159
28bd181a 3160static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3161{
3162 const struct sky2_port *sky2 = netdev_priv(dev);
3163
3164 if (netif_msg_probe(sky2))
3165 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3166 dev->name,
3167 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3168 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3169}
3170
fb2690a9
SH		 3171/* Handle software interrupt used during MSI test */
3172static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3173 struct pt_regs *regs)
3174{
3175 struct sky2_hw *hw = dev_id;
3176 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3177
3178 if (status == 0)
3179 return IRQ_NONE;
3180
3181 if (status & Y2_IS_IRQ_SW) {
3182 hw->msi_detected = 1;
3183 wake_up(&hw->msi_wait);
3184 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3185 }
3186 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3187
3188 return IRQ_HANDLED;
3189}
3190
3191/* Test interrupt path by forcing a a software IRQ */
3192static int __devinit sky2_test_msi(struct sky2_hw *hw)
3193{
3194 struct pci_dev *pdev = hw->pdev;
3195 int err;
3196
bb507fe1
SH		 3197 init_waitqueue_head (&hw->msi_wait);
3198
fb2690a9
SH		 3199 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3200
1fb9df5d 3201 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3202 if (err) {
3203 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3204 pci_name(pdev), pdev->irq);
3205 return err;
3206 }
3207
fb2690a9 3208 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3209 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3210
3211 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3212
3213 if (!hw->msi_detected) {
3214 /* MSI test failed, go back to INTx mode */
3215 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3216 "switching to INTx mode. Please report this failure to "
3217 "the PCI maintainer and include system chipset information.\n",
3218 pci_name(pdev));
3219
3220 err = -EOPNOTSUPP;
3221 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3222 }
3223
3224 sky2_write32(hw, B0_IMSK, 0);
3225
3226 free_irq(pdev->irq, hw);
3227
3228 return err;
3229}
3230
cd28ab6a
SH		 3231static int __devinit sky2_probe(struct pci_dev *pdev,
3232 const struct pci_device_id *ent)
3233{
793b883e 3234 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3235 struct sky2_hw *hw;
5afa0a9c 3236 int err, pm_cap, using_dac = 0;
cd28ab6a 3237
793b883e
SH		 3238 err = pci_enable_device(pdev);
3239 if (err) {
cd28ab6a
SH		 3240 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3241 pci_name(pdev));
3242 goto err_out;
3243 }
3244
793b883e
SH		 3245 err = pci_request_regions(pdev, DRV_NAME);
3246 if (err) {
cd28ab6a
SH		 3247 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3248 pci_name(pdev));
793b883e 3249 goto err_out;
cd28ab6a
SH		 3250 }
3251
3252 pci_set_master(pdev);
3253
5afa0a9c
SH		 3254 /* Find power-management capability. */
3255 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3256 if (pm_cap == 0) {
3257 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3258 "aborting.\n");
3259 err = -EIO;
3260 goto err_out_free_regions;
3261 }
3262
d1f3d4dd
SH		 3263 if (sizeof(dma_addr_t) > sizeof(u32) &&
3264 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3265 using_dac = 1;
3266 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3267 if (err < 0) {
3268 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3269 "for consistent allocations\n", pci_name(pdev));
3270 goto err_out_free_regions;
3271 }
cd28ab6a 3272
d1f3d4dd 3273 } else {
cd28ab6a
SH		 3274 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3275 if (err) {
3276 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3277 pci_name(pdev));
3278 goto err_out_free_regions;
3279 }
3280 }
d1f3d4dd 3281
cd28ab6a 3282 err = -ENOMEM;
6aad85d6 3283 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3284 if (!hw) {
3285 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3286 pci_name(pdev));
3287 goto err_out_free_regions;
3288 }
3289
cd28ab6a 3290 hw->pdev = pdev;
cd28ab6a
SH		 3291
3292 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3293 if (!hw->regs) {
3294 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3295 pci_name(pdev));
3296 goto err_out_free_hw;
3297 }
5afa0a9c 3298 hw->pm_cap = pm_cap;
cd28ab6a 3299
56a645cc
SH		 3300#ifdef __BIG_ENDIAN
3301 /* byte swap descriptors in hardware */
3302 {
3303 u32 reg;
3304
3305 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3306 reg |= PCI_REV_DESC;
3307 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3308 }
3309#endif
3310
08c06d8a
SH		 3311 /* ring for status responses */
3312 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3313 &hw->st_dma);
3314 if (!hw->st_le)
3315 goto err_out_iounmap;
3316
cd28ab6a
SH		 3317 err = sky2_reset(hw);
3318 if (err)
793b883e 3319 goto err_out_iounmap;
cd28ab6a 3320
7c7459d1
GKH		 3321 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3322 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3323 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3324 hw->chip_id, hw->chip_rev);
cd28ab6a 3325
793b883e
SH		 3326 dev = sky2_init_netdev(hw, 0, using_dac);
3327 if (!dev)
cd28ab6a
SH		 3328 goto err_out_free_pci;
3329
793b883e
SH		 3330 err = register_netdev(dev);
3331 if (err) {
cd28ab6a
SH		 3332 printk(KERN_ERR PFX "%s: cannot register net device\n",
3333 pci_name(pdev));
3334 goto err_out_free_netdev;
3335 }
3336
3337 sky2_show_addr(dev);
3338
3339 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3340 if (register_netdev(dev1) == 0)
3341 sky2_show_addr(dev1);
3342 else {
3343 /* Failure to register second port need not be fatal */
793b883e
SH		 3344 printk(KERN_WARNING PFX
3345 "register of second port failed\n");
cd28ab6a
SH		 3346 hw->dev[1] = NULL;
3347 free_netdev(dev1);
3348 }
3349 }
3350
fb2690a9
SH		 3351 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3352 err = sky2_test_msi(hw);
3353 if (err == -EOPNOTSUPP)
3354 pci_disable_msi(pdev);
3355 else if (err)
3356 goto err_out_unregister;
3357 }
3358
1fb9df5d 3359 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
793b883e
SH		 3360 if (err) {
3361 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3362 pci_name(pdev), pdev->irq);
3363 goto err_out_unregister;
3364 }
3365
e07b1aa8 3366 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
793b883e 3367
01bd7564 3368 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3369 sky2_idle_start(hw);
d27ed387 3370
793b883e
SH		 3371 pci_set_drvdata(pdev, hw);
3372
cd28ab6a
SH		 3373 return 0;
3374
793b883e 3375err_out_unregister:
fb2690a9 3376 pci_disable_msi(pdev);
793b883e
SH		 3377 if (dev1) {
3378 unregister_netdev(dev1);
3379 free_netdev(dev1);
3380 }
3381 unregister_netdev(dev);
cd28ab6a
SH		 3382err_out_free_netdev:
3383 free_netdev(dev);
cd28ab6a 3384err_out_free_pci:
793b883e 3385 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3386 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3387err_out_iounmap:
3388 iounmap(hw->regs);
3389err_out_free_hw:
3390 kfree(hw);
3391err_out_free_regions:
3392 pci_release_regions(pdev);
cd28ab6a 3393 pci_disable_device(pdev);
cd28ab6a
SH		 3394err_out:
3395 return err;
3396}
3397
3398static void __devexit sky2_remove(struct pci_dev *pdev)
3399{
793b883e 3400 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3401 struct net_device *dev0, *dev1;
3402
793b883e 3403 if (!hw)
cd28ab6a
SH		 3404 return;
3405
d27ed387
SH		 3406 del_timer_sync(&hw->idle_timer);
3407
3408 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3409 synchronize_irq(hw->pdev->irq);
3410
cd28ab6a 3411 dev0 = hw->dev[0];
793b883e
SH		 3412 dev1 = hw->dev[1];
3413 if (dev1)
3414 unregister_netdev(dev1);
cd28ab6a
SH		 3415 unregister_netdev(dev0);
3416
5afa0a9c 3417 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3418 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3419 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3420 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3421
3422 free_irq(pdev->irq, hw);
fb2690a9 3423 pci_disable_msi(pdev);
793b883e 3424 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3425 pci_release_regions(pdev);
3426 pci_disable_device(pdev);
793b883e 3427
cd28ab6a
SH		 3428 if (dev1)
3429 free_netdev(dev1);
3430 free_netdev(dev0);
3431 iounmap(hw->regs);
3432 kfree(hw);
5afa0a9c 3433
cd28ab6a
SH		 3434 pci_set_drvdata(pdev, NULL);
3435}
3436
3437#ifdef CONFIG_PM
3438static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3439{
793b883e 3440 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3441 int i;
2ccc99b7
SH		 3442 pci_power_t pstate = pci_choose_state(pdev, state);
3443
3444 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3445 return -EINVAL;
cd28ab6a 3446
eb35cf60 3447 del_timer_sync(&hw->idle_timer);
6a5706b9 3448 netif_poll_disable(hw->dev[0]);
eb35cf60 3449
f05267e7 3450 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3451 struct net_device *dev = hw->dev[i];
3452
6a5706b9 3453 if (netif_running(dev)) {
5afa0a9c 3454 sky2_down(dev);
cd28ab6a 3455 netif_device_detach(dev);
cd28ab6a
SH		 3456 }
3457 }
3458
8ab8fca2 3459 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3460 pci_save_state(pdev);
2ccc99b7
SH		 3461 sky2_set_power_state(hw, pstate);
3462 return 0;
cd28ab6a
SH		 3463}
3464
3465static int sky2_resume(struct pci_dev *pdev)
3466{
793b883e 3467 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3468 int i, err;
cd28ab6a 3469
cd28ab6a
SH		 3470 pci_restore_state(pdev);
3471 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3472 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3473
08c06d8a
SH		 3474 err = sky2_reset(hw);
3475 if (err)
3476 goto out;
cd28ab6a 3477
8ab8fca2
SH		 3478 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3479
f05267e7 3480 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3481 struct net_device *dev = hw->dev[i];
6a5706b9 3482 if (netif_running(dev)) {
08c06d8a 3483 netif_device_attach(dev);
88d11360 3484
08c06d8a
SH		 3485 err = sky2_up(dev);
3486 if (err) {
3487 printk(KERN_ERR PFX "%s: could not up: %d\n",
3488 dev->name, err);
3489 dev_close(dev);
eb35cf60 3490 goto out;
5afa0a9c 3491 }
cd28ab6a
SH		 3492 }
3493 }
eb35cf60 3494
6a5706b9 3495 netif_poll_enable(hw->dev[0]);
eb35cf60 3496 sky2_idle_start(hw);
08c06d8a
SH		 3497out:
3498 return err;
cd28ab6a
SH		 3499}
3500#endif
3501
3502static struct pci_driver sky2_driver = {
793b883e
SH		 3503 .name = DRV_NAME,
3504 .id_table = sky2_id_table,
3505 .probe = sky2_probe,
3506 .remove = __devexit_p(sky2_remove),
cd28ab6a 3507#ifdef CONFIG_PM
793b883e
SH		 3508 .suspend = sky2_suspend,
3509 .resume = sky2_resume,
cd28ab6a
SH		 3510#endif
3511};
3512
3513static int __init sky2_init_module(void)
3514{
50241c4c 3515 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3516}
3517
3518static void __exit sky2_cleanup_module(void)
3519{
3520 pci_unregister_driver(&sky2_driver);
3521}
3522
3523module_init(sky2_init_module);
3524module_exit(sky2_cleanup_module);
3525
3526MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3527MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3528MODULE_LICENSE("GPL");
5f4f9dc1 3529MODULE_VERSION(DRV_VERSION);
Clone of davem's net-next-2.6 tree