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baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
f15063cd
JP		 26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
14c85021 28#include <linux/in.h>
baef58b1
SH		 29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
4075400b 40#include <linux/dma-mapping.h>
678aa1f6 41#include <linux/debugfs.h>
d43c36dc 42#include <linux/sched.h>
678aa1f6 43#include <linux/seq_file.h>
2cd8e5d3 44#include <linux/mii.h>
baef58b1
SH		 45#include <asm/irq.h>
46
47#include "skge.h"
48
49#define DRV_NAME "skge"
bf9f56d5 50#define DRV_VERSION "1.13"
baef58b1
SH		 51
52#define DEFAULT_TX_RING_SIZE 128
53#define DEFAULT_RX_RING_SIZE 512
54#define MAX_TX_RING_SIZE 1024
9db96479 55#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 56#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 57#define RX_COPY_THRESHOLD 128
58#define RX_BUF_SIZE 1536
baef58b1
SH		 59#define PHY_RETRIES 1000
60#define ETH_JUMBO_MTU 9000
61#define TX_WATCHDOG (5 * HZ)
62#define NAPI_WEIGHT 64
6abebb53 63#define BLINK_MS 250
501fb72d 64#define LINK_HZ HZ
baef58b1 65
afa151b9
SH		 66#define SKGE_EEPROM_MAGIC 0x9933aabb
67
68
baef58b1 69MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 70MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 71MODULE_LICENSE("GPL");
72MODULE_VERSION(DRV_VERSION);
73
67777f9b
JP		 74static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
75 NETIF_MSG_LINK | NETIF_MSG_IFUP |
76 NETIF_MSG_IFDOWN);
baef58b1
SH		 77
78static int debug = -1; /* defaults above */
79module_param(debug, int, 0);
80MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
81
a3aa1884 82static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
275834d1
SH		 83 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
84 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
85 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
86 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 87 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 88 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 89 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
90 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
91 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 92 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 93 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 94 { 0 }
95};
96MODULE_DEVICE_TABLE(pci, skge_id_table);
97
98static int skge_up(struct net_device *dev);
99static int skge_down(struct net_device *dev);
ee294dcd 100static void skge_phy_reset(struct skge_port *skge);
513f533e 101static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 102static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
103static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 104static void genesis_get_stats(struct skge_port *skge, u64 *data);
105static void yukon_get_stats(struct skge_port *skge, u64 *data);
106static void yukon_init(struct skge_hw *hw, int port);
baef58b1 107static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 108static void genesis_link_up(struct skge_port *skge);
f80d032b 109static void skge_set_multicast(struct net_device *dev);
baef58b1 110
7e676d91 111/* Avoid conditionals by using array */
baef58b1
SH		 112static const int txqaddr[] = { Q_XA1, Q_XA2 };
113static const int rxqaddr[] = { Q_R1, Q_R2 };
114static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
115static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 116static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
117static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 118
baef58b1
SH		 119static int skge_get_regs_len(struct net_device *dev)
120{
c3f8be96 121 return 0x4000;
baef58b1
SH		 122}
123
124/*
c3f8be96
SH		 125 * Returns copy of whole control register region
126 * Note: skip RAM address register because accessing it will
127 * cause bus hangs!
baef58b1
SH		 128 */
129static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
130 void *p)
131{
132 const struct skge_port *skge = netdev_priv(dev);
baef58b1 133 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 134
135 regs->version = 1;
c3f8be96
SH		 136 memset(p, 0, regs->len);
137 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 138
c3f8be96
SH		 139 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
140 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 141}
142
8f3f8193 143/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 144static u32 wol_supported(const struct skge_hw *hw)
baef58b1 145{
d17ecb23 146 if (hw->chip_id == CHIP_ID_GENESIS)
a504e64a 147 return 0;
d17ecb23
SH		 148
149 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
150 return 0;
151
152 return WAKE_MAGIC | WAKE_PHY;
a504e64a
SH		 153}
154
a504e64a
SH		 155static void skge_wol_init(struct skge_port *skge)
156{
157 struct skge_hw *hw = skge->hw;
158 int port = skge->port;
692412b3 159 u16 ctrl;
a504e64a 160
a504e64a
SH		 161 skge_write16(hw, B0_CTST, CS_RST_CLR);
162 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
163
692412b3
SH		 164 /* Turn on Vaux */
165 skge_write8(hw, B0_POWER_CTRL,
166 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
a504e64a 167
692412b3
SH		 168 /* WA code for COMA mode -- clear PHY reset */
169 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
170 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
171 u32 reg = skge_read32(hw, B2_GP_IO);
172 reg |= GP_DIR_9;
173 reg &= ~GP_IO_9;
174 skge_write32(hw, B2_GP_IO, reg);
175 }
a504e64a 176
692412b3
SH		 177 skge_write32(hw, SK_REG(port, GPHY_CTRL),
178 GPC_DIS_SLEEP |
179 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
180 GPC_ANEG_1 | GPC_RST_SET);
a504e64a 181
692412b3
SH		 182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_DIS_SLEEP |
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_CLR);
186
187 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
188
189 /* Force to 10/100 skge_reset will re-enable on resume */
190 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
67777f9b
JP		 191 (PHY_AN_100FULL | PHY_AN_100HALF |
192 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
692412b3
SH		 193 /* no 1000 HD/FD */
194 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
195 gm_phy_write(hw, port, PHY_MARV_CTRL,
196 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
197 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
a504e64a 198
a504e64a
SH		 199
200 /* Set GMAC to no flow control and auto update for speed/duplex */
201 gma_write16(hw, port, GM_GP_CTRL,
202 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
203 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
204
205 /* Set WOL address */
206 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
207 skge->netdev->dev_addr, ETH_ALEN);
208
209 /* Turn on appropriate WOL control bits */
210 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
211 ctrl = 0;
212 if (skge->wol & WAKE_PHY)
213 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
214 else
215 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
216
217 if (skge->wol & WAKE_MAGIC)
218 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
219 else
a419aef8 220 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
a504e64a
SH		 221
222 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
223 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
224
225 /* block receiver */
226 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 227}
228
229static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
230{
231 struct skge_port *skge = netdev_priv(dev);
232
a504e64a
SH		 233 wol->supported = wol_supported(skge->hw);
234 wol->wolopts = skge->wol;
baef58b1
SH		 235}
236
237static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
238{
239 struct skge_port *skge = netdev_priv(dev);
240 struct skge_hw *hw = skge->hw;
241
8e95a202
JP		 242 if ((wol->wolopts & ~wol_supported(hw)) ||
243 !device_can_wakeup(&hw->pdev->dev))
baef58b1
SH		 244 return -EOPNOTSUPP;
245
a504e64a 246 skge->wol = wol->wolopts;
5177b324
RW		 247
248 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
249
baef58b1
SH		 250 return 0;
251}
252
8f3f8193
SH		 253/* Determine supported/advertised modes based on hardware.
254 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 255 */
256static u32 skge_supported_modes(const struct skge_hw *hw)
257{
258 u32 supported;
259
5e1705dd 260 if (hw->copper) {
67777f9b
JP		 261 supported = (SUPPORTED_10baseT_Half |
262 SUPPORTED_10baseT_Full |
263 SUPPORTED_100baseT_Half |
264 SUPPORTED_100baseT_Full |
265 SUPPORTED_1000baseT_Half |
266 SUPPORTED_1000baseT_Full |
267 SUPPORTED_Autoneg |
268 SUPPORTED_TP);
31b619c5
SH		 269
270 if (hw->chip_id == CHIP_ID_GENESIS)
67777f9b
JP		 271 supported &= ~(SUPPORTED_10baseT_Half |
272 SUPPORTED_10baseT_Full |
273 SUPPORTED_100baseT_Half |
274 SUPPORTED_100baseT_Full);
31b619c5
SH		 275
276 else if (hw->chip_id == CHIP_ID_YUKON)
277 supported &= ~SUPPORTED_1000baseT_Half;
278 } else
67777f9b
JP		 279 supported = (SUPPORTED_1000baseT_Full |
280 SUPPORTED_1000baseT_Half |
281 SUPPORTED_FIBRE |
282 SUPPORTED_Autoneg);
31b619c5
SH		 283
284 return supported;
285}
baef58b1
SH		 286
287static int skge_get_settings(struct net_device *dev,
288 struct ethtool_cmd *ecmd)
289{
290 struct skge_port *skge = netdev_priv(dev);
291 struct skge_hw *hw = skge->hw;
292
293 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 294 ecmd->supported = skge_supported_modes(hw);
baef58b1 295
5e1705dd 296 if (hw->copper) {
baef58b1
SH		 297 ecmd->port = PORT_TP;
298 ecmd->phy_address = hw->phy_addr;
31b619c5 299 } else
baef58b1 300 ecmd->port = PORT_FIBRE;
baef58b1
SH		 301
302 ecmd->advertising = skge->advertising;
303 ecmd->autoneg = skge->autoneg;
304 ecmd->speed = skge->speed;
305 ecmd->duplex = skge->duplex;
306 return 0;
307}
308
baef58b1
SH		 309static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
310{
311 struct skge_port *skge = netdev_priv(dev);
312 const struct skge_hw *hw = skge->hw;
31b619c5 313 u32 supported = skge_supported_modes(hw);
9ac1353f 314 int err = 0;
baef58b1
SH		 315
316 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 317 ecmd->advertising = supported;
318 skge->duplex = -1;
319 skge->speed = -1;
baef58b1 320 } else {
31b619c5
SH		 321 u32 setting;
322
2c668514 323 switch (ecmd->speed) {
baef58b1 324 case SPEED_1000:
31b619c5
SH		 325 if (ecmd->duplex == DUPLEX_FULL)
326 setting = SUPPORTED_1000baseT_Full;
327 else if (ecmd->duplex == DUPLEX_HALF)
328 setting = SUPPORTED_1000baseT_Half;
329 else
330 return -EINVAL;
baef58b1
SH		 331 break;
332 case SPEED_100:
31b619c5
SH		 333 if (ecmd->duplex == DUPLEX_FULL)
334 setting = SUPPORTED_100baseT_Full;
335 else if (ecmd->duplex == DUPLEX_HALF)
336 setting = SUPPORTED_100baseT_Half;
337 else
338 return -EINVAL;
339 break;
340
baef58b1 341 case SPEED_10:
31b619c5
SH		 342 if (ecmd->duplex == DUPLEX_FULL)
343 setting = SUPPORTED_10baseT_Full;
344 else if (ecmd->duplex == DUPLEX_HALF)
345 setting = SUPPORTED_10baseT_Half;
346 else
baef58b1
SH		 347 return -EINVAL;
348 break;
349 default:
350 return -EINVAL;
351 }
31b619c5
SH		 352
353 if ((setting & supported) == 0)
354 return -EINVAL;
355
356 skge->speed = ecmd->speed;
357 skge->duplex = ecmd->duplex;
baef58b1
SH		 358 }
359
360 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 361 skge->advertising = ecmd->advertising;
362
9ac1353f
XZ		 363 if (netif_running(dev)) {
364 skge_down(dev);
365 err = skge_up(dev);
366 if (err) {
367 dev_close(dev);
368 return err;
369 }
370 }
ee294dcd 371
67777f9b 372 return 0;
baef58b1
SH		 373}
374
375static void skge_get_drvinfo(struct net_device *dev,
376 struct ethtool_drvinfo *info)
377{
378 struct skge_port *skge = netdev_priv(dev);
379
380 strcpy(info->driver, DRV_NAME);
381 strcpy(info->version, DRV_VERSION);
382 strcpy(info->fw_version, "N/A");
383 strcpy(info->bus_info, pci_name(skge->hw->pdev));
384}
385
386static const struct skge_stat {
387 char name[ETH_GSTRING_LEN];
388 u16 xmac_offset;
389 u16 gma_offset;
390} skge_stats[] = {
391 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
392 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
393
394 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
395 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
396 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
397 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
398 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
399 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
400 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
401 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
402
403 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
404 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
405 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
406 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
407 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
408 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
409
410 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
411 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
412 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
413 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
414 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
415};
416
b9f2c044 417static int skge_get_sset_count(struct net_device *dev, int sset)
baef58b1 418{
b9f2c044
JG		 419 switch (sset) {
420 case ETH_SS_STATS:
421 return ARRAY_SIZE(skge_stats);
422 default:
423 return -EOPNOTSUPP;
424 }
baef58b1
SH		 425}
426
427static void skge_get_ethtool_stats(struct net_device *dev,
428 struct ethtool_stats *stats, u64 *data)
429{
430 struct skge_port *skge = netdev_priv(dev);
431
432 if (skge->hw->chip_id == CHIP_ID_GENESIS)
433 genesis_get_stats(skge, data);
434 else
435 yukon_get_stats(skge, data);
436}
437
438/* Use hardware MIB variables for critical path statistics and
439 * transmit feedback not reported at interrupt.
440 * Other errors are accounted for in interrupt handler.
441 */
442static struct net_device_stats *skge_get_stats(struct net_device *dev)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 u64 data[ARRAY_SIZE(skge_stats)];
446
447 if (skge->hw->chip_id == CHIP_ID_GENESIS)
448 genesis_get_stats(skge, data);
449 else
450 yukon_get_stats(skge, data);
451
da00772f
SH		 452 dev->stats.tx_bytes = data[0];
453 dev->stats.rx_bytes = data[1];
454 dev->stats.tx_packets = data[2] + data[4] + data[6];
455 dev->stats.rx_packets = data[3] + data[5] + data[7];
456 dev->stats.multicast = data[3] + data[5];
457 dev->stats.collisions = data[10];
458 dev->stats.tx_aborted_errors = data[12];
baef58b1 459
da00772f 460 return &dev->stats;
baef58b1
SH		 461}
462
463static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
464{
465 int i;
466
95566065 467 switch (stringset) {
baef58b1
SH		 468 case ETH_SS_STATS:
469 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
470 memcpy(data + i * ETH_GSTRING_LEN,
471 skge_stats[i].name, ETH_GSTRING_LEN);
472 break;
473 }
474}
475
476static void skge_get_ring_param(struct net_device *dev,
477 struct ethtool_ringparam *p)
478{
479 struct skge_port *skge = netdev_priv(dev);
480
481 p->rx_max_pending = MAX_RX_RING_SIZE;
482 p->tx_max_pending = MAX_TX_RING_SIZE;
483 p->rx_mini_max_pending = 0;
484 p->rx_jumbo_max_pending = 0;
485
486 p->rx_pending = skge->rx_ring.count;
487 p->tx_pending = skge->tx_ring.count;
488 p->rx_mini_pending = 0;
489 p->rx_jumbo_pending = 0;
490}
491
492static int skge_set_ring_param(struct net_device *dev,
493 struct ethtool_ringparam *p)
494{
495 struct skge_port *skge = netdev_priv(dev);
e824b3eb 496 int err = 0;
baef58b1
SH		 497
498 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 499 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 500 return -EINVAL;
501
502 skge->rx_ring.count = p->rx_pending;
503 skge->tx_ring.count = p->tx_pending;
504
505 if (netif_running(dev)) {
506 skge_down(dev);
3b8bb472
SH		 507 err = skge_up(dev);
508 if (err)
509 dev_close(dev);
baef58b1
SH		 510 }
511
e824b3eb 512 return err;
baef58b1
SH		 513}
514
515static u32 skge_get_msglevel(struct net_device *netdev)
516{
517 struct skge_port *skge = netdev_priv(netdev);
518 return skge->msg_enable;
519}
520
521static void skge_set_msglevel(struct net_device *netdev, u32 value)
522{
523 struct skge_port *skge = netdev_priv(netdev);
524 skge->msg_enable = value;
525}
526
527static int skge_nway_reset(struct net_device *dev)
528{
529 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 530
531 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
532 return -EINVAL;
533
ee294dcd 534 skge_phy_reset(skge);
baef58b1
SH		 535 return 0;
536}
537
538static int skge_set_sg(struct net_device *dev, u32 data)
539{
540 struct skge_port *skge = netdev_priv(dev);
541 struct skge_hw *hw = skge->hw;
542
543 if (hw->chip_id == CHIP_ID_GENESIS && data)
544 return -EOPNOTSUPP;
545 return ethtool_op_set_sg(dev, data);
546}
547
548static int skge_set_tx_csum(struct net_device *dev, u32 data)
549{
550 struct skge_port *skge = netdev_priv(dev);
551 struct skge_hw *hw = skge->hw;
552
553 if (hw->chip_id == CHIP_ID_GENESIS && data)
554 return -EOPNOTSUPP;
555
556 return ethtool_op_set_tx_csum(dev, data);
557}
558
559static u32 skge_get_rx_csum(struct net_device *dev)
560{
561 struct skge_port *skge = netdev_priv(dev);
562
563 return skge->rx_csum;
564}
565
566/* Only Yukon supports checksum offload. */
567static int skge_set_rx_csum(struct net_device *dev, u32 data)
568{
569 struct skge_port *skge = netdev_priv(dev);
570
571 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
572 return -EOPNOTSUPP;
573
574 skge->rx_csum = data;
575 return 0;
576}
577
baef58b1
SH		 578static void skge_get_pauseparam(struct net_device *dev,
579 struct ethtool_pauseparam *ecmd)
580{
581 struct skge_port *skge = netdev_priv(dev);
582
8e95a202
JP		 583 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
584 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
585 ecmd->tx_pause = (ecmd->rx_pause ||
586 (skge->flow_control == FLOW_MODE_LOC_SEND));
baef58b1 587
5d5c8e03 588 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 589}
590
591static int skge_set_pauseparam(struct net_device *dev,
592 struct ethtool_pauseparam *ecmd)
593{
594 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 595 struct ethtool_pauseparam old;
9ac1353f 596 int err = 0;
baef58b1 597
5d5c8e03
SH		 598 skge_get_pauseparam(dev, &old);
599
600 if (ecmd->autoneg != old.autoneg)
601 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
602 else {
603 if (ecmd->rx_pause && ecmd->tx_pause)
604 skge->flow_control = FLOW_MODE_SYMMETRIC;
605 else if (ecmd->rx_pause && !ecmd->tx_pause)
606 skge->flow_control = FLOW_MODE_SYM_OR_REM;
607 else if (!ecmd->rx_pause && ecmd->tx_pause)
608 skge->flow_control = FLOW_MODE_LOC_SEND;
609 else
610 skge->flow_control = FLOW_MODE_NONE;
611 }
baef58b1 612
9ac1353f
XZ		 613 if (netif_running(dev)) {
614 skge_down(dev);
615 err = skge_up(dev);
616 if (err) {
617 dev_close(dev);
618 return err;
619 }
620 }
5d5c8e03 621
baef58b1
SH		 622 return 0;
623}
624
625/* Chip internal frequency for clock calculations */
626static inline u32 hwkhz(const struct skge_hw *hw)
627{
187ff3b8 628 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 629}
630
8f3f8193 631/* Chip HZ to microseconds */
baef58b1
SH		 632static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
633{
634 return (ticks * 1000) / hwkhz(hw);
635}
636
8f3f8193 637/* Microseconds to chip HZ */
baef58b1
SH		 638static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
639{
640 return hwkhz(hw) * usec / 1000;
641}
642
643static int skge_get_coalesce(struct net_device *dev,
644 struct ethtool_coalesce *ecmd)
645{
646 struct skge_port *skge = netdev_priv(dev);
647 struct skge_hw *hw = skge->hw;
648 int port = skge->port;
649
650 ecmd->rx_coalesce_usecs = 0;
651 ecmd->tx_coalesce_usecs = 0;
652
653 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
654 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
655 u32 msk = skge_read32(hw, B2_IRQM_MSK);
656
657 if (msk & rxirqmask[port])
658 ecmd->rx_coalesce_usecs = delay;
659 if (msk & txirqmask[port])
660 ecmd->tx_coalesce_usecs = delay;
661 }
662
663 return 0;
664}
665
666/* Note: interrupt timer is per board, but can turn on/off per port */
667static int skge_set_coalesce(struct net_device *dev,
668 struct ethtool_coalesce *ecmd)
669{
670 struct skge_port *skge = netdev_priv(dev);
671 struct skge_hw *hw = skge->hw;
672 int port = skge->port;
673 u32 msk = skge_read32(hw, B2_IRQM_MSK);
674 u32 delay = 25;
675
676 if (ecmd->rx_coalesce_usecs == 0)
677 msk &= ~rxirqmask[port];
678 else if (ecmd->rx_coalesce_usecs < 25 ||
679 ecmd->rx_coalesce_usecs > 33333)
680 return -EINVAL;
681 else {
682 msk |= rxirqmask[port];
683 delay = ecmd->rx_coalesce_usecs;
684 }
685
686 if (ecmd->tx_coalesce_usecs == 0)
687 msk &= ~txirqmask[port];
688 else if (ecmd->tx_coalesce_usecs < 25 ||
689 ecmd->tx_coalesce_usecs > 33333)
690 return -EINVAL;
691 else {
692 msk |= txirqmask[port];
693 delay = min(delay, ecmd->rx_coalesce_usecs);
694 }
695
696 skge_write32(hw, B2_IRQM_MSK, msk);
697 if (msk == 0)
698 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
699 else {
700 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
701 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
702 }
703 return 0;
704}
705
6abebb53
SH		 706enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
707static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 708{
6abebb53
SH		 709 struct skge_hw *hw = skge->hw;
710 int port = skge->port;
711
9cbe330f 712 spin_lock_bh(&hw->phy_lock);
baef58b1 713 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 714 switch (mode) {
715 case LED_MODE_OFF:
64f6b64d
SH		 716 if (hw->phy_type == SK_PHY_BCOM)
717 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
718 else {
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
720 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
721 }
6abebb53
SH		 722 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
723 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
724 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
725 break;
baef58b1 726
6abebb53
SH		 727 case LED_MODE_ON:
728 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
729 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 730
6abebb53
SH		 731 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
732 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 733
6abebb53 734 break;
baef58b1 735
6abebb53
SH		 736 case LED_MODE_TST:
737 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
738 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
739 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 740
64f6b64d
SH		 741 if (hw->phy_type == SK_PHY_BCOM)
742 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
743 else {
744 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
745 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
746 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
747 }
748
6abebb53 749 }
baef58b1 750 } else {
6abebb53
SH		 751 switch (mode) {
752 case LED_MODE_OFF:
753 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
754 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
755 PHY_M_LED_MO_DUP(MO_LED_OFF) |
756 PHY_M_LED_MO_10(MO_LED_OFF) |
757 PHY_M_LED_MO_100(MO_LED_OFF) |
758 PHY_M_LED_MO_1000(MO_LED_OFF) |
759 PHY_M_LED_MO_RX(MO_LED_OFF));
760 break;
761 case LED_MODE_ON:
762 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
763 PHY_M_LED_PULS_DUR(PULS_170MS) |
764 PHY_M_LED_BLINK_RT(BLINK_84MS) |
765 PHY_M_LEDC_TX_CTRL |
766 PHY_M_LEDC_DP_CTRL);
46a60f2d 767
6abebb53
SH		 768 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
769 PHY_M_LED_MO_RX(MO_LED_OFF) |
770 (skge->speed == SPEED_100 ?
771 PHY_M_LED_MO_100(MO_LED_ON) : 0));
772 break;
773 case LED_MODE_TST:
774 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
775 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
776 PHY_M_LED_MO_DUP(MO_LED_ON) |
777 PHY_M_LED_MO_10(MO_LED_ON) |
778 PHY_M_LED_MO_100(MO_LED_ON) |
779 PHY_M_LED_MO_1000(MO_LED_ON) |
780 PHY_M_LED_MO_RX(MO_LED_ON));
781 }
baef58b1 782 }
9cbe330f 783 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 784}
785
786/* blink LED's for finding board */
787static int skge_phys_id(struct net_device *dev, u32 data)
788{
789 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 790 unsigned long ms;
791 enum led_mode mode = LED_MODE_TST;
baef58b1 792
95566065 793 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 794 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
795 else
796 ms = data * 1000;
baef58b1 797
6abebb53
SH		 798 while (ms > 0) {
799 skge_led(skge, mode);
800 mode ^= LED_MODE_TST;
baef58b1 801
6abebb53
SH		 802 if (msleep_interruptible(BLINK_MS))
803 break;
804 ms -= BLINK_MS;
805 }
baef58b1 806
6abebb53
SH		 807 /* back to regular LED state */
808 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 809
810 return 0;
811}
812
afa151b9
SH		 813static int skge_get_eeprom_len(struct net_device *dev)
814{
815 struct skge_port *skge = netdev_priv(dev);
816 u32 reg2;
817
818 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, &reg2);
67777f9b 819 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
afa151b9
SH		 820}
821
822static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
823{
824 u32 val;
825
826 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
827
828 do {
829 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
830 } while (!(offset & PCI_VPD_ADDR_F));
831
832 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
833 return val;
834}
835
836static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
837{
838 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
839 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
840 offset | PCI_VPD_ADDR_F);
841
842 do {
843 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
844 } while (offset & PCI_VPD_ADDR_F);
845}
846
847static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
848 u8 *data)
849{
850 struct skge_port *skge = netdev_priv(dev);
851 struct pci_dev *pdev = skge->hw->pdev;
852 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
853 int length = eeprom->len;
854 u16 offset = eeprom->offset;
855
856 if (!cap)
857 return -EINVAL;
858
859 eeprom->magic = SKGE_EEPROM_MAGIC;
860
861 while (length > 0) {
862 u32 val = skge_vpd_read(pdev, cap, offset);
863 int n = min_t(int, length, sizeof(val));
864
865 memcpy(data, &val, n);
866 length -= n;
867 data += n;
868 offset += n;
869 }
870 return 0;
871}
872
873static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
874 u8 *data)
875{
876 struct skge_port *skge = netdev_priv(dev);
877 struct pci_dev *pdev = skge->hw->pdev;
878 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
879 int length = eeprom->len;
880 u16 offset = eeprom->offset;
881
882 if (!cap)
883 return -EINVAL;
884
885 if (eeprom->magic != SKGE_EEPROM_MAGIC)
886 return -EINVAL;
887
888 while (length > 0) {
889 u32 val;
890 int n = min_t(int, length, sizeof(val));
891
892 if (n < sizeof(val))
893 val = skge_vpd_read(pdev, cap, offset);
894 memcpy(&val, data, n);
895
896 skge_vpd_write(pdev, cap, offset, val);
897
898 length -= n;
899 data += n;
900 offset += n;
901 }
902 return 0;
903}
904
7282d491 905static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 906 .get_settings = skge_get_settings,
907 .set_settings = skge_set_settings,
908 .get_drvinfo = skge_get_drvinfo,
909 .get_regs_len = skge_get_regs_len,
910 .get_regs = skge_get_regs,
911 .get_wol = skge_get_wol,
912 .set_wol = skge_set_wol,
913 .get_msglevel = skge_get_msglevel,
914 .set_msglevel = skge_set_msglevel,
915 .nway_reset = skge_nway_reset,
916 .get_link = ethtool_op_get_link,
afa151b9
SH		 917 .get_eeprom_len = skge_get_eeprom_len,
918 .get_eeprom = skge_get_eeprom,
919 .set_eeprom = skge_set_eeprom,
baef58b1
SH		 920 .get_ringparam = skge_get_ring_param,
921 .set_ringparam = skge_set_ring_param,
922 .get_pauseparam = skge_get_pauseparam,
923 .set_pauseparam = skge_set_pauseparam,
924 .get_coalesce = skge_get_coalesce,
925 .set_coalesce = skge_set_coalesce,
baef58b1 926 .set_sg = skge_set_sg,
baef58b1
SH		 927 .set_tx_csum = skge_set_tx_csum,
928 .get_rx_csum = skge_get_rx_csum,
929 .set_rx_csum = skge_set_rx_csum,
930 .get_strings = skge_get_strings,
931 .phys_id = skge_phys_id,
b9f2c044 932 .get_sset_count = skge_get_sset_count,
baef58b1
SH		 933 .get_ethtool_stats = skge_get_ethtool_stats,
934};
935
936/*
937 * Allocate ring elements and chain them together
938 * One-to-one association of board descriptors with ring elements
939 */
c3da1447 940static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 941{
942 struct skge_tx_desc *d;
943 struct skge_element *e;
944 int i;
945
cd861280 946 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 947 if (!ring->start)
948 return -ENOMEM;
949
950 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
951 e->desc = d;
952 if (i == ring->count - 1) {
953 e->next = ring->start;
954 d->next_offset = base;
955 } else {
956 e->next = e + 1;
957 d->next_offset = base + (i+1) * sizeof(*d);
958 }
959 }
960 ring->to_use = ring->to_clean = ring->start;
961
962 return 0;
963}
964
19a33d4e
SH		 965/* Allocate and setup a new buffer for receiving */
966static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
967 struct sk_buff *skb, unsigned int bufsize)
968{
969 struct skge_rx_desc *rd = e->desc;
970 u64 map;
baef58b1
SH		 971
972 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
973 PCI_DMA_FROMDEVICE);
974
975 rd->dma_lo = map;
976 rd->dma_hi = map >> 32;
977 e->skb = skb;
978 rd->csum1_start = ETH_HLEN;
979 rd->csum2_start = ETH_HLEN;
980 rd->csum1 = 0;
981 rd->csum2 = 0;
982
983 wmb();
984
985 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
986 pci_unmap_addr_set(e, mapaddr, map);
987 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 988}
989
19a33d4e
SH		 990/* Resume receiving using existing skb,
991 * Note: DMA address is not changed by chip.
992 * MTU not changed while receiver active.
993 */
5a011447 994static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 995{
996 struct skge_rx_desc *rd = e->desc;
997
998 rd->csum2 = 0;
999 rd->csum2_start = ETH_HLEN;
1000
1001 wmb();
1002
1003 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
1004}
1005
1006
1007/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 1008static void skge_rx_clean(struct skge_port *skge)
1009{
1010 struct skge_hw *hw = skge->hw;
1011 struct skge_ring *ring = &skge->rx_ring;
1012 struct skge_element *e;
1013
19a33d4e
SH		 1014 e = ring->start;
1015 do {
baef58b1
SH		 1016 struct skge_rx_desc *rd = e->desc;
1017 rd->control = 0;
19a33d4e
SH		 1018 if (e->skb) {
1019 pci_unmap_single(hw->pdev,
1020 pci_unmap_addr(e, mapaddr),
1021 pci_unmap_len(e, maplen),
1022 PCI_DMA_FROMDEVICE);
1023 dev_kfree_skb(e->skb);
1024 e->skb = NULL;
1025 }
1026 } while ((e = e->next) != ring->start);
baef58b1
SH		 1027}
1028
19a33d4e 1029
baef58b1 1030/* Allocate buffers for receive ring
19a33d4e 1031 * For receive: to_clean is next received frame.
baef58b1 1032 */
c54f9765 1033static int skge_rx_fill(struct net_device *dev)
baef58b1 1034{
c54f9765 1035 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 1036 struct skge_ring *ring = &skge->rx_ring;
1037 struct skge_element *e;
baef58b1 1038
19a33d4e
SH		 1039 e = ring->start;
1040 do {
383181ac 1041 struct sk_buff *skb;
baef58b1 1042
c54f9765
SH		 1043 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1044 GFP_KERNEL);
19a33d4e
SH		 1045 if (!skb)
1046 return -ENOMEM;
1047
383181ac
SH		 1048 skb_reserve(skb, NET_IP_ALIGN);
1049 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
67777f9b 1050 } while ((e = e->next) != ring->start);
baef58b1 1051
19a33d4e
SH		 1052 ring->to_clean = ring->start;
1053 return 0;
baef58b1
SH		 1054}
1055
5d5c8e03
SH		 1056static const char *skge_pause(enum pause_status status)
1057{
67777f9b 1058 switch (status) {
5d5c8e03
SH		 1059 case FLOW_STAT_NONE:
1060 return "none";
1061 case FLOW_STAT_REM_SEND:
1062 return "rx only";
1063 case FLOW_STAT_LOC_SEND:
1064 return "tx_only";
1065 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1066 return "both";
1067 default:
1068 return "indeterminated";
1069 }
1070}
1071
1072
baef58b1
SH		 1073static void skge_link_up(struct skge_port *skge)
1074{
46a60f2d 1075 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 1076 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1077
baef58b1 1078 netif_carrier_on(skge->netdev);
29b4e886 1079 netif_wake_queue(skge->netdev);
baef58b1 1080
d707204c
JP		 1081 netif_info(skge, link, skge->netdev,
1082 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1083 skge->speed,
1084 skge->duplex == DUPLEX_FULL ? "full" : "half",
1085 skge_pause(skge->flow_status));
baef58b1
SH		 1086}
1087
1088static void skge_link_down(struct skge_port *skge)
1089{
54cfb5aa 1090 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 1091 netif_carrier_off(skge->netdev);
1092 netif_stop_queue(skge->netdev);
1093
d707204c 1094 netif_info(skge, link, skge->netdev, "Link is down\n");
baef58b1
SH		 1095}
1096
a1bc9b87
SH		 1097
1098static void xm_link_down(struct skge_hw *hw, int port)
1099{
1100 struct net_device *dev = hw->dev[port];
1101 struct skge_port *skge = netdev_priv(dev);
a1bc9b87 1102
501fb72d 1103 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
a1bc9b87 1104
a1bc9b87
SH		 1105 if (netif_carrier_ok(dev))
1106 skge_link_down(skge);
1107}
1108
2cd8e5d3 1109static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 1110{
1111 int i;
baef58b1 1112
6b0c1480 1113 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 1114 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1115
64f6b64d
SH		 1116 if (hw->phy_type == SK_PHY_XMAC)
1117 goto ready;
1118
89bf5f23 1119 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1120 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1121 goto ready;
0781191c 1122 udelay(1);
baef58b1
SH		 1123 }
1124
2cd8e5d3 1125 return -ETIMEDOUT;
89bf5f23 1126 ready:
2cd8e5d3 1127 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1128
2cd8e5d3
SH		 1129 return 0;
1130}
1131
1132static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1133{
1134 u16 v = 0;
1135 if (__xm_phy_read(hw, port, reg, &v))
f15063cd 1136 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
baef58b1
SH		 1137 return v;
1138}
1139
2cd8e5d3 1140static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1141{
1142 int i;
1143
6b0c1480 1144 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1145 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1146 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1147 goto ready;
89bf5f23 1148 udelay(1);
baef58b1 1149 }
2cd8e5d3 1150 return -EIO;
baef58b1
SH		 1151
1152 ready:
6b0c1480 1153 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1154 for (i = 0; i < PHY_RETRIES; i++) {
1155 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1156 return 0;
1157 udelay(1);
1158 }
1159 return -ETIMEDOUT;
baef58b1
SH		 1160}
1161
1162static void genesis_init(struct skge_hw *hw)
1163{
1164 /* set blink source counter */
1165 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1166 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1167
1168 /* configure mac arbiter */
1169 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1170
1171 /* configure mac arbiter timeout values */
1172 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1173 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1174 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1175 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1176
1177 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1178 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1179 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1180 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1181
1182 /* configure packet arbiter timeout */
1183 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1184 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1185 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1186 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1187 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1188}
1189
1190static void genesis_reset(struct skge_hw *hw, int port)
1191{
45bada65 1192 const u8 zero[8] = { 0 };
21d7f677 1193 u32 reg;
baef58b1 1194
46a60f2d
SH		 1195 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1196
baef58b1 1197 /* reset the statistics module */
6b0c1480 1198 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
501fb72d 1199 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
6b0c1480
SH		 1200 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1201 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1202 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1203
89bf5f23 1204 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1205 if (hw->phy_type == SK_PHY_BCOM)
1206 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1207
45bada65 1208 xm_outhash(hw, port, XM_HSM, zero);
21d7f677
SH		 1209
1210 /* Flush TX and RX fifo */
1211 reg = xm_read32(hw, port, XM_MODE);
1212 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1213 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
baef58b1
SH		 1214}
1215
1216
45bada65
SH		 1217/* Convert mode to MII values */
1218static const u16 phy_pause_map[] = {
1219 [FLOW_MODE_NONE] = 0,
1220 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1221 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1222 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1223};
1224
4b67be99
SH		 1225/* special defines for FIBER (88E1011S only) */
1226static const u16 fiber_pause_map[] = {
1227 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1228 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1229 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1230 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1231};
1232
45bada65
SH		 1233
1234/* Check status of Broadcom phy link */
1235static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1236{
45bada65
SH		 1237 struct net_device *dev = hw->dev[port];
1238 struct skge_port *skge = netdev_priv(dev);
1239 u16 status;
1240
1241 /* read twice because of latch */
501fb72d 1242 xm_phy_read(hw, port, PHY_BCOM_STAT);
45bada65
SH		 1243 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1244
45bada65 1245 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1246 xm_link_down(hw, port);
64f6b64d
SH		 1247 return;
1248 }
45bada65 1249
64f6b64d
SH		 1250 if (skge->autoneg == AUTONEG_ENABLE) {
1251 u16 lpa, aux;
45bada65 1252
64f6b64d
SH		 1253 if (!(status & PHY_ST_AN_OVER))
1254 return;
45bada65 1255
64f6b64d
SH		 1256 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1257 if (lpa & PHY_B_AN_RF) {
f15063cd 1258 netdev_notice(dev, "remote fault\n");
64f6b64d
SH		 1259 return;
1260 }
45bada65 1261
64f6b64d
SH		 1262 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1263
1264 /* Check Duplex mismatch */
1265 switch (aux & PHY_B_AS_AN_RES_MSK) {
1266 case PHY_B_RES_1000FD:
1267 skge->duplex = DUPLEX_FULL;
1268 break;
1269 case PHY_B_RES_1000HD:
1270 skge->duplex = DUPLEX_HALF;
1271 break;
1272 default:
f15063cd 1273 netdev_notice(dev, "duplex mismatch\n");
64f6b64d 1274 return;
45bada65
SH		 1275 }
1276
64f6b64d
SH		 1277 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1278 switch (aux & PHY_B_AS_PAUSE_MSK) {
1279 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1280 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1281 break;
1282 case PHY_B_AS_PRR:
5d5c8e03 1283 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1284 break;
1285 case PHY_B_AS_PRT:
5d5c8e03 1286 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1287 break;
1288 default:
5d5c8e03 1289 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1290 }
1291 skge->speed = SPEED_1000;
45bada65 1292 }
64f6b64d
SH		 1293
1294 if (!netif_carrier_ok(dev))
1295 genesis_link_up(skge);
45bada65
SH		 1296}
1297
1298/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1299 * Phy on for 100 or 10Mbit operation
1300 */
64f6b64d 1301static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1302{
1303 struct skge_hw *hw = skge->hw;
1304 int port = skge->port;
baef58b1 1305 int i;
45bada65 1306 u16 id1, r, ext, ctl;
baef58b1
SH		 1307
1308 /* magic workaround patterns for Broadcom */
1309 static const struct {
1310 u16 reg;
1311 u16 val;
1312 } A1hack[] = {
1313 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1314 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1315 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1316 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1317 }, C0hack[] = {
1318 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1319 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1320 };
1321
45bada65
SH		 1322 /* read Id from external PHY (all have the same address) */
1323 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1324
1325 /* Optimize MDIO transfer by suppressing preamble. */
1326 r = xm_read16(hw, port, XM_MMU_CMD);
1327 r |= XM_MMU_NO_PRE;
67777f9b 1328 xm_write16(hw, port, XM_MMU_CMD, r);
45bada65 1329
2c668514 1330 switch (id1) {
45bada65
SH		 1331 case PHY_BCOM_ID1_C0:
1332 /*
1333 * Workaround BCOM Errata for the C0 type.
1334 * Write magic patterns to reserved registers.
1335 */
1336 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1337 xm_phy_write(hw, port,
1338 C0hack[i].reg, C0hack[i].val);
1339
1340 break;
1341 case PHY_BCOM_ID1_A1:
1342 /*
1343 * Workaround BCOM Errata for the A1 type.
1344 * Write magic patterns to reserved registers.
1345 */
1346 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1347 xm_phy_write(hw, port,
1348 A1hack[i].reg, A1hack[i].val);
1349 break;
1350 }
1351
1352 /*
1353 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1354 * Disable Power Management after reset.
1355 */
1356 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1357 r |= PHY_B_AC_DIS_PM;
1358 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1359
1360 /* Dummy read */
1361 xm_read16(hw, port, XM_ISRC);
1362
1363 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1364 ctl = PHY_CT_SP1000; /* always 1000mbit */
1365
1366 if (skge->autoneg == AUTONEG_ENABLE) {
1367 /*
1368 * Workaround BCOM Errata #1 for the C5 type.
1369 * 1000Base-T Link Acquisition Failure in Slave Mode
1370 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1371 */
1372 u16 adv = PHY_B_1000C_RD;
1373 if (skge->advertising & ADVERTISED_1000baseT_Half)
1374 adv |= PHY_B_1000C_AHD;
1375 if (skge->advertising & ADVERTISED_1000baseT_Full)
1376 adv |= PHY_B_1000C_AFD;
1377 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1378
1379 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1380 } else {
1381 if (skge->duplex == DUPLEX_FULL)
1382 ctl |= PHY_CT_DUP_MD;
1383 /* Force to slave */
1384 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1385 }
1386
1387 /* Set autonegotiation pause parameters */
1388 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1389 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1390
1391 /* Handle Jumbo frames */
64f6b64d 1392 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1393 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1394 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1395
1396 ext |= PHY_B_PEC_HIGH_LA;
1397
1398 }
1399
1400 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1401 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1402
8f3f8193 1403 /* Use link status change interrupt */
45bada65 1404 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1405}
45bada65 1406
64f6b64d
SH		 1407static void xm_phy_init(struct skge_port *skge)
1408{
1409 struct skge_hw *hw = skge->hw;
1410 int port = skge->port;
1411 u16 ctrl = 0;
1412
1413 if (skge->autoneg == AUTONEG_ENABLE) {
1414 if (skge->advertising & ADVERTISED_1000baseT_Half)
1415 ctrl |= PHY_X_AN_HD;
1416 if (skge->advertising & ADVERTISED_1000baseT_Full)
1417 ctrl |= PHY_X_AN_FD;
1418
4b67be99 1419 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1420
1421 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1422
1423 /* Restart Auto-negotiation */
1424 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1425 } else {
1426 /* Set DuplexMode in Config register */
1427 if (skge->duplex == DUPLEX_FULL)
1428 ctrl |= PHY_CT_DUP_MD;
1429 /*
1430 * Do NOT enable Auto-negotiation here. This would hold
1431 * the link down because no IDLEs are transmitted
1432 */
1433 }
1434
1435 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1436
1437 /* Poll PHY for status changes */
9cbe330f 1438 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1439}
1440
501fb72d 1441static int xm_check_link(struct net_device *dev)
64f6b64d
SH		 1442{
1443 struct skge_port *skge = netdev_priv(dev);
1444 struct skge_hw *hw = skge->hw;
1445 int port = skge->port;
1446 u16 status;
1447
1448 /* read twice because of latch */
501fb72d 1449 xm_phy_read(hw, port, PHY_XMAC_STAT);
64f6b64d
SH		 1450 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1451
1452 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1453 xm_link_down(hw, port);
501fb72d 1454 return 0;
64f6b64d
SH		 1455 }
1456
1457 if (skge->autoneg == AUTONEG_ENABLE) {
1458 u16 lpa, res;
1459
1460 if (!(status & PHY_ST_AN_OVER))
501fb72d 1461 return 0;
64f6b64d
SH		 1462
1463 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1464 if (lpa & PHY_B_AN_RF) {
f15063cd 1465 netdev_notice(dev, "remote fault\n");
501fb72d 1466 return 0;
64f6b64d
SH		 1467 }
1468
1469 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1470
1471 /* Check Duplex mismatch */
1472 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1473 case PHY_X_RS_FD:
1474 skge->duplex = DUPLEX_FULL;
1475 break;
1476 case PHY_X_RS_HD:
1477 skge->duplex = DUPLEX_HALF;
1478 break;
1479 default:
f15063cd 1480 netdev_notice(dev, "duplex mismatch\n");
501fb72d 1481 return 0;
64f6b64d
SH		 1482 }
1483
1484 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1485 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1486 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1487 (lpa & PHY_X_P_SYM_MD))
1488 skge->flow_status = FLOW_STAT_SYMMETRIC;
1489 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1490 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1491 /* Enable PAUSE receive, disable PAUSE transmit */
1492 skge->flow_status = FLOW_STAT_REM_SEND;
1493 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1494 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1495 /* Disable PAUSE receive, enable PAUSE transmit */
1496 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1497 else
5d5c8e03 1498 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1499
1500 skge->speed = SPEED_1000;
1501 }
1502
1503 if (!netif_carrier_ok(dev))
1504 genesis_link_up(skge);
501fb72d 1505 return 1;
64f6b64d
SH		 1506}
1507
1508/* Poll to check for link coming up.
501fb72d 1509 *
64f6b64d 1510 * Since internal PHY is wired to a level triggered pin, can't
501fb72d
SH		 1511 * get an interrupt when carrier is detected, need to poll for
1512 * link coming up.
64f6b64d 1513 */
9cbe330f 1514static void xm_link_timer(unsigned long arg)
64f6b64d 1515{
9cbe330f 1516 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1517 struct net_device *dev = skge->netdev;
67777f9b 1518 struct skge_hw *hw = skge->hw;
64f6b64d 1519 int port = skge->port;
501fb72d
SH		 1520 int i;
1521 unsigned long flags;
64f6b64d
SH		 1522
1523 if (!netif_running(dev))
1524 return;
1525
501fb72d
SH		 1526 spin_lock_irqsave(&hw->phy_lock, flags);
1527
1528 /*
1529 * Verify that the link by checking GPIO register three times.
1530 * This pin has the signal from the link_sync pin connected to it.
1531 */
1532 for (i = 0; i < 3; i++) {
1533 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1534 goto link_down;
1535 }
1536
67777f9b 1537 /* Re-enable interrupt to detect link down */
501fb72d
SH		 1538 if (xm_check_link(dev)) {
1539 u16 msk = xm_read16(hw, port, XM_IMSK);
1540 msk &= ~XM_IS_INP_ASS;
1541 xm_write16(hw, port, XM_IMSK, msk);
64f6b64d 1542 xm_read16(hw, port, XM_ISRC);
64f6b64d 1543 } else {
501fb72d
SH		 1544link_down:
1545 mod_timer(&skge->link_timer,
1546 round_jiffies(jiffies + LINK_HZ));
64f6b64d 1547 }
501fb72d 1548 spin_unlock_irqrestore(&hw->phy_lock, flags);
45bada65
SH		 1549}
1550
1551static void genesis_mac_init(struct skge_hw *hw, int port)
1552{
1553 struct net_device *dev = hw->dev[port];
1554 struct skge_port *skge = netdev_priv(dev);
1555 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1556 int i;
1557 u32 r;
1558 const u8 zero[6] = { 0 };
1559
0781191c
SH		 1560 for (i = 0; i < 10; i++) {
1561 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1562 MFF_SET_MAC_RST);
1563 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1564 goto reset_ok;
1565 udelay(1);
1566 }
baef58b1 1567
f15063cd 1568 netdev_warn(dev, "genesis reset failed\n");
0781191c
SH		 1569
1570 reset_ok:
baef58b1 1571 /* Unreset the XMAC. */
6b0c1480 1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1573
1574 /*
1575 * Perform additional initialization for external PHYs,
1576 * namely for the 1000baseTX cards that use the XMAC's
1577 * GMII mode.
1578 */
64f6b64d
SH		 1579 if (hw->phy_type != SK_PHY_XMAC) {
1580 /* Take external Phy out of reset */
1581 r = skge_read32(hw, B2_GP_IO);
1582 if (port == 0)
1583 r |= GP_DIR_0|GP_IO_0;
1584 else
1585 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1586
64f6b64d 1587 skge_write32(hw, B2_GP_IO, r);
0781191c 1588
64f6b64d
SH		 1589 /* Enable GMII interface */
1590 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1591 }
89bf5f23 1592
89bf5f23 1593
67777f9b 1594 switch (hw->phy_type) {
64f6b64d
SH		 1595 case SK_PHY_XMAC:
1596 xm_phy_init(skge);
1597 break;
1598 case SK_PHY_BCOM:
1599 bcom_phy_init(skge);
1600 bcom_check_link(hw, port);
1601 }
89bf5f23 1602
45bada65
SH		 1603 /* Set Station Address */
1604 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1605
45bada65
SH		 1606 /* We don't use match addresses so clear */
1607 for (i = 1; i < 16; i++)
1608 xm_outaddr(hw, port, XM_EXM(i), zero);
1609
0781191c
SH		 1610 /* Clear MIB counters */
1611 xm_write16(hw, port, XM_STAT_CMD,
1612 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1613 /* Clear two times according to Errata #3 */
1614 xm_write16(hw, port, XM_STAT_CMD,
1615 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1616
45bada65
SH		 1617 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1618 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1619
1620 /* We don't need the FCS appended to the packet. */
1621 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1622 if (jumbo)
1623 r |= XM_RX_BIG_PK_OK;
89bf5f23 1624
45bada65 1625 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1626 /*
45bada65
SH		 1627 * If in manual half duplex mode the other side might be in
1628 * full duplex mode, so ignore if a carrier extension is not seen
1629 * on frames received
89bf5f23 1630 */
45bada65 1631 r |= XM_RX_DIS_CEXT;
baef58b1 1632 }
45bada65 1633 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1634
baef58b1 1635 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1636 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1637
485982a9
SH		 1638 /* Increase threshold for jumbo frames on dual port */
1639 if (hw->ports > 1 && jumbo)
1640 xm_write16(hw, port, XM_TX_THR, 1020);
1641 else
1642 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1643
1644 /*
1645 * Enable the reception of all error frames. This is is
1646 * a necessary evil due to the design of the XMAC. The
1647 * XMAC's receive FIFO is only 8K in size, however jumbo
1648 * frames can be up to 9000 bytes in length. When bad
1649 * frame filtering is enabled, the XMAC's RX FIFO operates
1650 * in 'store and forward' mode. For this to work, the
1651 * entire frame has to fit into the FIFO, but that means
1652 * that jumbo frames larger than 8192 bytes will be
1653 * truncated. Disabling all bad frame filtering causes
1654 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1655 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1656 * RX FIFO as soon as the FIFO threshold is reached.
1657 */
45bada65 1658 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1659
baef58b1
SH		 1660
1661 /*
45bada65
SH		 1662 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1663 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1664 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1665 */
45bada65
SH		 1666 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1667
1668 /*
1669 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1670 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1671 * and 'Octets Tx OK Hi Cnt Ov'.
1672 */
1673 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1674
1675 /* Configure MAC arbiter */
1676 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1677
1678 /* configure timeout values */
1679 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1680 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1681 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1682 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1683
1684 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1685 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1686 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1687 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1688
1689 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1690 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1691 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1692 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1693
1694 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1695 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1696 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1697 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1698
45bada65 1699 if (jumbo) {
baef58b1 1700 /* Enable frame flushing if jumbo frames used */
67777f9b 1701 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1702 } else {
1703 /* enable timeout timers if normal frames */
1704 skge_write16(hw, B3_PA_CTRL,
45bada65 1705 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1706 }
baef58b1
SH		 1707}
1708
1709static void genesis_stop(struct skge_port *skge)
1710{
1711 struct skge_hw *hw = skge->hw;
1712 int port = skge->port;
799b21d2 1713 unsigned retries = 1000;
21d7f677
SH		 1714 u16 cmd;
1715
67777f9b 1716 /* Disable Tx and Rx */
21d7f677
SH		 1717 cmd = xm_read16(hw, port, XM_MMU_CMD);
1718 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1719 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1720
46a60f2d
SH		 1721 genesis_reset(hw, port);
1722
baef58b1
SH		 1723 /* Clear Tx packet arbiter timeout IRQ */
1724 skge_write16(hw, B3_PA_CTRL,
1725 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1726
baef58b1 1727 /* Reset the MAC */
799b21d2
SH		 1728 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1729 do {
1730 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1731 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1732 break;
1733 } while (--retries > 0);
baef58b1
SH		 1734
1735 /* For external PHYs there must be special handling */
64f6b64d 1736 if (hw->phy_type != SK_PHY_XMAC) {
799b21d2 1737 u32 reg = skge_read32(hw, B2_GP_IO);
64f6b64d
SH		 1738 if (port == 0) {
1739 reg |= GP_DIR_0;
1740 reg &= ~GP_IO_0;
1741 } else {
1742 reg |= GP_DIR_2;
1743 reg &= ~GP_IO_2;
1744 }
1745 skge_write32(hw, B2_GP_IO, reg);
1746 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1747 }
1748
6b0c1480
SH		 1749 xm_write16(hw, port, XM_MMU_CMD,
1750 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1751 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1752
6b0c1480 1753 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1754}
1755
1756
1757static void genesis_get_stats(struct skge_port *skge, u64 *data)
1758{
1759 struct skge_hw *hw = skge->hw;
1760 int port = skge->port;
1761 int i;
1762 unsigned long timeout = jiffies + HZ;
1763
6b0c1480 1764 xm_write16(hw, port,
baef58b1
SH		 1765 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1766
1767 /* wait for update to complete */
6b0c1480 1768 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1769 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1770 if (time_after(jiffies, timeout))
1771 break;
1772 udelay(10);
1773 }
1774
1775 /* special case for 64 bit octet counter */
6b0c1480
SH		 1776 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1777 | xm_read32(hw, port, XM_TXO_OK_LO);
1778 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1779 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1780
1781 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1782 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1783}
1784
1785static void genesis_mac_intr(struct skge_hw *hw, int port)
1786{
da00772f
SH		 1787 struct net_device *dev = hw->dev[port];
1788 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1789 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1790
d707204c
JP		 1791 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1792 "mac interrupt status 0x%x\n", status);
baef58b1 1793
501fb72d 1794 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
67777f9b 1795 xm_link_down(hw, port);
501fb72d
SH		 1796 mod_timer(&skge->link_timer, jiffies + 1);
1797 }
a1bc9b87 1798
baef58b1 1799 if (status & XM_IS_TXF_UR) {
6b0c1480 1800 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
da00772f 1801 ++dev->stats.tx_fifo_errors;
baef58b1 1802 }
baef58b1
SH		 1803}
1804
baef58b1
SH		 1805static void genesis_link_up(struct skge_port *skge)
1806{
1807 struct skge_hw *hw = skge->hw;
1808 int port = skge->port;
a1bc9b87 1809 u16 cmd, msk;
64f6b64d 1810 u32 mode;
baef58b1 1811
6b0c1480 1812 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1813
1814 /*
1815 * enabling pause frame reception is required for 1000BT
1816 * because the XMAC is not reset if the link is going down
1817 */
5d5c8e03
SH		 1818 if (skge->flow_status == FLOW_STAT_NONE ||
1819 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1820 /* Disable Pause Frame Reception */
baef58b1
SH		 1821 cmd |= XM_MMU_IGN_PF;
1822 else
1823 /* Enable Pause Frame Reception */
1824 cmd &= ~XM_MMU_IGN_PF;
1825
6b0c1480 1826 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1827
6b0c1480 1828 mode = xm_read32(hw, port, XM_MODE);
67777f9b 1829 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
5d5c8e03 1830 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1831 /*
1832 * Configure Pause Frame Generation
1833 * Use internal and external Pause Frame Generation.
1834 * Sending pause frames is edge triggered.
1835 * Send a Pause frame with the maximum pause time if
1836 * internal oder external FIFO full condition occurs.
1837 * Send a zero pause time frame to re-start transmission.
1838 */
1839 /* XM_PAUSE_DA = '010000C28001' (default) */
1840 /* XM_MAC_PTIME = 0xffff (maximum) */
1841 /* remember this value is defined in big endian (!) */
6b0c1480 1842 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1843
1844 mode |= XM_PAUSE_MODE;
6b0c1480 1845 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1846 } else {
1847 /*
1848 * disable pause frame generation is required for 1000BT
1849 * because the XMAC is not reset if the link is going down
1850 */
1851 /* Disable Pause Mode in Mode Register */
1852 mode &= ~XM_PAUSE_MODE;
1853
6b0c1480 1854 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1855 }
1856
6b0c1480 1857 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87 1858
d08b9bdf 1859 /* Turn on detection of Tx underrun */
501fb72d 1860 msk = xm_read16(hw, port, XM_IMSK);
d08b9bdf 1861 msk &= ~XM_IS_TXF_UR;
a1bc9b87 1862 xm_write16(hw, port, XM_IMSK, msk);
501fb72d 1863
6b0c1480 1864 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1865
1866 /* get MMU Command Reg. */
6b0c1480 1867 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1868 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1869 cmd |= XM_MMU_GMII_FD;
1870
89bf5f23
SH		 1871 /*
1872 * Workaround BCOM Errata (#10523) for all BCom Phys
1873 * Enable Power Management after link up
1874 */
64f6b64d
SH		 1875 if (hw->phy_type == SK_PHY_BCOM) {
1876 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1877 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1878 & ~PHY_B_AC_DIS_PM);
1879 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1880 }
baef58b1
SH		 1881
1882 /* enable Rx/Tx */
6b0c1480 1883 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1884 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1885 skge_link_up(skge);
1886}
1887
1888
45bada65 1889static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1890{
1891 struct skge_hw *hw = skge->hw;
1892 int port = skge->port;
45bada65
SH		 1893 u16 isrc;
1894
1895 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
d707204c
JP		 1896 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1897 "phy interrupt status 0x%x\n", isrc);
baef58b1 1898
45bada65 1899 if (isrc & PHY_B_IS_PSE)
f15063cd 1900 pr_err("%s: uncorrectable pair swap error\n",
45bada65 1901 hw->dev[port]->name);
baef58b1
SH		 1902
1903 /* Workaround BCom Errata:
1904 * enable and disable loopback mode if "NO HCD" occurs.
1905 */
45bada65 1906 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1907 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1908 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1909 ctrl | PHY_CT_LOOP);
6b0c1480 1910 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1911 ctrl & ~PHY_CT_LOOP);
1912 }
1913
45bada65
SH		 1914 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1915 bcom_check_link(hw, port);
baef58b1 1916
baef58b1
SH		 1917}
1918
2cd8e5d3
SH		 1919static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1920{
1921 int i;
1922
1923 gma_write16(hw, port, GM_SMI_DATA, val);
1924 gma_write16(hw, port, GM_SMI_CTRL,
1925 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1926 for (i = 0; i < PHY_RETRIES; i++) {
1927 udelay(1);
1928
1929 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1930 return 0;
1931 }
1932
f15063cd 1933 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1934 return -EIO;
1935}
1936
1937static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1938{
1939 int i;
1940
1941 gma_write16(hw, port, GM_SMI_CTRL,
1942 GM_SMI_CT_PHY_AD(hw->phy_addr)
1943 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1944
1945 for (i = 0; i < PHY_RETRIES; i++) {
1946 udelay(1);
1947 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1948 goto ready;
1949 }
1950
1951 return -ETIMEDOUT;
1952 ready:
1953 *val = gma_read16(hw, port, GM_SMI_DATA);
1954 return 0;
1955}
1956
1957static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1958{
1959 u16 v = 0;
1960 if (__gm_phy_read(hw, port, reg, &v))
f15063cd 1961 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
2cd8e5d3
SH		 1962 return v;
1963}
1964
8f3f8193 1965/* Marvell Phy Initialization */
baef58b1
SH		 1966static void yukon_init(struct skge_hw *hw, int port)
1967{
1968 struct skge_port *skge = netdev_priv(hw->dev[port]);
1969 u16 ctrl, ct1000, adv;
baef58b1 1970
baef58b1 1971 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1972 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1973
1974 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1975 PHY_M_EC_MAC_S_MSK);
1976 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1977
c506a509 1978 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1979
6b0c1480 1980 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1981 }
1982
6b0c1480 1983 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1984 if (skge->autoneg == AUTONEG_DISABLE)
1985 ctrl &= ~PHY_CT_ANE;
1986
1987 ctrl |= PHY_CT_RESET;
6b0c1480 1988 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1989
1990 ctrl = 0;
1991 ct1000 = 0;
b18f2091 1992 adv = PHY_AN_CSMA;
baef58b1
SH		 1993
1994 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1995 if (hw->copper) {
baef58b1
SH		 1996 if (skge->advertising & ADVERTISED_1000baseT_Full)
1997 ct1000 |= PHY_M_1000C_AFD;
1998 if (skge->advertising & ADVERTISED_1000baseT_Half)
1999 ct1000 |= PHY_M_1000C_AHD;
2000 if (skge->advertising & ADVERTISED_100baseT_Full)
2001 adv |= PHY_M_AN_100_FD;
2002 if (skge->advertising & ADVERTISED_100baseT_Half)
2003 adv |= PHY_M_AN_100_HD;
2004 if (skge->advertising & ADVERTISED_10baseT_Full)
2005 adv |= PHY_M_AN_10_FD;
2006 if (skge->advertising & ADVERTISED_10baseT_Half)
2007 adv |= PHY_M_AN_10_HD;
baef58b1 2008
4b67be99
SH		 2009 /* Set Flow-control capabilities */
2010 adv |= phy_pause_map[skge->flow_control];
2011 } else {
2012 if (skge->advertising & ADVERTISED_1000baseT_Full)
2013 adv |= PHY_M_AN_1000X_AFD;
2014 if (skge->advertising & ADVERTISED_1000baseT_Half)
2015 adv |= PHY_M_AN_1000X_AHD;
2016
2017 adv |= fiber_pause_map[skge->flow_control];
2018 }
45bada65 2019
baef58b1
SH		 2020 /* Restart Auto-negotiation */
2021 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2022 } else {
2023 /* forced speed/duplex settings */
2024 ct1000 = PHY_M_1000C_MSE;
2025
2026 if (skge->duplex == DUPLEX_FULL)
2027 ctrl |= PHY_CT_DUP_MD;
2028
2029 switch (skge->speed) {
2030 case SPEED_1000:
2031 ctrl |= PHY_CT_SP1000;
2032 break;
2033 case SPEED_100:
2034 ctrl |= PHY_CT_SP100;
2035 break;
2036 }
2037
2038 ctrl |= PHY_CT_RESET;
2039 }
2040
c506a509 2041 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 2042
6b0c1480
SH		 2043 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2044 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 2045
baef58b1
SH		 2046 /* Enable phy interrupt on autonegotiation complete (or link up) */
2047 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 2048 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 2049 else
4cde06ed 2050 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2051}
2052
2053static void yukon_reset(struct skge_hw *hw, int port)
2054{
6b0c1480
SH		 2055 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2056 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2057 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2058 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2059 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 2060
6b0c1480
SH		 2061 gma_write16(hw, port, GM_RX_CTRL,
2062 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 2063 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2064}
2065
c8868611
SH		 2066/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2067static int is_yukon_lite_a0(struct skge_hw *hw)
2068{
2069 u32 reg;
2070 int ret;
2071
2072 if (hw->chip_id != CHIP_ID_YUKON)
2073 return 0;
2074
2075 reg = skge_read32(hw, B2_FAR);
2076 skge_write8(hw, B2_FAR + 3, 0xff);
2077 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2078 skge_write32(hw, B2_FAR, reg);
2079 return ret;
2080}
2081
baef58b1
SH		 2082static void yukon_mac_init(struct skge_hw *hw, int port)
2083{
2084 struct skge_port *skge = netdev_priv(hw->dev[port]);
2085 int i;
2086 u32 reg;
2087 const u8 *addr = hw->dev[port]->dev_addr;
2088
2089 /* WA code for COMA mode -- set PHY reset */
2090 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2091 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2092 reg = skge_read32(hw, B2_GP_IO);
2093 reg |= GP_DIR_9 | GP_IO_9;
2094 skge_write32(hw, B2_GP_IO, reg);
2095 }
baef58b1
SH		 2096
2097 /* hard reset */
6b0c1480
SH		 2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2099 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2100
2101 /* WA code for COMA mode -- clear PHY reset */
2102 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 2103 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2104 reg = skge_read32(hw, B2_GP_IO);
2105 reg |= GP_DIR_9;
2106 reg &= ~GP_IO_9;
2107 skge_write32(hw, B2_GP_IO, reg);
2108 }
baef58b1
SH		 2109
2110 /* Set hardware config mode */
2111 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2112 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 2113 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 2114
2115 /* Clear GMC reset */
6b0c1480
SH		 2116 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2117 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2118 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 2119
baef58b1
SH		 2120 if (skge->autoneg == AUTONEG_DISABLE) {
2121 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2122 gma_write16(hw, port, GM_GP_CTRL,
2123 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2124
2125 switch (skge->speed) {
2126 case SPEED_1000:
564f9abb 2127 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2128 reg |= GM_GPCR_SPEED_1000;
564f9abb 2129 break;
baef58b1 2130 case SPEED_100:
564f9abb 2131 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2132 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2133 break;
2134 case SPEED_10:
2135 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2136 break;
baef58b1
SH		 2137 }
2138
2139 if (skge->duplex == DUPLEX_FULL)
2140 reg |= GM_GPCR_DUP_FULL;
2141 } else
2142 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2143
baef58b1
SH		 2144 switch (skge->flow_control) {
2145 case FLOW_MODE_NONE:
6b0c1480 2146 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2147 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2148 break;
2149 case FLOW_MODE_LOC_SEND:
2150 /* disable Rx flow-control */
2151 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2152 break;
2153 case FLOW_MODE_SYMMETRIC:
2154 case FLOW_MODE_SYM_OR_REM:
2155 /* enable Tx & Rx flow-control */
2156 break;
baef58b1
SH		 2157 }
2158
6b0c1480 2159 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2160 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2161
baef58b1 2162 yukon_init(hw, port);
baef58b1
SH		 2163
2164 /* MIB clear */
6b0c1480
SH		 2165 reg = gma_read16(hw, port, GM_PHY_ADDR);
2166 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2167
2168 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2169 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2170 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2171
2172 /* transmit control */
6b0c1480 2173 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2174
2175 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2176 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2177 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2178
2179 /* transmit flow control */
6b0c1480 2180 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2181
2182 /* transmit parameter */
6b0c1480 2183 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2184 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2185 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2186 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2187
44c7fcce
SH		 2188 /* configure the Serial Mode Register */
2189 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2190 | GM_SMOD_VLAN_ENA
2191 | IPG_DATA_VAL(IPG_DATA_DEF);
2192
2193 if (hw->dev[port]->mtu > ETH_DATA_LEN)
baef58b1
SH		 2194 reg |= GM_SMOD_JUMBO_ENA;
2195
6b0c1480 2196 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2197
2198 /* physical address: used for pause frames */
6b0c1480 2199 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2200 /* virtual address for data */
6b0c1480 2201 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2202
2203 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2204 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2205 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2206 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2207
2208 /* Initialize Mac Fifo */
2209
2210 /* Configure Rx MAC FIFO */
6b0c1480 2211 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2212 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2213
2214 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2215 if (is_yukon_lite_a0(hw))
baef58b1 2216 reg &= ~GMF_RX_F_FL_ON;
c8868611 2217
6b0c1480
SH		 2218 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2219 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2220 /*
2221 * because Pause Packet Truncation in GMAC is not working
2222 * we have to increase the Flush Threshold to 64 bytes
2223 * in order to flush pause packets in Rx FIFO on Yukon-1
2224 */
2225 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2226
2227 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2228 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2229 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2230}
2231
355ec572
SH		 2232/* Go into power down mode */
2233static void yukon_suspend(struct skge_hw *hw, int port)
2234{
2235 u16 ctrl;
2236
2237 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2238 ctrl |= PHY_M_PC_POL_R_DIS;
2239 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2240
2241 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2242 ctrl |= PHY_CT_RESET;
2243 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2244
2245 /* switch IEEE compatible power down mode on */
2246 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2247 ctrl |= PHY_CT_PDOWN;
2248 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2249}
2250
baef58b1
SH		 2251static void yukon_stop(struct skge_port *skge)
2252{
2253 struct skge_hw *hw = skge->hw;
2254 int port = skge->port;
2255
46a60f2d
SH		 2256 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2257 yukon_reset(hw, port);
baef58b1 2258
6b0c1480
SH		 2259 gma_write16(hw, port, GM_GP_CTRL,
2260 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2261 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2262 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2263
355ec572 2264 yukon_suspend(hw, port);
46a60f2d 2265
baef58b1 2266 /* set GPHY Control reset */
46a60f2d
SH		 2267 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2268 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2269}
2270
2271static void yukon_get_stats(struct skge_port *skge, u64 *data)
2272{
2273 struct skge_hw *hw = skge->hw;
2274 int port = skge->port;
2275 int i;
2276
6b0c1480
SH		 2277 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2278 | gma_read32(hw, port, GM_TXO_OK_LO);
2279 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2280 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2281
2282 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2283 data[i] = gma_read32(hw, port,
baef58b1
SH		 2284 skge_stats[i].gma_offset);
2285}
2286
2287static void yukon_mac_intr(struct skge_hw *hw, int port)
2288{
7e676d91
SH		 2289 struct net_device *dev = hw->dev[port];
2290 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2291 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2292
d707204c
JP		 2293 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2294 "mac interrupt status 0x%x\n", status);
7e676d91 2295
baef58b1 2296 if (status & GM_IS_RX_FF_OR) {
da00772f 2297 ++dev->stats.rx_fifo_errors;
d8a09943 2298 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2299 }
d8a09943 2300
baef58b1 2301 if (status & GM_IS_TX_FF_UR) {
da00772f 2302 ++dev->stats.tx_fifo_errors;
d8a09943 2303 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2304 }
2305
2306}
2307
2308static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2309{
95566065 2310 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2311 case PHY_M_PS_SPEED_1000:
2312 return SPEED_1000;
2313 case PHY_M_PS_SPEED_100:
2314 return SPEED_100;
2315 default:
2316 return SPEED_10;
2317 }
2318}
2319
2320static void yukon_link_up(struct skge_port *skge)
2321{
2322 struct skge_hw *hw = skge->hw;
2323 int port = skge->port;
2324 u16 reg;
2325
baef58b1 2326 /* Enable Transmit FIFO Underrun */
46a60f2d 2327 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2328
6b0c1480 2329 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2330 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2331 reg |= GM_GPCR_DUP_FULL;
2332
2333 /* enable Rx/Tx */
2334 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2335 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2336
4cde06ed 2337 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2338 skge_link_up(skge);
2339}
2340
2341static void yukon_link_down(struct skge_port *skge)
2342{
2343 struct skge_hw *hw = skge->hw;
2344 int port = skge->port;
d8a09943 2345 u16 ctrl;
baef58b1 2346
d8a09943
SH		 2347 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2348 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2349 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2350
5d5c8e03
SH		 2351 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2352 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2353 ctrl |= PHY_M_AN_ASP;
baef58b1 2354 /* restore Asymmetric Pause bit */
5d5c8e03 2355 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2356 }
2357
baef58b1
SH		 2358 skge_link_down(skge);
2359
2360 yukon_init(hw, port);
2361}
2362
2363static void yukon_phy_intr(struct skge_port *skge)
2364{
2365 struct skge_hw *hw = skge->hw;
2366 int port = skge->port;
2367 const char *reason = NULL;
2368 u16 istatus, phystat;
2369
6b0c1480
SH		 2370 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2371 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91 2372
d707204c
JP		 2373 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2374 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
baef58b1
SH		 2375
2376 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2377 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2378 & PHY_M_AN_RF) {
2379 reason = "remote fault";
2380 goto failed;
2381 }
2382
c506a509 2383 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2384 reason = "master/slave fault";
2385 goto failed;
2386 }
2387
2388 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2389 reason = "speed/duplex";
2390 goto failed;
2391 }
2392
2393 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2394 ? DUPLEX_FULL : DUPLEX_HALF;
2395 skge->speed = yukon_speed(hw, phystat);
2396
baef58b1
SH		 2397 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2398 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2399 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2400 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2401 break;
2402 case PHY_M_PS_RX_P_EN:
5d5c8e03 2403 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2404 break;
2405 case PHY_M_PS_TX_P_EN:
5d5c8e03 2406 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2407 break;
2408 default:
5d5c8e03 2409 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2410 }
2411
5d5c8e03 2412 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2413 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2414 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2415 else
6b0c1480 2416 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2417 yukon_link_up(skge);
2418 return;
2419 }
2420
2421 if (istatus & PHY_M_IS_LSP_CHANGE)
2422 skge->speed = yukon_speed(hw, phystat);
2423
2424 if (istatus & PHY_M_IS_DUP_CHANGE)
2425 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2426 if (istatus & PHY_M_IS_LST_CHANGE) {
2427 if (phystat & PHY_M_PS_LINK_UP)
2428 yukon_link_up(skge);
2429 else
2430 yukon_link_down(skge);
2431 }
2432 return;
2433 failed:
f15063cd 2434 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
baef58b1
SH		 2435
2436 /* XXX restart autonegotiation? */
2437}
2438
ee294dcd
SH		 2439static void skge_phy_reset(struct skge_port *skge)
2440{
2441 struct skge_hw *hw = skge->hw;
2442 int port = skge->port;
aae343d4 2443 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2444
2445 netif_stop_queue(skge->netdev);
2446 netif_carrier_off(skge->netdev);
2447
9cbe330f 2448 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2449 if (hw->chip_id == CHIP_ID_GENESIS) {
2450 genesis_reset(hw, port);
2451 genesis_mac_init(hw, port);
2452 } else {
2453 yukon_reset(hw, port);
2454 yukon_init(hw, port);
2455 }
9cbe330f 2456 spin_unlock_bh(&hw->phy_lock);
75814090 2457
f80d032b 2458 skge_set_multicast(dev);
ee294dcd
SH		 2459}
2460
2cd8e5d3
SH		 2461/* Basic MII support */
2462static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2463{
2464 struct mii_ioctl_data *data = if_mii(ifr);
2465 struct skge_port *skge = netdev_priv(dev);
2466 struct skge_hw *hw = skge->hw;
2467 int err = -EOPNOTSUPP;
2468
2469 if (!netif_running(dev))
2470 return -ENODEV; /* Phy still in reset */
2471
67777f9b 2472 switch (cmd) {
2cd8e5d3
SH		 2473 case SIOCGMIIPHY:
2474 data->phy_id = hw->phy_addr;
2475
2476 /* fallthru */
2477 case SIOCGMIIREG: {
2478 u16 val = 0;
9cbe330f 2479 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2480 if (hw->chip_id == CHIP_ID_GENESIS)
2481 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2482 else
2483 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2484 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2485 data->val_out = val;
2486 break;
2487 }
2488
2489 case SIOCSMIIREG:
9cbe330f 2490 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2491 if (hw->chip_id == CHIP_ID_GENESIS)
2492 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2493 data->val_in);
2494 else
2495 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2496 data->val_in);
9cbe330f 2497 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2498 break;
2499 }
2500 return err;
2501}
2502
279e1dab 2503static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
baef58b1
SH		 2504{
2505 u32 end;
2506
279e1dab
LT		 2507 start /= 8;
2508 len /= 8;
2509 end = start + len - 1;
baef58b1
SH		 2510
2511 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2512 skge_write32(hw, RB_ADDR(q, RB_START), start);
2513 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2514 skge_write32(hw, RB_ADDR(q, RB_RP), start);
279e1dab 2515 skge_write32(hw, RB_ADDR(q, RB_END), end);
baef58b1
SH		 2516
2517 if (q == Q_R1 || q == Q_R2) {
2518 /* Set thresholds on receive queue's */
279e1dab
LT		 2519 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2520 start + (2*len)/3);
2521 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2522 start + (len/3));
2523 } else {
2524 /* Enable store & forward on Tx queue's because
2525 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2526 */
baef58b1 2527 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
279e1dab 2528 }
baef58b1
SH		 2529
2530 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2531}
2532
2533/* Setup Bus Memory Interface */
2534static void skge_qset(struct skge_port *skge, u16 q,
2535 const struct skge_element *e)
2536{
2537 struct skge_hw *hw = skge->hw;
2538 u32 watermark = 0x600;
2539 u64 base = skge->dma + (e->desc - skge->mem);
2540
2541 /* optimization to reduce window on 32bit/33mhz */
2542 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2543 watermark /= 2;
2544
2545 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2546 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2547 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2548 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2549}
2550
2551static int skge_up(struct net_device *dev)
2552{
2553 struct skge_port *skge = netdev_priv(dev);
2554 struct skge_hw *hw = skge->hw;
2555 int port = skge->port;
279e1dab 2556 u32 chunk, ram_addr;
baef58b1
SH		 2557 size_t rx_size, tx_size;
2558 int err;
2559
fae87592
SH		 2560 if (!is_valid_ether_addr(dev->dev_addr))
2561 return -EINVAL;
2562
d707204c 2563 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
baef58b1 2564
19a33d4e 2565 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2566 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2567 else
2568 skge->rx_buf_size = RX_BUF_SIZE;
2569
2570
baef58b1
SH		 2571 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2572 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2573 skge->mem_size = tx_size + rx_size;
2574 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2575 if (!skge->mem)
2576 return -ENOMEM;
2577
c3da1447
SH		 2578 BUG_ON(skge->dma & 7);
2579
2580 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2581 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2582 err = -EINVAL;
2583 goto free_pci_mem;
2584 }
2585
baef58b1
SH		 2586 memset(skge->mem, 0, skge->mem_size);
2587
203babb6
SH		 2588 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2589 if (err)
baef58b1
SH		 2590 goto free_pci_mem;
2591
c54f9765 2592 err = skge_rx_fill(dev);
19a33d4e 2593 if (err)
baef58b1
SH		 2594 goto free_rx_ring;
2595
203babb6
SH		 2596 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2597 skge->dma + rx_size);
2598 if (err)
baef58b1
SH		 2599 goto free_rx_ring;
2600
8f3f8193 2601 /* Initialize MAC */
9cbe330f 2602 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2603 if (hw->chip_id == CHIP_ID_GENESIS)
2604 genesis_mac_init(hw, port);
2605 else
2606 yukon_mac_init(hw, port);
9cbe330f 2607 spin_unlock_bh(&hw->phy_lock);
baef58b1 2608
29816d9a
SH		 2609 /* Configure RAMbuffers - equally between ports and tx/rx */
2610 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
279e1dab 2611 ram_addr = hw->ram_offset + 2 * chunk * port;
baef58b1 2612
279e1dab 2613 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
7fb7ac24 2614 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
279e1dab 2615
baef58b1 2616 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
279e1dab 2617 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
baef58b1
SH		 2618 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2619
2620 /* Start receiver BMU */
2621 wmb();
2622 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2623 skge_led(skge, LED_MODE_ON);
baef58b1 2624
4ebabfcb
SH		 2625 spin_lock_irq(&hw->hw_lock);
2626 hw->intr_mask |= portmask[port];
2627 skge_write32(hw, B0_IMSK, hw->intr_mask);
2628 spin_unlock_irq(&hw->hw_lock);
2629
bea3348e 2630 napi_enable(&skge->napi);
baef58b1
SH		 2631 return 0;
2632
2633 free_rx_ring:
2634 skge_rx_clean(skge);
2635 kfree(skge->rx_ring.start);
2636 free_pci_mem:
2637 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2638 skge->mem = NULL;
baef58b1
SH		 2639
2640 return err;
2641}
2642
60b24b51
SH		 2643/* stop receiver */
2644static void skge_rx_stop(struct skge_hw *hw, int port)
2645{
2646 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2647 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2648 RB_RST_SET|RB_DIS_OP_MD);
2649 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2650}
2651
baef58b1
SH		 2652static int skge_down(struct net_device *dev)
2653{
2654 struct skge_port *skge = netdev_priv(dev);
2655 struct skge_hw *hw = skge->hw;
2656 int port = skge->port;
2657
7731a4ea
SH		 2658 if (skge->mem == NULL)
2659 return 0;
2660
d707204c 2661 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
baef58b1 2662
d119b392 2663 netif_tx_disable(dev);
692412b3 2664
64f6b64d 2665 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2666 del_timer_sync(&skge->link_timer);
baef58b1 2667
bea3348e 2668 napi_disable(&skge->napi);
692412b3 2669 netif_carrier_off(dev);
4ebabfcb
SH		 2670
2671 spin_lock_irq(&hw->hw_lock);
2672 hw->intr_mask &= ~portmask[port];
2673 skge_write32(hw, B0_IMSK, hw->intr_mask);
2674 spin_unlock_irq(&hw->hw_lock);
2675
46a60f2d
SH		 2676 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2677 if (hw->chip_id == CHIP_ID_GENESIS)
2678 genesis_stop(skge);
2679 else
2680 yukon_stop(skge);
2681
baef58b1
SH		 2682 /* Stop transmitter */
2683 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2684 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2685 RB_RST_SET|RB_DIS_OP_MD);
2686
baef58b1
SH		 2687
2688 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2689 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2690 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2691
2692 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2693 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2694 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2695
2696 /* Reset PCI FIFO */
2697 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2698 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2699
2700 /* Reset the RAM Buffer async Tx queue */
2701 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
60b24b51
SH		 2702
2703 skge_rx_stop(hw, port);
baef58b1
SH		 2704
2705 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2706 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2707 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2708 } else {
6b0c1480
SH		 2709 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2710 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2711 }
2712
6abebb53 2713 skge_led(skge, LED_MODE_OFF);
baef58b1 2714
e3a1b99f 2715 netif_tx_lock_bh(dev);
513f533e 2716 skge_tx_clean(dev);
e3a1b99f
SH		 2717 netif_tx_unlock_bh(dev);
2718
baef58b1
SH		 2719 skge_rx_clean(skge);
2720
2721 kfree(skge->rx_ring.start);
2722 kfree(skge->tx_ring.start);
2723 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2724 skge->mem = NULL;
baef58b1
SH		 2725 return 0;
2726}
2727
29b4e886
SH		 2728static inline int skge_avail(const struct skge_ring *ring)
2729{
992c9623 2730 smp_mb();
29b4e886
SH		 2731 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2732 + (ring->to_clean - ring->to_use) - 1;
2733}
2734
61357325
SH		 2735static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2736 struct net_device *dev)
baef58b1
SH		 2737{
2738 struct skge_port *skge = netdev_priv(dev);
2739 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2740 struct skge_element *e;
2741 struct skge_tx_desc *td;
2742 int i;
2743 u32 control, len;
2744 u64 map;
baef58b1 2745
5b057c6b 2746 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2747 return NETDEV_TX_OK;
2748
513f533e 2749 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2750 return NETDEV_TX_BUSY;
baef58b1 2751
7c442fa1 2752 e = skge->tx_ring.to_use;
baef58b1 2753 td = e->desc;
7c442fa1 2754 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2755 e->skb = skb;
2756 len = skb_headlen(skb);
2757 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2758 pci_unmap_addr_set(e, mapaddr, map);
2759 pci_unmap_len_set(e, maplen, len);
2760
2761 td->dma_lo = map;
2762 td->dma_hi = map >> 32;
2763
84fa7933 2764 if (skb->ip_summed == CHECKSUM_PARTIAL) {
ea2ae17d 2765 const int offset = skb_transport_offset(skb);
baef58b1
SH		 2766
2767 /* This seems backwards, but it is what the sk98lin
2768 * does. Looks like hardware is wrong?
2769 */
8e95a202 2770 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
67777f9b 2771 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2772 control = BMU_TCP_CHECK;
2773 else
2774 control = BMU_UDP_CHECK;
2775
2776 td->csum_offs = 0;
2777 td->csum_start = offset;
ff1dcadb 2778 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2779 } else
2780 control = BMU_CHECK;
2781
2782 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
67777f9b 2783 control |= BMU_EOF | BMU_IRQ_EOF;
baef58b1
SH		 2784 else {
2785 struct skge_tx_desc *tf = td;
2786
2787 control |= BMU_STFWD;
2788 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2789 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2790
2791 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2792 frag->size, PCI_DMA_TODEVICE);
2793
2794 e = e->next;
7c442fa1 2795 e->skb = skb;
baef58b1 2796 tf = e->desc;
7c442fa1
SH		 2797 BUG_ON(tf->control & BMU_OWN);
2798
baef58b1
SH		 2799 tf->dma_lo = map;
2800 tf->dma_hi = (u64) map >> 32;
2801 pci_unmap_addr_set(e, mapaddr, map);
2802 pci_unmap_len_set(e, maplen, frag->size);
2803
2804 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2805 }
2806 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2807 }
2808 /* Make sure all the descriptors written */
2809 wmb();
2810 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2811 wmb();
2812
2813 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2814
d707204c
JP		 2815 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2816 "tx queued, slot %td, len %d\n",
2817 e - skge->tx_ring.start, skb->len);
baef58b1 2818
7c442fa1 2819 skge->tx_ring.to_use = e->next;
992c9623
SH		 2820 smp_wmb();
2821
9db96479 2822 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
f15063cd 2823 netdev_dbg(dev, "transmit queue full\n");
baef58b1
SH		 2824 netif_stop_queue(dev);
2825 }
2826
baef58b1
SH		 2827 return NETDEV_TX_OK;
2828}
2829
7c442fa1
SH		 2830
2831/* Free resources associated with this reing element */
2832static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2833 u32 control)
866b4f3e
SH		 2834{
2835 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2836
7c442fa1
SH		 2837 /* skb header vs. fragment */
2838 if (control & BMU_STF)
866b4f3e 2839 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2840 pci_unmap_len(e, maplen),
2841 PCI_DMA_TODEVICE);
2842 else
2843 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2844 pci_unmap_len(e, maplen),
2845 PCI_DMA_TODEVICE);
866b4f3e 2846
7c442fa1 2847 if (control & BMU_EOF) {
d707204c
JP		 2848 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2849 "tx done slot %td\n", e - skge->tx_ring.start);
866b4f3e 2850
513f533e 2851 dev_kfree_skb(e->skb);
baef58b1
SH		 2852 }
2853}
2854
7c442fa1 2855/* Free all buffers in transmit ring */
513f533e 2856static void skge_tx_clean(struct net_device *dev)
baef58b1 2857{
513f533e 2858 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2859 struct skge_element *e;
baef58b1 2860
7c442fa1
SH		 2861 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2862 struct skge_tx_desc *td = e->desc;
2863 skge_tx_free(skge, e, td->control);
2864 td->control = 0;
2865 }
2866
2867 skge->tx_ring.to_clean = e;
baef58b1
SH		 2868}
2869
2870static void skge_tx_timeout(struct net_device *dev)
2871{
2872 struct skge_port *skge = netdev_priv(dev);
2873
d707204c 2874 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
baef58b1
SH		 2875
2876 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2877 skge_tx_clean(dev);
d119b392 2878 netif_wake_queue(dev);
baef58b1
SH		 2879}
2880
2881static int skge_change_mtu(struct net_device *dev, int new_mtu)
2882{
7731a4ea 2883 int err;
baef58b1 2884
95566065 2885 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2886 return -EINVAL;
2887
7731a4ea
SH		 2888 if (!netif_running(dev)) {
2889 dev->mtu = new_mtu;
2890 return 0;
2891 }
2892
1a8098be 2893 skge_down(dev);
baef58b1 2894
19a33d4e 2895 dev->mtu = new_mtu;
7731a4ea 2896
1a8098be 2897 err = skge_up(dev);
7731a4ea
SH		 2898 if (err)
2899 dev_close(dev);
baef58b1
SH		 2900
2901 return err;
2902}
2903
c4cd29d2
SH		 2904static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2905
2906static void genesis_add_filter(u8 filter[8], const u8 *addr)
2907{
2908 u32 crc, bit;
2909
2910 crc = ether_crc_le(ETH_ALEN, addr);
2911 bit = ~crc & 0x3f;
2912 filter[bit/8] |= 1 << (bit%8);
2913}
2914
baef58b1
SH		 2915static void genesis_set_multicast(struct net_device *dev)
2916{
2917 struct skge_port *skge = netdev_priv(dev);
2918 struct skge_hw *hw = skge->hw;
2919 int port = skge->port;
5508590c 2920 struct dev_mc_list *list;
baef58b1
SH		 2921 u32 mode;
2922 u8 filter[8];
2923
6b0c1480 2924 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2925 mode |= XM_MD_ENA_HASH;
2926 if (dev->flags & IFF_PROMISC)
2927 mode |= XM_MD_ENA_PROM;
2928 else
2929 mode &= ~XM_MD_ENA_PROM;
2930
2931 if (dev->flags & IFF_ALLMULTI)
2932 memset(filter, 0xff, sizeof(filter));
2933 else {
2934 memset(filter, 0, sizeof(filter));
c4cd29d2 2935
8e95a202
JP		 2936 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2937 skge->flow_status == FLOW_STAT_SYMMETRIC)
c4cd29d2
SH		 2938 genesis_add_filter(filter, pause_mc_addr);
2939
5508590c 2940 netdev_for_each_mc_addr(list, dev)
c4cd29d2 2941 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2942 }
2943
6b0c1480 2944 xm_write32(hw, port, XM_MODE, mode);
45bada65 2945 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2946}
2947
c4cd29d2
SH		 2948static void yukon_add_filter(u8 filter[8], const u8 *addr)
2949{
2950 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2951 filter[bit/8] |= 1 << (bit%8);
2952}
2953
baef58b1
SH		 2954static void yukon_set_multicast(struct net_device *dev)
2955{
2956 struct skge_port *skge = netdev_priv(dev);
2957 struct skge_hw *hw = skge->hw;
2958 int port = skge->port;
5508590c 2959 struct dev_mc_list *list;
8e95a202
JP		 2960 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2961 skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2962 u16 reg;
2963 u8 filter[8];
2964
2965 memset(filter, 0, sizeof(filter));
2966
6b0c1480 2967 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2968 reg |= GM_RXCR_UCF_ENA;
2969
8f3f8193 2970 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2971 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2972 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2973 memset(filter, 0xff, sizeof(filter));
4cd24eaf 2974 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
baef58b1
SH		 2975 reg &= ~GM_RXCR_MCF_ENA;
2976 else {
baef58b1
SH		 2977 reg |= GM_RXCR_MCF_ENA;
2978
c4cd29d2
SH		 2979 if (rx_pause)
2980 yukon_add_filter(filter, pause_mc_addr);
2981
5508590c 2982 netdev_for_each_mc_addr(list, dev)
c4cd29d2 2983 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2984 }
2985
2986
6b0c1480 2987 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2988 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2989 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2990 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2991 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2992 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2993 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2994 (u16)filter[6] | ((u16)filter[7] << 8));
2995
6b0c1480 2996 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2997}
2998
383181ac
SH		 2999static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3000{
3001 if (hw->chip_id == CHIP_ID_GENESIS)
3002 return status >> XMR_FS_LEN_SHIFT;
3003 else
3004 return status >> GMR_FS_LEN_SHIFT;
3005}
3006
baef58b1
SH		 3007static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3008{
3009 if (hw->chip_id == CHIP_ID_GENESIS)
3010 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3011 else
3012 return (status & GMR_FS_ANY_ERR) ||
3013 (status & GMR_FS_RX_OK) == 0;
3014}
3015
f80d032b
SH		 3016static void skge_set_multicast(struct net_device *dev)
3017{
3018 struct skge_port *skge = netdev_priv(dev);
3019 struct skge_hw *hw = skge->hw;
3020
3021 if (hw->chip_id == CHIP_ID_GENESIS)
3022 genesis_set_multicast(dev);
3023 else
3024 yukon_set_multicast(dev);
3025
3026}
3027
19a33d4e
SH		 3028
3029/* Get receive buffer from descriptor.
3030 * Handles copy of small buffers and reallocation failures
3031 */
c54f9765
SH		 3032static struct sk_buff *skge_rx_get(struct net_device *dev,
3033 struct skge_element *e,
3034 u32 control, u32 status, u16 csum)
19a33d4e 3035{
c54f9765 3036 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 3037 struct sk_buff *skb;
3038 u16 len = control & BMU_BBC;
3039
d707204c
JP		 3040 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3041 "rx slot %td status 0x%x len %d\n",
3042 e - skge->rx_ring.start, status, len);
383181ac
SH		 3043
3044 if (len > skge->rx_buf_size)
3045 goto error;
3046
3047 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3048 goto error;
3049
3050 if (bad_phy_status(skge->hw, status))
3051 goto error;
3052
3053 if (phy_length(skge->hw, status) != len)
3054 goto error;
19a33d4e
SH		 3055
3056 if (len < RX_COPY_THRESHOLD) {
89d71a66 3057 skb = netdev_alloc_skb_ip_align(dev, len);
383181ac
SH		 3058 if (!skb)
3059 goto resubmit;
19a33d4e
SH		 3060
3061 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3062 pci_unmap_addr(e, mapaddr),
3063 len, PCI_DMA_FROMDEVICE);
d626f62b 3064 skb_copy_from_linear_data(e->skb, skb->data, len);
19a33d4e
SH		 3065 pci_dma_sync_single_for_device(skge->hw->pdev,
3066 pci_unmap_addr(e, mapaddr),
3067 len, PCI_DMA_FROMDEVICE);
19a33d4e 3068 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 3069 } else {
383181ac 3070 struct sk_buff *nskb;
89d71a66
ED		 3071
3072 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
383181ac
SH		 3073 if (!nskb)
3074 goto resubmit;
19a33d4e
SH		 3075
3076 pci_unmap_single(skge->hw->pdev,
3077 pci_unmap_addr(e, mapaddr),
3078 pci_unmap_len(e, maplen),
3079 PCI_DMA_FROMDEVICE);
3080 skb = e->skb;
67777f9b 3081 prefetch(skb->data);
19a33d4e 3082 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 3083 }
383181ac
SH		 3084
3085 skb_put(skb, len);
383181ac
SH		 3086 if (skge->rx_csum) {
3087 skb->csum = csum;
84fa7933 3088 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 3089 }
3090
c54f9765 3091 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 3092
3093 return skb;
3094error:
3095
d707204c
JP		 3096 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3097 "rx err, slot %td control 0x%x status 0x%x\n",
3098 e - skge->rx_ring.start, control, status);
383181ac
SH		 3099
3100 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3101 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
da00772f 3102 dev->stats.rx_length_errors++;
383181ac 3103 if (status & XMR_FS_FRA_ERR)
da00772f 3104 dev->stats.rx_frame_errors++;
383181ac 3105 if (status & XMR_FS_FCS_ERR)
da00772f 3106 dev->stats.rx_crc_errors++;
383181ac
SH		 3107 } else {
3108 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
da00772f 3109 dev->stats.rx_length_errors++;
383181ac 3110 if (status & GMR_FS_FRAGMENT)
da00772f 3111 dev->stats.rx_frame_errors++;
383181ac 3112 if (status & GMR_FS_CRC_ERR)
da00772f 3113 dev->stats.rx_crc_errors++;
383181ac
SH		 3114 }
3115
3116resubmit:
3117 skge_rx_reuse(e, skge->rx_buf_size);
3118 return NULL;
baef58b1
SH		 3119}
3120
7c442fa1 3121/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 3122static void skge_tx_done(struct net_device *dev)
00a6cae2 3123{
7c442fa1 3124 struct skge_port *skge = netdev_priv(dev);
00a6cae2 3125 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 3126 struct skge_element *e;
3127
513f533e 3128 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3129
866b4f3e 3130 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
992c9623 3131 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
00a6cae2 3132
992c9623 3133 if (control & BMU_OWN)
00a6cae2
SH		 3134 break;
3135
992c9623 3136 skge_tx_free(skge, e, control);
00a6cae2 3137 }
7c442fa1 3138 skge->tx_ring.to_clean = e;
866b4f3e 3139
992c9623
SH		 3140 /* Can run lockless until we need to synchronize to restart queue. */
3141 smp_mb();
3142
3143 if (unlikely(netif_queue_stopped(dev) &&
3144 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3145 netif_tx_lock(dev);
3146 if (unlikely(netif_queue_stopped(dev) &&
3147 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3148 netif_wake_queue(dev);
00a6cae2 3149
992c9623
SH		 3150 }
3151 netif_tx_unlock(dev);
3152 }
00a6cae2 3153}
19a33d4e 3154
bea3348e 3155static int skge_poll(struct napi_struct *napi, int to_do)
baef58b1 3156{
bea3348e
SH		 3157 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3158 struct net_device *dev = skge->netdev;
baef58b1
SH		 3159 struct skge_hw *hw = skge->hw;
3160 struct skge_ring *ring = &skge->rx_ring;
3161 struct skge_element *e;
00a6cae2
SH		 3162 int work_done = 0;
3163
513f533e
SH		 3164 skge_tx_done(dev);
3165
3166 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3167
1631aef1 3168 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3169 struct skge_rx_desc *rd = e->desc;
19a33d4e 3170 struct sk_buff *skb;
383181ac 3171 u32 control;
baef58b1
SH		 3172
3173 rmb();
3174 control = rd->control;
3175 if (control & BMU_OWN)
3176 break;
3177
c54f9765 3178 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3179 if (likely(skb)) {
19a33d4e 3180 netif_receive_skb(skb);
baef58b1 3181
19a33d4e 3182 ++work_done;
5a011447 3183 }
baef58b1
SH		 3184 }
3185 ring->to_clean = e;
3186
baef58b1
SH		 3187 /* restart receiver */
3188 wmb();
a9cdab86 3189 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3190
bea3348e 3191 if (work_done < to_do) {
6ef2977d 3192 unsigned long flags;
f0c88f9c 3193
6ef2977d 3194 spin_lock_irqsave(&hw->hw_lock, flags);
288379f0 3195 __napi_complete(napi);
bea3348e
SH		 3196 hw->intr_mask |= napimask[skge->port];
3197 skge_write32(hw, B0_IMSK, hw->intr_mask);
3198 skge_read32(hw, B0_IMSK);
6ef2977d 3199 spin_unlock_irqrestore(&hw->hw_lock, flags);
bea3348e 3200 }
1631aef1 3201
bea3348e 3202 return work_done;
baef58b1
SH		 3203}
3204
f6620cab
SH		 3205/* Parity errors seem to happen when Genesis is connected to a switch
3206 * with no other ports present. Heartbeat error??
3207 */
baef58b1
SH		 3208static void skge_mac_parity(struct skge_hw *hw, int port)
3209{
f6620cab
SH		 3210 struct net_device *dev = hw->dev[port];
3211
da00772f 3212 ++dev->stats.tx_heartbeat_errors;
baef58b1
SH		 3213
3214 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3215 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3216 MFF_CLR_PERR);
3217 else
3218 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3219 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3220 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3221 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3222}
3223
baef58b1
SH		 3224static void skge_mac_intr(struct skge_hw *hw, int port)
3225{
95566065 3226 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3227 genesis_mac_intr(hw, port);
3228 else
3229 yukon_mac_intr(hw, port);
3230}
3231
3232/* Handle device specific framing and timeout interrupts */
3233static void skge_error_irq(struct skge_hw *hw)
3234{
1479d13c 3235 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3236 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3237
3238 if (hw->chip_id == CHIP_ID_GENESIS) {
3239 /* clear xmac errors */
3240 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3241 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3242 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3243 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3244 } else {
3245 /* Timestamp (unused) overflow */
3246 if (hwstatus & IS_IRQ_TIST_OV)
3247 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3248 }
3249
3250 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3251 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3252 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3253 }
3254
3255 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3256 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3257 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3258 }
3259
3260 if (hwstatus & IS_M1_PAR_ERR)
3261 skge_mac_parity(hw, 0);
3262
3263 if (hwstatus & IS_M2_PAR_ERR)
3264 skge_mac_parity(hw, 1);
3265
b9d64acc 3266 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3267 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3268 hw->dev[0]->name);
baef58b1 3269 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3270 }
baef58b1 3271
b9d64acc 3272 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3273 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3274 hw->dev[1]->name);
baef58b1 3275 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3276 }
baef58b1
SH		 3277
3278 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3279 u16 pci_status, pci_cmd;
3280
1479d13c
SH		 3281 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3282 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3283
1479d13c
SH		 3284 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3285 pci_cmd, pci_status);
b9d64acc
SH		 3286
3287 /* Write the error bits back to clear them. */
3288 pci_status &= PCI_STATUS_ERROR_BITS;
3289 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3290 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3291 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3292 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3293 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3294
050ec18a 3295 /* if error still set then just ignore it */
baef58b1
SH		 3296 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3297 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3298 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3299 hw->intr_mask &= ~IS_HW_ERR;
3300 }
3301 }
3302}
3303
3304/*
9cbe330f 3305 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3306 * because accessing phy registers requires spin wait which might
3307 * cause excess interrupt latency.
3308 */
9cbe330f 3309static void skge_extirq(unsigned long arg)
baef58b1 3310{
9cbe330f 3311 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3312 int port;
3313
cfc3ed79 3314 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3315 struct net_device *dev = hw->dev[port];
3316
cfc3ed79 3317 if (netif_running(dev)) {
9cbe330f
SH		 3318 struct skge_port *skge = netdev_priv(dev);
3319
3320 spin_lock(&hw->phy_lock);
baef58b1
SH		 3321 if (hw->chip_id != CHIP_ID_GENESIS)
3322 yukon_phy_intr(skge);
64f6b64d 3323 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3324 bcom_phy_intr(skge);
9cbe330f 3325 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3326 }
3327 }
baef58b1 3328
7c442fa1 3329 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3330 hw->intr_mask |= IS_EXT_REG;
3331 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3332 skge_read32(hw, B0_IMSK);
7c442fa1 3333 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3334}
3335
7d12e780 3336static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3337{
3338 struct skge_hw *hw = dev_id;
cfc3ed79 3339 u32 status;
29365c90 3340 int handled = 0;
baef58b1 3341
29365c90 3342 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3343 /* Reading this register masks IRQ */
3344 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3345 if (status == 0 || status == ~0)
29365c90 3346 goto out;
baef58b1 3347
29365c90 3348 handled = 1;
7c442fa1 3349 status &= hw->intr_mask;
cfc3ed79
SH		 3350 if (status & IS_EXT_REG) {
3351 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3352 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3353 }
3354
513f533e 3355 if (status & (IS_XA1_F|IS_R1_F)) {
bea3348e 3356 struct skge_port *skge = netdev_priv(hw->dev[0]);
513f533e 3357 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
288379f0 3358 napi_schedule(&skge->napi);
baef58b1
SH		 3359 }
3360
7c442fa1
SH		 3361 if (status & IS_PA_TO_TX1)
3362 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3363
d25f5a67 3364 if (status & IS_PA_TO_RX1) {
da00772f 3365 ++hw->dev[0]->stats.rx_over_errors;
7c442fa1 3366 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3367 }
3368
d25f5a67 3369
baef58b1
SH		 3370 if (status & IS_MAC1)
3371 skge_mac_intr(hw, 0);
95566065 3372
7c442fa1 3373 if (hw->dev[1]) {
bea3348e
SH		 3374 struct skge_port *skge = netdev_priv(hw->dev[1]);
3375
513f533e
SH		 3376 if (status & (IS_XA2_F|IS_R2_F)) {
3377 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
288379f0 3378 napi_schedule(&skge->napi);
7c442fa1
SH		 3379 }
3380
3381 if (status & IS_PA_TO_RX2) {
da00772f 3382 ++hw->dev[1]->stats.rx_over_errors;
7c442fa1
SH		 3383 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3384 }
3385
3386 if (status & IS_PA_TO_TX2)
3387 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3388
3389 if (status & IS_MAC2)
3390 skge_mac_intr(hw, 1);
3391 }
baef58b1
SH		 3392
3393 if (status & IS_HW_ERR)
3394 skge_error_irq(hw);
3395
7e676d91 3396 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3397 skge_read32(hw, B0_IMSK);
29365c90 3398out:
7c442fa1 3399 spin_unlock(&hw->hw_lock);
baef58b1 3400
29365c90 3401 return IRQ_RETVAL(handled);
baef58b1
SH		 3402}
3403
3404#ifdef CONFIG_NET_POLL_CONTROLLER
3405static void skge_netpoll(struct net_device *dev)
3406{
3407 struct skge_port *skge = netdev_priv(dev);
3408
3409 disable_irq(dev->irq);
7d12e780 3410 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3411 enable_irq(dev->irq);
3412}
3413#endif
3414
3415static int skge_set_mac_address(struct net_device *dev, void *p)
3416{
3417 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3418 struct skge_hw *hw = skge->hw;
3419 unsigned port = skge->port;
3420 const struct sockaddr *addr = p;
2eb3e621 3421 u16 ctrl;
baef58b1
SH		 3422
3423 if (!is_valid_ether_addr(addr->sa_data))
3424 return -EADDRNOTAVAIL;
3425
baef58b1 3426 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3427
9cbe330f
SH		 3428 if (!netif_running(dev)) {
3429 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3430 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3431 } else {
3432 /* disable Rx */
3433 spin_lock_bh(&hw->phy_lock);
3434 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3435 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3436
9cbe330f
SH		 3437 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3438 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3439
2eb3e621
SH		 3440 if (hw->chip_id == CHIP_ID_GENESIS)
3441 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3442 else {
3443 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3444 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3445 }
2eb3e621 3446
9cbe330f
SH		 3447 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3448 spin_unlock_bh(&hw->phy_lock);
3449 }
c2681dd8
SH		 3450
3451 return 0;
baef58b1
SH		 3452}
3453
3454static const struct {
3455 u8 id;
3456 const char *name;
3457} skge_chips[] = {
3458 { CHIP_ID_GENESIS, "Genesis" },
3459 { CHIP_ID_YUKON, "Yukon" },
3460 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3461 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3462};
3463
3464static const char *skge_board_name(const struct skge_hw *hw)
3465{
3466 int i;
3467 static char buf[16];
3468
3469 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3470 if (skge_chips[i].id == hw->chip_id)
3471 return skge_chips[i].name;
3472
3473 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3474 return buf;
3475}
3476
3477
3478/*
3479 * Setup the board data structure, but don't bring up
3480 * the port(s)
3481 */
3482static int skge_reset(struct skge_hw *hw)
3483{
adba9e23 3484 u32 reg;
b9d64acc 3485 u16 ctst, pci_status;
64f6b64d 3486 u8 t8, mac_cfg, pmd_type;
981d0377 3487 int i;
baef58b1
SH		 3488
3489 ctst = skge_read16(hw, B0_CTST);
3490
3491 /* do a SW reset */
3492 skge_write8(hw, B0_CTST, CS_RST_SET);
3493 skge_write8(hw, B0_CTST, CS_RST_CLR);
3494
3495 /* clear PCI errors, if any */
b9d64acc
SH		 3496 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3497 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3498
b9d64acc
SH		 3499 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3500 pci_write_config_word(hw->pdev, PCI_STATUS,
3501 pci_status | PCI_STATUS_ERROR_BITS);
3502 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3503 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3504
3505 /* restore CLK_RUN bits (for Yukon-Lite) */
3506 skge_write16(hw, B0_CTST,
3507 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3508
3509 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3510 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3511 pmd_type = skge_read8(hw, B2_PMD_TYP);
3512 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3513
95566065 3514 switch (hw->chip_id) {
baef58b1 3515 case CHIP_ID_GENESIS:
64f6b64d
SH		 3516 switch (hw->phy_type) {
3517 case SK_PHY_XMAC:
3518 hw->phy_addr = PHY_ADDR_XMAC;
3519 break;
baef58b1
SH		 3520 case SK_PHY_BCOM:
3521 hw->phy_addr = PHY_ADDR_BCOM;
3522 break;
3523 default:
1479d13c
SH		 3524 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3525 hw->phy_type);
baef58b1
SH		 3526 return -EOPNOTSUPP;
3527 }
3528 break;
3529
3530 case CHIP_ID_YUKON:
3531 case CHIP_ID_YUKON_LITE:
3532 case CHIP_ID_YUKON_LP:
64f6b64d 3533 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3534 hw->copper = 1;
baef58b1
SH		 3535
3536 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3537 break;
3538
3539 default:
1479d13c
SH		 3540 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3541 hw->chip_id);
baef58b1
SH		 3542 return -EOPNOTSUPP;
3543 }
3544
981d0377
SH		 3545 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3546 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3547 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3548
3549 /* read the adapters RAM size */
3550 t8 = skge_read8(hw, B2_E_0);
3551 if (hw->chip_id == CHIP_ID_GENESIS) {
3552 if (t8 == 3) {
3553 /* special case: 4 x 64k x 36, offset = 0x80000 */
279e1dab
LT		 3554 hw->ram_size = 0x100000;
3555 hw->ram_offset = 0x80000;
baef58b1
SH		 3556 } else
3557 hw->ram_size = t8 * 512;
67777f9b 3558 } else if (t8 == 0)
279e1dab
LT		 3559 hw->ram_size = 0x20000;
3560 else
3561 hw->ram_size = t8 * 4096;
baef58b1 3562
4ebabfcb 3563 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3564
4ebabfcb 3565 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3566 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3567 hw->intr_mask |= IS_EXT_REG;
3568
baef58b1
SH		 3569 if (hw->chip_id == CHIP_ID_GENESIS)
3570 genesis_init(hw);
3571 else {
3572 /* switch power to VCC (WA for VAUX problem) */
3573 skge_write8(hw, B0_POWER_CTRL,
3574 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3575
050ec18a
SH		 3576 /* avoid boards with stuck Hardware error bits */
3577 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3578 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3579 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3580 hw->intr_mask &= ~IS_HW_ERR;
3581 }
3582
adba9e23
SH		 3583 /* Clear PHY COMA */
3584 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3585 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3586 reg &= ~PCI_PHY_COMA;
3587 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3588 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3589
3590
981d0377 3591 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3592 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3593 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3594 }
3595 }
3596
3597 /* turn off hardware timer (unused) */
3598 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3599 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3600 skge_write8(hw, B0_LED, LED_STAT_ON);
3601
3602 /* enable the Tx Arbiters */
981d0377 3603 for (i = 0; i < hw->ports; i++)
6b0c1480 3604 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3605
3606 /* Initialize ram interface */
3607 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3608
3609 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3610 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3611 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3612 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3613 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3614 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3615 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3616 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3617 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3618 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3619 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3620 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3621
3622 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3623
3624 /* Set interrupt moderation for Transmit only
3625 * Receive interrupts avoided by NAPI
3626 */
3627 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3628 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3629 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3630
baef58b1
SH		 3631 skge_write32(hw, B0_IMSK, hw->intr_mask);
3632
981d0377 3633 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3634 if (hw->chip_id == CHIP_ID_GENESIS)
3635 genesis_reset(hw, i);
3636 else
3637 yukon_reset(hw, i);
3638 }
baef58b1
SH		 3639
3640 return 0;
3641}
3642
678aa1f6
SH		 3643
3644#ifdef CONFIG_SKGE_DEBUG
3645
3646static struct dentry *skge_debug;
3647
3648static int skge_debug_show(struct seq_file *seq, void *v)
3649{
3650 struct net_device *dev = seq->private;
3651 const struct skge_port *skge = netdev_priv(dev);
3652 const struct skge_hw *hw = skge->hw;
3653 const struct skge_element *e;
3654
3655 if (!netif_running(dev))
3656 return -ENETDOWN;
3657
3658 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3659 skge_read32(hw, B0_IMSK));
3660
3661 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3662 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3663 const struct skge_tx_desc *t = e->desc;
3664 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3665 t->control, t->dma_hi, t->dma_lo, t->status,
3666 t->csum_offs, t->csum_write, t->csum_start);
3667 }
3668
2381a55c 3669 seq_printf(seq, "\nRx Ring:\n");
678aa1f6
SH		 3670 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3671 const struct skge_rx_desc *r = e->desc;
3672
3673 if (r->control & BMU_OWN)
3674 break;
3675
3676 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3677 r->control, r->dma_hi, r->dma_lo, r->status,
3678 r->timestamp, r->csum1, r->csum1_start);
3679 }
3680
3681 return 0;
3682}
3683
3684static int skge_debug_open(struct inode *inode, struct file *file)
3685{
3686 return single_open(file, skge_debug_show, inode->i_private);
3687}
3688
3689static const struct file_operations skge_debug_fops = {
3690 .owner = THIS_MODULE,
3691 .open = skge_debug_open,
3692 .read = seq_read,
3693 .llseek = seq_lseek,
3694 .release = single_release,
3695};
3696
3697/*
3698 * Use network device events to create/remove/rename
3699 * debugfs file entries
3700 */
3701static int skge_device_event(struct notifier_block *unused,
3702 unsigned long event, void *ptr)
3703{
3704 struct net_device *dev = ptr;
3705 struct skge_port *skge;
3706 struct dentry *d;
3707
f80d032b 3708 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
678aa1f6
SH		 3709 goto done;
3710
3711 skge = netdev_priv(dev);
67777f9b 3712 switch (event) {
678aa1f6
SH		 3713 case NETDEV_CHANGENAME:
3714 if (skge->debugfs) {
3715 d = debugfs_rename(skge_debug, skge->debugfs,
3716 skge_debug, dev->name);
3717 if (d)
3718 skge->debugfs = d;
3719 else {
f15063cd 3720 netdev_info(dev, "rename failed\n");
678aa1f6
SH		 3721 debugfs_remove(skge->debugfs);
3722 }
3723 }
3724 break;
3725
3726 case NETDEV_GOING_DOWN:
3727 if (skge->debugfs) {
3728 debugfs_remove(skge->debugfs);
3729 skge->debugfs = NULL;
3730 }
3731 break;
3732
3733 case NETDEV_UP:
3734 d = debugfs_create_file(dev->name, S_IRUGO,
3735 skge_debug, dev,
3736 &skge_debug_fops);
3737 if (!d || IS_ERR(d))
f15063cd 3738 netdev_info(dev, "debugfs create failed\n");
678aa1f6
SH		 3739 else
3740 skge->debugfs = d;
3741 break;
3742 }
3743
3744done:
3745 return NOTIFY_DONE;
3746}
3747
3748static struct notifier_block skge_notifier = {
3749 .notifier_call = skge_device_event,
3750};
3751
3752
3753static __init void skge_debug_init(void)
3754{
3755 struct dentry *ent;
3756
3757 ent = debugfs_create_dir("skge", NULL);
3758 if (!ent || IS_ERR(ent)) {
f15063cd 3759 pr_info("debugfs create directory failed\n");
678aa1f6
SH		 3760 return;
3761 }
3762
3763 skge_debug = ent;
3764 register_netdevice_notifier(&skge_notifier);
3765}
3766
3767static __exit void skge_debug_cleanup(void)
3768{
3769 if (skge_debug) {
3770 unregister_netdevice_notifier(&skge_notifier);
3771 debugfs_remove(skge_debug);
3772 skge_debug = NULL;
3773 }
3774}
3775
3776#else
3777#define skge_debug_init()
3778#define skge_debug_cleanup()
3779#endif
3780
f80d032b
SH		 3781static const struct net_device_ops skge_netdev_ops = {
3782 .ndo_open = skge_up,
3783 .ndo_stop = skge_down,
00829823 3784 .ndo_start_xmit = skge_xmit_frame,
f80d032b
SH		 3785 .ndo_do_ioctl = skge_ioctl,
3786 .ndo_get_stats = skge_get_stats,
3787 .ndo_tx_timeout = skge_tx_timeout,
3788 .ndo_change_mtu = skge_change_mtu,
3789 .ndo_validate_addr = eth_validate_addr,
3790 .ndo_set_multicast_list = skge_set_multicast,
3791 .ndo_set_mac_address = skge_set_mac_address,
3792#ifdef CONFIG_NET_POLL_CONTROLLER
3793 .ndo_poll_controller = skge_netpoll,
3794#endif
3795};
3796
3797
baef58b1 3798/* Initialize network device */
981d0377
SH		 3799static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3800 int highmem)
baef58b1
SH		 3801{
3802 struct skge_port *skge;
3803 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3804
3805 if (!dev) {
1479d13c 3806 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3807 return NULL;
3808 }
3809
baef58b1 3810 SET_NETDEV_DEV(dev, &hw->pdev->dev);
f80d032b
SH		 3811 dev->netdev_ops = &skge_netdev_ops;
3812 dev->ethtool_ops = &skge_ethtool_ops;
baef58b1 3813 dev->watchdog_timeo = TX_WATCHDOG;
baef58b1 3814 dev->irq = hw->pdev->irq;
513f533e 3815
981d0377
SH		 3816 if (highmem)
3817 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3818
3819 skge = netdev_priv(dev);
bea3348e 3820 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
baef58b1
SH		 3821 skge->netdev = dev;
3822 skge->hw = hw;
3823 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3824
baef58b1
SH		 3825 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3826 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3827
3828 /* Auto speed and flow control */
3829 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3830 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3831 skge->duplex = -1;
3832 skge->speed = -1;
31b619c5 3833 skge->advertising = skge_supported_modes(hw);
5b982c5b 3834
7b55a4a3 3835 if (device_can_wakeup(&hw->pdev->dev)) {
5b982c5b 3836 skge->wol = wol_supported(hw) & WAKE_MAGIC;
7b55a4a3
RW		 3837 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3838 }
baef58b1
SH		 3839
3840 hw->dev[port] = dev;
3841
3842 skge->port = port;
3843
64f6b64d 3844 /* Only used for Genesis XMAC */
9cbe330f 3845 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3846
baef58b1
SH		 3847 if (hw->chip_id != CHIP_ID_GENESIS) {
3848 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3849 skge->rx_csum = 1;
3850 }
3851
3852 /* read the mac address */
3853 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3854 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3855
3856 /* device is off until link detection */
3857 netif_carrier_off(dev);
3858 netif_stop_queue(dev);
3859
3860 return dev;
3861}
3862
3863static void __devinit skge_show_addr(struct net_device *dev)
3864{
3865 const struct skge_port *skge = netdev_priv(dev);
3866
d707204c 3867 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
baef58b1
SH		 3868}
3869
3870static int __devinit skge_probe(struct pci_dev *pdev,
3871 const struct pci_device_id *ent)
3872{
3873 struct net_device *dev, *dev1;
3874 struct skge_hw *hw;
3875 int err, using_dac = 0;
3876
203babb6
SH		 3877 err = pci_enable_device(pdev);
3878 if (err) {
1479d13c 3879 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3880 goto err_out;
3881 }
3882
203babb6
SH		 3883 err = pci_request_regions(pdev, DRV_NAME);
3884 if (err) {
1479d13c 3885 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3886 goto err_out_disable_pdev;
3887 }
3888
3889 pci_set_master(pdev);
3890
6a35528a 3891 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
baef58b1 3892 using_dac = 1;
6a35528a 3893 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3894 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
93aea718 3895 using_dac = 0;
284901a9 3896 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
93aea718
SH		 3897 }
3898
3899 if (err) {
1479d13c 3900 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3901 goto err_out_free_regions;
baef58b1
SH		 3902 }
3903
3904#ifdef __BIG_ENDIAN
8f3f8193 3905 /* byte swap descriptors in hardware */
baef58b1
SH		 3906 {
3907 u32 reg;
3908
3909 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3910 reg |= PCI_REV_DESC;
3911 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3912 }
3913#endif
3914
3915 err = -ENOMEM;
415e69e6 3916 /* space for skge@pci:0000:04:00.0 */
67777f9b 3917 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
415e69e6 3918 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
baef58b1 3919 if (!hw) {
1479d13c 3920 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3921 goto err_out_free_regions;
3922 }
415e69e6 3923 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
baef58b1 3924
baef58b1 3925 hw->pdev = pdev;
d38efdd6 3926 spin_lock_init(&hw->hw_lock);
9cbe330f 3927 spin_lock_init(&hw->phy_lock);
164165da 3928 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
baef58b1
SH		 3929
3930 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3931 if (!hw->regs) {
1479d13c 3932 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3933 goto err_out_free_hw;
3934 }
3935
baef58b1
SH		 3936 err = skge_reset(hw);
3937 if (err)
ccdaa2a9 3938 goto err_out_iounmap;
baef58b1 3939
f15063cd
JP		 3940 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3941 DRV_VERSION,
3942 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3943 skge_board_name(hw), hw->chip_rev);
baef58b1 3944
ccdaa2a9
SH		 3945 dev = skge_devinit(hw, 0, using_dac);
3946 if (!dev)
baef58b1
SH		 3947 goto err_out_led_off;
3948
fae87592 3949 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3950 if (!is_valid_ether_addr(dev->dev_addr))
3951 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3952
203babb6
SH		 3953 err = register_netdev(dev);
3954 if (err) {
1479d13c 3955 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3956 goto err_out_free_netdev;
3957 }
3958
415e69e6 3959 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
ccdaa2a9 3960 if (err) {
1479d13c 3961 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3962 dev->name, pdev->irq);
3963 goto err_out_unregister;
3964 }
baef58b1
SH		 3965 skge_show_addr(dev);
3966
f1914226
MM		 3967 if (hw->ports > 1) {
3968 dev1 = skge_devinit(hw, 1, using_dac);
3969 if (dev1 && register_netdev(dev1) == 0)
baef58b1
SH		 3970 skge_show_addr(dev1);
3971 else {
3972 /* Failure to register second port need not be fatal */
1479d13c 3973 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1 3974 hw->dev[1] = NULL;
f1914226
MM		 3975 hw->ports = 1;
3976 if (dev1)
3977 free_netdev(dev1);
baef58b1
SH		 3978 }
3979 }
ccdaa2a9 3980 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3981
3982 return 0;
3983
ccdaa2a9
SH		 3984err_out_unregister:
3985 unregister_netdev(dev);
baef58b1
SH		 3986err_out_free_netdev:
3987 free_netdev(dev);
3988err_out_led_off:
3989 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3990err_out_iounmap:
3991 iounmap(hw->regs);
3992err_out_free_hw:
3993 kfree(hw);
3994err_out_free_regions:
3995 pci_release_regions(pdev);
3996err_out_disable_pdev:
3997 pci_disable_device(pdev);
3998 pci_set_drvdata(pdev, NULL);
3999err_out:
4000 return err;
4001}
4002
4003static void __devexit skge_remove(struct pci_dev *pdev)
4004{
4005 struct skge_hw *hw = pci_get_drvdata(pdev);
4006 struct net_device *dev0, *dev1;
4007
95566065 4008 if (!hw)
baef58b1
SH		 4009 return;
4010
208491d8
SH		 4011 flush_scheduled_work();
4012
67777f9b
JP		 4013 dev1 = hw->dev[1];
4014 if (dev1)
baef58b1
SH		 4015 unregister_netdev(dev1);
4016 dev0 = hw->dev[0];
4017 unregister_netdev(dev0);
4018
9cbe330f
SH		 4019 tasklet_disable(&hw->phy_task);
4020
7c442fa1
SH		 4021 spin_lock_irq(&hw->hw_lock);
4022 hw->intr_mask = 0;
46a60f2d 4023 skge_write32(hw, B0_IMSK, 0);
78bc2186 4024 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 4025 spin_unlock_irq(&hw->hw_lock);
4026
46a60f2d 4027 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 4028 skge_write8(hw, B0_CTST, CS_RST_SET);
4029
baef58b1
SH		 4030 free_irq(pdev->irq, hw);
4031 pci_release_regions(pdev);
4032 pci_disable_device(pdev);
4033 if (dev1)
4034 free_netdev(dev1);
4035 free_netdev(dev0);
46a60f2d 4036
baef58b1
SH		 4037 iounmap(hw->regs);
4038 kfree(hw);
4039 pci_set_drvdata(pdev, NULL);
4040}
4041
4042#ifdef CONFIG_PM
2a569579 4043static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 4044{
4045 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 4046 int i, err, wol = 0;
4047
e3b7df17
SH		 4048 if (!hw)
4049 return 0;
4050
a504e64a
SH		 4051 err = pci_save_state(pdev);
4052 if (err)
4053 return err;
baef58b1 4054
d38efdd6 4055 for (i = 0; i < hw->ports; i++) {
baef58b1 4056 struct net_device *dev = hw->dev[i];
a504e64a 4057 struct skge_port *skge = netdev_priv(dev);
baef58b1 4058
a504e64a
SH		 4059 if (netif_running(dev))
4060 skge_down(dev);
4061 if (skge->wol)
4062 skge_wol_init(skge);
d38efdd6 4063
a504e64a 4064 wol |= skge->wol;
baef58b1
SH		 4065 }
4066
d38efdd6 4067 skge_write32(hw, B0_IMSK, 0);
5177b324
RW		 4068
4069 pci_prepare_to_sleep(pdev);
baef58b1
SH		 4070
4071 return 0;
4072}
4073
4074static int skge_resume(struct pci_dev *pdev)
4075{
4076 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 4077 int i, err;
baef58b1 4078
e3b7df17
SH		 4079 if (!hw)
4080 return 0;
4081
5177b324 4082 err = pci_back_from_sleep(pdev);
a504e64a
SH		 4083 if (err)
4084 goto out;
4085
4086 err = pci_restore_state(pdev);
4087 if (err)
4088 goto out;
4089
d38efdd6
SH		 4090 err = skge_reset(hw);
4091 if (err)
4092 goto out;
baef58b1 4093
d38efdd6 4094 for (i = 0; i < hw->ports; i++) {
baef58b1 4095 struct net_device *dev = hw->dev[i];
d38efdd6 4096
d38efdd6
SH		 4097 if (netif_running(dev)) {
4098 err = skge_up(dev);
4099
4100 if (err) {
f15063cd 4101 netdev_err(dev, "could not up: %d\n", err);
edd702e8 4102 dev_close(dev);
d38efdd6
SH		 4103 goto out;
4104 }
baef58b1
SH		 4105 }
4106 }
d38efdd6
SH		 4107out:
4108 return err;
baef58b1
SH		 4109}
4110#endif
4111
692412b3
SH		 4112static void skge_shutdown(struct pci_dev *pdev)
4113{
4114 struct skge_hw *hw = pci_get_drvdata(pdev);
4115 int i, wol = 0;
4116
e3b7df17
SH		 4117 if (!hw)
4118 return;
4119
692412b3
SH		 4120 for (i = 0; i < hw->ports; i++) {
4121 struct net_device *dev = hw->dev[i];
4122 struct skge_port *skge = netdev_priv(dev);
4123
4124 if (skge->wol)
4125 skge_wol_init(skge);
4126 wol |= skge->wol;
4127 }
4128
5177b324
RW		 4129 if (pci_enable_wake(pdev, PCI_D3cold, wol))
4130 pci_enable_wake(pdev, PCI_D3hot, wol);
692412b3
SH		 4131
4132 pci_disable_device(pdev);
4133 pci_set_power_state(pdev, PCI_D3hot);
4134
4135}
4136
baef58b1
SH		 4137static struct pci_driver skge_driver = {
4138 .name = DRV_NAME,
4139 .id_table = skge_id_table,
4140 .probe = skge_probe,
4141 .remove = __devexit_p(skge_remove),
4142#ifdef CONFIG_PM
4143 .suspend = skge_suspend,
4144 .resume = skge_resume,
4145#endif
692412b3 4146 .shutdown = skge_shutdown,
baef58b1
SH		 4147};
4148
4149static int __init skge_init_module(void)
4150{
678aa1f6 4151 skge_debug_init();
29917620 4152 return pci_register_driver(&skge_driver);
baef58b1
SH		 4153}
4154
4155static void __exit skge_cleanup_module(void)
4156{
4157 pci_unregister_driver(&skge_driver);
678aa1f6 4158 skge_debug_cleanup();
baef58b1
SH		 4159}
4160
4161module_init(skge_init_module);
4162module_exit(skge_cleanup_module);
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