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890e8d0a
FR		 1/*
2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
3
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
7
40292fb0
FR		 8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
9 genuine driver.
890e8d0a
FR		 10
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
17
18 See the file COPYING in this distribution for more information.
19
20 */
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/netdevice.h>
43afb949 25#include <linux/rtnetlink.h>
890e8d0a
FR		 26#include <linux/etherdevice.h>
27#include <linux/ethtool.h>
28#include <linux/pci.h>
29#include <linux/mii.h>
30#include <linux/delay.h>
31#include <linux/crc32.h>
32#include <linux/dma-mapping.h>
33#include <asm/irq.h>
34
35#define net_drv(p, arg...) if (netif_msg_drv(p)) \
36 printk(arg)
37#define net_probe(p, arg...) if (netif_msg_probe(p)) \
38 printk(arg)
39#define net_link(p, arg...) if (netif_msg_link(p)) \
40 printk(arg)
41#define net_intr(p, arg...) if (netif_msg_intr(p)) \
42 printk(arg)
43#define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
44 printk(arg)
45
fcb9821d
FR		 46#define PHY_MAX_ADDR 32
47#define PHY_ID_ANY 0x1f
48#define MII_REG_ANY 0x1f
49
bea3348e 50#define DRV_VERSION "1.2"
890e8d0a
FR		 51#define DRV_NAME "sis190"
52#define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
53#define PFX DRV_NAME ": "
54
890e8d0a
FR		 55#define sis190_rx_skb netif_rx
56#define sis190_rx_quota(count, quota) count
890e8d0a
FR		 57
58#define MAC_ADDR_LEN 6
59
bcad5e53
FR		 60#define NUM_TX_DESC 64 /* [8..1024] */
61#define NUM_RX_DESC 64 /* [8..8192] */
890e8d0a
FR		 62#define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
63#define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
64#define RX_BUF_SIZE 1536
8b5641d4 65#define RX_BUF_MASK 0xfff8
890e8d0a
FR		 66
67#define SIS190_REGS_SIZE 0x80
68#define SIS190_TX_TIMEOUT (6*HZ)
69#define SIS190_PHY_TIMEOUT (10*HZ)
70#define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
71 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
72 NETIF_MSG_IFDOWN)
73
74/* Enhanced PHY access register bit definitions */
75#define EhnMIIread 0x0000
76#define EhnMIIwrite 0x0020
77#define EhnMIIdataShift 16
78#define EhnMIIpmdShift 6 /* 7016 only */
79#define EhnMIIregShift 11
80#define EhnMIIreq 0x0010
81#define EhnMIInotDone 0x0010
82
83/* Write/read MMIO register */
84#define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
85#define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
86#define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
87#define SIS_R8(reg) readb (ioaddr + (reg))
88#define SIS_R16(reg) readw (ioaddr + (reg))
89#define SIS_R32(reg) readl (ioaddr + (reg))
90
91#define SIS_PCI_COMMIT() SIS_R32(IntrControl)
92
93enum sis190_registers {
94 TxControl = 0x00,
95 TxDescStartAddr = 0x04,
188f23ba
FR		 96 rsv0 = 0x08, // reserved
97 TxSts = 0x0c, // unused (Control/Status)
890e8d0a
FR		 98 RxControl = 0x10,
99 RxDescStartAddr = 0x14,
188f23ba
FR		 100 rsv1 = 0x18, // reserved
101 RxSts = 0x1c, // unused
890e8d0a
FR		 102 IntrStatus = 0x20,
103 IntrMask = 0x24,
104 IntrControl = 0x28,
188f23ba
FR		 105 IntrTimer = 0x2c, // unused (Interupt Timer)
106 PMControl = 0x30, // unused (Power Mgmt Control/Status)
107 rsv2 = 0x34, // reserved
890e8d0a
FR		 108 ROMControl = 0x38,
109 ROMInterface = 0x3c,
110 StationControl = 0x40,
111 GMIIControl = 0x44,
188f23ba
FR		 112 GIoCR = 0x48, // unused (GMAC IO Compensation)
113 GIoCtrl = 0x4c, // unused (GMAC IO Control)
890e8d0a 114 TxMacControl = 0x50,
188f23ba
FR		 115 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
116 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
117 rsv3 = 0x5c, // reserved
890e8d0a
FR		 118 RxMacControl = 0x60,
119 RxMacAddr = 0x62,
120 RxHashTable = 0x68,
121 // Undocumented = 0x6c,
188f23ba
FR		 122 RxWolCtrl = 0x70,
123 RxWolData = 0x74, // unused (Rx WOL Data Access)
124 RxMPSControl = 0x78, // unused (Rx MPS Control)
125 rsv4 = 0x7c, // reserved
890e8d0a
FR		 126};
127
128enum sis190_register_content {
129 /* IntrStatus */
130 SoftInt = 0x40000000, // unused
131 Timeup = 0x20000000, // unused
132 PauseFrame = 0x00080000, // unused
133 MagicPacket = 0x00040000, // unused
134 WakeupFrame = 0x00020000, // unused
135 LinkChange = 0x00010000,
136 RxQEmpty = 0x00000080,
137 RxQInt = 0x00000040,
138 TxQ1Empty = 0x00000020, // unused
139 TxQ1Int = 0x00000010,
140 TxQ0Empty = 0x00000008, // unused
141 TxQ0Int = 0x00000004,
142 RxHalt = 0x00000002,
143 TxHalt = 0x00000001,
144
890e8d0a
FR		 145 /* {Rx/Tx}CmdBits */
146 CmdReset = 0x10,
147 CmdRxEnb = 0x08, // unused
148 CmdTxEnb = 0x01,
149 RxBufEmpty = 0x01, // unused
150
151 /* Cfg9346Bits */
152 Cfg9346_Lock = 0x00, // unused
153 Cfg9346_Unlock = 0xc0, // unused
154
155 /* RxMacControl */
156 AcceptErr = 0x20, // unused
157 AcceptRunt = 0x10, // unused
158 AcceptBroadcast = 0x0800,
159 AcceptMulticast = 0x0400,
160 AcceptMyPhys = 0x0200,
161 AcceptAllPhys = 0x0100,
162
163 /* RxConfigBits */
164 RxCfgFIFOShift = 13,
165 RxCfgDMAShift = 8, // 0x1a in RxControl ?
166
167 /* TxConfigBits */
168 TxInterFrameGapShift = 24,
169 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
170
890e8d0a
FR		 171 LinkStatus = 0x02, // unused
172 FullDup = 0x01, // unused
173
174 /* TBICSRBit */
175 TBILinkOK = 0x02000000, // unused
176};
177
178struct TxDesc {
3cec93c7
FR		 179 __le32 PSize;
180 __le32 status;
181 __le32 addr;
182 __le32 size;
890e8d0a
FR		 183};
184
185struct RxDesc {
3cec93c7
FR		 186 __le32 PSize;
187 __le32 status;
188 __le32 addr;
189 __le32 size;
890e8d0a
FR		 190};
191
192enum _DescStatusBit {
193 /* _Desc.status */
bcad5e53
FR		 194 OWNbit = 0x80000000, // RXOWN/TXOWN
195 INTbit = 0x40000000, // RXINT/TXINT
196 CRCbit = 0x00020000, // CRCOFF/CRCEN
197 PADbit = 0x00010000, // PREADD/PADEN
890e8d0a 198 /* _Desc.size */
bcad5e53
FR		 199 RingEnd = 0x80000000,
200 /* TxDesc.status */
201 LSEN = 0x08000000, // TSO ? -- FR
202 IPCS = 0x04000000,
203 TCPCS = 0x02000000,
204 UDPCS = 0x01000000,
205 BSTEN = 0x00800000,
206 EXTEN = 0x00400000,
207 DEFEN = 0x00200000,
208 BKFEN = 0x00100000,
209 CRSEN = 0x00080000,
210 COLEN = 0x00040000,
211 THOL3 = 0x30000000,
212 THOL2 = 0x20000000,
213 THOL1 = 0x10000000,
214 THOL0 = 0x00000000,
697c2696
FR		 215
216 WND = 0x00080000,
217 TABRT = 0x00040000,
218 FIFO = 0x00020000,
219 LINK = 0x00010000,
220 ColCountMask = 0x0000ffff,
bcad5e53
FR		 221 /* RxDesc.status */
222 IPON = 0x20000000,
223 TCPON = 0x10000000,
224 UDPON = 0x08000000,
225 Wakup = 0x00400000,
226 Magic = 0x00200000,
227 Pause = 0x00100000,
228 DEFbit = 0x00200000,
229 BCAST = 0x000c0000,
230 MCAST = 0x00080000,
231 UCAST = 0x00040000,
232 /* RxDesc.PSize */
233 TAGON = 0x80000000,
234 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
235 ABORT = 0x00800000,
236 SHORT = 0x00400000,
237 LIMIT = 0x00200000,
238 MIIER = 0x00100000,
239 OVRUN = 0x00080000,
240 NIBON = 0x00040000,
241 COLON = 0x00020000,
242 CRCOK = 0x00010000,
890e8d0a 243 RxSizeMask = 0x0000ffff
bcad5e53
FR		 244 /*
245 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
246 * provide two (unused with Linux) Tx queues. No publically
247 * available documentation alas.
248 */
890e8d0a
FR		 249};
250
40292fb0
FR		 251enum sis190_eeprom_access_register_bits {
252 EECS = 0x00000001, // unused
253 EECLK = 0x00000002, // unused
254 EEDO = 0x00000008, // unused
255 EEDI = 0x00000004, // unused
256 EEREQ = 0x00000080,
257 EEROP = 0x00000200,
258 EEWOP = 0x00000100 // unused
259};
260
830fb7d2
FR		 261/* EEPROM Addresses */
262enum sis190_eeprom_address {
263 EEPROMSignature = 0x00,
264 EEPROMCLK = 0x01, // unused
265 EEPROMInfo = 0x02,
266 EEPROMMACAddr = 0x03
267};
268
900eb9d6
FR		 269enum sis190_feature {
270 F_HAS_RGMII = 1,
c3d6f1f2
FR		 271 F_PHY_88E1111 = 2,
272 F_PHY_BCM5461 = 4
900eb9d6
FR		 273};
274
890e8d0a
FR		 275struct sis190_private {
276 void __iomem *mmio_addr;
277 struct pci_dev *pci_dev;
c4028958 278 struct net_device *dev;
890e8d0a
FR		 279 spinlock_t lock;
280 u32 rx_buf_sz;
281 u32 cur_rx;
282 u32 cur_tx;
283 u32 dirty_rx;
284 u32 dirty_tx;
285 dma_addr_t rx_dma;
286 dma_addr_t tx_dma;
287 struct RxDesc *RxDescRing;
288 struct TxDesc *TxDescRing;
289 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
290 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
291 struct work_struct phy_task;
292 struct timer_list timer;
293 u32 msg_enable;
43afb949 294 struct mii_if_info mii_if;
fcb9821d 295 struct list_head first_phy;
900eb9d6 296 u32 features;
fcb9821d
FR		 297};
298
299struct sis190_phy {
300 struct list_head list;
301 int phy_id;
302 u16 id[2];
303 u16 status;
304 u8 type;
305};
306
307enum sis190_phy_type {
308 UNKNOWN = 0x00,
309 HOME = 0x01,
310 LAN = 0x02,
311 MIX = 0x03
312};
313
314static struct mii_chip_info {
315 const char *name;
316 u16 id[2];
317 unsigned int type;
900eb9d6 318 u32 feature;
fcb9821d 319} mii_chip_table[] = {
708f6e27 320 { "Atheros PHY AR8012", { 0x004d, 0xd020 }, LAN, 0 },
c3d6f1f2 321 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
bd7a4448 322 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
900eb9d6
FR		 323 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
324 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
325 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
fcb9821d 326 { NULL, }
890e8d0a
FR		 327};
328
3c6bee1d 329static const struct {
890e8d0a 330 const char *name;
890e8d0a 331} sis_chip_info[] = {
e797637f
FR		 332 { "SiS 190 PCI Fast Ethernet adapter" },
333 { "SiS 191 PCI Gigabit Ethernet adapter" },
890e8d0a
FR		 334};
335
8ee8e922 336static struct pci_device_id sis190_pci_tbl[] = {
890e8d0a 337 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
e797637f 338 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
890e8d0a
FR		 339 { 0, },
340};
341
342MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
343
344static int rx_copybreak = 200;
345
346static struct {
347 u32 msg_enable;
348} debug = { -1 };
349
350MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
351module_param(rx_copybreak, int, 0);
352MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
353module_param_named(debug, debug.msg_enable, int, 0);
354MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
355MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
356MODULE_VERSION(DRV_VERSION);
357MODULE_LICENSE("GPL");
358
359static const u32 sis190_intr_mask =
21461380 360 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
890e8d0a
FR		 361
362/*
363 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
364 * The chips use a 64 element hash table based on the Ethernet CRC.
365 */
f71e1309 366static const int multicast_filter_limit = 32;
890e8d0a
FR		 367
368static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
369{
370 unsigned int i;
371
372 SIS_W32(GMIIControl, ctl);
373
374 msleep(1);
375
376 for (i = 0; i < 100; i++) {
377 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
378 break;
379 msleep(1);
380 }
381
7bf3f232 382 if (i > 99)
890e8d0a
FR		 383 printk(KERN_ERR PFX "PHY command failed !\n");
384}
385
9ede109b 386static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
890e8d0a 387{
890e8d0a 388 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
9ede109b 389 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
890e8d0a
FR		 390 (((u32) val) << EhnMIIdataShift));
391}
392
9ede109b 393static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
890e8d0a 394{
890e8d0a 395 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
9ede109b 396 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
890e8d0a
FR		 397
398 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
399}
400
43afb949
FR		 401static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
402{
403 struct sis190_private *tp = netdev_priv(dev);
404
9ede109b 405 mdio_write(tp->mmio_addr, phy_id, reg, val);
43afb949
FR		 406}
407
408static int __mdio_read(struct net_device *dev, int phy_id, int reg)
409{
410 struct sis190_private *tp = netdev_priv(dev);
411
9ede109b 412 return mdio_read(tp->mmio_addr, phy_id, reg);
43afb949
FR		 413}
414
fc10c39d
FR		 415static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
416{
417 mdio_read(ioaddr, phy_id, reg);
418 return mdio_read(ioaddr, phy_id, reg);
419}
420
40292fb0 421static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
890e8d0a 422{
40292fb0 423 u16 data = 0xffff;
890e8d0a 424 unsigned int i;
890e8d0a
FR		 425
426 if (!(SIS_R32(ROMControl) & 0x0002))
427 return 0;
428
40292fb0 429 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
890e8d0a
FR		 430
431 for (i = 0; i < 200; i++) {
40292fb0
FR		 432 if (!(SIS_R32(ROMInterface) & EEREQ)) {
433 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
890e8d0a 434 break;
40292fb0 435 }
890e8d0a
FR		 436 msleep(1);
437 }
438
890e8d0a
FR		 439 return data;
440}
441
442static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
443{
444 SIS_W32(IntrMask, 0x00);
445 SIS_W32(IntrStatus, 0xffffffff);
446 SIS_PCI_COMMIT();
447}
448
449static void sis190_asic_down(void __iomem *ioaddr)
450{
451 /* Stop the chip's Tx and Rx DMA processes. */
452
453 SIS_W32(TxControl, 0x1a00);
454 SIS_W32(RxControl, 0x1a00);
455
456 sis190_irq_mask_and_ack(ioaddr);
457}
458
459static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
460{
461 desc->size |= cpu_to_le32(RingEnd);
462}
463
464static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
465{
466 u32 eor = le32_to_cpu(desc->size) & RingEnd;
467
468 desc->PSize = 0x0;
8b5641d4 469 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
890e8d0a
FR		 470 wmb();
471 desc->status = cpu_to_le32(OWNbit | INTbit);
472}
473
474static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
475 u32 rx_buf_sz)
476{
477 desc->addr = cpu_to_le32(mapping);
478 sis190_give_to_asic(desc, rx_buf_sz);
479}
480
481static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
482{
483 desc->PSize = 0x0;
961994a0 484 desc->addr = cpu_to_le32(0xdeadbeef);
890e8d0a
FR		 485 desc->size &= cpu_to_le32(RingEnd);
486 wmb();
487 desc->status = 0x0;
488}
489
35aeb780
SH		 490static struct sk_buff *sis190_alloc_rx_skb(struct sis190_private *tp,
491 struct RxDesc *desc)
890e8d0a 492{
35aeb780 493 u32 rx_buf_sz = tp->rx_buf_sz;
890e8d0a 494 struct sk_buff *skb;
890e8d0a 495
35aeb780 496 skb = netdev_alloc_skb(tp->dev, rx_buf_sz);
4709aa59
SH		 497 if (likely(skb)) {
498 dma_addr_t mapping;
890e8d0a 499
35aeb780 500 mapping = pci_map_single(tp->pci_dev, skb->data, tp->rx_buf_sz,
4709aa59
SH		 501 PCI_DMA_FROMDEVICE);
502 sis190_map_to_asic(desc, mapping, rx_buf_sz);
503 } else
504 sis190_make_unusable_by_asic(desc);
890e8d0a 505
4709aa59 506 return skb;
890e8d0a
FR		 507}
508
509static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
510 u32 start, u32 end)
511{
512 u32 cur;
513
514 for (cur = start; cur < end; cur++) {
4709aa59 515 unsigned int i = cur % NUM_RX_DESC;
890e8d0a
FR		 516
517 if (tp->Rx_skbuff[i])
518 continue;
519
35aeb780
SH		 520 tp->Rx_skbuff[i] = sis190_alloc_rx_skb(tp, tp->RxDescRing + i);
521
4709aa59 522 if (!tp->Rx_skbuff[i])
890e8d0a
FR		 523 break;
524 }
525 return cur - start;
526}
527
47e47815
FR		 528static bool sis190_try_rx_copy(struct sis190_private *tp,
529 struct sk_buff **sk_buff, int pkt_size,
530 dma_addr_t addr)
890e8d0a 531{
47e47815
FR		 532 struct sk_buff *skb;
533 bool done = false;
534
535 if (pkt_size >= rx_copybreak)
536 goto out;
537
538 skb = netdev_alloc_skb(tp->dev, pkt_size + 2);
539 if (!skb)
540 goto out;
541
542 pci_dma_sync_single_for_device(tp->pci_dev, addr, pkt_size,
543 PCI_DMA_FROMDEVICE);
544 skb_reserve(skb, 2);
545 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
546 *sk_buff = skb;
547 done = true;
548out:
549 return done;
890e8d0a
FR		 550}
551
bcad5e53
FR		 552static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
553{
554#define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
555
556 if ((status & CRCOK) && !(status & ErrMask))
557 return 0;
558
559 if (!(status & CRCOK))
560 stats->rx_crc_errors++;
561 else if (status & OVRUN)
562 stats->rx_over_errors++;
563 else if (status & (SHORT | LIMIT))
564 stats->rx_length_errors++;
565 else if (status & (MIIER | NIBON | COLON))
566 stats->rx_frame_errors++;
567
568 stats->rx_errors++;
569 return -1;
570}
571
890e8d0a
FR		 572static int sis190_rx_interrupt(struct net_device *dev,
573 struct sis190_private *tp, void __iomem *ioaddr)
574{
09f75cd7 575 struct net_device_stats *stats = &dev->stats;
890e8d0a
FR		 576 u32 rx_left, cur_rx = tp->cur_rx;
577 u32 delta, count;
578
579 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
580 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
581
582 for (; rx_left > 0; rx_left--, cur_rx++) {
583 unsigned int entry = cur_rx % NUM_RX_DESC;
584 struct RxDesc *desc = tp->RxDescRing + entry;
585 u32 status;
586
961994a0 587 if (le32_to_cpu(desc->status) & OWNbit)
890e8d0a
FR		 588 break;
589
590 status = le32_to_cpu(desc->PSize);
591
592 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
593 // status);
594
bcad5e53 595 if (sis190_rx_pkt_err(status, stats) < 0)
890e8d0a 596 sis190_give_to_asic(desc, tp->rx_buf_sz);
bcad5e53 597 else {
890e8d0a 598 struct sk_buff *skb = tp->Rx_skbuff[entry];
47e47815 599 dma_addr_t addr = le32_to_cpu(desc->addr);
890e8d0a 600 int pkt_size = (status & RxSizeMask) - 4;
47e47815 601 struct pci_dev *pdev = tp->pci_dev;
890e8d0a
FR		 602
603 if (unlikely(pkt_size > tp->rx_buf_sz)) {
604 net_intr(tp, KERN_INFO
605 "%s: (frag) status = %08x.\n",
606 dev->name, status);
607 stats->rx_dropped++;
608 stats->rx_length_errors++;
609 sis190_give_to_asic(desc, tp->rx_buf_sz);
610 continue;
611 }
612
890e8d0a 613
47e47815
FR		 614 if (sis190_try_rx_copy(tp, &skb, pkt_size, addr)) {
615 pci_dma_sync_single_for_device(pdev, addr,
616 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
617 sis190_give_to_asic(desc, tp->rx_buf_sz);
618 } else {
619 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
620 PCI_DMA_FROMDEVICE);
890e8d0a
FR		 621 tp->Rx_skbuff[entry] = NULL;
622 sis190_make_unusable_by_asic(desc);
623 }
624
890e8d0a
FR		 625 skb_put(skb, pkt_size);
626 skb->protocol = eth_type_trans(skb, dev);
627
628 sis190_rx_skb(skb);
629
890e8d0a 630 stats->rx_packets++;
bcad5e53
FR		 631 stats->rx_bytes += pkt_size;
632 if ((status & BCAST) == MCAST)
633 stats->multicast++;
890e8d0a
FR		 634 }
635 }
636 count = cur_rx - tp->cur_rx;
637 tp->cur_rx = cur_rx;
638
639 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
640 if (!delta && count && netif_msg_intr(tp))
641 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
642 tp->dirty_rx += delta;
643
644 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
645 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
646
647 return count;
648}
649
650static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
651 struct TxDesc *desc)
652{
653 unsigned int len;
654
655 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
656
657 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
658
659 memset(desc, 0x00, sizeof(*desc));
660}
661
697c2696
FR		 662static inline int sis190_tx_pkt_err(u32 status, struct net_device_stats *stats)
663{
664#define TxErrMask (WND | TABRT | FIFO | LINK)
665
666 if (!unlikely(status & TxErrMask))
667 return 0;
668
669 if (status & WND)
670 stats->tx_window_errors++;
671 if (status & TABRT)
672 stats->tx_aborted_errors++;
673 if (status & FIFO)
674 stats->tx_fifo_errors++;
675 if (status & LINK)
676 stats->tx_carrier_errors++;
677
678 stats->tx_errors++;
679
680 return -1;
681}
682
890e8d0a
FR		 683static void sis190_tx_interrupt(struct net_device *dev,
684 struct sis190_private *tp, void __iomem *ioaddr)
685{
697c2696 686 struct net_device_stats *stats = &dev->stats;
890e8d0a
FR		 687 u32 pending, dirty_tx = tp->dirty_tx;
688 /*
689 * It would not be needed if queueing was allowed to be enabled
690 * again too early (hint: think preempt and unclocked smp systems).
691 */
692 unsigned int queue_stopped;
693
694 smp_rmb();
695 pending = tp->cur_tx - dirty_tx;
696 queue_stopped = (pending == NUM_TX_DESC);
697
698 for (; pending; pending--, dirty_tx++) {
699 unsigned int entry = dirty_tx % NUM_TX_DESC;
700 struct TxDesc *txd = tp->TxDescRing + entry;
697c2696 701 u32 status = le32_to_cpu(txd->status);
890e8d0a
FR		 702 struct sk_buff *skb;
703
697c2696 704 if (status & OWNbit)
890e8d0a
FR		 705 break;
706
707 skb = tp->Tx_skbuff[entry];
708
697c2696
FR		 709 if (likely(sis190_tx_pkt_err(status, stats) == 0)) {
710 stats->tx_packets++;
711 stats->tx_bytes += skb->len;
712 stats->collisions += ((status & ColCountMask) - 1);
713 }
890e8d0a
FR		 714
715 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
716 tp->Tx_skbuff[entry] = NULL;
717 dev_kfree_skb_irq(skb);
718 }
719
720 if (tp->dirty_tx != dirty_tx) {
721 tp->dirty_tx = dirty_tx;
722 smp_wmb();
723 if (queue_stopped)
724 netif_wake_queue(dev);
725 }
726}
727
728/*
729 * The interrupt handler does all of the Rx thread work and cleans up after
730 * the Tx thread.
731 */
7d12e780 732static irqreturn_t sis190_interrupt(int irq, void *__dev)
890e8d0a
FR		 733{
734 struct net_device *dev = __dev;
735 struct sis190_private *tp = netdev_priv(dev);
736 void __iomem *ioaddr = tp->mmio_addr;
737 unsigned int handled = 0;
738 u32 status;
739
740 status = SIS_R32(IntrStatus);
741
742 if ((status == 0xffffffff) || !status)
743 goto out;
744
745 handled = 1;
746
747 if (unlikely(!netif_running(dev))) {
748 sis190_asic_down(ioaddr);
749 goto out;
750 }
751
752 SIS_W32(IntrStatus, status);
753
754 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
755
756 if (status & LinkChange) {
757 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
758 schedule_work(&tp->phy_task);
759 }
760
761 if (status & RxQInt)
762 sis190_rx_interrupt(dev, tp, ioaddr);
763
764 if (status & TxQ0Int)
765 sis190_tx_interrupt(dev, tp, ioaddr);
766out:
767 return IRQ_RETVAL(handled);
768}
769
4405d3b5
FR		 770#ifdef CONFIG_NET_POLL_CONTROLLER
771static void sis190_netpoll(struct net_device *dev)
772{
773 struct sis190_private *tp = netdev_priv(dev);
774 struct pci_dev *pdev = tp->pci_dev;
775
776 disable_irq(pdev->irq);
7d12e780 777 sis190_interrupt(pdev->irq, dev);
4405d3b5
FR		 778 enable_irq(pdev->irq);
779}
780#endif
781
890e8d0a
FR		 782static void sis190_free_rx_skb(struct sis190_private *tp,
783 struct sk_buff **sk_buff, struct RxDesc *desc)
784{
785 struct pci_dev *pdev = tp->pci_dev;
786
787 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
788 PCI_DMA_FROMDEVICE);
789 dev_kfree_skb(*sk_buff);
790 *sk_buff = NULL;
791 sis190_make_unusable_by_asic(desc);
792}
793
794static void sis190_rx_clear(struct sis190_private *tp)
795{
796 unsigned int i;
797
798 for (i = 0; i < NUM_RX_DESC; i++) {
799 if (!tp->Rx_skbuff[i])
800 continue;
801 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
802 }
803}
804
805static void sis190_init_ring_indexes(struct sis190_private *tp)
806{
807 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
808}
809
810static int sis190_init_ring(struct net_device *dev)
811{
812 struct sis190_private *tp = netdev_priv(dev);
813
814 sis190_init_ring_indexes(tp);
815
816 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
817 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
818
819 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
820 goto err_rx_clear;
821
822 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
823
824 return 0;
825
826err_rx_clear:
827 sis190_rx_clear(tp);
828 return -ENOMEM;
829}
830
831static void sis190_set_rx_mode(struct net_device *dev)
832{
833 struct sis190_private *tp = netdev_priv(dev);
834 void __iomem *ioaddr = tp->mmio_addr;
835 unsigned long flags;
836 u32 mc_filter[2]; /* Multicast hash filter */
837 u16 rx_mode;
838
839 if (dev->flags & IFF_PROMISC) {
890e8d0a
FR		 840 rx_mode =
841 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
842 AcceptAllPhys;
843 mc_filter[1] = mc_filter[0] = 0xffffffff;
844 } else if ((dev->mc_count > multicast_filter_limit) ||
845 (dev->flags & IFF_ALLMULTI)) {
846 /* Too many to filter perfectly -- accept all multicasts. */
847 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
848 mc_filter[1] = mc_filter[0] = 0xffffffff;
849 } else {
850 struct dev_mc_list *mclist;
851 unsigned int i;
852
853 rx_mode = AcceptBroadcast | AcceptMyPhys;
854 mc_filter[1] = mc_filter[0] = 0;
855 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
856 i++, mclist = mclist->next) {
857 int bit_nr =
8fee5f51 858 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
890e8d0a
FR		 859 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
860 rx_mode |= AcceptMulticast;
861 }
862 }
863
864 spin_lock_irqsave(&tp->lock, flags);
865
866 SIS_W16(RxMacControl, rx_mode | 0x2);
867 SIS_W32(RxHashTable, mc_filter[0]);
868 SIS_W32(RxHashTable + 4, mc_filter[1]);
869
870 spin_unlock_irqrestore(&tp->lock, flags);
871}
872
873static void sis190_soft_reset(void __iomem *ioaddr)
874{
875 SIS_W32(IntrControl, 0x8000);
876 SIS_PCI_COMMIT();
890e8d0a
FR		 877 SIS_W32(IntrControl, 0x0);
878 sis190_asic_down(ioaddr);
890e8d0a
FR		 879}
880
881static void sis190_hw_start(struct net_device *dev)
882{
883 struct sis190_private *tp = netdev_priv(dev);
884 void __iomem *ioaddr = tp->mmio_addr;
885
886 sis190_soft_reset(ioaddr);
887
888 SIS_W32(TxDescStartAddr, tp->tx_dma);
889 SIS_W32(RxDescStartAddr, tp->rx_dma);
890
891 SIS_W32(IntrStatus, 0xffffffff);
892 SIS_W32(IntrMask, 0x0);
890e8d0a
FR		 893 SIS_W32(GMIIControl, 0x0);
894 SIS_W32(TxMacControl, 0x60);
895 SIS_W16(RxMacControl, 0x02);
896 SIS_W32(RxHashTable, 0x0);
897 SIS_W32(0x6c, 0x0);
188f23ba
FR		 898 SIS_W32(RxWolCtrl, 0x0);
899 SIS_W32(RxWolData, 0x0);
890e8d0a
FR		 900
901 SIS_PCI_COMMIT();
902
903 sis190_set_rx_mode(dev);
904
905 /* Enable all known interrupts by setting the interrupt mask. */
906 SIS_W32(IntrMask, sis190_intr_mask);
907
908 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
909 SIS_W32(RxControl, 0x1a1d);
910
911 netif_start_queue(dev);
912}
913
c4028958 914static void sis190_phy_task(struct work_struct *work)
890e8d0a 915{
c4028958
DH		 916 struct sis190_private *tp =
917 container_of(work, struct sis190_private, phy_task);
918 struct net_device *dev = tp->dev;
890e8d0a 919 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 920 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 921 u16 val;
922
43afb949
FR		 923 rtnl_lock();
924
c014f6c8
FR		 925 if (!netif_running(dev))
926 goto out_unlock;
927
9ede109b 928 val = mdio_read(ioaddr, phy_id, MII_BMCR);
890e8d0a
FR		 929 if (val & BMCR_RESET) {
930 // FIXME: needlessly high ? -- FR 02/07/2005
931 mod_timer(&tp->timer, jiffies + HZ/10);
fc10c39d
FR		 932 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
933 BMSR_ANEGCOMPLETE)) {
21461380 934 netif_carrier_off(dev);
c34ebbae
FR		 935 net_link(tp, KERN_WARNING "%s: auto-negotiating...\n",
936 dev->name);
890e8d0a
FR		 937 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
938 } else {
939 /* Rejoice ! */
940 struct {
941 int val;
6614a6dc 942 u32 ctl;
890e8d0a 943 const char *msg;
890e8d0a 944 } reg31[] = {
6614a6dc
FR		 945 { LPA_1000XFULL | LPA_SLCT, 0x07000c00 | 0x00001000,
946 "1000 Mbps Full Duplex" },
947 { LPA_1000XHALF | LPA_SLCT, 0x07000c00,
948 "1000 Mbps Half Duplex" },
949 { LPA_100FULL, 0x04000800 | 0x00001000,
950 "100 Mbps Full Duplex" },
951 { LPA_100HALF, 0x04000800,
952 "100 Mbps Half Duplex" },
953 { LPA_10FULL, 0x04000400 | 0x00001000,
954 "10 Mbps Full Duplex" },
955 { LPA_10HALF, 0x04000400,
956 "10 Mbps Half Duplex" },
957 { 0, 0x04000400, "unknown" }
958 }, *p;
8348b4db 959 u16 adv;
890e8d0a 960
9ede109b 961 val = mdio_read(ioaddr, phy_id, 0x1f);
890e8d0a
FR		 962 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
963
9ede109b 964 val = mdio_read(ioaddr, phy_id, MII_LPA);
8348b4db
FR		 965 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
966 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
967 dev->name, val, adv);
968
969 val &= adv;
890e8d0a 970
6614a6dc 971 for (p = reg31; p->val; p++) {
890e8d0a
FR		 972 if ((val & p->val) == p->val)
973 break;
974 }
6614a6dc
FR		 975
976 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
977
c3d6f1f2
FR		 978 if ((tp->features & F_HAS_RGMII) &&
979 (tp->features & F_PHY_BCM5461)) {
980 // Set Tx Delay in RGMII mode.
981 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
982 udelay(200);
983 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
984 p->ctl |= 0x03000000;
985 }
986
6614a6dc
FR		 987 SIS_W32(StationControl, p->ctl);
988
c3d6f1f2
FR		 989 if (tp->features & F_HAS_RGMII) {
990 SIS_W32(RGDelay, 0x0441);
991 SIS_W32(RGDelay, 0x0440);
992 }
993
890e8d0a
FR		 994 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
995 p->msg);
996 netif_carrier_on(dev);
997 }
43afb949 998
c014f6c8 999out_unlock:
43afb949 1000 rtnl_unlock();
890e8d0a
FR		 1001}
1002
1003static void sis190_phy_timer(unsigned long __opaque)
1004{
1005 struct net_device *dev = (struct net_device *)__opaque;
1006 struct sis190_private *tp = netdev_priv(dev);
1007
1008 if (likely(netif_running(dev)))
1009 schedule_work(&tp->phy_task);
1010}
1011
1012static inline void sis190_delete_timer(struct net_device *dev)
1013{
1014 struct sis190_private *tp = netdev_priv(dev);
1015
1016 del_timer_sync(&tp->timer);
1017}
1018
1019static inline void sis190_request_timer(struct net_device *dev)
1020{
1021 struct sis190_private *tp = netdev_priv(dev);
1022 struct timer_list *timer = &tp->timer;
1023
1024 init_timer(timer);
1025 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1026 timer->data = (unsigned long)dev;
1027 timer->function = sis190_phy_timer;
1028 add_timer(timer);
1029}
1030
1031static void sis190_set_rxbufsize(struct sis190_private *tp,
1032 struct net_device *dev)
1033{
1034 unsigned int mtu = dev->mtu;
1035
1036 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
8b5641d4
FR		 1037 /* RxDesc->size has a licence to kill the lower bits */
1038 if (tp->rx_buf_sz & 0x07) {
1039 tp->rx_buf_sz += 8;
1040 tp->rx_buf_sz &= RX_BUF_MASK;
1041 }
890e8d0a
FR		 1042}
1043
1044static int sis190_open(struct net_device *dev)
1045{
1046 struct sis190_private *tp = netdev_priv(dev);
1047 struct pci_dev *pdev = tp->pci_dev;
1048 int rc = -ENOMEM;
1049
1050 sis190_set_rxbufsize(tp, dev);
1051
1052 /*
1053 * Rx and Tx descriptors need 256 bytes alignment.
1054 * pci_alloc_consistent() guarantees a stronger alignment.
1055 */
1056 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1057 if (!tp->TxDescRing)
1058 goto out;
1059
1060 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1061 if (!tp->RxDescRing)
1062 goto err_free_tx_0;
1063
1064 rc = sis190_init_ring(dev);
1065 if (rc < 0)
1066 goto err_free_rx_1;
1067
890e8d0a
FR		 1068 sis190_request_timer(dev);
1069
1fb9df5d 1070 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
890e8d0a
FR		 1071 if (rc < 0)
1072 goto err_release_timer_2;
1073
1074 sis190_hw_start(dev);
1075out:
1076 return rc;
1077
1078err_release_timer_2:
1079 sis190_delete_timer(dev);
1080 sis190_rx_clear(tp);
1081err_free_rx_1:
1082 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1083 tp->rx_dma);
1084err_free_tx_0:
1085 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1086 tp->tx_dma);
1087 goto out;
1088}
1089
1090static void sis190_tx_clear(struct sis190_private *tp)
1091{
1092 unsigned int i;
1093
1094 for (i = 0; i < NUM_TX_DESC; i++) {
1095 struct sk_buff *skb = tp->Tx_skbuff[i];
1096
1097 if (!skb)
1098 continue;
1099
1100 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1101 tp->Tx_skbuff[i] = NULL;
1102 dev_kfree_skb(skb);
1103
09f75cd7 1104 tp->dev->stats.tx_dropped++;
890e8d0a
FR		 1105 }
1106 tp->cur_tx = tp->dirty_tx = 0;
1107}
1108
1109static void sis190_down(struct net_device *dev)
1110{
1111 struct sis190_private *tp = netdev_priv(dev);
1112 void __iomem *ioaddr = tp->mmio_addr;
1113 unsigned int poll_locked = 0;
1114
1115 sis190_delete_timer(dev);
1116
1117 netif_stop_queue(dev);
1118
890e8d0a
FR		 1119 do {
1120 spin_lock_irq(&tp->lock);
1121
1122 sis190_asic_down(ioaddr);
1123
1124 spin_unlock_irq(&tp->lock);
1125
1126 synchronize_irq(dev->irq);
1127
bea3348e 1128 if (!poll_locked)
890e8d0a 1129 poll_locked++;
890e8d0a
FR		 1130
1131 synchronize_sched();
1132
1133 } while (SIS_R32(IntrMask));
1134
1135 sis190_tx_clear(tp);
1136 sis190_rx_clear(tp);
1137}
1138
1139static int sis190_close(struct net_device *dev)
1140{
1141 struct sis190_private *tp = netdev_priv(dev);
1142 struct pci_dev *pdev = tp->pci_dev;
1143
1144 sis190_down(dev);
1145
1146 free_irq(dev->irq, dev);
1147
890e8d0a
FR		 1148 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1149 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1150
1151 tp->TxDescRing = NULL;
1152 tp->RxDescRing = NULL;
1153
1154 return 0;
1155}
1156
1157static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1158{
1159 struct sis190_private *tp = netdev_priv(dev);
1160 void __iomem *ioaddr = tp->mmio_addr;
1161 u32 len, entry, dirty_tx;
1162 struct TxDesc *desc;
1163 dma_addr_t mapping;
1164
1165 if (unlikely(skb->len < ETH_ZLEN)) {
5b057c6b 1166 if (skb_padto(skb, ETH_ZLEN)) {
09f75cd7 1167 dev->stats.tx_dropped++;
890e8d0a
FR		 1168 goto out;
1169 }
1170 len = ETH_ZLEN;
1171 } else {
1172 len = skb->len;
1173 }
1174
1175 entry = tp->cur_tx % NUM_TX_DESC;
1176 desc = tp->TxDescRing + entry;
1177
1178 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1179 netif_stop_queue(dev);
1180 net_tx_err(tp, KERN_ERR PFX
1181 "%s: BUG! Tx Ring full when queue awake!\n",
1182 dev->name);
1183 return NETDEV_TX_BUSY;
1184 }
1185
1186 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1187
1188 tp->Tx_skbuff[entry] = skb;
1189
1190 desc->PSize = cpu_to_le32(len);
1191 desc->addr = cpu_to_le32(mapping);
1192
1193 desc->size = cpu_to_le32(len);
1194 if (entry == (NUM_TX_DESC - 1))
1195 desc->size |= cpu_to_le32(RingEnd);
1196
1197 wmb();
1198
1199 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1200
1201 tp->cur_tx++;
1202
1203 smp_wmb();
1204
1205 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1206
890e8d0a
FR		 1207 dirty_tx = tp->dirty_tx;
1208 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1209 netif_stop_queue(dev);
1210 smp_rmb();
1211 if (dirty_tx != tp->dirty_tx)
1212 netif_wake_queue(dev);
1213 }
1214out:
1215 return NETDEV_TX_OK;
1216}
1217
fcb9821d
FR		 1218static void sis190_free_phy(struct list_head *first_phy)
1219{
1220 struct sis190_phy *cur, *next;
1221
1222 list_for_each_entry_safe(cur, next, first_phy, list) {
1223 kfree(cur);
1224 }
1225}
1226
1227/**
1228 * sis190_default_phy - Select default PHY for sis190 mac.
1229 * @dev: the net device to probe for
1230 *
1231 * Select first detected PHY with link as default.
1232 * If no one is link on, select PHY whose types is HOME as default.
1233 * If HOME doesn't exist, select LAN.
1234 */
1235static u16 sis190_default_phy(struct net_device *dev)
1236{
1237 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1238 struct sis190_private *tp = netdev_priv(dev);
1239 struct mii_if_info *mii_if = &tp->mii_if;
1240 void __iomem *ioaddr = tp->mmio_addr;
1241 u16 status;
1242
1243 phy_home = phy_default = phy_lan = NULL;
1244
1245 list_for_each_entry(phy, &tp->first_phy, list) {
1246 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1247
1248 // Link ON & Not select default PHY & not ghost PHY.
1249 if ((status & BMSR_LSTATUS) &&
1250 !phy_default &&
1251 (phy->type != UNKNOWN)) {
1252 phy_default = phy;
1253 } else {
1254 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1255 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1256 status | BMCR_ANENABLE | BMCR_ISOLATE);
1257 if (phy->type == HOME)
1258 phy_home = phy;
1259 else if (phy->type == LAN)
1260 phy_lan = phy;
1261 }
1262 }
1263
1264 if (!phy_default) {
1265 if (phy_home)
1266 phy_default = phy_home;
1267 else if (phy_lan)
1268 phy_default = phy_lan;
1269 else
1270 phy_default = list_entry(&tp->first_phy,
1271 struct sis190_phy, list);
1272 }
1273
1274 if (mii_if->phy_id != phy_default->phy_id) {
1275 mii_if->phy_id = phy_default->phy_id;
1276 net_probe(tp, KERN_INFO
1277 "%s: Using transceiver at address %d as default.\n",
3690b6c1 1278 pci_name(tp->pci_dev), mii_if->phy_id);
fcb9821d
FR		 1279 }
1280
1281 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1282 status &= (~BMCR_ISOLATE);
1283
1284 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1285 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1286
1287 return status;
1288}
1289
1290static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1291 struct sis190_phy *phy, unsigned int phy_id,
1292 u16 mii_status)
1293{
1294 void __iomem *ioaddr = tp->mmio_addr;
1295 struct mii_chip_info *p;
1296
1297 INIT_LIST_HEAD(&phy->list);
1298 phy->status = mii_status;
1299 phy->phy_id = phy_id;
1300
1301 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1302 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1303
1304 for (p = mii_chip_table; p->type; p++) {
1305 if ((p->id[0] == phy->id[0]) &&
1306 (p->id[1] == (phy->id[1] & 0xfff0))) {
1307 break;
1308 }
1309 }
1310
1311 if (p->id[1]) {
1312 phy->type = (p->type == MIX) ?
1313 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1314 LAN : HOME) : p->type;
900eb9d6 1315 tp->features |= p->feature;
fcb9821d
FR		 1316 } else
1317 phy->type = UNKNOWN;
1318
1319 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
3690b6c1
FR		 1320 pci_name(tp->pci_dev),
1321 (phy->type == UNKNOWN) ? "Unknown PHY" : p->name, phy_id);
fcb9821d
FR		 1322}
1323
900eb9d6
FR		 1324static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1325{
1326 if (tp->features & F_PHY_88E1111) {
1327 void __iomem *ioaddr = tp->mmio_addr;
1328 int phy_id = tp->mii_if.phy_id;
1329 u16 reg[2][2] = {
1330 { 0x808b, 0x0ce1 },
1331 { 0x808f, 0x0c60 }
1332 }, *p;
1333
1334 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1335
1336 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1337 udelay(200);
1338 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1339 udelay(200);
1340 }
1341}
1342
fcb9821d
FR		 1343/**
1344 * sis190_mii_probe - Probe MII PHY for sis190
1345 * @dev: the net device to probe for
1346 *
1347 * Search for total of 32 possible mii phy addresses.
1348 * Identify and set current phy if found one,
1349 * return error if it failed to found.
1350 */
1351static int __devinit sis190_mii_probe(struct net_device *dev)
1352{
1353 struct sis190_private *tp = netdev_priv(dev);
1354 struct mii_if_info *mii_if = &tp->mii_if;
1355 void __iomem *ioaddr = tp->mmio_addr;
1356 int phy_id;
1357 int rc = 0;
1358
1359 INIT_LIST_HEAD(&tp->first_phy);
1360
1361 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1362 struct sis190_phy *phy;
1363 u16 status;
1364
1365 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1366
1367 // Try next mii if the current one is not accessible.
1368 if (status == 0xffff || status == 0x0000)
1369 continue;
1370
1371 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1372 if (!phy) {
1373 sis190_free_phy(&tp->first_phy);
1374 rc = -ENOMEM;
1375 goto out;
1376 }
1377
1378 sis190_init_phy(dev, tp, phy, phy_id, status);
1379
1380 list_add(&tp->first_phy, &phy->list);
1381 }
1382
1383 if (list_empty(&tp->first_phy)) {
1384 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
3690b6c1 1385 pci_name(tp->pci_dev));
fcb9821d
FR		 1386 rc = -EIO;
1387 goto out;
1388 }
1389
1390 /* Select default PHY for mac */
1391 sis190_default_phy(dev);
1392
900eb9d6
FR		 1393 sis190_mii_probe_88e1111_fixup(tp);
1394
fcb9821d
FR		 1395 mii_if->dev = dev;
1396 mii_if->mdio_read = __mdio_read;
1397 mii_if->mdio_write = __mdio_write;
1398 mii_if->phy_id_mask = PHY_ID_ANY;
1399 mii_if->reg_num_mask = MII_REG_ANY;
1400out:
1401 return rc;
1402}
1403
c2b75f0c 1404static void sis190_mii_remove(struct net_device *dev)
fcb9821d
FR		 1405{
1406 struct sis190_private *tp = netdev_priv(dev);
1407
1408 sis190_free_phy(&tp->first_phy);
1409}
1410
890e8d0a
FR		 1411static void sis190_release_board(struct pci_dev *pdev)
1412{
1413 struct net_device *dev = pci_get_drvdata(pdev);
1414 struct sis190_private *tp = netdev_priv(dev);
1415
1416 iounmap(tp->mmio_addr);
1417 pci_release_regions(pdev);
1418 pci_disable_device(pdev);
1419 free_netdev(dev);
1420}
1421
1422static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1423{
1424 struct sis190_private *tp;
1425 struct net_device *dev;
1426 void __iomem *ioaddr;
1427 int rc;
1428
1429 dev = alloc_etherdev(sizeof(*tp));
1430 if (!dev) {
1431 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1432 rc = -ENOMEM;
1433 goto err_out_0;
1434 }
1435
890e8d0a
FR		 1436 SET_NETDEV_DEV(dev, &pdev->dev);
1437
1438 tp = netdev_priv(dev);
c4028958 1439 tp->dev = dev;
890e8d0a
FR		 1440 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1441
1442 rc = pci_enable_device(pdev);
1443 if (rc < 0) {
1444 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1445 goto err_free_dev_1;
1446 }
1447
1448 rc = -ENODEV;
1449
1450 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1451 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1452 pci_name(pdev));
1453 goto err_pci_disable_2;
1454 }
1455 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1456 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1457 pci_name(pdev));
1458 goto err_pci_disable_2;
1459 }
1460
1461 rc = pci_request_regions(pdev, DRV_NAME);
1462 if (rc < 0) {
1463 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1464 pci_name(pdev));
1465 goto err_pci_disable_2;
1466 }
1467
284901a9 1468 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
890e8d0a
FR		 1469 if (rc < 0) {
1470 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1471 pci_name(pdev));
1472 goto err_free_res_3;
1473 }
1474
1475 pci_set_master(pdev);
1476
1477 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1478 if (!ioaddr) {
1479 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1480 pci_name(pdev));
1481 rc = -EIO;
1482 goto err_free_res_3;
1483 }
1484
1485 tp->pci_dev = pdev;
1486 tp->mmio_addr = ioaddr;
1487
1488 sis190_irq_mask_and_ack(ioaddr);
1489
1490 sis190_soft_reset(ioaddr);
1491out:
1492 return dev;
1493
1494err_free_res_3:
1495 pci_release_regions(pdev);
1496err_pci_disable_2:
1497 pci_disable_device(pdev);
1498err_free_dev_1:
1499 free_netdev(dev);
1500err_out_0:
1501 dev = ERR_PTR(rc);
1502 goto out;
1503}
1504
1505static void sis190_tx_timeout(struct net_device *dev)
1506{
1507 struct sis190_private *tp = netdev_priv(dev);
1508 void __iomem *ioaddr = tp->mmio_addr;
1509 u8 tmp8;
1510
1511 /* Disable Tx, if not already */
1512 tmp8 = SIS_R8(TxControl);
1513 if (tmp8 & CmdTxEnb)
1514 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1515
188f23ba
FR		 1516
1517 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1518 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1519
890e8d0a
FR		 1520 /* Disable interrupts by clearing the interrupt mask. */
1521 SIS_W32(IntrMask, 0x0000);
1522
1523 /* Stop a shared interrupt from scavenging while we are. */
1524 spin_lock_irq(&tp->lock);
1525 sis190_tx_clear(tp);
1526 spin_unlock_irq(&tp->lock);
1527
1528 /* ...and finally, reset everything. */
1529 sis190_hw_start(dev);
1530
1531 netif_wake_queue(dev);
1532}
1533
900eb9d6
FR		 1534static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1535{
1536 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1537}
1538
830fb7d2
FR		 1539static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1540 struct net_device *dev)
1541{
1542 struct sis190_private *tp = netdev_priv(dev);
1543 void __iomem *ioaddr = tp->mmio_addr;
1544 u16 sig;
1545 int i;
1546
1547 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1548 pci_name(pdev));
1549
1550 /* Check to see if there is a sane EEPROM */
1551 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1552
1553 if ((sig == 0xffff) || (sig == 0x0000)) {
1554 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1555 pci_name(pdev), sig);
1556 return -EIO;
1557 }
1558
1559 /* Get MAC address from EEPROM */
1560 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
961994a0 1561 u16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
830fb7d2 1562
961994a0 1563 ((__le16 *)dev->dev_addr)[i] = cpu_to_le16(w);
830fb7d2
FR		 1564 }
1565
900eb9d6
FR		 1566 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1567
830fb7d2
FR		 1568 return 0;
1569}
1570
1571/**
ebc71647 1572 * sis190_get_mac_addr_from_apc - Get MAC address for SiS96x model
830fb7d2
FR		 1573 * @pdev: PCI device
1574 * @dev: network device to get address for
1575 *
ebc71647 1576 * SiS96x model, use APC CMOS RAM to store MAC address.
830fb7d2
FR		 1577 * APC CMOS RAM is accessed through ISA bridge.
1578 * MAC address is read into @net_dev->dev_addr.
1579 */
1580static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1581 struct net_device *dev)
1582{
ebc71647 1583 static const u16 __devinitdata ids[] = { 0x0965, 0x0966, 0x0968 };
830fb7d2
FR		 1584 struct sis190_private *tp = netdev_priv(dev);
1585 struct pci_dev *isa_bridge;
1586 u8 reg, tmp8;
ebc71647 1587 unsigned int i;
830fb7d2
FR		 1588
1589 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1590 pci_name(pdev));
1591
ebc71647
FR		 1592 for (i = 0; i < ARRAY_SIZE(ids); i++) {
1593 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, ids[i], NULL);
1594 if (isa_bridge)
1595 break;
1596 }
8eb7ad68 1597
830fb7d2
FR		 1598 if (!isa_bridge) {
1599 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1600 pci_name(pdev));
1601 return -EIO;
1602 }
1603
1604 /* Enable port 78h & 79h to access APC Registers. */
1605 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1606 reg = (tmp8 & ~0x02);
1607 pci_write_config_byte(isa_bridge, 0x48, reg);
1608 udelay(50);
1609 pci_read_config_byte(isa_bridge, 0x48, &reg);
1610
1611 for (i = 0; i < MAC_ADDR_LEN; i++) {
1612 outb(0x9 + i, 0x78);
1613 dev->dev_addr[i] = inb(0x79);
1614 }
1615
1616 outb(0x12, 0x78);
1617 reg = inb(0x79);
1618
900eb9d6
FR		 1619 sis190_set_rgmii(tp, reg);
1620
830fb7d2
FR		 1621 /* Restore the value to ISA Bridge */
1622 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1623 pci_dev_put(isa_bridge);
1624
1625 return 0;
1626}
1627
1628/**
1629 * sis190_init_rxfilter - Initialize the Rx filter
1630 * @dev: network device to initialize
1631 *
1632 * Set receive filter address to our MAC address
1633 * and enable packet filtering.
1634 */
1635static inline void sis190_init_rxfilter(struct net_device *dev)
1636{
1637 struct sis190_private *tp = netdev_priv(dev);
1638 void __iomem *ioaddr = tp->mmio_addr;
1639 u16 ctl;
1640 int i;
1641
1642 ctl = SIS_R16(RxMacControl);
1643 /*
1644 * Disable packet filtering before setting filter.
1645 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1646 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1647 */
1648 SIS_W16(RxMacControl, ctl & ~0x0f00);
1649
1650 for (i = 0; i < MAC_ADDR_LEN; i++)
1651 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1652
1653 SIS_W16(RxMacControl, ctl);
1654 SIS_PCI_COMMIT();
1655}
1656
7d2e3cb7 1657static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
d785ad74 1658 struct net_device *dev)
830fb7d2 1659{
563e0ae0
FR		 1660 int rc;
1661
1662 rc = sis190_get_mac_addr_from_eeprom(pdev, dev);
1663 if (rc < 0) {
1664 u8 reg;
830fb7d2 1665
563e0ae0 1666 pci_read_config_byte(pdev, 0x73, &reg);
830fb7d2 1667
563e0ae0
FR		 1668 if (reg & 0x00000001)
1669 rc = sis190_get_mac_addr_from_apc(pdev, dev);
1670 }
1671 return rc;
830fb7d2
FR		 1672}
1673
890e8d0a
FR		 1674static void sis190_set_speed_auto(struct net_device *dev)
1675{
1676 struct sis190_private *tp = netdev_priv(dev);
1677 void __iomem *ioaddr = tp->mmio_addr;
9ede109b 1678 int phy_id = tp->mii_if.phy_id;
890e8d0a
FR		 1679 int val;
1680
1681 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1682
9ede109b 1683 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
890e8d0a
FR		 1684
1685 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1686 // unchanged.
9ede109b 1687 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
890e8d0a
FR		 1688 ADVERTISE_100FULL | ADVERTISE_10FULL |
1689 ADVERTISE_100HALF | ADVERTISE_10HALF);
1690
1691 // Enable 1000 Full Mode.
9ede109b 1692 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
890e8d0a
FR		 1693
1694 // Enable auto-negotiation and restart auto-negotiation.
9ede109b 1695 mdio_write(ioaddr, phy_id, MII_BMCR,
890e8d0a
FR		 1696 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1697}
1698
43afb949
FR		 1699static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1700{
1701 struct sis190_private *tp = netdev_priv(dev);
1702
1703 return mii_ethtool_gset(&tp->mii_if, cmd);
1704}
1705
1706static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1707{
1708 struct sis190_private *tp = netdev_priv(dev);
1709
1710 return mii_ethtool_sset(&tp->mii_if, cmd);
1711}
1712
890e8d0a
FR		 1713static void sis190_get_drvinfo(struct net_device *dev,
1714 struct ethtool_drvinfo *info)
1715{
1716 struct sis190_private *tp = netdev_priv(dev);
1717
1718 strcpy(info->driver, DRV_NAME);
1719 strcpy(info->version, DRV_VERSION);
1720 strcpy(info->bus_info, pci_name(tp->pci_dev));
1721}
1722
1723static int sis190_get_regs_len(struct net_device *dev)
1724{
1725 return SIS190_REGS_SIZE;
1726}
1727
1728static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1729 void *p)
1730{
1731 struct sis190_private *tp = netdev_priv(dev);
1732 unsigned long flags;
1733
1734 if (regs->len > SIS190_REGS_SIZE)
1735 regs->len = SIS190_REGS_SIZE;
1736
1737 spin_lock_irqsave(&tp->lock, flags);
1738 memcpy_fromio(p, tp->mmio_addr, regs->len);
1739 spin_unlock_irqrestore(&tp->lock, flags);
1740}
1741
43afb949
FR		 1742static int sis190_nway_reset(struct net_device *dev)
1743{
1744 struct sis190_private *tp = netdev_priv(dev);
1745
1746 return mii_nway_restart(&tp->mii_if);
1747}
1748
890e8d0a
FR		 1749static u32 sis190_get_msglevel(struct net_device *dev)
1750{
1751 struct sis190_private *tp = netdev_priv(dev);
1752
1753 return tp->msg_enable;
1754}
1755
1756static void sis190_set_msglevel(struct net_device *dev, u32 value)
1757{
1758 struct sis190_private *tp = netdev_priv(dev);
1759
1760 tp->msg_enable = value;
1761}
1762
7282d491 1763static const struct ethtool_ops sis190_ethtool_ops = {
43afb949
FR		 1764 .get_settings = sis190_get_settings,
1765 .set_settings = sis190_set_settings,
890e8d0a
FR		 1766 .get_drvinfo = sis190_get_drvinfo,
1767 .get_regs_len = sis190_get_regs_len,
1768 .get_regs = sis190_get_regs,
1769 .get_link = ethtool_op_get_link,
1770 .get_msglevel = sis190_get_msglevel,
1771 .set_msglevel = sis190_set_msglevel,
43afb949 1772 .nway_reset = sis190_nway_reset,
890e8d0a
FR		 1773};
1774
43afb949
FR		 1775static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1776{
1777 struct sis190_private *tp = netdev_priv(dev);
1778
1779 return !netif_running(dev) ? -EINVAL :
1780 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1781}
1782
97488c5b
SH		 1783static const struct net_device_ops sis190_netdev_ops = {
1784 .ndo_open = sis190_open,
1785 .ndo_stop = sis190_close,
1786 .ndo_do_ioctl = sis190_ioctl,
1787 .ndo_start_xmit = sis190_start_xmit,
1788 .ndo_tx_timeout = sis190_tx_timeout,
1789 .ndo_set_multicast_list = sis190_set_rx_mode,
1790 .ndo_change_mtu = eth_change_mtu,
1791 .ndo_set_mac_address = eth_mac_addr,
1792 .ndo_validate_addr = eth_validate_addr,
1793#ifdef CONFIG_NET_POLL_CONTROLLER
1794 .ndo_poll_controller = sis190_netpoll,
1795#endif
1796};
1797
890e8d0a
FR		 1798static int __devinit sis190_init_one(struct pci_dev *pdev,
1799 const struct pci_device_id *ent)
1800{
1801 static int printed_version = 0;
1802 struct sis190_private *tp;
1803 struct net_device *dev;
1804 void __iomem *ioaddr;
830fb7d2 1805 int rc;
890e8d0a
FR		 1806
1807 if (!printed_version) {
1808 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1809 printed_version = 1;
1810 }
1811
1812 dev = sis190_init_board(pdev);
1813 if (IS_ERR(dev)) {
1814 rc = PTR_ERR(dev);
1815 goto out;
1816 }
1817
10487fbd
FR		 1818 pci_set_drvdata(pdev, dev);
1819
890e8d0a
FR		 1820 tp = netdev_priv(dev);
1821 ioaddr = tp->mmio_addr;
1822
830fb7d2
FR		 1823 rc = sis190_get_mac_addr(pdev, dev);
1824 if (rc < 0)
1825 goto err_release_board;
890e8d0a 1826
830fb7d2 1827 sis190_init_rxfilter(dev);
890e8d0a 1828
c4028958 1829 INIT_WORK(&tp->phy_task, sis190_phy_task);
890e8d0a 1830
97488c5b
SH		 1831 dev->netdev_ops = &sis190_netdev_ops;
1832
890e8d0a
FR		 1833 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1834 dev->irq = pdev->irq;
1835 dev->base_addr = (unsigned long) 0xdead;
97488c5b 1836 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
890e8d0a
FR		 1837
1838 spin_lock_init(&tp->lock);
3690b6c1
FR		 1839
1840 rc = sis190_mii_probe(dev);
830fb7d2
FR		 1841 if (rc < 0)
1842 goto err_release_board;
890e8d0a 1843
3690b6c1 1844 rc = register_netdev(dev);
fcb9821d 1845 if (rc < 0)
3690b6c1
FR		 1846 goto err_remove_mii;
1847
e174961c 1848 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), %pM\n",
0795af57 1849 pci_name(pdev), sis_chip_info[ent->driver_data].name,
e174961c 1850 ioaddr, dev->irq, dev->dev_addr);
890e8d0a 1851
900eb9d6
FR		 1852 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1853 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1854
890e8d0a
FR		 1855 netif_carrier_off(dev);
1856
1857 sis190_set_speed_auto(dev);
1858out:
1859 return rc;
830fb7d2 1860
3690b6c1
FR		 1861err_remove_mii:
1862 sis190_mii_remove(dev);
830fb7d2
FR		 1863err_release_board:
1864 sis190_release_board(pdev);
1865 goto out;
890e8d0a
FR		 1866}
1867
1868static void __devexit sis190_remove_one(struct pci_dev *pdev)
1869{
1870 struct net_device *dev = pci_get_drvdata(pdev);
1871
fcb9821d 1872 sis190_mii_remove(dev);
c014f6c8 1873 flush_scheduled_work();
890e8d0a
FR		 1874 unregister_netdev(dev);
1875 sis190_release_board(pdev);
1876 pci_set_drvdata(pdev, NULL);
1877}
1878
1879static struct pci_driver sis190_pci_driver = {
1880 .name = DRV_NAME,
1881 .id_table = sis190_pci_tbl,
1882 .probe = sis190_init_one,
1883 .remove = __devexit_p(sis190_remove_one),
1884};
1885
1886static int __init sis190_init_module(void)
1887{
29917620 1888 return pci_register_driver(&sis190_pci_driver);
890e8d0a
FR		 1889}
1890
1891static void __exit sis190_cleanup_module(void)
1892{
1893 pci_unregister_driver(&sis190_pci_driver);
1894}
1895
1896module_init(sis190_init_module);
1897module_exit(sis190_cleanup_module);
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