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[net-next-2.6.git] / drivers / net / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2
NI		 23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/netdevice.h>
30#include <linux/phy.h>
31#include <linux/cache.h>
32#include <linux/io.h>
bcd5149d 33#include <linux/pm_runtime.h>
f568a926 34#include <asm/cacheflush.h>
86a74ff2
NI		 35
36#include "sh_eth.h"
37
380af9e3 38/* There is CPU dependent code */
65ac8851
YS		 39#if defined(CONFIG_CPU_SUBTYPE_SH7724)
40#define SH_ETH_RESET_DEFAULT 1
41static void sh_eth_set_duplex(struct net_device *ndev)
42{
43 struct sh_eth_private *mdp = netdev_priv(ndev);
44 u32 ioaddr = ndev->base_addr;
45
46 if (mdp->duplex) /* Full */
47 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
48 else /* Half */
49 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
50}
51
52static void sh_eth_set_rate(struct net_device *ndev)
53{
54 struct sh_eth_private *mdp = netdev_priv(ndev);
55 u32 ioaddr = ndev->base_addr;
56
57 switch (mdp->speed) {
58 case 10: /* 10BASE */
59 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
60 break;
61 case 100:/* 100BASE */
62 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
63 break;
64 default:
65 break;
66 }
67}
68
69/* SH7724 */
70static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
71 .set_duplex = sh_eth_set_duplex,
72 .set_rate = sh_eth_set_rate,
73
74 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
75 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
76 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
77
78 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
79 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
80 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
81 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
82
83 .apr = 1,
84 .mpr = 1,
85 .tpauser = 1,
86 .hw_swap = 1,
503914cf
MD		 87 .rpadir = 1,
88 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851
YS		 89};
90
91#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 92#define SH_ETH_HAS_TSU 1
93static void sh_eth_chip_reset(struct net_device *ndev)
94{
95 /* reset device */
96 ctrl_outl(ARSTR_ARSTR, ARSTR);
97 mdelay(1);
98}
99
100static void sh_eth_reset(struct net_device *ndev)
101{
102 u32 ioaddr = ndev->base_addr;
103 int cnt = 100;
104
105 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
106 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
107 while (cnt > 0) {
108 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
109 break;
110 mdelay(1);
111 cnt--;
112 }
890c8c18 113 if (cnt == 0)
380af9e3
YS		 114 printk(KERN_ERR "Device reset fail\n");
115
116 /* Table Init */
117 ctrl_outl(0x0, ioaddr + TDLAR);
118 ctrl_outl(0x0, ioaddr + TDFAR);
119 ctrl_outl(0x0, ioaddr + TDFXR);
120 ctrl_outl(0x0, ioaddr + TDFFR);
121 ctrl_outl(0x0, ioaddr + RDLAR);
122 ctrl_outl(0x0, ioaddr + RDFAR);
123 ctrl_outl(0x0, ioaddr + RDFXR);
124 ctrl_outl(0x0, ioaddr + RDFFR);
125}
126
127static void sh_eth_set_duplex(struct net_device *ndev)
128{
129 struct sh_eth_private *mdp = netdev_priv(ndev);
130 u32 ioaddr = ndev->base_addr;
131
132 if (mdp->duplex) /* Full */
133 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
134 else /* Half */
135 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
136}
137
138static void sh_eth_set_rate(struct net_device *ndev)
139{
140 struct sh_eth_private *mdp = netdev_priv(ndev);
141 u32 ioaddr = ndev->base_addr;
142
143 switch (mdp->speed) {
144 case 10: /* 10BASE */
145 ctrl_outl(GECMR_10, ioaddr + GECMR);
146 break;
147 case 100:/* 100BASE */
148 ctrl_outl(GECMR_100, ioaddr + GECMR);
149 break;
150 case 1000: /* 1000BASE */
151 ctrl_outl(GECMR_1000, ioaddr + GECMR);
152 break;
153 default:
154 break;
155 }
156}
157
158/* sh7763 */
159static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
160 .chip_reset = sh_eth_chip_reset,
161 .set_duplex = sh_eth_set_duplex,
162 .set_rate = sh_eth_set_rate,
163
164 .ecsr_value = ECSR_ICD | ECSR_MPD,
165 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
166 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
167
168 .tx_check = EESR_TC1 | EESR_FTC,
169 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
170 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
171 EESR_ECI,
172 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
173 EESR_TFE,
174
175 .apr = 1,
176 .mpr = 1,
177 .tpauser = 1,
178 .bculr = 1,
179 .hw_swap = 1,
380af9e3
YS		 180 .no_trimd = 1,
181 .no_ade = 1,
182};
183
184#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
185#define SH_ETH_RESET_DEFAULT 1
186static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
187 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
188
189 .apr = 1,
190 .mpr = 1,
191 .tpauser = 1,
192 .hw_swap = 1,
193};
194#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
195#define SH_ETH_RESET_DEFAULT 1
196#define SH_ETH_HAS_TSU 1
197static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
198 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
199};
200#endif
201
202static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
203{
204 if (!cd->ecsr_value)
205 cd->ecsr_value = DEFAULT_ECSR_INIT;
206
207 if (!cd->ecsipr_value)
208 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
209
210 if (!cd->fcftr_value)
211 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
212 DEFAULT_FIFO_F_D_RFD;
213
214 if (!cd->fdr_value)
215 cd->fdr_value = DEFAULT_FDR_INIT;
216
217 if (!cd->rmcr_value)
218 cd->rmcr_value = DEFAULT_RMCR_VALUE;
219
220 if (!cd->tx_check)
221 cd->tx_check = DEFAULT_TX_CHECK;
222
223 if (!cd->eesr_err_check)
224 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
225
226 if (!cd->tx_error_check)
227 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
228}
229
230#if defined(SH_ETH_RESET_DEFAULT)
231/* Chip Reset */
232static void sh_eth_reset(struct net_device *ndev)
233{
234 u32 ioaddr = ndev->base_addr;
235
236 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
237 mdelay(3);
238 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
239}
240#endif
241
242#if defined(CONFIG_CPU_SH4)
243static void sh_eth_set_receive_align(struct sk_buff *skb)
244{
245 int reserve;
246
247 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
248 if (reserve)
249 skb_reserve(skb, reserve);
250}
251#else
252static void sh_eth_set_receive_align(struct sk_buff *skb)
253{
254 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
255}
256#endif
257
258
71557a37
YS		 259/* CPU <-> EDMAC endian convert */
260static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
261{
262 switch (mdp->edmac_endian) {
263 case EDMAC_LITTLE_ENDIAN:
264 return cpu_to_le32(x);
265 case EDMAC_BIG_ENDIAN:
266 return cpu_to_be32(x);
267 }
268 return x;
269}
270
271static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
272{
273 switch (mdp->edmac_endian) {
274 case EDMAC_LITTLE_ENDIAN:
275 return le32_to_cpu(x);
276 case EDMAC_BIG_ENDIAN:
277 return be32_to_cpu(x);
278 }
279 return x;
280}
281
86a74ff2
NI		 282/*
283 * Program the hardware MAC address from dev->dev_addr.
284 */
285static void update_mac_address(struct net_device *ndev)
286{
287 u32 ioaddr = ndev->base_addr;
288
289 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
290 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
291 ioaddr + MAHR);
292 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
293 ioaddr + MALR);
294}
295
296/*
297 * Get MAC address from SuperH MAC address register
298 *
299 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
300 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
301 * When you want use this device, you must set MAC address in bootloader.
302 *
303 */
748031f9 304static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2
NI		 305{
306 u32 ioaddr = ndev->base_addr;
307
748031f9
MD		 308 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
309 memcpy(ndev->dev_addr, mac, 6);
310 } else {
311 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
312 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
313 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
314 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
315 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
316 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
317 }
86a74ff2
NI		 318}
319
320struct bb_info {
321 struct mdiobb_ctrl ctrl;
322 u32 addr;
323 u32 mmd_msk;/* MMD */
324 u32 mdo_msk;
325 u32 mdi_msk;
326 u32 mdc_msk;
327};
328
329/* PHY bit set */
330static void bb_set(u32 addr, u32 msk)
331{
332 ctrl_outl(ctrl_inl(addr) | msk, addr);
333}
334
335/* PHY bit clear */
336static void bb_clr(u32 addr, u32 msk)
337{
338 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
339}
340
341/* PHY bit read */
342static int bb_read(u32 addr, u32 msk)
343{
344 return (ctrl_inl(addr) & msk) != 0;
345}
346
347/* Data I/O pin control */
348static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
349{
350 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
351 if (bit)
352 bb_set(bitbang->addr, bitbang->mmd_msk);
353 else
354 bb_clr(bitbang->addr, bitbang->mmd_msk);
355}
356
357/* Set bit data*/
358static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
359{
360 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
361
362 if (bit)
363 bb_set(bitbang->addr, bitbang->mdo_msk);
364 else
365 bb_clr(bitbang->addr, bitbang->mdo_msk);
366}
367
368/* Get bit data*/
369static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
370{
371 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
372 return bb_read(bitbang->addr, bitbang->mdi_msk);
373}
374
375/* MDC pin control */
376static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
377{
378 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
379
380 if (bit)
381 bb_set(bitbang->addr, bitbang->mdc_msk);
382 else
383 bb_clr(bitbang->addr, bitbang->mdc_msk);
384}
385
386/* mdio bus control struct */
387static struct mdiobb_ops bb_ops = {
388 .owner = THIS_MODULE,
389 .set_mdc = sh_mdc_ctrl,
390 .set_mdio_dir = sh_mmd_ctrl,
391 .set_mdio_data = sh_set_mdio,
392 .get_mdio_data = sh_get_mdio,
393};
394
86a74ff2
NI		 395/* free skb and descriptor buffer */
396static void sh_eth_ring_free(struct net_device *ndev)
397{
398 struct sh_eth_private *mdp = netdev_priv(ndev);
399 int i;
400
401 /* Free Rx skb ringbuffer */
402 if (mdp->rx_skbuff) {
403 for (i = 0; i < RX_RING_SIZE; i++) {
404 if (mdp->rx_skbuff[i])
405 dev_kfree_skb(mdp->rx_skbuff[i]);
406 }
407 }
408 kfree(mdp->rx_skbuff);
409
410 /* Free Tx skb ringbuffer */
411 if (mdp->tx_skbuff) {
412 for (i = 0; i < TX_RING_SIZE; i++) {
413 if (mdp->tx_skbuff[i])
414 dev_kfree_skb(mdp->tx_skbuff[i]);
415 }
416 }
417 kfree(mdp->tx_skbuff);
418}
419
420/* format skb and descriptor buffer */
421static void sh_eth_ring_format(struct net_device *ndev)
422{
380af9e3 423 u32 ioaddr = ndev->base_addr;
86a74ff2
NI		 424 struct sh_eth_private *mdp = netdev_priv(ndev);
425 int i;
426 struct sk_buff *skb;
427 struct sh_eth_rxdesc *rxdesc = NULL;
428 struct sh_eth_txdesc *txdesc = NULL;
429 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
430 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
431
432 mdp->cur_rx = mdp->cur_tx = 0;
433 mdp->dirty_rx = mdp->dirty_tx = 0;
434
435 memset(mdp->rx_ring, 0, rx_ringsize);
436
437 /* build Rx ring buffer */
438 for (i = 0; i < RX_RING_SIZE; i++) {
439 /* skb */
440 mdp->rx_skbuff[i] = NULL;
441 skb = dev_alloc_skb(mdp->rx_buf_sz);
442 mdp->rx_skbuff[i] = skb;
443 if (skb == NULL)
444 break;
e88aae7b
YS		 445 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
446 DMA_FROM_DEVICE);
b0ca2a21 447 skb->dev = ndev; /* Mark as being used by this device. */
380af9e3
YS		 448 sh_eth_set_receive_align(skb);
449
86a74ff2
NI		 450 /* RX descriptor */
451 rxdesc = &mdp->rx_ring[i];
0029d64a 452 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 453 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 454
455 /* The size of the buffer is 16 byte boundary. */
0029d64a 456 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 457 /* Rx descriptor address set */
458 if (i == 0) {
0029d64a 459 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
b0ca2a21 460#if defined(CONFIG_CPU_SUBTYPE_SH7763)
0029d64a 461 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
b0ca2a21
NI		 462#endif
463 }
86a74ff2
NI		 464 }
465
466 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
467
468 /* Mark the last entry as wrapping the ring. */
71557a37 469 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 470
471 memset(mdp->tx_ring, 0, tx_ringsize);
472
473 /* build Tx ring buffer */
474 for (i = 0; i < TX_RING_SIZE; i++) {
475 mdp->tx_skbuff[i] = NULL;
476 txdesc = &mdp->tx_ring[i];
71557a37 477 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 478 txdesc->buffer_length = 0;
b0ca2a21 479 if (i == 0) {
71557a37 480 /* Tx descriptor address set */
0029d64a 481 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
b0ca2a21 482#if defined(CONFIG_CPU_SUBTYPE_SH7763)
0029d64a 483 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
b0ca2a21
NI		 484#endif
485 }
86a74ff2
NI		 486 }
487
71557a37 488 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 489}
490
491/* Get skb and descriptor buffer */
492static int sh_eth_ring_init(struct net_device *ndev)
493{
494 struct sh_eth_private *mdp = netdev_priv(ndev);
495 int rx_ringsize, tx_ringsize, ret = 0;
496
497 /*
498 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
499 * card needs room to do 8 byte alignment, +2 so we can reserve
500 * the first 2 bytes, and +16 gets room for the status word from the
501 * card.
502 */
503 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
504 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 505 if (mdp->cd->rpadir)
506 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 507
508 /* Allocate RX and TX skb rings */
509 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
510 GFP_KERNEL);
511 if (!mdp->rx_skbuff) {
380af9e3 512 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 513 ret = -ENOMEM;
514 return ret;
515 }
516
517 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
518 GFP_KERNEL);
519 if (!mdp->tx_skbuff) {
380af9e3 520 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 521 ret = -ENOMEM;
522 goto skb_ring_free;
523 }
524
525 /* Allocate all Rx descriptors. */
526 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
527 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
528 GFP_KERNEL);
529
530 if (!mdp->rx_ring) {
380af9e3
YS		 531 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
532 rx_ringsize);
86a74ff2
NI		 533 ret = -ENOMEM;
534 goto desc_ring_free;
535 }
536
537 mdp->dirty_rx = 0;
538
539 /* Allocate all Tx descriptors. */
540 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
541 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
542 GFP_KERNEL);
543 if (!mdp->tx_ring) {
380af9e3
YS		 544 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
545 tx_ringsize);
86a74ff2
NI		 546 ret = -ENOMEM;
547 goto desc_ring_free;
548 }
549 return ret;
550
551desc_ring_free:
552 /* free DMA buffer */
553 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
554
555skb_ring_free:
556 /* Free Rx and Tx skb ring buffer */
557 sh_eth_ring_free(ndev);
558
559 return ret;
560}
561
562static int sh_eth_dev_init(struct net_device *ndev)
563{
564 int ret = 0;
565 struct sh_eth_private *mdp = netdev_priv(ndev);
566 u32 ioaddr = ndev->base_addr;
567 u_int32_t rx_int_var, tx_int_var;
568 u32 val;
569
570 /* Soft Reset */
571 sh_eth_reset(ndev);
572
b0ca2a21
NI		 573 /* Descriptor format */
574 sh_eth_ring_format(ndev);
380af9e3
YS		 575 if (mdp->cd->rpadir)
576 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
86a74ff2
NI		 577
578 /* all sh_eth int mask */
579 ctrl_outl(0, ioaddr + EESIPR);
580
380af9e3
YS		 581#if defined(__LITTLE_ENDIAN__)
582 if (mdp->cd->hw_swap)
583 ctrl_outl(EDMR_EL, ioaddr + EDMR);
584 else
b0ca2a21 585#endif
380af9e3 586 ctrl_outl(0, ioaddr + EDMR);
86a74ff2 587
b0ca2a21 588 /* FIFO size set */
380af9e3 589 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
86a74ff2
NI		 590 ctrl_outl(0, ioaddr + TFTR);
591
b0ca2a21 592 /* Frame recv control */
380af9e3 593 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
86a74ff2
NI		 594
595 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
596 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
597 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
598
380af9e3
YS		 599 if (mdp->cd->bculr)
600 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
b0ca2a21 601
380af9e3 602 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
86a74ff2 603
380af9e3
YS		 604 if (!mdp->cd->no_trimd)
605 ctrl_outl(0, ioaddr + TRIMD);
86a74ff2 606
b0ca2a21
NI		 607 /* Recv frame limit set register */
608 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
86a74ff2
NI		 609
610 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
380af9e3 611 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
86a74ff2
NI		 612
613 /* PAUSE Prohibition */
614 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
615 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
616
617 ctrl_outl(val, ioaddr + ECMR);
b0ca2a21 618
380af9e3
YS		 619 if (mdp->cd->set_rate)
620 mdp->cd->set_rate(ndev);
621
b0ca2a21 622 /* E-MAC Status Register clear */
380af9e3 623 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
b0ca2a21
NI		 624
625 /* E-MAC Interrupt Enable register */
380af9e3 626 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
86a74ff2
NI		 627
628 /* Set MAC address */
629 update_mac_address(ndev);
630
631 /* mask reset */
380af9e3
YS		 632 if (mdp->cd->apr)
633 ctrl_outl(APR_AP, ioaddr + APR);
634 if (mdp->cd->mpr)
635 ctrl_outl(MPR_MP, ioaddr + MPR);
636 if (mdp->cd->tpauser)
637 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
b0ca2a21 638
86a74ff2
NI		 639 /* Setting the Rx mode will start the Rx process. */
640 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
641
642 netif_start_queue(ndev);
643
644 return ret;
645}
646
647/* free Tx skb function */
648static int sh_eth_txfree(struct net_device *ndev)
649{
650 struct sh_eth_private *mdp = netdev_priv(ndev);
651 struct sh_eth_txdesc *txdesc;
652 int freeNum = 0;
653 int entry = 0;
654
655 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
656 entry = mdp->dirty_tx % TX_RING_SIZE;
657 txdesc = &mdp->tx_ring[entry];
71557a37 658 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 659 break;
660 /* Free the original skb. */
661 if (mdp->tx_skbuff[entry]) {
662 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
663 mdp->tx_skbuff[entry] = NULL;
664 freeNum++;
665 }
71557a37 666 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 667 if (entry >= TX_RING_SIZE - 1)
71557a37 668 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 669
670 mdp->stats.tx_packets++;
671 mdp->stats.tx_bytes += txdesc->buffer_length;
672 }
673 return freeNum;
674}
675
676/* Packet receive function */
677static int sh_eth_rx(struct net_device *ndev)
678{
679 struct sh_eth_private *mdp = netdev_priv(ndev);
680 struct sh_eth_rxdesc *rxdesc;
681
682 int entry = mdp->cur_rx % RX_RING_SIZE;
683 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
684 struct sk_buff *skb;
685 u16 pkt_len = 0;
380af9e3 686 u32 desc_status;
86a74ff2
NI		 687
688 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 689 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
690 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 691 pkt_len = rxdesc->frame_length;
692
693 if (--boguscnt < 0)
694 break;
695
696 if (!(desc_status & RDFEND))
697 mdp->stats.rx_length_errors++;
698
699 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
700 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
701 mdp->stats.rx_errors++;
702 if (desc_status & RD_RFS1)
703 mdp->stats.rx_crc_errors++;
704 if (desc_status & RD_RFS2)
705 mdp->stats.rx_frame_errors++;
706 if (desc_status & RD_RFS3)
707 mdp->stats.rx_length_errors++;
708 if (desc_status & RD_RFS4)
709 mdp->stats.rx_length_errors++;
710 if (desc_status & RD_RFS6)
711 mdp->stats.rx_missed_errors++;
712 if (desc_status & RD_RFS10)
713 mdp->stats.rx_over_errors++;
714 } else {
380af9e3
YS		 715 if (!mdp->cd->hw_swap)
716 sh_eth_soft_swap(
717 phys_to_virt(ALIGN(rxdesc->addr, 4)),
718 pkt_len + 2);
86a74ff2
NI		 719 skb = mdp->rx_skbuff[entry];
720 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 721 if (mdp->cd->rpadir)
722 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 723 skb_put(skb, pkt_len);
724 skb->protocol = eth_type_trans(skb, ndev);
725 netif_rx(skb);
86a74ff2
NI		 726 mdp->stats.rx_packets++;
727 mdp->stats.rx_bytes += pkt_len;
728 }
71557a37 729 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 730 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 731 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 732 }
733
734 /* Refill the Rx ring buffers. */
735 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
736 entry = mdp->dirty_rx % RX_RING_SIZE;
737 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 738 /* The size of the buffer is 16 byte boundary. */
0029d64a 739 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 740
86a74ff2
NI		 741 if (mdp->rx_skbuff[entry] == NULL) {
742 skb = dev_alloc_skb(mdp->rx_buf_sz);
743 mdp->rx_skbuff[entry] = skb;
744 if (skb == NULL)
745 break; /* Better luck next round. */
e88aae7b
YS		 746 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
747 DMA_FROM_DEVICE);
86a74ff2 748 skb->dev = ndev;
380af9e3
YS		 749 sh_eth_set_receive_align(skb);
750
b0ca2a21 751 skb->ip_summed = CHECKSUM_NONE;
0029d64a 752 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 753 }
86a74ff2
NI		 754 if (entry >= RX_RING_SIZE - 1)
755 rxdesc->status |=
71557a37 756 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 757 else
758 rxdesc->status |=
71557a37 759 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 760 }
761
762 /* Restart Rx engine if stopped. */
763 /* If we don't need to check status, don't. -KDU */
b0ca2a21
NI		 764 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
765 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
86a74ff2
NI		 766
767 return 0;
768}
769
770/* error control function */
771static void sh_eth_error(struct net_device *ndev, int intr_status)
772{
773 struct sh_eth_private *mdp = netdev_priv(ndev);
774 u32 ioaddr = ndev->base_addr;
775 u32 felic_stat;
380af9e3
YS		 776 u32 link_stat;
777 u32 mask;
86a74ff2
NI		 778
779 if (intr_status & EESR_ECI) {
780 felic_stat = ctrl_inl(ioaddr + ECSR);
781 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
782 if (felic_stat & ECSR_ICD)
783 mdp->stats.tx_carrier_errors++;
784 if (felic_stat & ECSR_LCHNG) {
785 /* Link Changed */
4923576b 786 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 787 if (mdp->link == PHY_DOWN)
788 link_stat = 0;
789 else
790 link_stat = PHY_ST_LINK;
791 } else {
792 link_stat = (ctrl_inl(ioaddr + PSR));
4923576b
YS		 793 if (mdp->ether_link_active_low)
794 link_stat = ~link_stat;
380af9e3 795 }
86a74ff2
NI		 796 if (!(link_stat & PHY_ST_LINK)) {
797 /* Link Down : disable tx and rx */
798 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
799 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
800 } else {
801 /* Link Up */
802 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
803 ~DMAC_M_ECI, ioaddr + EESIPR);
804 /*clear int */
805 ctrl_outl(ctrl_inl(ioaddr + ECSR),
806 ioaddr + ECSR);
807 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
808 DMAC_M_ECI, ioaddr + EESIPR);
809 /* enable tx and rx */
810 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
811 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
812 }
813 }
814 }
815
816 if (intr_status & EESR_TWB) {
817 /* Write buck end. unused write back interrupt */
818 if (intr_status & EESR_TABT) /* Transmit Abort int */
819 mdp->stats.tx_aborted_errors++;
820 }
821
822 if (intr_status & EESR_RABT) {
823 /* Receive Abort int */
824 if (intr_status & EESR_RFRMER) {
825 /* Receive Frame Overflow int */
826 mdp->stats.rx_frame_errors++;
380af9e3 827 dev_err(&ndev->dev, "Receive Frame Overflow\n");
86a74ff2
NI		 828 }
829 }
380af9e3
YS		 830
831 if (!mdp->cd->no_ade) {
832 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
833 intr_status & EESR_TFE)
834 mdp->stats.tx_fifo_errors++;
86a74ff2
NI		 835 }
836
837 if (intr_status & EESR_RDE) {
838 /* Receive Descriptor Empty int */
839 mdp->stats.rx_over_errors++;
840
841 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
842 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
380af9e3 843 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2
NI		 844 }
845 if (intr_status & EESR_RFE) {
846 /* Receive FIFO Overflow int */
847 mdp->stats.rx_fifo_errors++;
380af9e3 848 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
86a74ff2 849 }
380af9e3
YS		 850
851 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
852 if (mdp->cd->no_ade)
853 mask &= ~EESR_ADE;
854 if (intr_status & mask) {
86a74ff2
NI		 855 /* Tx error */
856 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
857 /* dmesg */
380af9e3
YS		 858 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
859 intr_status, mdp->cur_tx);
860 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 861 mdp->dirty_tx, (u32) ndev->state, edtrr);
862 /* dirty buffer free */
863 sh_eth_txfree(ndev);
864
865 /* SH7712 BUG */
866 if (edtrr ^ EDTRR_TRNS) {
867 /* tx dma start */
868 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
869 }
870 /* wakeup */
871 netif_wake_queue(ndev);
872 }
873}
874
875static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
876{
877 struct net_device *ndev = netdev;
878 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 879 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 880 irqreturn_t ret = IRQ_NONE;
37c8ae3a 881 u32 ioaddr, intr_status = 0;
86a74ff2
NI		 882
883 ioaddr = ndev->base_addr;
884 spin_lock(&mdp->lock);
885
b0ca2a21 886 /* Get interrpt stat */
86a74ff2
NI		 887 intr_status = ctrl_inl(ioaddr + EESR);
888 /* Clear interrupt */
0e0fde3c
NI		 889 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
890 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 891 cd->tx_check | cd->eesr_err_check)) {
0e0fde3c
NI		 892 ctrl_outl(intr_status, ioaddr + EESR);
893 ret = IRQ_HANDLED;
894 } else
895 goto other_irq;
86a74ff2 896
b0ca2a21
NI		 897 if (intr_status & (EESR_FRC | /* Frame recv*/
898 EESR_RMAF | /* Multi cast address recv*/
899 EESR_RRF | /* Bit frame recv */
900 EESR_RTLF | /* Long frame recv*/
901 EESR_RTSF | /* short frame recv */
902 EESR_PRE | /* PHY-LSI recv error */
903 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 904 sh_eth_rx(ndev);
b0ca2a21 905 }
86a74ff2 906
b0ca2a21 907 /* Tx Check */
380af9e3 908 if (intr_status & cd->tx_check) {
86a74ff2
NI		 909 sh_eth_txfree(ndev);
910 netif_wake_queue(ndev);
911 }
912
380af9e3 913 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 914 sh_eth_error(ndev, intr_status);
915
0e0fde3c 916other_irq:
86a74ff2
NI		 917 spin_unlock(&mdp->lock);
918
0e0fde3c 919 return ret;
86a74ff2
NI		 920}
921
922static void sh_eth_timer(unsigned long data)
923{
924 struct net_device *ndev = (struct net_device *)data;
925 struct sh_eth_private *mdp = netdev_priv(ndev);
926
927 mod_timer(&mdp->timer, jiffies + (10 * HZ));
928}
929
930/* PHY state control function */
931static void sh_eth_adjust_link(struct net_device *ndev)
932{
933 struct sh_eth_private *mdp = netdev_priv(ndev);
934 struct phy_device *phydev = mdp->phydev;
935 u32 ioaddr = ndev->base_addr;
936 int new_state = 0;
937
938 if (phydev->link != PHY_DOWN) {
939 if (phydev->duplex != mdp->duplex) {
940 new_state = 1;
941 mdp->duplex = phydev->duplex;
380af9e3
YS		 942 if (mdp->cd->set_duplex)
943 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 944 }
945
946 if (phydev->speed != mdp->speed) {
947 new_state = 1;
948 mdp->speed = phydev->speed;
380af9e3
YS		 949 if (mdp->cd->set_rate)
950 mdp->cd->set_rate(ndev);
86a74ff2
NI		 951 }
952 if (mdp->link == PHY_DOWN) {
953 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
954 | ECMR_DM, ioaddr + ECMR);
955 new_state = 1;
956 mdp->link = phydev->link;
86a74ff2
NI		 957 }
958 } else if (mdp->link) {
959 new_state = 1;
960 mdp->link = PHY_DOWN;
961 mdp->speed = 0;
962 mdp->duplex = -1;
86a74ff2
NI		 963 }
964
965 if (new_state)
966 phy_print_status(phydev);
967}
968
969/* PHY init function */
970static int sh_eth_phy_init(struct net_device *ndev)
971{
972 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 973 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 974 struct phy_device *phydev = NULL;
975
fb28ad35 976 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 977 mdp->mii_bus->id , mdp->phy_id);
978
979 mdp->link = PHY_DOWN;
980 mdp->speed = 0;
981 mdp->duplex = -1;
982
983 /* Try connect to PHY */
984 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
985 0, PHY_INTERFACE_MODE_MII);
986 if (IS_ERR(phydev)) {
987 dev_err(&ndev->dev, "phy_connect failed\n");
988 return PTR_ERR(phydev);
989 }
380af9e3 990
86a74ff2 991 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 992 phydev->addr, phydev->drv->name);
86a74ff2
NI		 993
994 mdp->phydev = phydev;
995
996 return 0;
997}
998
999/* PHY control start function */
1000static int sh_eth_phy_start(struct net_device *ndev)
1001{
1002 struct sh_eth_private *mdp = netdev_priv(ndev);
1003 int ret;
1004
1005 ret = sh_eth_phy_init(ndev);
1006 if (ret)
1007 return ret;
1008
1009 /* reset phy - this also wakes it from PDOWN */
1010 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1011 phy_start(mdp->phydev);
1012
1013 return 0;
1014}
1015
1016/* network device open function */
1017static int sh_eth_open(struct net_device *ndev)
1018{
1019 int ret = 0;
1020 struct sh_eth_private *mdp = netdev_priv(ndev);
1021
bcd5149d
MD		 1022 pm_runtime_get_sync(&mdp->pdev->dev);
1023
a0607fd3 1024 ret = request_irq(ndev->irq, sh_eth_interrupt,
0e0fde3c
NI		 1025#if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1026 IRQF_SHARED,
1027#else
1028 0,
1029#endif
1030 ndev->name, ndev);
86a74ff2 1031 if (ret) {
380af9e3 1032 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1033 return ret;
1034 }
1035
1036 /* Descriptor set */
1037 ret = sh_eth_ring_init(ndev);
1038 if (ret)
1039 goto out_free_irq;
1040
1041 /* device init */
1042 ret = sh_eth_dev_init(ndev);
1043 if (ret)
1044 goto out_free_irq;
1045
1046 /* PHY control start*/
1047 ret = sh_eth_phy_start(ndev);
1048 if (ret)
1049 goto out_free_irq;
1050
1051 /* Set the timer to check for link beat. */
1052 init_timer(&mdp->timer);
1053 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1054 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1055
1056 return ret;
1057
1058out_free_irq:
1059 free_irq(ndev->irq, ndev);
bcd5149d 1060 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1061 return ret;
1062}
1063
1064/* Timeout function */
1065static void sh_eth_tx_timeout(struct net_device *ndev)
1066{
1067 struct sh_eth_private *mdp = netdev_priv(ndev);
1068 u32 ioaddr = ndev->base_addr;
1069 struct sh_eth_rxdesc *rxdesc;
1070 int i;
1071
1072 netif_stop_queue(ndev);
1073
1074 /* worning message out. */
1075 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
1076 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
1077
1078 /* tx_errors count up */
1079 mdp->stats.tx_errors++;
1080
1081 /* timer off */
1082 del_timer_sync(&mdp->timer);
1083
1084 /* Free all the skbuffs in the Rx queue. */
1085 for (i = 0; i < RX_RING_SIZE; i++) {
1086 rxdesc = &mdp->rx_ring[i];
1087 rxdesc->status = 0;
1088 rxdesc->addr = 0xBADF00D0;
1089 if (mdp->rx_skbuff[i])
1090 dev_kfree_skb(mdp->rx_skbuff[i]);
1091 mdp->rx_skbuff[i] = NULL;
1092 }
1093 for (i = 0; i < TX_RING_SIZE; i++) {
1094 if (mdp->tx_skbuff[i])
1095 dev_kfree_skb(mdp->tx_skbuff[i]);
1096 mdp->tx_skbuff[i] = NULL;
1097 }
1098
1099 /* device init */
1100 sh_eth_dev_init(ndev);
1101
1102 /* timer on */
1103 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1104 add_timer(&mdp->timer);
1105}
1106
1107/* Packet transmit function */
1108static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1109{
1110 struct sh_eth_private *mdp = netdev_priv(ndev);
1111 struct sh_eth_txdesc *txdesc;
1112 u32 entry;
fb5e2f9b 1113 unsigned long flags;
86a74ff2
NI		 1114
1115 spin_lock_irqsave(&mdp->lock, flags);
1116 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1117 if (!sh_eth_txfree(ndev)) {
1118 netif_stop_queue(ndev);
1119 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1120 return NETDEV_TX_BUSY;
86a74ff2
NI		 1121 }
1122 }
1123 spin_unlock_irqrestore(&mdp->lock, flags);
1124
1125 entry = mdp->cur_tx % TX_RING_SIZE;
1126 mdp->tx_skbuff[entry] = skb;
1127 txdesc = &mdp->tx_ring[entry];
0029d64a 1128 txdesc->addr = virt_to_phys(skb->data);
86a74ff2 1129 /* soft swap. */
380af9e3
YS		 1130 if (!mdp->cd->hw_swap)
1131 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1132 skb->len + 2);
86a74ff2
NI		 1133 /* write back */
1134 __flush_purge_region(skb->data, skb->len);
1135 if (skb->len < ETHERSMALL)
1136 txdesc->buffer_length = ETHERSMALL;
1137 else
1138 txdesc->buffer_length = skb->len;
1139
1140 if (entry >= TX_RING_SIZE - 1)
71557a37 1141 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1142 else
71557a37 1143 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1144
1145 mdp->cur_tx++;
1146
b0ca2a21
NI		 1147 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1148 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1149
86a74ff2
NI		 1150 ndev->trans_start = jiffies;
1151
6ed10654 1152 return NETDEV_TX_OK;
86a74ff2
NI		 1153}
1154
1155/* device close function */
1156static int sh_eth_close(struct net_device *ndev)
1157{
1158 struct sh_eth_private *mdp = netdev_priv(ndev);
1159 u32 ioaddr = ndev->base_addr;
1160 int ringsize;
1161
1162 netif_stop_queue(ndev);
1163
1164 /* Disable interrupts by clearing the interrupt mask. */
1165 ctrl_outl(0x0000, ioaddr + EESIPR);
1166
1167 /* Stop the chip's Tx and Rx processes. */
1168 ctrl_outl(0, ioaddr + EDTRR);
1169 ctrl_outl(0, ioaddr + EDRRR);
1170
1171 /* PHY Disconnect */
1172 if (mdp->phydev) {
1173 phy_stop(mdp->phydev);
1174 phy_disconnect(mdp->phydev);
1175 }
1176
1177 free_irq(ndev->irq, ndev);
1178
1179 del_timer_sync(&mdp->timer);
1180
1181 /* Free all the skbuffs in the Rx queue. */
1182 sh_eth_ring_free(ndev);
1183
1184 /* free DMA buffer */
1185 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1186 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1187
1188 /* free DMA buffer */
1189 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1190 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1191
bcd5149d
MD		 1192 pm_runtime_put_sync(&mdp->pdev->dev);
1193
86a74ff2
NI		 1194 return 0;
1195}
1196
1197static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1198{
1199 struct sh_eth_private *mdp = netdev_priv(ndev);
1200 u32 ioaddr = ndev->base_addr;
1201
bcd5149d
MD		 1202 pm_runtime_get_sync(&mdp->pdev->dev);
1203
86a74ff2
NI		 1204 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1205 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1206 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1207 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1208 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1209 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
b0ca2a21
NI		 1210#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1211 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1212 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1213 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1214 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1215#else
86a74ff2
NI		 1216 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1217 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
b0ca2a21 1218#endif
bcd5149d
MD		 1219 pm_runtime_put_sync(&mdp->pdev->dev);
1220
86a74ff2
NI		 1221 return &mdp->stats;
1222}
1223
1224/* ioctl to device funciotn*/
1225static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1226 int cmd)
1227{
1228 struct sh_eth_private *mdp = netdev_priv(ndev);
1229 struct phy_device *phydev = mdp->phydev;
1230
1231 if (!netif_running(ndev))
1232 return -EINVAL;
1233
1234 if (!phydev)
1235 return -ENODEV;
1236
1237 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1238}
1239
380af9e3 1240#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1241/* Multicast reception directions set */
1242static void sh_eth_set_multicast_list(struct net_device *ndev)
1243{
1244 u32 ioaddr = ndev->base_addr;
1245
1246 if (ndev->flags & IFF_PROMISC) {
1247 /* Set promiscuous. */
1248 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1249 ioaddr + ECMR);
1250 } else {
1251 /* Normal, unicast/broadcast-only mode. */
1252 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1253 ioaddr + ECMR);
1254 }
1255}
1256
1257/* SuperH's TSU register init function */
1258static void sh_eth_tsu_init(u32 ioaddr)
1259{
1260 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1261 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1262 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1263 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1264 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1265 ctrl_outl(0, ioaddr + TSU_PRISL0);
1266 ctrl_outl(0, ioaddr + TSU_PRISL1);
1267 ctrl_outl(0, ioaddr + TSU_FWSL0);
1268 ctrl_outl(0, ioaddr + TSU_FWSL1);
1269 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
b0ca2a21
NI		 1270#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1271 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1272 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1273#else
86a74ff2
NI		 1274 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1275 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
b0ca2a21 1276#endif
86a74ff2
NI		 1277 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1278 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1279 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1280 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1281 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1282 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1283 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1284}
380af9e3 1285#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1286
1287/* MDIO bus release function */
1288static int sh_mdio_release(struct net_device *ndev)
1289{
1290 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1291
1292 /* unregister mdio bus */
1293 mdiobus_unregister(bus);
1294
1295 /* remove mdio bus info from net_device */
1296 dev_set_drvdata(&ndev->dev, NULL);
1297
1298 /* free bitbang info */
1299 free_mdio_bitbang(bus);
1300
1301 return 0;
1302}
1303
1304/* MDIO bus init function */
1305static int sh_mdio_init(struct net_device *ndev, int id)
1306{
1307 int ret, i;
1308 struct bb_info *bitbang;
1309 struct sh_eth_private *mdp = netdev_priv(ndev);
1310
1311 /* create bit control struct for PHY */
1312 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1313 if (!bitbang) {
1314 ret = -ENOMEM;
1315 goto out;
1316 }
1317
1318 /* bitbang init */
1319 bitbang->addr = ndev->base_addr + PIR;
1320 bitbang->mdi_msk = 0x08;
1321 bitbang->mdo_msk = 0x04;
1322 bitbang->mmd_msk = 0x02;/* MMD */
1323 bitbang->mdc_msk = 0x01;
1324 bitbang->ctrl.ops = &bb_ops;
1325
1326 /* MII contorller setting */
1327 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1328 if (!mdp->mii_bus) {
1329 ret = -ENOMEM;
1330 goto out_free_bitbang;
1331 }
1332
1333 /* Hook up MII support for ethtool */
1334 mdp->mii_bus->name = "sh_mii";
18ee49dd 1335 mdp->mii_bus->parent = &ndev->dev;
fb5e2f9b 1336 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
86a74ff2
NI		 1337
1338 /* PHY IRQ */
1339 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1340 if (!mdp->mii_bus->irq) {
1341 ret = -ENOMEM;
1342 goto out_free_bus;
1343 }
1344
1345 for (i = 0; i < PHY_MAX_ADDR; i++)
1346 mdp->mii_bus->irq[i] = PHY_POLL;
1347
1348 /* regist mdio bus */
1349 ret = mdiobus_register(mdp->mii_bus);
1350 if (ret)
1351 goto out_free_irq;
1352
1353 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1354
1355 return 0;
1356
1357out_free_irq:
1358 kfree(mdp->mii_bus->irq);
1359
1360out_free_bus:
298cf9be 1361 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1362
1363out_free_bitbang:
1364 kfree(bitbang);
1365
1366out:
1367 return ret;
1368}
1369
ebf84eaa
AB		 1370static const struct net_device_ops sh_eth_netdev_ops = {
1371 .ndo_open = sh_eth_open,
1372 .ndo_stop = sh_eth_close,
1373 .ndo_start_xmit = sh_eth_start_xmit,
1374 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1375#if defined(SH_ETH_HAS_TSU)
ebf84eaa 1376 .ndo_set_multicast_list = sh_eth_set_multicast_list,
380af9e3 1377#endif
ebf84eaa
AB		 1378 .ndo_tx_timeout = sh_eth_tx_timeout,
1379 .ndo_do_ioctl = sh_eth_do_ioctl,
1380 .ndo_validate_addr = eth_validate_addr,
1381 .ndo_set_mac_address = eth_mac_addr,
1382 .ndo_change_mtu = eth_change_mtu,
1383};
1384
86a74ff2
NI		 1385static int sh_eth_drv_probe(struct platform_device *pdev)
1386{
1387 int ret, i, devno = 0;
1388 struct resource *res;
1389 struct net_device *ndev = NULL;
1390 struct sh_eth_private *mdp;
71557a37 1391 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1392
1393 /* get base addr */
1394 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1395 if (unlikely(res == NULL)) {
1396 dev_err(&pdev->dev, "invalid resource\n");
1397 ret = -EINVAL;
1398 goto out;
1399 }
1400
1401 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1402 if (!ndev) {
380af9e3 1403 dev_err(&pdev->dev, "Could not allocate device.\n");
86a74ff2
NI		 1404 ret = -ENOMEM;
1405 goto out;
1406 }
1407
1408 /* The sh Ether-specific entries in the device structure. */
1409 ndev->base_addr = res->start;
1410 devno = pdev->id;
1411 if (devno < 0)
1412 devno = 0;
1413
1414 ndev->dma = -1;
cc3c080d 1415 ret = platform_get_irq(pdev, 0);
1416 if (ret < 0) {
86a74ff2
NI		 1417 ret = -ENODEV;
1418 goto out_release;
1419 }
cc3c080d 1420 ndev->irq = ret;
86a74ff2
NI		 1421
1422 SET_NETDEV_DEV(ndev, &pdev->dev);
1423
1424 /* Fill in the fields of the device structure with ethernet values. */
1425 ether_setup(ndev);
1426
1427 mdp = netdev_priv(ndev);
1428 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1429 mdp->pdev = pdev;
1430 pm_runtime_enable(&pdev->dev);
1431 pm_runtime_resume(&pdev->dev);
86a74ff2 1432
71557a37 1433 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1434 /* get PHY ID */
71557a37
YS		 1435 mdp->phy_id = pd->phy;
1436 /* EDMAC endian */
1437 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1438 mdp->no_ether_link = pd->no_ether_link;
1439 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 1440
380af9e3
YS		 1441 /* set cpu data */
1442 mdp->cd = &sh_eth_my_cpu_data;
1443 sh_eth_set_default_cpu_data(mdp->cd);
1444
86a74ff2 1445 /* set function */
ebf84eaa 1446 ndev->netdev_ops = &sh_eth_netdev_ops;
86a74ff2
NI		 1447 ndev->watchdog_timeo = TX_TIMEOUT;
1448
1449 mdp->post_rx = POST_RX >> (devno << 1);
1450 mdp->post_fw = POST_FW >> (devno << 1);
1451
1452 /* read and set MAC address */
748031f9 1453 read_mac_address(ndev, pd->mac_addr);
86a74ff2
NI		 1454
1455 /* First device only init */
1456 if (!devno) {
380af9e3
YS		 1457 if (mdp->cd->chip_reset)
1458 mdp->cd->chip_reset(ndev);
86a74ff2 1459
380af9e3 1460#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1461 /* TSU init (Init only)*/
1462 sh_eth_tsu_init(SH_TSU_ADDR);
71557a37 1463#endif
86a74ff2
NI		 1464 }
1465
1466 /* network device register */
1467 ret = register_netdev(ndev);
1468 if (ret)
1469 goto out_release;
1470
1471 /* mdio bus init */
1472 ret = sh_mdio_init(ndev, pdev->id);
1473 if (ret)
1474 goto out_unregister;
1475
6cd9b49d
HS		 1476 /* print device infomation */
1477 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1478 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 1479
1480 platform_set_drvdata(pdev, ndev);
1481
1482 return ret;
1483
1484out_unregister:
1485 unregister_netdev(ndev);
1486
1487out_release:
1488 /* net_dev free */
1489 if (ndev)
1490 free_netdev(ndev);
1491
1492out:
1493 return ret;
1494}
1495
1496static int sh_eth_drv_remove(struct platform_device *pdev)
1497{
1498 struct net_device *ndev = platform_get_drvdata(pdev);
1499
1500 sh_mdio_release(ndev);
1501 unregister_netdev(ndev);
1502 flush_scheduled_work();
bcd5149d 1503 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 1504 free_netdev(ndev);
1505 platform_set_drvdata(pdev, NULL);
1506
1507 return 0;
1508}
1509
bcd5149d
MD		 1510static int sh_eth_runtime_nop(struct device *dev)
1511{
1512 /*
1513 * Runtime PM callback shared between ->runtime_suspend()
1514 * and ->runtime_resume(). Simply returns success.
1515 *
1516 * This driver re-initializes all registers after
1517 * pm_runtime_get_sync() anyway so there is no need
1518 * to save and restore registers here.
1519 */
1520 return 0;
1521}
1522
1523static struct dev_pm_ops sh_eth_dev_pm_ops = {
1524 .runtime_suspend = sh_eth_runtime_nop,
1525 .runtime_resume = sh_eth_runtime_nop,
1526};
1527
86a74ff2
NI		 1528static struct platform_driver sh_eth_driver = {
1529 .probe = sh_eth_drv_probe,
1530 .remove = sh_eth_drv_remove,
1531 .driver = {
1532 .name = CARDNAME,
bcd5149d 1533 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1534 },
1535};
1536
1537static int __init sh_eth_init(void)
1538{
1539 return platform_driver_register(&sh_eth_driver);
1540}
1541
1542static void __exit sh_eth_cleanup(void)
1543{
1544 platform_driver_unregister(&sh_eth_driver);
1545}
1546
1547module_init(sh_eth_init);
1548module_exit(sh_eth_cleanup);
1549
1550MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1551MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1552MODULE_LICENSE("GPL v2");
Clone of davem's net-next-2.6 tree