]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/sh_eth.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
netsched: Allow var_sk_bound_if meta to work on all namespaces
[net-next-2.6.git] / drivers / net / sh_eth.c
CommitLineData
86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2
NI		 23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/netdevice.h>
30#include <linux/phy.h>
31#include <linux/cache.h>
32#include <linux/io.h>
bcd5149d 33#include <linux/pm_runtime.h>
f568a926 34#include <asm/cacheflush.h>
86a74ff2
NI		 35
36#include "sh_eth.h"
37
380af9e3 38/* There is CPU dependent code */
65ac8851
YS		 39#if defined(CONFIG_CPU_SUBTYPE_SH7724)
40#define SH_ETH_RESET_DEFAULT 1
41static void sh_eth_set_duplex(struct net_device *ndev)
42{
43 struct sh_eth_private *mdp = netdev_priv(ndev);
44 u32 ioaddr = ndev->base_addr;
45
46 if (mdp->duplex) /* Full */
47 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
48 else /* Half */
49 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
50}
51
52static void sh_eth_set_rate(struct net_device *ndev)
53{
54 struct sh_eth_private *mdp = netdev_priv(ndev);
55 u32 ioaddr = ndev->base_addr;
56
57 switch (mdp->speed) {
58 case 10: /* 10BASE */
59 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_RTM, ioaddr + ECMR);
60 break;
61 case 100:/* 100BASE */
62 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_RTM, ioaddr + ECMR);
63 break;
64 default:
65 break;
66 }
67}
68
69/* SH7724 */
70static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
71 .set_duplex = sh_eth_set_duplex,
72 .set_rate = sh_eth_set_rate,
73
74 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
75 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
76 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
77
78 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
79 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
80 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
81 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
82
83 .apr = 1,
84 .mpr = 1,
85 .tpauser = 1,
86 .hw_swap = 1,
87};
88
89#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 90#define SH_ETH_HAS_TSU 1
91static void sh_eth_chip_reset(struct net_device *ndev)
92{
93 /* reset device */
94 ctrl_outl(ARSTR_ARSTR, ARSTR);
95 mdelay(1);
96}
97
98static void sh_eth_reset(struct net_device *ndev)
99{
100 u32 ioaddr = ndev->base_addr;
101 int cnt = 100;
102
103 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
104 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
105 while (cnt > 0) {
106 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
107 break;
108 mdelay(1);
109 cnt--;
110 }
111 if (cnt < 0)
112 printk(KERN_ERR "Device reset fail\n");
113
114 /* Table Init */
115 ctrl_outl(0x0, ioaddr + TDLAR);
116 ctrl_outl(0x0, ioaddr + TDFAR);
117 ctrl_outl(0x0, ioaddr + TDFXR);
118 ctrl_outl(0x0, ioaddr + TDFFR);
119 ctrl_outl(0x0, ioaddr + RDLAR);
120 ctrl_outl(0x0, ioaddr + RDFAR);
121 ctrl_outl(0x0, ioaddr + RDFXR);
122 ctrl_outl(0x0, ioaddr + RDFFR);
123}
124
125static void sh_eth_set_duplex(struct net_device *ndev)
126{
127 struct sh_eth_private *mdp = netdev_priv(ndev);
128 u32 ioaddr = ndev->base_addr;
129
130 if (mdp->duplex) /* Full */
131 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM, ioaddr + ECMR);
132 else /* Half */
133 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM, ioaddr + ECMR);
134}
135
136static void sh_eth_set_rate(struct net_device *ndev)
137{
138 struct sh_eth_private *mdp = netdev_priv(ndev);
139 u32 ioaddr = ndev->base_addr;
140
141 switch (mdp->speed) {
142 case 10: /* 10BASE */
143 ctrl_outl(GECMR_10, ioaddr + GECMR);
144 break;
145 case 100:/* 100BASE */
146 ctrl_outl(GECMR_100, ioaddr + GECMR);
147 break;
148 case 1000: /* 1000BASE */
149 ctrl_outl(GECMR_1000, ioaddr + GECMR);
150 break;
151 default:
152 break;
153 }
154}
155
156/* sh7763 */
157static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
158 .chip_reset = sh_eth_chip_reset,
159 .set_duplex = sh_eth_set_duplex,
160 .set_rate = sh_eth_set_rate,
161
162 .ecsr_value = ECSR_ICD | ECSR_MPD,
163 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
164 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
165
166 .tx_check = EESR_TC1 | EESR_FTC,
167 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
168 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
169 EESR_ECI,
170 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
171 EESR_TFE,
172
173 .apr = 1,
174 .mpr = 1,
175 .tpauser = 1,
176 .bculr = 1,
177 .hw_swap = 1,
178 .rpadir = 1,
179 .no_trimd = 1,
180 .no_ade = 1,
181};
182
183#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
184#define SH_ETH_RESET_DEFAULT 1
185static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
186 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
187
188 .apr = 1,
189 .mpr = 1,
190 .tpauser = 1,
191 .hw_swap = 1,
192};
193#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
194#define SH_ETH_RESET_DEFAULT 1
195#define SH_ETH_HAS_TSU 1
196static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
197 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
198};
199#endif
200
201static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
202{
203 if (!cd->ecsr_value)
204 cd->ecsr_value = DEFAULT_ECSR_INIT;
205
206 if (!cd->ecsipr_value)
207 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
208
209 if (!cd->fcftr_value)
210 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
211 DEFAULT_FIFO_F_D_RFD;
212
213 if (!cd->fdr_value)
214 cd->fdr_value = DEFAULT_FDR_INIT;
215
216 if (!cd->rmcr_value)
217 cd->rmcr_value = DEFAULT_RMCR_VALUE;
218
219 if (!cd->tx_check)
220 cd->tx_check = DEFAULT_TX_CHECK;
221
222 if (!cd->eesr_err_check)
223 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
224
225 if (!cd->tx_error_check)
226 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
227}
228
229#if defined(SH_ETH_RESET_DEFAULT)
230/* Chip Reset */
231static void sh_eth_reset(struct net_device *ndev)
232{
233 u32 ioaddr = ndev->base_addr;
234
235 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
236 mdelay(3);
237 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
238}
239#endif
240
241#if defined(CONFIG_CPU_SH4)
242static void sh_eth_set_receive_align(struct sk_buff *skb)
243{
244 int reserve;
245
246 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
247 if (reserve)
248 skb_reserve(skb, reserve);
249}
250#else
251static void sh_eth_set_receive_align(struct sk_buff *skb)
252{
253 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
254}
255#endif
256
257
71557a37
YS		 258/* CPU <-> EDMAC endian convert */
259static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
260{
261 switch (mdp->edmac_endian) {
262 case EDMAC_LITTLE_ENDIAN:
263 return cpu_to_le32(x);
264 case EDMAC_BIG_ENDIAN:
265 return cpu_to_be32(x);
266 }
267 return x;
268}
269
270static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
271{
272 switch (mdp->edmac_endian) {
273 case EDMAC_LITTLE_ENDIAN:
274 return le32_to_cpu(x);
275 case EDMAC_BIG_ENDIAN:
276 return be32_to_cpu(x);
277 }
278 return x;
279}
280
86a74ff2
NI		 281/*
282 * Program the hardware MAC address from dev->dev_addr.
283 */
284static void update_mac_address(struct net_device *ndev)
285{
286 u32 ioaddr = ndev->base_addr;
287
288 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
289 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
290 ioaddr + MAHR);
291 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
292 ioaddr + MALR);
293}
294
295/*
296 * Get MAC address from SuperH MAC address register
297 *
298 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
299 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
300 * When you want use this device, you must set MAC address in bootloader.
301 *
302 */
748031f9 303static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2
NI		 304{
305 u32 ioaddr = ndev->base_addr;
306
748031f9
MD		 307 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
308 memcpy(ndev->dev_addr, mac, 6);
309 } else {
310 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
311 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
312 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
313 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
314 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
315 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
316 }
86a74ff2
NI		 317}
318
319struct bb_info {
320 struct mdiobb_ctrl ctrl;
321 u32 addr;
322 u32 mmd_msk;/* MMD */
323 u32 mdo_msk;
324 u32 mdi_msk;
325 u32 mdc_msk;
326};
327
328/* PHY bit set */
329static void bb_set(u32 addr, u32 msk)
330{
331 ctrl_outl(ctrl_inl(addr) | msk, addr);
332}
333
334/* PHY bit clear */
335static void bb_clr(u32 addr, u32 msk)
336{
337 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
338}
339
340/* PHY bit read */
341static int bb_read(u32 addr, u32 msk)
342{
343 return (ctrl_inl(addr) & msk) != 0;
344}
345
346/* Data I/O pin control */
347static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
348{
349 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
350 if (bit)
351 bb_set(bitbang->addr, bitbang->mmd_msk);
352 else
353 bb_clr(bitbang->addr, bitbang->mmd_msk);
354}
355
356/* Set bit data*/
357static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
358{
359 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
360
361 if (bit)
362 bb_set(bitbang->addr, bitbang->mdo_msk);
363 else
364 bb_clr(bitbang->addr, bitbang->mdo_msk);
365}
366
367/* Get bit data*/
368static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
369{
370 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
371 return bb_read(bitbang->addr, bitbang->mdi_msk);
372}
373
374/* MDC pin control */
375static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
376{
377 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
378
379 if (bit)
380 bb_set(bitbang->addr, bitbang->mdc_msk);
381 else
382 bb_clr(bitbang->addr, bitbang->mdc_msk);
383}
384
385/* mdio bus control struct */
386static struct mdiobb_ops bb_ops = {
387 .owner = THIS_MODULE,
388 .set_mdc = sh_mdc_ctrl,
389 .set_mdio_dir = sh_mmd_ctrl,
390 .set_mdio_data = sh_set_mdio,
391 .get_mdio_data = sh_get_mdio,
392};
393
86a74ff2
NI		 394/* free skb and descriptor buffer */
395static void sh_eth_ring_free(struct net_device *ndev)
396{
397 struct sh_eth_private *mdp = netdev_priv(ndev);
398 int i;
399
400 /* Free Rx skb ringbuffer */
401 if (mdp->rx_skbuff) {
402 for (i = 0; i < RX_RING_SIZE; i++) {
403 if (mdp->rx_skbuff[i])
404 dev_kfree_skb(mdp->rx_skbuff[i]);
405 }
406 }
407 kfree(mdp->rx_skbuff);
408
409 /* Free Tx skb ringbuffer */
410 if (mdp->tx_skbuff) {
411 for (i = 0; i < TX_RING_SIZE; i++) {
412 if (mdp->tx_skbuff[i])
413 dev_kfree_skb(mdp->tx_skbuff[i]);
414 }
415 }
416 kfree(mdp->tx_skbuff);
417}
418
419/* format skb and descriptor buffer */
420static void sh_eth_ring_format(struct net_device *ndev)
421{
380af9e3 422 u32 ioaddr = ndev->base_addr;
86a74ff2
NI		 423 struct sh_eth_private *mdp = netdev_priv(ndev);
424 int i;
425 struct sk_buff *skb;
426 struct sh_eth_rxdesc *rxdesc = NULL;
427 struct sh_eth_txdesc *txdesc = NULL;
428 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
429 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
430
431 mdp->cur_rx = mdp->cur_tx = 0;
432 mdp->dirty_rx = mdp->dirty_tx = 0;
433
434 memset(mdp->rx_ring, 0, rx_ringsize);
435
436 /* build Rx ring buffer */
437 for (i = 0; i < RX_RING_SIZE; i++) {
438 /* skb */
439 mdp->rx_skbuff[i] = NULL;
440 skb = dev_alloc_skb(mdp->rx_buf_sz);
441 mdp->rx_skbuff[i] = skb;
442 if (skb == NULL)
443 break;
e88aae7b
YS		 444 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
445 DMA_FROM_DEVICE);
b0ca2a21 446 skb->dev = ndev; /* Mark as being used by this device. */
380af9e3
YS		 447 sh_eth_set_receive_align(skb);
448
86a74ff2
NI		 449 /* RX descriptor */
450 rxdesc = &mdp->rx_ring[i];
0029d64a 451 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 452 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 453
454 /* The size of the buffer is 16 byte boundary. */
0029d64a 455 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 456 /* Rx descriptor address set */
457 if (i == 0) {
0029d64a 458 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDLAR);
b0ca2a21 459#if defined(CONFIG_CPU_SUBTYPE_SH7763)
0029d64a 460 ctrl_outl(mdp->rx_desc_dma, ioaddr + RDFAR);
b0ca2a21
NI		 461#endif
462 }
86a74ff2
NI		 463 }
464
465 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
466
467 /* Mark the last entry as wrapping the ring. */
71557a37 468 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 469
470 memset(mdp->tx_ring, 0, tx_ringsize);
471
472 /* build Tx ring buffer */
473 for (i = 0; i < TX_RING_SIZE; i++) {
474 mdp->tx_skbuff[i] = NULL;
475 txdesc = &mdp->tx_ring[i];
71557a37 476 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 477 txdesc->buffer_length = 0;
b0ca2a21 478 if (i == 0) {
71557a37 479 /* Tx descriptor address set */
0029d64a 480 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDLAR);
b0ca2a21 481#if defined(CONFIG_CPU_SUBTYPE_SH7763)
0029d64a 482 ctrl_outl(mdp->tx_desc_dma, ioaddr + TDFAR);
b0ca2a21
NI		 483#endif
484 }
86a74ff2
NI		 485 }
486
71557a37 487 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 488}
489
490/* Get skb and descriptor buffer */
491static int sh_eth_ring_init(struct net_device *ndev)
492{
493 struct sh_eth_private *mdp = netdev_priv(ndev);
494 int rx_ringsize, tx_ringsize, ret = 0;
495
496 /*
497 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
498 * card needs room to do 8 byte alignment, +2 so we can reserve
499 * the first 2 bytes, and +16 gets room for the status word from the
500 * card.
501 */
502 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
503 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
504
505 /* Allocate RX and TX skb rings */
506 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
507 GFP_KERNEL);
508 if (!mdp->rx_skbuff) {
380af9e3 509 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 510 ret = -ENOMEM;
511 return ret;
512 }
513
514 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
515 GFP_KERNEL);
516 if (!mdp->tx_skbuff) {
380af9e3 517 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 518 ret = -ENOMEM;
519 goto skb_ring_free;
520 }
521
522 /* Allocate all Rx descriptors. */
523 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
524 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
525 GFP_KERNEL);
526
527 if (!mdp->rx_ring) {
380af9e3
YS		 528 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
529 rx_ringsize);
86a74ff2
NI		 530 ret = -ENOMEM;
531 goto desc_ring_free;
532 }
533
534 mdp->dirty_rx = 0;
535
536 /* Allocate all Tx descriptors. */
537 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
538 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
539 GFP_KERNEL);
540 if (!mdp->tx_ring) {
380af9e3
YS		 541 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
542 tx_ringsize);
86a74ff2
NI		 543 ret = -ENOMEM;
544 goto desc_ring_free;
545 }
546 return ret;
547
548desc_ring_free:
549 /* free DMA buffer */
550 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
551
552skb_ring_free:
553 /* Free Rx and Tx skb ring buffer */
554 sh_eth_ring_free(ndev);
555
556 return ret;
557}
558
559static int sh_eth_dev_init(struct net_device *ndev)
560{
561 int ret = 0;
562 struct sh_eth_private *mdp = netdev_priv(ndev);
563 u32 ioaddr = ndev->base_addr;
564 u_int32_t rx_int_var, tx_int_var;
565 u32 val;
566
567 /* Soft Reset */
568 sh_eth_reset(ndev);
569
b0ca2a21
NI		 570 /* Descriptor format */
571 sh_eth_ring_format(ndev);
380af9e3
YS		 572 if (mdp->cd->rpadir)
573 ctrl_outl(mdp->cd->rpadir_value, ioaddr + RPADIR);
86a74ff2
NI		 574
575 /* all sh_eth int mask */
576 ctrl_outl(0, ioaddr + EESIPR);
577
380af9e3
YS		 578#if defined(__LITTLE_ENDIAN__)
579 if (mdp->cd->hw_swap)
580 ctrl_outl(EDMR_EL, ioaddr + EDMR);
581 else
b0ca2a21 582#endif
380af9e3 583 ctrl_outl(0, ioaddr + EDMR);
86a74ff2 584
b0ca2a21 585 /* FIFO size set */
380af9e3 586 ctrl_outl(mdp->cd->fdr_value, ioaddr + FDR);
86a74ff2
NI		 587 ctrl_outl(0, ioaddr + TFTR);
588
b0ca2a21 589 /* Frame recv control */
380af9e3 590 ctrl_outl(mdp->cd->rmcr_value, ioaddr + RMCR);
86a74ff2
NI		 591
592 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
593 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
594 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
595
380af9e3
YS		 596 if (mdp->cd->bculr)
597 ctrl_outl(0x800, ioaddr + BCULR); /* Burst sycle set */
b0ca2a21 598
380af9e3 599 ctrl_outl(mdp->cd->fcftr_value, ioaddr + FCFTR);
86a74ff2 600
380af9e3
YS		 601 if (!mdp->cd->no_trimd)
602 ctrl_outl(0, ioaddr + TRIMD);
86a74ff2 603
b0ca2a21
NI		 604 /* Recv frame limit set register */
605 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
86a74ff2
NI		 606
607 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
380af9e3 608 ctrl_outl(mdp->cd->eesipr_value, ioaddr + EESIPR);
86a74ff2
NI		 609
610 /* PAUSE Prohibition */
611 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
612 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
613
614 ctrl_outl(val, ioaddr + ECMR);
b0ca2a21 615
380af9e3
YS		 616 if (mdp->cd->set_rate)
617 mdp->cd->set_rate(ndev);
618
b0ca2a21 619 /* E-MAC Status Register clear */
380af9e3 620 ctrl_outl(mdp->cd->ecsr_value, ioaddr + ECSR);
b0ca2a21
NI		 621
622 /* E-MAC Interrupt Enable register */
380af9e3 623 ctrl_outl(mdp->cd->ecsipr_value, ioaddr + ECSIPR);
86a74ff2
NI		 624
625 /* Set MAC address */
626 update_mac_address(ndev);
627
628 /* mask reset */
380af9e3
YS		 629 if (mdp->cd->apr)
630 ctrl_outl(APR_AP, ioaddr + APR);
631 if (mdp->cd->mpr)
632 ctrl_outl(MPR_MP, ioaddr + MPR);
633 if (mdp->cd->tpauser)
634 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
b0ca2a21 635
86a74ff2
NI		 636 /* Setting the Rx mode will start the Rx process. */
637 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
638
639 netif_start_queue(ndev);
640
641 return ret;
642}
643
644/* free Tx skb function */
645static int sh_eth_txfree(struct net_device *ndev)
646{
647 struct sh_eth_private *mdp = netdev_priv(ndev);
648 struct sh_eth_txdesc *txdesc;
649 int freeNum = 0;
650 int entry = 0;
651
652 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
653 entry = mdp->dirty_tx % TX_RING_SIZE;
654 txdesc = &mdp->tx_ring[entry];
71557a37 655 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 656 break;
657 /* Free the original skb. */
658 if (mdp->tx_skbuff[entry]) {
659 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
660 mdp->tx_skbuff[entry] = NULL;
661 freeNum++;
662 }
71557a37 663 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 664 if (entry >= TX_RING_SIZE - 1)
71557a37 665 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 666
667 mdp->stats.tx_packets++;
668 mdp->stats.tx_bytes += txdesc->buffer_length;
669 }
670 return freeNum;
671}
672
673/* Packet receive function */
674static int sh_eth_rx(struct net_device *ndev)
675{
676 struct sh_eth_private *mdp = netdev_priv(ndev);
677 struct sh_eth_rxdesc *rxdesc;
678
679 int entry = mdp->cur_rx % RX_RING_SIZE;
680 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
681 struct sk_buff *skb;
682 u16 pkt_len = 0;
380af9e3 683 u32 desc_status;
86a74ff2
NI		 684
685 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 686 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
687 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 688 pkt_len = rxdesc->frame_length;
689
690 if (--boguscnt < 0)
691 break;
692
693 if (!(desc_status & RDFEND))
694 mdp->stats.rx_length_errors++;
695
696 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
697 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
698 mdp->stats.rx_errors++;
699 if (desc_status & RD_RFS1)
700 mdp->stats.rx_crc_errors++;
701 if (desc_status & RD_RFS2)
702 mdp->stats.rx_frame_errors++;
703 if (desc_status & RD_RFS3)
704 mdp->stats.rx_length_errors++;
705 if (desc_status & RD_RFS4)
706 mdp->stats.rx_length_errors++;
707 if (desc_status & RD_RFS6)
708 mdp->stats.rx_missed_errors++;
709 if (desc_status & RD_RFS10)
710 mdp->stats.rx_over_errors++;
711 } else {
380af9e3
YS		 712 if (!mdp->cd->hw_swap)
713 sh_eth_soft_swap(
714 phys_to_virt(ALIGN(rxdesc->addr, 4)),
715 pkt_len + 2);
86a74ff2
NI		 716 skb = mdp->rx_skbuff[entry];
717 mdp->rx_skbuff[entry] = NULL;
718 skb_put(skb, pkt_len);
719 skb->protocol = eth_type_trans(skb, ndev);
720 netif_rx(skb);
86a74ff2
NI		 721 mdp->stats.rx_packets++;
722 mdp->stats.rx_bytes += pkt_len;
723 }
71557a37 724 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 725 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 726 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 727 }
728
729 /* Refill the Rx ring buffers. */
730 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
731 entry = mdp->dirty_rx % RX_RING_SIZE;
732 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 733 /* The size of the buffer is 16 byte boundary. */
0029d64a 734 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 735
86a74ff2
NI		 736 if (mdp->rx_skbuff[entry] == NULL) {
737 skb = dev_alloc_skb(mdp->rx_buf_sz);
738 mdp->rx_skbuff[entry] = skb;
739 if (skb == NULL)
740 break; /* Better luck next round. */
e88aae7b
YS		 741 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
742 DMA_FROM_DEVICE);
86a74ff2 743 skb->dev = ndev;
380af9e3
YS		 744 sh_eth_set_receive_align(skb);
745
b0ca2a21 746 skb->ip_summed = CHECKSUM_NONE;
0029d64a 747 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 748 }
86a74ff2
NI		 749 if (entry >= RX_RING_SIZE - 1)
750 rxdesc->status |=
71557a37 751 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 752 else
753 rxdesc->status |=
71557a37 754 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 755 }
756
757 /* Restart Rx engine if stopped. */
758 /* If we don't need to check status, don't. -KDU */
b0ca2a21
NI		 759 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
760 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
86a74ff2
NI		 761
762 return 0;
763}
764
765/* error control function */
766static void sh_eth_error(struct net_device *ndev, int intr_status)
767{
768 struct sh_eth_private *mdp = netdev_priv(ndev);
769 u32 ioaddr = ndev->base_addr;
770 u32 felic_stat;
380af9e3
YS		 771 u32 link_stat;
772 u32 mask;
86a74ff2
NI		 773
774 if (intr_status & EESR_ECI) {
775 felic_stat = ctrl_inl(ioaddr + ECSR);
776 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
777 if (felic_stat & ECSR_ICD)
778 mdp->stats.tx_carrier_errors++;
779 if (felic_stat & ECSR_LCHNG) {
780 /* Link Changed */
4923576b 781 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 782 if (mdp->link == PHY_DOWN)
783 link_stat = 0;
784 else
785 link_stat = PHY_ST_LINK;
786 } else {
787 link_stat = (ctrl_inl(ioaddr + PSR));
4923576b
YS		 788 if (mdp->ether_link_active_low)
789 link_stat = ~link_stat;
380af9e3 790 }
86a74ff2
NI		 791 if (!(link_stat & PHY_ST_LINK)) {
792 /* Link Down : disable tx and rx */
793 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
794 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
795 } else {
796 /* Link Up */
797 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
798 ~DMAC_M_ECI, ioaddr + EESIPR);
799 /*clear int */
800 ctrl_outl(ctrl_inl(ioaddr + ECSR),
801 ioaddr + ECSR);
802 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
803 DMAC_M_ECI, ioaddr + EESIPR);
804 /* enable tx and rx */
805 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
806 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
807 }
808 }
809 }
810
811 if (intr_status & EESR_TWB) {
812 /* Write buck end. unused write back interrupt */
813 if (intr_status & EESR_TABT) /* Transmit Abort int */
814 mdp->stats.tx_aborted_errors++;
815 }
816
817 if (intr_status & EESR_RABT) {
818 /* Receive Abort int */
819 if (intr_status & EESR_RFRMER) {
820 /* Receive Frame Overflow int */
821 mdp->stats.rx_frame_errors++;
380af9e3 822 dev_err(&ndev->dev, "Receive Frame Overflow\n");
86a74ff2
NI		 823 }
824 }
380af9e3
YS		 825
826 if (!mdp->cd->no_ade) {
827 if (intr_status & EESR_ADE && intr_status & EESR_TDE &&
828 intr_status & EESR_TFE)
829 mdp->stats.tx_fifo_errors++;
86a74ff2
NI		 830 }
831
832 if (intr_status & EESR_RDE) {
833 /* Receive Descriptor Empty int */
834 mdp->stats.rx_over_errors++;
835
836 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
837 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
380af9e3 838 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2
NI		 839 }
840 if (intr_status & EESR_RFE) {
841 /* Receive FIFO Overflow int */
842 mdp->stats.rx_fifo_errors++;
380af9e3 843 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
86a74ff2 844 }
380af9e3
YS		 845
846 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
847 if (mdp->cd->no_ade)
848 mask &= ~EESR_ADE;
849 if (intr_status & mask) {
86a74ff2
NI		 850 /* Tx error */
851 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
852 /* dmesg */
380af9e3
YS		 853 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
854 intr_status, mdp->cur_tx);
855 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 856 mdp->dirty_tx, (u32) ndev->state, edtrr);
857 /* dirty buffer free */
858 sh_eth_txfree(ndev);
859
860 /* SH7712 BUG */
861 if (edtrr ^ EDTRR_TRNS) {
862 /* tx dma start */
863 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
864 }
865 /* wakeup */
866 netif_wake_queue(ndev);
867 }
868}
869
870static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
871{
872 struct net_device *ndev = netdev;
873 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 874 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 875 irqreturn_t ret = IRQ_NONE;
37c8ae3a 876 u32 ioaddr, intr_status = 0;
86a74ff2
NI		 877
878 ioaddr = ndev->base_addr;
879 spin_lock(&mdp->lock);
880
b0ca2a21 881 /* Get interrpt stat */
86a74ff2
NI		 882 intr_status = ctrl_inl(ioaddr + EESR);
883 /* Clear interrupt */
0e0fde3c
NI		 884 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
885 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 886 cd->tx_check | cd->eesr_err_check)) {
0e0fde3c
NI		 887 ctrl_outl(intr_status, ioaddr + EESR);
888 ret = IRQ_HANDLED;
889 } else
890 goto other_irq;
86a74ff2 891
b0ca2a21
NI		 892 if (intr_status & (EESR_FRC | /* Frame recv*/
893 EESR_RMAF | /* Multi cast address recv*/
894 EESR_RRF | /* Bit frame recv */
895 EESR_RTLF | /* Long frame recv*/
896 EESR_RTSF | /* short frame recv */
897 EESR_PRE | /* PHY-LSI recv error */
898 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 899 sh_eth_rx(ndev);
b0ca2a21 900 }
86a74ff2 901
b0ca2a21 902 /* Tx Check */
380af9e3 903 if (intr_status & cd->tx_check) {
86a74ff2
NI		 904 sh_eth_txfree(ndev);
905 netif_wake_queue(ndev);
906 }
907
380af9e3 908 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 909 sh_eth_error(ndev, intr_status);
910
0e0fde3c 911other_irq:
86a74ff2
NI		 912 spin_unlock(&mdp->lock);
913
0e0fde3c 914 return ret;
86a74ff2
NI		 915}
916
917static void sh_eth_timer(unsigned long data)
918{
919 struct net_device *ndev = (struct net_device *)data;
920 struct sh_eth_private *mdp = netdev_priv(ndev);
921
922 mod_timer(&mdp->timer, jiffies + (10 * HZ));
923}
924
925/* PHY state control function */
926static void sh_eth_adjust_link(struct net_device *ndev)
927{
928 struct sh_eth_private *mdp = netdev_priv(ndev);
929 struct phy_device *phydev = mdp->phydev;
930 u32 ioaddr = ndev->base_addr;
931 int new_state = 0;
932
933 if (phydev->link != PHY_DOWN) {
934 if (phydev->duplex != mdp->duplex) {
935 new_state = 1;
936 mdp->duplex = phydev->duplex;
380af9e3
YS		 937 if (mdp->cd->set_duplex)
938 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 939 }
940
941 if (phydev->speed != mdp->speed) {
942 new_state = 1;
943 mdp->speed = phydev->speed;
380af9e3
YS		 944 if (mdp->cd->set_rate)
945 mdp->cd->set_rate(ndev);
86a74ff2
NI		 946 }
947 if (mdp->link == PHY_DOWN) {
948 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
949 | ECMR_DM, ioaddr + ECMR);
950 new_state = 1;
951 mdp->link = phydev->link;
86a74ff2
NI		 952 }
953 } else if (mdp->link) {
954 new_state = 1;
955 mdp->link = PHY_DOWN;
956 mdp->speed = 0;
957 mdp->duplex = -1;
86a74ff2
NI		 958 }
959
960 if (new_state)
961 phy_print_status(phydev);
962}
963
964/* PHY init function */
965static int sh_eth_phy_init(struct net_device *ndev)
966{
967 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 968 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 969 struct phy_device *phydev = NULL;
970
fb28ad35 971 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 972 mdp->mii_bus->id , mdp->phy_id);
973
974 mdp->link = PHY_DOWN;
975 mdp->speed = 0;
976 mdp->duplex = -1;
977
978 /* Try connect to PHY */
979 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
980 0, PHY_INTERFACE_MODE_MII);
981 if (IS_ERR(phydev)) {
982 dev_err(&ndev->dev, "phy_connect failed\n");
983 return PTR_ERR(phydev);
984 }
380af9e3 985
86a74ff2 986 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 987 phydev->addr, phydev->drv->name);
86a74ff2
NI		 988
989 mdp->phydev = phydev;
990
991 return 0;
992}
993
994/* PHY control start function */
995static int sh_eth_phy_start(struct net_device *ndev)
996{
997 struct sh_eth_private *mdp = netdev_priv(ndev);
998 int ret;
999
1000 ret = sh_eth_phy_init(ndev);
1001 if (ret)
1002 return ret;
1003
1004 /* reset phy - this also wakes it from PDOWN */
1005 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1006 phy_start(mdp->phydev);
1007
1008 return 0;
1009}
1010
1011/* network device open function */
1012static int sh_eth_open(struct net_device *ndev)
1013{
1014 int ret = 0;
1015 struct sh_eth_private *mdp = netdev_priv(ndev);
1016
bcd5149d
MD		 1017 pm_runtime_get_sync(&mdp->pdev->dev);
1018
0e0fde3c
NI		 1019 ret = request_irq(ndev->irq, &sh_eth_interrupt,
1020#if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764)
1021 IRQF_SHARED,
1022#else
1023 0,
1024#endif
1025 ndev->name, ndev);
86a74ff2 1026 if (ret) {
380af9e3 1027 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1028 return ret;
1029 }
1030
1031 /* Descriptor set */
1032 ret = sh_eth_ring_init(ndev);
1033 if (ret)
1034 goto out_free_irq;
1035
1036 /* device init */
1037 ret = sh_eth_dev_init(ndev);
1038 if (ret)
1039 goto out_free_irq;
1040
1041 /* PHY control start*/
1042 ret = sh_eth_phy_start(ndev);
1043 if (ret)
1044 goto out_free_irq;
1045
1046 /* Set the timer to check for link beat. */
1047 init_timer(&mdp->timer);
1048 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1049 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1050
1051 return ret;
1052
1053out_free_irq:
1054 free_irq(ndev->irq, ndev);
bcd5149d 1055 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1056 return ret;
1057}
1058
1059/* Timeout function */
1060static void sh_eth_tx_timeout(struct net_device *ndev)
1061{
1062 struct sh_eth_private *mdp = netdev_priv(ndev);
1063 u32 ioaddr = ndev->base_addr;
1064 struct sh_eth_rxdesc *rxdesc;
1065 int i;
1066
1067 netif_stop_queue(ndev);
1068
1069 /* worning message out. */
1070 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
1071 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
1072
1073 /* tx_errors count up */
1074 mdp->stats.tx_errors++;
1075
1076 /* timer off */
1077 del_timer_sync(&mdp->timer);
1078
1079 /* Free all the skbuffs in the Rx queue. */
1080 for (i = 0; i < RX_RING_SIZE; i++) {
1081 rxdesc = &mdp->rx_ring[i];
1082 rxdesc->status = 0;
1083 rxdesc->addr = 0xBADF00D0;
1084 if (mdp->rx_skbuff[i])
1085 dev_kfree_skb(mdp->rx_skbuff[i]);
1086 mdp->rx_skbuff[i] = NULL;
1087 }
1088 for (i = 0; i < TX_RING_SIZE; i++) {
1089 if (mdp->tx_skbuff[i])
1090 dev_kfree_skb(mdp->tx_skbuff[i]);
1091 mdp->tx_skbuff[i] = NULL;
1092 }
1093
1094 /* device init */
1095 sh_eth_dev_init(ndev);
1096
1097 /* timer on */
1098 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1099 add_timer(&mdp->timer);
1100}
1101
1102/* Packet transmit function */
1103static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1104{
1105 struct sh_eth_private *mdp = netdev_priv(ndev);
1106 struct sh_eth_txdesc *txdesc;
1107 u32 entry;
fb5e2f9b 1108 unsigned long flags;
86a74ff2
NI		 1109
1110 spin_lock_irqsave(&mdp->lock, flags);
1111 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1112 if (!sh_eth_txfree(ndev)) {
1113 netif_stop_queue(ndev);
1114 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1115 return NETDEV_TX_BUSY;
86a74ff2
NI		 1116 }
1117 }
1118 spin_unlock_irqrestore(&mdp->lock, flags);
1119
1120 entry = mdp->cur_tx % TX_RING_SIZE;
1121 mdp->tx_skbuff[entry] = skb;
1122 txdesc = &mdp->tx_ring[entry];
0029d64a 1123 txdesc->addr = virt_to_phys(skb->data);
86a74ff2 1124 /* soft swap. */
380af9e3
YS		 1125 if (!mdp->cd->hw_swap)
1126 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1127 skb->len + 2);
86a74ff2
NI		 1128 /* write back */
1129 __flush_purge_region(skb->data, skb->len);
1130 if (skb->len < ETHERSMALL)
1131 txdesc->buffer_length = ETHERSMALL;
1132 else
1133 txdesc->buffer_length = skb->len;
1134
1135 if (entry >= TX_RING_SIZE - 1)
71557a37 1136 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1137 else
71557a37 1138 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1139
1140 mdp->cur_tx++;
1141
b0ca2a21
NI		 1142 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
1143 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
1144
86a74ff2
NI		 1145 ndev->trans_start = jiffies;
1146
6ed10654 1147 return NETDEV_TX_OK;
86a74ff2
NI		 1148}
1149
1150/* device close function */
1151static int sh_eth_close(struct net_device *ndev)
1152{
1153 struct sh_eth_private *mdp = netdev_priv(ndev);
1154 u32 ioaddr = ndev->base_addr;
1155 int ringsize;
1156
1157 netif_stop_queue(ndev);
1158
1159 /* Disable interrupts by clearing the interrupt mask. */
1160 ctrl_outl(0x0000, ioaddr + EESIPR);
1161
1162 /* Stop the chip's Tx and Rx processes. */
1163 ctrl_outl(0, ioaddr + EDTRR);
1164 ctrl_outl(0, ioaddr + EDRRR);
1165
1166 /* PHY Disconnect */
1167 if (mdp->phydev) {
1168 phy_stop(mdp->phydev);
1169 phy_disconnect(mdp->phydev);
1170 }
1171
1172 free_irq(ndev->irq, ndev);
1173
1174 del_timer_sync(&mdp->timer);
1175
1176 /* Free all the skbuffs in the Rx queue. */
1177 sh_eth_ring_free(ndev);
1178
1179 /* free DMA buffer */
1180 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1181 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1182
1183 /* free DMA buffer */
1184 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1185 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1186
bcd5149d
MD		 1187 pm_runtime_put_sync(&mdp->pdev->dev);
1188
86a74ff2
NI		 1189 return 0;
1190}
1191
1192static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1193{
1194 struct sh_eth_private *mdp = netdev_priv(ndev);
1195 u32 ioaddr = ndev->base_addr;
1196
bcd5149d
MD		 1197 pm_runtime_get_sync(&mdp->pdev->dev);
1198
86a74ff2
NI		 1199 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1200 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1201 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1202 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1203 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1204 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
b0ca2a21
NI		 1205#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1206 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1207 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1208 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1209 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1210#else
86a74ff2
NI		 1211 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1212 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
b0ca2a21 1213#endif
bcd5149d
MD		 1214 pm_runtime_put_sync(&mdp->pdev->dev);
1215
86a74ff2
NI		 1216 return &mdp->stats;
1217}
1218
1219/* ioctl to device funciotn*/
1220static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1221 int cmd)
1222{
1223 struct sh_eth_private *mdp = netdev_priv(ndev);
1224 struct phy_device *phydev = mdp->phydev;
1225
1226 if (!netif_running(ndev))
1227 return -EINVAL;
1228
1229 if (!phydev)
1230 return -ENODEV;
1231
1232 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1233}
1234
380af9e3 1235#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1236/* Multicast reception directions set */
1237static void sh_eth_set_multicast_list(struct net_device *ndev)
1238{
1239 u32 ioaddr = ndev->base_addr;
1240
1241 if (ndev->flags & IFF_PROMISC) {
1242 /* Set promiscuous. */
1243 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1244 ioaddr + ECMR);
1245 } else {
1246 /* Normal, unicast/broadcast-only mode. */
1247 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1248 ioaddr + ECMR);
1249 }
1250}
1251
1252/* SuperH's TSU register init function */
1253static void sh_eth_tsu_init(u32 ioaddr)
1254{
1255 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1256 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1257 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1258 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1259 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1260 ctrl_outl(0, ioaddr + TSU_PRISL0);
1261 ctrl_outl(0, ioaddr + TSU_PRISL1);
1262 ctrl_outl(0, ioaddr + TSU_FWSL0);
1263 ctrl_outl(0, ioaddr + TSU_FWSL1);
1264 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
b0ca2a21
NI		 1265#if defined(CONFIG_CPU_SUBTYPE_SH7763)
1266 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1267 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1268#else
86a74ff2
NI		 1269 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1270 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
b0ca2a21 1271#endif
86a74ff2
NI		 1272 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1273 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1274 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1275 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1276 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1277 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1278 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1279}
380af9e3 1280#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1281
1282/* MDIO bus release function */
1283static int sh_mdio_release(struct net_device *ndev)
1284{
1285 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1286
1287 /* unregister mdio bus */
1288 mdiobus_unregister(bus);
1289
1290 /* remove mdio bus info from net_device */
1291 dev_set_drvdata(&ndev->dev, NULL);
1292
1293 /* free bitbang info */
1294 free_mdio_bitbang(bus);
1295
1296 return 0;
1297}
1298
1299/* MDIO bus init function */
1300static int sh_mdio_init(struct net_device *ndev, int id)
1301{
1302 int ret, i;
1303 struct bb_info *bitbang;
1304 struct sh_eth_private *mdp = netdev_priv(ndev);
1305
1306 /* create bit control struct for PHY */
1307 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1308 if (!bitbang) {
1309 ret = -ENOMEM;
1310 goto out;
1311 }
1312
1313 /* bitbang init */
1314 bitbang->addr = ndev->base_addr + PIR;
1315 bitbang->mdi_msk = 0x08;
1316 bitbang->mdo_msk = 0x04;
1317 bitbang->mmd_msk = 0x02;/* MMD */
1318 bitbang->mdc_msk = 0x01;
1319 bitbang->ctrl.ops = &bb_ops;
1320
1321 /* MII contorller setting */
1322 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1323 if (!mdp->mii_bus) {
1324 ret = -ENOMEM;
1325 goto out_free_bitbang;
1326 }
1327
1328 /* Hook up MII support for ethtool */
1329 mdp->mii_bus->name = "sh_mii";
18ee49dd 1330 mdp->mii_bus->parent = &ndev->dev;
fb5e2f9b 1331 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
86a74ff2
NI		 1332
1333 /* PHY IRQ */
1334 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1335 if (!mdp->mii_bus->irq) {
1336 ret = -ENOMEM;
1337 goto out_free_bus;
1338 }
1339
1340 for (i = 0; i < PHY_MAX_ADDR; i++)
1341 mdp->mii_bus->irq[i] = PHY_POLL;
1342
1343 /* regist mdio bus */
1344 ret = mdiobus_register(mdp->mii_bus);
1345 if (ret)
1346 goto out_free_irq;
1347
1348 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1349
1350 return 0;
1351
1352out_free_irq:
1353 kfree(mdp->mii_bus->irq);
1354
1355out_free_bus:
298cf9be 1356 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1357
1358out_free_bitbang:
1359 kfree(bitbang);
1360
1361out:
1362 return ret;
1363}
1364
ebf84eaa
AB		 1365static const struct net_device_ops sh_eth_netdev_ops = {
1366 .ndo_open = sh_eth_open,
1367 .ndo_stop = sh_eth_close,
1368 .ndo_start_xmit = sh_eth_start_xmit,
1369 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1370#if defined(SH_ETH_HAS_TSU)
ebf84eaa 1371 .ndo_set_multicast_list = sh_eth_set_multicast_list,
380af9e3 1372#endif
ebf84eaa
AB		 1373 .ndo_tx_timeout = sh_eth_tx_timeout,
1374 .ndo_do_ioctl = sh_eth_do_ioctl,
1375 .ndo_validate_addr = eth_validate_addr,
1376 .ndo_set_mac_address = eth_mac_addr,
1377 .ndo_change_mtu = eth_change_mtu,
1378};
1379
86a74ff2
NI		 1380static int sh_eth_drv_probe(struct platform_device *pdev)
1381{
1382 int ret, i, devno = 0;
1383 struct resource *res;
1384 struct net_device *ndev = NULL;
1385 struct sh_eth_private *mdp;
71557a37 1386 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1387
1388 /* get base addr */
1389 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1390 if (unlikely(res == NULL)) {
1391 dev_err(&pdev->dev, "invalid resource\n");
1392 ret = -EINVAL;
1393 goto out;
1394 }
1395
1396 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1397 if (!ndev) {
380af9e3 1398 dev_err(&pdev->dev, "Could not allocate device.\n");
86a74ff2
NI		 1399 ret = -ENOMEM;
1400 goto out;
1401 }
1402
1403 /* The sh Ether-specific entries in the device structure. */
1404 ndev->base_addr = res->start;
1405 devno = pdev->id;
1406 if (devno < 0)
1407 devno = 0;
1408
1409 ndev->dma = -1;
cc3c080d 1410 ret = platform_get_irq(pdev, 0);
1411 if (ret < 0) {
86a74ff2
NI		 1412 ret = -ENODEV;
1413 goto out_release;
1414 }
cc3c080d 1415 ndev->irq = ret;
86a74ff2
NI		 1416
1417 SET_NETDEV_DEV(ndev, &pdev->dev);
1418
1419 /* Fill in the fields of the device structure with ethernet values. */
1420 ether_setup(ndev);
1421
1422 mdp = netdev_priv(ndev);
1423 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1424 mdp->pdev = pdev;
1425 pm_runtime_enable(&pdev->dev);
1426 pm_runtime_resume(&pdev->dev);
86a74ff2 1427
71557a37 1428 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1429 /* get PHY ID */
71557a37
YS		 1430 mdp->phy_id = pd->phy;
1431 /* EDMAC endian */
1432 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1433 mdp->no_ether_link = pd->no_ether_link;
1434 mdp->ether_link_active_low = pd->ether_link_active_low;
86a74ff2 1435
380af9e3
YS		 1436 /* set cpu data */
1437 mdp->cd = &sh_eth_my_cpu_data;
1438 sh_eth_set_default_cpu_data(mdp->cd);
1439
86a74ff2 1440 /* set function */
ebf84eaa 1441 ndev->netdev_ops = &sh_eth_netdev_ops;
86a74ff2
NI		 1442 ndev->watchdog_timeo = TX_TIMEOUT;
1443
1444 mdp->post_rx = POST_RX >> (devno << 1);
1445 mdp->post_fw = POST_FW >> (devno << 1);
1446
1447 /* read and set MAC address */
748031f9 1448 read_mac_address(ndev, pd->mac_addr);
86a74ff2
NI		 1449
1450 /* First device only init */
1451 if (!devno) {
380af9e3
YS		 1452 if (mdp->cd->chip_reset)
1453 mdp->cd->chip_reset(ndev);
86a74ff2 1454
380af9e3 1455#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1456 /* TSU init (Init only)*/
1457 sh_eth_tsu_init(SH_TSU_ADDR);
71557a37 1458#endif
86a74ff2
NI		 1459 }
1460
1461 /* network device register */
1462 ret = register_netdev(ndev);
1463 if (ret)
1464 goto out_release;
1465
1466 /* mdio bus init */
1467 ret = sh_mdio_init(ndev, pdev->id);
1468 if (ret)
1469 goto out_unregister;
1470
1471 /* pritnt device infomation */
380af9e3
YS		 1472 pr_info("Base address at 0x%x, ",
1473 (u32)ndev->base_addr);
86a74ff2
NI		 1474
1475 for (i = 0; i < 5; i++)
71557a37
YS		 1476 printk("%02X:", ndev->dev_addr[i]);
1477 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
86a74ff2
NI		 1478
1479 platform_set_drvdata(pdev, ndev);
1480
1481 return ret;
1482
1483out_unregister:
1484 unregister_netdev(ndev);
1485
1486out_release:
1487 /* net_dev free */
1488 if (ndev)
1489 free_netdev(ndev);
1490
1491out:
1492 return ret;
1493}
1494
1495static int sh_eth_drv_remove(struct platform_device *pdev)
1496{
1497 struct net_device *ndev = platform_get_drvdata(pdev);
1498
1499 sh_mdio_release(ndev);
1500 unregister_netdev(ndev);
1501 flush_scheduled_work();
bcd5149d 1502 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 1503 free_netdev(ndev);
1504 platform_set_drvdata(pdev, NULL);
1505
1506 return 0;
1507}
1508
bcd5149d
MD		 1509static int sh_eth_runtime_nop(struct device *dev)
1510{
1511 /*
1512 * Runtime PM callback shared between ->runtime_suspend()
1513 * and ->runtime_resume(). Simply returns success.
1514 *
1515 * This driver re-initializes all registers after
1516 * pm_runtime_get_sync() anyway so there is no need
1517 * to save and restore registers here.
1518 */
1519 return 0;
1520}
1521
1522static struct dev_pm_ops sh_eth_dev_pm_ops = {
1523 .runtime_suspend = sh_eth_runtime_nop,
1524 .runtime_resume = sh_eth_runtime_nop,
1525};
1526
86a74ff2
NI		 1527static struct platform_driver sh_eth_driver = {
1528 .probe = sh_eth_drv_probe,
1529 .remove = sh_eth_drv_remove,
1530 .driver = {
1531 .name = CARDNAME,
bcd5149d 1532 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1533 },
1534};
1535
1536static int __init sh_eth_init(void)
1537{
1538 return platform_driver_register(&sh_eth_driver);
1539}
1540
1541static void __exit sh_eth_cleanup(void)
1542{
1543 platform_driver_unregister(&sh_eth_driver);
1544}
1545
1546module_init(sh_eth_init);
1547module_exit(sh_eth_cleanup);
1548
1549MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1550MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1551MODULE_LICENSE("GPL v2");
Clone of davem's net-next-2.6 tree