]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/sfc/siena.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sfc: Enable IPv6 RSS using random key for Toeplitz hash
[net-next-2.6.git] / drivers / net / sfc / siena.c
CommitLineData
afd4aea0
BH		 1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#include <linux/bitops.h>
12#include <linux/delay.h>
13#include <linux/pci.h>
14#include <linux/module.h>
5a0e3ad6 15#include <linux/slab.h>
d614cfbc 16#include <linux/random.h>
afd4aea0
BH		 17#include "net_driver.h"
18#include "bitfield.h"
19#include "efx.h"
20#include "nic.h"
21#include "mac.h"
22#include "spi.h"
23#include "regs.h"
24#include "io.h"
25#include "phy.h"
26#include "workarounds.h"
27#include "mcdi.h"
28#include "mcdi_pcol.h"
29
30/* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31
32static void siena_init_wol(struct efx_nic *efx);
33
34
35static void siena_push_irq_moderation(struct efx_channel *channel)
36{
37 efx_dword_t timer_cmd;
38
39 if (channel->irq_moderation)
40 EFX_POPULATE_DWORD_2(timer_cmd,
41 FRF_CZ_TC_TIMER_MODE,
42 FFE_CZ_TIMER_MODE_INT_HLDOFF,
43 FRF_CZ_TC_TIMER_VAL,
44 channel->irq_moderation - 1);
45 else
46 EFX_POPULATE_DWORD_2(timer_cmd,
47 FRF_CZ_TC_TIMER_MODE,
48 FFE_CZ_TIMER_MODE_DIS,
49 FRF_CZ_TC_TIMER_VAL, 0);
50 efx_writed_page_locked(channel->efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
51 channel->channel);
52}
53
54static void siena_push_multicast_hash(struct efx_nic *efx)
55{
56 WARN_ON(!mutex_is_locked(&efx->mac_lock));
57
58 efx_mcdi_rpc(efx, MC_CMD_SET_MCAST_HASH,
59 efx->multicast_hash.byte, sizeof(efx->multicast_hash),
60 NULL, 0, NULL);
61}
62
63static int siena_mdio_write(struct net_device *net_dev,
64 int prtad, int devad, u16 addr, u16 value)
65{
66 struct efx_nic *efx = netdev_priv(net_dev);
67 uint32_t status;
68 int rc;
69
70 rc = efx_mcdi_mdio_write(efx, efx->mdio_bus, prtad, devad,
71 addr, value, &status);
72 if (rc)
73 return rc;
74 if (status != MC_CMD_MDIO_STATUS_GOOD)
75 return -EIO;
76
77 return 0;
78}
79
80static int siena_mdio_read(struct net_device *net_dev,
81 int prtad, int devad, u16 addr)
82{
83 struct efx_nic *efx = netdev_priv(net_dev);
84 uint16_t value;
85 uint32_t status;
86 int rc;
87
88 rc = efx_mcdi_mdio_read(efx, efx->mdio_bus, prtad, devad,
89 addr, &value, &status);
90 if (rc)
91 return rc;
92 if (status != MC_CMD_MDIO_STATUS_GOOD)
93 return -EIO;
94
95 return (int)value;
96}
97
98/* This call is responsible for hooking in the MAC and PHY operations */
99static int siena_probe_port(struct efx_nic *efx)
100{
101 int rc;
102
103 /* Hook in PHY operations table */
104 efx->phy_op = &efx_mcdi_phy_ops;
105
106 /* Set up MDIO structure for PHY */
107 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
108 efx->mdio.mdio_read = siena_mdio_read;
109 efx->mdio.mdio_write = siena_mdio_write;
110
7a6b8f6f 111 /* Fill out MDIO structure, loopback modes, and initial link state */
afd4aea0
BH		 112 rc = efx->phy_op->probe(efx);
113 if (rc != 0)
114 return rc;
115
afd4aea0
BH		 116 /* Allocate buffer for stats */
117 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
118 MC_CMD_MAC_NSTATS * sizeof(u64));
119 if (rc)
120 return rc;
121 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
122 (u64)efx->stats_buffer.dma_addr,
123 efx->stats_buffer.addr,
124 (u64)virt_to_phys(efx->stats_buffer.addr));
125
126 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 1);
127
128 return 0;
129}
130
131void siena_remove_port(struct efx_nic *efx)
132{
ff3b00a0 133 efx->phy_op->remove(efx);
afd4aea0
BH		 134 efx_nic_free_buffer(efx, &efx->stats_buffer);
135}
136
137static const struct efx_nic_register_test siena_register_tests[] = {
138 { FR_AZ_ADR_REGION,
4cddca54 139 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
afd4aea0
BH		 140 { FR_CZ_USR_EV_CFG,
141 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
142 { FR_AZ_RX_CFG,
143 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
144 { FR_AZ_TX_CFG,
145 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
146 { FR_AZ_TX_RESERVED,
147 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
148 { FR_AZ_SRM_TX_DC_CFG,
149 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
150 { FR_AZ_RX_DC_CFG,
151 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
152 { FR_AZ_RX_DC_PF_WM,
153 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
154 { FR_BZ_DP_CTRL,
155 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
156 { FR_BZ_RX_RSS_TKEY,
157 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
158 { FR_CZ_RX_RSS_IPV6_REG1,
159 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
160 { FR_CZ_RX_RSS_IPV6_REG2,
161 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
162 { FR_CZ_RX_RSS_IPV6_REG3,
163 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
164};
165
166static int siena_test_registers(struct efx_nic *efx)
167{
168 return efx_nic_test_registers(efx, siena_register_tests,
169 ARRAY_SIZE(siena_register_tests));
170}
171
172/**************************************************************************
173 *
174 * Device reset
175 *
176 **************************************************************************
177 */
178
179static int siena_reset_hw(struct efx_nic *efx, enum reset_type method)
180{
8b2103ad
SH		 181 int rc;
182
183 /* Recover from a failed assertion pre-reset */
184 rc = efx_mcdi_handle_assertion(efx);
185 if (rc)
186 return rc;
afd4aea0
BH		 187
188 if (method == RESET_TYPE_WORLD)
189 return efx_mcdi_reset_mc(efx);
190 else
191 return efx_mcdi_reset_port(efx);
192}
193
194static int siena_probe_nvconfig(struct efx_nic *efx)
195{
196 int rc;
197
198 rc = efx_mcdi_get_board_cfg(efx, efx->mac_address, NULL);
199 if (rc)
200 return rc;
201
202 return 0;
203}
204
205static int siena_probe_nic(struct efx_nic *efx)
206{
207 struct siena_nic_data *nic_data;
208 bool already_attached = 0;
209 int rc;
210
211 /* Allocate storage for hardware specific data */
212 nic_data = kzalloc(sizeof(struct siena_nic_data), GFP_KERNEL);
213 if (!nic_data)
214 return -ENOMEM;
215 efx->nic_data = nic_data;
216
217 if (efx_nic_fpga_ver(efx) != 0) {
218 EFX_ERR(efx, "Siena FPGA not supported\n");
219 rc = -ENODEV;
220 goto fail1;
221 }
222
223 efx_mcdi_init(efx);
224
225 /* Recover from a failed assertion before probing */
226 rc = efx_mcdi_handle_assertion(efx);
227 if (rc)
228 goto fail1;
229
230 rc = efx_mcdi_fwver(efx, &nic_data->fw_version, &nic_data->fw_build);
231 if (rc) {
232 EFX_ERR(efx, "Failed to read MCPU firmware version - "
233 "rc %d\n", rc);
234 goto fail1; /* MCPU absent? */
235 }
236
237 /* Let the BMC know that the driver is now in charge of link and
238 * filter settings. We must do this before we reset the NIC */
239 rc = efx_mcdi_drv_attach(efx, true, &already_attached);
240 if (rc) {
241 EFX_ERR(efx, "Unable to register driver with MCPU\n");
242 goto fail2;
243 }
244 if (already_attached)
245 /* Not a fatal error */
246 EFX_ERR(efx, "Host already registered with MCPU\n");
247
248 /* Now we can reset the NIC */
249 rc = siena_reset_hw(efx, RESET_TYPE_ALL);
250 if (rc) {
251 EFX_ERR(efx, "failed to reset NIC\n");
252 goto fail3;
253 }
254
255 siena_init_wol(efx);
256
257 /* Allocate memory for INT_KER */
258 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
259 if (rc)
260 goto fail4;
261 BUG_ON(efx->irq_status.dma_addr & 0x0f);
262
263 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
264 (unsigned long long)efx->irq_status.dma_addr,
265 efx->irq_status.addr,
266 (unsigned long long)virt_to_phys(efx->irq_status.addr));
267
268 /* Read in the non-volatile configuration */
269 rc = siena_probe_nvconfig(efx);
270 if (rc == -EINVAL) {
271 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
272 efx->phy_type = PHY_TYPE_NONE;
273 efx->mdio.prtad = MDIO_PRTAD_NONE;
274 } else if (rc) {
275 goto fail5;
276 }
277
d614cfbc
BH		 278 get_random_bytes(&nic_data->ipv6_rss_key,
279 sizeof(nic_data->ipv6_rss_key));
280
afd4aea0
BH		 281 return 0;
282
283fail5:
284 efx_nic_free_buffer(efx, &efx->irq_status);
285fail4:
286fail3:
287 efx_mcdi_drv_attach(efx, false, NULL);
288fail2:
289fail1:
290 kfree(efx->nic_data);
291 return rc;
292}
293
294/* This call performs hardware-specific global initialisation, such as
295 * defining the descriptor cache sizes and number of RSS channels.
296 * It does not set up any buffers, descriptor rings or event queues.
297 */
298static int siena_init_nic(struct efx_nic *efx)
299{
d614cfbc 300 struct siena_nic_data *nic_data = efx->nic_data;
afd4aea0
BH		 301 efx_oword_t temp;
302 int rc;
303
304 /* Recover from a failed assertion post-reset */
305 rc = efx_mcdi_handle_assertion(efx);
306 if (rc)
307 return rc;
308
309 /* Squash TX of packets of 16 bytes or less */
310 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
311 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
312 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
313
314 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
315 * descriptors (which is bad).
316 */
317 efx_reado(efx, &temp, FR_AZ_TX_CFG);
318 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
319 EFX_SET_OWORD_FIELD(temp, FRF_CZ_TX_FILTER_EN_BIT, 1);
320 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
321
322 efx_reado(efx, &temp, FR_AZ_RX_CFG);
323 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_DESC_PUSH_EN, 0);
324 EFX_SET_OWORD_FIELD(temp, FRF_BZ_RX_INGR_EN, 1);
325 efx_writeo(efx, &temp, FR_AZ_RX_CFG);
326
d614cfbc
BH		 327 /* Enable IPv6 RSS */
328 BUILD_BUG_ON(sizeof(nic_data->ipv6_rss_key) !=
329 2 * sizeof(temp) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8 ||
330 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN != 0);
331 memcpy(&temp, nic_data->ipv6_rss_key, sizeof(temp));
332 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG1);
333 memcpy(&temp, nic_data->ipv6_rss_key + sizeof(temp), sizeof(temp));
334 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG2);
335 EFX_POPULATE_OWORD_2(temp, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1,
336 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, 1);
337 memcpy(&temp, nic_data->ipv6_rss_key + 2 * sizeof(temp),
338 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH / 8);
339 efx_writeo(efx, &temp, FR_CZ_RX_RSS_IPV6_REG3);
340
afd4aea0
BH		 341 if (efx_nic_rx_xoff_thresh >= 0 || efx_nic_rx_xon_thresh >= 0)
342 /* No MCDI operation has been defined to set thresholds */
343 EFX_ERR(efx, "ignoring RX flow control thresholds\n");
344
345 /* Enable event logging */
346 rc = efx_mcdi_log_ctrl(efx, true, false, 0);
347 if (rc)
348 return rc;
349
350 /* Set destination of both TX and RX Flush events */
351 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
352 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
353
354 EFX_POPULATE_OWORD_1(temp, FRF_CZ_USREV_DIS, 1);
355 efx_writeo(efx, &temp, FR_CZ_USR_EV_CFG);
356
357 efx_nic_init_common(efx);
358 return 0;
359}
360
361static void siena_remove_nic(struct efx_nic *efx)
362{
363 efx_nic_free_buffer(efx, &efx->irq_status);
364
365 siena_reset_hw(efx, RESET_TYPE_ALL);
366
367 /* Relinquish the device back to the BMC */
368 if (efx_nic_has_mc(efx))
369 efx_mcdi_drv_attach(efx, false, NULL);
370
371 /* Tear down the private nic state */
372 kfree(efx->nic_data);
373 efx->nic_data = NULL;
374}
375
376#define STATS_GENERATION_INVALID ((u64)(-1))
377
378static int siena_try_update_nic_stats(struct efx_nic *efx)
379{
380 u64 *dma_stats;
381 struct efx_mac_stats *mac_stats;
382 u64 generation_start;
383 u64 generation_end;
384
385 mac_stats = &efx->mac_stats;
386 dma_stats = (u64 *)efx->stats_buffer.addr;
387
388 generation_end = dma_stats[MC_CMD_MAC_GENERATION_END];
389 if (generation_end == STATS_GENERATION_INVALID)
390 return 0;
391 rmb();
392
393#define MAC_STAT(M, D) \
394 mac_stats->M = dma_stats[MC_CMD_MAC_ ## D]
395
396 MAC_STAT(tx_bytes, TX_BYTES);
397 MAC_STAT(tx_bad_bytes, TX_BAD_BYTES);
398 mac_stats->tx_good_bytes = (mac_stats->tx_bytes -
399 mac_stats->tx_bad_bytes);
400 MAC_STAT(tx_packets, TX_PKTS);
401 MAC_STAT(tx_bad, TX_BAD_FCS_PKTS);
402 MAC_STAT(tx_pause, TX_PAUSE_PKTS);
403 MAC_STAT(tx_control, TX_CONTROL_PKTS);
404 MAC_STAT(tx_unicast, TX_UNICAST_PKTS);
405 MAC_STAT(tx_multicast, TX_MULTICAST_PKTS);
406 MAC_STAT(tx_broadcast, TX_BROADCAST_PKTS);
407 MAC_STAT(tx_lt64, TX_LT64_PKTS);
408 MAC_STAT(tx_64, TX_64_PKTS);
409 MAC_STAT(tx_65_to_127, TX_65_TO_127_PKTS);
410 MAC_STAT(tx_128_to_255, TX_128_TO_255_PKTS);
411 MAC_STAT(tx_256_to_511, TX_256_TO_511_PKTS);
412 MAC_STAT(tx_512_to_1023, TX_512_TO_1023_PKTS);
413 MAC_STAT(tx_1024_to_15xx, TX_1024_TO_15XX_PKTS);
414 MAC_STAT(tx_15xx_to_jumbo, TX_15XX_TO_JUMBO_PKTS);
415 MAC_STAT(tx_gtjumbo, TX_GTJUMBO_PKTS);
416 mac_stats->tx_collision = 0;
417 MAC_STAT(tx_single_collision, TX_SINGLE_COLLISION_PKTS);
418 MAC_STAT(tx_multiple_collision, TX_MULTIPLE_COLLISION_PKTS);
419 MAC_STAT(tx_excessive_collision, TX_EXCESSIVE_COLLISION_PKTS);
420 MAC_STAT(tx_deferred, TX_DEFERRED_PKTS);
421 MAC_STAT(tx_late_collision, TX_LATE_COLLISION_PKTS);
422 mac_stats->tx_collision = (mac_stats->tx_single_collision +
423 mac_stats->tx_multiple_collision +
424 mac_stats->tx_excessive_collision +
425 mac_stats->tx_late_collision);
426 MAC_STAT(tx_excessive_deferred, TX_EXCESSIVE_DEFERRED_PKTS);
427 MAC_STAT(tx_non_tcpudp, TX_NON_TCPUDP_PKTS);
428 MAC_STAT(tx_mac_src_error, TX_MAC_SRC_ERR_PKTS);
429 MAC_STAT(tx_ip_src_error, TX_IP_SRC_ERR_PKTS);
430 MAC_STAT(rx_bytes, RX_BYTES);
431 MAC_STAT(rx_bad_bytes, RX_BAD_BYTES);
432 mac_stats->rx_good_bytes = (mac_stats->rx_bytes -
433 mac_stats->rx_bad_bytes);
434 MAC_STAT(rx_packets, RX_PKTS);
435 MAC_STAT(rx_good, RX_GOOD_PKTS);
436 mac_stats->rx_bad = mac_stats->rx_packets - mac_stats->rx_good;
437 MAC_STAT(rx_pause, RX_PAUSE_PKTS);
438 MAC_STAT(rx_control, RX_CONTROL_PKTS);
439 MAC_STAT(rx_unicast, RX_UNICAST_PKTS);
440 MAC_STAT(rx_multicast, RX_MULTICAST_PKTS);
441 MAC_STAT(rx_broadcast, RX_BROADCAST_PKTS);
442 MAC_STAT(rx_lt64, RX_UNDERSIZE_PKTS);
443 MAC_STAT(rx_64, RX_64_PKTS);
444 MAC_STAT(rx_65_to_127, RX_65_TO_127_PKTS);
445 MAC_STAT(rx_128_to_255, RX_128_TO_255_PKTS);
446 MAC_STAT(rx_256_to_511, RX_256_TO_511_PKTS);
447 MAC_STAT(rx_512_to_1023, RX_512_TO_1023_PKTS);
448 MAC_STAT(rx_1024_to_15xx, RX_1024_TO_15XX_PKTS);
449 MAC_STAT(rx_15xx_to_jumbo, RX_15XX_TO_JUMBO_PKTS);
450 MAC_STAT(rx_gtjumbo, RX_GTJUMBO_PKTS);
451 mac_stats->rx_bad_lt64 = 0;
452 mac_stats->rx_bad_64_to_15xx = 0;
453 mac_stats->rx_bad_15xx_to_jumbo = 0;
454 MAC_STAT(rx_bad_gtjumbo, RX_JABBER_PKTS);
455 MAC_STAT(rx_overflow, RX_OVERFLOW_PKTS);
456 mac_stats->rx_missed = 0;
457 MAC_STAT(rx_false_carrier, RX_FALSE_CARRIER_PKTS);
458 MAC_STAT(rx_symbol_error, RX_SYMBOL_ERROR_PKTS);
459 MAC_STAT(rx_align_error, RX_ALIGN_ERROR_PKTS);
460 MAC_STAT(rx_length_error, RX_LENGTH_ERROR_PKTS);
461 MAC_STAT(rx_internal_error, RX_INTERNAL_ERROR_PKTS);
462 mac_stats->rx_good_lt64 = 0;
463
464 efx->n_rx_nodesc_drop_cnt = dma_stats[MC_CMD_MAC_RX_NODESC_DROPS];
465
466#undef MAC_STAT
467
468 rmb();
469 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
470 if (generation_end != generation_start)
471 return -EAGAIN;
472
473 return 0;
474}
475
476static void siena_update_nic_stats(struct efx_nic *efx)
477{
478 while (siena_try_update_nic_stats(efx) == -EAGAIN)
479 cpu_relax();
480}
481
482static void siena_start_nic_stats(struct efx_nic *efx)
483{
484 u64 *dma_stats = (u64 *)efx->stats_buffer.addr;
485
486 dma_stats[MC_CMD_MAC_GENERATION_END] = STATS_GENERATION_INVALID;
487
488 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr,
489 MC_CMD_MAC_NSTATS * sizeof(u64), 1, 0);
490}
491
492static void siena_stop_nic_stats(struct efx_nic *efx)
493{
494 efx_mcdi_mac_stats(efx, efx->stats_buffer.dma_addr, 0, 0, 0);
495}
496
497void siena_print_fwver(struct efx_nic *efx, char *buf, size_t len)
498{
499 struct siena_nic_data *nic_data = efx->nic_data;
500 snprintf(buf, len, "%u.%u.%u.%u",
501 (unsigned int)(nic_data->fw_version >> 48),
502 (unsigned int)(nic_data->fw_version >> 32 & 0xffff),
503 (unsigned int)(nic_data->fw_version >> 16 & 0xffff),
504 (unsigned int)(nic_data->fw_version & 0xffff));
505}
506
507/**************************************************************************
508 *
509 * Wake on LAN
510 *
511 **************************************************************************
512 */
513
514static void siena_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
515{
516 struct siena_nic_data *nic_data = efx->nic_data;
517
518 wol->supported = WAKE_MAGIC;
519 if (nic_data->wol_filter_id != -1)
520 wol->wolopts = WAKE_MAGIC;
521 else
522 wol->wolopts = 0;
523 memset(&wol->sopass, 0, sizeof(wol->sopass));
524}
525
526
527static int siena_set_wol(struct efx_nic *efx, u32 type)
528{
529 struct siena_nic_data *nic_data = efx->nic_data;
530 int rc;
531
532 if (type & ~WAKE_MAGIC)
533 return -EINVAL;
534
535 if (type & WAKE_MAGIC) {
536 if (nic_data->wol_filter_id != -1)
537 efx_mcdi_wol_filter_remove(efx,
538 nic_data->wol_filter_id);
539 rc = efx_mcdi_wol_filter_set_magic(efx, efx->mac_address,
540 &nic_data->wol_filter_id);
541 if (rc)
542 goto fail;
543
544 pci_wake_from_d3(efx->pci_dev, true);
545 } else {
546 rc = efx_mcdi_wol_filter_reset(efx);
547 nic_data->wol_filter_id = -1;
548 pci_wake_from_d3(efx->pci_dev, false);
549 if (rc)
550 goto fail;
551 }
552
553 return 0;
554 fail:
555 EFX_ERR(efx, "%s failed: type=%d rc=%d\n", __func__, type, rc);
556 return rc;
557}
558
559
560static void siena_init_wol(struct efx_nic *efx)
561{
562 struct siena_nic_data *nic_data = efx->nic_data;
563 int rc;
564
565 rc = efx_mcdi_wol_filter_get_magic(efx, &nic_data->wol_filter_id);
566
567 if (rc != 0) {
568 /* If it failed, attempt to get into a synchronised
569 * state with MC by resetting any set WoL filters */
570 efx_mcdi_wol_filter_reset(efx);
571 nic_data->wol_filter_id = -1;
572 } else if (nic_data->wol_filter_id != -1) {
573 pci_wake_from_d3(efx->pci_dev, true);
574 }
575}
576
577
578/**************************************************************************
579 *
580 * Revision-dependent attributes used by efx.c and nic.c
581 *
582 **************************************************************************
583 */
584
585struct efx_nic_type siena_a0_nic_type = {
586 .probe = siena_probe_nic,
587 .remove = siena_remove_nic,
588 .init = siena_init_nic,
589 .fini = efx_port_dummy_op_void,
590 .monitor = NULL,
591 .reset = siena_reset_hw,
592 .probe_port = siena_probe_port,
593 .remove_port = siena_remove_port,
594 .prepare_flush = efx_port_dummy_op_void,
595 .update_stats = siena_update_nic_stats,
596 .start_stats = siena_start_nic_stats,
597 .stop_stats = siena_stop_nic_stats,
598 .set_id_led = efx_mcdi_set_id_led,
599 .push_irq_moderation = siena_push_irq_moderation,
600 .push_multicast_hash = siena_push_multicast_hash,
601 .reconfigure_port = efx_mcdi_phy_reconfigure,
602 .get_wol = siena_get_wol,
603 .set_wol = siena_set_wol,
604 .resume_wol = siena_init_wol,
605 .test_registers = siena_test_registers,
2e803407 606 .test_nvram = efx_mcdi_nvram_test_all,
afd4aea0
BH		 607 .default_mac_ops = &efx_mcdi_mac_operations,
608
609 .revision = EFX_REV_SIENA_A0,
610 .mem_map_size = (FR_CZ_MC_TREG_SMEM +
611 FR_CZ_MC_TREG_SMEM_STEP * FR_CZ_MC_TREG_SMEM_ROWS),
612 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
613 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
614 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
615 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
616 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
617 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
618 .rx_buffer_padding = 0,
619 .max_interrupt_mode = EFX_INT_MODE_MSIX,
620 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
621 * interrupt handler only supports 32
622 * channels */
623 .tx_dc_base = 0x88000,
624 .rx_dc_base = 0x68000,
625 .offload_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM,
626 .reset_world_flags = ETH_RESET_MGMT << ETH_RESET_SHARED_SHIFT,
627};
Clone of davem's net-next-2.6 tree