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1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | /* Common definitions for all Efx net driver code */ | |
12 | ||
13 | #ifndef EFX_NET_DRIVER_H | |
14 | #define EFX_NET_DRIVER_H | |
15 | ||
16 | #include <linux/version.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/etherdevice.h> | |
19 | #include <linux/ethtool.h> | |
20 | #include <linux/if_vlan.h> | |
90d683af | 21 | #include <linux/timer.h> |
68e7f45e | 22 | #include <linux/mdio.h> |
8ceee660 BH |
23 | #include <linux/list.h> |
24 | #include <linux/pci.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/highmem.h> | |
27 | #include <linux/workqueue.h> | |
37b5a603 | 28 | #include <linux/i2c.h> |
8ceee660 BH |
29 | |
30 | #include "enum.h" | |
31 | #include "bitfield.h" | |
8ceee660 | 32 | |
8ceee660 BH |
33 | /************************************************************************** |
34 | * | |
35 | * Build definitions | |
36 | * | |
37 | **************************************************************************/ | |
38 | #ifndef EFX_DRIVER_NAME | |
39 | #define EFX_DRIVER_NAME "sfc" | |
40 | #endif | |
906bb26c | 41 | #define EFX_DRIVER_VERSION "3.0" |
8ceee660 BH |
42 | |
43 | #ifdef EFX_ENABLE_DEBUG | |
44 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) | |
45 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) | |
46 | #else | |
47 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) | |
48 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) | |
49 | #endif | |
50 | ||
8ceee660 BH |
51 | /* Un-rate-limited logging */ |
52 | #define EFX_ERR(efx, fmt, args...) \ | |
55668611 | 53 | dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
54 | |
55 | #define EFX_INFO(efx, fmt, args...) \ | |
55668611 | 56 | dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
57 | |
58 | #ifdef EFX_ENABLE_DEBUG | |
59 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 60 | dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
61 | #else |
62 | #define EFX_LOG(efx, fmt, args...) \ | |
55668611 | 63 | dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
8ceee660 BH |
64 | #endif |
65 | ||
66 | #define EFX_TRACE(efx, fmt, args...) do {} while (0) | |
67 | ||
68 | #define EFX_REGDUMP(efx, fmt, args...) do {} while (0) | |
69 | ||
70 | /* Rate-limited logging */ | |
71 | #define EFX_ERR_RL(efx, fmt, args...) \ | |
72 | do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0) | |
73 | ||
74 | #define EFX_INFO_RL(efx, fmt, args...) \ | |
75 | do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0) | |
76 | ||
77 | #define EFX_LOG_RL(efx, fmt, args...) \ | |
78 | do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0) | |
79 | ||
8ceee660 BH |
80 | /************************************************************************** |
81 | * | |
82 | * Efx data structures | |
83 | * | |
84 | **************************************************************************/ | |
85 | ||
86 | #define EFX_MAX_CHANNELS 32 | |
8ceee660 BH |
87 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
88 | ||
a4900ac9 BH |
89 | /* Checksum generation is a per-queue option in hardware, so each |
90 | * queue visible to the networking core is backed by two hardware TX | |
91 | * queues. */ | |
92 | #define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS | |
93 | #define EFX_TXQ_TYPE_OFFLOAD 1 | |
94 | #define EFX_TXQ_TYPES 2 | |
95 | #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES) | |
60ac1065 | 96 | |
8ceee660 BH |
97 | /** |
98 | * struct efx_special_buffer - An Efx special buffer | |
99 | * @addr: CPU base address of the buffer | |
100 | * @dma_addr: DMA base address of the buffer | |
101 | * @len: Buffer length, in bytes | |
102 | * @index: Buffer index within controller;s buffer table | |
103 | * @entries: Number of buffer table entries | |
104 | * | |
105 | * Special buffers are used for the event queues and the TX and RX | |
106 | * descriptor queues for each channel. They are *not* used for the | |
107 | * actual transmit and receive buffers. | |
8ceee660 BH |
108 | */ |
109 | struct efx_special_buffer { | |
110 | void *addr; | |
111 | dma_addr_t dma_addr; | |
112 | unsigned int len; | |
113 | int index; | |
114 | int entries; | |
115 | }; | |
116 | ||
127e6e10 BH |
117 | enum efx_flush_state { |
118 | FLUSH_NONE, | |
119 | FLUSH_PENDING, | |
120 | FLUSH_FAILED, | |
121 | FLUSH_DONE, | |
122 | }; | |
123 | ||
8ceee660 BH |
124 | /** |
125 | * struct efx_tx_buffer - An Efx TX buffer | |
126 | * @skb: The associated socket buffer. | |
127 | * Set only on the final fragment of a packet; %NULL for all other | |
128 | * fragments. When this fragment completes, then we can free this | |
129 | * skb. | |
b9b39b62 BH |
130 | * @tsoh: The associated TSO header structure, or %NULL if this |
131 | * buffer is not a TSO header. | |
8ceee660 BH |
132 | * @dma_addr: DMA address of the fragment. |
133 | * @len: Length of this fragment. | |
134 | * This field is zero when the queue slot is empty. | |
135 | * @continuation: True if this fragment is not the end of a packet. | |
136 | * @unmap_single: True if pci_unmap_single should be used. | |
8ceee660 BH |
137 | * @unmap_len: Length of this fragment to unmap |
138 | */ | |
139 | struct efx_tx_buffer { | |
140 | const struct sk_buff *skb; | |
b9b39b62 | 141 | struct efx_tso_header *tsoh; |
8ceee660 BH |
142 | dma_addr_t dma_addr; |
143 | unsigned short len; | |
dc8cfa55 BH |
144 | bool continuation; |
145 | bool unmap_single; | |
8ceee660 BH |
146 | unsigned short unmap_len; |
147 | }; | |
148 | ||
149 | /** | |
150 | * struct efx_tx_queue - An Efx TX queue | |
151 | * | |
152 | * This is a ring buffer of TX fragments. | |
153 | * Since the TX completion path always executes on the same | |
154 | * CPU and the xmit path can operate on different CPUs, | |
155 | * performance is increased by ensuring that the completion | |
156 | * path and the xmit path operate on different cache lines. | |
157 | * This is particularly important if the xmit path is always | |
158 | * executing on one CPU which is different from the completion | |
159 | * path. There is also a cache line for members which are | |
160 | * read but not written on the fast path. | |
161 | * | |
162 | * @efx: The associated Efx NIC | |
163 | * @queue: DMA queue number | |
8ceee660 BH |
164 | * @channel: The associated channel |
165 | * @buffer: The software buffer ring | |
166 | * @txd: The hardware descriptor ring | |
6bc5d3a9 | 167 | * @flushed: Used when handling queue flushing |
8ceee660 BH |
168 | * @read_count: Current read pointer. |
169 | * This is the number of buffers that have been removed from both rings. | |
dc8cfa55 | 170 | * @stopped: Stopped count. |
8ceee660 BH |
171 | * Set if this TX queue is currently stopping its port. |
172 | * @insert_count: Current insert pointer | |
173 | * This is the number of buffers that have been added to the | |
174 | * software ring. | |
175 | * @write_count: Current write pointer | |
176 | * This is the number of buffers that have been added to the | |
177 | * hardware ring. | |
178 | * @old_read_count: The value of read_count when last checked. | |
179 | * This is here for performance reasons. The xmit path will | |
180 | * only get the up-to-date value of read_count if this | |
181 | * variable indicates that the queue is full. This is to | |
182 | * avoid cache-line ping-pong between the xmit path and the | |
183 | * completion path. | |
b9b39b62 BH |
184 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
185 | * that are not in use, and so available for new TSO sends. The list | |
186 | * is protected by the TX queue lock. | |
187 | * @tso_bursts: Number of times TSO xmit invoked by kernel | |
188 | * @tso_long_headers: Number of packets with headers too long for standard | |
189 | * blocks | |
190 | * @tso_packets: Number of packets via the TSO xmit path | |
8ceee660 BH |
191 | */ |
192 | struct efx_tx_queue { | |
193 | /* Members which don't change on the fast path */ | |
194 | struct efx_nic *efx ____cacheline_aligned_in_smp; | |
a4900ac9 | 195 | unsigned queue; |
8ceee660 BH |
196 | struct efx_channel *channel; |
197 | struct efx_nic *nic; | |
198 | struct efx_tx_buffer *buffer; | |
199 | struct efx_special_buffer txd; | |
127e6e10 | 200 | enum efx_flush_state flushed; |
8ceee660 BH |
201 | |
202 | /* Members used mainly on the completion path */ | |
203 | unsigned int read_count ____cacheline_aligned_in_smp; | |
204 | int stopped; | |
205 | ||
206 | /* Members used only on the xmit path */ | |
207 | unsigned int insert_count ____cacheline_aligned_in_smp; | |
208 | unsigned int write_count; | |
209 | unsigned int old_read_count; | |
b9b39b62 BH |
210 | struct efx_tso_header *tso_headers_free; |
211 | unsigned int tso_bursts; | |
212 | unsigned int tso_long_headers; | |
213 | unsigned int tso_packets; | |
8ceee660 BH |
214 | }; |
215 | ||
216 | /** | |
217 | * struct efx_rx_buffer - An Efx RX data buffer | |
218 | * @dma_addr: DMA base address of the buffer | |
219 | * @skb: The associated socket buffer, if any. | |
220 | * If both this and page are %NULL, the buffer slot is currently free. | |
221 | * @page: The associated page buffer, if any. | |
222 | * If both this and skb are %NULL, the buffer slot is currently free. | |
223 | * @data: Pointer to ethernet header | |
224 | * @len: Buffer length, in bytes. | |
8ceee660 BH |
225 | */ |
226 | struct efx_rx_buffer { | |
227 | dma_addr_t dma_addr; | |
228 | struct sk_buff *skb; | |
229 | struct page *page; | |
230 | char *data; | |
231 | unsigned int len; | |
8ceee660 BH |
232 | }; |
233 | ||
62b330ba SH |
234 | /** |
235 | * struct efx_rx_page_state - Page-based rx buffer state | |
236 | * | |
237 | * Inserted at the start of every page allocated for receive buffers. | |
238 | * Used to facilitate sharing dma mappings between recycled rx buffers | |
239 | * and those passed up to the kernel. | |
240 | * | |
241 | * @refcnt: Number of struct efx_rx_buffer's referencing this page. | |
242 | * When refcnt falls to zero, the page is unmapped for dma | |
243 | * @dma_addr: The dma address of this page. | |
244 | */ | |
245 | struct efx_rx_page_state { | |
246 | unsigned refcnt; | |
247 | dma_addr_t dma_addr; | |
248 | ||
249 | unsigned int __pad[0] ____cacheline_aligned; | |
250 | }; | |
251 | ||
8ceee660 BH |
252 | /** |
253 | * struct efx_rx_queue - An Efx RX queue | |
254 | * @efx: The associated Efx NIC | |
255 | * @queue: DMA queue number | |
8ceee660 BH |
256 | * @channel: The associated channel |
257 | * @buffer: The software buffer ring | |
258 | * @rxd: The hardware descriptor ring | |
259 | * @added_count: Number of buffers added to the receive queue. | |
260 | * @notified_count: Number of buffers given to NIC (<= @added_count). | |
261 | * @removed_count: Number of buffers removed from the receive queue. | |
8ceee660 BH |
262 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
263 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill | |
264 | * (<= @max_fill) | |
265 | * @fast_fill_limit: The level to which a fast fill will fill | |
266 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) | |
267 | * @min_fill: RX descriptor minimum non-zero fill level. | |
268 | * This records the minimum fill level observed when a ring | |
269 | * refill was triggered. | |
270 | * @min_overfill: RX descriptor minimum overflow fill level. | |
271 | * This records the minimum fill level at which RX queue | |
272 | * overflow was observed. It should never be set. | |
273 | * @alloc_page_count: RX allocation strategy counter. | |
274 | * @alloc_skb_count: RX allocation strategy counter. | |
90d683af | 275 | * @slow_fill: Timer used to defer efx_nic_generate_fill_event(). |
6bc5d3a9 | 276 | * @flushed: Use when handling queue flushing |
8ceee660 BH |
277 | */ |
278 | struct efx_rx_queue { | |
279 | struct efx_nic *efx; | |
280 | int queue; | |
8ceee660 BH |
281 | struct efx_channel *channel; |
282 | struct efx_rx_buffer *buffer; | |
283 | struct efx_special_buffer rxd; | |
284 | ||
285 | int added_count; | |
286 | int notified_count; | |
287 | int removed_count; | |
8ceee660 BH |
288 | unsigned int max_fill; |
289 | unsigned int fast_fill_trigger; | |
290 | unsigned int fast_fill_limit; | |
291 | unsigned int min_fill; | |
292 | unsigned int min_overfill; | |
293 | unsigned int alloc_page_count; | |
294 | unsigned int alloc_skb_count; | |
90d683af | 295 | struct timer_list slow_fill; |
8ceee660 BH |
296 | unsigned int slow_fill_count; |
297 | ||
127e6e10 | 298 | enum efx_flush_state flushed; |
8ceee660 BH |
299 | }; |
300 | ||
301 | /** | |
302 | * struct efx_buffer - An Efx general-purpose buffer | |
303 | * @addr: host base address of the buffer | |
304 | * @dma_addr: DMA base address of the buffer | |
305 | * @len: Buffer length, in bytes | |
306 | * | |
754c653a | 307 | * The NIC uses these buffers for its interrupt status registers and |
8ceee660 BH |
308 | * MAC stats dumps. |
309 | */ | |
310 | struct efx_buffer { | |
311 | void *addr; | |
312 | dma_addr_t dma_addr; | |
313 | unsigned int len; | |
314 | }; | |
315 | ||
316 | ||
8ceee660 BH |
317 | enum efx_rx_alloc_method { |
318 | RX_ALLOC_METHOD_AUTO = 0, | |
319 | RX_ALLOC_METHOD_SKB = 1, | |
320 | RX_ALLOC_METHOD_PAGE = 2, | |
321 | }; | |
322 | ||
323 | /** | |
324 | * struct efx_channel - An Efx channel | |
325 | * | |
326 | * A channel comprises an event queue, at least one TX queue, at least | |
327 | * one RX queue, and an associated tasklet for processing the event | |
328 | * queue. | |
329 | * | |
330 | * @efx: Associated Efx NIC | |
8ceee660 | 331 | * @channel: Channel instance number |
56536e9c | 332 | * @name: Name for channel and IRQ |
8ceee660 BH |
333 | * @enabled: Channel enabled indicator |
334 | * @irq: IRQ number (MSI and MSI-X only) | |
0d86ebd8 | 335 | * @irq_moderation: IRQ moderation value (in hardware ticks) |
8ceee660 BH |
336 | * @napi_dev: Net device used with NAPI |
337 | * @napi_str: NAPI control structure | |
338 | * @reset_work: Scheduled reset work thread | |
339 | * @work_pending: Is work pending via NAPI? | |
340 | * @eventq: Event queue buffer | |
341 | * @eventq_read_ptr: Event queue read pointer | |
342 | * @last_eventq_read_ptr: Last event queue read pointer value. | |
d730dc52 | 343 | * @magic_count: Event queue test event count |
6fb70fd1 BH |
344 | * @irq_count: Number of IRQs since last adaptive moderation decision |
345 | * @irq_mod_score: IRQ moderation score | |
8ceee660 BH |
346 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors |
347 | * and diagnostic counters | |
348 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing | |
349 | * descriptors | |
8ceee660 | 350 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
8ceee660 BH |
351 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
352 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors | |
c1ac403b | 353 | * @n_rx_mcast_mismatch: Count of unmatched multicast frames |
8ceee660 BH |
354 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
355 | * @n_rx_overlength: Count of RX_OVERLENGTH errors | |
356 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun | |
a4900ac9 BH |
357 | * @tx_queue: Pointer to first TX queue, or %NULL if not used for TX |
358 | * @tx_stop_count: Core TX queue stop count | |
359 | * @tx_stop_lock: Core TX queue stop lock | |
8ceee660 BH |
360 | */ |
361 | struct efx_channel { | |
362 | struct efx_nic *efx; | |
8ceee660 | 363 | int channel; |
56536e9c | 364 | char name[IFNAMSIZ + 6]; |
dc8cfa55 | 365 | bool enabled; |
8ceee660 | 366 | int irq; |
8ceee660 BH |
367 | unsigned int irq_moderation; |
368 | struct net_device *napi_dev; | |
369 | struct napi_struct napi_str; | |
dc8cfa55 | 370 | bool work_pending; |
8ceee660 BH |
371 | struct efx_special_buffer eventq; |
372 | unsigned int eventq_read_ptr; | |
373 | unsigned int last_eventq_read_ptr; | |
d730dc52 | 374 | unsigned int magic_count; |
8ceee660 | 375 | |
6fb70fd1 BH |
376 | unsigned int irq_count; |
377 | unsigned int irq_mod_score; | |
378 | ||
8ceee660 BH |
379 | int rx_alloc_level; |
380 | int rx_alloc_push_pages; | |
8ceee660 BH |
381 | |
382 | unsigned n_rx_tobe_disc; | |
8ceee660 BH |
383 | unsigned n_rx_ip_hdr_chksum_err; |
384 | unsigned n_rx_tcp_udp_chksum_err; | |
c1ac403b | 385 | unsigned n_rx_mcast_mismatch; |
8ceee660 BH |
386 | unsigned n_rx_frm_trunc; |
387 | unsigned n_rx_overlength; | |
388 | unsigned n_skbuff_leaks; | |
389 | ||
390 | /* Used to pipeline received packets in order to optimise memory | |
391 | * access with prefetches. | |
392 | */ | |
393 | struct efx_rx_buffer *rx_pkt; | |
dc8cfa55 | 394 | bool rx_pkt_csummed; |
8ceee660 | 395 | |
a4900ac9 BH |
396 | struct efx_tx_queue *tx_queue; |
397 | atomic_t tx_stop_count; | |
398 | spinlock_t tx_stop_lock; | |
8ceee660 BH |
399 | }; |
400 | ||
398468ed BH |
401 | enum efx_led_mode { |
402 | EFX_LED_OFF = 0, | |
403 | EFX_LED_ON = 1, | |
404 | EFX_LED_DEFAULT = 2 | |
405 | }; | |
406 | ||
c459302d BH |
407 | #define STRING_TABLE_LOOKUP(val, member) \ |
408 | ((val) < member ## _max) ? member ## _names[val] : "(invalid)" | |
409 | ||
410 | extern const char *efx_loopback_mode_names[]; | |
411 | extern const unsigned int efx_loopback_mode_max; | |
412 | #define LOOPBACK_MODE(efx) \ | |
413 | STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode) | |
414 | ||
415 | extern const char *efx_interrupt_mode_names[]; | |
416 | extern const unsigned int efx_interrupt_mode_max; | |
417 | #define INT_MODE(efx) \ | |
418 | STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode) | |
419 | ||
420 | extern const char *efx_reset_type_names[]; | |
421 | extern const unsigned int efx_reset_type_max; | |
422 | #define RESET_TYPE(type) \ | |
423 | STRING_TABLE_LOOKUP(type, efx_reset_type) | |
3273c2e8 | 424 | |
8ceee660 BH |
425 | enum efx_int_mode { |
426 | /* Be careful if altering to correct macro below */ | |
427 | EFX_INT_MODE_MSIX = 0, | |
428 | EFX_INT_MODE_MSI = 1, | |
429 | EFX_INT_MODE_LEGACY = 2, | |
430 | EFX_INT_MODE_MAX /* Insert any new items before this */ | |
431 | }; | |
432 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) | |
433 | ||
eb50c0d6 | 434 | #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000) |
177dfcd8 | 435 | |
8ceee660 BH |
436 | enum nic_state { |
437 | STATE_INIT = 0, | |
438 | STATE_RUNNING = 1, | |
439 | STATE_FINI = 2, | |
3c78708f | 440 | STATE_DISABLED = 3, |
8ceee660 BH |
441 | STATE_MAX, |
442 | }; | |
443 | ||
444 | /* | |
445 | * Alignment of page-allocated RX buffers | |
446 | * | |
447 | * Controls the number of bytes inserted at the start of an RX buffer. | |
448 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment | |
449 | * of the skb->head for hardware DMA]. | |
450 | */ | |
13e9ab11 | 451 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
8ceee660 BH |
452 | #define EFX_PAGE_IP_ALIGN 0 |
453 | #else | |
454 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN | |
455 | #endif | |
456 | ||
457 | /* | |
458 | * Alignment of the skb->head which wraps a page-allocated RX buffer | |
459 | * | |
460 | * The skb allocated to wrap an rx_buffer can have this alignment. Since | |
461 | * the data is memcpy'd from the rx_buf, it does not need to be equal to | |
462 | * EFX_PAGE_IP_ALIGN. | |
463 | */ | |
464 | #define EFX_PAGE_SKB_ALIGN 2 | |
465 | ||
466 | /* Forward declaration */ | |
467 | struct efx_nic; | |
468 | ||
469 | /* Pseudo bit-mask flow control field */ | |
470 | enum efx_fc_type { | |
3f926da8 BH |
471 | EFX_FC_RX = FLOW_CTRL_RX, |
472 | EFX_FC_TX = FLOW_CTRL_TX, | |
8ceee660 BH |
473 | EFX_FC_AUTO = 4, |
474 | }; | |
475 | ||
eb50c0d6 BH |
476 | /** |
477 | * struct efx_link_state - Current state of the link | |
478 | * @up: Link is up | |
479 | * @fd: Link is full-duplex | |
480 | * @fc: Actual flow control flags | |
481 | * @speed: Link speed (Mbps) | |
482 | */ | |
483 | struct efx_link_state { | |
484 | bool up; | |
485 | bool fd; | |
486 | enum efx_fc_type fc; | |
487 | unsigned int speed; | |
488 | }; | |
489 | ||
fdaa9aed SH |
490 | static inline bool efx_link_state_equal(const struct efx_link_state *left, |
491 | const struct efx_link_state *right) | |
492 | { | |
493 | return left->up == right->up && left->fd == right->fd && | |
494 | left->fc == right->fc && left->speed == right->speed; | |
495 | } | |
496 | ||
177dfcd8 BH |
497 | /** |
498 | * struct efx_mac_operations - Efx MAC operations table | |
499 | * @reconfigure: Reconfigure MAC. Serialised by the mac_lock | |
500 | * @update_stats: Update statistics | |
9007b9fa | 501 | * @check_fault: Check fault state. True if fault present. |
177dfcd8 BH |
502 | */ |
503 | struct efx_mac_operations { | |
d3245b28 | 504 | int (*reconfigure) (struct efx_nic *efx); |
177dfcd8 | 505 | void (*update_stats) (struct efx_nic *efx); |
9007b9fa | 506 | bool (*check_fault)(struct efx_nic *efx); |
177dfcd8 BH |
507 | }; |
508 | ||
8ceee660 BH |
509 | /** |
510 | * struct efx_phy_operations - Efx PHY operations table | |
c1c4f453 BH |
511 | * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds, |
512 | * efx->loopback_modes. | |
8ceee660 BH |
513 | * @init: Initialise PHY |
514 | * @fini: Shut down PHY | |
515 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) | |
fdaa9aed SH |
516 | * @poll: Update @link_state and report whether it changed. |
517 | * Serialised by the mac_lock. | |
177dfcd8 BH |
518 | * @get_settings: Get ethtool settings. Serialised by the mac_lock. |
519 | * @set_settings: Set ethtool settings. Serialised by the mac_lock. | |
af4ad9bc | 520 | * @set_npage_adv: Set abilities advertised in (Extended) Next Page |
04cc8cac | 521 | * (only needed where AN bit is set in mmds) |
4f16c073 | 522 | * @test_alive: Test that PHY is 'alive' (online) |
c1c4f453 | 523 | * @test_name: Get the name of a PHY-specific test/result |
4f16c073 | 524 | * @run_tests: Run tests and record results as appropriate (offline). |
1796721a | 525 | * Flags are the ethtool tests flags. |
8ceee660 BH |
526 | */ |
527 | struct efx_phy_operations { | |
c1c4f453 | 528 | int (*probe) (struct efx_nic *efx); |
8ceee660 BH |
529 | int (*init) (struct efx_nic *efx); |
530 | void (*fini) (struct efx_nic *efx); | |
ff3b00a0 | 531 | void (*remove) (struct efx_nic *efx); |
d3245b28 | 532 | int (*reconfigure) (struct efx_nic *efx); |
fdaa9aed | 533 | bool (*poll) (struct efx_nic *efx); |
177dfcd8 BH |
534 | void (*get_settings) (struct efx_nic *efx, |
535 | struct ethtool_cmd *ecmd); | |
536 | int (*set_settings) (struct efx_nic *efx, | |
537 | struct ethtool_cmd *ecmd); | |
af4ad9bc | 538 | void (*set_npage_adv) (struct efx_nic *efx, u32); |
4f16c073 | 539 | int (*test_alive) (struct efx_nic *efx); |
c1c4f453 | 540 | const char *(*test_name) (struct efx_nic *efx, unsigned int index); |
1796721a | 541 | int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags); |
8ceee660 BH |
542 | }; |
543 | ||
f8b87c17 BH |
544 | /** |
545 | * @enum efx_phy_mode - PHY operating mode flags | |
546 | * @PHY_MODE_NORMAL: on and should pass traffic | |
547 | * @PHY_MODE_TX_DISABLED: on with TX disabled | |
3e133c44 BH |
548 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
549 | * @PHY_MODE_OFF: switched off through external control | |
f8b87c17 BH |
550 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
551 | */ | |
552 | enum efx_phy_mode { | |
553 | PHY_MODE_NORMAL = 0, | |
554 | PHY_MODE_TX_DISABLED = 1, | |
3e133c44 BH |
555 | PHY_MODE_LOW_POWER = 2, |
556 | PHY_MODE_OFF = 4, | |
f8b87c17 BH |
557 | PHY_MODE_SPECIAL = 8, |
558 | }; | |
559 | ||
560 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) | |
561 | { | |
8c8661e4 | 562 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
f8b87c17 BH |
563 | } |
564 | ||
8ceee660 BH |
565 | /* |
566 | * Efx extended statistics | |
567 | * | |
568 | * Not all statistics are provided by all supported MACs. The purpose | |
569 | * is this structure is to contain the raw statistics provided by each | |
570 | * MAC. | |
571 | */ | |
572 | struct efx_mac_stats { | |
573 | u64 tx_bytes; | |
574 | u64 tx_good_bytes; | |
575 | u64 tx_bad_bytes; | |
576 | unsigned long tx_packets; | |
577 | unsigned long tx_bad; | |
578 | unsigned long tx_pause; | |
579 | unsigned long tx_control; | |
580 | unsigned long tx_unicast; | |
581 | unsigned long tx_multicast; | |
582 | unsigned long tx_broadcast; | |
583 | unsigned long tx_lt64; | |
584 | unsigned long tx_64; | |
585 | unsigned long tx_65_to_127; | |
586 | unsigned long tx_128_to_255; | |
587 | unsigned long tx_256_to_511; | |
588 | unsigned long tx_512_to_1023; | |
589 | unsigned long tx_1024_to_15xx; | |
590 | unsigned long tx_15xx_to_jumbo; | |
591 | unsigned long tx_gtjumbo; | |
592 | unsigned long tx_collision; | |
593 | unsigned long tx_single_collision; | |
594 | unsigned long tx_multiple_collision; | |
595 | unsigned long tx_excessive_collision; | |
596 | unsigned long tx_deferred; | |
597 | unsigned long tx_late_collision; | |
598 | unsigned long tx_excessive_deferred; | |
599 | unsigned long tx_non_tcpudp; | |
600 | unsigned long tx_mac_src_error; | |
601 | unsigned long tx_ip_src_error; | |
602 | u64 rx_bytes; | |
603 | u64 rx_good_bytes; | |
604 | u64 rx_bad_bytes; | |
605 | unsigned long rx_packets; | |
606 | unsigned long rx_good; | |
607 | unsigned long rx_bad; | |
608 | unsigned long rx_pause; | |
609 | unsigned long rx_control; | |
610 | unsigned long rx_unicast; | |
611 | unsigned long rx_multicast; | |
612 | unsigned long rx_broadcast; | |
613 | unsigned long rx_lt64; | |
614 | unsigned long rx_64; | |
615 | unsigned long rx_65_to_127; | |
616 | unsigned long rx_128_to_255; | |
617 | unsigned long rx_256_to_511; | |
618 | unsigned long rx_512_to_1023; | |
619 | unsigned long rx_1024_to_15xx; | |
620 | unsigned long rx_15xx_to_jumbo; | |
621 | unsigned long rx_gtjumbo; | |
622 | unsigned long rx_bad_lt64; | |
623 | unsigned long rx_bad_64_to_15xx; | |
624 | unsigned long rx_bad_15xx_to_jumbo; | |
625 | unsigned long rx_bad_gtjumbo; | |
626 | unsigned long rx_overflow; | |
627 | unsigned long rx_missed; | |
628 | unsigned long rx_false_carrier; | |
629 | unsigned long rx_symbol_error; | |
630 | unsigned long rx_align_error; | |
631 | unsigned long rx_length_error; | |
632 | unsigned long rx_internal_error; | |
633 | unsigned long rx_good_lt64; | |
634 | }; | |
635 | ||
636 | /* Number of bits used in a multicast filter hash address */ | |
637 | #define EFX_MCAST_HASH_BITS 8 | |
638 | ||
639 | /* Number of (single-bit) entries in a multicast filter hash */ | |
640 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) | |
641 | ||
642 | /* An Efx multicast filter hash */ | |
643 | union efx_multicast_hash { | |
644 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; | |
645 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; | |
646 | }; | |
647 | ||
648 | /** | |
649 | * struct efx_nic - an Efx NIC | |
650 | * @name: Device name (net device name or bus id before net device registered) | |
651 | * @pci_dev: The PCI device | |
dd8f61d7 | 652 | * @port_num: Index of this host port within the controller |
8ceee660 BH |
653 | * @type: Controller type attributes |
654 | * @legacy_irq: IRQ number | |
8d9853d9 BH |
655 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
656 | * Work items do not hold and must not acquire RTNL. | |
6977dc63 | 657 | * @workqueue_name: Name of workqueue |
8ceee660 BH |
658 | * @reset_work: Scheduled reset workitem |
659 | * @monitor_work: Hardware monitor workitem | |
660 | * @membase_phys: Memory BAR value as physical address | |
661 | * @membase: Memory BAR value | |
662 | * @biu_lock: BIU (bus interface unit) lock | |
663 | * @interrupt_mode: Interrupt mode | |
6fb70fd1 BH |
664 | * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues |
665 | * @irq_rx_moderation: IRQ moderation time for RX event queues | |
8ceee660 BH |
666 | * @state: Device state flag. Serialised by the rtnl_lock. |
667 | * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) | |
668 | * @tx_queue: TX DMA queues | |
669 | * @rx_queue: RX DMA queues | |
670 | * @channel: Channels | |
0484e0db | 671 | * @next_buffer_table: First available buffer table id |
28b581ab | 672 | * @n_channels: Number of channels in use |
a4900ac9 BH |
673 | * @n_rx_channels: Number of channels used for RX (= number of RX queues) |
674 | * @n_tx_channels: Number of channels used for TX | |
8ceee660 BH |
675 | * @rx_buffer_len: RX buffer length |
676 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer | |
0484e0db BH |
677 | * @int_error_count: Number of internal errors seen recently |
678 | * @int_error_expire: Time at which error count will be expired | |
8ceee660 BH |
679 | * @irq_status: Interrupt status buffer |
680 | * @last_irq_cpu: Last CPU to handle interrupt. | |
681 | * This register is written with the SMP processor ID whenever an | |
754c653a | 682 | * interrupt is handled. It is used by efx_nic_test_interrupt() |
8ceee660 | 683 | * to verify that an interrupt has occurred. |
c28884c5 | 684 | * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0 |
63695459 | 685 | * @fatal_irq_level: IRQ level (bit number) used for serious errors |
4a5b504d | 686 | * @spi_flash: SPI flash device |
76884835 | 687 | * This field will be %NULL if no flash device is present (or for Siena). |
4a5b504d | 688 | * @spi_eeprom: SPI EEPROM device |
76884835 | 689 | * This field will be %NULL if no EEPROM device is present (or for Siena). |
f4150724 | 690 | * @spi_lock: SPI bus lock |
76884835 | 691 | * @mtd_list: List of MTDs attached to the NIC |
8ceee660 BH |
692 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
693 | * @nic_data: Hardware dependant state | |
8c8661e4 BH |
694 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
695 | * @port_inhibited, efx_monitor() and efx_reconfigure_port() | |
8ceee660 | 696 | * @port_enabled: Port enabled indicator. |
fdaa9aed SH |
697 | * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and |
698 | * efx_mac_work() with kernel interfaces. Safe to read under any | |
699 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must | |
700 | * be held to modify it. | |
8c8661e4 | 701 | * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock |
8ceee660 BH |
702 | * @port_initialized: Port initialized? |
703 | * @net_dev: Operating system network device. Consider holding the rtnl lock | |
704 | * @rx_checksum_enabled: RX checksumming enabled | |
8ceee660 BH |
705 | * @mac_stats: MAC statistics. These include all statistics the MACs |
706 | * can provide. Generic code converts these into a standard | |
707 | * &struct net_device_stats. | |
708 | * @stats_buffer: DMA buffer for statistics | |
8c8661e4 | 709 | * @stats_lock: Statistics update lock. Serialises statistics fetches |
177dfcd8 | 710 | * @mac_op: MAC interface |
8ceee660 BH |
711 | * @mac_address: Permanent MAC address |
712 | * @phy_type: PHY type | |
ab867461 | 713 | * @mdio_lock: MDIO lock |
8ceee660 BH |
714 | * @phy_op: PHY interface |
715 | * @phy_data: PHY private data (including PHY-specific stats) | |
68e7f45e | 716 | * @mdio: PHY MDIO interface |
8880f4ec | 717 | * @mdio_bus: PHY MDIO bus ID (only used by Siena) |
8c8661e4 | 718 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
9007b9fa | 719 | * @xmac_poll_required: XMAC link state needs polling |
d3245b28 | 720 | * @link_advertising: Autonegotiation advertising flags |
eb50c0d6 | 721 | * @link_state: Current state of the link |
8ceee660 BH |
722 | * @n_link_state_changes: Number of times the link has changed state |
723 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. | |
724 | * @multicast_hash: Multicast hash table | |
04cc8cac | 725 | * @wanted_fc: Wanted flow control flags |
8be4f3e6 | 726 | * @mac_work: Work item for changing MAC promiscuity and multicast hash |
3273c2e8 BH |
727 | * @loopback_mode: Loopback status |
728 | * @loopback_modes: Supported loopback mode bitmask | |
729 | * @loopback_selftest: Offline self-test private state | |
8ceee660 | 730 | * |
754c653a | 731 | * This is stored in the private area of the &struct net_device. |
8ceee660 BH |
732 | */ |
733 | struct efx_nic { | |
734 | char name[IFNAMSIZ]; | |
735 | struct pci_dev *pci_dev; | |
dd8f61d7 | 736 | unsigned port_num; |
8ceee660 BH |
737 | const struct efx_nic_type *type; |
738 | int legacy_irq; | |
739 | struct workqueue_struct *workqueue; | |
6977dc63 | 740 | char workqueue_name[16]; |
8ceee660 BH |
741 | struct work_struct reset_work; |
742 | struct delayed_work monitor_work; | |
086ea356 | 743 | resource_size_t membase_phys; |
8ceee660 BH |
744 | void __iomem *membase; |
745 | spinlock_t biu_lock; | |
746 | enum efx_int_mode interrupt_mode; | |
6fb70fd1 BH |
747 | bool irq_rx_adaptive; |
748 | unsigned int irq_rx_moderation; | |
8ceee660 | 749 | |
8ceee660 BH |
750 | enum nic_state state; |
751 | enum reset_type reset_pending; | |
752 | ||
a4900ac9 | 753 | struct efx_tx_queue tx_queue[EFX_MAX_TX_QUEUES]; |
8ceee660 BH |
754 | struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES]; |
755 | struct efx_channel channel[EFX_MAX_CHANNELS]; | |
756 | ||
0484e0db | 757 | unsigned next_buffer_table; |
a4900ac9 BH |
758 | unsigned n_channels; |
759 | unsigned n_rx_channels; | |
760 | unsigned n_tx_channels; | |
8ceee660 BH |
761 | unsigned int rx_buffer_len; |
762 | unsigned int rx_buffer_order; | |
763 | ||
0484e0db BH |
764 | unsigned int_error_count; |
765 | unsigned long int_error_expire; | |
766 | ||
8ceee660 BH |
767 | struct efx_buffer irq_status; |
768 | volatile signed int last_irq_cpu; | |
c28884c5 | 769 | unsigned irq_zero_count; |
63695459 | 770 | unsigned fatal_irq_level; |
8ceee660 | 771 | |
4a5b504d BH |
772 | struct efx_spi_device *spi_flash; |
773 | struct efx_spi_device *spi_eeprom; | |
f4150724 | 774 | struct mutex spi_lock; |
76884835 BH |
775 | #ifdef CONFIG_SFC_MTD |
776 | struct list_head mtd_list; | |
777 | #endif | |
4a5b504d | 778 | |
8ceee660 BH |
779 | unsigned n_rx_nodesc_drop_cnt; |
780 | ||
8880f4ec | 781 | void *nic_data; |
8ceee660 BH |
782 | |
783 | struct mutex mac_lock; | |
766ca0fa | 784 | struct work_struct mac_work; |
dc8cfa55 | 785 | bool port_enabled; |
8c8661e4 | 786 | bool port_inhibited; |
8ceee660 | 787 | |
dc8cfa55 | 788 | bool port_initialized; |
8ceee660 | 789 | struct net_device *net_dev; |
dc8cfa55 | 790 | bool rx_checksum_enabled; |
8ceee660 | 791 | |
8ceee660 BH |
792 | struct efx_mac_stats mac_stats; |
793 | struct efx_buffer stats_buffer; | |
794 | spinlock_t stats_lock; | |
795 | ||
177dfcd8 | 796 | struct efx_mac_operations *mac_op; |
8ceee660 BH |
797 | unsigned char mac_address[ETH_ALEN]; |
798 | ||
c1c4f453 | 799 | unsigned int phy_type; |
ab867461 | 800 | struct mutex mdio_lock; |
8ceee660 BH |
801 | struct efx_phy_operations *phy_op; |
802 | void *phy_data; | |
68e7f45e | 803 | struct mdio_if_info mdio; |
8880f4ec | 804 | unsigned int mdio_bus; |
f8b87c17 | 805 | enum efx_phy_mode phy_mode; |
8ceee660 | 806 | |
9007b9fa | 807 | bool xmac_poll_required; |
d3245b28 | 808 | u32 link_advertising; |
eb50c0d6 | 809 | struct efx_link_state link_state; |
8ceee660 BH |
810 | unsigned int n_link_state_changes; |
811 | ||
dc8cfa55 | 812 | bool promiscuous; |
8ceee660 | 813 | union efx_multicast_hash multicast_hash; |
04cc8cac | 814 | enum efx_fc_type wanted_fc; |
8ceee660 BH |
815 | |
816 | atomic_t rx_reset; | |
3273c2e8 | 817 | enum efx_loopback_mode loopback_mode; |
e58f69f4 | 818 | u64 loopback_modes; |
3273c2e8 BH |
819 | |
820 | void *loopback_selftest; | |
8ceee660 BH |
821 | }; |
822 | ||
55668611 BH |
823 | static inline int efx_dev_registered(struct efx_nic *efx) |
824 | { | |
825 | return efx->net_dev->reg_state == NETREG_REGISTERED; | |
826 | } | |
827 | ||
828 | /* Net device name, for inclusion in log messages if it has been registered. | |
829 | * Use efx->name not efx->net_dev->name so that races with (un)registration | |
830 | * are harmless. | |
831 | */ | |
832 | static inline const char *efx_dev_name(struct efx_nic *efx) | |
833 | { | |
834 | return efx_dev_registered(efx) ? efx->name : ""; | |
835 | } | |
836 | ||
8880f4ec BH |
837 | static inline unsigned int efx_port_num(struct efx_nic *efx) |
838 | { | |
3df95ce9 | 839 | return efx->net_dev->dev_id; |
8880f4ec BH |
840 | } |
841 | ||
8ceee660 BH |
842 | /** |
843 | * struct efx_nic_type - Efx device type definition | |
ef2b90ee BH |
844 | * @probe: Probe the controller |
845 | * @remove: Free resources allocated by probe() | |
846 | * @init: Initialise the controller | |
847 | * @fini: Shut down the controller | |
848 | * @monitor: Periodic function for polling link state and hardware monitor | |
849 | * @reset: Reset the controller hardware and possibly the PHY. This will | |
850 | * be called while the controller is uninitialised. | |
851 | * @probe_port: Probe the MAC and PHY | |
852 | * @remove_port: Free resources allocated by probe_port() | |
853 | * @prepare_flush: Prepare the hardware for flushing the DMA queues | |
854 | * @update_stats: Update statistics not provided by event handling | |
855 | * @start_stats: Start the regular fetching of statistics | |
856 | * @stop_stats: Stop the regular fetching of statistics | |
06629f07 | 857 | * @set_id_led: Set state of identifying LED or revert to automatic function |
ef2b90ee BH |
858 | * @push_irq_moderation: Apply interrupt moderation value |
859 | * @push_multicast_hash: Apply multicast hash table | |
d3245b28 | 860 | * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY |
89c758fa BH |
861 | * @get_wol: Get WoL configuration from driver state |
862 | * @set_wol: Push WoL configuration to the NIC | |
863 | * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume) | |
9bfc4bb1 | 864 | * @test_registers: Test read/write functionality of control registers |
0aa3fbaa | 865 | * @test_nvram: Test validity of NVRAM contents |
b895d73e | 866 | * @default_mac_ops: efx_mac_operations to set at startup |
daeda630 | 867 | * @revision: Hardware architecture revision |
8ceee660 BH |
868 | * @mem_map_size: Memory BAR mapped size |
869 | * @txd_ptr_tbl_base: TX descriptor ring base address | |
870 | * @rxd_ptr_tbl_base: RX descriptor ring base address | |
871 | * @buf_tbl_base: Buffer table base address | |
872 | * @evq_ptr_tbl_base: Event queue pointer table base address | |
873 | * @evq_rptr_tbl_base: Event queue read-pointer table base address | |
8ceee660 | 874 | * @max_dma_mask: Maximum possible DMA mask |
8ceee660 BH |
875 | * @rx_buffer_padding: Padding added to each RX buffer |
876 | * @max_interrupt_mode: Highest capability interrupt mode supported | |
877 | * from &enum efx_init_mode. | |
878 | * @phys_addr_channels: Number of channels with physically addressed | |
879 | * descriptors | |
0228f5cd BH |
880 | * @tx_dc_base: Base address in SRAM of TX queue descriptor caches |
881 | * @rx_dc_base: Base address in SRAM of RX queue descriptor caches | |
c383b537 BH |
882 | * @offload_features: net_device feature flags for protocol offload |
883 | * features implemented in hardware | |
eb9f6744 BH |
884 | * @reset_world_flags: Flags for additional components covered by |
885 | * reset method RESET_TYPE_WORLD | |
8ceee660 BH |
886 | */ |
887 | struct efx_nic_type { | |
ef2b90ee BH |
888 | int (*probe)(struct efx_nic *efx); |
889 | void (*remove)(struct efx_nic *efx); | |
890 | int (*init)(struct efx_nic *efx); | |
891 | void (*fini)(struct efx_nic *efx); | |
892 | void (*monitor)(struct efx_nic *efx); | |
893 | int (*reset)(struct efx_nic *efx, enum reset_type method); | |
894 | int (*probe_port)(struct efx_nic *efx); | |
895 | void (*remove_port)(struct efx_nic *efx); | |
896 | void (*prepare_flush)(struct efx_nic *efx); | |
897 | void (*update_stats)(struct efx_nic *efx); | |
898 | void (*start_stats)(struct efx_nic *efx); | |
899 | void (*stop_stats)(struct efx_nic *efx); | |
06629f07 | 900 | void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode); |
ef2b90ee BH |
901 | void (*push_irq_moderation)(struct efx_channel *channel); |
902 | void (*push_multicast_hash)(struct efx_nic *efx); | |
d3245b28 | 903 | int (*reconfigure_port)(struct efx_nic *efx); |
89c758fa BH |
904 | void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol); |
905 | int (*set_wol)(struct efx_nic *efx, u32 type); | |
906 | void (*resume_wol)(struct efx_nic *efx); | |
9bfc4bb1 | 907 | int (*test_registers)(struct efx_nic *efx); |
0aa3fbaa | 908 | int (*test_nvram)(struct efx_nic *efx); |
b895d73e SH |
909 | struct efx_mac_operations *default_mac_ops; |
910 | ||
daeda630 | 911 | int revision; |
8ceee660 BH |
912 | unsigned int mem_map_size; |
913 | unsigned int txd_ptr_tbl_base; | |
914 | unsigned int rxd_ptr_tbl_base; | |
915 | unsigned int buf_tbl_base; | |
916 | unsigned int evq_ptr_tbl_base; | |
917 | unsigned int evq_rptr_tbl_base; | |
9bbd7d9a | 918 | u64 max_dma_mask; |
8ceee660 BH |
919 | unsigned int rx_buffer_padding; |
920 | unsigned int max_interrupt_mode; | |
921 | unsigned int phys_addr_channels; | |
0228f5cd BH |
922 | unsigned int tx_dc_base; |
923 | unsigned int rx_dc_base; | |
c383b537 | 924 | unsigned long offload_features; |
eb9f6744 | 925 | u32 reset_world_flags; |
8ceee660 BH |
926 | }; |
927 | ||
928 | /************************************************************************** | |
929 | * | |
930 | * Prototypes and inline functions | |
931 | * | |
932 | *************************************************************************/ | |
933 | ||
934 | /* Iterate over all used channels */ | |
935 | #define efx_for_each_channel(_channel, _efx) \ | |
3d07df11 | 936 | for (_channel = &((_efx)->channel[0]); \ |
a4900ac9 BH |
937 | _channel < &((_efx)->channel[(efx)->n_channels]); \ |
938 | _channel++) | |
8ceee660 | 939 | |
8ceee660 BH |
940 | /* Iterate over all used TX queues */ |
941 | #define efx_for_each_tx_queue(_tx_queue, _efx) \ | |
3d07df11 | 942 | for (_tx_queue = &((_efx)->tx_queue[0]); \ |
a4900ac9 BH |
943 | _tx_queue < &((_efx)->tx_queue[EFX_TXQ_TYPES * \ |
944 | (_efx)->n_tx_channels]); \ | |
60ac1065 | 945 | _tx_queue++) |
8ceee660 BH |
946 | |
947 | /* Iterate over all TX queues belonging to a channel */ | |
948 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ | |
a4900ac9 BH |
949 | for (_tx_queue = (_channel)->tx_queue; \ |
950 | _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \ | |
951 | _tx_queue++) | |
8ceee660 BH |
952 | |
953 | /* Iterate over all used RX queues */ | |
954 | #define efx_for_each_rx_queue(_rx_queue, _efx) \ | |
3d07df11 | 955 | for (_rx_queue = &((_efx)->rx_queue[0]); \ |
a4900ac9 | 956 | _rx_queue < &((_efx)->rx_queue[(_efx)->n_rx_channels]); \ |
8831da7b | 957 | _rx_queue++) |
8ceee660 BH |
958 | |
959 | /* Iterate over all RX queues belonging to a channel */ | |
960 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ | |
3d07df11 | 961 | for (_rx_queue = &((_channel)->efx->rx_queue[(_channel)->channel]); \ |
a2589027 BH |
962 | _rx_queue; \ |
963 | _rx_queue = NULL) \ | |
3d07df11 | 964 | if (_rx_queue->channel != (_channel)) \ |
8ceee660 BH |
965 | continue; \ |
966 | else | |
967 | ||
968 | /* Returns a pointer to the specified receive buffer in the RX | |
969 | * descriptor queue. | |
970 | */ | |
971 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, | |
972 | unsigned int index) | |
973 | { | |
974 | return (&rx_queue->buffer[index]); | |
975 | } | |
976 | ||
977 | /* Set bit in a little-endian bitfield */ | |
18c2fc04 | 978 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
979 | { |
980 | addr[nr / 8] |= (1 << (nr % 8)); | |
981 | } | |
982 | ||
983 | /* Clear bit in a little-endian bitfield */ | |
18c2fc04 | 984 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
8ceee660 BH |
985 | { |
986 | addr[nr / 8] &= ~(1 << (nr % 8)); | |
987 | } | |
988 | ||
989 | ||
990 | /** | |
991 | * EFX_MAX_FRAME_LEN - calculate maximum frame length | |
992 | * | |
993 | * This calculates the maximum frame length that will be used for a | |
994 | * given MTU. The frame length will be equal to the MTU plus a | |
995 | * constant amount of header space and padding. This is the quantity | |
996 | * that the net driver will program into the MAC as the maximum frame | |
997 | * length. | |
998 | * | |
754c653a | 999 | * The 10G MAC requires 8-byte alignment on the frame |
8ceee660 | 1000 | * length, so we round up to the nearest 8. |
cc11763b BH |
1001 | * |
1002 | * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an | |
1003 | * XGMII cycle). If the frame length reaches the maximum value in the | |
1004 | * same cycle, the XMAC can miss the IPG altogether. We work around | |
1005 | * this by adding a further 16 bytes. | |
8ceee660 BH |
1006 | */ |
1007 | #define EFX_MAX_FRAME_LEN(mtu) \ | |
cc11763b | 1008 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16) |
8ceee660 BH |
1009 | |
1010 | ||
1011 | #endif /* EFX_NET_DRIVER_H */ |