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sc92031: use device id directly instead of made-up name
[net-next-2.6.git] / drivers / net / sc92031.c
CommitLineData
bf345707
CEB		 1/* Silan SC92031 PCI Fast Ethernet Adapter driver
2 *
3 * Based on vendor drivers:
4 * Silan Fast Ethernet Netcard Driver:
5 * MODULE_AUTHOR ("gaoyonghong");
6 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
7 * MODULE_LICENSE("GPL");
8 * 8139D Fast Ethernet driver:
9 * (C) 2002 by gaoyonghong
10 * MODULE_AUTHOR ("gaoyonghong");
11 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
12 * MODULE_LICENSE("GPL");
13 * Both are almost identical and seem to be based on pci-skeleton.c
14 *
15 * Rewritten for 2.6 by Cesar Eduardo Barros
16 */
17
18/* Note about set_mac_address: I don't know how to change the hardware
19 * matching, so you need to enable IFF_PROMISC when using it.
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/pci.h>
26#include <linux/dma-mapping.h>
27#include <linux/netdevice.h>
28#include <linux/etherdevice.h>
29#include <linux/ethtool.h>
30#include <linux/crc32.h>
31
32#include <asm/irq.h>
33
bf345707 34#define SC92031_NAME "sc92031"
bf345707
CEB		 35
36/* BAR 0 is MMIO, BAR 1 is PIO */
37#ifndef SC92031_USE_BAR
38#define SC92031_USE_BAR 0
39#endif
40
41/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
42static int multicast_filter_limit = 64;
43module_param(multicast_filter_limit, int, 0);
44MODULE_PARM_DESC(multicast_filter_limit,
45 "Maximum number of filtered multicast addresses");
46
47static int media;
48module_param(media, int, 0);
49MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
50 " 0x01 = 10M half, 0x02 = 10M full,"
51 " 0x04 = 100M half, 0x08 = 100M full)");
52
53/* Size of the in-memory receive ring. */
54#define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
55#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
56
57/* Number of Tx descriptor registers. */
58#define NUM_TX_DESC 4
59
60/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
61#define MAX_ETH_FRAME_SIZE 1536
62
63/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
64#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
65#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
66
67/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
68#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
69
70/* Time in jiffies before concluding the transmitter is hung. */
71#define TX_TIMEOUT (4*HZ)
72
73#define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
74
75/* media options */
76#define AUTOSELECT 0x00
77#define M10_HALF 0x01
78#define M10_FULL 0x02
79#define M100_HALF 0x04
80#define M100_FULL 0x08
81
82 /* Symbolic offsets to registers. */
83enum silan_registers {
84 Config0 = 0x00, // Config0
85 Config1 = 0x04, // Config1
86 RxBufWPtr = 0x08, // Rx buffer writer poiter
87 IntrStatus = 0x0C, // Interrupt status
88 IntrMask = 0x10, // Interrupt mask
89 RxbufAddr = 0x14, // Rx buffer start address
90 RxBufRPtr = 0x18, // Rx buffer read pointer
91 Txstatusall = 0x1C, // Transmit status of all descriptors
92 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
93 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
94 RxConfig = 0x40, // Rx configuration
95 MAC0 = 0x44, // Ethernet hardware address.
96 MAR0 = 0x4C, // Multicast filter.
97 RxStatus0 = 0x54, // Rx status
98 TxConfig = 0x5C, // Tx configuration
99 PhyCtrl = 0x60, // physical control
100 FlowCtrlConfig = 0x64, // flow control
101 Miicmd0 = 0x68, // Mii command0 register
102 Miicmd1 = 0x6C, // Mii command1 register
103 Miistatus = 0x70, // Mii status register
104 Timercnt = 0x74, // Timer counter register
105 TimerIntr = 0x78, // Timer interrupt register
106 PMConfig = 0x7C, // Power Manager configuration
107 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
108 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
109 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
110 TestD0 = 0xD0,
111 TestD4 = 0xD4,
112 TestD8 = 0xD8,
113};
114
115#define MII_BMCR 0 // Basic mode control register
116#define MII_BMSR 1 // Basic mode status register
117#define MII_JAB 16
118#define MII_OutputStatus 24
119
120#define BMCR_FULLDPLX 0x0100 // Full duplex
121#define BMCR_ANRESTART 0x0200 // Auto negotiation restart
122#define BMCR_ANENABLE 0x1000 // Enable auto negotiation
123#define BMCR_SPEED100 0x2000 // Select 100Mbps
124#define BMSR_LSTATUS 0x0004 // Link status
125#define PHY_16_JAB_ENB 0x1000
126#define PHY_16_PORT_ENB 0x1
127
128enum IntrStatusBits {
129 LinkFail = 0x80000000,
130 LinkOK = 0x40000000,
131 TimeOut = 0x20000000,
132 RxOverflow = 0x0040,
133 RxOK = 0x0020,
134 TxOK = 0x0001,
135 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
136};
137
138enum TxStatusBits {
139 TxCarrierLost = 0x20000000,
140 TxAborted = 0x10000000,
141 TxOutOfWindow = 0x08000000,
142 TxNccShift = 22,
143 EarlyTxThresShift = 16,
144 TxStatOK = 0x8000,
145 TxUnderrun = 0x4000,
146 TxOwn = 0x2000,
147};
148
149enum RxStatusBits {
150 RxStatesOK = 0x80000,
151 RxBadAlign = 0x40000,
152 RxHugeFrame = 0x20000,
153 RxSmallFrame = 0x10000,
154 RxCRCOK = 0x8000,
155 RxCrlFrame = 0x4000,
156 Rx_Broadcast = 0x2000,
157 Rx_Multicast = 0x1000,
158 RxAddrMatch = 0x0800,
159 MiiErr = 0x0400,
160};
161
162enum RxConfigBits {
163 RxFullDx = 0x80000000,
164 RxEnb = 0x40000000,
165 RxSmall = 0x20000000,
166 RxHuge = 0x10000000,
167 RxErr = 0x08000000,
168 RxAllphys = 0x04000000,
169 RxMulticast = 0x02000000,
170 RxBroadcast = 0x01000000,
171 RxLoopBack = (1 << 23) | (1 << 22),
172 LowThresholdShift = 12,
173 HighThresholdShift = 2,
174};
175
176enum TxConfigBits {
177 TxFullDx = 0x80000000,
178 TxEnb = 0x40000000,
179 TxEnbPad = 0x20000000,
180 TxEnbHuge = 0x10000000,
181 TxEnbFCS = 0x08000000,
182 TxNoBackOff = 0x04000000,
183 TxEnbPrem = 0x02000000,
184 TxCareLostCrs = 0x1000000,
185 TxExdCollNum = 0xf00000,
186 TxDataRate = 0x80000,
187};
188
189enum PhyCtrlconfigbits {
190 PhyCtrlAne = 0x80000000,
191 PhyCtrlSpd100 = 0x40000000,
192 PhyCtrlSpd10 = 0x20000000,
193 PhyCtrlPhyBaseAddr = 0x1f000000,
194 PhyCtrlDux = 0x800000,
195 PhyCtrlReset = 0x400000,
196};
197
198enum FlowCtrlConfigBits {
199 FlowCtrlFullDX = 0x80000000,
200 FlowCtrlEnb = 0x40000000,
201};
202
203enum Config0Bits {
204 Cfg0_Reset = 0x80000000,
205 Cfg0_Anaoff = 0x40000000,
206 Cfg0_LDPS = 0x20000000,
207};
208
209enum Config1Bits {
210 Cfg1_EarlyRx = 1 << 31,
211 Cfg1_EarlyTx = 1 << 30,
212
213 //rx buffer size
214 Cfg1_Rcv8K = 0x0,
215 Cfg1_Rcv16K = 0x1,
216 Cfg1_Rcv32K = 0x3,
217 Cfg1_Rcv64K = 0x7,
218 Cfg1_Rcv128K = 0xf,
219};
220
221enum MiiCmd0Bits {
222 Mii_Divider = 0x20000000,
223 Mii_WRITE = 0x400000,
224 Mii_READ = 0x200000,
225 Mii_SCAN = 0x100000,
226 Mii_Tamod = 0x80000,
227 Mii_Drvmod = 0x40000,
228 Mii_mdc = 0x20000,
229 Mii_mdoen = 0x10000,
230 Mii_mdo = 0x8000,
231 Mii_mdi = 0x4000,
232};
233
234enum MiiStatusBits {
235 Mii_StatusBusy = 0x80000000,
236};
237
238enum PMConfigBits {
239 PM_Enable = 1 << 31,
240 PM_LongWF = 1 << 30,
241 PM_Magic = 1 << 29,
242 PM_LANWake = 1 << 28,
243 PM_LWPTN = (1 << 27 | 1<< 26),
244 PM_LinkUp = 1 << 25,
245 PM_WakeUp = 1 << 24,
246};
247
248/* Locking rules:
249 * priv->lock protects most of the fields of priv and most of the
250 * hardware registers. It does not have to protect against softirqs
251 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
252 * it also does not need to be used in ->open and ->stop while the
253 * device interrupts are off.
254 * Not having to protect against softirqs is very useful due to heavy
255 * use of mdelay() at _sc92031_reset.
256 * Functions prefixed with _sc92031_ must be called with the lock held;
257 * functions prefixed with sc92031_ must be called without the lock held.
258 * Use mmiowb() before unlocking if the hardware was written to.
259 */
260
261/* Locking rules for the interrupt:
262 * - the interrupt and the tasklet never run at the same time
263 * - neither run between sc92031_disable_interrupts and
264 * sc92031_enable_interrupt
265 */
266
267struct sc92031_priv {
268 spinlock_t lock;
269 /* iomap.h cookie */
270 void __iomem *port_base;
271 /* pci device structure */
272 struct pci_dev *pdev;
273 /* tasklet */
274 struct tasklet_struct tasklet;
275
276 /* CPU address of rx ring */
277 void *rx_ring;
278 /* PCI address of rx ring */
279 dma_addr_t rx_ring_dma_addr;
280 /* PCI address of rx ring read pointer */
281 dma_addr_t rx_ring_tail;
282
283 /* tx ring write index */
284 unsigned tx_head;
285 /* tx ring read index */
286 unsigned tx_tail;
287 /* CPU address of tx bounce buffer */
288 void *tx_bufs;
289 /* PCI address of tx bounce buffer */
290 dma_addr_t tx_bufs_dma_addr;
291
292 /* copies of some hardware registers */
293 u32 intr_status;
294 atomic_t intr_mask;
295 u32 rx_config;
296 u32 tx_config;
297 u32 pm_config;
298
299 /* copy of some flags from dev->flags */
300 unsigned int mc_flags;
301
302 /* for ETHTOOL_GSTATS */
303 u64 tx_timeouts;
304 u64 rx_loss;
305
306 /* for dev->get_stats */
307 long rx_value;
bf345707
CEB		 308};
309
310/* I don't know which registers can be safely read; however, I can guess
311 * MAC0 is one of them. */
312static inline void _sc92031_dummy_read(void __iomem *port_base)
313{
314 ioread32(port_base + MAC0);
315}
316
317static u32 _sc92031_mii_wait(void __iomem *port_base)
318{
319 u32 mii_status;
320
321 do {
322 udelay(10);
323 mii_status = ioread32(port_base + Miistatus);
324 } while (mii_status & Mii_StatusBusy);
325
326 return mii_status;
327}
328
329static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
330{
331 iowrite32(Mii_Divider, port_base + Miicmd0);
332
333 _sc92031_mii_wait(port_base);
334
335 iowrite32(cmd1, port_base + Miicmd1);
336 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
337
338 return _sc92031_mii_wait(port_base);
339}
340
341static void _sc92031_mii_scan(void __iomem *port_base)
342{
343 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
344}
345
346static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
347{
348 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
349}
350
351static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
352{
353 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
354}
355
356static void sc92031_disable_interrupts(struct net_device *dev)
357{
358 struct sc92031_priv *priv = netdev_priv(dev);
359 void __iomem *port_base = priv->port_base;
360
361 /* tell the tasklet/interrupt not to enable interrupts */
362 atomic_set(&priv->intr_mask, 0);
363 wmb();
364
365 /* stop interrupts */
366 iowrite32(0, port_base + IntrMask);
367 _sc92031_dummy_read(port_base);
368 mmiowb();
369
370 /* wait for any concurrent interrupt/tasklet to finish */
371 synchronize_irq(dev->irq);
372 tasklet_disable(&priv->tasklet);
373}
374
375static void sc92031_enable_interrupts(struct net_device *dev)
376{
377 struct sc92031_priv *priv = netdev_priv(dev);
378 void __iomem *port_base = priv->port_base;
379
380 tasklet_enable(&priv->tasklet);
381
382 atomic_set(&priv->intr_mask, IntrBits);
383 wmb();
384
385 iowrite32(IntrBits, port_base + IntrMask);
386 mmiowb();
387}
388
389static void _sc92031_disable_tx_rx(struct net_device *dev)
390{
391 struct sc92031_priv *priv = netdev_priv(dev);
392 void __iomem *port_base = priv->port_base;
393
394 priv->rx_config &= ~RxEnb;
395 priv->tx_config &= ~TxEnb;
396 iowrite32(priv->rx_config, port_base + RxConfig);
397 iowrite32(priv->tx_config, port_base + TxConfig);
398}
399
400static void _sc92031_enable_tx_rx(struct net_device *dev)
401{
402 struct sc92031_priv *priv = netdev_priv(dev);
403 void __iomem *port_base = priv->port_base;
404
405 priv->rx_config |= RxEnb;
406 priv->tx_config |= TxEnb;
407 iowrite32(priv->rx_config, port_base + RxConfig);
408 iowrite32(priv->tx_config, port_base + TxConfig);
409}
410
411static void _sc92031_tx_clear(struct net_device *dev)
412{
413 struct sc92031_priv *priv = netdev_priv(dev);
414
415 while (priv->tx_head - priv->tx_tail > 0) {
416 priv->tx_tail++;
9c28eaea 417 dev->stats.tx_dropped++;
bf345707
CEB		 418 }
419 priv->tx_head = priv->tx_tail = 0;
420}
421
422static void _sc92031_set_mar(struct net_device *dev)
423{
424 struct sc92031_priv *priv = netdev_priv(dev);
425 void __iomem *port_base = priv->port_base;
426 u32 mar0 = 0, mar1 = 0;
427
428 if ((dev->flags & IFF_PROMISC)
429 || dev->mc_count > multicast_filter_limit
430 || (dev->flags & IFF_ALLMULTI))
431 mar0 = mar1 = 0xffffffff;
432 else if (dev->flags & IFF_MULTICAST) {
433 struct dev_mc_list *mc_list;
434
435 for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) {
436 u32 crc;
437 unsigned bit = 0;
438
439 crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr);
440 crc >>= 24;
441
442 if (crc & 0x01) bit |= 0x02;
443 if (crc & 0x02) bit |= 0x01;
444 if (crc & 0x10) bit |= 0x20;
445 if (crc & 0x20) bit |= 0x10;
446 if (crc & 0x40) bit |= 0x08;
447 if (crc & 0x80) bit |= 0x04;
448
449 if (bit > 31)
450 mar0 |= 0x1 << (bit - 32);
451 else
452 mar1 |= 0x1 << bit;
453 }
454 }
455
456 iowrite32(mar0, port_base + MAR0);
457 iowrite32(mar1, port_base + MAR0 + 4);
458}
459
460static void _sc92031_set_rx_config(struct net_device *dev)
461{
462 struct sc92031_priv *priv = netdev_priv(dev);
463 void __iomem *port_base = priv->port_base;
464 unsigned int old_mc_flags;
465 u32 rx_config_bits = 0;
466
467 old_mc_flags = priv->mc_flags;
468
469 if (dev->flags & IFF_PROMISC)
470 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
471 | RxMulticast | RxAllphys;
472
473 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
474 rx_config_bits |= RxMulticast;
475
476 if (dev->flags & IFF_BROADCAST)
477 rx_config_bits |= RxBroadcast;
478
479 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
480 | RxMulticast | RxAllphys);
481 priv->rx_config |= rx_config_bits;
482
483 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
484 | IFF_MULTICAST | IFF_BROADCAST);
485
486 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
487 iowrite32(priv->rx_config, port_base + RxConfig);
488}
489
490static bool _sc92031_check_media(struct net_device *dev)
491{
492 struct sc92031_priv *priv = netdev_priv(dev);
493 void __iomem *port_base = priv->port_base;
494 u16 bmsr;
495
496 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
497 rmb();
498 if (bmsr & BMSR_LSTATUS) {
499 bool speed_100, duplex_full;
500 u32 flow_ctrl_config = 0;
501 u16 output_status = _sc92031_mii_read(port_base,
502 MII_OutputStatus);
503 _sc92031_mii_scan(port_base);
504
505 speed_100 = output_status & 0x2;
506 duplex_full = output_status & 0x4;
507
508 /* Initial Tx/Rx configuration */
509 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
510 priv->tx_config = 0x48800000;
511
512 /* NOTE: vendor driver had dead code here to enable tx padding */
513
514 if (!speed_100)
515 priv->tx_config |= 0x80000;
516
517 // configure rx mode
518 _sc92031_set_rx_config(dev);
519
520 if (duplex_full) {
521 priv->rx_config |= RxFullDx;
522 priv->tx_config |= TxFullDx;
523 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
524 } else {
525 priv->rx_config &= ~RxFullDx;
526 priv->tx_config &= ~TxFullDx;
527 }
528
529 _sc92031_set_mar(dev);
530 _sc92031_set_rx_config(dev);
531 _sc92031_enable_tx_rx(dev);
532 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
533
534 netif_carrier_on(dev);
535
536 if (printk_ratelimit())
537 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
538 dev->name,
539 speed_100 ? "100" : "10",
540 duplex_full ? "full" : "half");
541 return true;
542 } else {
543 _sc92031_mii_scan(port_base);
544
545 netif_carrier_off(dev);
546
547 _sc92031_disable_tx_rx(dev);
548
549 if (printk_ratelimit())
550 printk(KERN_INFO "%s: link down\n", dev->name);
551 return false;
552 }
553}
554
555static void _sc92031_phy_reset(struct net_device *dev)
556{
557 struct sc92031_priv *priv = netdev_priv(dev);
558 void __iomem *port_base = priv->port_base;
559 u32 phy_ctrl;
560
561 phy_ctrl = ioread32(port_base + PhyCtrl);
562 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
563 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
564
565 switch (media) {
566 default:
567 case AUTOSELECT:
568 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
569 break;
570 case M10_HALF:
571 phy_ctrl |= PhyCtrlSpd10;
572 break;
573 case M10_FULL:
574 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
575 break;
576 case M100_HALF:
577 phy_ctrl |= PhyCtrlSpd100;
578 break;
579 case M100_FULL:
580 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
581 break;
582 }
583
584 iowrite32(phy_ctrl, port_base + PhyCtrl);
585 mdelay(10);
586
587 phy_ctrl &= ~PhyCtrlReset;
588 iowrite32(phy_ctrl, port_base + PhyCtrl);
589 mdelay(1);
590
591 _sc92031_mii_write(port_base, MII_JAB,
592 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
593 _sc92031_mii_scan(port_base);
594
595 netif_carrier_off(dev);
596 netif_stop_queue(dev);
597}
598
599static void _sc92031_reset(struct net_device *dev)
600{
601 struct sc92031_priv *priv = netdev_priv(dev);
602 void __iomem *port_base = priv->port_base;
603
604 /* disable PM */
605 iowrite32(0, port_base + PMConfig);
606
607 /* soft reset the chip */
608 iowrite32(Cfg0_Reset, port_base + Config0);
609 mdelay(200);
610
611 iowrite32(0, port_base + Config0);
612 mdelay(10);
613
614 /* disable interrupts */
615 iowrite32(0, port_base + IntrMask);
616
617 /* clear multicast address */
618 iowrite32(0, port_base + MAR0);
619 iowrite32(0, port_base + MAR0 + 4);
620
621 /* init rx ring */
622 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
623 priv->rx_ring_tail = priv->rx_ring_dma_addr;
624
625 /* init tx ring */
626 _sc92031_tx_clear(dev);
627
628 /* clear old register values */
629 priv->intr_status = 0;
630 atomic_set(&priv->intr_mask, 0);
631 priv->rx_config = 0;
632 priv->tx_config = 0;
633 priv->mc_flags = 0;
634
635 /* configure rx buffer size */
636 /* NOTE: vendor driver had dead code here to enable early tx/rx */
637 iowrite32(Cfg1_Rcv64K, port_base + Config1);
638
639 _sc92031_phy_reset(dev);
640 _sc92031_check_media(dev);
641
642 /* calculate rx fifo overflow */
643 priv->rx_value = 0;
644
645 /* enable PM */
646 iowrite32(priv->pm_config, port_base + PMConfig);
647
648 /* clear intr register */
649 ioread32(port_base + IntrStatus);
650}
651
652static void _sc92031_tx_tasklet(struct net_device *dev)
653{
654 struct sc92031_priv *priv = netdev_priv(dev);
655 void __iomem *port_base = priv->port_base;
656
657 unsigned old_tx_tail;
658 unsigned entry;
659 u32 tx_status;
660
661 old_tx_tail = priv->tx_tail;
662 while (priv->tx_head - priv->tx_tail > 0) {
663 entry = priv->tx_tail % NUM_TX_DESC;
664 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
665
666 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
667 break;
668
669 priv->tx_tail++;
670
671 if (tx_status & TxStatOK) {
9c28eaea
SH		 672 dev->stats.tx_bytes += tx_status & 0x1fff;
673 dev->stats.tx_packets++;
bf345707 674 /* Note: TxCarrierLost is always asserted at 100mbps. */
9c28eaea 675 dev->stats.collisions += (tx_status >> 22) & 0xf;
bf345707
CEB		 676 }
677
678 if (tx_status & (TxOutOfWindow | TxAborted)) {
9c28eaea 679 dev->stats.tx_errors++;
bf345707
CEB		 680
681 if (tx_status & TxAborted)
9c28eaea 682 dev->stats.tx_aborted_errors++;
bf345707
CEB		 683
684 if (tx_status & TxCarrierLost)
9c28eaea 685 dev->stats.tx_carrier_errors++;
bf345707
CEB		 686
687 if (tx_status & TxOutOfWindow)
9c28eaea 688 dev->stats.tx_window_errors++;
bf345707
CEB		 689 }
690
691 if (tx_status & TxUnderrun)
9c28eaea 692 dev->stats.tx_fifo_errors++;
bf345707
CEB		 693 }
694
695 if (priv->tx_tail != old_tx_tail)
696 if (netif_queue_stopped(dev))
697 netif_wake_queue(dev);
698}
699
9c28eaea
SH		 700static void _sc92031_rx_tasklet_error(struct net_device *dev,
701 u32 rx_status, unsigned rx_size)
bf345707
CEB		 702{
703 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
9c28eaea
SH		 704 dev->stats.rx_errors++;
705 dev->stats.rx_length_errors++;
bf345707
CEB		 706 }
707
708 if (!(rx_status & RxStatesOK)) {
9c28eaea 709 dev->stats.rx_errors++;
bf345707
CEB		 710
711 if (rx_status & (RxHugeFrame | RxSmallFrame))
9c28eaea 712 dev->stats.rx_length_errors++;
bf345707
CEB		 713
714 if (rx_status & RxBadAlign)
9c28eaea 715 dev->stats.rx_frame_errors++;
bf345707
CEB		 716
717 if (!(rx_status & RxCRCOK))
9c28eaea
SH		 718 dev->stats.rx_crc_errors++;
719 } else {
720 struct sc92031_priv *priv = netdev_priv(dev);
bf345707 721 priv->rx_loss++;
9c28eaea 722 }
bf345707
CEB		 723}
724
725static void _sc92031_rx_tasklet(struct net_device *dev)
726{
727 struct sc92031_priv *priv = netdev_priv(dev);
728 void __iomem *port_base = priv->port_base;
729
730 dma_addr_t rx_ring_head;
731 unsigned rx_len;
732 unsigned rx_ring_offset;
733 void *rx_ring = priv->rx_ring;
734
735 rx_ring_head = ioread32(port_base + RxBufWPtr);
736 rmb();
737
738 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
739 * we need to change it to 32 bits physical address
740 */
741 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
742 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
743 if (rx_ring_head < priv->rx_ring_dma_addr)
744 rx_ring_head += RX_BUF_LEN;
745
746 if (rx_ring_head >= priv->rx_ring_tail)
747 rx_len = rx_ring_head - priv->rx_ring_tail;
748 else
749 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
750
751 if (!rx_len)
752 return;
753
754 if (unlikely(rx_len > RX_BUF_LEN)) {
755 if (printk_ratelimit())
756 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
757 dev->name);
758 return;
759 }
760
761 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
762
763 while (rx_len) {
764 u32 rx_status;
765 unsigned rx_size, rx_size_align, pkt_size;
766 struct sk_buff *skb;
767
768 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
769 rmb();
770
771 rx_size = rx_status >> 20;
772 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
773 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
774
775 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
776
777 if (unlikely(rx_status == 0
778 || rx_size > (MAX_ETH_FRAME_SIZE + 4)
779 || rx_size < 16
780 || !(rx_status & RxStatesOK))) {
9c28eaea 781 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
bf345707
CEB		 782 break;
783 }
784
785 if (unlikely(rx_size_align + 4 > rx_len)) {
786 if (printk_ratelimit())
787 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
788 break;
789 }
790
791 rx_len -= rx_size_align + 4;
792
2723b019 793 skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN);
bf345707
CEB		 794 if (unlikely(!skb)) {
795 if (printk_ratelimit())
796 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
797 dev->name, pkt_size);
798 goto next;
799 }
800
801 skb_reserve(skb, NET_IP_ALIGN);
802
803 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
804 memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset),
805 rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset);
806 memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)),
807 rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset));
808 } else {
809 memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size);
810 }
811
bf345707 812 skb->protocol = eth_type_trans(skb, dev);
bf345707
CEB		 813 netif_rx(skb);
814
9c28eaea
SH		 815 dev->stats.rx_bytes += pkt_size;
816 dev->stats.rx_packets++;
bf345707
CEB		 817
818 if (rx_status & Rx_Multicast)
9c28eaea 819 dev->stats.multicast++;
bf345707
CEB		 820
821 next:
822 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
823 }
824 mb();
825
826 priv->rx_ring_tail = rx_ring_head;
827 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
828}
829
830static void _sc92031_link_tasklet(struct net_device *dev)
831{
bf345707
CEB		 832 if (_sc92031_check_media(dev))
833 netif_wake_queue(dev);
834 else {
835 netif_stop_queue(dev);
9c28eaea 836 dev->stats.tx_carrier_errors++;
bf345707
CEB		 837 }
838}
839
840static void sc92031_tasklet(unsigned long data)
841{
842 struct net_device *dev = (struct net_device *)data;
843 struct sc92031_priv *priv = netdev_priv(dev);
844 void __iomem *port_base = priv->port_base;
845 u32 intr_status, intr_mask;
846
847 intr_status = priv->intr_status;
848
849 spin_lock(&priv->lock);
850
851 if (unlikely(!netif_running(dev)))
852 goto out;
853
854 if (intr_status & TxOK)
855 _sc92031_tx_tasklet(dev);
856
857 if (intr_status & RxOK)
858 _sc92031_rx_tasklet(dev);
859
860 if (intr_status & RxOverflow)
9c28eaea 861 dev->stats.rx_errors++;
bf345707
CEB		 862
863 if (intr_status & TimeOut) {
9c28eaea
SH		 864 dev->stats.rx_errors++;
865 dev->stats.rx_length_errors++;
bf345707
CEB		 866 }
867
868 if (intr_status & (LinkFail | LinkOK))
869 _sc92031_link_tasklet(dev);
870
871out:
872 intr_mask = atomic_read(&priv->intr_mask);
873 rmb();
874
875 iowrite32(intr_mask, port_base + IntrMask);
876 mmiowb();
877
878 spin_unlock(&priv->lock);
879}
880
881static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
882{
883 struct net_device *dev = dev_id;
884 struct sc92031_priv *priv = netdev_priv(dev);
885 void __iomem *port_base = priv->port_base;
886 u32 intr_status, intr_mask;
887
888 /* mask interrupts before clearing IntrStatus */
889 iowrite32(0, port_base + IntrMask);
890 _sc92031_dummy_read(port_base);
891
892 intr_status = ioread32(port_base + IntrStatus);
893 if (unlikely(intr_status == 0xffffffff))
894 return IRQ_NONE; // hardware has gone missing
895
896 intr_status &= IntrBits;
897 if (!intr_status)
898 goto out_none;
899
900 priv->intr_status = intr_status;
901 tasklet_schedule(&priv->tasklet);
902
903 return IRQ_HANDLED;
904
905out_none:
906 intr_mask = atomic_read(&priv->intr_mask);
907 rmb();
908
909 iowrite32(intr_mask, port_base + IntrMask);
910 mmiowb();
911
912 return IRQ_NONE;
913}
914
915static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
916{
917 struct sc92031_priv *priv = netdev_priv(dev);
918 void __iomem *port_base = priv->port_base;
919
920 // FIXME I do not understand what is this trying to do.
921 if (netif_running(dev)) {
922 int temp;
923
924 spin_lock_bh(&priv->lock);
925
926 /* Update the error count. */
927 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
928
929 if (temp == 0xffff) {
930 priv->rx_value += temp;
9c28eaea
SH		 931 dev->stats.rx_fifo_errors = priv->rx_value;
932 } else
933 dev->stats.rx_fifo_errors = temp + priv->rx_value;
bf345707
CEB		 934
935 spin_unlock_bh(&priv->lock);
936 }
937
9c28eaea 938 return &dev->stats;
bf345707
CEB		 939}
940
941static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev)
942{
bf345707
CEB		 943 struct sc92031_priv *priv = netdev_priv(dev);
944 void __iomem *port_base = priv->port_base;
bf345707
CEB		 945 unsigned len;
946 unsigned entry;
947 u32 tx_status;
948
949 if (unlikely(skb->len > TX_BUF_SIZE)) {
9c28eaea 950 dev->stats.tx_dropped++;
bf345707
CEB		 951 goto out;
952 }
953
699784b7 954 spin_lock(&priv->lock);
bf345707
CEB		 955
956 if (unlikely(!netif_carrier_ok(dev))) {
9c28eaea 957 dev->stats.tx_dropped++;
bf345707
CEB		 958 goto out_unlock;
959 }
960
961 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
962
963 entry = priv->tx_head++ % NUM_TX_DESC;
964
965 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
966
967 len = skb->len;
6f94f709 968 if (len < ETH_ZLEN) {
5a0a92e6
GR		 969 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
970 0, ETH_ZLEN - len);
971 len = ETH_ZLEN;
972 }
bf345707
CEB		 973
974 wmb();
975
976 if (len < 100)
977 tx_status = len;
978 else if (len < 300)
979 tx_status = 0x30000 | len;
980 else
981 tx_status = 0x50000 | len;
982
983 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
984 port_base + TxAddr0 + entry * 4);
985 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
986 mmiowb();
987
988 dev->trans_start = jiffies;
989
990 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
991 netif_stop_queue(dev);
992
993out_unlock:
699784b7 994 spin_unlock(&priv->lock);
bf345707
CEB		 995
996out:
997 dev_kfree_skb(skb);
998
26a17b7b 999 return NETDEV_TX_OK;
bf345707
CEB		 1000}
1001
1002static int sc92031_open(struct net_device *dev)
1003{
1004 int err;
1005 struct sc92031_priv *priv = netdev_priv(dev);
1006 struct pci_dev *pdev = priv->pdev;
1007
1008 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
1009 &priv->rx_ring_dma_addr);
1010 if (unlikely(!priv->rx_ring)) {
1011 err = -ENOMEM;
1012 goto out_alloc_rx_ring;
1013 }
1014
1015 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1016 &priv->tx_bufs_dma_addr);
1017 if (unlikely(!priv->tx_bufs)) {
1018 err = -ENOMEM;
1019 goto out_alloc_tx_bufs;
1020 }
1021 priv->tx_head = priv->tx_tail = 0;
1022
1023 err = request_irq(pdev->irq, sc92031_interrupt,
2db6346f 1024 IRQF_SHARED, dev->name, dev);
bf345707
CEB		 1025 if (unlikely(err < 0))
1026 goto out_request_irq;
1027
1028 priv->pm_config = 0;
1029
1030 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
699784b7 1031 spin_lock_bh(&priv->lock);
bf345707
CEB		 1032
1033 _sc92031_reset(dev);
1034 mmiowb();
1035
699784b7 1036 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1037 sc92031_enable_interrupts(dev);
1038
1039 if (netif_carrier_ok(dev))
1040 netif_start_queue(dev);
1041 else
1042 netif_tx_disable(dev);
1043
1044 return 0;
1045
1046out_request_irq:
1047 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1048 priv->tx_bufs_dma_addr);
1049out_alloc_tx_bufs:
1050 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1051 priv->rx_ring_dma_addr);
1052out_alloc_rx_ring:
1053 return err;
1054}
1055
1056static int sc92031_stop(struct net_device *dev)
1057{
1058 struct sc92031_priv *priv = netdev_priv(dev);
1059 struct pci_dev *pdev = priv->pdev;
1060
1061 netif_tx_disable(dev);
1062
1063 /* Disable interrupts, stop Tx and Rx. */
1064 sc92031_disable_interrupts(dev);
1065
699784b7 1066 spin_lock_bh(&priv->lock);
bf345707
CEB		 1067
1068 _sc92031_disable_tx_rx(dev);
1069 _sc92031_tx_clear(dev);
1070 mmiowb();
1071
699784b7 1072 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1073
1074 free_irq(pdev->irq, dev);
1075 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1076 priv->tx_bufs_dma_addr);
1077 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1078 priv->rx_ring_dma_addr);
1079
1080 return 0;
1081}
1082
1083static void sc92031_set_multicast_list(struct net_device *dev)
1084{
1085 struct sc92031_priv *priv = netdev_priv(dev);
1086
1087 spin_lock_bh(&priv->lock);
1088
1089 _sc92031_set_mar(dev);
1090 _sc92031_set_rx_config(dev);
1091 mmiowb();
1092
1093 spin_unlock_bh(&priv->lock);
1094}
1095
1096static void sc92031_tx_timeout(struct net_device *dev)
1097{
1098 struct sc92031_priv *priv = netdev_priv(dev);
1099
1100 /* Disable interrupts by clearing the interrupt mask.*/
1101 sc92031_disable_interrupts(dev);
1102
1103 spin_lock(&priv->lock);
1104
1105 priv->tx_timeouts++;
1106
1107 _sc92031_reset(dev);
1108 mmiowb();
1109
1110 spin_unlock(&priv->lock);
1111
1112 /* enable interrupts */
1113 sc92031_enable_interrupts(dev);
1114
1115 if (netif_carrier_ok(dev))
1116 netif_wake_queue(dev);
1117}
1118
1119#ifdef CONFIG_NET_POLL_CONTROLLER
1120static void sc92031_poll_controller(struct net_device *dev)
1121{
1122 disable_irq(dev->irq);
1123 if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE)
1124 sc92031_tasklet((unsigned long)dev);
1125 enable_irq(dev->irq);
1126}
1127#endif
1128
1129static int sc92031_ethtool_get_settings(struct net_device *dev,
1130 struct ethtool_cmd *cmd)
1131{
1132 struct sc92031_priv *priv = netdev_priv(dev);
1133 void __iomem *port_base = priv->port_base;
1134 u8 phy_address;
1135 u32 phy_ctrl;
1136 u16 output_status;
1137
1138 spin_lock_bh(&priv->lock);
1139
1140 phy_address = ioread32(port_base + Miicmd1) >> 27;
1141 phy_ctrl = ioread32(port_base + PhyCtrl);
1142
1143 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1144 _sc92031_mii_scan(port_base);
1145 mmiowb();
1146
1147 spin_unlock_bh(&priv->lock);
1148
1149 cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1150 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1151 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1152
1153 cmd->advertising = ADVERTISED_TP | ADVERTISED_MII;
1154
1155 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1156 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1157 cmd->advertising |= ADVERTISED_Autoneg;
1158
1159 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1160 cmd->advertising |= ADVERTISED_10baseT_Half;
1161
1162 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1163 == (PhyCtrlSpd10 | PhyCtrlDux))
1164 cmd->advertising |= ADVERTISED_10baseT_Full;
1165
1166 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1167 cmd->advertising |= ADVERTISED_100baseT_Half;
1168
1169 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1170 == (PhyCtrlSpd100 | PhyCtrlDux))
1171 cmd->advertising |= ADVERTISED_100baseT_Full;
1172
1173 if (phy_ctrl & PhyCtrlAne)
1174 cmd->advertising |= ADVERTISED_Autoneg;
1175
1176 cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1177 cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1178 cmd->port = PORT_MII;
1179 cmd->phy_address = phy_address;
1180 cmd->transceiver = XCVR_INTERNAL;
1181 cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE;
1182
1183 return 0;
1184}
1185
1186static int sc92031_ethtool_set_settings(struct net_device *dev,
1187 struct ethtool_cmd *cmd)
1188{
1189 struct sc92031_priv *priv = netdev_priv(dev);
1190 void __iomem *port_base = priv->port_base;
1191 u32 phy_ctrl;
1192 u32 old_phy_ctrl;
1193
1194 if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100))
1195 return -EINVAL;
1196 if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL))
1197 return -EINVAL;
1198 if (!(cmd->port == PORT_MII))
1199 return -EINVAL;
1200 if (!(cmd->phy_address == 0x1f))
1201 return -EINVAL;
1202 if (!(cmd->transceiver == XCVR_INTERNAL))
1203 return -EINVAL;
1204 if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE))
1205 return -EINVAL;
1206
1207 if (cmd->autoneg == AUTONEG_ENABLE) {
1208 if (!(cmd->advertising & (ADVERTISED_Autoneg
1209 | ADVERTISED_100baseT_Full
1210 | ADVERTISED_100baseT_Half
1211 | ADVERTISED_10baseT_Full
1212 | ADVERTISED_10baseT_Half)))
1213 return -EINVAL;
1214
1215 phy_ctrl = PhyCtrlAne;
1216
1217 // FIXME: I'm not sure what the original code was trying to do
1218 if (cmd->advertising & ADVERTISED_Autoneg)
1219 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1220 if (cmd->advertising & ADVERTISED_100baseT_Full)
1221 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1222 if (cmd->advertising & ADVERTISED_100baseT_Half)
1223 phy_ctrl |= PhyCtrlSpd100;
1224 if (cmd->advertising & ADVERTISED_10baseT_Full)
1225 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1226 if (cmd->advertising & ADVERTISED_10baseT_Half)
1227 phy_ctrl |= PhyCtrlSpd10;
1228 } else {
1229 // FIXME: Whole branch guessed
1230 phy_ctrl = 0;
1231
1232 if (cmd->speed == SPEED_10)
1233 phy_ctrl |= PhyCtrlSpd10;
1234 else /* cmd->speed == SPEED_100 */
1235 phy_ctrl |= PhyCtrlSpd100;
1236
1237 if (cmd->duplex == DUPLEX_FULL)
1238 phy_ctrl |= PhyCtrlDux;
1239 }
1240
1241 spin_lock_bh(&priv->lock);
1242
1243 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1244 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1245 | PhyCtrlSpd100 | PhyCtrlSpd10);
1246 if (phy_ctrl != old_phy_ctrl)
1247 iowrite32(phy_ctrl, port_base + PhyCtrl);
1248
1249 spin_unlock_bh(&priv->lock);
1250
1251 return 0;
1252}
1253
1254static void sc92031_ethtool_get_drvinfo(struct net_device *dev,
1255 struct ethtool_drvinfo *drvinfo)
1256{
1257 struct sc92031_priv *priv = netdev_priv(dev);
1258 struct pci_dev *pdev = priv->pdev;
1259
1260 strcpy(drvinfo->driver, SC92031_NAME);
bf345707
CEB		 1261 strcpy(drvinfo->bus_info, pci_name(pdev));
1262}
1263
1264static void sc92031_ethtool_get_wol(struct net_device *dev,
1265 struct ethtool_wolinfo *wolinfo)
1266{
1267 struct sc92031_priv *priv = netdev_priv(dev);
1268 void __iomem *port_base = priv->port_base;
1269 u32 pm_config;
1270
1271 spin_lock_bh(&priv->lock);
1272 pm_config = ioread32(port_base + PMConfig);
1273 spin_unlock_bh(&priv->lock);
1274
1275 // FIXME: Guessed
1276 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1277 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1278 wolinfo->wolopts = 0;
1279
1280 if (pm_config & PM_LinkUp)
1281 wolinfo->wolopts |= WAKE_PHY;
1282
1283 if (pm_config & PM_Magic)
1284 wolinfo->wolopts |= WAKE_MAGIC;
1285
1286 if (pm_config & PM_WakeUp)
1287 // FIXME: Guessed
1288 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1289}
1290
1291static int sc92031_ethtool_set_wol(struct net_device *dev,
1292 struct ethtool_wolinfo *wolinfo)
1293{
1294 struct sc92031_priv *priv = netdev_priv(dev);
1295 void __iomem *port_base = priv->port_base;
1296 u32 pm_config;
1297
1298 spin_lock_bh(&priv->lock);
1299
1300 pm_config = ioread32(port_base + PMConfig)
1301 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1302
1303 if (wolinfo->wolopts & WAKE_PHY)
1304 pm_config |= PM_LinkUp;
1305
1306 if (wolinfo->wolopts & WAKE_MAGIC)
1307 pm_config |= PM_Magic;
1308
1309 // FIXME: Guessed
1310 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1311 pm_config |= PM_WakeUp;
1312
1313 priv->pm_config = pm_config;
1314 iowrite32(pm_config, port_base + PMConfig);
1315 mmiowb();
1316
1317 spin_unlock_bh(&priv->lock);
1318
1319 return 0;
1320}
1321
1322static int sc92031_ethtool_nway_reset(struct net_device *dev)
1323{
1324 int err = 0;
1325 struct sc92031_priv *priv = netdev_priv(dev);
1326 void __iomem *port_base = priv->port_base;
1327 u16 bmcr;
1328
1329 spin_lock_bh(&priv->lock);
1330
1331 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1332 if (!(bmcr & BMCR_ANENABLE)) {
1333 err = -EINVAL;
1334 goto out;
1335 }
1336
1337 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1338
1339out:
1340 _sc92031_mii_scan(port_base);
1341 mmiowb();
1342
1343 spin_unlock_bh(&priv->lock);
1344
1345 return err;
1346}
1347
1348static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1349 "tx_timeout",
1350 "rx_loss",
1351};
1352
1353static void sc92031_ethtool_get_strings(struct net_device *dev,
1354 u32 stringset, u8 *data)
1355{
1356 if (stringset == ETH_SS_STATS)
1357 memcpy(data, sc92031_ethtool_stats_strings,
1358 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1359}
1360
b9f2c044 1361static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
bf345707 1362{
b9f2c044
JG		 1363 switch (sset) {
1364 case ETH_SS_STATS:
1365 return SILAN_STATS_NUM;
1366 default:
1367 return -EOPNOTSUPP;
1368 }
bf345707
CEB		 1369}
1370
1371static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1372 struct ethtool_stats *stats, u64 *data)
1373{
1374 struct sc92031_priv *priv = netdev_priv(dev);
1375
1376 spin_lock_bh(&priv->lock);
1377 data[0] = priv->tx_timeouts;
1378 data[1] = priv->rx_loss;
1379 spin_unlock_bh(&priv->lock);
1380}
1381
974acda0 1382static const struct ethtool_ops sc92031_ethtool_ops = {
bf345707
CEB		 1383 .get_settings = sc92031_ethtool_get_settings,
1384 .set_settings = sc92031_ethtool_set_settings,
1385 .get_drvinfo = sc92031_ethtool_get_drvinfo,
1386 .get_wol = sc92031_ethtool_get_wol,
1387 .set_wol = sc92031_ethtool_set_wol,
1388 .nway_reset = sc92031_ethtool_nway_reset,
1389 .get_link = ethtool_op_get_link,
bf345707 1390 .get_strings = sc92031_ethtool_get_strings,
b9f2c044 1391 .get_sset_count = sc92031_ethtool_get_sset_count,
bf345707 1392 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
bf345707
CEB		 1393};
1394
974acda0
SH		 1395
1396static const struct net_device_ops sc92031_netdev_ops = {
1397 .ndo_get_stats = sc92031_get_stats,
1398 .ndo_start_xmit = sc92031_start_xmit,
1399 .ndo_open = sc92031_open,
1400 .ndo_stop = sc92031_stop,
1401 .ndo_set_multicast_list = sc92031_set_multicast_list,
1402 .ndo_change_mtu = eth_change_mtu,
1403 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 1404 .ndo_set_mac_address = eth_mac_addr,
974acda0
SH		 1405 .ndo_tx_timeout = sc92031_tx_timeout,
1406#ifdef CONFIG_NET_POLL_CONTROLLER
1407 .ndo_poll_controller = sc92031_poll_controller,
1408#endif
1409};
1410
bf345707
CEB		 1411static int __devinit sc92031_probe(struct pci_dev *pdev,
1412 const struct pci_device_id *id)
1413{
1414 int err;
1415 void __iomem* port_base;
1416 struct net_device *dev;
1417 struct sc92031_priv *priv;
1418 u32 mac0, mac1;
eb5c8bc1 1419 unsigned long base_addr;
bf345707
CEB		 1420
1421 err = pci_enable_device(pdev);
1422 if (unlikely(err < 0))
1423 goto out_enable_device;
1424
1425 pci_set_master(pdev);
1426
1427 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1428 if (unlikely(err < 0))
1429 goto out_set_dma_mask;
1430
1431 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1432 if (unlikely(err < 0))
1433 goto out_set_dma_mask;
1434
1435 err = pci_request_regions(pdev, SC92031_NAME);
1436 if (unlikely(err < 0))
1437 goto out_request_regions;
1438
1439 port_base = pci_iomap(pdev, SC92031_USE_BAR, 0);
1440 if (unlikely(!port_base)) {
1441 err = -EIO;
1442 goto out_iomap;
1443 }
1444
1445 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1446 if (unlikely(!dev)) {
1447 err = -ENOMEM;
1448 goto out_alloc_etherdev;
1449 }
1450
1451 pci_set_drvdata(pdev, dev);
5a81f143 1452 SET_NETDEV_DEV(dev, &pdev->dev);
bf345707
CEB		 1453
1454#if SC92031_USE_BAR == 0
1455 dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR);
1456 dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR);
1457#elif SC92031_USE_BAR == 1
1458 dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR);
1459#endif
1460 dev->irq = pdev->irq;
1461
1462 /* faked with skb_copy_and_csum_dev */
1463 dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1464
974acda0 1465 dev->netdev_ops = &sc92031_netdev_ops;
bf345707 1466 dev->watchdog_timeo = TX_TIMEOUT;
974acda0 1467 dev->ethtool_ops = &sc92031_ethtool_ops;
bf345707
CEB		 1468
1469 priv = netdev_priv(dev);
1470 spin_lock_init(&priv->lock);
1471 priv->port_base = port_base;
1472 priv->pdev = pdev;
1473 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1474 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1475 * sc92031_open will work correctly */
1476 tasklet_disable_nosync(&priv->tasklet);
1477
1478 /* PCI PM Wakeup */
1479 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1480
1481 mac0 = ioread32(port_base + MAC0);
1482 mac1 = ioread32(port_base + MAC0 + 4);
1483 dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24;
1484 dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16;
1485 dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8;
1486 dev->dev_addr[3] = dev->perm_addr[3] = mac0;
1487 dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8;
1488 dev->dev_addr[5] = dev->perm_addr[5] = mac1;
1489
1490 err = register_netdev(dev);
1491 if (err < 0)
1492 goto out_register_netdev;
1493
eb5c8bc1
CEB		 1494#if SC92031_USE_BAR == 0
1495 base_addr = dev->mem_start;
1496#elif SC92031_USE_BAR == 1
1497 base_addr = dev->base_addr;
1498#endif
1499 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1500 base_addr, dev->dev_addr, dev->irq);
1501
bf345707
CEB		 1502 return 0;
1503
1504out_register_netdev:
1505 free_netdev(dev);
1506out_alloc_etherdev:
1507 pci_iounmap(pdev, port_base);
1508out_iomap:
1509 pci_release_regions(pdev);
1510out_request_regions:
1511out_set_dma_mask:
1512 pci_disable_device(pdev);
1513out_enable_device:
1514 return err;
1515}
1516
1517static void __devexit sc92031_remove(struct pci_dev *pdev)
1518{
1519 struct net_device *dev = pci_get_drvdata(pdev);
1520 struct sc92031_priv *priv = netdev_priv(dev);
1521 void __iomem* port_base = priv->port_base;
1522
1523 unregister_netdev(dev);
1524 free_netdev(dev);
1525 pci_iounmap(pdev, port_base);
1526 pci_release_regions(pdev);
1527 pci_disable_device(pdev);
1528}
1529
1530static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1531{
1532 struct net_device *dev = pci_get_drvdata(pdev);
1533 struct sc92031_priv *priv = netdev_priv(dev);
1534
1535 pci_save_state(pdev);
1536
1537 if (!netif_running(dev))
1538 goto out;
1539
1540 netif_device_detach(dev);
1541
1542 /* Disable interrupts, stop Tx and Rx. */
1543 sc92031_disable_interrupts(dev);
1544
699784b7 1545 spin_lock_bh(&priv->lock);
bf345707
CEB		 1546
1547 _sc92031_disable_tx_rx(dev);
1548 _sc92031_tx_clear(dev);
1549 mmiowb();
1550
699784b7 1551 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1552
1553out:
1554 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1555
1556 return 0;
1557}
1558
1559static int sc92031_resume(struct pci_dev *pdev)
1560{
1561 struct net_device *dev = pci_get_drvdata(pdev);
1562 struct sc92031_priv *priv = netdev_priv(dev);
1563
1564 pci_restore_state(pdev);
1565 pci_set_power_state(pdev, PCI_D0);
1566
1567 if (!netif_running(dev))
1568 goto out;
1569
1570 /* Interrupts already disabled by sc92031_suspend */
699784b7 1571 spin_lock_bh(&priv->lock);
bf345707
CEB		 1572
1573 _sc92031_reset(dev);
1574 mmiowb();
1575
699784b7 1576 spin_unlock_bh(&priv->lock);
bf345707
CEB		 1577 sc92031_enable_interrupts(dev);
1578
1579 netif_device_attach(dev);
1580
1581 if (netif_carrier_ok(dev))
1582 netif_wake_queue(dev);
1583 else
1584 netif_tx_disable(dev);
1585
1586out:
1587 return 0;
1588}
1589
1590static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = {
5ec99fdf
CEB		 1591 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1592 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
bf345707
CEB		 1593 { 0, }
1594};
1595MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1596
1597static struct pci_driver sc92031_pci_driver = {
1598 .name = SC92031_NAME,
1599 .id_table = sc92031_pci_device_id_table,
1600 .probe = sc92031_probe,
1601 .remove = __devexit_p(sc92031_remove),
1602 .suspend = sc92031_suspend,
1603 .resume = sc92031_resume,
1604};
1605
1606static int __init sc92031_init(void)
1607{
bf345707
CEB		 1608 return pci_register_driver(&sc92031_pci_driver);
1609}
1610
1611static void __exit sc92031_exit(void)
1612{
1613 pci_unregister_driver(&sc92031_pci_driver);
1614}
1615
1616module_init(sc92031_init);
1617module_exit(sc92031_exit);
1618
1619MODULE_LICENSE("GPL");
1620MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
f08d7c36 1621MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");
Clone of davem's net-next-2.6 tree