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[PATCH] r8169: de-obfuscate supported PCI ID
[net-next-2.6.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
72#define RTL8169_VERSION "2.2LK"
73#define MODULENAME "r8169"
74#define PFX MODULENAME ": "
75
76#ifdef RTL8169_DEBUG
77#define assert(expr) \
78 if(!(expr)) { \
79 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
80 #expr,__FILE__,__FUNCTION__,__LINE__); \
81 }
82#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
83#else
84#define assert(expr) do {} while (0)
85#define dprintk(fmt, args...) do {} while (0)
86#endif /* RTL8169_DEBUG */
87
88#define TX_BUFFS_AVAIL(tp) \
89 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
90
91#ifdef CONFIG_R8169_NAPI
92#define rtl8169_rx_skb netif_receive_skb
93#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
94#define rtl8169_rx_quota(count, quota) min(count, quota)
95#else
96#define rtl8169_rx_skb netif_rx
97#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
98#define rtl8169_rx_quota(count, quota) count
99#endif
100
101/* media options */
102#define MAX_UNITS 8
103static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
104static int num_media = 0;
105
106/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
107static int max_interrupt_work = 20;
108
109/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
110 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
111static int multicast_filter_limit = 32;
112
113/* MAC address length */
114#define MAC_ADDR_LEN 6
115
116#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
117#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
118#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
119#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
120#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
121#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
122#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
123
124#define R8169_REGS_SIZE 256
125#define R8169_NAPI_WEIGHT 64
126#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
127#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
128#define RX_BUF_SIZE 1536 /* Rx Buffer size */
129#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
130#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
131
132#define RTL8169_TX_TIMEOUT (6*HZ)
133#define RTL8169_PHY_TIMEOUT (10*HZ)
134
135/* write/read MMIO register */
136#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
137#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
138#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
139#define RTL_R8(reg) readb (ioaddr + (reg))
140#define RTL_R16(reg) readw (ioaddr + (reg))
141#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
142
143enum mac_version {
144 RTL_GIGA_MAC_VER_B = 0x00,
145 /* RTL_GIGA_MAC_VER_C = 0x03, */
146 RTL_GIGA_MAC_VER_D = 0x01,
147 RTL_GIGA_MAC_VER_E = 0x02,
148 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
149};
150
151enum phy_version {
152 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
153 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
154 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
155 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
156 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
157 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
158};
159
160
161#define _R(NAME,MAC,MASK) \
162 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
163
164const static struct {
165 const char *name;
166 u8 mac_version;
167 u32 RxConfigMask; /* Clears the bits supported by this chip */
168} rtl_chip_info[] = {
169 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
170 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
171 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
172 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
173};
174#undef _R
175
176static struct pci_device_id rtl8169_pci_tbl[] = {
53456f60
FR		 177 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
178 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
179 { PCI_DEVICE(0x16ec, 0x0116), },
1da177e4
LT		 180 {0,},
181};
182
183MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
184
185static int rx_copybreak = 200;
186static int use_dac;
187
188enum RTL8169_registers {
189 MAC0 = 0, /* Ethernet hardware address. */
190 MAR0 = 8, /* Multicast filter. */
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3C,
200 IntrStatus = 0x3E,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4C,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5C,
212 PHYAR = 0x60,
213 TBICSR = 0x64,
214 TBI_ANAR = 0x68,
215 TBI_LPAR = 0x6A,
216 PHYstatus = 0x6C,
217 RxMaxSize = 0xDA,
218 CPlusCmd = 0xE0,
219 IntrMitigate = 0xE2,
220 RxDescAddrLow = 0xE4,
221 RxDescAddrHigh = 0xE8,
222 EarlyTxThres = 0xEC,
223 FuncEvent = 0xF0,
224 FuncEventMask = 0xF4,
225 FuncPresetState = 0xF8,
226 FuncForceEvent = 0xFC,
227};
228
229enum RTL8169_register_content {
230 /* InterruptStatusBits */
231 SYSErr = 0x8000,
232 PCSTimeout = 0x4000,
233 SWInt = 0x0100,
234 TxDescUnavail = 0x80,
235 RxFIFOOver = 0x40,
236 LinkChg = 0x20,
237 RxOverflow = 0x10,
238 TxErr = 0x08,
239 TxOK = 0x04,
240 RxErr = 0x02,
241 RxOK = 0x01,
242
243 /* RxStatusDesc */
244 RxRES = 0x00200000,
245 RxCRC = 0x00080000,
246 RxRUNT = 0x00100000,
247 RxRWT = 0x00400000,
248
249 /* ChipCmdBits */
250 CmdReset = 0x10,
251 CmdRxEnb = 0x08,
252 CmdTxEnb = 0x04,
253 RxBufEmpty = 0x01,
254
255 /* Cfg9346Bits */
256 Cfg9346_Lock = 0x00,
257 Cfg9346_Unlock = 0xC0,
258
259 /* rx_mode_bits */
260 AcceptErr = 0x20,
261 AcceptRunt = 0x10,
262 AcceptBroadcast = 0x08,
263 AcceptMulticast = 0x04,
264 AcceptMyPhys = 0x02,
265 AcceptAllPhys = 0x01,
266
267 /* RxConfigBits */
268 RxCfgFIFOShift = 13,
269 RxCfgDMAShift = 8,
270
271 /* TxConfigBits */
272 TxInterFrameGapShift = 24,
273 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
274
275 /* TBICSR p.28 */
276 TBIReset = 0x80000000,
277 TBILoopback = 0x40000000,
278 TBINwEnable = 0x20000000,
279 TBINwRestart = 0x10000000,
280 TBILinkOk = 0x02000000,
281 TBINwComplete = 0x01000000,
282
283 /* CPlusCmd p.31 */
284 RxVlan = (1 << 6),
285 RxChkSum = (1 << 5),
286 PCIDAC = (1 << 4),
287 PCIMulRW = (1 << 3),
288
289 /* rtl8169_PHYstatus */
290 TBI_Enable = 0x80,
291 TxFlowCtrl = 0x40,
292 RxFlowCtrl = 0x20,
293 _1000bpsF = 0x10,
294 _100bps = 0x08,
295 _10bps = 0x04,
296 LinkStatus = 0x02,
297 FullDup = 0x01,
298
299 /* GIGABIT_PHY_registers */
300 PHY_CTRL_REG = 0,
301 PHY_STAT_REG = 1,
302 PHY_AUTO_NEGO_REG = 4,
303 PHY_1000_CTRL_REG = 9,
304
305 /* GIGABIT_PHY_REG_BIT */
306 PHY_Restart_Auto_Nego = 0x0200,
307 PHY_Enable_Auto_Nego = 0x1000,
308
309 /* PHY_STAT_REG = 1 */
310 PHY_Auto_Neco_Comp = 0x0020,
311
312 /* PHY_AUTO_NEGO_REG = 4 */
313 PHY_Cap_10_Half = 0x0020,
314 PHY_Cap_10_Full = 0x0040,
315 PHY_Cap_100_Half = 0x0080,
316 PHY_Cap_100_Full = 0x0100,
317
318 /* PHY_1000_CTRL_REG = 9 */
319 PHY_Cap_1000_Full = 0x0200,
320
321 PHY_Cap_Null = 0x0,
322
323 /* _MediaType */
324 _10_Half = 0x01,
325 _10_Full = 0x02,
326 _100_Half = 0x04,
327 _100_Full = 0x08,
328 _1000_Full = 0x10,
329
330 /* _TBICSRBit */
331 TBILinkOK = 0x02000000,
332};
333
334enum _DescStatusBit {
335 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
336 RingEnd = (1 << 30), /* End of descriptor ring */
337 FirstFrag = (1 << 29), /* First segment of a packet */
338 LastFrag = (1 << 28), /* Final segment of a packet */
339
340 /* Tx private */
341 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
342 MSSShift = 16, /* MSS value position */
343 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
344 IPCS = (1 << 18), /* Calculate IP checksum */
345 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
346 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
347 TxVlanTag = (1 << 17), /* Add VLAN tag */
348
349 /* Rx private */
350 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
351 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
352
353#define RxProtoUDP (PID1)
354#define RxProtoTCP (PID0)
355#define RxProtoIP (PID1 | PID0)
356#define RxProtoMask RxProtoIP
357
358 IPFail = (1 << 16), /* IP checksum failed */
359 UDPFail = (1 << 15), /* UDP/IP checksum failed */
360 TCPFail = (1 << 14), /* TCP/IP checksum failed */
361 RxVlanTag = (1 << 16), /* VLAN tag available */
362};
363
364#define RsvdMask 0x3fffc000
365
366struct TxDesc {
367 u32 opts1;
368 u32 opts2;
369 u64 addr;
370};
371
372struct RxDesc {
373 u32 opts1;
374 u32 opts2;
375 u64 addr;
376};
377
378struct ring_info {
379 struct sk_buff *skb;
380 u32 len;
381 u8 __pad[sizeof(void *) - sizeof(u32)];
382};
383
384struct rtl8169_private {
385 void __iomem *mmio_addr; /* memory map physical address */
386 struct pci_dev *pci_dev; /* Index of PCI device */
387 struct net_device_stats stats; /* statistics of net device */
388 spinlock_t lock; /* spin lock flag */
389 int chipset;
390 int mac_version;
391 int phy_version;
392 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
393 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
394 u32 dirty_rx;
395 u32 dirty_tx;
396 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
397 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
398 dma_addr_t TxPhyAddr;
399 dma_addr_t RxPhyAddr;
400 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
401 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
402 unsigned rx_buf_sz;
403 struct timer_list timer;
404 u16 cp_cmd;
405 u16 intr_mask;
406 int phy_auto_nego_reg;
407 int phy_1000_ctrl_reg;
408#ifdef CONFIG_R8169_VLAN
409 struct vlan_group *vlgrp;
410#endif
411 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
412 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
413 void (*phy_reset_enable)(void __iomem *);
414 unsigned int (*phy_reset_pending)(void __iomem *);
415 unsigned int (*link_ok)(void __iomem *);
416 struct work_struct task;
417};
418
419MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@oss.sgi.com>");
420MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
421module_param_array(media, int, &num_media, 0);
422module_param(rx_copybreak, int, 0);
423module_param(use_dac, int, 0);
424MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
425MODULE_LICENSE("GPL");
426MODULE_VERSION(RTL8169_VERSION);
427
428static int rtl8169_open(struct net_device *dev);
429static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
430static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
431 struct pt_regs *regs);
432static int rtl8169_init_ring(struct net_device *dev);
433static void rtl8169_hw_start(struct net_device *dev);
434static int rtl8169_close(struct net_device *dev);
435static void rtl8169_set_rx_mode(struct net_device *dev);
436static void rtl8169_tx_timeout(struct net_device *dev);
437static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
438static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
439 void __iomem *);
440static int rtl8169_change_mtu(struct net_device *netdev, int new_mtu);
441static void rtl8169_down(struct net_device *dev);
442
443#ifdef CONFIG_R8169_NAPI
444static int rtl8169_poll(struct net_device *dev, int *budget);
445#endif
446
447static const u16 rtl8169_intr_mask =
448 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
449static const u16 rtl8169_napi_event =
450 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
451static const unsigned int rtl8169_rx_config =
452 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
453
454#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
455#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
456#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
457#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
458
459static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
460{
461 int i;
462
463 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
464 udelay(1000);
465
466 for (i = 2000; i > 0; i--) {
467 /* Check if the RTL8169 has completed writing to the specified MII register */
468 if (!(RTL_R32(PHYAR) & 0x80000000))
469 break;
470 udelay(100);
471 }
472}
473
474static int mdio_read(void __iomem *ioaddr, int RegAddr)
475{
476 int i, value = -1;
477
478 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
479 udelay(1000);
480
481 for (i = 2000; i > 0; i--) {
482 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
483 if (RTL_R32(PHYAR) & 0x80000000) {
484 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
485 break;
486 }
487 udelay(100);
488 }
489 return value;
490}
491
492static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
493{
494 RTL_W16(IntrMask, 0x0000);
495
496 RTL_W16(IntrStatus, 0xffff);
497}
498
499static void rtl8169_asic_down(void __iomem *ioaddr)
500{
501 RTL_W8(ChipCmd, 0x00);
502 rtl8169_irq_mask_and_ack(ioaddr);
503 RTL_R16(CPlusCmd);
504}
505
506static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
507{
508 return RTL_R32(TBICSR) & TBIReset;
509}
510
511static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
512{
513 return mdio_read(ioaddr, 0) & 0x8000;
514}
515
516static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
517{
518 return RTL_R32(TBICSR) & TBILinkOk;
519}
520
521static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
522{
523 return RTL_R8(PHYstatus) & LinkStatus;
524}
525
526static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
527{
528 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
529}
530
531static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
532{
533 unsigned int val;
534
535 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
536 mdio_write(ioaddr, PHY_CTRL_REG, val);
537}
538
539static void rtl8169_check_link_status(struct net_device *dev,
540 struct rtl8169_private *tp, void __iomem *ioaddr)
541{
542 unsigned long flags;
543
544 spin_lock_irqsave(&tp->lock, flags);
545 if (tp->link_ok(ioaddr)) {
546 netif_carrier_on(dev);
547 printk(KERN_INFO PFX "%s: link up\n", dev->name);
548 } else
549 netif_carrier_off(dev);
550 spin_unlock_irqrestore(&tp->lock, flags);
551}
552
553static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
554{
555 struct {
556 u16 speed;
557 u8 duplex;
558 u8 autoneg;
559 u8 media;
560 } link_settings[] = {
561 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
562 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
563 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
564 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
565 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
566 /* Make TBI happy */
567 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
568 }, *p;
569 unsigned char option;
570
571 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
572
573 if ((option != 0xff) && !idx)
574 printk(KERN_WARNING PFX "media option is deprecated.\n");
575
576 for (p = link_settings; p->media != 0xff; p++) {
577 if (p->media == option)
578 break;
579 }
580 *autoneg = p->autoneg;
581 *speed = p->speed;
582 *duplex = p->duplex;
583}
584
585static void rtl8169_get_drvinfo(struct net_device *dev,
586 struct ethtool_drvinfo *info)
587{
588 struct rtl8169_private *tp = netdev_priv(dev);
589
590 strcpy(info->driver, MODULENAME);
591 strcpy(info->version, RTL8169_VERSION);
592 strcpy(info->bus_info, pci_name(tp->pci_dev));
593}
594
595static int rtl8169_get_regs_len(struct net_device *dev)
596{
597 return R8169_REGS_SIZE;
598}
599
600static int rtl8169_set_speed_tbi(struct net_device *dev,
601 u8 autoneg, u16 speed, u8 duplex)
602{
603 struct rtl8169_private *tp = netdev_priv(dev);
604 void __iomem *ioaddr = tp->mmio_addr;
605 int ret = 0;
606 u32 reg;
607
608 reg = RTL_R32(TBICSR);
609 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
610 (duplex == DUPLEX_FULL)) {
611 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
612 } else if (autoneg == AUTONEG_ENABLE)
613 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
614 else {
615 printk(KERN_WARNING PFX
616 "%s: incorrect speed setting refused in TBI mode\n",
617 dev->name);
618 ret = -EOPNOTSUPP;
619 }
620
621 return ret;
622}
623
624static int rtl8169_set_speed_xmii(struct net_device *dev,
625 u8 autoneg, u16 speed, u8 duplex)
626{
627 struct rtl8169_private *tp = netdev_priv(dev);
628 void __iomem *ioaddr = tp->mmio_addr;
629 int auto_nego, giga_ctrl;
630
631 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
632 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
633 PHY_Cap_100_Half | PHY_Cap_100_Full);
634 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
635 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
636
637 if (autoneg == AUTONEG_ENABLE) {
638 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
639 PHY_Cap_100_Half | PHY_Cap_100_Full);
640 giga_ctrl |= PHY_Cap_1000_Full;
641 } else {
642 if (speed == SPEED_10)
643 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
644 else if (speed == SPEED_100)
645 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
646 else if (speed == SPEED_1000)
647 giga_ctrl |= PHY_Cap_1000_Full;
648
649 if (duplex == DUPLEX_HALF)
650 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
651 }
652
653 tp->phy_auto_nego_reg = auto_nego;
654 tp->phy_1000_ctrl_reg = giga_ctrl;
655
656 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
657 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
658 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
659 PHY_Restart_Auto_Nego);
660 return 0;
661}
662
663static int rtl8169_set_speed(struct net_device *dev,
664 u8 autoneg, u16 speed, u8 duplex)
665{
666 struct rtl8169_private *tp = netdev_priv(dev);
667 int ret;
668
669 ret = tp->set_speed(dev, autoneg, speed, duplex);
670
671 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
672 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
673
674 return ret;
675}
676
677static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
678{
679 struct rtl8169_private *tp = netdev_priv(dev);
680 unsigned long flags;
681 int ret;
682
683 spin_lock_irqsave(&tp->lock, flags);
684 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
685 spin_unlock_irqrestore(&tp->lock, flags);
686
687 return ret;
688}
689
690static u32 rtl8169_get_rx_csum(struct net_device *dev)
691{
692 struct rtl8169_private *tp = netdev_priv(dev);
693
694 return tp->cp_cmd & RxChkSum;
695}
696
697static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
698{
699 struct rtl8169_private *tp = netdev_priv(dev);
700 void __iomem *ioaddr = tp->mmio_addr;
701 unsigned long flags;
702
703 spin_lock_irqsave(&tp->lock, flags);
704
705 if (data)
706 tp->cp_cmd |= RxChkSum;
707 else
708 tp->cp_cmd &= ~RxChkSum;
709
710 RTL_W16(CPlusCmd, tp->cp_cmd);
711 RTL_R16(CPlusCmd);
712
713 spin_unlock_irqrestore(&tp->lock, flags);
714
715 return 0;
716}
717
718#ifdef CONFIG_R8169_VLAN
719
720static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
721 struct sk_buff *skb)
722{
723 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
724 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
725}
726
727static void rtl8169_vlan_rx_register(struct net_device *dev,
728 struct vlan_group *grp)
729{
730 struct rtl8169_private *tp = netdev_priv(dev);
731 void __iomem *ioaddr = tp->mmio_addr;
732 unsigned long flags;
733
734 spin_lock_irqsave(&tp->lock, flags);
735 tp->vlgrp = grp;
736 if (tp->vlgrp)
737 tp->cp_cmd |= RxVlan;
738 else
739 tp->cp_cmd &= ~RxVlan;
740 RTL_W16(CPlusCmd, tp->cp_cmd);
741 RTL_R16(CPlusCmd);
742 spin_unlock_irqrestore(&tp->lock, flags);
743}
744
745static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
746{
747 struct rtl8169_private *tp = netdev_priv(dev);
748 unsigned long flags;
749
750 spin_lock_irqsave(&tp->lock, flags);
751 if (tp->vlgrp)
752 tp->vlgrp->vlan_devices[vid] = NULL;
753 spin_unlock_irqrestore(&tp->lock, flags);
754}
755
756static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
757 struct sk_buff *skb)
758{
759 u32 opts2 = le32_to_cpu(desc->opts2);
760 int ret;
761
762 if (tp->vlgrp && (opts2 & RxVlanTag)) {
763 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
764 swab16(opts2 & 0xffff));
765 ret = 0;
766 } else
767 ret = -1;
768 desc->opts2 = 0;
769 return ret;
770}
771
772#else /* !CONFIG_R8169_VLAN */
773
774static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
775 struct sk_buff *skb)
776{
777 return 0;
778}
779
780static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
781 struct sk_buff *skb)
782{
783 return -1;
784}
785
786#endif
787
788static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
789{
790 struct rtl8169_private *tp = netdev_priv(dev);
791 void __iomem *ioaddr = tp->mmio_addr;
792 u32 status;
793
794 cmd->supported =
795 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
796 cmd->port = PORT_FIBRE;
797 cmd->transceiver = XCVR_INTERNAL;
798
799 status = RTL_R32(TBICSR);
800 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
801 cmd->autoneg = !!(status & TBINwEnable);
802
803 cmd->speed = SPEED_1000;
804 cmd->duplex = DUPLEX_FULL; /* Always set */
805}
806
807static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
808{
809 struct rtl8169_private *tp = netdev_priv(dev);
810 void __iomem *ioaddr = tp->mmio_addr;
811 u8 status;
812
813 cmd->supported = SUPPORTED_10baseT_Half |
814 SUPPORTED_10baseT_Full |
815 SUPPORTED_100baseT_Half |
816 SUPPORTED_100baseT_Full |
817 SUPPORTED_1000baseT_Full |
818 SUPPORTED_Autoneg |
819 SUPPORTED_TP;
820
821 cmd->autoneg = 1;
822 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
823
824 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
825 cmd->advertising |= ADVERTISED_10baseT_Half;
826 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
827 cmd->advertising |= ADVERTISED_10baseT_Full;
828 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
829 cmd->advertising |= ADVERTISED_100baseT_Half;
830 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
831 cmd->advertising |= ADVERTISED_100baseT_Full;
832 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
833 cmd->advertising |= ADVERTISED_1000baseT_Full;
834
835 status = RTL_R8(PHYstatus);
836
837 if (status & _1000bpsF)
838 cmd->speed = SPEED_1000;
839 else if (status & _100bps)
840 cmd->speed = SPEED_100;
841 else if (status & _10bps)
842 cmd->speed = SPEED_10;
843
844 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
845 DUPLEX_FULL : DUPLEX_HALF;
846}
847
848static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
849{
850 struct rtl8169_private *tp = netdev_priv(dev);
851 unsigned long flags;
852
853 spin_lock_irqsave(&tp->lock, flags);
854
855 tp->get_settings(dev, cmd);
856
857 spin_unlock_irqrestore(&tp->lock, flags);
858 return 0;
859}
860
861static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
862 void *p)
863{
864 struct rtl8169_private *tp = netdev_priv(dev);
865 unsigned long flags;
866
867 if (regs->len > R8169_REGS_SIZE)
868 regs->len = R8169_REGS_SIZE;
869
870 spin_lock_irqsave(&tp->lock, flags);
871 memcpy_fromio(p, tp->mmio_addr, regs->len);
872 spin_unlock_irqrestore(&tp->lock, flags);
873}
874
875static struct ethtool_ops rtl8169_ethtool_ops = {
876 .get_drvinfo = rtl8169_get_drvinfo,
877 .get_regs_len = rtl8169_get_regs_len,
878 .get_link = ethtool_op_get_link,
879 .get_settings = rtl8169_get_settings,
880 .set_settings = rtl8169_set_settings,
881 .get_rx_csum = rtl8169_get_rx_csum,
882 .set_rx_csum = rtl8169_set_rx_csum,
883 .get_tx_csum = ethtool_op_get_tx_csum,
884 .set_tx_csum = ethtool_op_set_tx_csum,
885 .get_sg = ethtool_op_get_sg,
886 .set_sg = ethtool_op_set_sg,
887 .get_tso = ethtool_op_get_tso,
888 .set_tso = ethtool_op_set_tso,
889 .get_regs = rtl8169_get_regs,
890};
891
892static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
893 int bitval)
894{
895 int val;
896
897 val = mdio_read(ioaddr, reg);
898 val = (bitval == 1) ?
899 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
900 mdio_write(ioaddr, reg, val & 0xffff);
901}
902
903static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
904{
905 const struct {
906 u32 mask;
907 int mac_version;
908 } mac_info[] = {
909 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
910 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
911 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
912 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
913 }, *p = mac_info;
914 u32 reg;
915
916 reg = RTL_R32(TxConfig) & 0x7c800000;
917 while ((reg & p->mask) != p->mask)
918 p++;
919 tp->mac_version = p->mac_version;
920}
921
922static void rtl8169_print_mac_version(struct rtl8169_private *tp)
923{
924 struct {
925 int version;
926 char *msg;
927 } mac_print[] = {
928 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
929 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
930 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
931 { 0, NULL }
932 }, *p;
933
934 for (p = mac_print; p->msg; p++) {
935 if (tp->mac_version == p->version) {
936 dprintk("mac_version == %s (%04d)\n", p->msg,
937 p->version);
938 return;
939 }
940 }
941 dprintk("mac_version == Unknown\n");
942}
943
944static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
945{
946 const struct {
947 u16 mask;
948 u16 set;
949 int phy_version;
950 } phy_info[] = {
951 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
952 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
953 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
954 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
955 }, *p = phy_info;
956 u16 reg;
957
958 reg = mdio_read(ioaddr, 3) & 0xffff;
959 while ((reg & p->mask) != p->set)
960 p++;
961 tp->phy_version = p->phy_version;
962}
963
964static void rtl8169_print_phy_version(struct rtl8169_private *tp)
965{
966 struct {
967 int version;
968 char *msg;
969 u32 reg;
970 } phy_print[] = {
971 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
972 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
973 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
974 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
975 { 0, NULL, 0x0000 }
976 }, *p;
977
978 for (p = phy_print; p->msg; p++) {
979 if (tp->phy_version == p->version) {
980 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
981 return;
982 }
983 }
984 dprintk("phy_version == Unknown\n");
985}
986
987static void rtl8169_hw_phy_config(struct net_device *dev)
988{
989 struct rtl8169_private *tp = netdev_priv(dev);
990 void __iomem *ioaddr = tp->mmio_addr;
991 struct {
992 u16 regs[5]; /* Beware of bit-sign propagation */
993 } phy_magic[5] = { {
994 { 0x0000, //w 4 15 12 0
995 0x00a1, //w 3 15 0 00a1
996 0x0008, //w 2 15 0 0008
997 0x1020, //w 1 15 0 1020
998 0x1000 } },{ //w 0 15 0 1000
999 { 0x7000, //w 4 15 12 7
1000 0xff41, //w 3 15 0 ff41
1001 0xde60, //w 2 15 0 de60
1002 0x0140, //w 1 15 0 0140
1003 0x0077 } },{ //w 0 15 0 0077
1004 { 0xa000, //w 4 15 12 a
1005 0xdf01, //w 3 15 0 df01
1006 0xdf20, //w 2 15 0 df20
1007 0xff95, //w 1 15 0 ff95
1008 0xfa00 } },{ //w 0 15 0 fa00
1009 { 0xb000, //w 4 15 12 b
1010 0xff41, //w 3 15 0 ff41
1011 0xde20, //w 2 15 0 de20
1012 0x0140, //w 1 15 0 0140
1013 0x00bb } },{ //w 0 15 0 00bb
1014 { 0xf000, //w 4 15 12 f
1015 0xdf01, //w 3 15 0 df01
1016 0xdf20, //w 2 15 0 df20
1017 0xff95, //w 1 15 0 ff95
1018 0xbf00 } //w 0 15 0 bf00
1019 }
1020 }, *p = phy_magic;
1021 int i;
1022
1023 rtl8169_print_mac_version(tp);
1024 rtl8169_print_phy_version(tp);
1025
1026 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1027 return;
1028 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1029 return;
1030
1031 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1032 dprintk("Do final_reg2.cfg\n");
1033
1034 /* Shazam ! */
1035
1036 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1037 mdio_write(ioaddr, 31, 0x0001);
1038 mdio_write(ioaddr, 9, 0x273a);
1039 mdio_write(ioaddr, 14, 0x7bfb);
1040 mdio_write(ioaddr, 27, 0x841e);
1041
1042 mdio_write(ioaddr, 31, 0x0002);
1043 mdio_write(ioaddr, 1, 0x90d0);
1044 mdio_write(ioaddr, 31, 0x0000);
1045 return;
1046 }
1047
1048 /* phy config for RTL8169s mac_version C chip */
1049 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1050 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1051 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1052 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1053
1054 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1055 int val, pos = 4;
1056
1057 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1058 mdio_write(ioaddr, pos, val);
1059 while (--pos >= 0)
1060 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1061 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1062 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1063 }
1064 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1065}
1066
1067static void rtl8169_phy_timer(unsigned long __opaque)
1068{
1069 struct net_device *dev = (struct net_device *)__opaque;
1070 struct rtl8169_private *tp = netdev_priv(dev);
1071 struct timer_list *timer = &tp->timer;
1072 void __iomem *ioaddr = tp->mmio_addr;
1073 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1074
1075 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1076 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1077
1078 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1079 return;
1080
1081 spin_lock_irq(&tp->lock);
1082
1083 if (tp->phy_reset_pending(ioaddr)) {
1084 /*
1085 * A busy loop could burn quite a few cycles on nowadays CPU.
1086 * Let's delay the execution of the timer for a few ticks.
1087 */
1088 timeout = HZ/10;
1089 goto out_mod_timer;
1090 }
1091
1092 if (tp->link_ok(ioaddr))
1093 goto out_unlock;
1094
1095 printk(KERN_WARNING PFX "%s: PHY reset until link up\n", dev->name);
1096
1097 tp->phy_reset_enable(ioaddr);
1098
1099out_mod_timer:
1100 mod_timer(timer, jiffies + timeout);
1101out_unlock:
1102 spin_unlock_irq(&tp->lock);
1103}
1104
1105static inline void rtl8169_delete_timer(struct net_device *dev)
1106{
1107 struct rtl8169_private *tp = netdev_priv(dev);
1108 struct timer_list *timer = &tp->timer;
1109
1110 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1111 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1112 return;
1113
1114 del_timer_sync(timer);
1115}
1116
1117static inline void rtl8169_request_timer(struct net_device *dev)
1118{
1119 struct rtl8169_private *tp = netdev_priv(dev);
1120 struct timer_list *timer = &tp->timer;
1121
1122 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1123 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1124 return;
1125
1126 init_timer(timer);
1127 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1128 timer->data = (unsigned long)(dev);
1129 timer->function = rtl8169_phy_timer;
1130 add_timer(timer);
1131}
1132
1133#ifdef CONFIG_NET_POLL_CONTROLLER
1134/*
1135 * Polling 'interrupt' - used by things like netconsole to send skbs
1136 * without having to re-enable interrupts. It's not called while
1137 * the interrupt routine is executing.
1138 */
1139static void rtl8169_netpoll(struct net_device *dev)
1140{
1141 struct rtl8169_private *tp = netdev_priv(dev);
1142 struct pci_dev *pdev = tp->pci_dev;
1143
1144 disable_irq(pdev->irq);
1145 rtl8169_interrupt(pdev->irq, dev, NULL);
1146 enable_irq(pdev->irq);
1147}
1148#endif
1149
1150static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1151 void __iomem *ioaddr)
1152{
1153 iounmap(ioaddr);
1154 pci_release_regions(pdev);
1155 pci_disable_device(pdev);
1156 free_netdev(dev);
1157}
1158
1159static int __devinit
1160rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1161 void __iomem **ioaddr_out)
1162{
1163 void __iomem *ioaddr;
1164 struct net_device *dev;
1165 struct rtl8169_private *tp;
1166 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1167
1168 assert(ioaddr_out != NULL);
1169
1170 /* dev zeroed in alloc_etherdev */
1171 dev = alloc_etherdev(sizeof (*tp));
1172 if (dev == NULL) {
1173 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1174 goto err_out;
1175 }
1176
1177 SET_MODULE_OWNER(dev);
1178 SET_NETDEV_DEV(dev, &pdev->dev);
1179 tp = netdev_priv(dev);
1180
1181 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1182 rc = pci_enable_device(pdev);
1183 if (rc) {
1184 printk(KERN_ERR PFX "%s: enable failure\n", pci_name(pdev));
1185 goto err_out_free_dev;
1186 }
1187
1188 rc = pci_set_mwi(pdev);
1189 if (rc < 0)
1190 goto err_out_disable;
1191
1192 /* save power state before pci_enable_device overwrites it */
1193 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1194 if (pm_cap) {
1195 u16 pwr_command;
1196
1197 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1198 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1199 } else {
1200 printk(KERN_ERR PFX
1201 "Cannot find PowerManagement capability, aborting.\n");
1202 goto err_out_mwi;
1203 }
1204
1205 /* make sure PCI base addr 1 is MMIO */
1206 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1207 printk(KERN_ERR PFX
1208 "region #1 not an MMIO resource, aborting\n");
1209 rc = -ENODEV;
1210 goto err_out_mwi;
1211 }
1212 /* check for weird/broken PCI region reporting */
1213 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1214 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
1215 rc = -ENODEV;
1216 goto err_out_mwi;
1217 }
1218
1219 rc = pci_request_regions(pdev, MODULENAME);
1220 if (rc) {
1221 printk(KERN_ERR PFX "%s: could not request regions.\n",
1222 pci_name(pdev));
1223 goto err_out_mwi;
1224 }
1225
1226 tp->cp_cmd = PCIMulRW | RxChkSum;
1227
1228 if ((sizeof(dma_addr_t) > 4) &&
1229 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1230 tp->cp_cmd |= PCIDAC;
1231 dev->features |= NETIF_F_HIGHDMA;
1232 } else {
1233 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1234 if (rc < 0) {
1235 printk(KERN_ERR PFX "DMA configuration failed.\n");
1236 goto err_out_free_res;
1237 }
1238 }
1239
1240 pci_set_master(pdev);
1241
1242 /* ioremap MMIO region */
1243 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1244 if (ioaddr == NULL) {
1245 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1246 rc = -EIO;
1247 goto err_out_free_res;
1248 }
1249
1250 /* Unneeded ? Don't mess with Mrs. Murphy. */
1251 rtl8169_irq_mask_and_ack(ioaddr);
1252
1253 /* Soft reset the chip. */
1254 RTL_W8(ChipCmd, CmdReset);
1255
1256 /* Check that the chip has finished the reset. */
1257 for (i = 1000; i > 0; i--) {
1258 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1259 break;
1260 udelay(10);
1261 }
1262
1263 /* Identify chip attached to board */
1264 rtl8169_get_mac_version(tp, ioaddr);
1265 rtl8169_get_phy_version(tp, ioaddr);
1266
1267 rtl8169_print_mac_version(tp);
1268 rtl8169_print_phy_version(tp);
1269
1270 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1271 if (tp->mac_version == rtl_chip_info[i].mac_version)
1272 break;
1273 }
1274 if (i < 0) {
1275 /* Unknown chip: assume array element #0, original RTL-8169 */
1276 printk(KERN_DEBUG PFX
1277 "PCI device %s: unknown chip version, assuming %s\n",
1278 pci_name(pdev), rtl_chip_info[0].name);
1279 i++;
1280 }
1281 tp->chipset = i;
1282
1283 *ioaddr_out = ioaddr;
1284 *dev_out = dev;
1285out:
1286 return rc;
1287
1288err_out_free_res:
1289 pci_release_regions(pdev);
1290
1291err_out_mwi:
1292 pci_clear_mwi(pdev);
1293
1294err_out_disable:
1295 pci_disable_device(pdev);
1296
1297err_out_free_dev:
1298 free_netdev(dev);
1299err_out:
1300 *ioaddr_out = NULL;
1301 *dev_out = NULL;
1302 goto out;
1303}
1304
1305static int __devinit
1306rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1307{
1308 struct net_device *dev = NULL;
1309 struct rtl8169_private *tp;
1310 void __iomem *ioaddr = NULL;
1311 static int board_idx = -1;
1312 static int printed_version = 0;
1313 u8 autoneg, duplex;
1314 u16 speed;
1315 int i, rc;
1316
1317 assert(pdev != NULL);
1318 assert(ent != NULL);
1319
1320 board_idx++;
1321
1322 if (!printed_version) {
1323 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1324 MODULENAME, RTL8169_VERSION);
1325 printed_version = 1;
1326 }
1327
1328 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1329 if (rc)
1330 return rc;
1331
1332 tp = netdev_priv(dev);
1333 assert(ioaddr != NULL);
1334
1335 if (RTL_R8(PHYstatus) & TBI_Enable) {
1336 tp->set_speed = rtl8169_set_speed_tbi;
1337 tp->get_settings = rtl8169_gset_tbi;
1338 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1339 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1340 tp->link_ok = rtl8169_tbi_link_ok;
1341
1342 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1343 } else {
1344 tp->set_speed = rtl8169_set_speed_xmii;
1345 tp->get_settings = rtl8169_gset_xmii;
1346 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1347 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1348 tp->link_ok = rtl8169_xmii_link_ok;
1349 }
1350
1351 /* Get MAC address. FIXME: read EEPROM */
1352 for (i = 0; i < MAC_ADDR_LEN; i++)
1353 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1354
1355 dev->open = rtl8169_open;
1356 dev->hard_start_xmit = rtl8169_start_xmit;
1357 dev->get_stats = rtl8169_get_stats;
1358 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1359 dev->stop = rtl8169_close;
1360 dev->tx_timeout = rtl8169_tx_timeout;
1361 dev->set_multicast_list = rtl8169_set_rx_mode;
1362 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1363 dev->irq = pdev->irq;
1364 dev->base_addr = (unsigned long) ioaddr;
1365 dev->change_mtu = rtl8169_change_mtu;
1366
1367#ifdef CONFIG_R8169_NAPI
1368 dev->poll = rtl8169_poll;
1369 dev->weight = R8169_NAPI_WEIGHT;
1370 printk(KERN_INFO PFX "NAPI enabled\n");
1371#endif
1372
1373#ifdef CONFIG_R8169_VLAN
1374 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1375 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1376 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1377#endif
1378
1379#ifdef CONFIG_NET_POLL_CONTROLLER
1380 dev->poll_controller = rtl8169_netpoll;
1381#endif
1382
1383 tp->intr_mask = 0xffff;
1384 tp->pci_dev = pdev;
1385 tp->mmio_addr = ioaddr;
1386
1387 spin_lock_init(&tp->lock);
1388
1389 rc = register_netdev(dev);
1390 if (rc) {
1391 rtl8169_release_board(pdev, dev, ioaddr);
1392 return rc;
1393 }
1394
1395 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
1396 rtl_chip_info[tp->chipset].name);
1397
1398 pci_set_drvdata(pdev, dev);
1399
1400 printk(KERN_INFO "%s: %s at 0x%lx, "
1401 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1402 "IRQ %d\n",
1403 dev->name,
1404 rtl_chip_info[ent->driver_data].name,
1405 dev->base_addr,
1406 dev->dev_addr[0], dev->dev_addr[1],
1407 dev->dev_addr[2], dev->dev_addr[3],
1408 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1409
1410 rtl8169_hw_phy_config(dev);
1411
1412 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1413 RTL_W8(0x82, 0x01);
1414
1415 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1416 dprintk("Set PCI Latency=0x40\n");
1417 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1418 }
1419
1420 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1421 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1422 RTL_W8(0x82, 0x01);
1423 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1424 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1425 }
1426
1427 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1428
1429 rtl8169_set_speed(dev, autoneg, speed, duplex);
1430
1431 if (RTL_R8(PHYstatus) & TBI_Enable)
1432 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1433
1434 return 0;
1435}
1436
1437static void __devexit
1438rtl8169_remove_one(struct pci_dev *pdev)
1439{
1440 struct net_device *dev = pci_get_drvdata(pdev);
1441 struct rtl8169_private *tp = netdev_priv(dev);
1442
1443 assert(dev != NULL);
1444 assert(tp != NULL);
1445
1446 unregister_netdev(dev);
1447 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1448 pci_set_drvdata(pdev, NULL);
1449}
1450
1451#ifdef CONFIG_PM
1452
05adc3b7 1453static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
1da177e4
LT		 1454{
1455 struct net_device *dev = pci_get_drvdata(pdev);
1456 struct rtl8169_private *tp = netdev_priv(dev);
1457 void __iomem *ioaddr = tp->mmio_addr;
1458 unsigned long flags;
1459
1460 if (!netif_running(dev))
1461 return 0;
1462
1463 netif_device_detach(dev);
1464 netif_stop_queue(dev);
1465 spin_lock_irqsave(&tp->lock, flags);
1466
1467 /* Disable interrupts, stop Rx and Tx */
1468 RTL_W16(IntrMask, 0);
1469 RTL_W8(ChipCmd, 0);
1470
1471 /* Update the error counts. */
1472 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1473 RTL_W32(RxMissed, 0);
1474 spin_unlock_irqrestore(&tp->lock, flags);
1475
1476 return 0;
1477}
1478
1479static int rtl8169_resume(struct pci_dev *pdev)
1480{
1481 struct net_device *dev = pci_get_drvdata(pdev);
1482
1483 if (!netif_running(dev))
1484 return 0;
1485
1486 netif_device_attach(dev);
1487 rtl8169_hw_start(dev);
1488
1489 return 0;
1490}
1491
1492#endif /* CONFIG_PM */
1493
1494static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1495 struct net_device *dev)
1496{
1497 unsigned int mtu = dev->mtu;
1498
1499 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1500}
1501
1502static int rtl8169_open(struct net_device *dev)
1503{
1504 struct rtl8169_private *tp = netdev_priv(dev);
1505 struct pci_dev *pdev = tp->pci_dev;
1506 int retval;
1507
1508 rtl8169_set_rxbufsize(tp, dev);
1509
1510 retval =
1511 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1512 if (retval < 0)
1513 goto out;
1514
1515 retval = -ENOMEM;
1516
1517 /*
1518 * Rx and Tx desscriptors needs 256 bytes alignment.
1519 * pci_alloc_consistent provides more.
1520 */
1521 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1522 &tp->TxPhyAddr);
1523 if (!tp->TxDescArray)
1524 goto err_free_irq;
1525
1526 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1527 &tp->RxPhyAddr);
1528 if (!tp->RxDescArray)
1529 goto err_free_tx;
1530
1531 retval = rtl8169_init_ring(dev);
1532 if (retval < 0)
1533 goto err_free_rx;
1534
1535 INIT_WORK(&tp->task, NULL, dev);
1536
1537 rtl8169_hw_start(dev);
1538
1539 rtl8169_request_timer(dev);
1540
1541 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1542out:
1543 return retval;
1544
1545err_free_rx:
1546 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1547 tp->RxPhyAddr);
1548err_free_tx:
1549 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1550 tp->TxPhyAddr);
1551err_free_irq:
1552 free_irq(dev->irq, dev);
1553 goto out;
1554}
1555
1556static void rtl8169_hw_reset(void __iomem *ioaddr)
1557{
1558 /* Disable interrupts */
1559 rtl8169_irq_mask_and_ack(ioaddr);
1560
1561 /* Reset the chipset */
1562 RTL_W8(ChipCmd, CmdReset);
1563
1564 /* PCI commit */
1565 RTL_R8(ChipCmd);
1566}
1567
1568static void
1569rtl8169_hw_start(struct net_device *dev)
1570{
1571 struct rtl8169_private *tp = netdev_priv(dev);
1572 void __iomem *ioaddr = tp->mmio_addr;
1573 u32 i;
1574
1575 /* Soft reset the chip. */
1576 RTL_W8(ChipCmd, CmdReset);
1577
1578 /* Check that the chip has finished the reset. */
1579 for (i = 1000; i > 0; i--) {
1580 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1581 break;
1582 udelay(10);
1583 }
1584
1585 RTL_W8(Cfg9346, Cfg9346_Unlock);
1586 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1587 RTL_W8(EarlyTxThres, EarlyTxThld);
1588
126fa4b9
FR		 1589 /* Low hurts. Let's disable the filtering. */
1590 RTL_W16(RxMaxSize, 16383);
1da177e4
LT		 1591
1592 /* Set Rx Config register */
1593 i = rtl8169_rx_config |
1594 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1595 RTL_W32(RxConfig, i);
1596
1597 /* Set DMA burst size and Interframe Gap Time */
1598 RTL_W32(TxConfig,
1599 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1600 TxInterFrameGapShift));
1601 tp->cp_cmd |= RTL_R16(CPlusCmd);
1602 RTL_W16(CPlusCmd, tp->cp_cmd);
1603
1604 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1605 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1606 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1607 "Bit-3 and bit-14 MUST be 1\n");
1608 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1609 RTL_W16(CPlusCmd, tp->cp_cmd);
1610 }
1611
1612 /*
1613 * Undocumented corner. Supposedly:
1614 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1615 */
1616 RTL_W16(IntrMitigate, 0x0000);
1617
1618 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1619 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1620 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1621 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1622 RTL_W8(Cfg9346, Cfg9346_Lock);
1623 udelay(10);
1624
1625 RTL_W32(RxMissed, 0);
1626
1627 rtl8169_set_rx_mode(dev);
1628
1629 /* no early-rx interrupts */
1630 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1631
1632 /* Enable all known interrupts by setting the interrupt mask. */
1633 RTL_W16(IntrMask, rtl8169_intr_mask);
1634
1635 netif_start_queue(dev);
1636}
1637
1638static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1639{
1640 struct rtl8169_private *tp = netdev_priv(dev);
1641 int ret = 0;
1642
1643 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1644 return -EINVAL;
1645
1646 dev->mtu = new_mtu;
1647
1648 if (!netif_running(dev))
1649 goto out;
1650
1651 rtl8169_down(dev);
1652
1653 rtl8169_set_rxbufsize(tp, dev);
1654
1655 ret = rtl8169_init_ring(dev);
1656 if (ret < 0)
1657 goto out;
1658
1659 netif_poll_enable(dev);
1660
1661 rtl8169_hw_start(dev);
1662
1663 rtl8169_request_timer(dev);
1664
1665out:
1666 return ret;
1667}
1668
1669static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1670{
1671 desc->addr = 0x0badbadbadbadbadull;
1672 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1673}
1674
1675static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1676 struct sk_buff **sk_buff, struct RxDesc *desc)
1677{
1678 struct pci_dev *pdev = tp->pci_dev;
1679
1680 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1681 PCI_DMA_FROMDEVICE);
1682 dev_kfree_skb(*sk_buff);
1683 *sk_buff = NULL;
1684 rtl8169_make_unusable_by_asic(desc);
1685}
1686
1687static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1688{
1689 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1690
1691 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1692}
1693
1694static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1695 u32 rx_buf_sz)
1696{
1697 desc->addr = cpu_to_le64(mapping);
1698 wmb();
1699 rtl8169_mark_to_asic(desc, rx_buf_sz);
1700}
1701
1702static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1703 struct RxDesc *desc, int rx_buf_sz)
1704{
1705 struct sk_buff *skb;
1706 dma_addr_t mapping;
1707 int ret = 0;
1708
1709 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1710 if (!skb)
1711 goto err_out;
1712
1713 skb_reserve(skb, NET_IP_ALIGN);
1714 *sk_buff = skb;
1715
1716 mapping = pci_map_single(pdev, skb->tail, rx_buf_sz,
1717 PCI_DMA_FROMDEVICE);
1718
1719 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1720
1721out:
1722 return ret;
1723
1724err_out:
1725 ret = -ENOMEM;
1726 rtl8169_make_unusable_by_asic(desc);
1727 goto out;
1728}
1729
1730static void rtl8169_rx_clear(struct rtl8169_private *tp)
1731{
1732 int i;
1733
1734 for (i = 0; i < NUM_RX_DESC; i++) {
1735 if (tp->Rx_skbuff[i]) {
1736 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1737 tp->RxDescArray + i);
1738 }
1739 }
1740}
1741
1742static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1743 u32 start, u32 end)
1744{
1745 u32 cur;
1746
1747 for (cur = start; end - cur > 0; cur++) {
1748 int ret, i = cur % NUM_RX_DESC;
1749
1750 if (tp->Rx_skbuff[i])
1751 continue;
1752
1753 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1754 tp->RxDescArray + i, tp->rx_buf_sz);
1755 if (ret < 0)
1756 break;
1757 }
1758 return cur - start;
1759}
1760
1761static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1762{
1763 desc->opts1 |= cpu_to_le32(RingEnd);
1764}
1765
1766static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1767{
1768 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1769}
1770
1771static int rtl8169_init_ring(struct net_device *dev)
1772{
1773 struct rtl8169_private *tp = netdev_priv(dev);
1774
1775 rtl8169_init_ring_indexes(tp);
1776
1777 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1778 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1779
1780 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1781 goto err_out;
1782
1783 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1784
1785 return 0;
1786
1787err_out:
1788 rtl8169_rx_clear(tp);
1789 return -ENOMEM;
1790}
1791
1792static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
1793 struct TxDesc *desc)
1794{
1795 unsigned int len = tx_skb->len;
1796
1797 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
1798 desc->opts1 = 0x00;
1799 desc->opts2 = 0x00;
1800 desc->addr = 0x00;
1801 tx_skb->len = 0;
1802}
1803
1804static void rtl8169_tx_clear(struct rtl8169_private *tp)
1805{
1806 unsigned int i;
1807
1808 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
1809 unsigned int entry = i % NUM_TX_DESC;
1810 struct ring_info *tx_skb = tp->tx_skb + entry;
1811 unsigned int len = tx_skb->len;
1812
1813 if (len) {
1814 struct sk_buff *skb = tx_skb->skb;
1815
1816 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
1817 tp->TxDescArray + entry);
1818 if (skb) {
1819 dev_kfree_skb(skb);
1820 tx_skb->skb = NULL;
1821 }
1822 tp->stats.tx_dropped++;
1823 }
1824 }
1825 tp->cur_tx = tp->dirty_tx = 0;
1826}
1827
1828static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
1829{
1830 struct rtl8169_private *tp = netdev_priv(dev);
1831
1832 PREPARE_WORK(&tp->task, task, dev);
1833 schedule_delayed_work(&tp->task, 4);
1834}
1835
1836static void rtl8169_wait_for_quiescence(struct net_device *dev)
1837{
1838 struct rtl8169_private *tp = netdev_priv(dev);
1839 void __iomem *ioaddr = tp->mmio_addr;
1840
1841 synchronize_irq(dev->irq);
1842
1843 /* Wait for any pending NAPI task to complete */
1844 netif_poll_disable(dev);
1845
1846 rtl8169_irq_mask_and_ack(ioaddr);
1847
1848 netif_poll_enable(dev);
1849}
1850
1851static void rtl8169_reinit_task(void *_data)
1852{
1853 struct net_device *dev = _data;
1854 int ret;
1855
1856 if (netif_running(dev)) {
1857 rtl8169_wait_for_quiescence(dev);
1858 rtl8169_close(dev);
1859 }
1860
1861 ret = rtl8169_open(dev);
1862 if (unlikely(ret < 0)) {
1863 if (net_ratelimit()) {
1864 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
1865 " Rescheduling.\n", dev->name, ret);
1866 }
1867 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1868 }
1869}
1870
1871static void rtl8169_reset_task(void *_data)
1872{
1873 struct net_device *dev = _data;
1874 struct rtl8169_private *tp = netdev_priv(dev);
1875
1876 if (!netif_running(dev))
1877 return;
1878
1879 rtl8169_wait_for_quiescence(dev);
1880
1881 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
1882 rtl8169_tx_clear(tp);
1883
1884 if (tp->dirty_rx == tp->cur_rx) {
1885 rtl8169_init_ring_indexes(tp);
1886 rtl8169_hw_start(dev);
1887 netif_wake_queue(dev);
1888 } else {
1889 if (net_ratelimit()) {
1890 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
1891 dev->name);
1892 }
1893 rtl8169_schedule_work(dev, rtl8169_reset_task);
1894 }
1895}
1896
1897static void rtl8169_tx_timeout(struct net_device *dev)
1898{
1899 struct rtl8169_private *tp = netdev_priv(dev);
1900
1901 rtl8169_hw_reset(tp->mmio_addr);
1902
1903 /* Let's wait a bit while any (async) irq lands on */
1904 rtl8169_schedule_work(dev, rtl8169_reset_task);
1905}
1906
1907static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
1908 u32 opts1)
1909{
1910 struct skb_shared_info *info = skb_shinfo(skb);
1911 unsigned int cur_frag, entry;
1912 struct TxDesc *txd;
1913
1914 entry = tp->cur_tx;
1915 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
1916 skb_frag_t *frag = info->frags + cur_frag;
1917 dma_addr_t mapping;
1918 u32 status, len;
1919 void *addr;
1920
1921 entry = (entry + 1) % NUM_TX_DESC;
1922
1923 txd = tp->TxDescArray + entry;
1924 len = frag->size;
1925 addr = ((void *) page_address(frag->page)) + frag->page_offset;
1926 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
1927
1928 /* anti gcc 2.95.3 bugware (sic) */
1929 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1930
1931 txd->opts1 = cpu_to_le32(status);
1932 txd->addr = cpu_to_le64(mapping);
1933
1934 tp->tx_skb[entry].len = len;
1935 }
1936
1937 if (cur_frag) {
1938 tp->tx_skb[entry].skb = skb;
1939 txd->opts1 |= cpu_to_le32(LastFrag);
1940 }
1941
1942 return cur_frag;
1943}
1944
1945static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
1946{
1947 if (dev->features & NETIF_F_TSO) {
1948 u32 mss = skb_shinfo(skb)->tso_size;
1949
1950 if (mss)
1951 return LargeSend | ((mss & MSSMask) << MSSShift);
1952 }
1953 if (skb->ip_summed == CHECKSUM_HW) {
1954 const struct iphdr *ip = skb->nh.iph;
1955
1956 if (ip->protocol == IPPROTO_TCP)
1957 return IPCS | TCPCS;
1958 else if (ip->protocol == IPPROTO_UDP)
1959 return IPCS | UDPCS;
1960 WARN_ON(1); /* we need a WARN() */
1961 }
1962 return 0;
1963}
1964
1965static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1966{
1967 struct rtl8169_private *tp = netdev_priv(dev);
1968 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
1969 struct TxDesc *txd = tp->TxDescArray + entry;
1970 void __iomem *ioaddr = tp->mmio_addr;
1971 dma_addr_t mapping;
1972 u32 status, len;
1973 u32 opts1;
1974 int ret = 0;
1975
1976 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
1977 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1978 dev->name);
1979 goto err_stop;
1980 }
1981
1982 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
1983 goto err_stop;
1984
1985 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
1986
1987 frags = rtl8169_xmit_frags(tp, skb, opts1);
1988 if (frags) {
1989 len = skb_headlen(skb);
1990 opts1 |= FirstFrag;
1991 } else {
1992 len = skb->len;
1993
1994 if (unlikely(len < ETH_ZLEN)) {
1995 skb = skb_padto(skb, ETH_ZLEN);
1996 if (!skb)
1997 goto err_update_stats;
1998 len = ETH_ZLEN;
1999 }
2000
2001 opts1 |= FirstFrag | LastFrag;
2002 tp->tx_skb[entry].skb = skb;
2003 }
2004
2005 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2006
2007 tp->tx_skb[entry].len = len;
2008 txd->addr = cpu_to_le64(mapping);
2009 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2010
2011 wmb();
2012
2013 /* anti gcc 2.95.3 bugware (sic) */
2014 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2015 txd->opts1 = cpu_to_le32(status);
2016
2017 dev->trans_start = jiffies;
2018
2019 tp->cur_tx += frags + 1;
2020
2021 smp_wmb();
2022
2023 RTL_W8(TxPoll, 0x40); /* set polling bit */
2024
2025 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2026 netif_stop_queue(dev);
2027 smp_rmb();
2028 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2029 netif_wake_queue(dev);
2030 }
2031
2032out:
2033 return ret;
2034
2035err_stop:
2036 netif_stop_queue(dev);
2037 ret = 1;
2038err_update_stats:
2039 tp->stats.tx_dropped++;
2040 goto out;
2041}
2042
2043static void rtl8169_pcierr_interrupt(struct net_device *dev)
2044{
2045 struct rtl8169_private *tp = netdev_priv(dev);
2046 struct pci_dev *pdev = tp->pci_dev;
2047 void __iomem *ioaddr = tp->mmio_addr;
2048 u16 pci_status, pci_cmd;
2049
2050 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2051 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2052
2053 printk(KERN_ERR PFX "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2054 dev->name, pci_cmd, pci_status);
2055
2056 /*
2057 * The recovery sequence below admits a very elaborated explanation:
2058 * - it seems to work;
2059 * - I did not see what else could be done.
2060 *
2061 * Feel free to adjust to your needs.
2062 */
2063 pci_write_config_word(pdev, PCI_COMMAND,
2064 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2065
2066 pci_write_config_word(pdev, PCI_STATUS,
2067 pci_status & (PCI_STATUS_DETECTED_PARITY |
2068 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2069 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2070
2071 /* The infamous DAC f*ckup only happens at boot time */
2072 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2073 printk(KERN_INFO PFX "%s: disabling PCI DAC.\n", dev->name);
2074 tp->cp_cmd &= ~PCIDAC;
2075 RTL_W16(CPlusCmd, tp->cp_cmd);
2076 dev->features &= ~NETIF_F_HIGHDMA;
2077 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2078 }
2079
2080 rtl8169_hw_reset(ioaddr);
2081}
2082
2083static void
2084rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2085 void __iomem *ioaddr)
2086{
2087 unsigned int dirty_tx, tx_left;
2088
2089 assert(dev != NULL);
2090 assert(tp != NULL);
2091 assert(ioaddr != NULL);
2092
2093 dirty_tx = tp->dirty_tx;
2094 smp_rmb();
2095 tx_left = tp->cur_tx - dirty_tx;
2096
2097 while (tx_left > 0) {
2098 unsigned int entry = dirty_tx % NUM_TX_DESC;
2099 struct ring_info *tx_skb = tp->tx_skb + entry;
2100 u32 len = tx_skb->len;
2101 u32 status;
2102
2103 rmb();
2104 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2105 if (status & DescOwn)
2106 break;
2107
2108 tp->stats.tx_bytes += len;
2109 tp->stats.tx_packets++;
2110
2111 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2112
2113 if (status & LastFrag) {
2114 dev_kfree_skb_irq(tx_skb->skb);
2115 tx_skb->skb = NULL;
2116 }
2117 dirty_tx++;
2118 tx_left--;
2119 }
2120
2121 if (tp->dirty_tx != dirty_tx) {
2122 tp->dirty_tx = dirty_tx;
2123 smp_wmb();
2124 if (netif_queue_stopped(dev) &&
2125 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2126 netif_wake_queue(dev);
2127 }
2128 }
2129}
2130
126fa4b9
FR		 2131static inline int rtl8169_fragmented_frame(u32 status)
2132{
2133 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2134}
2135
1da177e4
LT		 2136static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2137{
2138 u32 opts1 = le32_to_cpu(desc->opts1);
2139 u32 status = opts1 & RxProtoMask;
2140
2141 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2142 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2143 ((status == RxProtoIP) && !(opts1 & IPFail)))
2144 skb->ip_summed = CHECKSUM_UNNECESSARY;
2145 else
2146 skb->ip_summed = CHECKSUM_NONE;
2147}
2148
2149static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2150 struct RxDesc *desc, int rx_buf_sz)
2151{
2152 int ret = -1;
2153
2154 if (pkt_size < rx_copybreak) {
2155 struct sk_buff *skb;
2156
2157 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2158 if (skb) {
2159 skb_reserve(skb, NET_IP_ALIGN);
2160 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
2161 *sk_buff = skb;
2162 rtl8169_mark_to_asic(desc, rx_buf_sz);
2163 ret = 0;
2164 }
2165 }
2166 return ret;
2167}
2168
2169static int
2170rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2171 void __iomem *ioaddr)
2172{
2173 unsigned int cur_rx, rx_left;
2174 unsigned int delta, count;
2175
2176 assert(dev != NULL);
2177 assert(tp != NULL);
2178 assert(ioaddr != NULL);
2179
2180 cur_rx = tp->cur_rx;
2181 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2182 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2183
2184 while (rx_left > 0) {
2185 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2186 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2187 u32 status;
2188
2189 rmb();
126fa4b9 2190 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2191
2192 if (status & DescOwn)
2193 break;
2194 if (status & RxRES) {
126fa4b9
FR		 2195 printk(KERN_INFO "%s: Rx ERROR. status = %08x\n",
2196 dev->name, status);
1da177e4
LT		 2197 tp->stats.rx_errors++;
2198 if (status & (RxRWT | RxRUNT))
2199 tp->stats.rx_length_errors++;
2200 if (status & RxCRC)
2201 tp->stats.rx_crc_errors++;
126fa4b9 2202 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2203 } else {
1da177e4
LT		 2204 struct sk_buff *skb = tp->Rx_skbuff[entry];
2205 int pkt_size = (status & 0x00001FFF) - 4;
2206 void (*pci_action)(struct pci_dev *, dma_addr_t,
2207 size_t, int) = pci_dma_sync_single_for_device;
2208
126fa4b9
FR		 2209 /*
2210 * The driver does not support incoming fragmented
2211 * frames. They are seen as a symptom of over-mtu
2212 * sized frames.
2213 */
2214 if (unlikely(rtl8169_fragmented_frame(status))) {
2215 tp->stats.rx_dropped++;
2216 tp->stats.rx_length_errors++;
2217 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2218 goto move_on;
2219 }
2220
1da177e4
LT		 2221 rtl8169_rx_csum(skb, desc);
2222
2223 pci_dma_sync_single_for_cpu(tp->pci_dev,
2224 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2225 PCI_DMA_FROMDEVICE);
2226
2227 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2228 tp->rx_buf_sz)) {
2229 pci_action = pci_unmap_single;
2230 tp->Rx_skbuff[entry] = NULL;
2231 }
2232
2233 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2234 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2235
2236 skb->dev = dev;
2237 skb_put(skb, pkt_size);
2238 skb->protocol = eth_type_trans(skb, dev);
2239
2240 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2241 rtl8169_rx_skb(skb);
2242
2243 dev->last_rx = jiffies;
2244 tp->stats.rx_bytes += pkt_size;
2245 tp->stats.rx_packets++;
2246 }
126fa4b9 2247move_on:
1da177e4
LT		 2248 cur_rx++;
2249 rx_left--;
2250 }
2251
2252 count = cur_rx - tp->cur_rx;
2253 tp->cur_rx = cur_rx;
2254
2255 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2256 if (!delta && count)
2257 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2258 tp->dirty_rx += delta;
2259
2260 /*
2261 * FIXME: until there is periodic timer to try and refill the ring,
2262 * a temporary shortage may definitely kill the Rx process.
2263 * - disable the asic to try and avoid an overflow and kick it again
2264 * after refill ?
2265 * - how do others driver handle this condition (Uh oh...).
2266 */
2267 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
2268 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2269
2270 return count;
2271}
2272
2273/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2274static irqreturn_t
2275rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2276{
2277 struct net_device *dev = (struct net_device *) dev_instance;
2278 struct rtl8169_private *tp = netdev_priv(dev);
2279 int boguscnt = max_interrupt_work;
2280 void __iomem *ioaddr = tp->mmio_addr;
2281 int status;
2282 int handled = 0;
2283
2284 do {
2285 status = RTL_R16(IntrStatus);
2286
2287 /* hotplug/major error/no more work/shared irq */
2288 if ((status == 0xFFFF) || !status)
2289 break;
2290
2291 handled = 1;
2292
2293 if (unlikely(!netif_running(dev))) {
2294 rtl8169_asic_down(ioaddr);
2295 goto out;
2296 }
2297
2298 status &= tp->intr_mask;
2299 RTL_W16(IntrStatus,
2300 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2301
2302 if (!(status & rtl8169_intr_mask))
2303 break;
2304
2305 if (unlikely(status & SYSErr)) {
2306 rtl8169_pcierr_interrupt(dev);
2307 break;
2308 }
2309
2310 if (status & LinkChg)
2311 rtl8169_check_link_status(dev, tp, ioaddr);
2312
2313#ifdef CONFIG_R8169_NAPI
2314 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2315 tp->intr_mask = ~rtl8169_napi_event;
2316
2317 if (likely(netif_rx_schedule_prep(dev)))
2318 __netif_rx_schedule(dev);
2319 else {
2320 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2321 dev->name, status);
2322 }
2323 break;
2324#else
2325 /* Rx interrupt */
2326 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2327 rtl8169_rx_interrupt(dev, tp, ioaddr);
2328 }
2329 /* Tx interrupt */
2330 if (status & (TxOK | TxErr))
2331 rtl8169_tx_interrupt(dev, tp, ioaddr);
2332#endif
2333
2334 boguscnt--;
2335 } while (boguscnt > 0);
2336
2337 if (boguscnt <= 0) {
2338 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
2339 dev->name);
2340 /* Clear all interrupt sources. */
2341 RTL_W16(IntrStatus, 0xffff);
2342 }
2343out:
2344 return IRQ_RETVAL(handled);
2345}
2346
2347#ifdef CONFIG_R8169_NAPI
2348static int rtl8169_poll(struct net_device *dev, int *budget)
2349{
2350 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2351 struct rtl8169_private *tp = netdev_priv(dev);
2352 void __iomem *ioaddr = tp->mmio_addr;
2353
2354 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2355 rtl8169_tx_interrupt(dev, tp, ioaddr);
2356
2357 *budget -= work_done;
2358 dev->quota -= work_done;
2359
2360 if (work_done < work_to_do) {
2361 netif_rx_complete(dev);
2362 tp->intr_mask = 0xffff;
2363 /*
2364 * 20040426: the barrier is not strictly required but the
2365 * behavior of the irq handler could be less predictable
2366 * without it. Btw, the lack of flush for the posted pci
2367 * write is safe - FR
2368 */
2369 smp_wmb();
2370 RTL_W16(IntrMask, rtl8169_intr_mask);
2371 }
2372
2373 return (work_done >= work_to_do);
2374}
2375#endif
2376
2377static void rtl8169_down(struct net_device *dev)
2378{
2379 struct rtl8169_private *tp = netdev_priv(dev);
2380 void __iomem *ioaddr = tp->mmio_addr;
2381 unsigned int poll_locked = 0;
2382
2383 rtl8169_delete_timer(dev);
2384
2385 netif_stop_queue(dev);
2386
2387 flush_scheduled_work();
2388
2389core_down:
2390 spin_lock_irq(&tp->lock);
2391
2392 rtl8169_asic_down(ioaddr);
2393
2394 /* Update the error counts. */
2395 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2396 RTL_W32(RxMissed, 0);
2397
2398 spin_unlock_irq(&tp->lock);
2399
2400 synchronize_irq(dev->irq);
2401
2402 if (!poll_locked) {
2403 netif_poll_disable(dev);
2404 poll_locked++;
2405 }
2406
2407 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2408 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2409
2410 /*
2411 * And now for the 50k$ question: are IRQ disabled or not ?
2412 *
2413 * Two paths lead here:
2414 * 1) dev->close
2415 * -> netif_running() is available to sync the current code and the
2416 * IRQ handler. See rtl8169_interrupt for details.
2417 * 2) dev->change_mtu
2418 * -> rtl8169_poll can not be issued again and re-enable the
2419 * interruptions. Let's simply issue the IRQ down sequence again.
2420 */
2421 if (RTL_R16(IntrMask))
2422 goto core_down;
2423
2424 rtl8169_tx_clear(tp);
2425
2426 rtl8169_rx_clear(tp);
2427}
2428
2429static int rtl8169_close(struct net_device *dev)
2430{
2431 struct rtl8169_private *tp = netdev_priv(dev);
2432 struct pci_dev *pdev = tp->pci_dev;
2433
2434 rtl8169_down(dev);
2435
2436 free_irq(dev->irq, dev);
2437
2438 netif_poll_enable(dev);
2439
2440 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2441 tp->RxPhyAddr);
2442 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2443 tp->TxPhyAddr);
2444 tp->TxDescArray = NULL;
2445 tp->RxDescArray = NULL;
2446
2447 return 0;
2448}
2449
2450static void
2451rtl8169_set_rx_mode(struct net_device *dev)
2452{
2453 struct rtl8169_private *tp = netdev_priv(dev);
2454 void __iomem *ioaddr = tp->mmio_addr;
2455 unsigned long flags;
2456 u32 mc_filter[2]; /* Multicast hash filter */
2457 int i, rx_mode;
2458 u32 tmp = 0;
2459
2460 if (dev->flags & IFF_PROMISC) {
2461 /* Unconditionally log net taps. */
2462 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2463 dev->name);
2464 rx_mode =
2465 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2466 AcceptAllPhys;
2467 mc_filter[1] = mc_filter[0] = 0xffffffff;
2468 } else if ((dev->mc_count > multicast_filter_limit)
2469 || (dev->flags & IFF_ALLMULTI)) {
2470 /* Too many to filter perfectly -- accept all multicasts. */
2471 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2472 mc_filter[1] = mc_filter[0] = 0xffffffff;
2473 } else {
2474 struct dev_mc_list *mclist;
2475 rx_mode = AcceptBroadcast | AcceptMyPhys;
2476 mc_filter[1] = mc_filter[0] = 0;
2477 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2478 i++, mclist = mclist->next) {
2479 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2480 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2481 rx_mode |= AcceptMulticast;
2482 }
2483 }
2484
2485 spin_lock_irqsave(&tp->lock, flags);
2486
2487 tmp = rtl8169_rx_config | rx_mode |
2488 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2489
2490 RTL_W32(RxConfig, tmp);
2491 RTL_W32(MAR0 + 0, mc_filter[0]);
2492 RTL_W32(MAR0 + 4, mc_filter[1]);
2493
2494 spin_unlock_irqrestore(&tp->lock, flags);
2495}
2496
2497/**
2498 * rtl8169_get_stats - Get rtl8169 read/write statistics
2499 * @dev: The Ethernet Device to get statistics for
2500 *
2501 * Get TX/RX statistics for rtl8169
2502 */
2503static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2504{
2505 struct rtl8169_private *tp = netdev_priv(dev);
2506 void __iomem *ioaddr = tp->mmio_addr;
2507 unsigned long flags;
2508
2509 if (netif_running(dev)) {
2510 spin_lock_irqsave(&tp->lock, flags);
2511 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2512 RTL_W32(RxMissed, 0);
2513 spin_unlock_irqrestore(&tp->lock, flags);
2514 }
2515
2516 return &tp->stats;
2517}
2518
2519static struct pci_driver rtl8169_pci_driver = {
2520 .name = MODULENAME,
2521 .id_table = rtl8169_pci_tbl,
2522 .probe = rtl8169_init_one,
2523 .remove = __devexit_p(rtl8169_remove_one),
2524#ifdef CONFIG_PM
2525 .suspend = rtl8169_suspend,
2526 .resume = rtl8169_resume,
2527#endif
2528};
2529
2530static int __init
2531rtl8169_init_module(void)
2532{
2533 return pci_module_init(&rtl8169_pci_driver);
2534}
2535
2536static void __exit
2537rtl8169_cleanup_module(void)
2538{
2539 pci_unregister_driver(&rtl8169_pci_driver);
2540}
2541
2542module_init(rtl8169_init_module);
2543module_exit(rtl8169_cleanup_module);
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