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[net-next-2.6.git] / drivers / net / r8169.c
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1da177e4
LT		 1/*
2=========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10=========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23=========================================================================
24VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/pci.h>
56#include <linux/netdevice.h>
57#include <linux/etherdevice.h>
58#include <linux/delay.h>
59#include <linux/ethtool.h>
60#include <linux/mii.h>
61#include <linux/if_vlan.h>
62#include <linux/crc32.h>
63#include <linux/in.h>
64#include <linux/ip.h>
65#include <linux/tcp.h>
66#include <linux/init.h>
67#include <linux/dma-mapping.h>
68
69#include <asm/io.h>
70#include <asm/irq.h>
71
72#define RTL8169_VERSION "2.2LK"
73#define MODULENAME "r8169"
74#define PFX MODULENAME ": "
75
76#ifdef RTL8169_DEBUG
77#define assert(expr) \
78 if(!(expr)) { \
79 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
80 #expr,__FILE__,__FUNCTION__,__LINE__); \
81 }
82#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
83#else
84#define assert(expr) do {} while (0)
85#define dprintk(fmt, args...) do {} while (0)
86#endif /* RTL8169_DEBUG */
87
88#define TX_BUFFS_AVAIL(tp) \
89 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
90
91#ifdef CONFIG_R8169_NAPI
92#define rtl8169_rx_skb netif_receive_skb
93#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
94#define rtl8169_rx_quota(count, quota) min(count, quota)
95#else
96#define rtl8169_rx_skb netif_rx
97#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
98#define rtl8169_rx_quota(count, quota) count
99#endif
100
101/* media options */
102#define MAX_UNITS 8
103static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
104static int num_media = 0;
105
106/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
107static int max_interrupt_work = 20;
108
109/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
110 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
111static int multicast_filter_limit = 32;
112
113/* MAC address length */
114#define MAC_ADDR_LEN 6
115
116#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
117#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
118#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
119#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
120#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
121#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
122#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
123
124#define R8169_REGS_SIZE 256
125#define R8169_NAPI_WEIGHT 64
126#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
127#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
128#define RX_BUF_SIZE 1536 /* Rx Buffer size */
129#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
130#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
131
132#define RTL8169_TX_TIMEOUT (6*HZ)
133#define RTL8169_PHY_TIMEOUT (10*HZ)
134
135/* write/read MMIO register */
136#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
137#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
138#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
139#define RTL_R8(reg) readb (ioaddr + (reg))
140#define RTL_R16(reg) readw (ioaddr + (reg))
141#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
142
143enum mac_version {
144 RTL_GIGA_MAC_VER_B = 0x00,
145 /* RTL_GIGA_MAC_VER_C = 0x03, */
146 RTL_GIGA_MAC_VER_D = 0x01,
147 RTL_GIGA_MAC_VER_E = 0x02,
148 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
149};
150
151enum phy_version {
152 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
153 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
154 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
155 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
156 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
157 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
158};
159
160
161#define _R(NAME,MAC,MASK) \
162 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
163
164const static struct {
165 const char *name;
166 u8 mac_version;
167 u32 RxConfigMask; /* Clears the bits supported by this chip */
168} rtl_chip_info[] = {
169 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
170 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
171 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
172 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
173};
174#undef _R
175
176static struct pci_device_id rtl8169_pci_tbl[] = {
177 {0x10ec, 0x8169, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {0x1186, 0x4300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {0,},
180};
181
182MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
183
184static int rx_copybreak = 200;
185static int use_dac;
186
187enum RTL8169_registers {
188 MAC0 = 0, /* Ethernet hardware address. */
189 MAR0 = 8, /* Multicast filter. */
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
194 FLASH = 0x30,
195 ERSR = 0x36,
196 ChipCmd = 0x37,
197 TxPoll = 0x38,
198 IntrMask = 0x3C,
199 IntrStatus = 0x3E,
200 TxConfig = 0x40,
201 RxConfig = 0x44,
202 RxMissed = 0x4C,
203 Cfg9346 = 0x50,
204 Config0 = 0x51,
205 Config1 = 0x52,
206 Config2 = 0x53,
207 Config3 = 0x54,
208 Config4 = 0x55,
209 Config5 = 0x56,
210 MultiIntr = 0x5C,
211 PHYAR = 0x60,
212 TBICSR = 0x64,
213 TBI_ANAR = 0x68,
214 TBI_LPAR = 0x6A,
215 PHYstatus = 0x6C,
216 RxMaxSize = 0xDA,
217 CPlusCmd = 0xE0,
218 IntrMitigate = 0xE2,
219 RxDescAddrLow = 0xE4,
220 RxDescAddrHigh = 0xE8,
221 EarlyTxThres = 0xEC,
222 FuncEvent = 0xF0,
223 FuncEventMask = 0xF4,
224 FuncPresetState = 0xF8,
225 FuncForceEvent = 0xFC,
226};
227
228enum RTL8169_register_content {
229 /* InterruptStatusBits */
230 SYSErr = 0x8000,
231 PCSTimeout = 0x4000,
232 SWInt = 0x0100,
233 TxDescUnavail = 0x80,
234 RxFIFOOver = 0x40,
235 LinkChg = 0x20,
236 RxOverflow = 0x10,
237 TxErr = 0x08,
238 TxOK = 0x04,
239 RxErr = 0x02,
240 RxOK = 0x01,
241
242 /* RxStatusDesc */
243 RxRES = 0x00200000,
244 RxCRC = 0x00080000,
245 RxRUNT = 0x00100000,
246 RxRWT = 0x00400000,
247
248 /* ChipCmdBits */
249 CmdReset = 0x10,
250 CmdRxEnb = 0x08,
251 CmdTxEnb = 0x04,
252 RxBufEmpty = 0x01,
253
254 /* Cfg9346Bits */
255 Cfg9346_Lock = 0x00,
256 Cfg9346_Unlock = 0xC0,
257
258 /* rx_mode_bits */
259 AcceptErr = 0x20,
260 AcceptRunt = 0x10,
261 AcceptBroadcast = 0x08,
262 AcceptMulticast = 0x04,
263 AcceptMyPhys = 0x02,
264 AcceptAllPhys = 0x01,
265
266 /* RxConfigBits */
267 RxCfgFIFOShift = 13,
268 RxCfgDMAShift = 8,
269
270 /* TxConfigBits */
271 TxInterFrameGapShift = 24,
272 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
273
274 /* TBICSR p.28 */
275 TBIReset = 0x80000000,
276 TBILoopback = 0x40000000,
277 TBINwEnable = 0x20000000,
278 TBINwRestart = 0x10000000,
279 TBILinkOk = 0x02000000,
280 TBINwComplete = 0x01000000,
281
282 /* CPlusCmd p.31 */
283 RxVlan = (1 << 6),
284 RxChkSum = (1 << 5),
285 PCIDAC = (1 << 4),
286 PCIMulRW = (1 << 3),
287
288 /* rtl8169_PHYstatus */
289 TBI_Enable = 0x80,
290 TxFlowCtrl = 0x40,
291 RxFlowCtrl = 0x20,
292 _1000bpsF = 0x10,
293 _100bps = 0x08,
294 _10bps = 0x04,
295 LinkStatus = 0x02,
296 FullDup = 0x01,
297
298 /* GIGABIT_PHY_registers */
299 PHY_CTRL_REG = 0,
300 PHY_STAT_REG = 1,
301 PHY_AUTO_NEGO_REG = 4,
302 PHY_1000_CTRL_REG = 9,
303
304 /* GIGABIT_PHY_REG_BIT */
305 PHY_Restart_Auto_Nego = 0x0200,
306 PHY_Enable_Auto_Nego = 0x1000,
307
308 /* PHY_STAT_REG = 1 */
309 PHY_Auto_Neco_Comp = 0x0020,
310
311 /* PHY_AUTO_NEGO_REG = 4 */
312 PHY_Cap_10_Half = 0x0020,
313 PHY_Cap_10_Full = 0x0040,
314 PHY_Cap_100_Half = 0x0080,
315 PHY_Cap_100_Full = 0x0100,
316
317 /* PHY_1000_CTRL_REG = 9 */
318 PHY_Cap_1000_Full = 0x0200,
319
320 PHY_Cap_Null = 0x0,
321
322 /* _MediaType */
323 _10_Half = 0x01,
324 _10_Full = 0x02,
325 _100_Half = 0x04,
326 _100_Full = 0x08,
327 _1000_Full = 0x10,
328
329 /* _TBICSRBit */
330 TBILinkOK = 0x02000000,
331};
332
333enum _DescStatusBit {
334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
338
339 /* Tx private */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
347
348 /* Rx private */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351
352#define RxProtoUDP (PID1)
353#define RxProtoTCP (PID0)
354#define RxProtoIP (PID1 | PID0)
355#define RxProtoMask RxProtoIP
356
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
361};
362
363#define RsvdMask 0x3fffc000
364
365struct TxDesc {
366 u32 opts1;
367 u32 opts2;
368 u64 addr;
369};
370
371struct RxDesc {
372 u32 opts1;
373 u32 opts2;
374 u64 addr;
375};
376
377struct ring_info {
378 struct sk_buff *skb;
379 u32 len;
380 u8 __pad[sizeof(void *) - sizeof(u32)];
381};
382
383struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
386 struct net_device_stats stats; /* statistics of net device */
387 spinlock_t lock; /* spin lock flag */
388 int chipset;
389 int mac_version;
390 int phy_version;
391 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
392 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
393 u32 dirty_rx;
394 u32 dirty_tx;
395 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
396 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
397 dma_addr_t TxPhyAddr;
398 dma_addr_t RxPhyAddr;
399 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
400 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
401 unsigned rx_buf_sz;
402 struct timer_list timer;
403 u16 cp_cmd;
404 u16 intr_mask;
405 int phy_auto_nego_reg;
406 int phy_1000_ctrl_reg;
407#ifdef CONFIG_R8169_VLAN
408 struct vlan_group *vlgrp;
409#endif
410 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
411 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
412 void (*phy_reset_enable)(void __iomem *);
413 unsigned int (*phy_reset_pending)(void __iomem *);
414 unsigned int (*link_ok)(void __iomem *);
415 struct work_struct task;
416};
417
418MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@oss.sgi.com>");
419MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
420module_param_array(media, int, &num_media, 0);
421module_param(rx_copybreak, int, 0);
422module_param(use_dac, int, 0);
423MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
424MODULE_LICENSE("GPL");
425MODULE_VERSION(RTL8169_VERSION);
426
427static int rtl8169_open(struct net_device *dev);
428static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
429static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
430 struct pt_regs *regs);
431static int rtl8169_init_ring(struct net_device *dev);
432static void rtl8169_hw_start(struct net_device *dev);
433static int rtl8169_close(struct net_device *dev);
434static void rtl8169_set_rx_mode(struct net_device *dev);
435static void rtl8169_tx_timeout(struct net_device *dev);
436static struct net_device_stats *rtl8169_get_stats(struct net_device *netdev);
437static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
438 void __iomem *);
439static int rtl8169_change_mtu(struct net_device *netdev, int new_mtu);
440static void rtl8169_down(struct net_device *dev);
441
442#ifdef CONFIG_R8169_NAPI
443static int rtl8169_poll(struct net_device *dev, int *budget);
444#endif
445
446static const u16 rtl8169_intr_mask =
447 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
448static const u16 rtl8169_napi_event =
449 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
450static const unsigned int rtl8169_rx_config =
451 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
452
453#define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
454#define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
455#define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
456#define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
457
458static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
459{
460 int i;
461
462 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
463 udelay(1000);
464
465 for (i = 2000; i > 0; i--) {
466 /* Check if the RTL8169 has completed writing to the specified MII register */
467 if (!(RTL_R32(PHYAR) & 0x80000000))
468 break;
469 udelay(100);
470 }
471}
472
473static int mdio_read(void __iomem *ioaddr, int RegAddr)
474{
475 int i, value = -1;
476
477 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
478 udelay(1000);
479
480 for (i = 2000; i > 0; i--) {
481 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
482 if (RTL_R32(PHYAR) & 0x80000000) {
483 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
484 break;
485 }
486 udelay(100);
487 }
488 return value;
489}
490
491static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
492{
493 RTL_W16(IntrMask, 0x0000);
494
495 RTL_W16(IntrStatus, 0xffff);
496}
497
498static void rtl8169_asic_down(void __iomem *ioaddr)
499{
500 RTL_W8(ChipCmd, 0x00);
501 rtl8169_irq_mask_and_ack(ioaddr);
502 RTL_R16(CPlusCmd);
503}
504
505static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
506{
507 return RTL_R32(TBICSR) & TBIReset;
508}
509
510static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
511{
512 return mdio_read(ioaddr, 0) & 0x8000;
513}
514
515static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
516{
517 return RTL_R32(TBICSR) & TBILinkOk;
518}
519
520static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
521{
522 return RTL_R8(PHYstatus) & LinkStatus;
523}
524
525static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
526{
527 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
528}
529
530static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
531{
532 unsigned int val;
533
534 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
535 mdio_write(ioaddr, PHY_CTRL_REG, val);
536}
537
538static void rtl8169_check_link_status(struct net_device *dev,
539 struct rtl8169_private *tp, void __iomem *ioaddr)
540{
541 unsigned long flags;
542
543 spin_lock_irqsave(&tp->lock, flags);
544 if (tp->link_ok(ioaddr)) {
545 netif_carrier_on(dev);
546 printk(KERN_INFO PFX "%s: link up\n", dev->name);
547 } else
548 netif_carrier_off(dev);
549 spin_unlock_irqrestore(&tp->lock, flags);
550}
551
552static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
553{
554 struct {
555 u16 speed;
556 u8 duplex;
557 u8 autoneg;
558 u8 media;
559 } link_settings[] = {
560 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
561 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
562 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
563 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
564 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
565 /* Make TBI happy */
566 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
567 }, *p;
568 unsigned char option;
569
570 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
571
572 if ((option != 0xff) && !idx)
573 printk(KERN_WARNING PFX "media option is deprecated.\n");
574
575 for (p = link_settings; p->media != 0xff; p++) {
576 if (p->media == option)
577 break;
578 }
579 *autoneg = p->autoneg;
580 *speed = p->speed;
581 *duplex = p->duplex;
582}
583
584static void rtl8169_get_drvinfo(struct net_device *dev,
585 struct ethtool_drvinfo *info)
586{
587 struct rtl8169_private *tp = netdev_priv(dev);
588
589 strcpy(info->driver, MODULENAME);
590 strcpy(info->version, RTL8169_VERSION);
591 strcpy(info->bus_info, pci_name(tp->pci_dev));
592}
593
594static int rtl8169_get_regs_len(struct net_device *dev)
595{
596 return R8169_REGS_SIZE;
597}
598
599static int rtl8169_set_speed_tbi(struct net_device *dev,
600 u8 autoneg, u16 speed, u8 duplex)
601{
602 struct rtl8169_private *tp = netdev_priv(dev);
603 void __iomem *ioaddr = tp->mmio_addr;
604 int ret = 0;
605 u32 reg;
606
607 reg = RTL_R32(TBICSR);
608 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
609 (duplex == DUPLEX_FULL)) {
610 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
611 } else if (autoneg == AUTONEG_ENABLE)
612 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
613 else {
614 printk(KERN_WARNING PFX
615 "%s: incorrect speed setting refused in TBI mode\n",
616 dev->name);
617 ret = -EOPNOTSUPP;
618 }
619
620 return ret;
621}
622
623static int rtl8169_set_speed_xmii(struct net_device *dev,
624 u8 autoneg, u16 speed, u8 duplex)
625{
626 struct rtl8169_private *tp = netdev_priv(dev);
627 void __iomem *ioaddr = tp->mmio_addr;
628 int auto_nego, giga_ctrl;
629
630 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
631 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
632 PHY_Cap_100_Half | PHY_Cap_100_Full);
633 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
634 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
635
636 if (autoneg == AUTONEG_ENABLE) {
637 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
638 PHY_Cap_100_Half | PHY_Cap_100_Full);
639 giga_ctrl |= PHY_Cap_1000_Full;
640 } else {
641 if (speed == SPEED_10)
642 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
643 else if (speed == SPEED_100)
644 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
645 else if (speed == SPEED_1000)
646 giga_ctrl |= PHY_Cap_1000_Full;
647
648 if (duplex == DUPLEX_HALF)
649 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
650 }
651
652 tp->phy_auto_nego_reg = auto_nego;
653 tp->phy_1000_ctrl_reg = giga_ctrl;
654
655 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
656 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
657 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
658 PHY_Restart_Auto_Nego);
659 return 0;
660}
661
662static int rtl8169_set_speed(struct net_device *dev,
663 u8 autoneg, u16 speed, u8 duplex)
664{
665 struct rtl8169_private *tp = netdev_priv(dev);
666 int ret;
667
668 ret = tp->set_speed(dev, autoneg, speed, duplex);
669
670 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
671 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
672
673 return ret;
674}
675
676static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
677{
678 struct rtl8169_private *tp = netdev_priv(dev);
679 unsigned long flags;
680 int ret;
681
682 spin_lock_irqsave(&tp->lock, flags);
683 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
684 spin_unlock_irqrestore(&tp->lock, flags);
685
686 return ret;
687}
688
689static u32 rtl8169_get_rx_csum(struct net_device *dev)
690{
691 struct rtl8169_private *tp = netdev_priv(dev);
692
693 return tp->cp_cmd & RxChkSum;
694}
695
696static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
697{
698 struct rtl8169_private *tp = netdev_priv(dev);
699 void __iomem *ioaddr = tp->mmio_addr;
700 unsigned long flags;
701
702 spin_lock_irqsave(&tp->lock, flags);
703
704 if (data)
705 tp->cp_cmd |= RxChkSum;
706 else
707 tp->cp_cmd &= ~RxChkSum;
708
709 RTL_W16(CPlusCmd, tp->cp_cmd);
710 RTL_R16(CPlusCmd);
711
712 spin_unlock_irqrestore(&tp->lock, flags);
713
714 return 0;
715}
716
717#ifdef CONFIG_R8169_VLAN
718
719static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
720 struct sk_buff *skb)
721{
722 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
723 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
724}
725
726static void rtl8169_vlan_rx_register(struct net_device *dev,
727 struct vlan_group *grp)
728{
729 struct rtl8169_private *tp = netdev_priv(dev);
730 void __iomem *ioaddr = tp->mmio_addr;
731 unsigned long flags;
732
733 spin_lock_irqsave(&tp->lock, flags);
734 tp->vlgrp = grp;
735 if (tp->vlgrp)
736 tp->cp_cmd |= RxVlan;
737 else
738 tp->cp_cmd &= ~RxVlan;
739 RTL_W16(CPlusCmd, tp->cp_cmd);
740 RTL_R16(CPlusCmd);
741 spin_unlock_irqrestore(&tp->lock, flags);
742}
743
744static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
745{
746 struct rtl8169_private *tp = netdev_priv(dev);
747 unsigned long flags;
748
749 spin_lock_irqsave(&tp->lock, flags);
750 if (tp->vlgrp)
751 tp->vlgrp->vlan_devices[vid] = NULL;
752 spin_unlock_irqrestore(&tp->lock, flags);
753}
754
755static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
756 struct sk_buff *skb)
757{
758 u32 opts2 = le32_to_cpu(desc->opts2);
759 int ret;
760
761 if (tp->vlgrp && (opts2 & RxVlanTag)) {
762 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
763 swab16(opts2 & 0xffff));
764 ret = 0;
765 } else
766 ret = -1;
767 desc->opts2 = 0;
768 return ret;
769}
770
771#else /* !CONFIG_R8169_VLAN */
772
773static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
774 struct sk_buff *skb)
775{
776 return 0;
777}
778
779static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
780 struct sk_buff *skb)
781{
782 return -1;
783}
784
785#endif
786
787static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
788{
789 struct rtl8169_private *tp = netdev_priv(dev);
790 void __iomem *ioaddr = tp->mmio_addr;
791 u32 status;
792
793 cmd->supported =
794 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
795 cmd->port = PORT_FIBRE;
796 cmd->transceiver = XCVR_INTERNAL;
797
798 status = RTL_R32(TBICSR);
799 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
800 cmd->autoneg = !!(status & TBINwEnable);
801
802 cmd->speed = SPEED_1000;
803 cmd->duplex = DUPLEX_FULL; /* Always set */
804}
805
806static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
807{
808 struct rtl8169_private *tp = netdev_priv(dev);
809 void __iomem *ioaddr = tp->mmio_addr;
810 u8 status;
811
812 cmd->supported = SUPPORTED_10baseT_Half |
813 SUPPORTED_10baseT_Full |
814 SUPPORTED_100baseT_Half |
815 SUPPORTED_100baseT_Full |
816 SUPPORTED_1000baseT_Full |
817 SUPPORTED_Autoneg |
818 SUPPORTED_TP;
819
820 cmd->autoneg = 1;
821 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
822
823 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
824 cmd->advertising |= ADVERTISED_10baseT_Half;
825 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
826 cmd->advertising |= ADVERTISED_10baseT_Full;
827 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
828 cmd->advertising |= ADVERTISED_100baseT_Half;
829 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
830 cmd->advertising |= ADVERTISED_100baseT_Full;
831 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
832 cmd->advertising |= ADVERTISED_1000baseT_Full;
833
834 status = RTL_R8(PHYstatus);
835
836 if (status & _1000bpsF)
837 cmd->speed = SPEED_1000;
838 else if (status & _100bps)
839 cmd->speed = SPEED_100;
840 else if (status & _10bps)
841 cmd->speed = SPEED_10;
842
843 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
844 DUPLEX_FULL : DUPLEX_HALF;
845}
846
847static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
848{
849 struct rtl8169_private *tp = netdev_priv(dev);
850 unsigned long flags;
851
852 spin_lock_irqsave(&tp->lock, flags);
853
854 tp->get_settings(dev, cmd);
855
856 spin_unlock_irqrestore(&tp->lock, flags);
857 return 0;
858}
859
860static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
861 void *p)
862{
863 struct rtl8169_private *tp = netdev_priv(dev);
864 unsigned long flags;
865
866 if (regs->len > R8169_REGS_SIZE)
867 regs->len = R8169_REGS_SIZE;
868
869 spin_lock_irqsave(&tp->lock, flags);
870 memcpy_fromio(p, tp->mmio_addr, regs->len);
871 spin_unlock_irqrestore(&tp->lock, flags);
872}
873
874static struct ethtool_ops rtl8169_ethtool_ops = {
875 .get_drvinfo = rtl8169_get_drvinfo,
876 .get_regs_len = rtl8169_get_regs_len,
877 .get_link = ethtool_op_get_link,
878 .get_settings = rtl8169_get_settings,
879 .set_settings = rtl8169_set_settings,
880 .get_rx_csum = rtl8169_get_rx_csum,
881 .set_rx_csum = rtl8169_set_rx_csum,
882 .get_tx_csum = ethtool_op_get_tx_csum,
883 .set_tx_csum = ethtool_op_set_tx_csum,
884 .get_sg = ethtool_op_get_sg,
885 .set_sg = ethtool_op_set_sg,
886 .get_tso = ethtool_op_get_tso,
887 .set_tso = ethtool_op_set_tso,
888 .get_regs = rtl8169_get_regs,
889};
890
891static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
892 int bitval)
893{
894 int val;
895
896 val = mdio_read(ioaddr, reg);
897 val = (bitval == 1) ?
898 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
899 mdio_write(ioaddr, reg, val & 0xffff);
900}
901
902static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
903{
904 const struct {
905 u32 mask;
906 int mac_version;
907 } mac_info[] = {
908 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
909 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
910 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
911 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
912 }, *p = mac_info;
913 u32 reg;
914
915 reg = RTL_R32(TxConfig) & 0x7c800000;
916 while ((reg & p->mask) != p->mask)
917 p++;
918 tp->mac_version = p->mac_version;
919}
920
921static void rtl8169_print_mac_version(struct rtl8169_private *tp)
922{
923 struct {
924 int version;
925 char *msg;
926 } mac_print[] = {
927 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
928 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
929 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
930 { 0, NULL }
931 }, *p;
932
933 for (p = mac_print; p->msg; p++) {
934 if (tp->mac_version == p->version) {
935 dprintk("mac_version == %s (%04d)\n", p->msg,
936 p->version);
937 return;
938 }
939 }
940 dprintk("mac_version == Unknown\n");
941}
942
943static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
944{
945 const struct {
946 u16 mask;
947 u16 set;
948 int phy_version;
949 } phy_info[] = {
950 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
951 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
952 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
953 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
954 }, *p = phy_info;
955 u16 reg;
956
957 reg = mdio_read(ioaddr, 3) & 0xffff;
958 while ((reg & p->mask) != p->set)
959 p++;
960 tp->phy_version = p->phy_version;
961}
962
963static void rtl8169_print_phy_version(struct rtl8169_private *tp)
964{
965 struct {
966 int version;
967 char *msg;
968 u32 reg;
969 } phy_print[] = {
970 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
971 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
972 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
973 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
974 { 0, NULL, 0x0000 }
975 }, *p;
976
977 for (p = phy_print; p->msg; p++) {
978 if (tp->phy_version == p->version) {
979 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
980 return;
981 }
982 }
983 dprintk("phy_version == Unknown\n");
984}
985
986static void rtl8169_hw_phy_config(struct net_device *dev)
987{
988 struct rtl8169_private *tp = netdev_priv(dev);
989 void __iomem *ioaddr = tp->mmio_addr;
990 struct {
991 u16 regs[5]; /* Beware of bit-sign propagation */
992 } phy_magic[5] = { {
993 { 0x0000, //w 4 15 12 0
994 0x00a1, //w 3 15 0 00a1
995 0x0008, //w 2 15 0 0008
996 0x1020, //w 1 15 0 1020
997 0x1000 } },{ //w 0 15 0 1000
998 { 0x7000, //w 4 15 12 7
999 0xff41, //w 3 15 0 ff41
1000 0xde60, //w 2 15 0 de60
1001 0x0140, //w 1 15 0 0140
1002 0x0077 } },{ //w 0 15 0 0077
1003 { 0xa000, //w 4 15 12 a
1004 0xdf01, //w 3 15 0 df01
1005 0xdf20, //w 2 15 0 df20
1006 0xff95, //w 1 15 0 ff95
1007 0xfa00 } },{ //w 0 15 0 fa00
1008 { 0xb000, //w 4 15 12 b
1009 0xff41, //w 3 15 0 ff41
1010 0xde20, //w 2 15 0 de20
1011 0x0140, //w 1 15 0 0140
1012 0x00bb } },{ //w 0 15 0 00bb
1013 { 0xf000, //w 4 15 12 f
1014 0xdf01, //w 3 15 0 df01
1015 0xdf20, //w 2 15 0 df20
1016 0xff95, //w 1 15 0 ff95
1017 0xbf00 } //w 0 15 0 bf00
1018 }
1019 }, *p = phy_magic;
1020 int i;
1021
1022 rtl8169_print_mac_version(tp);
1023 rtl8169_print_phy_version(tp);
1024
1025 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1026 return;
1027 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1028 return;
1029
1030 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1031 dprintk("Do final_reg2.cfg\n");
1032
1033 /* Shazam ! */
1034
1035 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1036 mdio_write(ioaddr, 31, 0x0001);
1037 mdio_write(ioaddr, 9, 0x273a);
1038 mdio_write(ioaddr, 14, 0x7bfb);
1039 mdio_write(ioaddr, 27, 0x841e);
1040
1041 mdio_write(ioaddr, 31, 0x0002);
1042 mdio_write(ioaddr, 1, 0x90d0);
1043 mdio_write(ioaddr, 31, 0x0000);
1044 return;
1045 }
1046
1047 /* phy config for RTL8169s mac_version C chip */
1048 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1049 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1050 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1051 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1052
1053 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1054 int val, pos = 4;
1055
1056 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1057 mdio_write(ioaddr, pos, val);
1058 while (--pos >= 0)
1059 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1060 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1061 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1062 }
1063 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1064}
1065
1066static void rtl8169_phy_timer(unsigned long __opaque)
1067{
1068 struct net_device *dev = (struct net_device *)__opaque;
1069 struct rtl8169_private *tp = netdev_priv(dev);
1070 struct timer_list *timer = &tp->timer;
1071 void __iomem *ioaddr = tp->mmio_addr;
1072 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1073
1074 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1075 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1076
1077 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1078 return;
1079
1080 spin_lock_irq(&tp->lock);
1081
1082 if (tp->phy_reset_pending(ioaddr)) {
1083 /*
1084 * A busy loop could burn quite a few cycles on nowadays CPU.
1085 * Let's delay the execution of the timer for a few ticks.
1086 */
1087 timeout = HZ/10;
1088 goto out_mod_timer;
1089 }
1090
1091 if (tp->link_ok(ioaddr))
1092 goto out_unlock;
1093
1094 printk(KERN_WARNING PFX "%s: PHY reset until link up\n", dev->name);
1095
1096 tp->phy_reset_enable(ioaddr);
1097
1098out_mod_timer:
1099 mod_timer(timer, jiffies + timeout);
1100out_unlock:
1101 spin_unlock_irq(&tp->lock);
1102}
1103
1104static inline void rtl8169_delete_timer(struct net_device *dev)
1105{
1106 struct rtl8169_private *tp = netdev_priv(dev);
1107 struct timer_list *timer = &tp->timer;
1108
1109 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1110 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1111 return;
1112
1113 del_timer_sync(timer);
1114}
1115
1116static inline void rtl8169_request_timer(struct net_device *dev)
1117{
1118 struct rtl8169_private *tp = netdev_priv(dev);
1119 struct timer_list *timer = &tp->timer;
1120
1121 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1122 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1123 return;
1124
1125 init_timer(timer);
1126 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1127 timer->data = (unsigned long)(dev);
1128 timer->function = rtl8169_phy_timer;
1129 add_timer(timer);
1130}
1131
1132#ifdef CONFIG_NET_POLL_CONTROLLER
1133/*
1134 * Polling 'interrupt' - used by things like netconsole to send skbs
1135 * without having to re-enable interrupts. It's not called while
1136 * the interrupt routine is executing.
1137 */
1138static void rtl8169_netpoll(struct net_device *dev)
1139{
1140 struct rtl8169_private *tp = netdev_priv(dev);
1141 struct pci_dev *pdev = tp->pci_dev;
1142
1143 disable_irq(pdev->irq);
1144 rtl8169_interrupt(pdev->irq, dev, NULL);
1145 enable_irq(pdev->irq);
1146}
1147#endif
1148
1149static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1150 void __iomem *ioaddr)
1151{
1152 iounmap(ioaddr);
1153 pci_release_regions(pdev);
1154 pci_disable_device(pdev);
1155 free_netdev(dev);
1156}
1157
1158static int __devinit
1159rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1160 void __iomem **ioaddr_out)
1161{
1162 void __iomem *ioaddr;
1163 struct net_device *dev;
1164 struct rtl8169_private *tp;
1165 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1166
1167 assert(ioaddr_out != NULL);
1168
1169 /* dev zeroed in alloc_etherdev */
1170 dev = alloc_etherdev(sizeof (*tp));
1171 if (dev == NULL) {
1172 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1173 goto err_out;
1174 }
1175
1176 SET_MODULE_OWNER(dev);
1177 SET_NETDEV_DEV(dev, &pdev->dev);
1178 tp = netdev_priv(dev);
1179
1180 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1181 rc = pci_enable_device(pdev);
1182 if (rc) {
1183 printk(KERN_ERR PFX "%s: enable failure\n", pci_name(pdev));
1184 goto err_out_free_dev;
1185 }
1186
1187 rc = pci_set_mwi(pdev);
1188 if (rc < 0)
1189 goto err_out_disable;
1190
1191 /* save power state before pci_enable_device overwrites it */
1192 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1193 if (pm_cap) {
1194 u16 pwr_command;
1195
1196 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1197 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1198 } else {
1199 printk(KERN_ERR PFX
1200 "Cannot find PowerManagement capability, aborting.\n");
1201 goto err_out_mwi;
1202 }
1203
1204 /* make sure PCI base addr 1 is MMIO */
1205 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1206 printk(KERN_ERR PFX
1207 "region #1 not an MMIO resource, aborting\n");
1208 rc = -ENODEV;
1209 goto err_out_mwi;
1210 }
1211 /* check for weird/broken PCI region reporting */
1212 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1213 printk(KERN_ERR PFX "Invalid PCI region size(s), aborting\n");
1214 rc = -ENODEV;
1215 goto err_out_mwi;
1216 }
1217
1218 rc = pci_request_regions(pdev, MODULENAME);
1219 if (rc) {
1220 printk(KERN_ERR PFX "%s: could not request regions.\n",
1221 pci_name(pdev));
1222 goto err_out_mwi;
1223 }
1224
1225 tp->cp_cmd = PCIMulRW | RxChkSum;
1226
1227 if ((sizeof(dma_addr_t) > 4) &&
1228 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1229 tp->cp_cmd |= PCIDAC;
1230 dev->features |= NETIF_F_HIGHDMA;
1231 } else {
1232 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1233 if (rc < 0) {
1234 printk(KERN_ERR PFX "DMA configuration failed.\n");
1235 goto err_out_free_res;
1236 }
1237 }
1238
1239 pci_set_master(pdev);
1240
1241 /* ioremap MMIO region */
1242 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1243 if (ioaddr == NULL) {
1244 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1245 rc = -EIO;
1246 goto err_out_free_res;
1247 }
1248
1249 /* Unneeded ? Don't mess with Mrs. Murphy. */
1250 rtl8169_irq_mask_and_ack(ioaddr);
1251
1252 /* Soft reset the chip. */
1253 RTL_W8(ChipCmd, CmdReset);
1254
1255 /* Check that the chip has finished the reset. */
1256 for (i = 1000; i > 0; i--) {
1257 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1258 break;
1259 udelay(10);
1260 }
1261
1262 /* Identify chip attached to board */
1263 rtl8169_get_mac_version(tp, ioaddr);
1264 rtl8169_get_phy_version(tp, ioaddr);
1265
1266 rtl8169_print_mac_version(tp);
1267 rtl8169_print_phy_version(tp);
1268
1269 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1270 if (tp->mac_version == rtl_chip_info[i].mac_version)
1271 break;
1272 }
1273 if (i < 0) {
1274 /* Unknown chip: assume array element #0, original RTL-8169 */
1275 printk(KERN_DEBUG PFX
1276 "PCI device %s: unknown chip version, assuming %s\n",
1277 pci_name(pdev), rtl_chip_info[0].name);
1278 i++;
1279 }
1280 tp->chipset = i;
1281
1282 *ioaddr_out = ioaddr;
1283 *dev_out = dev;
1284out:
1285 return rc;
1286
1287err_out_free_res:
1288 pci_release_regions(pdev);
1289
1290err_out_mwi:
1291 pci_clear_mwi(pdev);
1292
1293err_out_disable:
1294 pci_disable_device(pdev);
1295
1296err_out_free_dev:
1297 free_netdev(dev);
1298err_out:
1299 *ioaddr_out = NULL;
1300 *dev_out = NULL;
1301 goto out;
1302}
1303
1304static int __devinit
1305rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1306{
1307 struct net_device *dev = NULL;
1308 struct rtl8169_private *tp;
1309 void __iomem *ioaddr = NULL;
1310 static int board_idx = -1;
1311 static int printed_version = 0;
1312 u8 autoneg, duplex;
1313 u16 speed;
1314 int i, rc;
1315
1316 assert(pdev != NULL);
1317 assert(ent != NULL);
1318
1319 board_idx++;
1320
1321 if (!printed_version) {
1322 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1323 MODULENAME, RTL8169_VERSION);
1324 printed_version = 1;
1325 }
1326
1327 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1328 if (rc)
1329 return rc;
1330
1331 tp = netdev_priv(dev);
1332 assert(ioaddr != NULL);
1333
1334 if (RTL_R8(PHYstatus) & TBI_Enable) {
1335 tp->set_speed = rtl8169_set_speed_tbi;
1336 tp->get_settings = rtl8169_gset_tbi;
1337 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1338 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1339 tp->link_ok = rtl8169_tbi_link_ok;
1340
1341 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1342 } else {
1343 tp->set_speed = rtl8169_set_speed_xmii;
1344 tp->get_settings = rtl8169_gset_xmii;
1345 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1346 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1347 tp->link_ok = rtl8169_xmii_link_ok;
1348 }
1349
1350 /* Get MAC address. FIXME: read EEPROM */
1351 for (i = 0; i < MAC_ADDR_LEN; i++)
1352 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1353
1354 dev->open = rtl8169_open;
1355 dev->hard_start_xmit = rtl8169_start_xmit;
1356 dev->get_stats = rtl8169_get_stats;
1357 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1358 dev->stop = rtl8169_close;
1359 dev->tx_timeout = rtl8169_tx_timeout;
1360 dev->set_multicast_list = rtl8169_set_rx_mode;
1361 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1362 dev->irq = pdev->irq;
1363 dev->base_addr = (unsigned long) ioaddr;
1364 dev->change_mtu = rtl8169_change_mtu;
1365
1366#ifdef CONFIG_R8169_NAPI
1367 dev->poll = rtl8169_poll;
1368 dev->weight = R8169_NAPI_WEIGHT;
1369 printk(KERN_INFO PFX "NAPI enabled\n");
1370#endif
1371
1372#ifdef CONFIG_R8169_VLAN
1373 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1374 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1375 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1376#endif
1377
1378#ifdef CONFIG_NET_POLL_CONTROLLER
1379 dev->poll_controller = rtl8169_netpoll;
1380#endif
1381
1382 tp->intr_mask = 0xffff;
1383 tp->pci_dev = pdev;
1384 tp->mmio_addr = ioaddr;
1385
1386 spin_lock_init(&tp->lock);
1387
1388 rc = register_netdev(dev);
1389 if (rc) {
1390 rtl8169_release_board(pdev, dev, ioaddr);
1391 return rc;
1392 }
1393
1394 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n", dev->name,
1395 rtl_chip_info[tp->chipset].name);
1396
1397 pci_set_drvdata(pdev, dev);
1398
1399 printk(KERN_INFO "%s: %s at 0x%lx, "
1400 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1401 "IRQ %d\n",
1402 dev->name,
1403 rtl_chip_info[ent->driver_data].name,
1404 dev->base_addr,
1405 dev->dev_addr[0], dev->dev_addr[1],
1406 dev->dev_addr[2], dev->dev_addr[3],
1407 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1408
1409 rtl8169_hw_phy_config(dev);
1410
1411 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1412 RTL_W8(0x82, 0x01);
1413
1414 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1415 dprintk("Set PCI Latency=0x40\n");
1416 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1417 }
1418
1419 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1420 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1421 RTL_W8(0x82, 0x01);
1422 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1423 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1424 }
1425
1426 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1427
1428 rtl8169_set_speed(dev, autoneg, speed, duplex);
1429
1430 if (RTL_R8(PHYstatus) & TBI_Enable)
1431 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1432
1433 return 0;
1434}
1435
1436static void __devexit
1437rtl8169_remove_one(struct pci_dev *pdev)
1438{
1439 struct net_device *dev = pci_get_drvdata(pdev);
1440 struct rtl8169_private *tp = netdev_priv(dev);
1441
1442 assert(dev != NULL);
1443 assert(tp != NULL);
1444
1445 unregister_netdev(dev);
1446 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1447 pci_set_drvdata(pdev, NULL);
1448}
1449
1450#ifdef CONFIG_PM
1451
1452static int rtl8169_suspend(struct pci_dev *pdev, u32 state)
1453{
1454 struct net_device *dev = pci_get_drvdata(pdev);
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 void __iomem *ioaddr = tp->mmio_addr;
1457 unsigned long flags;
1458
1459 if (!netif_running(dev))
1460 return 0;
1461
1462 netif_device_detach(dev);
1463 netif_stop_queue(dev);
1464 spin_lock_irqsave(&tp->lock, flags);
1465
1466 /* Disable interrupts, stop Rx and Tx */
1467 RTL_W16(IntrMask, 0);
1468 RTL_W8(ChipCmd, 0);
1469
1470 /* Update the error counts. */
1471 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
1472 RTL_W32(RxMissed, 0);
1473 spin_unlock_irqrestore(&tp->lock, flags);
1474
1475 return 0;
1476}
1477
1478static int rtl8169_resume(struct pci_dev *pdev)
1479{
1480 struct net_device *dev = pci_get_drvdata(pdev);
1481
1482 if (!netif_running(dev))
1483 return 0;
1484
1485 netif_device_attach(dev);
1486 rtl8169_hw_start(dev);
1487
1488 return 0;
1489}
1490
1491#endif /* CONFIG_PM */
1492
1493static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1494 struct net_device *dev)
1495{
1496 unsigned int mtu = dev->mtu;
1497
1498 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1499}
1500
1501static int rtl8169_open(struct net_device *dev)
1502{
1503 struct rtl8169_private *tp = netdev_priv(dev);
1504 struct pci_dev *pdev = tp->pci_dev;
1505 int retval;
1506
1507 rtl8169_set_rxbufsize(tp, dev);
1508
1509 retval =
1510 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1511 if (retval < 0)
1512 goto out;
1513
1514 retval = -ENOMEM;
1515
1516 /*
1517 * Rx and Tx desscriptors needs 256 bytes alignment.
1518 * pci_alloc_consistent provides more.
1519 */
1520 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1521 &tp->TxPhyAddr);
1522 if (!tp->TxDescArray)
1523 goto err_free_irq;
1524
1525 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1526 &tp->RxPhyAddr);
1527 if (!tp->RxDescArray)
1528 goto err_free_tx;
1529
1530 retval = rtl8169_init_ring(dev);
1531 if (retval < 0)
1532 goto err_free_rx;
1533
1534 INIT_WORK(&tp->task, NULL, dev);
1535
1536 rtl8169_hw_start(dev);
1537
1538 rtl8169_request_timer(dev);
1539
1540 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1541out:
1542 return retval;
1543
1544err_free_rx:
1545 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1546 tp->RxPhyAddr);
1547err_free_tx:
1548 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1549 tp->TxPhyAddr);
1550err_free_irq:
1551 free_irq(dev->irq, dev);
1552 goto out;
1553}
1554
1555static void rtl8169_hw_reset(void __iomem *ioaddr)
1556{
1557 /* Disable interrupts */
1558 rtl8169_irq_mask_and_ack(ioaddr);
1559
1560 /* Reset the chipset */
1561 RTL_W8(ChipCmd, CmdReset);
1562
1563 /* PCI commit */
1564 RTL_R8(ChipCmd);
1565}
1566
1567static void
1568rtl8169_hw_start(struct net_device *dev)
1569{
1570 struct rtl8169_private *tp = netdev_priv(dev);
1571 void __iomem *ioaddr = tp->mmio_addr;
1572 u32 i;
1573
1574 /* Soft reset the chip. */
1575 RTL_W8(ChipCmd, CmdReset);
1576
1577 /* Check that the chip has finished the reset. */
1578 for (i = 1000; i > 0; i--) {
1579 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1580 break;
1581 udelay(10);
1582 }
1583
1584 RTL_W8(Cfg9346, Cfg9346_Unlock);
1585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1586 RTL_W8(EarlyTxThres, EarlyTxThld);
1587
1588 /* For gigabit rtl8169, MTU + header + CRC + VLAN */
1589 RTL_W16(RxMaxSize, tp->rx_buf_sz);
1590
1591 /* Set Rx Config register */
1592 i = rtl8169_rx_config |
1593 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1594 RTL_W32(RxConfig, i);
1595
1596 /* Set DMA burst size and Interframe Gap Time */
1597 RTL_W32(TxConfig,
1598 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1599 TxInterFrameGapShift));
1600 tp->cp_cmd |= RTL_R16(CPlusCmd);
1601 RTL_W16(CPlusCmd, tp->cp_cmd);
1602
1603 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1604 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1605 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1606 "Bit-3 and bit-14 MUST be 1\n");
1607 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1608 RTL_W16(CPlusCmd, tp->cp_cmd);
1609 }
1610
1611 /*
1612 * Undocumented corner. Supposedly:
1613 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1614 */
1615 RTL_W16(IntrMitigate, 0x0000);
1616
1617 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1618 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1619 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1620 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1621 RTL_W8(Cfg9346, Cfg9346_Lock);
1622 udelay(10);
1623
1624 RTL_W32(RxMissed, 0);
1625
1626 rtl8169_set_rx_mode(dev);
1627
1628 /* no early-rx interrupts */
1629 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1630
1631 /* Enable all known interrupts by setting the interrupt mask. */
1632 RTL_W16(IntrMask, rtl8169_intr_mask);
1633
1634 netif_start_queue(dev);
1635}
1636
1637static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1638{
1639 struct rtl8169_private *tp = netdev_priv(dev);
1640 int ret = 0;
1641
1642 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1643 return -EINVAL;
1644
1645 dev->mtu = new_mtu;
1646
1647 if (!netif_running(dev))
1648 goto out;
1649
1650 rtl8169_down(dev);
1651
1652 rtl8169_set_rxbufsize(tp, dev);
1653
1654 ret = rtl8169_init_ring(dev);
1655 if (ret < 0)
1656 goto out;
1657
1658 netif_poll_enable(dev);
1659
1660 rtl8169_hw_start(dev);
1661
1662 rtl8169_request_timer(dev);
1663
1664out:
1665 return ret;
1666}
1667
1668static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1669{
1670 desc->addr = 0x0badbadbadbadbadull;
1671 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1672}
1673
1674static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1675 struct sk_buff **sk_buff, struct RxDesc *desc)
1676{
1677 struct pci_dev *pdev = tp->pci_dev;
1678
1679 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1680 PCI_DMA_FROMDEVICE);
1681 dev_kfree_skb(*sk_buff);
1682 *sk_buff = NULL;
1683 rtl8169_make_unusable_by_asic(desc);
1684}
1685
1686static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1687{
1688 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1689
1690 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1691}
1692
1693static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1694 u32 rx_buf_sz)
1695{
1696 desc->addr = cpu_to_le64(mapping);
1697 wmb();
1698 rtl8169_mark_to_asic(desc, rx_buf_sz);
1699}
1700
1701static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1702 struct RxDesc *desc, int rx_buf_sz)
1703{
1704 struct sk_buff *skb;
1705 dma_addr_t mapping;
1706 int ret = 0;
1707
1708 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1709 if (!skb)
1710 goto err_out;
1711
1712 skb_reserve(skb, NET_IP_ALIGN);
1713 *sk_buff = skb;
1714
1715 mapping = pci_map_single(pdev, skb->tail, rx_buf_sz,
1716 PCI_DMA_FROMDEVICE);
1717
1718 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1719
1720out:
1721 return ret;
1722
1723err_out:
1724 ret = -ENOMEM;
1725 rtl8169_make_unusable_by_asic(desc);
1726 goto out;
1727}
1728
1729static void rtl8169_rx_clear(struct rtl8169_private *tp)
1730{
1731 int i;
1732
1733 for (i = 0; i < NUM_RX_DESC; i++) {
1734 if (tp->Rx_skbuff[i]) {
1735 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1736 tp->RxDescArray + i);
1737 }
1738 }
1739}
1740
1741static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1742 u32 start, u32 end)
1743{
1744 u32 cur;
1745
1746 for (cur = start; end - cur > 0; cur++) {
1747 int ret, i = cur % NUM_RX_DESC;
1748
1749 if (tp->Rx_skbuff[i])
1750 continue;
1751
1752 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1753 tp->RxDescArray + i, tp->rx_buf_sz);
1754 if (ret < 0)
1755 break;
1756 }
1757 return cur - start;
1758}
1759
1760static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1761{
1762 desc->opts1 |= cpu_to_le32(RingEnd);
1763}
1764
1765static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1766{
1767 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1768}
1769
1770static int rtl8169_init_ring(struct net_device *dev)
1771{
1772 struct rtl8169_private *tp = netdev_priv(dev);
1773
1774 rtl8169_init_ring_indexes(tp);
1775
1776 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1777 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
1778
1779 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
1780 goto err_out;
1781
1782 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
1783
1784 return 0;
1785
1786err_out:
1787 rtl8169_rx_clear(tp);
1788 return -ENOMEM;
1789}
1790
1791static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
1792 struct TxDesc *desc)
1793{
1794 unsigned int len = tx_skb->len;
1795
1796 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
1797 desc->opts1 = 0x00;
1798 desc->opts2 = 0x00;
1799 desc->addr = 0x00;
1800 tx_skb->len = 0;
1801}
1802
1803static void rtl8169_tx_clear(struct rtl8169_private *tp)
1804{
1805 unsigned int i;
1806
1807 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
1808 unsigned int entry = i % NUM_TX_DESC;
1809 struct ring_info *tx_skb = tp->tx_skb + entry;
1810 unsigned int len = tx_skb->len;
1811
1812 if (len) {
1813 struct sk_buff *skb = tx_skb->skb;
1814
1815 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
1816 tp->TxDescArray + entry);
1817 if (skb) {
1818 dev_kfree_skb(skb);
1819 tx_skb->skb = NULL;
1820 }
1821 tp->stats.tx_dropped++;
1822 }
1823 }
1824 tp->cur_tx = tp->dirty_tx = 0;
1825}
1826
1827static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
1828{
1829 struct rtl8169_private *tp = netdev_priv(dev);
1830
1831 PREPARE_WORK(&tp->task, task, dev);
1832 schedule_delayed_work(&tp->task, 4);
1833}
1834
1835static void rtl8169_wait_for_quiescence(struct net_device *dev)
1836{
1837 struct rtl8169_private *tp = netdev_priv(dev);
1838 void __iomem *ioaddr = tp->mmio_addr;
1839
1840 synchronize_irq(dev->irq);
1841
1842 /* Wait for any pending NAPI task to complete */
1843 netif_poll_disable(dev);
1844
1845 rtl8169_irq_mask_and_ack(ioaddr);
1846
1847 netif_poll_enable(dev);
1848}
1849
1850static void rtl8169_reinit_task(void *_data)
1851{
1852 struct net_device *dev = _data;
1853 int ret;
1854
1855 if (netif_running(dev)) {
1856 rtl8169_wait_for_quiescence(dev);
1857 rtl8169_close(dev);
1858 }
1859
1860 ret = rtl8169_open(dev);
1861 if (unlikely(ret < 0)) {
1862 if (net_ratelimit()) {
1863 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
1864 " Rescheduling.\n", dev->name, ret);
1865 }
1866 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1867 }
1868}
1869
1870static void rtl8169_reset_task(void *_data)
1871{
1872 struct net_device *dev = _data;
1873 struct rtl8169_private *tp = netdev_priv(dev);
1874
1875 if (!netif_running(dev))
1876 return;
1877
1878 rtl8169_wait_for_quiescence(dev);
1879
1880 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
1881 rtl8169_tx_clear(tp);
1882
1883 if (tp->dirty_rx == tp->cur_rx) {
1884 rtl8169_init_ring_indexes(tp);
1885 rtl8169_hw_start(dev);
1886 netif_wake_queue(dev);
1887 } else {
1888 if (net_ratelimit()) {
1889 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
1890 dev->name);
1891 }
1892 rtl8169_schedule_work(dev, rtl8169_reset_task);
1893 }
1894}
1895
1896static void rtl8169_tx_timeout(struct net_device *dev)
1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899
1900 rtl8169_hw_reset(tp->mmio_addr);
1901
1902 /* Let's wait a bit while any (async) irq lands on */
1903 rtl8169_schedule_work(dev, rtl8169_reset_task);
1904}
1905
1906static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
1907 u32 opts1)
1908{
1909 struct skb_shared_info *info = skb_shinfo(skb);
1910 unsigned int cur_frag, entry;
1911 struct TxDesc *txd;
1912
1913 entry = tp->cur_tx;
1914 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
1915 skb_frag_t *frag = info->frags + cur_frag;
1916 dma_addr_t mapping;
1917 u32 status, len;
1918 void *addr;
1919
1920 entry = (entry + 1) % NUM_TX_DESC;
1921
1922 txd = tp->TxDescArray + entry;
1923 len = frag->size;
1924 addr = ((void *) page_address(frag->page)) + frag->page_offset;
1925 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
1926
1927 /* anti gcc 2.95.3 bugware (sic) */
1928 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1929
1930 txd->opts1 = cpu_to_le32(status);
1931 txd->addr = cpu_to_le64(mapping);
1932
1933 tp->tx_skb[entry].len = len;
1934 }
1935
1936 if (cur_frag) {
1937 tp->tx_skb[entry].skb = skb;
1938 txd->opts1 |= cpu_to_le32(LastFrag);
1939 }
1940
1941 return cur_frag;
1942}
1943
1944static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
1945{
1946 if (dev->features & NETIF_F_TSO) {
1947 u32 mss = skb_shinfo(skb)->tso_size;
1948
1949 if (mss)
1950 return LargeSend | ((mss & MSSMask) << MSSShift);
1951 }
1952 if (skb->ip_summed == CHECKSUM_HW) {
1953 const struct iphdr *ip = skb->nh.iph;
1954
1955 if (ip->protocol == IPPROTO_TCP)
1956 return IPCS | TCPCS;
1957 else if (ip->protocol == IPPROTO_UDP)
1958 return IPCS | UDPCS;
1959 WARN_ON(1); /* we need a WARN() */
1960 }
1961 return 0;
1962}
1963
1964static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
1965{
1966 struct rtl8169_private *tp = netdev_priv(dev);
1967 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
1968 struct TxDesc *txd = tp->TxDescArray + entry;
1969 void __iomem *ioaddr = tp->mmio_addr;
1970 dma_addr_t mapping;
1971 u32 status, len;
1972 u32 opts1;
1973 int ret = 0;
1974
1975 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
1976 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1977 dev->name);
1978 goto err_stop;
1979 }
1980
1981 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
1982 goto err_stop;
1983
1984 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
1985
1986 frags = rtl8169_xmit_frags(tp, skb, opts1);
1987 if (frags) {
1988 len = skb_headlen(skb);
1989 opts1 |= FirstFrag;
1990 } else {
1991 len = skb->len;
1992
1993 if (unlikely(len < ETH_ZLEN)) {
1994 skb = skb_padto(skb, ETH_ZLEN);
1995 if (!skb)
1996 goto err_update_stats;
1997 len = ETH_ZLEN;
1998 }
1999
2000 opts1 |= FirstFrag | LastFrag;
2001 tp->tx_skb[entry].skb = skb;
2002 }
2003
2004 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2005
2006 tp->tx_skb[entry].len = len;
2007 txd->addr = cpu_to_le64(mapping);
2008 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2009
2010 wmb();
2011
2012 /* anti gcc 2.95.3 bugware (sic) */
2013 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2014 txd->opts1 = cpu_to_le32(status);
2015
2016 dev->trans_start = jiffies;
2017
2018 tp->cur_tx += frags + 1;
2019
2020 smp_wmb();
2021
2022 RTL_W8(TxPoll, 0x40); /* set polling bit */
2023
2024 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2025 netif_stop_queue(dev);
2026 smp_rmb();
2027 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2028 netif_wake_queue(dev);
2029 }
2030
2031out:
2032 return ret;
2033
2034err_stop:
2035 netif_stop_queue(dev);
2036 ret = 1;
2037err_update_stats:
2038 tp->stats.tx_dropped++;
2039 goto out;
2040}
2041
2042static void rtl8169_pcierr_interrupt(struct net_device *dev)
2043{
2044 struct rtl8169_private *tp = netdev_priv(dev);
2045 struct pci_dev *pdev = tp->pci_dev;
2046 void __iomem *ioaddr = tp->mmio_addr;
2047 u16 pci_status, pci_cmd;
2048
2049 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2050 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2051
2052 printk(KERN_ERR PFX "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2053 dev->name, pci_cmd, pci_status);
2054
2055 /*
2056 * The recovery sequence below admits a very elaborated explanation:
2057 * - it seems to work;
2058 * - I did not see what else could be done.
2059 *
2060 * Feel free to adjust to your needs.
2061 */
2062 pci_write_config_word(pdev, PCI_COMMAND,
2063 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
2064
2065 pci_write_config_word(pdev, PCI_STATUS,
2066 pci_status & (PCI_STATUS_DETECTED_PARITY |
2067 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2068 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2069
2070 /* The infamous DAC f*ckup only happens at boot time */
2071 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2072 printk(KERN_INFO PFX "%s: disabling PCI DAC.\n", dev->name);
2073 tp->cp_cmd &= ~PCIDAC;
2074 RTL_W16(CPlusCmd, tp->cp_cmd);
2075 dev->features &= ~NETIF_F_HIGHDMA;
2076 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2077 }
2078
2079 rtl8169_hw_reset(ioaddr);
2080}
2081
2082static void
2083rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2084 void __iomem *ioaddr)
2085{
2086 unsigned int dirty_tx, tx_left;
2087
2088 assert(dev != NULL);
2089 assert(tp != NULL);
2090 assert(ioaddr != NULL);
2091
2092 dirty_tx = tp->dirty_tx;
2093 smp_rmb();
2094 tx_left = tp->cur_tx - dirty_tx;
2095
2096 while (tx_left > 0) {
2097 unsigned int entry = dirty_tx % NUM_TX_DESC;
2098 struct ring_info *tx_skb = tp->tx_skb + entry;
2099 u32 len = tx_skb->len;
2100 u32 status;
2101
2102 rmb();
2103 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2104 if (status & DescOwn)
2105 break;
2106
2107 tp->stats.tx_bytes += len;
2108 tp->stats.tx_packets++;
2109
2110 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2111
2112 if (status & LastFrag) {
2113 dev_kfree_skb_irq(tx_skb->skb);
2114 tx_skb->skb = NULL;
2115 }
2116 dirty_tx++;
2117 tx_left--;
2118 }
2119
2120 if (tp->dirty_tx != dirty_tx) {
2121 tp->dirty_tx = dirty_tx;
2122 smp_wmb();
2123 if (netif_queue_stopped(dev) &&
2124 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2125 netif_wake_queue(dev);
2126 }
2127 }
2128}
2129
2130static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2131{
2132 u32 opts1 = le32_to_cpu(desc->opts1);
2133 u32 status = opts1 & RxProtoMask;
2134
2135 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2136 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2137 ((status == RxProtoIP) && !(opts1 & IPFail)))
2138 skb->ip_summed = CHECKSUM_UNNECESSARY;
2139 else
2140 skb->ip_summed = CHECKSUM_NONE;
2141}
2142
2143static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2144 struct RxDesc *desc, int rx_buf_sz)
2145{
2146 int ret = -1;
2147
2148 if (pkt_size < rx_copybreak) {
2149 struct sk_buff *skb;
2150
2151 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2152 if (skb) {
2153 skb_reserve(skb, NET_IP_ALIGN);
2154 eth_copy_and_sum(skb, sk_buff[0]->tail, pkt_size, 0);
2155 *sk_buff = skb;
2156 rtl8169_mark_to_asic(desc, rx_buf_sz);
2157 ret = 0;
2158 }
2159 }
2160 return ret;
2161}
2162
2163static int
2164rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2165 void __iomem *ioaddr)
2166{
2167 unsigned int cur_rx, rx_left;
2168 unsigned int delta, count;
2169
2170 assert(dev != NULL);
2171 assert(tp != NULL);
2172 assert(ioaddr != NULL);
2173
2174 cur_rx = tp->cur_rx;
2175 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2176 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2177
2178 while (rx_left > 0) {
2179 unsigned int entry = cur_rx % NUM_RX_DESC;
2180 u32 status;
2181
2182 rmb();
2183 status = le32_to_cpu(tp->RxDescArray[entry].opts1);
2184
2185 if (status & DescOwn)
2186 break;
2187 if (status & RxRES) {
2188 printk(KERN_INFO "%s: Rx ERROR!!!\n", dev->name);
2189 tp->stats.rx_errors++;
2190 if (status & (RxRWT | RxRUNT))
2191 tp->stats.rx_length_errors++;
2192 if (status & RxCRC)
2193 tp->stats.rx_crc_errors++;
2194 } else {
2195 struct RxDesc *desc = tp->RxDescArray + entry;
2196 struct sk_buff *skb = tp->Rx_skbuff[entry];
2197 int pkt_size = (status & 0x00001FFF) - 4;
2198 void (*pci_action)(struct pci_dev *, dma_addr_t,
2199 size_t, int) = pci_dma_sync_single_for_device;
2200
2201 rtl8169_rx_csum(skb, desc);
2202
2203 pci_dma_sync_single_for_cpu(tp->pci_dev,
2204 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2205 PCI_DMA_FROMDEVICE);
2206
2207 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2208 tp->rx_buf_sz)) {
2209 pci_action = pci_unmap_single;
2210 tp->Rx_skbuff[entry] = NULL;
2211 }
2212
2213 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2214 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2215
2216 skb->dev = dev;
2217 skb_put(skb, pkt_size);
2218 skb->protocol = eth_type_trans(skb, dev);
2219
2220 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2221 rtl8169_rx_skb(skb);
2222
2223 dev->last_rx = jiffies;
2224 tp->stats.rx_bytes += pkt_size;
2225 tp->stats.rx_packets++;
2226 }
2227
2228 cur_rx++;
2229 rx_left--;
2230 }
2231
2232 count = cur_rx - tp->cur_rx;
2233 tp->cur_rx = cur_rx;
2234
2235 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2236 if (!delta && count)
2237 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2238 tp->dirty_rx += delta;
2239
2240 /*
2241 * FIXME: until there is periodic timer to try and refill the ring,
2242 * a temporary shortage may definitely kill the Rx process.
2243 * - disable the asic to try and avoid an overflow and kick it again
2244 * after refill ?
2245 * - how do others driver handle this condition (Uh oh...).
2246 */
2247 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
2248 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2249
2250 return count;
2251}
2252
2253/* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2254static irqreturn_t
2255rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2256{
2257 struct net_device *dev = (struct net_device *) dev_instance;
2258 struct rtl8169_private *tp = netdev_priv(dev);
2259 int boguscnt = max_interrupt_work;
2260 void __iomem *ioaddr = tp->mmio_addr;
2261 int status;
2262 int handled = 0;
2263
2264 do {
2265 status = RTL_R16(IntrStatus);
2266
2267 /* hotplug/major error/no more work/shared irq */
2268 if ((status == 0xFFFF) || !status)
2269 break;
2270
2271 handled = 1;
2272
2273 if (unlikely(!netif_running(dev))) {
2274 rtl8169_asic_down(ioaddr);
2275 goto out;
2276 }
2277
2278 status &= tp->intr_mask;
2279 RTL_W16(IntrStatus,
2280 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2281
2282 if (!(status & rtl8169_intr_mask))
2283 break;
2284
2285 if (unlikely(status & SYSErr)) {
2286 rtl8169_pcierr_interrupt(dev);
2287 break;
2288 }
2289
2290 if (status & LinkChg)
2291 rtl8169_check_link_status(dev, tp, ioaddr);
2292
2293#ifdef CONFIG_R8169_NAPI
2294 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2295 tp->intr_mask = ~rtl8169_napi_event;
2296
2297 if (likely(netif_rx_schedule_prep(dev)))
2298 __netif_rx_schedule(dev);
2299 else {
2300 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2301 dev->name, status);
2302 }
2303 break;
2304#else
2305 /* Rx interrupt */
2306 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2307 rtl8169_rx_interrupt(dev, tp, ioaddr);
2308 }
2309 /* Tx interrupt */
2310 if (status & (TxOK | TxErr))
2311 rtl8169_tx_interrupt(dev, tp, ioaddr);
2312#endif
2313
2314 boguscnt--;
2315 } while (boguscnt > 0);
2316
2317 if (boguscnt <= 0) {
2318 printk(KERN_WARNING "%s: Too much work at interrupt!\n",
2319 dev->name);
2320 /* Clear all interrupt sources. */
2321 RTL_W16(IntrStatus, 0xffff);
2322 }
2323out:
2324 return IRQ_RETVAL(handled);
2325}
2326
2327#ifdef CONFIG_R8169_NAPI
2328static int rtl8169_poll(struct net_device *dev, int *budget)
2329{
2330 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2331 struct rtl8169_private *tp = netdev_priv(dev);
2332 void __iomem *ioaddr = tp->mmio_addr;
2333
2334 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2335 rtl8169_tx_interrupt(dev, tp, ioaddr);
2336
2337 *budget -= work_done;
2338 dev->quota -= work_done;
2339
2340 if (work_done < work_to_do) {
2341 netif_rx_complete(dev);
2342 tp->intr_mask = 0xffff;
2343 /*
2344 * 20040426: the barrier is not strictly required but the
2345 * behavior of the irq handler could be less predictable
2346 * without it. Btw, the lack of flush for the posted pci
2347 * write is safe - FR
2348 */
2349 smp_wmb();
2350 RTL_W16(IntrMask, rtl8169_intr_mask);
2351 }
2352
2353 return (work_done >= work_to_do);
2354}
2355#endif
2356
2357static void rtl8169_down(struct net_device *dev)
2358{
2359 struct rtl8169_private *tp = netdev_priv(dev);
2360 void __iomem *ioaddr = tp->mmio_addr;
2361 unsigned int poll_locked = 0;
2362
2363 rtl8169_delete_timer(dev);
2364
2365 netif_stop_queue(dev);
2366
2367 flush_scheduled_work();
2368
2369core_down:
2370 spin_lock_irq(&tp->lock);
2371
2372 rtl8169_asic_down(ioaddr);
2373
2374 /* Update the error counts. */
2375 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2376 RTL_W32(RxMissed, 0);
2377
2378 spin_unlock_irq(&tp->lock);
2379
2380 synchronize_irq(dev->irq);
2381
2382 if (!poll_locked) {
2383 netif_poll_disable(dev);
2384 poll_locked++;
2385 }
2386
2387 /* Give a racing hard_start_xmit a few cycles to complete. */
2388 synchronize_kernel();
2389
2390 /*
2391 * And now for the 50k$ question: are IRQ disabled or not ?
2392 *
2393 * Two paths lead here:
2394 * 1) dev->close
2395 * -> netif_running() is available to sync the current code and the
2396 * IRQ handler. See rtl8169_interrupt for details.
2397 * 2) dev->change_mtu
2398 * -> rtl8169_poll can not be issued again and re-enable the
2399 * interruptions. Let's simply issue the IRQ down sequence again.
2400 */
2401 if (RTL_R16(IntrMask))
2402 goto core_down;
2403
2404 rtl8169_tx_clear(tp);
2405
2406 rtl8169_rx_clear(tp);
2407}
2408
2409static int rtl8169_close(struct net_device *dev)
2410{
2411 struct rtl8169_private *tp = netdev_priv(dev);
2412 struct pci_dev *pdev = tp->pci_dev;
2413
2414 rtl8169_down(dev);
2415
2416 free_irq(dev->irq, dev);
2417
2418 netif_poll_enable(dev);
2419
2420 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2421 tp->RxPhyAddr);
2422 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2423 tp->TxPhyAddr);
2424 tp->TxDescArray = NULL;
2425 tp->RxDescArray = NULL;
2426
2427 return 0;
2428}
2429
2430static void
2431rtl8169_set_rx_mode(struct net_device *dev)
2432{
2433 struct rtl8169_private *tp = netdev_priv(dev);
2434 void __iomem *ioaddr = tp->mmio_addr;
2435 unsigned long flags;
2436 u32 mc_filter[2]; /* Multicast hash filter */
2437 int i, rx_mode;
2438 u32 tmp = 0;
2439
2440 if (dev->flags & IFF_PROMISC) {
2441 /* Unconditionally log net taps. */
2442 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2443 dev->name);
2444 rx_mode =
2445 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2446 AcceptAllPhys;
2447 mc_filter[1] = mc_filter[0] = 0xffffffff;
2448 } else if ((dev->mc_count > multicast_filter_limit)
2449 || (dev->flags & IFF_ALLMULTI)) {
2450 /* Too many to filter perfectly -- accept all multicasts. */
2451 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2452 mc_filter[1] = mc_filter[0] = 0xffffffff;
2453 } else {
2454 struct dev_mc_list *mclist;
2455 rx_mode = AcceptBroadcast | AcceptMyPhys;
2456 mc_filter[1] = mc_filter[0] = 0;
2457 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2458 i++, mclist = mclist->next) {
2459 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2460 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2461 rx_mode |= AcceptMulticast;
2462 }
2463 }
2464
2465 spin_lock_irqsave(&tp->lock, flags);
2466
2467 tmp = rtl8169_rx_config | rx_mode |
2468 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2469
2470 RTL_W32(RxConfig, tmp);
2471 RTL_W32(MAR0 + 0, mc_filter[0]);
2472 RTL_W32(MAR0 + 4, mc_filter[1]);
2473
2474 spin_unlock_irqrestore(&tp->lock, flags);
2475}
2476
2477/**
2478 * rtl8169_get_stats - Get rtl8169 read/write statistics
2479 * @dev: The Ethernet Device to get statistics for
2480 *
2481 * Get TX/RX statistics for rtl8169
2482 */
2483static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2484{
2485 struct rtl8169_private *tp = netdev_priv(dev);
2486 void __iomem *ioaddr = tp->mmio_addr;
2487 unsigned long flags;
2488
2489 if (netif_running(dev)) {
2490 spin_lock_irqsave(&tp->lock, flags);
2491 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2492 RTL_W32(RxMissed, 0);
2493 spin_unlock_irqrestore(&tp->lock, flags);
2494 }
2495
2496 return &tp->stats;
2497}
2498
2499static struct pci_driver rtl8169_pci_driver = {
2500 .name = MODULENAME,
2501 .id_table = rtl8169_pci_tbl,
2502 .probe = rtl8169_init_one,
2503 .remove = __devexit_p(rtl8169_remove_one),
2504#ifdef CONFIG_PM
2505 .suspend = rtl8169_suspend,
2506 .resume = rtl8169_resume,
2507#endif
2508};
2509
2510static int __init
2511rtl8169_init_module(void)
2512{
2513 return pci_module_init(&rtl8169_pci_driver);
2514}
2515
2516static void __exit
2517rtl8169_cleanup_module(void)
2518{
2519 pci_unregister_driver(&rtl8169_pci_driver);
2520}
2521
2522module_init(rtl8169_init_module);
2523module_exit(rtl8169_cleanup_module);
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