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drivers/net/: use DEFINE_PCI_DEVICE_TABLE()
[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
01935d7d
DF		 25#define DRV_VERSION "1.35"
26#define DRV_RELDATE "21.Apr.2008"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
d43c36dc 34#include <linux/sched.h>
1da177e4
LT		 35#include <linux/string.h>
36#include <linux/errno.h>
37#include <linux/ioport.h>
38#include <linux/slab.h>
39#include <linux/interrupt.h>
40#include <linux/pci.h>
41#include <linux/delay.h>
42#include <linux/init.h>
43#include <linux/ethtool.h>
44#include <linux/mii.h>
45#include <linux/crc32.h>
46#include <linux/netdevice.h>
47#include <linux/etherdevice.h>
48#include <linux/skbuff.h>
49#include <linux/spinlock.h>
50#include <linux/moduleparam.h>
51#include <linux/bitops.h>
52
53#include <asm/dma.h>
54#include <asm/io.h>
55#include <asm/uaccess.h>
56#include <asm/irq.h>
57
58/*
59 * PCI device identifiers for "new style" Linux PCI Device Drivers
60 */
a3aa1884 61static DEFINE_PCI_DEVICE_TABLE(pcnet32_pci_tbl) = {
f2622a2b
DF		 62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
63 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
4a5e8e29
JG		 64
65 /*
66 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
67 * the incorrect vendor id.
68 */
f2622a2b
DF		 69 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
70 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
4a5e8e29
JG		 71
72 { } /* terminate list */
1da177e4
LT		 73};
74
4a5e8e29 75MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 76
77static int cards_found;
78
79/*
80 * VLB I/O addresses
81 */
82static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 83 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 84
85static int pcnet32_debug = 0;
4a5e8e29
JG		 86static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
87static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 88
89static struct net_device *pcnet32_dev;
90
91static int max_interrupt_work = 2;
92static int rx_copybreak = 200;
93
94#define PCNET32_PORT_AUI 0x00
95#define PCNET32_PORT_10BT 0x01
96#define PCNET32_PORT_GPSI 0x02
97#define PCNET32_PORT_MII 0x03
98
99#define PCNET32_PORT_PORTSEL 0x03
100#define PCNET32_PORT_ASEL 0x04
101#define PCNET32_PORT_100 0x40
102#define PCNET32_PORT_FD 0x80
103
104#define PCNET32_DMA_MASK 0xffffffff
105
106#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
107#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
108
109/*
110 * table to translate option values from tulip
111 * to internal options
112 */
f71e1309 113static const unsigned char options_mapping[] = {
4a5e8e29
JG		 114 PCNET32_PORT_ASEL, /* 0 Auto-select */
115 PCNET32_PORT_AUI, /* 1 BNC/AUI */
116 PCNET32_PORT_AUI, /* 2 AUI/BNC */
117 PCNET32_PORT_ASEL, /* 3 not supported */
118 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
119 PCNET32_PORT_ASEL, /* 5 not supported */
120 PCNET32_PORT_ASEL, /* 6 not supported */
121 PCNET32_PORT_ASEL, /* 7 not supported */
122 PCNET32_PORT_ASEL, /* 8 not supported */
123 PCNET32_PORT_MII, /* 9 MII 10baseT */
124 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
125 PCNET32_PORT_MII, /* 11 MII (autosel) */
126 PCNET32_PORT_10BT, /* 12 10BaseT */
127 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
128 /* 14 MII 100BaseTx-FD */
129 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
130 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 131};
132
133static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 134 "Loopback test (offline)"
1da177e4 135};
4a5e8e29 136
4c3616cd 137#define PCNET32_TEST_LEN ARRAY_SIZE(pcnet32_gstrings_test)
1da177e4 138
ac62ef04 139#define PCNET32_NUM_REGS 136
1da177e4 140
4a5e8e29 141#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 142static int options[MAX_UNITS];
143static int full_duplex[MAX_UNITS];
144static int homepna[MAX_UNITS];
145
146/*
147 * Theory of Operation
148 *
149 * This driver uses the same software structure as the normal lance
150 * driver. So look for a verbose description in lance.c. The differences
151 * to the normal lance driver is the use of the 32bit mode of PCnet32
152 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
153 * 16MB limitation and we don't need bounce buffers.
154 */
155
1da177e4
LT		 156/*
157 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
158 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
159 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
160 */
161#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 162#define PCNET32_LOG_TX_BUFFERS 4
163#define PCNET32_LOG_RX_BUFFERS 5
164#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
165#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 166#endif
167
168#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 169#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 170
171#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 172#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4 173
232c5640
DF		 174#define PKT_BUF_SKB 1544
175/* actual buffer length after being aligned */
176#define PKT_BUF_SIZE (PKT_BUF_SKB - NET_IP_ALIGN)
177/* chip wants twos complement of the (aligned) buffer length */
178#define NEG_BUF_SIZE (NET_IP_ALIGN - PKT_BUF_SKB)
1da177e4
LT		 179
180/* Offsets from base I/O address. */
181#define PCNET32_WIO_RDP 0x10
182#define PCNET32_WIO_RAP 0x12
183#define PCNET32_WIO_RESET 0x14
184#define PCNET32_WIO_BDP 0x16
185
186#define PCNET32_DWIO_RDP 0x10
187#define PCNET32_DWIO_RAP 0x14
188#define PCNET32_DWIO_RESET 0x18
189#define PCNET32_DWIO_BDP 0x1C
190
191#define PCNET32_TOTAL_SIZE 0x20
192
06c87850
DF		 193#define CSR0 0
194#define CSR0_INIT 0x1
195#define CSR0_START 0x2
196#define CSR0_STOP 0x4
197#define CSR0_TXPOLL 0x8
198#define CSR0_INTEN 0x40
199#define CSR0_IDON 0x0100
200#define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
201#define PCNET32_INIT_LOW 1
202#define PCNET32_INIT_HIGH 2
203#define CSR3 3
204#define CSR4 4
205#define CSR5 5
206#define CSR5_SUSPEND 0x0001
207#define CSR15 15
208#define PCNET32_MC_FILTER 8
209
8d916266
DF		 210#define PCNET32_79C970A 0x2621
211
1da177e4
LT		 212/* The PCNET32 Rx and Tx ring descriptors. */
213struct pcnet32_rx_head {
3e33545b
AV		 214 __le32 base;
215 __le16 buf_length; /* two`s complement of length */
216 __le16 status;
217 __le32 msg_length;
218 __le32 reserved;
1da177e4
LT		 219};
220
221struct pcnet32_tx_head {
3e33545b
AV		 222 __le32 base;
223 __le16 length; /* two`s complement of length */
224 __le16 status;
225 __le32 misc;
226 __le32 reserved;
1da177e4
LT		 227};
228
229/* The PCNET32 32-Bit initialization block, described in databook. */
230struct pcnet32_init_block {
3e33545b
AV		 231 __le16 mode;
232 __le16 tlen_rlen;
0b5bf225 233 u8 phys_addr[6];
3e33545b
AV		 234 __le16 reserved;
235 __le32 filter[2];
4a5e8e29 236 /* Receive and transmit ring base, along with extra bits. */
3e33545b
AV		 237 __le32 rx_ring;
238 __le32 tx_ring;
1da177e4
LT		 239};
240
241/* PCnet32 access functions */
242struct pcnet32_access {
4a5e8e29
JG		 243 u16 (*read_csr) (unsigned long, int);
244 void (*write_csr) (unsigned long, int, u16);
245 u16 (*read_bcr) (unsigned long, int);
246 void (*write_bcr) (unsigned long, int, u16);
247 u16 (*read_rap) (unsigned long);
248 void (*write_rap) (unsigned long, u16);
249 void (*reset) (unsigned long);
1da177e4
LT		 250};
251
252/*
76209926
HWL		 253 * The first field of pcnet32_private is read by the ethernet device
254 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 255 */
256struct pcnet32_private {
6ecb7667 257 struct pcnet32_init_block *init_block;
4a5e8e29 258 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 259 struct pcnet32_rx_head *rx_ring;
260 struct pcnet32_tx_head *tx_ring;
6ecb7667
DF		 261 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
262 returned by pci_alloc_consistent */
0b5bf225
JG		 263 struct pci_dev *pci_dev;
264 const char *name;
4a5e8e29 265 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 266 struct sk_buff **tx_skbuff;
267 struct sk_buff **rx_skbuff;
268 dma_addr_t *tx_dma_addr;
269 dma_addr_t *rx_dma_addr;
270 struct pcnet32_access a;
271 spinlock_t lock; /* Guard lock */
272 unsigned int cur_rx, cur_tx; /* The next free ring entry */
273 unsigned int rx_ring_size; /* current rx ring size */
274 unsigned int tx_ring_size; /* current tx ring size */
275 unsigned int rx_mod_mask; /* rx ring modular mask */
276 unsigned int tx_mod_mask; /* tx ring modular mask */
277 unsigned short rx_len_bits;
278 unsigned short tx_len_bits;
279 dma_addr_t rx_ring_dma_addr;
280 dma_addr_t tx_ring_dma_addr;
281 unsigned int dirty_rx, /* ring entries to be freed. */
282 dirty_tx;
283
bea3348e
SH		 284 struct net_device *dev;
285 struct napi_struct napi;
0b5bf225
JG		 286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 297
298 /* each bit indicates an available PHY */
0b5bf225 299 u32 phymask;
8d916266 300 unsigned short chip_version; /* which variant this is */
1da177e4
LT		 301};
302
4a5e8e29
JG		 303static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305static int pcnet32_open(struct net_device *);
306static int pcnet32_init_ring(struct net_device *);
61357325
SH		 307static netdev_tx_t pcnet32_start_xmit(struct sk_buff *,
308 struct net_device *);
4a5e8e29 309static void pcnet32_tx_timeout(struct net_device *dev);
7d12e780 310static irqreturn_t pcnet32_interrupt(int, void *);
4a5e8e29 311static int pcnet32_close(struct net_device *);
1da177e4
LT		 312static struct net_device_stats *pcnet32_get_stats(struct net_device *);
313static void pcnet32_load_multicast(struct net_device *dev);
314static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 315static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 316static void pcnet32_watchdog(struct net_device *);
317static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 318static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
319 int val);
1da177e4
LT		 320static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
321static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 322 struct ethtool_test *eth_test, u64 * data);
323static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 324static int pcnet32_phys_id(struct net_device *dev, u32 data);
325static void pcnet32_led_blink_callback(struct net_device *dev);
326static int pcnet32_get_regs_len(struct net_device *dev);
327static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 328 void *ptr);
1bcd3153 329static void pcnet32_purge_tx_ring(struct net_device *dev);
b166cfba 330static int pcnet32_alloc_ring(struct net_device *dev, const char *name);
eabf0415 331static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 332static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 333
4a5e8e29 334static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 335{
4a5e8e29
JG		 336 outw(index, addr + PCNET32_WIO_RAP);
337 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 338}
339
4a5e8e29 340static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 341{
4a5e8e29
JG		 342 outw(index, addr + PCNET32_WIO_RAP);
343 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 344}
345
4a5e8e29 346static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 347{
4a5e8e29
JG		 348 outw(index, addr + PCNET32_WIO_RAP);
349 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 350}
351
4a5e8e29 352static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 353{
4a5e8e29
JG		 354 outw(index, addr + PCNET32_WIO_RAP);
355 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 356}
357
4a5e8e29 358static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 359{
4a5e8e29 360 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 361}
362
4a5e8e29 363static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 364{
4a5e8e29 365 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 366}
367
4a5e8e29 368static void pcnet32_wio_reset(unsigned long addr)
1da177e4 369{
4a5e8e29 370 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 371}
372
4a5e8e29 373static int pcnet32_wio_check(unsigned long addr)
1da177e4 374{
4a5e8e29
JG		 375 outw(88, addr + PCNET32_WIO_RAP);
376 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 377}
378
379static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 380 .read_csr = pcnet32_wio_read_csr,
381 .write_csr = pcnet32_wio_write_csr,
382 .read_bcr = pcnet32_wio_read_bcr,
383 .write_bcr = pcnet32_wio_write_bcr,
384 .read_rap = pcnet32_wio_read_rap,
385 .write_rap = pcnet32_wio_write_rap,
386 .reset = pcnet32_wio_reset
1da177e4
LT		 387};
388
4a5e8e29 389static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 390{
4a5e8e29
JG		 391 outl(index, addr + PCNET32_DWIO_RAP);
392 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 393}
394
4a5e8e29 395static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 396{
4a5e8e29
JG		 397 outl(index, addr + PCNET32_DWIO_RAP);
398 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 399}
400
4a5e8e29 401static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 402{
4a5e8e29
JG		 403 outl(index, addr + PCNET32_DWIO_RAP);
404 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 405}
406
4a5e8e29 407static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 408{
4a5e8e29
JG		 409 outl(index, addr + PCNET32_DWIO_RAP);
410 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 411}
412
4a5e8e29 413static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 414{
4a5e8e29 415 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 416}
417
4a5e8e29 418static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 419{
4a5e8e29 420 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 421}
422
4a5e8e29 423static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 424{
4a5e8e29 425 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 426}
427
4a5e8e29 428static int pcnet32_dwio_check(unsigned long addr)
1da177e4 429{
4a5e8e29
JG		 430 outl(88, addr + PCNET32_DWIO_RAP);
431 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 432}
433
434static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 435 .read_csr = pcnet32_dwio_read_csr,
436 .write_csr = pcnet32_dwio_write_csr,
437 .read_bcr = pcnet32_dwio_read_bcr,
438 .write_bcr = pcnet32_dwio_write_bcr,
439 .read_rap = pcnet32_dwio_read_rap,
440 .write_rap = pcnet32_dwio_write_rap,
441 .reset = pcnet32_dwio_reset
1da177e4
LT		 442};
443
06c87850
DF		 444static void pcnet32_netif_stop(struct net_device *dev)
445{
bea3348e 446 struct pcnet32_private *lp = netdev_priv(dev);
01935d7d 447
06c87850 448 dev->trans_start = jiffies;
bea3348e 449 napi_disable(&lp->napi);
06c87850
DF		 450 netif_tx_disable(dev);
451}
452
453static void pcnet32_netif_start(struct net_device *dev)
454{
bea3348e 455 struct pcnet32_private *lp = netdev_priv(dev);
d1d08d12
DM		 456 ulong ioaddr = dev->base_addr;
457 u16 val;
01935d7d 458
06c87850 459 netif_wake_queue(dev);
d1d08d12
DM		 460 val = lp->a.read_csr(ioaddr, CSR3);
461 val &= 0x00ff;
462 lp->a.write_csr(ioaddr, CSR3, val);
bea3348e 463 napi_enable(&lp->napi);
06c87850
DF		 464}
465
466/*
467 * Allocate space for the new sized tx ring.
468 * Free old resources
469 * Save new resources.
470 * Any failure keeps old resources.
471 * Must be called with lp->lock held.
472 */
473static void pcnet32_realloc_tx_ring(struct net_device *dev,
474 struct pcnet32_private *lp,
475 unsigned int size)
476{
477 dma_addr_t new_ring_dma_addr;
478 dma_addr_t *new_dma_addr_list;
479 struct pcnet32_tx_head *new_tx_ring;
480 struct sk_buff **new_skb_list;
481
482 pcnet32_purge_tx_ring(dev);
483
484 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
485 sizeof(struct pcnet32_tx_head) *
486 (1 << size),
487 &new_ring_dma_addr);
488 if (new_tx_ring == NULL) {
489 if (netif_msg_drv(lp))
ad361c98 490 printk(KERN_ERR
06c87850
DF		 491 "%s: Consistent memory allocation failed.\n",
492 dev->name);
493 return;
494 }
495 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
496
497 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
498 GFP_ATOMIC);
499 if (!new_dma_addr_list) {
500 if (netif_msg_drv(lp))
ad361c98 501 printk(KERN_ERR
06c87850
DF		 502 "%s: Memory allocation failed.\n", dev->name);
503 goto free_new_tx_ring;
504 }
505
506 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
507 GFP_ATOMIC);
508 if (!new_skb_list) {
509 if (netif_msg_drv(lp))
ad361c98 510 printk(KERN_ERR
06c87850
DF		 511 "%s: Memory allocation failed.\n", dev->name);
512 goto free_new_lists;
513 }
514
515 kfree(lp->tx_skbuff);
516 kfree(lp->tx_dma_addr);
517 pci_free_consistent(lp->pci_dev,
518 sizeof(struct pcnet32_tx_head) *
519 lp->tx_ring_size, lp->tx_ring,
520 lp->tx_ring_dma_addr);
521
522 lp->tx_ring_size = (1 << size);
523 lp->tx_mod_mask = lp->tx_ring_size - 1;
524 lp->tx_len_bits = (size << 12);
525 lp->tx_ring = new_tx_ring;
526 lp->tx_ring_dma_addr = new_ring_dma_addr;
527 lp->tx_dma_addr = new_dma_addr_list;
528 lp->tx_skbuff = new_skb_list;
529 return;
530
531 free_new_lists:
532 kfree(new_dma_addr_list);
533 free_new_tx_ring:
534 pci_free_consistent(lp->pci_dev,
535 sizeof(struct pcnet32_tx_head) *
536 (1 << size),
537 new_tx_ring,
538 new_ring_dma_addr);
539 return;
540}
541
542/*
543 * Allocate space for the new sized rx ring.
544 * Re-use old receive buffers.
545 * alloc extra buffers
546 * free unneeded buffers
547 * free unneeded buffers
548 * Save new resources.
549 * Any failure keeps old resources.
550 * Must be called with lp->lock held.
551 */
552static void pcnet32_realloc_rx_ring(struct net_device *dev,
553 struct pcnet32_private *lp,
554 unsigned int size)
555{
556 dma_addr_t new_ring_dma_addr;
557 dma_addr_t *new_dma_addr_list;
558 struct pcnet32_rx_head *new_rx_ring;
559 struct sk_buff **new_skb_list;
560 int new, overlap;
561
562 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
563 sizeof(struct pcnet32_rx_head) *
564 (1 << size),
565 &new_ring_dma_addr);
566 if (new_rx_ring == NULL) {
567 if (netif_msg_drv(lp))
ad361c98 568 printk(KERN_ERR
06c87850
DF		 569 "%s: Consistent memory allocation failed.\n",
570 dev->name);
571 return;
572 }
573 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
574
575 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
576 GFP_ATOMIC);
577 if (!new_dma_addr_list) {
578 if (netif_msg_drv(lp))
ad361c98 579 printk(KERN_ERR
06c87850
DF		 580 "%s: Memory allocation failed.\n", dev->name);
581 goto free_new_rx_ring;
582 }
583
584 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
585 GFP_ATOMIC);
586 if (!new_skb_list) {
587 if (netif_msg_drv(lp))
ad361c98 588 printk(KERN_ERR
06c87850
DF		 589 "%s: Memory allocation failed.\n", dev->name);
590 goto free_new_lists;
591 }
592
593 /* first copy the current receive buffers */
594 overlap = min(size, lp->rx_ring_size);
595 for (new = 0; new < overlap; new++) {
596 new_rx_ring[new] = lp->rx_ring[new];
597 new_dma_addr_list[new] = lp->rx_dma_addr[new];
598 new_skb_list[new] = lp->rx_skbuff[new];
599 }
600 /* now allocate any new buffers needed */
601 for (; new < size; new++ ) {
602 struct sk_buff *rx_skbuff;
232c5640 603 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
06c87850
DF		 604 if (!(rx_skbuff = new_skb_list[new])) {
605 /* keep the original lists and buffers */
606 if (netif_msg_drv(lp))
607 printk(KERN_ERR
608 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
609 dev->name);
610 goto free_all_new;
611 }
232c5640 612 skb_reserve(rx_skbuff, NET_IP_ALIGN);
06c87850
DF		 613
614 new_dma_addr_list[new] =
615 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 616 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 617 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
232c5640 618 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
3e33545b 619 new_rx_ring[new].status = cpu_to_le16(0x8000);
06c87850
DF		 620 }
621 /* and free any unneeded buffers */
622 for (; new < lp->rx_ring_size; new++) {
623 if (lp->rx_skbuff[new]) {
624 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
232c5640 625 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 626 dev_kfree_skb(lp->rx_skbuff[new]);
627 }
628 }
629
630 kfree(lp->rx_skbuff);
631 kfree(lp->rx_dma_addr);
632 pci_free_consistent(lp->pci_dev,
633 sizeof(struct pcnet32_rx_head) *
634 lp->rx_ring_size, lp->rx_ring,
635 lp->rx_ring_dma_addr);
636
637 lp->rx_ring_size = (1 << size);
638 lp->rx_mod_mask = lp->rx_ring_size - 1;
639 lp->rx_len_bits = (size << 4);
640 lp->rx_ring = new_rx_ring;
641 lp->rx_ring_dma_addr = new_ring_dma_addr;
642 lp->rx_dma_addr = new_dma_addr_list;
643 lp->rx_skbuff = new_skb_list;
644 return;
645
646 free_all_new:
647 for (; --new >= lp->rx_ring_size; ) {
648 if (new_skb_list[new]) {
649 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
232c5640 650 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
06c87850
DF		 651 dev_kfree_skb(new_skb_list[new]);
652 }
653 }
654 kfree(new_skb_list);
655 free_new_lists:
656 kfree(new_dma_addr_list);
657 free_new_rx_ring:
658 pci_free_consistent(lp->pci_dev,
659 sizeof(struct pcnet32_rx_head) *
660 (1 << size),
661 new_rx_ring,
662 new_ring_dma_addr);
663 return;
664}
665
ac5bfe40
DF		 666static void pcnet32_purge_rx_ring(struct net_device *dev)
667{
1e56a4b4 668 struct pcnet32_private *lp = netdev_priv(dev);
ac5bfe40
DF		 669 int i;
670
671 /* free all allocated skbuffs */
672 for (i = 0; i < lp->rx_ring_size; i++) {
673 lp->rx_ring[i].status = 0; /* CPU owns buffer */
674 wmb(); /* Make sure adapter sees owner change */
675 if (lp->rx_skbuff[i]) {
676 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
232c5640 677 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
ac5bfe40
DF		 678 dev_kfree_skb_any(lp->rx_skbuff[i]);
679 }
680 lp->rx_skbuff[i] = NULL;
681 lp->rx_dma_addr[i] = 0;
682 }
683}
684
1da177e4
LT		 685#ifdef CONFIG_NET_POLL_CONTROLLER
686static void pcnet32_poll_controller(struct net_device *dev)
687{
4a5e8e29 688 disable_irq(dev->irq);
7d12e780 689 pcnet32_interrupt(0, dev);
4a5e8e29 690 enable_irq(dev->irq);
1da177e4
LT		 691}
692#endif
693
1da177e4
LT		 694static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
695{
1e56a4b4 696 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 697 unsigned long flags;
698 int r = -EOPNOTSUPP;
1da177e4 699
4a5e8e29
JG		 700 if (lp->mii) {
701 spin_lock_irqsave(&lp->lock, flags);
702 mii_ethtool_gset(&lp->mii_if, cmd);
703 spin_unlock_irqrestore(&lp->lock, flags);
704 r = 0;
705 }
706 return r;
1da177e4
LT		 707}
708
709static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
710{
1e56a4b4 711 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 712 unsigned long flags;
713 int r = -EOPNOTSUPP;
1da177e4 714
4a5e8e29
JG		 715 if (lp->mii) {
716 spin_lock_irqsave(&lp->lock, flags);
717 r = mii_ethtool_sset(&lp->mii_if, cmd);
718 spin_unlock_irqrestore(&lp->lock, flags);
719 }
720 return r;
1da177e4
LT		 721}
722
4a5e8e29
JG		 723static void pcnet32_get_drvinfo(struct net_device *dev,
724 struct ethtool_drvinfo *info)
1da177e4 725{
1e56a4b4 726 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 727
728 strcpy(info->driver, DRV_NAME);
729 strcpy(info->version, DRV_VERSION);
730 if (lp->pci_dev)
731 strcpy(info->bus_info, pci_name(lp->pci_dev));
732 else
733 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 734}
735
736static u32 pcnet32_get_link(struct net_device *dev)
737{
1e56a4b4 738 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 739 unsigned long flags;
740 int r;
1da177e4 741
4a5e8e29
JG		 742 spin_lock_irqsave(&lp->lock, flags);
743 if (lp->mii) {
744 r = mii_link_ok(&lp->mii_if);
8d916266 745 } else if (lp->chip_version >= PCNET32_79C970A) {
4a5e8e29
JG		 746 ulong ioaddr = dev->base_addr; /* card base I/O address */
747 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
8d916266
DF		 748 } else { /* can not detect link on really old chips */
749 r = 1;
4a5e8e29
JG		 750 }
751 spin_unlock_irqrestore(&lp->lock, flags);
752
753 return r;
1da177e4
LT		 754}
755
756static u32 pcnet32_get_msglevel(struct net_device *dev)
757{
1e56a4b4 758 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 759 return lp->msg_enable;
1da177e4
LT		 760}
761
762static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
763{
1e56a4b4 764 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 765 lp->msg_enable = value;
1da177e4
LT		 766}
767
768static int pcnet32_nway_reset(struct net_device *dev)
769{
1e56a4b4 770 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 771 unsigned long flags;
772 int r = -EOPNOTSUPP;
1da177e4 773
4a5e8e29
JG		 774 if (lp->mii) {
775 spin_lock_irqsave(&lp->lock, flags);
776 r = mii_nway_restart(&lp->mii_if);
777 spin_unlock_irqrestore(&lp->lock, flags);
778 }
779 return r;
1da177e4
LT		 780}
781
4a5e8e29
JG		 782static void pcnet32_get_ringparam(struct net_device *dev,
783 struct ethtool_ringparam *ering)
1da177e4 784{
1e56a4b4 785 struct pcnet32_private *lp = netdev_priv(dev);
1da177e4 786
6dcd60c2
DF		 787 ering->tx_max_pending = TX_MAX_RING_SIZE;
788 ering->tx_pending = lp->tx_ring_size;
789 ering->rx_max_pending = RX_MAX_RING_SIZE;
790 ering->rx_pending = lp->rx_ring_size;
eabf0415
HWL		 791}
792
4a5e8e29
JG		 793static int pcnet32_set_ringparam(struct net_device *dev,
794 struct ethtool_ringparam *ering)
eabf0415 795{
1e56a4b4 796 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 797 unsigned long flags;
06c87850
DF		 798 unsigned int size;
799 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 800 int i;
801
802 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
803 return -EINVAL;
804
805 if (netif_running(dev))
06c87850 806 pcnet32_netif_stop(dev);
4a5e8e29
JG		 807
808 spin_lock_irqsave(&lp->lock, flags);
06c87850
DF		 809 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
810
811 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
4a5e8e29
JG		 812
813 /* set the minimum ring size to 4, to allow the loopback test to work
814 * unchanged.
815 */
816 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
06c87850 817 if (size <= (1 << i))
4a5e8e29
JG		 818 break;
819 }
06c87850
DF		 820 if ((1 << i) != lp->tx_ring_size)
821 pcnet32_realloc_tx_ring(dev, lp, i);
b368a3fb 822
06c87850 823 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
4a5e8e29 824 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
06c87850 825 if (size <= (1 << i))
4a5e8e29
JG		 826 break;
827 }
06c87850
DF		 828 if ((1 << i) != lp->rx_ring_size)
829 pcnet32_realloc_rx_ring(dev, lp, i);
b368a3fb 830
bea3348e 831 lp->napi.weight = lp->rx_ring_size / 2;
06c87850
DF		 832
833 if (netif_running(dev)) {
834 pcnet32_netif_start(dev);
835 pcnet32_restart(dev, CSR0_NORMAL);
4a5e8e29 836 }
eabf0415 837
4a5e8e29 838 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 839
06c87850
DF		 840 if (netif_msg_drv(lp))
841 printk(KERN_INFO
4a5e8e29
JG		 842 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
843 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 844
4a5e8e29 845 return 0;
1da177e4
LT		 846}
847
4a5e8e29
JG		 848static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
849 u8 * data)
1da177e4 850{
4a5e8e29 851 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 852}
853
b9f2c044 854static int pcnet32_get_sset_count(struct net_device *dev, int sset)
1da177e4 855{
b9f2c044
JG		 856 switch (sset) {
857 case ETH_SS_TEST:
858 return PCNET32_TEST_LEN;
859 default:
860 return -EOPNOTSUPP;
861 }
1da177e4
LT		 862}
863
864static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 865 struct ethtool_test *test, u64 * data)
1da177e4 866{
1e56a4b4 867 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 868 int rc;
869
870 if (test->flags == ETH_TEST_FL_OFFLINE) {
871 rc = pcnet32_loopback_test(dev, data);
872 if (rc) {
873 if (netif_msg_hw(lp))
874 printk(KERN_DEBUG "%s: Loopback test failed.\n",
875 dev->name);
876 test->flags |= ETH_TEST_FL_FAILED;
877 } else if (netif_msg_hw(lp))
878 printk(KERN_DEBUG "%s: Loopback test passed.\n",
879 dev->name);
1da177e4 880 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 881 printk(KERN_DEBUG
882 "%s: No tests to run (specify 'Offline' on ethtool).",
883 dev->name);
884} /* end pcnet32_ethtool_test */
1da177e4 885
4a5e8e29 886static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 887{
1e56a4b4 888 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 889 struct pcnet32_access *a = &lp->a; /* access to registers */
890 ulong ioaddr = dev->base_addr; /* card base I/O address */
891 struct sk_buff *skb; /* sk buff */
892 int x, i; /* counters */
893 int numbuffs = 4; /* number of TX/RX buffers and descs */
894 u16 status = 0x8300; /* TX ring status */
3e33545b 895 __le16 teststatus; /* test of ring status */
4a5e8e29
JG		 896 int rc; /* return code */
897 int size; /* size of packets */
898 unsigned char *packet; /* source packet data */
899 static const int data_len = 60; /* length of source packets */
900 unsigned long flags;
901 unsigned long ticks;
902
4a5e8e29
JG		 903 rc = 1; /* default to fail */
904
905 if (netif_running(dev))
7de745e5 906 pcnet32_netif_stop(dev);
4a5e8e29
JG		 907
908 spin_lock_irqsave(&lp->lock, flags);
ac5bfe40
DF		 909 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
910
911 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
4a5e8e29
JG		 912
913 /* Reset the PCNET32 */
914 lp->a.reset(ioaddr);
b368a3fb 915 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
4a5e8e29
JG		 916
917 /* switch pcnet32 to 32bit mode */
918 lp->a.write_bcr(ioaddr, 20, 2);
919
4a5e8e29
JG		 920 /* purge & init rings but don't actually restart */
921 pcnet32_restart(dev, 0x0000);
922
ac5bfe40 923 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 924
925 /* Initialize Transmit buffers. */
926 size = data_len + 15;
927 for (x = 0; x < numbuffs; x++) {
928 if (!(skb = dev_alloc_skb(size))) {
929 if (netif_msg_hw(lp))
930 printk(KERN_DEBUG
931 "%s: Cannot allocate skb at line: %d!\n",
932 dev->name, __LINE__);
933 goto clean_up;
934 } else {
935 packet = skb->data;
936 skb_put(skb, size); /* create space for data */
937 lp->tx_skbuff[x] = skb;
3e33545b 938 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
4a5e8e29
JG		 939 lp->tx_ring[x].misc = 0;
940
941 /* put DA and SA into the skb */
942 for (i = 0; i < 6; i++)
943 *packet++ = dev->dev_addr[i];
944 for (i = 0; i < 6; i++)
945 *packet++ = dev->dev_addr[i];
946 /* type */
947 *packet++ = 0x08;
948 *packet++ = 0x06;
949 /* packet number */
950 *packet++ = x;
951 /* fill packet with data */
952 for (i = 0; i < data_len; i++)
953 *packet++ = i;
954
955 lp->tx_dma_addr[x] =
956 pci_map_single(lp->pci_dev, skb->data, skb->len,
957 PCI_DMA_TODEVICE);
3e33545b 958 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
4a5e8e29 959 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 960 lp->tx_ring[x].status = cpu_to_le16(status);
4a5e8e29 961 }
1da177e4 962 }
1da177e4 963
ac5bfe40
DF		 964 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
965 a->write_bcr(ioaddr, 32, x | 0x0002);
4a5e8e29 966
ac5bfe40
DF		 967 /* set int loopback in CSR15 */
968 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
969 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
4a5e8e29 970
3e33545b 971 teststatus = cpu_to_le16(0x8000);
ac5bfe40 972 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
4a5e8e29
JG		 973
974 /* Check status of descriptors */
975 for (x = 0; x < numbuffs; x++) {
976 ticks = 0;
977 rmb();
978 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
979 spin_unlock_irqrestore(&lp->lock, flags);
ac5bfe40 980 msleep(1);
4a5e8e29
JG		 981 spin_lock_irqsave(&lp->lock, flags);
982 rmb();
983 ticks++;
984 }
985 if (ticks == 200) {
986 if (netif_msg_hw(lp))
987 printk("%s: Desc %d failed to reset!\n",
988 dev->name, x);
989 break;
990 }
991 }
992
ac5bfe40 993 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
4a5e8e29
JG		 994 wmb();
995 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
996 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
997
998 for (x = 0; x < numbuffs; x++) {
999 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1000 skb = lp->rx_skbuff[x];
1001 for (i = 0; i < size; i++) {
1002 printk("%02x ", *(skb->data + i));
1003 }
1004 printk("\n");
1005 }
1006 }
1da177e4 1007
4a5e8e29
JG		 1008 x = 0;
1009 rc = 0;
1010 while (x < numbuffs && !rc) {
1011 skb = lp->rx_skbuff[x];
1012 packet = lp->tx_skbuff[x]->data;
1013 for (i = 0; i < size; i++) {
1014 if (*(skb->data + i) != packet[i]) {
1015 if (netif_msg_hw(lp))
1016 printk(KERN_DEBUG
1017 "%s: Error in compare! %2x - %02x %02x\n",
1018 dev->name, i, *(skb->data + i),
1019 packet[i]);
1020 rc = 1;
1021 break;
1022 }
1023 }
1024 x++;
1025 }
1da177e4 1026
4a5e8e29 1027 clean_up:
ac5bfe40 1028 *data1 = rc;
4a5e8e29 1029 pcnet32_purge_tx_ring(dev);
1da177e4 1030
ac5bfe40
DF		 1031 x = a->read_csr(ioaddr, CSR15);
1032 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 1033
ac5bfe40
DF		 1034 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1035 a->write_bcr(ioaddr, 32, (x & ~0x0002));
4a5e8e29 1036
7de745e5
DF		 1037 if (netif_running(dev)) {
1038 pcnet32_netif_start(dev);
1039 pcnet32_restart(dev, CSR0_NORMAL);
1040 } else {
1041 pcnet32_purge_rx_ring(dev);
1042 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1043 }
1044 spin_unlock_irqrestore(&lp->lock, flags);
4a5e8e29
JG		 1045
1046 return (rc);
1047} /* end pcnet32_loopback_test */
1da177e4
LT		 1048
1049static void pcnet32_led_blink_callback(struct net_device *dev)
1050{
1e56a4b4 1051 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1052 struct pcnet32_access *a = &lp->a;
1053 ulong ioaddr = dev->base_addr;
1054 unsigned long flags;
1055 int i;
1056
1057 spin_lock_irqsave(&lp->lock, flags);
1058 for (i = 4; i < 8; i++) {
1059 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1060 }
1061 spin_unlock_irqrestore(&lp->lock, flags);
1062
1063 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 1064}
1065
1066static int pcnet32_phys_id(struct net_device *dev, u32 data)
1067{
1e56a4b4 1068 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1069 struct pcnet32_access *a = &lp->a;
1070 ulong ioaddr = dev->base_addr;
1071 unsigned long flags;
1072 int i, regs[4];
1073
1074 if (!lp->blink_timer.function) {
1075 init_timer(&lp->blink_timer);
1076 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1077 lp->blink_timer.data = (unsigned long)dev;
1078 }
1079
1080 /* Save the current value of the bcrs */
1081 spin_lock_irqsave(&lp->lock, flags);
1082 for (i = 4; i < 8; i++) {
1083 regs[i - 4] = a->read_bcr(ioaddr, i);
1084 }
1085 spin_unlock_irqrestore(&lp->lock, flags);
1086
1087 mod_timer(&lp->blink_timer, jiffies);
1088 set_current_state(TASK_INTERRUPTIBLE);
1089
3e33545b 1090 /* AV: the limit here makes no sense whatsoever */
4a5e8e29
JG		 1091 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1092 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1093
1094 msleep_interruptible(data * 1000);
1095 del_timer_sync(&lp->blink_timer);
1096
1097 /* Restore the original value of the bcrs */
1098 spin_lock_irqsave(&lp->lock, flags);
1099 for (i = 4; i < 8; i++) {
1100 a->write_bcr(ioaddr, i, regs[i - 4]);
1101 }
1102 spin_unlock_irqrestore(&lp->lock, flags);
1103
1104 return 0;
1da177e4
LT		 1105}
1106
df27f4a6
DF		 1107/*
1108 * lp->lock must be held.
1109 */
1110static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1111 int can_sleep)
1112{
1113 int csr5;
1e56a4b4 1114 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6
DF		 1115 struct pcnet32_access *a = &lp->a;
1116 ulong ioaddr = dev->base_addr;
1117 int ticks;
1118
8d916266
DF		 1119 /* really old chips have to be stopped. */
1120 if (lp->chip_version < PCNET32_79C970A)
1121 return 0;
1122
df27f4a6
DF		 1123 /* set SUSPEND (SPND) - CSR5 bit 0 */
1124 csr5 = a->read_csr(ioaddr, CSR5);
1125 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1126
1127 /* poll waiting for bit to be set */
1128 ticks = 0;
1129 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1130 spin_unlock_irqrestore(&lp->lock, *flags);
1131 if (can_sleep)
1132 msleep(1);
1133 else
1134 mdelay(1);
1135 spin_lock_irqsave(&lp->lock, *flags);
1136 ticks++;
1137 if (ticks > 200) {
1138 if (netif_msg_hw(lp))
1139 printk(KERN_DEBUG
1140 "%s: Error getting into suspend!\n",
1141 dev->name);
1142 return 0;
1143 }
1144 }
1145 return 1;
1146}
1147
3904c324
DF		 1148/*
1149 * process one receive descriptor entry
1150 */
1151
1152static void pcnet32_rx_entry(struct net_device *dev,
1153 struct pcnet32_private *lp,
1154 struct pcnet32_rx_head *rxp,
1155 int entry)
1156{
1157 int status = (short)le16_to_cpu(rxp->status) >> 8;
1158 int rx_in_place = 0;
1159 struct sk_buff *skb;
1160 short pkt_len;
1161
1162 if (status != 0x03) { /* There was an error. */
1163 /*
1164 * There is a tricky error noted by John Murphy,
1165 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1166 * buffers it's possible for a jabber packet to use two
1167 * buffers, with only the last correctly noting the error.
1168 */
1169 if (status & 0x01) /* Only count a general error at the */
4f1e5ba0 1170 dev->stats.rx_errors++; /* end of a packet. */
3904c324 1171 if (status & 0x20)
4f1e5ba0 1172 dev->stats.rx_frame_errors++;
3904c324 1173 if (status & 0x10)
4f1e5ba0 1174 dev->stats.rx_over_errors++;
3904c324 1175 if (status & 0x08)
4f1e5ba0 1176 dev->stats.rx_crc_errors++;
3904c324 1177 if (status & 0x04)
4f1e5ba0 1178 dev->stats.rx_fifo_errors++;
3904c324
DF		 1179 return;
1180 }
1181
1182 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1183
1184 /* Discard oversize frames. */
232c5640 1185 if (unlikely(pkt_len > PKT_BUF_SIZE)) {
3904c324
DF		 1186 if (netif_msg_drv(lp))
1187 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1188 dev->name, pkt_len);
4f1e5ba0 1189 dev->stats.rx_errors++;
3904c324
DF		 1190 return;
1191 }
1192 if (pkt_len < 60) {
1193 if (netif_msg_rx_err(lp))
1194 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
4f1e5ba0 1195 dev->stats.rx_errors++;
3904c324
DF		 1196 return;
1197 }
1198
1199 if (pkt_len > rx_copybreak) {
1200 struct sk_buff *newskb;
1201
232c5640
DF		 1202 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1203 skb_reserve(newskb, NET_IP_ALIGN);
3904c324
DF		 1204 skb = lp->rx_skbuff[entry];
1205 pci_unmap_single(lp->pci_dev,
1206 lp->rx_dma_addr[entry],
232c5640 1207 PKT_BUF_SIZE,
3904c324
DF		 1208 PCI_DMA_FROMDEVICE);
1209 skb_put(skb, pkt_len);
1210 lp->rx_skbuff[entry] = newskb;
3904c324
DF		 1211 lp->rx_dma_addr[entry] =
1212 pci_map_single(lp->pci_dev,
1213 newskb->data,
232c5640 1214 PKT_BUF_SIZE,
3904c324 1215 PCI_DMA_FROMDEVICE);
3e33545b 1216 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
3904c324
DF		 1217 rx_in_place = 1;
1218 } else
1219 skb = NULL;
1220 } else {
232c5640 1221 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
3904c324
DF		 1222 }
1223
1224 if (skb == NULL) {
1225 if (netif_msg_drv(lp))
1226 printk(KERN_ERR
1227 "%s: Memory squeeze, dropping packet.\n",
1228 dev->name);
4f1e5ba0 1229 dev->stats.rx_dropped++;
3904c324
DF		 1230 return;
1231 }
3904c324 1232 if (!rx_in_place) {
232c5640 1233 skb_reserve(skb, NET_IP_ALIGN);
3904c324
DF		 1234 skb_put(skb, pkt_len); /* Make room */
1235 pci_dma_sync_single_for_cpu(lp->pci_dev,
1236 lp->rx_dma_addr[entry],
b2cbbd8e 1237 pkt_len,
3904c324 1238 PCI_DMA_FROMDEVICE);
8c7b7faa 1239 skb_copy_to_linear_data(skb,
3904c324 1240 (unsigned char *)(lp->rx_skbuff[entry]->data),
8c7b7faa 1241 pkt_len);
3904c324
DF		 1242 pci_dma_sync_single_for_device(lp->pci_dev,
1243 lp->rx_dma_addr[entry],
b2cbbd8e 1244 pkt_len,
3904c324
DF		 1245 PCI_DMA_FROMDEVICE);
1246 }
4f1e5ba0 1247 dev->stats.rx_bytes += skb->len;
3904c324 1248 skb->protocol = eth_type_trans(skb, dev);
7de745e5 1249 netif_receive_skb(skb);
4f1e5ba0 1250 dev->stats.rx_packets++;
3904c324
DF		 1251 return;
1252}
1253
bea3348e 1254static int pcnet32_rx(struct net_device *dev, int budget)
9691edd2 1255{
1e56a4b4 1256 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2 1257 int entry = lp->cur_rx & lp->rx_mod_mask;
3904c324
DF		 1258 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1259 int npackets = 0;
9691edd2
DF		 1260
1261 /* If we own the next entry, it's a new packet. Send it up. */
bea3348e 1262 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
3904c324
DF		 1263 pcnet32_rx_entry(dev, lp, rxp, entry);
1264 npackets += 1;
9691edd2 1265 /*
3904c324
DF		 1266 * The docs say that the buffer length isn't touched, but Andrew
1267 * Boyd of QNX reports that some revs of the 79C965 clear it.
9691edd2 1268 */
232c5640 1269 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
3904c324 1270 wmb(); /* Make sure owner changes after others are visible */
3e33545b 1271 rxp->status = cpu_to_le16(0x8000);
9691edd2 1272 entry = (++lp->cur_rx) & lp->rx_mod_mask;
3904c324 1273 rxp = &lp->rx_ring[entry];
9691edd2
DF		 1274 }
1275
7de745e5 1276 return npackets;
9691edd2
DF		 1277}
1278
7de745e5 1279static int pcnet32_tx(struct net_device *dev)
9691edd2 1280{
1e56a4b4 1281 struct pcnet32_private *lp = netdev_priv(dev);
9691edd2
DF		 1282 unsigned int dirty_tx = lp->dirty_tx;
1283 int delta;
1284 int must_restart = 0;
1285
1286 while (dirty_tx != lp->cur_tx) {
1287 int entry = dirty_tx & lp->tx_mod_mask;
1288 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1289
1290 if (status < 0)
1291 break; /* It still hasn't been Txed */
1292
1293 lp->tx_ring[entry].base = 0;
1294
1295 if (status & 0x4000) {
3904c324 1296 /* There was a major error, log it. */
9691edd2 1297 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
4f1e5ba0 1298 dev->stats.tx_errors++;
9691edd2
DF		 1299 if (netif_msg_tx_err(lp))
1300 printk(KERN_ERR
1301 "%s: Tx error status=%04x err_status=%08x\n",
1302 dev->name, status,
1303 err_status);
1304 if (err_status & 0x04000000)
4f1e5ba0 1305 dev->stats.tx_aborted_errors++;
9691edd2 1306 if (err_status & 0x08000000)
4f1e5ba0 1307 dev->stats.tx_carrier_errors++;
9691edd2 1308 if (err_status & 0x10000000)
4f1e5ba0 1309 dev->stats.tx_window_errors++;
9691edd2
DF		 1310#ifndef DO_DXSUFLO
1311 if (err_status & 0x40000000) {
4f1e5ba0 1312 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1313 /* Ackk! On FIFO errors the Tx unit is turned off! */
1314 /* Remove this verbosity later! */
1315 if (netif_msg_tx_err(lp))
1316 printk(KERN_ERR
7de745e5
DF		 1317 "%s: Tx FIFO error!\n",
1318 dev->name);
9691edd2
DF		 1319 must_restart = 1;
1320 }
1321#else
1322 if (err_status & 0x40000000) {
4f1e5ba0 1323 dev->stats.tx_fifo_errors++;
9691edd2
DF		 1324 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1325 /* Ackk! On FIFO errors the Tx unit is turned off! */
1326 /* Remove this verbosity later! */
3904c324 1327 if (netif_msg_tx_err(lp))
9691edd2 1328 printk(KERN_ERR
7de745e5
DF		 1329 "%s: Tx FIFO error!\n",
1330 dev->name);
9691edd2
DF		 1331 must_restart = 1;
1332 }
1333 }
1334#endif
1335 } else {
1336 if (status & 0x1800)
4f1e5ba0
DF		 1337 dev->stats.collisions++;
1338 dev->stats.tx_packets++;
9691edd2
DF		 1339 }
1340
1341 /* We must free the original skb */
1342 if (lp->tx_skbuff[entry]) {
1343 pci_unmap_single(lp->pci_dev,
1344 lp->tx_dma_addr[entry],
1345 lp->tx_skbuff[entry]->
1346 len, PCI_DMA_TODEVICE);
3904c324 1347 dev_kfree_skb_any(lp->tx_skbuff[entry]);
9691edd2
DF		 1348 lp->tx_skbuff[entry] = NULL;
1349 lp->tx_dma_addr[entry] = 0;
1350 }
1351 dirty_tx++;
1352 }
1353
3904c324 1354 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
9691edd2
DF		 1355 if (delta > lp->tx_ring_size) {
1356 if (netif_msg_drv(lp))
1357 printk(KERN_ERR
1358 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1359 dev->name, dirty_tx, lp->cur_tx,
1360 lp->tx_full);
1361 dirty_tx += lp->tx_ring_size;
1362 delta -= lp->tx_ring_size;
1363 }
1364
1365 if (lp->tx_full &&
1366 netif_queue_stopped(dev) &&
1367 delta < lp->tx_ring_size - 2) {
1368 /* The ring is no longer full, clear tbusy. */
1369 lp->tx_full = 0;
1370 netif_wake_queue(dev);
1371 }
1372 lp->dirty_tx = dirty_tx;
1373
1374 return must_restart;
1375}
1376
bea3348e 1377static int pcnet32_poll(struct napi_struct *napi, int budget)
7de745e5 1378{
bea3348e
SH		 1379 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1380 struct net_device *dev = lp->dev;
7de745e5
DF		 1381 unsigned long ioaddr = dev->base_addr;
1382 unsigned long flags;
bea3348e 1383 int work_done;
7de745e5
DF		 1384 u16 val;
1385
bea3348e 1386 work_done = pcnet32_rx(dev, budget);
7de745e5
DF		 1387
1388 spin_lock_irqsave(&lp->lock, flags);
1389 if (pcnet32_tx(dev)) {
1390 /* reset the chip to clear the error condition, then restart */
1391 lp->a.reset(ioaddr);
1392 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1393 pcnet32_restart(dev, CSR0_START);
1394 netif_wake_queue(dev);
1395 }
1396 spin_unlock_irqrestore(&lp->lock, flags);
1397
bea3348e
SH		 1398 if (work_done < budget) {
1399 spin_lock_irqsave(&lp->lock, flags);
7de745e5 1400
288379f0 1401 __napi_complete(napi);
7de745e5 1402
bea3348e
SH		 1403 /* clear interrupt masks */
1404 val = lp->a.read_csr(ioaddr, CSR3);
1405 val &= 0x00ff;
1406 lp->a.write_csr(ioaddr, CSR3, val);
7de745e5 1407
bea3348e
SH		 1408 /* Set interrupt enable. */
1409 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
ce105a08 1410
bea3348e
SH		 1411 spin_unlock_irqrestore(&lp->lock, flags);
1412 }
1413 return work_done;
7de745e5 1414}
7de745e5 1415
ac62ef04
DF		 1416#define PCNET32_REGS_PER_PHY 32
1417#define PCNET32_MAX_PHYS 32
1da177e4
LT		 1418static int pcnet32_get_regs_len(struct net_device *dev)
1419{
1e56a4b4 1420 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 1421 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 1422
4a5e8e29 1423 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 1424}
1425
1426static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 1427 void *ptr)
1da177e4 1428{
4a5e8e29
JG		 1429 int i, csr0;
1430 u16 *buff = ptr;
1e56a4b4 1431 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 1432 struct pcnet32_access *a = &lp->a;
1433 ulong ioaddr = dev->base_addr;
4a5e8e29
JG		 1434 unsigned long flags;
1435
1436 spin_lock_irqsave(&lp->lock, flags);
1437
df27f4a6
DF		 1438 csr0 = a->read_csr(ioaddr, CSR0);
1439 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1440 pcnet32_suspend(dev, &flags, 1);
1da177e4 1441
4a5e8e29
JG		 1442 /* read address PROM */
1443 for (i = 0; i < 16; i += 2)
1444 *buff++ = inw(ioaddr + i);
1445
1446 /* read control and status registers */
1447 for (i = 0; i < 90; i++) {
1448 *buff++ = a->read_csr(ioaddr, i);
1449 }
1450
1451 *buff++ = a->read_csr(ioaddr, 112);
1452 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 1453
4a5e8e29
JG		 1454 /* read bus configuration registers */
1455 for (i = 0; i < 30; i++) {
1456 *buff++ = a->read_bcr(ioaddr, i);
1457 }
1458 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1459 for (i = 31; i < 36; i++) {
1460 *buff++ = a->read_bcr(ioaddr, i);
1461 }
1462
1463 /* read mii phy registers */
1464 if (lp->mii) {
1465 int j;
1466 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1467 if (lp->phymask & (1 << j)) {
1468 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1469 lp->a.write_bcr(ioaddr, 33,
1470 (j << 5) | i);
1471 *buff++ = lp->a.read_bcr(ioaddr, 34);
1472 }
1473 }
1474 }
1475 }
1476
df27f4a6
DF		 1477 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1478 int csr5;
1479
4a5e8e29 1480 /* clear SUSPEND (SPND) - CSR5 bit 0 */
df27f4a6
DF		 1481 csr5 = a->read_csr(ioaddr, CSR5);
1482 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
4a5e8e29
JG		 1483 }
1484
1485 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 1486}
1487
7282d491 1488static const struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 1489 .get_settings = pcnet32_get_settings,
1490 .set_settings = pcnet32_set_settings,
1491 .get_drvinfo = pcnet32_get_drvinfo,
1492 .get_msglevel = pcnet32_get_msglevel,
1493 .set_msglevel = pcnet32_set_msglevel,
1494 .nway_reset = pcnet32_nway_reset,
1495 .get_link = pcnet32_get_link,
1496 .get_ringparam = pcnet32_get_ringparam,
1497 .set_ringparam = pcnet32_set_ringparam,
4a5e8e29 1498 .get_strings = pcnet32_get_strings,
4a5e8e29
JG		 1499 .self_test = pcnet32_ethtool_test,
1500 .phys_id = pcnet32_phys_id,
1501 .get_regs_len = pcnet32_get_regs_len,
1502 .get_regs = pcnet32_get_regs,
b9f2c044 1503 .get_sset_count = pcnet32_get_sset_count,
1da177e4
LT		 1504};
1505
1506/* only probes for non-PCI devices, the rest are handled by
1507 * pci_register_driver via pcnet32_probe_pci */
1508
dcaf9769 1509static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1da177e4 1510{
4a5e8e29
JG		 1511 unsigned int *port, ioaddr;
1512
1513 /* search for PCnet32 VLB cards at known addresses */
1514 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1515 if (request_region
1516 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1517 /* check if there is really a pcnet chip on that ioaddr */
8e95a202
JP		 1518 if ((inb(ioaddr + 14) == 0x57) &&
1519 (inb(ioaddr + 15) == 0x57)) {
4a5e8e29
JG		 1520 pcnet32_probe1(ioaddr, 0, NULL);
1521 } else {
1522 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1523 }
1524 }
1525 }
1da177e4
LT		 1526}
1527
1da177e4
LT		 1528static int __devinit
1529pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1530{
4a5e8e29
JG		 1531 unsigned long ioaddr;
1532 int err;
1533
1534 err = pci_enable_device(pdev);
1535 if (err < 0) {
1536 if (pcnet32_debug & NETIF_MSG_PROBE)
1537 printk(KERN_ERR PFX
1538 "failed to enable device -- err=%d\n", err);
1539 return err;
1540 }
1541 pci_set_master(pdev);
1542
1543 ioaddr = pci_resource_start(pdev, 0);
1544 if (!ioaddr) {
1545 if (pcnet32_debug & NETIF_MSG_PROBE)
1546 printk(KERN_ERR PFX
1547 "card has no PCI IO resources, aborting\n");
1548 return -ENODEV;
1549 }
1da177e4 1550
4a5e8e29
JG		 1551 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1552 if (pcnet32_debug & NETIF_MSG_PROBE)
1553 printk(KERN_ERR PFX
1554 "architecture does not support 32bit PCI busmaster DMA\n");
1555 return -ENODEV;
1556 }
1557 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1558 NULL) {
1559 if (pcnet32_debug & NETIF_MSG_PROBE)
1560 printk(KERN_ERR PFX
1561 "io address range already allocated\n");
1562 return -EBUSY;
1563 }
1da177e4 1564
4a5e8e29
JG		 1565 err = pcnet32_probe1(ioaddr, 1, pdev);
1566 if (err < 0) {
1567 pci_disable_device(pdev);
1568 }
1569 return err;
1da177e4
LT		 1570}
1571
3bc124dd
SH		 1572static const struct net_device_ops pcnet32_netdev_ops = {
1573 .ndo_open = pcnet32_open,
1574 .ndo_stop = pcnet32_close,
1575 .ndo_start_xmit = pcnet32_start_xmit,
1576 .ndo_tx_timeout = pcnet32_tx_timeout,
1577 .ndo_get_stats = pcnet32_get_stats,
1578 .ndo_set_multicast_list = pcnet32_set_multicast_list,
1579 .ndo_do_ioctl = pcnet32_ioctl,
1580 .ndo_change_mtu = eth_change_mtu,
1581 .ndo_set_mac_address = eth_mac_addr,
1582 .ndo_validate_addr = eth_validate_addr,
1583#ifdef CONFIG_NET_POLL_CONTROLLER
1584 .ndo_poll_controller = pcnet32_poll_controller,
1585#endif
1586};
1587
1da177e4
LT		 1588/* pcnet32_probe1
1589 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1590 * pdev will be NULL when called from pcnet32_probe_vlbus.
1591 */
1592static int __devinit
1593pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1594{
4a5e8e29 1595 struct pcnet32_private *lp;
4a5e8e29
JG		 1596 int i, media;
1597 int fdx, mii, fset, dxsuflo;
1598 int chip_version;
1599 char *chipname;
1600 struct net_device *dev;
1601 struct pcnet32_access *a = NULL;
1602 u8 promaddr[6];
1603 int ret = -ENODEV;
1604
1605 /* reset the chip */
1606 pcnet32_wio_reset(ioaddr);
1607
1608 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1609 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1610 a = &pcnet32_wio;
1611 } else {
1612 pcnet32_dwio_reset(ioaddr);
8e95a202
JP		 1613 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 &&
1614 pcnet32_dwio_check(ioaddr)) {
4a5e8e29 1615 a = &pcnet32_dwio;
df4e7f72
DF		 1616 } else {
1617 if (pcnet32_debug & NETIF_MSG_PROBE)
1618 printk(KERN_ERR PFX "No access methods\n");
4a5e8e29 1619 goto err_release_region;
df4e7f72 1620 }
4a5e8e29
JG		 1621 }
1622
1623 chip_version =
1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1626 printk(KERN_INFO " PCnet chip version is %#x.\n",
1627 chip_version);
1628 if ((chip_version & 0xfff) != 0x003) {
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 printk(KERN_INFO PFX "Unsupported chip version.\n");
1631 goto err_release_region;
1632 }
1633
1634 /* initialize variables */
1635 fdx = mii = fset = dxsuflo = 0;
1636 chip_version = (chip_version >> 12) & 0xffff;
1637
1638 switch (chip_version) {
1639 case 0x2420:
1640 chipname = "PCnet/PCI 79C970"; /* PCI */
1641 break;
1642 case 0x2430:
1643 if (shared)
1644 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1645 else
1646 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1647 break;
1648 case 0x2621:
1649 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1650 fdx = 1;
1651 break;
1652 case 0x2623:
1653 chipname = "PCnet/FAST 79C971"; /* PCI */
1654 fdx = 1;
1655 mii = 1;
1656 fset = 1;
1657 break;
1658 case 0x2624:
1659 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1660 fdx = 1;
1661 mii = 1;
1662 fset = 1;
1663 break;
1664 case 0x2625:
1665 chipname = "PCnet/FAST III 79C973"; /* PCI */
1666 fdx = 1;
1667 mii = 1;
1668 break;
1669 case 0x2626:
1670 chipname = "PCnet/Home 79C978"; /* PCI */
1671 fdx = 1;
1672 /*
1673 * This is based on specs published at www.amd.com. This section
1674 * assumes that a card with a 79C978 wants to go into standard
1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1676 * and the module option homepna=1 can select this instead.
1677 */
1678 media = a->read_bcr(ioaddr, 49);
1679 media &= ~3; /* default to 10Mb ethernet */
1680 if (cards_found < MAX_UNITS && homepna[cards_found])
1681 media |= 1; /* switch to home wiring mode */
1682 if (pcnet32_debug & NETIF_MSG_PROBE)
1683 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1684 (media & 1) ? "1" : "10");
1685 a->write_bcr(ioaddr, 49, media);
1686 break;
1687 case 0x2627:
1688 chipname = "PCnet/FAST III 79C975"; /* PCI */
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 case 0x2628:
1693 chipname = "PCnet/PRO 79C976";
1694 fdx = 1;
1695 mii = 1;
1696 break;
1697 default:
1698 if (pcnet32_debug & NETIF_MSG_PROBE)
1699 printk(KERN_INFO PFX
1700 "PCnet version %#x, no PCnet32 chip.\n",
1701 chip_version);
1702 goto err_release_region;
1703 }
1704
1da177e4 1705 /*
4a5e8e29
JG		 1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1707 * starting until the packet is loaded. Strike one for reliability, lose
1708 * one for latency - although on PCI this isnt a big loss. Older chips
1709 * have FIFO's smaller than a packet, so you can't do this.
1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1711 */
4a5e8e29
JG		 1712
1713 if (fset) {
1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1715 a->write_csr(ioaddr, 80,
1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1717 dxsuflo = 1;
1718 }
1719
6ecb7667 1720 dev = alloc_etherdev(sizeof(*lp));
4a5e8e29
JG		 1721 if (!dev) {
1722 if (pcnet32_debug & NETIF_MSG_PROBE)
1723 printk(KERN_ERR PFX "Memory allocation failed.\n");
1724 ret = -ENOMEM;
1725 goto err_release_region;
1726 }
63097b3a
DF		 1727
1728 if (pdev)
1729 SET_NETDEV_DEV(dev, &pdev->dev);
4a5e8e29 1730
1da177e4 1731 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1732 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1733
1734 /* In most chips, after a chip reset, the ethernet address is read from the
1735 * station address PROM at the base address and programmed into the
1736 * "Physical Address Registers" CSR12-14.
1737 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1738 * they disagree with the CSRs. If they miscompare, and the PROM addr
1739 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1740 */
1741 for (i = 0; i < 3; i++) {
1742 unsigned int val;
1743 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1744 /* There may be endianness issues here. */
1745 dev->dev_addr[2 * i] = val & 0x0ff;
1746 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1747 }
1748
1749 /* read PROM address and compare with CSR address */
1da177e4 1750 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1751 promaddr[i] = inb(ioaddr + i);
1752
8e95a202
JP		 1753 if (memcmp(promaddr, dev->dev_addr, 6) ||
1754 !is_valid_ether_addr(dev->dev_addr)) {
4a5e8e29
JG		 1755 if (is_valid_ether_addr(promaddr)) {
1756 if (pcnet32_debug & NETIF_MSG_PROBE) {
1757 printk(" warning: CSR address invalid,\n");
1758 printk(KERN_INFO
1759 " using instead PROM address of");
1760 }
1761 memcpy(dev->dev_addr, promaddr, 6);
1762 }
1763 }
1764 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1765
1766 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1767 if (!is_valid_ether_addr(dev->perm_addr))
1768 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1769
1770 if (pcnet32_debug & NETIF_MSG_PROBE) {
e174961c 1771 printk(" %pM", dev->dev_addr);
4a5e8e29
JG		 1772
1773 /* Version 0x2623 and 0x2624 */
1774 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1775 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
ad361c98 1776 printk(KERN_INFO " tx_start_pt(0x%04x):", i);
4a5e8e29
JG		 1777 switch (i >> 10) {
1778 case 0:
ad361c98 1779 printk(KERN_CONT " 20 bytes,");
4a5e8e29
JG		 1780 break;
1781 case 1:
ad361c98 1782 printk(KERN_CONT " 64 bytes,");
4a5e8e29
JG		 1783 break;
1784 case 2:
ad361c98 1785 printk(KERN_CONT " 128 bytes,");
4a5e8e29
JG		 1786 break;
1787 case 3:
ad361c98 1788 printk(KERN_CONT "~220 bytes,");
4a5e8e29
JG		 1789 break;
1790 }
1791 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
ad361c98 1792 printk(KERN_CONT " BCR18(%x):", i & 0xffff);
4a5e8e29 1793 if (i & (1 << 5))
ad361c98 1794 printk(KERN_CONT "BurstWrEn ");
4a5e8e29 1795 if (i & (1 << 6))
ad361c98 1796 printk(KERN_CONT "BurstRdEn ");
4a5e8e29 1797 if (i & (1 << 7))
ad361c98 1798 printk(KERN_CONT "DWordIO ");
4a5e8e29 1799 if (i & (1 << 11))
ad361c98 1800 printk(KERN_CONT "NoUFlow ");
4a5e8e29 1801 i = a->read_bcr(ioaddr, 25);
ad361c98 1802 printk(KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
4a5e8e29 1803 i = a->read_bcr(ioaddr, 26);
ad361c98 1804 printk(KERN_CONT " SRAM_BND=0x%04x,", i << 8);
4a5e8e29
JG		 1805 i = a->read_bcr(ioaddr, 27);
1806 if (i & (1 << 14))
ad361c98 1807 printk(KERN_CONT "LowLatRx");
4a5e8e29
JG		 1808 }
1809 }
1810
1811 dev->base_addr = ioaddr;
1e56a4b4 1812 lp = netdev_priv(dev);
4a5e8e29 1813 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
6ecb7667
DF		 1814 if ((lp->init_block =
1815 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
4a5e8e29
JG		 1816 if (pcnet32_debug & NETIF_MSG_PROBE)
1817 printk(KERN_ERR PFX
1818 "Consistent memory allocation failed.\n");
1819 ret = -ENOMEM;
1820 goto err_free_netdev;
1821 }
4a5e8e29
JG		 1822 lp->pci_dev = pdev;
1823
bea3348e
SH		 1824 lp->dev = dev;
1825
4a5e8e29
JG		 1826 spin_lock_init(&lp->lock);
1827
4a5e8e29
JG		 1828 lp->name = chipname;
1829 lp->shared_irq = shared;
1830 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1831 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1832 lp->tx_mod_mask = lp->tx_ring_size - 1;
1833 lp->rx_mod_mask = lp->rx_ring_size - 1;
1834 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1835 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1836 lp->mii_if.full_duplex = fdx;
1837 lp->mii_if.phy_id_mask = 0x1f;
1838 lp->mii_if.reg_num_mask = 0x1f;
1839 lp->dxsuflo = dxsuflo;
1840 lp->mii = mii;
8d916266 1841 lp->chip_version = chip_version;
4a5e8e29 1842 lp->msg_enable = pcnet32_debug;
8e95a202
JP		 1843 if ((cards_found >= MAX_UNITS) ||
1844 (options[cards_found] >= sizeof(options_mapping)))
4a5e8e29
JG		 1845 lp->options = PCNET32_PORT_ASEL;
1846 else
1847 lp->options = options_mapping[options[cards_found]];
1848 lp->mii_if.dev = dev;
1849 lp->mii_if.mdio_read = mdio_read;
1850 lp->mii_if.mdio_write = mdio_write;
1851
feff348f
DF		 1852 /* napi.weight is used in both the napi and non-napi cases */
1853 lp->napi.weight = lp->rx_ring_size / 2;
1854
bea3348e 1855 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
bea3348e 1856
4a5e8e29
JG		 1857 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1858 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1859 lp->options |= PCNET32_PORT_FD;
1860
4a5e8e29
JG		 1861 lp->a = *a;
1862
1863 /* prior to register_netdev, dev->name is not yet correct */
1864 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1865 ret = -ENOMEM;
1866 goto err_free_ring;
1867 }
1868 /* detect special T1/E1 WAN card by checking for MAC address */
8e95a202
JP		 1869 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 &&
1870 dev->dev_addr[2] == 0x75)
4a5e8e29 1871 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1872
3e33545b 1873 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
6ecb7667 1874 lp->init_block->tlen_rlen =
3e33545b 1875 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 1876 for (i = 0; i < 6; i++)
6ecb7667
DF		 1877 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1878 lp->init_block->filter[0] = 0x00000000;
1879 lp->init_block->filter[1] = 0x00000000;
3e33545b
AV		 1880 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1881 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 1882
1883 /* switch pcnet32 to 32bit mode */
1884 a->write_bcr(ioaddr, 20, 2);
1885
6ecb7667
DF		 1886 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1887 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29
JG		 1888
1889 if (pdev) { /* use the IRQ provided by PCI */
1890 dev->irq = pdev->irq;
1891 if (pcnet32_debug & NETIF_MSG_PROBE)
1892 printk(" assigned IRQ %d.\n", dev->irq);
1893 } else {
1894 unsigned long irq_mask = probe_irq_on();
1895
1896 /*
1897 * To auto-IRQ we enable the initialization-done and DMA error
1898 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1899 * boards will work.
1900 */
1901 /* Trigger an initialization just for the interrupt. */
b368a3fb 1902 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
4a5e8e29
JG		 1903 mdelay(1);
1904
1905 dev->irq = probe_irq_off(irq_mask);
1906 if (!dev->irq) {
1907 if (pcnet32_debug & NETIF_MSG_PROBE)
1908 printk(", failed to detect IRQ line.\n");
1909 ret = -ENODEV;
1910 goto err_free_ring;
1911 }
1912 if (pcnet32_debug & NETIF_MSG_PROBE)
1913 printk(", probed IRQ %d.\n", dev->irq);
1914 }
1da177e4 1915
4a5e8e29
JG		 1916 /* Set the mii phy_id so that we can query the link state */
1917 if (lp->mii) {
1918 /* lp->phycount and lp->phymask are set to 0 by memset above */
1919
1920 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1921 /* scan for PHYs */
1922 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1923 unsigned short id1, id2;
1924
1925 id1 = mdio_read(dev, i, MII_PHYSID1);
1926 if (id1 == 0xffff)
1927 continue;
1928 id2 = mdio_read(dev, i, MII_PHYSID2);
1929 if (id2 == 0xffff)
1930 continue;
1931 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1932 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1933 lp->phycount++;
1934 lp->phymask |= (1 << i);
1935 lp->mii_if.phy_id = i;
1936 if (pcnet32_debug & NETIF_MSG_PROBE)
1937 printk(KERN_INFO PFX
1938 "Found PHY %04x:%04x at address %d.\n",
1939 id1, id2, i);
1940 }
1941 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1942 if (lp->phycount > 1) {
1943 lp->options |= PCNET32_PORT_MII;
1944 }
1da177e4 1945 }
4a5e8e29
JG		 1946
1947 init_timer(&lp->watchdog_timer);
1948 lp->watchdog_timer.data = (unsigned long)dev;
1949 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1950
1951 /* The PCNET32-specific entries in the device structure. */
3bc124dd 1952 dev->netdev_ops = &pcnet32_netdev_ops;
4a5e8e29 1953 dev->ethtool_ops = &pcnet32_ethtool_ops;
4a5e8e29 1954 dev->watchdog_timeo = (5 * HZ);
1da177e4 1955
4a5e8e29
JG		 1956 /* Fill in the generic fields of the device structure. */
1957 if (register_netdev(dev))
1958 goto err_free_ring;
1959
1960 if (pdev) {
1961 pci_set_drvdata(pdev, dev);
1962 } else {
1963 lp->next = pcnet32_dev;
1964 pcnet32_dev = dev;
1965 }
1966
1967 if (pcnet32_debug & NETIF_MSG_PROBE)
1968 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1969 cards_found++;
1970
1971 /* enable LED writes */
1972 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1973
4a5e8e29
JG		 1974 return 0;
1975
df4e7f72 1976err_free_ring:
4a5e8e29 1977 pcnet32_free_ring(dev);
7d2e3cb7 1978 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 1979 lp->init_block, lp->init_dma_addr);
df4e7f72 1980err_free_netdev:
4a5e8e29 1981 free_netdev(dev);
df4e7f72 1982err_release_region:
4a5e8e29
JG		 1983 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1984 return ret;
1985}
1da177e4 1986
a88c844c 1987/* if any allocation fails, caller must also call pcnet32_free_ring */
b166cfba 1988static int pcnet32_alloc_ring(struct net_device *dev, const char *name)
eabf0415 1989{
1e56a4b4 1990 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 1991
4a5e8e29
JG		 1992 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1993 sizeof(struct pcnet32_tx_head) *
1994 lp->tx_ring_size,
1995 &lp->tx_ring_dma_addr);
1996 if (lp->tx_ring == NULL) {
12fa30f3 1997 if (netif_msg_drv(lp))
ad361c98 1998 printk(KERN_ERR PFX
4a5e8e29
JG		 1999 "%s: Consistent memory allocation failed.\n",
2000 name);
2001 return -ENOMEM;
2002 }
eabf0415 2003
4a5e8e29
JG		 2004 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2005 sizeof(struct pcnet32_rx_head) *
2006 lp->rx_ring_size,
2007 &lp->rx_ring_dma_addr);
2008 if (lp->rx_ring == NULL) {
12fa30f3 2009 if (netif_msg_drv(lp))
ad361c98 2010 printk(KERN_ERR PFX
4a5e8e29
JG		 2011 "%s: Consistent memory allocation failed.\n",
2012 name);
2013 return -ENOMEM;
2014 }
eabf0415 2015
12fa30f3 2016 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2017 GFP_ATOMIC);
2018 if (!lp->tx_dma_addr) {
12fa30f3 2019 if (netif_msg_drv(lp))
ad361c98 2020 printk(KERN_ERR PFX
4a5e8e29
JG		 2021 "%s: Memory allocation failed.\n", name);
2022 return -ENOMEM;
2023 }
4a5e8e29 2024
12fa30f3 2025 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
4a5e8e29
JG		 2026 GFP_ATOMIC);
2027 if (!lp->rx_dma_addr) {
12fa30f3 2028 if (netif_msg_drv(lp))
ad361c98 2029 printk(KERN_ERR PFX
4a5e8e29
JG		 2030 "%s: Memory allocation failed.\n", name);
2031 return -ENOMEM;
2032 }
4a5e8e29 2033
12fa30f3 2034 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2035 GFP_ATOMIC);
2036 if (!lp->tx_skbuff) {
12fa30f3 2037 if (netif_msg_drv(lp))
ad361c98 2038 printk(KERN_ERR PFX
4a5e8e29
JG		 2039 "%s: Memory allocation failed.\n", name);
2040 return -ENOMEM;
2041 }
4a5e8e29 2042
12fa30f3 2043 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
4a5e8e29
JG		 2044 GFP_ATOMIC);
2045 if (!lp->rx_skbuff) {
12fa30f3 2046 if (netif_msg_drv(lp))
ad361c98 2047 printk(KERN_ERR PFX
4a5e8e29
JG		 2048 "%s: Memory allocation failed.\n", name);
2049 return -ENOMEM;
2050 }
4a5e8e29
JG		 2051
2052 return 0;
2053}
eabf0415
HWL		 2054
2055static void pcnet32_free_ring(struct net_device *dev)
2056{
1e56a4b4 2057 struct pcnet32_private *lp = netdev_priv(dev);
eabf0415 2058
4a5e8e29
JG		 2059 kfree(lp->tx_skbuff);
2060 lp->tx_skbuff = NULL;
eabf0415 2061
4a5e8e29
JG		 2062 kfree(lp->rx_skbuff);
2063 lp->rx_skbuff = NULL;
eabf0415 2064
4a5e8e29
JG		 2065 kfree(lp->tx_dma_addr);
2066 lp->tx_dma_addr = NULL;
eabf0415 2067
4a5e8e29
JG		 2068 kfree(lp->rx_dma_addr);
2069 lp->rx_dma_addr = NULL;
eabf0415 2070
4a5e8e29
JG		 2071 if (lp->tx_ring) {
2072 pci_free_consistent(lp->pci_dev,
2073 sizeof(struct pcnet32_tx_head) *
2074 lp->tx_ring_size, lp->tx_ring,
2075 lp->tx_ring_dma_addr);
2076 lp->tx_ring = NULL;
2077 }
eabf0415 2078
4a5e8e29
JG		 2079 if (lp->rx_ring) {
2080 pci_free_consistent(lp->pci_dev,
2081 sizeof(struct pcnet32_rx_head) *
2082 lp->rx_ring_size, lp->rx_ring,
2083 lp->rx_ring_dma_addr);
2084 lp->rx_ring = NULL;
2085 }
eabf0415
HWL		 2086}
2087
4a5e8e29 2088static int pcnet32_open(struct net_device *dev)
1da177e4 2089{
1e56a4b4 2090 struct pcnet32_private *lp = netdev_priv(dev);
63097b3a 2091 struct pci_dev *pdev = lp->pci_dev;
4a5e8e29
JG		 2092 unsigned long ioaddr = dev->base_addr;
2093 u16 val;
2094 int i;
2095 int rc;
2096 unsigned long flags;
2097
a0607fd3 2098 if (request_irq(dev->irq, pcnet32_interrupt,
1fb9df5d 2099 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 2100 (void *)dev)) {
2101 return -EAGAIN;
2102 }
2103
2104 spin_lock_irqsave(&lp->lock, flags);
2105 /* Check for a valid station address */
2106 if (!is_valid_ether_addr(dev->dev_addr)) {
2107 rc = -EINVAL;
2108 goto err_free_irq;
2109 }
2110
2111 /* Reset the PCNET32 */
2112 lp->a.reset(ioaddr);
2113
2114 /* switch pcnet32 to 32bit mode */
2115 lp->a.write_bcr(ioaddr, 20, 2);
2116
2117 if (netif_msg_ifup(lp))
2118 printk(KERN_DEBUG
2119 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2120 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2121 (u32) (lp->rx_ring_dma_addr),
6ecb7667 2122 (u32) (lp->init_dma_addr));
4a5e8e29
JG		 2123
2124 /* set/reset autoselect bit */
2125 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2126 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 2127 val |= 2;
4a5e8e29
JG		 2128 lp->a.write_bcr(ioaddr, 2, val);
2129
2130 /* handle full duplex setting */
2131 if (lp->mii_if.full_duplex) {
2132 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2133 if (lp->options & PCNET32_PORT_FD) {
2134 val |= 1;
2135 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2136 val |= 2;
2137 } else if (lp->options & PCNET32_PORT_ASEL) {
2138 /* workaround of xSeries250, turn on for 79C975 only */
8d916266 2139 if (lp->chip_version == 0x2627)
4a5e8e29
JG		 2140 val |= 3;
2141 }
2142 lp->a.write_bcr(ioaddr, 9, val);
2143 }
2144
2145 /* set/reset GPSI bit in test register */
2146 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2147 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2148 val |= 0x10;
2149 lp->a.write_csr(ioaddr, 124, val);
2150
2151 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
63097b3a
DF		 2152 if (pdev && pdev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2153 (pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2154 pdev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 2155 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 2156 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2157 if (netif_msg_link(lp))
2158 printk(KERN_DEBUG
2159 "%s: Setting 100Mb-Full Duplex.\n",
2160 dev->name);
2161 }
2162 }
2163 if (lp->phycount < 2) {
2164 /*
2165 * 24 Jun 2004 according AMD, in order to change the PHY,
2166 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2167 * duplex, and/or enable auto negotiation, and clear DANAS
2168 */
2169 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2170 lp->a.write_bcr(ioaddr, 32,
2171 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2172 /* disable Auto Negotiation, set 10Mpbs, HD */
2173 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2174 if (lp->options & PCNET32_PORT_FD)
2175 val |= 0x10;
2176 if (lp->options & PCNET32_PORT_100)
2177 val |= 0x08;
2178 lp->a.write_bcr(ioaddr, 32, val);
2179 } else {
2180 if (lp->options & PCNET32_PORT_ASEL) {
2181 lp->a.write_bcr(ioaddr, 32,
2182 lp->a.read_bcr(ioaddr,
2183 32) | 0x0080);
2184 /* enable auto negotiate, setup, disable fd */
2185 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2186 val |= 0x20;
2187 lp->a.write_bcr(ioaddr, 32, val);
2188 }
2189 }
2190 } else {
2191 int first_phy = -1;
2192 u16 bmcr;
2193 u32 bcr9;
2194 struct ethtool_cmd ecmd;
2195
2196 /*
2197 * There is really no good other way to handle multiple PHYs
2198 * other than turning off all automatics
2199 */
2200 val = lp->a.read_bcr(ioaddr, 2);
2201 lp->a.write_bcr(ioaddr, 2, val & ~2);
2202 val = lp->a.read_bcr(ioaddr, 32);
2203 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2204
2205 if (!(lp->options & PCNET32_PORT_ASEL)) {
2206 /* setup ecmd */
2207 ecmd.port = PORT_MII;
2208 ecmd.transceiver = XCVR_INTERNAL;
2209 ecmd.autoneg = AUTONEG_DISABLE;
2210 ecmd.speed =
2211 lp->
2212 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2213 bcr9 = lp->a.read_bcr(ioaddr, 9);
2214
2215 if (lp->options & PCNET32_PORT_FD) {
2216 ecmd.duplex = DUPLEX_FULL;
2217 bcr9 |= (1 << 0);
2218 } else {
2219 ecmd.duplex = DUPLEX_HALF;
2220 bcr9 |= ~(1 << 0);
2221 }
2222 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 2223 }
4a5e8e29
JG		 2224
2225 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2226 if (lp->phymask & (1 << i)) {
2227 /* isolate all but the first PHY */
2228 bmcr = mdio_read(dev, i, MII_BMCR);
2229 if (first_phy == -1) {
2230 first_phy = i;
2231 mdio_write(dev, i, MII_BMCR,
2232 bmcr & ~BMCR_ISOLATE);
2233 } else {
2234 mdio_write(dev, i, MII_BMCR,
2235 bmcr | BMCR_ISOLATE);
2236 }
2237 /* use mii_ethtool_sset to setup PHY */
2238 lp->mii_if.phy_id = i;
2239 ecmd.phy_address = i;
2240 if (lp->options & PCNET32_PORT_ASEL) {
2241 mii_ethtool_gset(&lp->mii_if, &ecmd);
2242 ecmd.autoneg = AUTONEG_ENABLE;
2243 }
2244 mii_ethtool_sset(&lp->mii_if, &ecmd);
2245 }
2246 }
2247 lp->mii_if.phy_id = first_phy;
2248 if (netif_msg_link(lp))
2249 printk(KERN_INFO "%s: Using PHY number %d.\n",
2250 dev->name, first_phy);
2251 }
1da177e4
LT		 2252
2253#ifdef DO_DXSUFLO
4a5e8e29 2254 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
b368a3fb 2255 val = lp->a.read_csr(ioaddr, CSR3);
4a5e8e29 2256 val |= 0x40;
b368a3fb 2257 lp->a.write_csr(ioaddr, CSR3, val);
4a5e8e29 2258 }
1da177e4
LT		 2259#endif
2260
6ecb7667 2261 lp->init_block->mode =
3e33545b 2262 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
4a5e8e29
JG		 2263 pcnet32_load_multicast(dev);
2264
2265 if (pcnet32_init_ring(dev)) {
2266 rc = -ENOMEM;
2267 goto err_free_ring;
2268 }
2269
bea3348e 2270 napi_enable(&lp->napi);
bea3348e 2271
4a5e8e29 2272 /* Re-initialize the PCNET32, and start it when done. */
6ecb7667
DF		 2273 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2274 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
4a5e8e29 2275
b368a3fb
DF		 2276 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2277 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2278
2279 netif_start_queue(dev);
2280
8d916266
DF		 2281 if (lp->chip_version >= PCNET32_79C970A) {
2282 /* Print the link status and start the watchdog */
2283 pcnet32_check_media(dev, 1);
283a21d3 2284 mod_timer(&lp->watchdog_timer, PCNET32_WATCHDOG_TIMEOUT);
8d916266 2285 }
4a5e8e29
JG		 2286
2287 i = 0;
2288 while (i++ < 100)
b368a3fb 2289 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29
JG		 2290 break;
2291 /*
2292 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2293 * reports that doing so triggers a bug in the '974.
2294 */
b368a3fb 2295 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
4a5e8e29
JG		 2296
2297 if (netif_msg_ifup(lp))
2298 printk(KERN_DEBUG
2299 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2300 dev->name, i,
6ecb7667 2301 (u32) (lp->init_dma_addr),
b368a3fb 2302 lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2303
2304 spin_unlock_irqrestore(&lp->lock, flags);
2305
2306 return 0; /* Always succeed */
2307
2308 err_free_ring:
2309 /* free any allocated skbuffs */
ac5bfe40 2310 pcnet32_purge_rx_ring(dev);
4a5e8e29 2311
4a5e8e29
JG		 2312 /*
2313 * Switch back to 16bit mode to avoid problems with dumb
2314 * DOS packet driver after a warm reboot
2315 */
2316 lp->a.write_bcr(ioaddr, 20, 4);
2317
2318 err_free_irq:
2319 spin_unlock_irqrestore(&lp->lock, flags);
2320 free_irq(dev->irq, dev);
2321 return rc;
1da177e4
LT		 2322}
2323
2324/*
2325 * The LANCE has been halted for one reason or another (busmaster memory
2326 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2327 * etc.). Modern LANCE variants always reload their ring-buffer
2328 * configuration when restarted, so we must reinitialize our ring
2329 * context before restarting. As part of this reinitialization,
2330 * find all packets still on the Tx ring and pretend that they had been
2331 * sent (in effect, drop the packets on the floor) - the higher-level
2332 * protocols will time out and retransmit. It'd be better to shuffle
2333 * these skbs to a temp list and then actually re-Tx them after
2334 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2335 */
2336
4a5e8e29 2337static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 2338{
1e56a4b4 2339 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2340 int i;
1da177e4 2341
4a5e8e29
JG		 2342 for (i = 0; i < lp->tx_ring_size; i++) {
2343 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2344 wmb(); /* Make sure adapter sees owner change */
2345 if (lp->tx_skbuff[i]) {
2346 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2347 lp->tx_skbuff[i]->len,
2348 PCI_DMA_TODEVICE);
2349 dev_kfree_skb_any(lp->tx_skbuff[i]);
2350 }
2351 lp->tx_skbuff[i] = NULL;
2352 lp->tx_dma_addr[i] = 0;
2353 }
2354}
1da177e4
LT		 2355
2356/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 2357static int pcnet32_init_ring(struct net_device *dev)
1da177e4 2358{
1e56a4b4 2359 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2360 int i;
2361
2362 lp->tx_full = 0;
2363 lp->cur_rx = lp->cur_tx = 0;
2364 lp->dirty_rx = lp->dirty_tx = 0;
2365
2366 for (i = 0; i < lp->rx_ring_size; i++) {
2367 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2368 if (rx_skbuff == NULL) {
2369 if (!
2370 (rx_skbuff = lp->rx_skbuff[i] =
232c5640 2371 dev_alloc_skb(PKT_BUF_SKB))) {
4a5e8e29 2372 /* there is not much, we can do at this point */
b368a3fb 2373 if (netif_msg_drv(lp))
4a5e8e29
JG		 2374 printk(KERN_ERR
2375 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2376 dev->name);
2377 return -1;
2378 }
232c5640 2379 skb_reserve(rx_skbuff, NET_IP_ALIGN);
4a5e8e29
JG		 2380 }
2381
2382 rmb();
2383 if (lp->rx_dma_addr[i] == 0)
2384 lp->rx_dma_addr[i] =
2385 pci_map_single(lp->pci_dev, rx_skbuff->data,
232c5640 2386 PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
3e33545b 2387 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
232c5640 2388 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
4a5e8e29 2389 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2390 lp->rx_ring[i].status = cpu_to_le16(0x8000);
4a5e8e29
JG		 2391 }
2392 /* The Tx buffer address is filled in as needed, but we do need to clear
2393 * the upper ownership bit. */
2394 for (i = 0; i < lp->tx_ring_size; i++) {
2395 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2396 wmb(); /* Make sure adapter sees owner change */
2397 lp->tx_ring[i].base = 0;
2398 lp->tx_dma_addr[i] = 0;
2399 }
2400
6ecb7667 2401 lp->init_block->tlen_rlen =
3e33545b 2402 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
4a5e8e29 2403 for (i = 0; i < 6; i++)
6ecb7667 2404 lp->init_block->phys_addr[i] = dev->dev_addr[i];
3e33545b
AV		 2405 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2406 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
4a5e8e29
JG		 2407 wmb(); /* Make sure all changes are visible */
2408 return 0;
1da177e4
LT		 2409}
2410
2411/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2412 * then flush the pending transmit operations, re-initialize the ring,
2413 * and tell the chip to initialize.
2414 */
4a5e8e29 2415static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 2416{
1e56a4b4 2417 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2418 unsigned long ioaddr = dev->base_addr;
2419 int i;
1da177e4 2420
4a5e8e29
JG		 2421 /* wait for stop */
2422 for (i = 0; i < 100; i++)
b368a3fb 2423 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
4a5e8e29 2424 break;
1da177e4 2425
4a5e8e29
JG		 2426 if (i >= 100 && netif_msg_drv(lp))
2427 printk(KERN_ERR
2428 "%s: pcnet32_restart timed out waiting for stop.\n",
2429 dev->name);
1da177e4 2430
4a5e8e29
JG		 2431 pcnet32_purge_tx_ring(dev);
2432 if (pcnet32_init_ring(dev))
2433 return;
1da177e4 2434
4a5e8e29 2435 /* ReInit Ring */
b368a3fb 2436 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
4a5e8e29
JG		 2437 i = 0;
2438 while (i++ < 1000)
b368a3fb 2439 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
4a5e8e29 2440 break;
1da177e4 2441
b368a3fb 2442 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
1da177e4
LT		 2443}
2444
4a5e8e29 2445static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 2446{
1e56a4b4 2447 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2448 unsigned long ioaddr = dev->base_addr, flags;
2449
2450 spin_lock_irqsave(&lp->lock, flags);
2451 /* Transmitter timeout, serious problems. */
2452 if (pcnet32_debug & NETIF_MSG_DRV)
2453 printk(KERN_ERR
2454 "%s: transmit timed out, status %4.4x, resetting.\n",
b368a3fb
DF		 2455 dev->name, lp->a.read_csr(ioaddr, CSR0));
2456 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
4f1e5ba0 2457 dev->stats.tx_errors++;
4a5e8e29
JG		 2458 if (netif_msg_tx_err(lp)) {
2459 int i;
2460 printk(KERN_DEBUG
2461 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2462 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2463 lp->cur_rx);
2464 for (i = 0; i < lp->rx_ring_size; i++)
2465 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2466 le32_to_cpu(lp->rx_ring[i].base),
2467 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2468 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2469 le16_to_cpu(lp->rx_ring[i].status));
2470 for (i = 0; i < lp->tx_ring_size; i++)
2471 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2472 le32_to_cpu(lp->tx_ring[i].base),
2473 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2474 le32_to_cpu(lp->tx_ring[i].misc),
2475 le16_to_cpu(lp->tx_ring[i].status));
2476 printk("\n");
2477 }
b368a3fb 2478 pcnet32_restart(dev, CSR0_NORMAL);
1da177e4 2479
4a5e8e29
JG		 2480 dev->trans_start = jiffies;
2481 netif_wake_queue(dev);
1da177e4 2482
4a5e8e29
JG		 2483 spin_unlock_irqrestore(&lp->lock, flags);
2484}
2485
61357325
SH		 2486static netdev_tx_t pcnet32_start_xmit(struct sk_buff *skb,
2487 struct net_device *dev)
1da177e4 2488{
1e56a4b4 2489 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2490 unsigned long ioaddr = dev->base_addr;
2491 u16 status;
2492 int entry;
2493 unsigned long flags;
1da177e4 2494
4a5e8e29 2495 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2496
4a5e8e29
JG		 2497 if (netif_msg_tx_queued(lp)) {
2498 printk(KERN_DEBUG
2499 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
b368a3fb 2500 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2501 }
1da177e4 2502
4a5e8e29
JG		 2503 /* Default status -- will not enable Successful-TxDone
2504 * interrupt when that option is available to us.
2505 */
2506 status = 0x8300;
1da177e4 2507
4a5e8e29 2508 /* Fill in a Tx ring entry */
1da177e4 2509
4a5e8e29
JG		 2510 /* Mask to ring buffer boundary. */
2511 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 2512
4a5e8e29
JG		 2513 /* Caution: the write order is important here, set the status
2514 * with the "ownership" bits last. */
1da177e4 2515
3e33545b 2516 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
1da177e4 2517
4a5e8e29 2518 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 2519
4a5e8e29
JG		 2520 lp->tx_skbuff[entry] = skb;
2521 lp->tx_dma_addr[entry] =
2522 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
3e33545b 2523 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
4a5e8e29 2524 wmb(); /* Make sure owner changes after all others are visible */
3e33545b 2525 lp->tx_ring[entry].status = cpu_to_le16(status);
1da177e4 2526
4a5e8e29 2527 lp->cur_tx++;
4f1e5ba0 2528 dev->stats.tx_bytes += skb->len;
1da177e4 2529
4a5e8e29 2530 /* Trigger an immediate send poll. */
b368a3fb 2531 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
1da177e4 2532
4a5e8e29 2533 dev->trans_start = jiffies;
1da177e4 2534
4a5e8e29
JG		 2535 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2536 lp->tx_full = 1;
2537 netif_stop_queue(dev);
2538 }
2539 spin_unlock_irqrestore(&lp->lock, flags);
6ed10654 2540 return NETDEV_TX_OK;
1da177e4
LT		 2541}
2542
2543/* The PCNET32 interrupt handler. */
2544static irqreturn_t
7d12e780 2545pcnet32_interrupt(int irq, void *dev_id)
1da177e4 2546{
4a5e8e29
JG		 2547 struct net_device *dev = dev_id;
2548 struct pcnet32_private *lp;
2549 unsigned long ioaddr;
5c99346a 2550 u16 csr0;
4a5e8e29 2551 int boguscnt = max_interrupt_work;
4a5e8e29 2552
4a5e8e29 2553 ioaddr = dev->base_addr;
1e56a4b4 2554 lp = netdev_priv(dev);
1da177e4 2555
4a5e8e29
JG		 2556 spin_lock(&lp->lock);
2557
3904c324
DF		 2558 csr0 = lp->a.read_csr(ioaddr, CSR0);
2559 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
4a5e8e29
JG		 2560 if (csr0 == 0xffff) {
2561 break; /* PCMCIA remove happened */
2562 }
2563 /* Acknowledge all of the current interrupt sources ASAP. */
3904c324 2564 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
4a5e8e29 2565
4a5e8e29
JG		 2566 if (netif_msg_intr(lp))
2567 printk(KERN_DEBUG
2568 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
3904c324 2569 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29 2570
4a5e8e29
JG		 2571 /* Log misc errors. */
2572 if (csr0 & 0x4000)
4f1e5ba0 2573 dev->stats.tx_errors++; /* Tx babble. */
4a5e8e29
JG		 2574 if (csr0 & 0x1000) {
2575 /*
3904c324
DF		 2576 * This happens when our receive ring is full. This
2577 * shouldn't be a problem as we will see normal rx
2578 * interrupts for the frames in the receive ring. But
2579 * there are some PCI chipsets (I can reproduce this
2580 * on SP3G with Intel saturn chipset) which have
2581 * sometimes problems and will fill up the receive
2582 * ring with error descriptors. In this situation we
2583 * don't get a rx interrupt, but a missed frame
7de745e5 2584 * interrupt sooner or later.
4a5e8e29 2585 */
4f1e5ba0 2586 dev->stats.rx_errors++; /* Missed a Rx frame. */
4a5e8e29
JG		 2587 }
2588 if (csr0 & 0x0800) {
2589 if (netif_msg_drv(lp))
2590 printk(KERN_ERR
2591 "%s: Bus master arbitration failure, status %4.4x.\n",
2592 dev->name, csr0);
2593 /* unlike for the lance, there is no restart needed */
1da177e4 2594 }
288379f0 2595 if (napi_schedule_prep(&lp->napi)) {
7de745e5
DF		 2596 u16 val;
2597 /* set interrupt masks */
2598 val = lp->a.read_csr(ioaddr, CSR3);
2599 val |= 0x5f00;
2600 lp->a.write_csr(ioaddr, CSR3, val);
ce105a08 2601
288379f0 2602 __napi_schedule(&lp->napi);
7de745e5
DF		 2603 break;
2604 }
3904c324 2605 csr0 = lp->a.read_csr(ioaddr, CSR0);
4a5e8e29
JG		 2606 }
2607
4a5e8e29
JG		 2608 if (netif_msg_intr(lp))
2609 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
b368a3fb 2610 dev->name, lp->a.read_csr(ioaddr, CSR0));
4a5e8e29
JG		 2611
2612 spin_unlock(&lp->lock);
2613
2614 return IRQ_HANDLED;
1da177e4
LT		 2615}
2616
4a5e8e29 2617static int pcnet32_close(struct net_device *dev)
1da177e4 2618{
4a5e8e29 2619 unsigned long ioaddr = dev->base_addr;
1e56a4b4 2620 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2621 unsigned long flags;
1da177e4 2622
4a5e8e29 2623 del_timer_sync(&lp->watchdog_timer);
1da177e4 2624
4a5e8e29 2625 netif_stop_queue(dev);
bea3348e 2626 napi_disable(&lp->napi);
1da177e4 2627
4a5e8e29 2628 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2629
4f1e5ba0 2630 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2631
4a5e8e29
JG		 2632 if (netif_msg_ifdown(lp))
2633 printk(KERN_DEBUG
2634 "%s: Shutting down ethercard, status was %2.2x.\n",
b368a3fb 2635 dev->name, lp->a.read_csr(ioaddr, CSR0));
1da177e4 2636
4a5e8e29 2637 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
b368a3fb 2638 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
1da177e4 2639
4a5e8e29
JG		 2640 /*
2641 * Switch back to 16bit mode to avoid problems with dumb
2642 * DOS packet driver after a warm reboot
2643 */
2644 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2645
4a5e8e29 2646 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2647
4a5e8e29 2648 free_irq(dev->irq, dev);
1da177e4 2649
4a5e8e29 2650 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2651
ac5bfe40
DF		 2652 pcnet32_purge_rx_ring(dev);
2653 pcnet32_purge_tx_ring(dev);
1da177e4 2654
4a5e8e29 2655 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2656
4a5e8e29 2657 return 0;
1da177e4
LT		 2658}
2659
4a5e8e29 2660static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2661{
1e56a4b4 2662 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2663 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2664 unsigned long flags;
2665
2666 spin_lock_irqsave(&lp->lock, flags);
4f1e5ba0 2667 dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
4a5e8e29
JG		 2668 spin_unlock_irqrestore(&lp->lock, flags);
2669
4f1e5ba0 2670 return &dev->stats;
1da177e4
LT		 2671}
2672
2673/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2674static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2675{
1e56a4b4 2676 struct pcnet32_private *lp = netdev_priv(dev);
6ecb7667 2677 volatile struct pcnet32_init_block *ib = lp->init_block;
3e33545b 2678 volatile __le16 *mcast_table = (__le16 *)ib->filter;
4a5e8e29 2679 struct dev_mc_list *dmi = dev->mc_list;
df27f4a6 2680 unsigned long ioaddr = dev->base_addr;
4a5e8e29
JG		 2681 char *addrs;
2682 int i;
2683 u32 crc;
2684
2685 /* set all multicast bits */
2686 if (dev->flags & IFF_ALLMULTI) {
3e33545b
AV		 2687 ib->filter[0] = cpu_to_le32(~0U);
2688 ib->filter[1] = cpu_to_le32(~0U);
df27f4a6
DF		 2689 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2690 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2691 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2692 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
4a5e8e29
JG		 2693 return;
2694 }
2695 /* clear the multicast filter */
2696 ib->filter[0] = 0;
2697 ib->filter[1] = 0;
2698
2699 /* Add addresses */
2700 for (i = 0; i < dev->mc_count; i++) {
2701 addrs = dmi->dmi_addr;
2702 dmi = dmi->next;
2703
2704 /* multicast address? */
2705 if (!(*addrs & 1))
2706 continue;
2707
2708 crc = ether_crc_le(6, addrs);
2709 crc = crc >> 26;
3e33545b 2710 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
4a5e8e29 2711 }
df27f4a6
DF		 2712 for (i = 0; i < 4; i++)
2713 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2714 le16_to_cpu(mcast_table[i]));
1da177e4 2715 return;
1da177e4
LT		 2716}
2717
1da177e4
LT		 2718/*
2719 * Set or clear the multicast filter for this adaptor.
2720 */
2721static void pcnet32_set_multicast_list(struct net_device *dev)
2722{
4a5e8e29 2723 unsigned long ioaddr = dev->base_addr, flags;
1e56a4b4 2724 struct pcnet32_private *lp = netdev_priv(dev);
df27f4a6 2725 int csr15, suspended;
4a5e8e29
JG		 2726
2727 spin_lock_irqsave(&lp->lock, flags);
df27f4a6
DF		 2728 suspended = pcnet32_suspend(dev, &flags, 0);
2729 csr15 = lp->a.read_csr(ioaddr, CSR15);
4a5e8e29
JG		 2730 if (dev->flags & IFF_PROMISC) {
2731 /* Log any net taps. */
2732 if (netif_msg_hw(lp))
2733 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2734 dev->name);
6ecb7667 2735 lp->init_block->mode =
3e33545b 2736 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
4a5e8e29 2737 7);
df27f4a6 2738 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
4a5e8e29 2739 } else {
6ecb7667 2740 lp->init_block->mode =
3e33545b 2741 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
df27f4a6 2742 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
4a5e8e29
JG		 2743 pcnet32_load_multicast(dev);
2744 }
2745
df27f4a6
DF		 2746 if (suspended) {
2747 int csr5;
2748 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2749 csr5 = lp->a.read_csr(ioaddr, CSR5);
2750 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
b368a3fb 2751 } else {
df27f4a6
DF		 2752 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2753 pcnet32_restart(dev, CSR0_NORMAL);
2754 netif_wake_queue(dev);
2755 }
4a5e8e29
JG		 2756
2757 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2758}
2759
2760/* This routine assumes that the lp->lock is held */
2761static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2762{
1e56a4b4 2763 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2764 unsigned long ioaddr = dev->base_addr;
2765 u16 val_out;
1da177e4 2766
4a5e8e29
JG		 2767 if (!lp->mii)
2768 return 0;
1da177e4 2769
4a5e8e29
JG		 2770 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2771 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2772
4a5e8e29 2773 return val_out;
1da177e4
LT		 2774}
2775
2776/* This routine assumes that the lp->lock is held */
2777static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2778{
1e56a4b4 2779 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2780 unsigned long ioaddr = dev->base_addr;
1da177e4 2781
4a5e8e29
JG		 2782 if (!lp->mii)
2783 return;
1da177e4 2784
4a5e8e29
JG		 2785 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2786 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2787}
2788
2789static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2790{
1e56a4b4 2791 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2792 int rc;
2793 unsigned long flags;
1da177e4 2794
4a5e8e29
JG		 2795 /* SIOC[GS]MIIxxx ioctls */
2796 if (lp->mii) {
2797 spin_lock_irqsave(&lp->lock, flags);
2798 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2799 spin_unlock_irqrestore(&lp->lock, flags);
2800 } else {
2801 rc = -EOPNOTSUPP;
2802 }
1da177e4 2803
4a5e8e29 2804 return rc;
1da177e4
LT		 2805}
2806
ac62ef04
DF		 2807static int pcnet32_check_otherphy(struct net_device *dev)
2808{
1e56a4b4 2809 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2810 struct mii_if_info mii = lp->mii_if;
2811 u16 bmcr;
2812 int i;
ac62ef04 2813
4a5e8e29
JG		 2814 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2815 if (i == lp->mii_if.phy_id)
2816 continue; /* skip active phy */
2817 if (lp->phymask & (1 << i)) {
2818 mii.phy_id = i;
2819 if (mii_link_ok(&mii)) {
2820 /* found PHY with active link */
2821 if (netif_msg_link(lp))
2822 printk(KERN_INFO
2823 "%s: Using PHY number %d.\n",
2824 dev->name, i);
2825
2826 /* isolate inactive phy */
2827 bmcr =
2828 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2829 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2830 bmcr | BMCR_ISOLATE);
2831
2832 /* de-isolate new phy */
2833 bmcr = mdio_read(dev, i, MII_BMCR);
2834 mdio_write(dev, i, MII_BMCR,
2835 bmcr & ~BMCR_ISOLATE);
2836
2837 /* set new phy address */
2838 lp->mii_if.phy_id = i;
2839 return 1;
2840 }
2841 }
ac62ef04 2842 }
4a5e8e29 2843 return 0;
ac62ef04
DF		 2844}
2845
2846/*
2847 * Show the status of the media. Similar to mii_check_media however it
2848 * correctly shows the link speed for all (tested) pcnet32 variants.
2849 * Devices with no mii just report link state without speed.
2850 *
2851 * Caller is assumed to hold and release the lp->lock.
2852 */
2853
2854static void pcnet32_check_media(struct net_device *dev, int verbose)
2855{
1e56a4b4 2856 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2857 int curr_link;
2858 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2859 u32 bcr9;
2860
ac62ef04 2861 if (lp->mii) {
4a5e8e29 2862 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2863 } else {
4a5e8e29
JG		 2864 ulong ioaddr = dev->base_addr; /* card base I/O address */
2865 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2866 }
2867 if (!curr_link) {
2868 if (prev_link || verbose) {
2869 netif_carrier_off(dev);
2870 if (netif_msg_link(lp))
2871 printk(KERN_INFO "%s: link down\n", dev->name);
2872 }
2873 if (lp->phycount > 1) {
2874 curr_link = pcnet32_check_otherphy(dev);
2875 prev_link = 0;
2876 }
2877 } else if (verbose || !prev_link) {
2878 netif_carrier_on(dev);
2879 if (lp->mii) {
2880 if (netif_msg_link(lp)) {
2881 struct ethtool_cmd ecmd;
2882 mii_ethtool_gset(&lp->mii_if, &ecmd);
2883 printk(KERN_INFO
2884 "%s: link up, %sMbps, %s-duplex\n",
2885 dev->name,
2886 (ecmd.speed == SPEED_100) ? "100" : "10",
2887 (ecmd.duplex ==
2888 DUPLEX_FULL) ? "full" : "half");
2889 }
2890 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2891 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2892 if (lp->mii_if.full_duplex)
2893 bcr9 |= (1 << 0);
2894 else
2895 bcr9 &= ~(1 << 0);
2896 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2897 }
2898 } else {
2899 if (netif_msg_link(lp))
2900 printk(KERN_INFO "%s: link up\n", dev->name);
2901 }
ac62ef04 2902 }
ac62ef04
DF		 2903}
2904
2905/*
2906 * Check for loss of link and link establishment.
2907 * Can not use mii_check_media because it does nothing if mode is forced.
2908 */
2909
1da177e4
LT		 2910static void pcnet32_watchdog(struct net_device *dev)
2911{
1e56a4b4 2912 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29 2913 unsigned long flags;
1da177e4 2914
4a5e8e29
JG		 2915 /* Print the link status if it has changed */
2916 spin_lock_irqsave(&lp->lock, flags);
2917 pcnet32_check_media(dev, 0);
2918 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2919
283a21d3 2920 mod_timer(&lp->watchdog_timer, round_jiffies(PCNET32_WATCHDOG_TIMEOUT));
1da177e4
LT		 2921}
2922
917270c6
DF		 2923static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2924{
2925 struct net_device *dev = pci_get_drvdata(pdev);
2926
2927 if (netif_running(dev)) {
2928 netif_device_detach(dev);
2929 pcnet32_close(dev);
2930 }
2931 pci_save_state(pdev);
2932 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2933 return 0;
2934}
2935
2936static int pcnet32_pm_resume(struct pci_dev *pdev)
2937{
2938 struct net_device *dev = pci_get_drvdata(pdev);
2939
2940 pci_set_power_state(pdev, PCI_D0);
2941 pci_restore_state(pdev);
2942
2943 if (netif_running(dev)) {
2944 pcnet32_open(dev);
2945 netif_device_attach(dev);
2946 }
2947 return 0;
2948}
2949
1da177e4
LT		 2950static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2951{
4a5e8e29
JG		 2952 struct net_device *dev = pci_get_drvdata(pdev);
2953
2954 if (dev) {
1e56a4b4 2955 struct pcnet32_private *lp = netdev_priv(dev);
4a5e8e29
JG		 2956
2957 unregister_netdev(dev);
2958 pcnet32_free_ring(dev);
2959 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 2960 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 2961 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 2962 free_netdev(dev);
2963 pci_disable_device(pdev);
2964 pci_set_drvdata(pdev, NULL);
2965 }
1da177e4
LT		 2966}
2967
2968static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2969 .name = DRV_NAME,
2970 .probe = pcnet32_probe_pci,
2971 .remove = __devexit_p(pcnet32_remove_one),
2972 .id_table = pcnet32_pci_tbl,
917270c6
DF		 2973 .suspend = pcnet32_pm_suspend,
2974 .resume = pcnet32_pm_resume,
1da177e4
LT		 2975};
2976
2977/* An additional parameter that may be passed in... */
2978static int debug = -1;
2979static int tx_start_pt = -1;
2980static int pcnet32_have_pci;
2981
2982module_param(debug, int, 0);
2983MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2984module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2985MODULE_PARM_DESC(max_interrupt_work,
2986 DRV_NAME " maximum events handled per interrupt");
1da177e4 2987module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2988MODULE_PARM_DESC(rx_copybreak,
2989 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2990module_param(tx_start_pt, int, 0);
2991MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2992module_param(pcnet32vlb, int, 0);
2993MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2994module_param_array(options, int, NULL, 0);
2995MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2996module_param_array(full_duplex, int, NULL, 0);
2997MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2998/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2999module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 3000MODULE_PARM_DESC(homepna,
3001 DRV_NAME
3002 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 3003
3004MODULE_AUTHOR("Thomas Bogendoerfer");
3005MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3006MODULE_LICENSE("GPL");
3007
3008#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3009
3010static int __init pcnet32_init_module(void)
3011{
4a5e8e29 3012 printk(KERN_INFO "%s", version);
1da177e4 3013
4a5e8e29 3014 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 3015
4a5e8e29
JG		 3016 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3017 tx_start = tx_start_pt;
1da177e4 3018
4a5e8e29 3019 /* find the PCI devices */
29917620 3020 if (!pci_register_driver(&pcnet32_driver))
4a5e8e29 3021 pcnet32_have_pci = 1;
1da177e4 3022
4a5e8e29
JG		 3023 /* should we find any remaining VLbus devices ? */
3024 if (pcnet32vlb)
dcaf9769 3025 pcnet32_probe_vlbus(pcnet32_portlist);
1da177e4 3026
4a5e8e29
JG		 3027 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3028 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 3029
4a5e8e29 3030 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 3031}
3032
3033static void __exit pcnet32_cleanup_module(void)
3034{
4a5e8e29
JG		 3035 struct net_device *next_dev;
3036
3037 while (pcnet32_dev) {
1e56a4b4 3038 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
4a5e8e29
JG		 3039 next_dev = lp->next;
3040 unregister_netdev(pcnet32_dev);
3041 pcnet32_free_ring(pcnet32_dev);
3042 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
7d2e3cb7 3043 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
6ecb7667 3044 lp->init_block, lp->init_dma_addr);
4a5e8e29
JG		 3045 free_netdev(pcnet32_dev);
3046 pcnet32_dev = next_dev;
3047 }
1da177e4 3048
4a5e8e29
JG		 3049 if (pcnet32_have_pci)
3050 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 3051}
3052
3053module_init(pcnet32_init_module);
3054module_exit(pcnet32_cleanup_module);
3055
3056/*
3057 * Local variables:
3058 * c-indent-level: 4
3059 * tab-width: 8
3060 * End:
3061 */
Clone of davem's net-next-2.6 tree