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[PATCH] irq-flags: drivers/net: Use the new IRQF_ constants
[net-next-2.6.git] / drivers / net / pcnet32.c
CommitLineData
1da177e4
LT		 1/* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2/*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15/**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24#define DRV_NAME "pcnet32"
ac62ef04
DF		 25#define DRV_VERSION "1.32"
26#define DRV_RELDATE "18.Mar.2006"
1da177e4
LT		 27#define PFX DRV_NAME ": "
28
4a5e8e29
JG		 29static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
1da177e4
LT		 31
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/string.h>
35#include <linux/errno.h>
36#include <linux/ioport.h>
37#include <linux/slab.h>
38#include <linux/interrupt.h>
39#include <linux/pci.h>
40#include <linux/delay.h>
41#include <linux/init.h>
42#include <linux/ethtool.h>
43#include <linux/mii.h>
44#include <linux/crc32.h>
45#include <linux/netdevice.h>
46#include <linux/etherdevice.h>
47#include <linux/skbuff.h>
48#include <linux/spinlock.h>
49#include <linux/moduleparam.h>
50#include <linux/bitops.h>
51
52#include <asm/dma.h>
53#include <asm/io.h>
54#include <asm/uaccess.h>
55#include <asm/irq.h>
56
57/*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60static struct pci_device_id pcnet32_pci_tbl[] = {
4a5e8e29
JG		 61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME,
62 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
63 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE,
64 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
65
66 /*
67 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
68 * the incorrect vendor id.
69 */
70 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE,
71 PCI_ANY_ID, PCI_ANY_ID,
72 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0},
73
74 { } /* terminate list */
1da177e4
LT		 75};
76
4a5e8e29 77MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
1da177e4
LT		 78
79static int cards_found;
80
81/*
82 * VLB I/O addresses
83 */
84static unsigned int pcnet32_portlist[] __initdata =
4a5e8e29 85 { 0x300, 0x320, 0x340, 0x360, 0 };
1da177e4
LT		 86
87static int pcnet32_debug = 0;
4a5e8e29
JG		 88static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
89static int pcnet32vlb; /* check for VLB cards ? */
1da177e4
LT		 90
91static struct net_device *pcnet32_dev;
92
93static int max_interrupt_work = 2;
94static int rx_copybreak = 200;
95
96#define PCNET32_PORT_AUI 0x00
97#define PCNET32_PORT_10BT 0x01
98#define PCNET32_PORT_GPSI 0x02
99#define PCNET32_PORT_MII 0x03
100
101#define PCNET32_PORT_PORTSEL 0x03
102#define PCNET32_PORT_ASEL 0x04
103#define PCNET32_PORT_100 0x40
104#define PCNET32_PORT_FD 0x80
105
106#define PCNET32_DMA_MASK 0xffffffff
107
108#define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
109#define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
110
111/*
112 * table to translate option values from tulip
113 * to internal options
114 */
f71e1309 115static const unsigned char options_mapping[] = {
4a5e8e29
JG		 116 PCNET32_PORT_ASEL, /* 0 Auto-select */
117 PCNET32_PORT_AUI, /* 1 BNC/AUI */
118 PCNET32_PORT_AUI, /* 2 AUI/BNC */
119 PCNET32_PORT_ASEL, /* 3 not supported */
120 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
121 PCNET32_PORT_ASEL, /* 5 not supported */
122 PCNET32_PORT_ASEL, /* 6 not supported */
123 PCNET32_PORT_ASEL, /* 7 not supported */
124 PCNET32_PORT_ASEL, /* 8 not supported */
125 PCNET32_PORT_MII, /* 9 MII 10baseT */
126 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
127 PCNET32_PORT_MII, /* 11 MII (autosel) */
128 PCNET32_PORT_10BT, /* 12 10BaseT */
129 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
130 /* 14 MII 100BaseTx-FD */
131 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
132 PCNET32_PORT_ASEL /* 15 not supported */
1da177e4
LT		 133};
134
135static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
4a5e8e29 136 "Loopback test (offline)"
1da177e4 137};
4a5e8e29 138
1da177e4
LT		 139#define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
140
ac62ef04 141#define PCNET32_NUM_REGS 136
1da177e4 142
4a5e8e29 143#define MAX_UNITS 8 /* More are supported, limit only on options */
1da177e4
LT		 144static int options[MAX_UNITS];
145static int full_duplex[MAX_UNITS];
146static int homepna[MAX_UNITS];
147
148/*
149 * Theory of Operation
150 *
151 * This driver uses the same software structure as the normal lance
152 * driver. So look for a verbose description in lance.c. The differences
153 * to the normal lance driver is the use of the 32bit mode of PCnet32
154 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
155 * 16MB limitation and we don't need bounce buffers.
156 */
157
1da177e4
LT		 158/*
159 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
160 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
161 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
162 */
163#ifndef PCNET32_LOG_TX_BUFFERS
eabf0415
HWL		 164#define PCNET32_LOG_TX_BUFFERS 4
165#define PCNET32_LOG_RX_BUFFERS 5
166#define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
167#define PCNET32_LOG_MAX_RX_BUFFERS 9
1da177e4
LT		 168#endif
169
170#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
eabf0415 171#define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
1da177e4
LT		 172
173#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
eabf0415 174#define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
1da177e4
LT		 175
176#define PKT_BUF_SZ 1544
177
178/* Offsets from base I/O address. */
179#define PCNET32_WIO_RDP 0x10
180#define PCNET32_WIO_RAP 0x12
181#define PCNET32_WIO_RESET 0x14
182#define PCNET32_WIO_BDP 0x16
183
184#define PCNET32_DWIO_RDP 0x10
185#define PCNET32_DWIO_RAP 0x14
186#define PCNET32_DWIO_RESET 0x18
187#define PCNET32_DWIO_BDP 0x1C
188
189#define PCNET32_TOTAL_SIZE 0x20
190
191/* The PCNET32 Rx and Tx ring descriptors. */
192struct pcnet32_rx_head {
0b5bf225
JG		 193 u32 base;
194 s16 buf_length;
195 s16 status;
196 u32 msg_length;
197 u32 reserved;
1da177e4
LT		 198};
199
200struct pcnet32_tx_head {
0b5bf225
JG		 201 u32 base;
202 s16 length;
203 s16 status;
204 u32 misc;
205 u32 reserved;
1da177e4
LT		 206};
207
208/* The PCNET32 32-Bit initialization block, described in databook. */
209struct pcnet32_init_block {
0b5bf225
JG		 210 u16 mode;
211 u16 tlen_rlen;
212 u8 phys_addr[6];
213 u16 reserved;
214 u32 filter[2];
4a5e8e29 215 /* Receive and transmit ring base, along with extra bits. */
0b5bf225
JG		 216 u32 rx_ring;
217 u32 tx_ring;
1da177e4
LT		 218};
219
220/* PCnet32 access functions */
221struct pcnet32_access {
4a5e8e29
JG		 222 u16 (*read_csr) (unsigned long, int);
223 void (*write_csr) (unsigned long, int, u16);
224 u16 (*read_bcr) (unsigned long, int);
225 void (*write_bcr) (unsigned long, int, u16);
226 u16 (*read_rap) (unsigned long);
227 void (*write_rap) (unsigned long, u16);
228 void (*reset) (unsigned long);
1da177e4
LT		 229};
230
231/*
76209926
HWL		 232 * The first field of pcnet32_private is read by the ethernet device
233 * so the structure should be allocated using pci_alloc_consistent().
1da177e4
LT		 234 */
235struct pcnet32_private {
4a5e8e29
JG		 236 struct pcnet32_init_block init_block;
237 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
0b5bf225
JG		 238 struct pcnet32_rx_head *rx_ring;
239 struct pcnet32_tx_head *tx_ring;
240 dma_addr_t dma_addr;/* DMA address of beginning of this
241 object, returned by pci_alloc_consistent */
242 struct pci_dev *pci_dev;
243 const char *name;
4a5e8e29 244 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0b5bf225
JG		 245 struct sk_buff **tx_skbuff;
246 struct sk_buff **rx_skbuff;
247 dma_addr_t *tx_dma_addr;
248 dma_addr_t *rx_dma_addr;
249 struct pcnet32_access a;
250 spinlock_t lock; /* Guard lock */
251 unsigned int cur_rx, cur_tx; /* The next free ring entry */
252 unsigned int rx_ring_size; /* current rx ring size */
253 unsigned int tx_ring_size; /* current tx ring size */
254 unsigned int rx_mod_mask; /* rx ring modular mask */
255 unsigned int tx_mod_mask; /* tx ring modular mask */
256 unsigned short rx_len_bits;
257 unsigned short tx_len_bits;
258 dma_addr_t rx_ring_dma_addr;
259 dma_addr_t tx_ring_dma_addr;
260 unsigned int dirty_rx, /* ring entries to be freed. */
261 dirty_tx;
262
263 struct net_device_stats stats;
264 char tx_full;
265 char phycount; /* number of phys found */
266 int options;
267 unsigned int shared_irq:1, /* shared irq possible */
268 dxsuflo:1, /* disable transmit stop on uflo */
269 mii:1; /* mii port available */
270 struct net_device *next;
271 struct mii_if_info mii_if;
272 struct timer_list watchdog_timer;
273 struct timer_list blink_timer;
274 u32 msg_enable; /* debug message level */
4a5e8e29
JG		 275
276 /* each bit indicates an available PHY */
0b5bf225 277 u32 phymask;
1da177e4
LT		 278};
279
280static void pcnet32_probe_vlbus(void);
4a5e8e29
JG		 281static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
282static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
283static int pcnet32_open(struct net_device *);
284static int pcnet32_init_ring(struct net_device *);
285static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
286static int pcnet32_rx(struct net_device *);
287static void pcnet32_tx_timeout(struct net_device *dev);
1da177e4 288static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
4a5e8e29 289static int pcnet32_close(struct net_device *);
1da177e4
LT		 290static struct net_device_stats *pcnet32_get_stats(struct net_device *);
291static void pcnet32_load_multicast(struct net_device *dev);
292static void pcnet32_set_multicast_list(struct net_device *);
4a5e8e29 293static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
1da177e4
LT		 294static void pcnet32_watchdog(struct net_device *);
295static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
4a5e8e29
JG		 296static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
297 int val);
1da177e4
LT		 298static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
299static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29
JG		 300 struct ethtool_test *eth_test, u64 * data);
301static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
1da177e4
LT		 302static int pcnet32_phys_id(struct net_device *dev, u32 data);
303static void pcnet32_led_blink_callback(struct net_device *dev);
304static int pcnet32_get_regs_len(struct net_device *dev);
305static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 306 void *ptr);
1bcd3153 307static void pcnet32_purge_tx_ring(struct net_device *dev);
a88c844c 308static int pcnet32_alloc_ring(struct net_device *dev, char *name);
eabf0415 309static void pcnet32_free_ring(struct net_device *dev);
ac62ef04 310static void pcnet32_check_media(struct net_device *dev, int verbose);
eabf0415 311
4a5e8e29 312static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
1da177e4 313{
4a5e8e29
JG		 314 outw(index, addr + PCNET32_WIO_RAP);
315 return inw(addr + PCNET32_WIO_RDP);
1da177e4
LT		 316}
317
4a5e8e29 318static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 319{
4a5e8e29
JG		 320 outw(index, addr + PCNET32_WIO_RAP);
321 outw(val, addr + PCNET32_WIO_RDP);
1da177e4
LT		 322}
323
4a5e8e29 324static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
1da177e4 325{
4a5e8e29
JG		 326 outw(index, addr + PCNET32_WIO_RAP);
327 return inw(addr + PCNET32_WIO_BDP);
1da177e4
LT		 328}
329
4a5e8e29 330static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 331{
4a5e8e29
JG		 332 outw(index, addr + PCNET32_WIO_RAP);
333 outw(val, addr + PCNET32_WIO_BDP);
1da177e4
LT		 334}
335
4a5e8e29 336static u16 pcnet32_wio_read_rap(unsigned long addr)
1da177e4 337{
4a5e8e29 338 return inw(addr + PCNET32_WIO_RAP);
1da177e4
LT		 339}
340
4a5e8e29 341static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
1da177e4 342{
4a5e8e29 343 outw(val, addr + PCNET32_WIO_RAP);
1da177e4
LT		 344}
345
4a5e8e29 346static void pcnet32_wio_reset(unsigned long addr)
1da177e4 347{
4a5e8e29 348 inw(addr + PCNET32_WIO_RESET);
1da177e4
LT		 349}
350
4a5e8e29 351static int pcnet32_wio_check(unsigned long addr)
1da177e4 352{
4a5e8e29
JG		 353 outw(88, addr + PCNET32_WIO_RAP);
354 return (inw(addr + PCNET32_WIO_RAP) == 88);
1da177e4
LT		 355}
356
357static struct pcnet32_access pcnet32_wio = {
4a5e8e29
JG		 358 .read_csr = pcnet32_wio_read_csr,
359 .write_csr = pcnet32_wio_write_csr,
360 .read_bcr = pcnet32_wio_read_bcr,
361 .write_bcr = pcnet32_wio_write_bcr,
362 .read_rap = pcnet32_wio_read_rap,
363 .write_rap = pcnet32_wio_write_rap,
364 .reset = pcnet32_wio_reset
1da177e4
LT		 365};
366
4a5e8e29 367static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
1da177e4 368{
4a5e8e29
JG		 369 outl(index, addr + PCNET32_DWIO_RAP);
370 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
1da177e4
LT		 371}
372
4a5e8e29 373static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
1da177e4 374{
4a5e8e29
JG		 375 outl(index, addr + PCNET32_DWIO_RAP);
376 outl(val, addr + PCNET32_DWIO_RDP);
1da177e4
LT		 377}
378
4a5e8e29 379static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
1da177e4 380{
4a5e8e29
JG		 381 outl(index, addr + PCNET32_DWIO_RAP);
382 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
1da177e4
LT		 383}
384
4a5e8e29 385static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
1da177e4 386{
4a5e8e29
JG		 387 outl(index, addr + PCNET32_DWIO_RAP);
388 outl(val, addr + PCNET32_DWIO_BDP);
1da177e4
LT		 389}
390
4a5e8e29 391static u16 pcnet32_dwio_read_rap(unsigned long addr)
1da177e4 392{
4a5e8e29 393 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
1da177e4
LT		 394}
395
4a5e8e29 396static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
1da177e4 397{
4a5e8e29 398 outl(val, addr + PCNET32_DWIO_RAP);
1da177e4
LT		 399}
400
4a5e8e29 401static void pcnet32_dwio_reset(unsigned long addr)
1da177e4 402{
4a5e8e29 403 inl(addr + PCNET32_DWIO_RESET);
1da177e4
LT		 404}
405
4a5e8e29 406static int pcnet32_dwio_check(unsigned long addr)
1da177e4 407{
4a5e8e29
JG		 408 outl(88, addr + PCNET32_DWIO_RAP);
409 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
1da177e4
LT		 410}
411
412static struct pcnet32_access pcnet32_dwio = {
4a5e8e29
JG		 413 .read_csr = pcnet32_dwio_read_csr,
414 .write_csr = pcnet32_dwio_write_csr,
415 .read_bcr = pcnet32_dwio_read_bcr,
416 .write_bcr = pcnet32_dwio_write_bcr,
417 .read_rap = pcnet32_dwio_read_rap,
418 .write_rap = pcnet32_dwio_write_rap,
419 .reset = pcnet32_dwio_reset
1da177e4
LT		 420};
421
422#ifdef CONFIG_NET_POLL_CONTROLLER
423static void pcnet32_poll_controller(struct net_device *dev)
424{
4a5e8e29
JG		 425 disable_irq(dev->irq);
426 pcnet32_interrupt(0, dev, NULL);
427 enable_irq(dev->irq);
1da177e4
LT		 428}
429#endif
430
1da177e4
LT		 431static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
432{
4a5e8e29
JG		 433 struct pcnet32_private *lp = dev->priv;
434 unsigned long flags;
435 int r = -EOPNOTSUPP;
1da177e4 436
4a5e8e29
JG		 437 if (lp->mii) {
438 spin_lock_irqsave(&lp->lock, flags);
439 mii_ethtool_gset(&lp->mii_if, cmd);
440 spin_unlock_irqrestore(&lp->lock, flags);
441 r = 0;
442 }
443 return r;
1da177e4
LT		 444}
445
446static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
447{
4a5e8e29
JG		 448 struct pcnet32_private *lp = dev->priv;
449 unsigned long flags;
450 int r = -EOPNOTSUPP;
1da177e4 451
4a5e8e29
JG		 452 if (lp->mii) {
453 spin_lock_irqsave(&lp->lock, flags);
454 r = mii_ethtool_sset(&lp->mii_if, cmd);
455 spin_unlock_irqrestore(&lp->lock, flags);
456 }
457 return r;
1da177e4
LT		 458}
459
4a5e8e29
JG		 460static void pcnet32_get_drvinfo(struct net_device *dev,
461 struct ethtool_drvinfo *info)
1da177e4 462{
4a5e8e29
JG		 463 struct pcnet32_private *lp = dev->priv;
464
465 strcpy(info->driver, DRV_NAME);
466 strcpy(info->version, DRV_VERSION);
467 if (lp->pci_dev)
468 strcpy(info->bus_info, pci_name(lp->pci_dev));
469 else
470 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
1da177e4
LT		 471}
472
473static u32 pcnet32_get_link(struct net_device *dev)
474{
4a5e8e29
JG		 475 struct pcnet32_private *lp = dev->priv;
476 unsigned long flags;
477 int r;
1da177e4 478
4a5e8e29
JG		 479 spin_lock_irqsave(&lp->lock, flags);
480 if (lp->mii) {
481 r = mii_link_ok(&lp->mii_if);
482 } else {
483 ulong ioaddr = dev->base_addr; /* card base I/O address */
484 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
485 }
486 spin_unlock_irqrestore(&lp->lock, flags);
487
488 return r;
1da177e4
LT		 489}
490
491static u32 pcnet32_get_msglevel(struct net_device *dev)
492{
4a5e8e29
JG		 493 struct pcnet32_private *lp = dev->priv;
494 return lp->msg_enable;
1da177e4
LT		 495}
496
497static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
498{
4a5e8e29
JG		 499 struct pcnet32_private *lp = dev->priv;
500 lp->msg_enable = value;
1da177e4
LT		 501}
502
503static int pcnet32_nway_reset(struct net_device *dev)
504{
4a5e8e29
JG		 505 struct pcnet32_private *lp = dev->priv;
506 unsigned long flags;
507 int r = -EOPNOTSUPP;
1da177e4 508
4a5e8e29
JG		 509 if (lp->mii) {
510 spin_lock_irqsave(&lp->lock, flags);
511 r = mii_nway_restart(&lp->mii_if);
512 spin_unlock_irqrestore(&lp->lock, flags);
513 }
514 return r;
1da177e4
LT		 515}
516
4a5e8e29
JG		 517static void pcnet32_get_ringparam(struct net_device *dev,
518 struct ethtool_ringparam *ering)
1da177e4 519{
4a5e8e29 520 struct pcnet32_private *lp = dev->priv;
1da177e4 521
4a5e8e29
JG		 522 ering->tx_max_pending = TX_MAX_RING_SIZE - 1;
523 ering->tx_pending = lp->tx_ring_size - 1;
524 ering->rx_max_pending = RX_MAX_RING_SIZE - 1;
525 ering->rx_pending = lp->rx_ring_size - 1;
eabf0415
HWL		 526}
527
4a5e8e29
JG		 528static int pcnet32_set_ringparam(struct net_device *dev,
529 struct ethtool_ringparam *ering)
eabf0415 530{
4a5e8e29
JG		 531 struct pcnet32_private *lp = dev->priv;
532 unsigned long flags;
533 int i;
534
535 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
536 return -EINVAL;
537
538 if (netif_running(dev))
539 pcnet32_close(dev);
540
541 spin_lock_irqsave(&lp->lock, flags);
eabf0415 542 pcnet32_free_ring(dev);
4a5e8e29
JG		 543 lp->tx_ring_size =
544 min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
545 lp->rx_ring_size =
546 min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
547
548 /* set the minimum ring size to 4, to allow the loopback test to work
549 * unchanged.
550 */
551 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
552 if (lp->tx_ring_size <= (1 << i))
553 break;
554 }
555 lp->tx_ring_size = (1 << i);
556 lp->tx_mod_mask = lp->tx_ring_size - 1;
557 lp->tx_len_bits = (i << 12);
eabf0415 558
4a5e8e29
JG		 559 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
560 if (lp->rx_ring_size <= (1 << i))
561 break;
562 }
563 lp->rx_ring_size = (1 << i);
564 lp->rx_mod_mask = lp->rx_ring_size - 1;
565 lp->rx_len_bits = (i << 4);
566
567 if (pcnet32_alloc_ring(dev, dev->name)) {
568 pcnet32_free_ring(dev);
569 spin_unlock_irqrestore(&lp->lock, flags);
570 return -ENOMEM;
571 }
eabf0415 572
4a5e8e29 573 spin_unlock_irqrestore(&lp->lock, flags);
eabf0415 574
4a5e8e29
JG		 575 if (pcnet32_debug & NETIF_MSG_DRV)
576 printk(KERN_INFO PFX
577 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
578 lp->rx_ring_size, lp->tx_ring_size);
eabf0415 579
4a5e8e29
JG		 580 if (netif_running(dev))
581 pcnet32_open(dev);
582
583 return 0;
1da177e4
LT		 584}
585
4a5e8e29
JG		 586static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
587 u8 * data)
1da177e4 588{
4a5e8e29 589 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
1da177e4
LT		 590}
591
592static int pcnet32_self_test_count(struct net_device *dev)
593{
4a5e8e29 594 return PCNET32_TEST_LEN;
1da177e4
LT		 595}
596
597static void pcnet32_ethtool_test(struct net_device *dev,
4a5e8e29 598 struct ethtool_test *test, u64 * data)
1da177e4 599{
4a5e8e29
JG		 600 struct pcnet32_private *lp = dev->priv;
601 int rc;
602
603 if (test->flags == ETH_TEST_FL_OFFLINE) {
604 rc = pcnet32_loopback_test(dev, data);
605 if (rc) {
606 if (netif_msg_hw(lp))
607 printk(KERN_DEBUG "%s: Loopback test failed.\n",
608 dev->name);
609 test->flags |= ETH_TEST_FL_FAILED;
610 } else if (netif_msg_hw(lp))
611 printk(KERN_DEBUG "%s: Loopback test passed.\n",
612 dev->name);
1da177e4 613 } else if (netif_msg_hw(lp))
4a5e8e29
JG		 614 printk(KERN_DEBUG
615 "%s: No tests to run (specify 'Offline' on ethtool).",
616 dev->name);
617} /* end pcnet32_ethtool_test */
1da177e4 618
4a5e8e29 619static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
1da177e4 620{
4a5e8e29
JG		 621 struct pcnet32_private *lp = dev->priv;
622 struct pcnet32_access *a = &lp->a; /* access to registers */
623 ulong ioaddr = dev->base_addr; /* card base I/O address */
624 struct sk_buff *skb; /* sk buff */
625 int x, i; /* counters */
626 int numbuffs = 4; /* number of TX/RX buffers and descs */
627 u16 status = 0x8300; /* TX ring status */
628 u16 teststatus; /* test of ring status */
629 int rc; /* return code */
630 int size; /* size of packets */
631 unsigned char *packet; /* source packet data */
632 static const int data_len = 60; /* length of source packets */
633 unsigned long flags;
634 unsigned long ticks;
635
636 *data1 = 1; /* status of test, default to fail */
637 rc = 1; /* default to fail */
638
639 if (netif_running(dev))
640 pcnet32_close(dev);
641
642 spin_lock_irqsave(&lp->lock, flags);
643
644 /* Reset the PCNET32 */
645 lp->a.reset(ioaddr);
646
647 /* switch pcnet32 to 32bit mode */
648 lp->a.write_bcr(ioaddr, 20, 2);
649
650 lp->init_block.mode =
651 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
652 lp->init_block.filter[0] = 0;
653 lp->init_block.filter[1] = 0;
654
655 /* purge & init rings but don't actually restart */
656 pcnet32_restart(dev, 0x0000);
657
658 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
659
660 /* Initialize Transmit buffers. */
661 size = data_len + 15;
662 for (x = 0; x < numbuffs; x++) {
663 if (!(skb = dev_alloc_skb(size))) {
664 if (netif_msg_hw(lp))
665 printk(KERN_DEBUG
666 "%s: Cannot allocate skb at line: %d!\n",
667 dev->name, __LINE__);
668 goto clean_up;
669 } else {
670 packet = skb->data;
671 skb_put(skb, size); /* create space for data */
672 lp->tx_skbuff[x] = skb;
673 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
674 lp->tx_ring[x].misc = 0;
675
676 /* put DA and SA into the skb */
677 for (i = 0; i < 6; i++)
678 *packet++ = dev->dev_addr[i];
679 for (i = 0; i < 6; i++)
680 *packet++ = dev->dev_addr[i];
681 /* type */
682 *packet++ = 0x08;
683 *packet++ = 0x06;
684 /* packet number */
685 *packet++ = x;
686 /* fill packet with data */
687 for (i = 0; i < data_len; i++)
688 *packet++ = i;
689
690 lp->tx_dma_addr[x] =
691 pci_map_single(lp->pci_dev, skb->data, skb->len,
692 PCI_DMA_TODEVICE);
693 lp->tx_ring[x].base =
694 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
695 wmb(); /* Make sure owner changes after all others are visible */
696 lp->tx_ring[x].status = le16_to_cpu(status);
697 }
1da177e4 698 }
1da177e4 699
4a5e8e29
JG		 700 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
701 x = x | 0x0002;
702 a->write_bcr(ioaddr, 32, x);
703
704 lp->a.write_csr(ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
705
706 teststatus = le16_to_cpu(0x8000);
707 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
708
709 /* Check status of descriptors */
710 for (x = 0; x < numbuffs; x++) {
711 ticks = 0;
712 rmb();
713 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
714 spin_unlock_irqrestore(&lp->lock, flags);
715 mdelay(1);
716 spin_lock_irqsave(&lp->lock, flags);
717 rmb();
718 ticks++;
719 }
720 if (ticks == 200) {
721 if (netif_msg_hw(lp))
722 printk("%s: Desc %d failed to reset!\n",
723 dev->name, x);
724 break;
725 }
726 }
727
728 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
729 wmb();
730 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
731 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
732
733 for (x = 0; x < numbuffs; x++) {
734 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
735 skb = lp->rx_skbuff[x];
736 for (i = 0; i < size; i++) {
737 printk("%02x ", *(skb->data + i));
738 }
739 printk("\n");
740 }
741 }
1da177e4 742
4a5e8e29
JG		 743 x = 0;
744 rc = 0;
745 while (x < numbuffs && !rc) {
746 skb = lp->rx_skbuff[x];
747 packet = lp->tx_skbuff[x]->data;
748 for (i = 0; i < size; i++) {
749 if (*(skb->data + i) != packet[i]) {
750 if (netif_msg_hw(lp))
751 printk(KERN_DEBUG
752 "%s: Error in compare! %2x - %02x %02x\n",
753 dev->name, i, *(skb->data + i),
754 packet[i]);
755 rc = 1;
756 break;
757 }
758 }
759 x++;
760 }
761 if (!rc) {
762 *data1 = 0;
763 }
1da177e4 764
4a5e8e29
JG		 765 clean_up:
766 pcnet32_purge_tx_ring(dev);
767 x = a->read_csr(ioaddr, 15) & 0xFFFF;
768 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
1da177e4 769
4a5e8e29
JG		 770 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
771 x = x & ~0x0002;
772 a->write_bcr(ioaddr, 32, x);
1da177e4 773
4a5e8e29
JG		 774 spin_unlock_irqrestore(&lp->lock, flags);
775
776 if (netif_running(dev)) {
777 pcnet32_open(dev);
778 } else {
779 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
780 }
781
782 return (rc);
783} /* end pcnet32_loopback_test */
1da177e4
LT		 784
785static void pcnet32_led_blink_callback(struct net_device *dev)
786{
4a5e8e29
JG		 787 struct pcnet32_private *lp = dev->priv;
788 struct pcnet32_access *a = &lp->a;
789 ulong ioaddr = dev->base_addr;
790 unsigned long flags;
791 int i;
792
793 spin_lock_irqsave(&lp->lock, flags);
794 for (i = 4; i < 8; i++) {
795 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
796 }
797 spin_unlock_irqrestore(&lp->lock, flags);
798
799 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1da177e4
LT		 800}
801
802static int pcnet32_phys_id(struct net_device *dev, u32 data)
803{
4a5e8e29
JG		 804 struct pcnet32_private *lp = dev->priv;
805 struct pcnet32_access *a = &lp->a;
806 ulong ioaddr = dev->base_addr;
807 unsigned long flags;
808 int i, regs[4];
809
810 if (!lp->blink_timer.function) {
811 init_timer(&lp->blink_timer);
812 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
813 lp->blink_timer.data = (unsigned long)dev;
814 }
815
816 /* Save the current value of the bcrs */
817 spin_lock_irqsave(&lp->lock, flags);
818 for (i = 4; i < 8; i++) {
819 regs[i - 4] = a->read_bcr(ioaddr, i);
820 }
821 spin_unlock_irqrestore(&lp->lock, flags);
822
823 mod_timer(&lp->blink_timer, jiffies);
824 set_current_state(TASK_INTERRUPTIBLE);
825
826 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
827 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
828
829 msleep_interruptible(data * 1000);
830 del_timer_sync(&lp->blink_timer);
831
832 /* Restore the original value of the bcrs */
833 spin_lock_irqsave(&lp->lock, flags);
834 for (i = 4; i < 8; i++) {
835 a->write_bcr(ioaddr, i, regs[i - 4]);
836 }
837 spin_unlock_irqrestore(&lp->lock, flags);
838
839 return 0;
1da177e4
LT		 840}
841
ac62ef04
DF		 842#define PCNET32_REGS_PER_PHY 32
843#define PCNET32_MAX_PHYS 32
1da177e4
LT		 844static int pcnet32_get_regs_len(struct net_device *dev)
845{
4a5e8e29
JG		 846 struct pcnet32_private *lp = dev->priv;
847 int j = lp->phycount * PCNET32_REGS_PER_PHY;
ac62ef04 848
4a5e8e29 849 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1da177e4
LT		 850}
851
852static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4a5e8e29 853 void *ptr)
1da177e4 854{
4a5e8e29
JG		 855 int i, csr0;
856 u16 *buff = ptr;
857 struct pcnet32_private *lp = dev->priv;
858 struct pcnet32_access *a = &lp->a;
859 ulong ioaddr = dev->base_addr;
860 int ticks;
861 unsigned long flags;
862
863 spin_lock_irqsave(&lp->lock, flags);
864
865 csr0 = a->read_csr(ioaddr, 0);
866 if (!(csr0 & 0x0004)) { /* If not stopped */
867 /* set SUSPEND (SPND) - CSR5 bit 0 */
868 a->write_csr(ioaddr, 5, 0x0001);
869
870 /* poll waiting for bit to be set */
871 ticks = 0;
872 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
873 spin_unlock_irqrestore(&lp->lock, flags);
874 mdelay(1);
875 spin_lock_irqsave(&lp->lock, flags);
876 ticks++;
877 if (ticks > 200) {
878 if (netif_msg_hw(lp))
879 printk(KERN_DEBUG
880 "%s: Error getting into suspend!\n",
881 dev->name);
882 break;
883 }
ac62ef04 884 }
1da177e4 885 }
1da177e4 886
4a5e8e29
JG		 887 /* read address PROM */
888 for (i = 0; i < 16; i += 2)
889 *buff++ = inw(ioaddr + i);
890
891 /* read control and status registers */
892 for (i = 0; i < 90; i++) {
893 *buff++ = a->read_csr(ioaddr, i);
894 }
895
896 *buff++ = a->read_csr(ioaddr, 112);
897 *buff++ = a->read_csr(ioaddr, 114);
1da177e4 898
4a5e8e29
JG		 899 /* read bus configuration registers */
900 for (i = 0; i < 30; i++) {
901 *buff++ = a->read_bcr(ioaddr, i);
902 }
903 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
904 for (i = 31; i < 36; i++) {
905 *buff++ = a->read_bcr(ioaddr, i);
906 }
907
908 /* read mii phy registers */
909 if (lp->mii) {
910 int j;
911 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
912 if (lp->phymask & (1 << j)) {
913 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
914 lp->a.write_bcr(ioaddr, 33,
915 (j << 5) | i);
916 *buff++ = lp->a.read_bcr(ioaddr, 34);
917 }
918 }
919 }
920 }
921
922 if (!(csr0 & 0x0004)) { /* If not stopped */
923 /* clear SUSPEND (SPND) - CSR5 bit 0 */
924 a->write_csr(ioaddr, 5, 0x0000);
925 }
926
927 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 928}
929
930static struct ethtool_ops pcnet32_ethtool_ops = {
4a5e8e29
JG		 931 .get_settings = pcnet32_get_settings,
932 .set_settings = pcnet32_set_settings,
933 .get_drvinfo = pcnet32_get_drvinfo,
934 .get_msglevel = pcnet32_get_msglevel,
935 .set_msglevel = pcnet32_set_msglevel,
936 .nway_reset = pcnet32_nway_reset,
937 .get_link = pcnet32_get_link,
938 .get_ringparam = pcnet32_get_ringparam,
939 .set_ringparam = pcnet32_set_ringparam,
940 .get_tx_csum = ethtool_op_get_tx_csum,
941 .get_sg = ethtool_op_get_sg,
942 .get_tso = ethtool_op_get_tso,
943 .get_strings = pcnet32_get_strings,
944 .self_test_count = pcnet32_self_test_count,
945 .self_test = pcnet32_ethtool_test,
946 .phys_id = pcnet32_phys_id,
947 .get_regs_len = pcnet32_get_regs_len,
948 .get_regs = pcnet32_get_regs,
949 .get_perm_addr = ethtool_op_get_perm_addr,
1da177e4
LT		 950};
951
952/* only probes for non-PCI devices, the rest are handled by
953 * pci_register_driver via pcnet32_probe_pci */
954
4a5e8e29 955static void __devinit pcnet32_probe_vlbus(void)
1da177e4 956{
4a5e8e29
JG		 957 unsigned int *port, ioaddr;
958
959 /* search for PCnet32 VLB cards at known addresses */
960 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
961 if (request_region
962 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
963 /* check if there is really a pcnet chip on that ioaddr */
964 if ((inb(ioaddr + 14) == 0x57)
965 && (inb(ioaddr + 15) == 0x57)) {
966 pcnet32_probe1(ioaddr, 0, NULL);
967 } else {
968 release_region(ioaddr, PCNET32_TOTAL_SIZE);
969 }
970 }
971 }
1da177e4
LT		 972}
973
1da177e4
LT		 974static int __devinit
975pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
976{
4a5e8e29
JG		 977 unsigned long ioaddr;
978 int err;
979
980 err = pci_enable_device(pdev);
981 if (err < 0) {
982 if (pcnet32_debug & NETIF_MSG_PROBE)
983 printk(KERN_ERR PFX
984 "failed to enable device -- err=%d\n", err);
985 return err;
986 }
987 pci_set_master(pdev);
988
989 ioaddr = pci_resource_start(pdev, 0);
990 if (!ioaddr) {
991 if (pcnet32_debug & NETIF_MSG_PROBE)
992 printk(KERN_ERR PFX
993 "card has no PCI IO resources, aborting\n");
994 return -ENODEV;
995 }
1da177e4 996
4a5e8e29
JG		 997 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
998 if (pcnet32_debug & NETIF_MSG_PROBE)
999 printk(KERN_ERR PFX
1000 "architecture does not support 32bit PCI busmaster DMA\n");
1001 return -ENODEV;
1002 }
1003 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1004 NULL) {
1005 if (pcnet32_debug & NETIF_MSG_PROBE)
1006 printk(KERN_ERR PFX
1007 "io address range already allocated\n");
1008 return -EBUSY;
1009 }
1da177e4 1010
4a5e8e29
JG		 1011 err = pcnet32_probe1(ioaddr, 1, pdev);
1012 if (err < 0) {
1013 pci_disable_device(pdev);
1014 }
1015 return err;
1da177e4
LT		 1016}
1017
1da177e4
LT		 1018/* pcnet32_probe1
1019 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1020 * pdev will be NULL when called from pcnet32_probe_vlbus.
1021 */
1022static int __devinit
1023pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1024{
4a5e8e29
JG		 1025 struct pcnet32_private *lp;
1026 dma_addr_t lp_dma_addr;
1027 int i, media;
1028 int fdx, mii, fset, dxsuflo;
1029 int chip_version;
1030 char *chipname;
1031 struct net_device *dev;
1032 struct pcnet32_access *a = NULL;
1033 u8 promaddr[6];
1034 int ret = -ENODEV;
1035
1036 /* reset the chip */
1037 pcnet32_wio_reset(ioaddr);
1038
1039 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1040 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1041 a = &pcnet32_wio;
1042 } else {
1043 pcnet32_dwio_reset(ioaddr);
1044 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1045 && pcnet32_dwio_check(ioaddr)) {
1046 a = &pcnet32_dwio;
1047 } else
1048 goto err_release_region;
1049 }
1050
1051 chip_version =
1052 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1053 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1054 printk(KERN_INFO " PCnet chip version is %#x.\n",
1055 chip_version);
1056 if ((chip_version & 0xfff) != 0x003) {
1057 if (pcnet32_debug & NETIF_MSG_PROBE)
1058 printk(KERN_INFO PFX "Unsupported chip version.\n");
1059 goto err_release_region;
1060 }
1061
1062 /* initialize variables */
1063 fdx = mii = fset = dxsuflo = 0;
1064 chip_version = (chip_version >> 12) & 0xffff;
1065
1066 switch (chip_version) {
1067 case 0x2420:
1068 chipname = "PCnet/PCI 79C970"; /* PCI */
1069 break;
1070 case 0x2430:
1071 if (shared)
1072 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1073 else
1074 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1075 break;
1076 case 0x2621:
1077 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1078 fdx = 1;
1079 break;
1080 case 0x2623:
1081 chipname = "PCnet/FAST 79C971"; /* PCI */
1082 fdx = 1;
1083 mii = 1;
1084 fset = 1;
1085 break;
1086 case 0x2624:
1087 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1088 fdx = 1;
1089 mii = 1;
1090 fset = 1;
1091 break;
1092 case 0x2625:
1093 chipname = "PCnet/FAST III 79C973"; /* PCI */
1094 fdx = 1;
1095 mii = 1;
1096 break;
1097 case 0x2626:
1098 chipname = "PCnet/Home 79C978"; /* PCI */
1099 fdx = 1;
1100 /*
1101 * This is based on specs published at www.amd.com. This section
1102 * assumes that a card with a 79C978 wants to go into standard
1103 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1104 * and the module option homepna=1 can select this instead.
1105 */
1106 media = a->read_bcr(ioaddr, 49);
1107 media &= ~3; /* default to 10Mb ethernet */
1108 if (cards_found < MAX_UNITS && homepna[cards_found])
1109 media |= 1; /* switch to home wiring mode */
1110 if (pcnet32_debug & NETIF_MSG_PROBE)
1111 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1112 (media & 1) ? "1" : "10");
1113 a->write_bcr(ioaddr, 49, media);
1114 break;
1115 case 0x2627:
1116 chipname = "PCnet/FAST III 79C975"; /* PCI */
1117 fdx = 1;
1118 mii = 1;
1119 break;
1120 case 0x2628:
1121 chipname = "PCnet/PRO 79C976";
1122 fdx = 1;
1123 mii = 1;
1124 break;
1125 default:
1126 if (pcnet32_debug & NETIF_MSG_PROBE)
1127 printk(KERN_INFO PFX
1128 "PCnet version %#x, no PCnet32 chip.\n",
1129 chip_version);
1130 goto err_release_region;
1131 }
1132
1da177e4 1133 /*
4a5e8e29
JG		 1134 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1135 * starting until the packet is loaded. Strike one for reliability, lose
1136 * one for latency - although on PCI this isnt a big loss. Older chips
1137 * have FIFO's smaller than a packet, so you can't do this.
1138 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1da177e4 1139 */
4a5e8e29
JG		 1140
1141 if (fset) {
1142 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1143 a->write_csr(ioaddr, 80,
1144 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1145 dxsuflo = 1;
1146 }
1147
1148 dev = alloc_etherdev(0);
1149 if (!dev) {
1150 if (pcnet32_debug & NETIF_MSG_PROBE)
1151 printk(KERN_ERR PFX "Memory allocation failed.\n");
1152 ret = -ENOMEM;
1153 goto err_release_region;
1154 }
1155 SET_NETDEV_DEV(dev, &pdev->dev);
1156
1da177e4 1157 if (pcnet32_debug & NETIF_MSG_PROBE)
4a5e8e29
JG		 1158 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1159
1160 /* In most chips, after a chip reset, the ethernet address is read from the
1161 * station address PROM at the base address and programmed into the
1162 * "Physical Address Registers" CSR12-14.
1163 * As a precautionary measure, we read the PROM values and complain if
bc0e1fc9
LV		 1164 * they disagree with the CSRs. If they miscompare, and the PROM addr
1165 * is valid, then the PROM addr is used.
4a5e8e29
JG		 1166 */
1167 for (i = 0; i < 3; i++) {
1168 unsigned int val;
1169 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1170 /* There may be endianness issues here. */
1171 dev->dev_addr[2 * i] = val & 0x0ff;
1172 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1173 }
1174
1175 /* read PROM address and compare with CSR address */
1da177e4 1176 for (i = 0; i < 6; i++)
4a5e8e29
JG		 1177 promaddr[i] = inb(ioaddr + i);
1178
1179 if (memcmp(promaddr, dev->dev_addr, 6)
1180 || !is_valid_ether_addr(dev->dev_addr)) {
1181 if (is_valid_ether_addr(promaddr)) {
1182 if (pcnet32_debug & NETIF_MSG_PROBE) {
1183 printk(" warning: CSR address invalid,\n");
1184 printk(KERN_INFO
1185 " using instead PROM address of");
1186 }
1187 memcpy(dev->dev_addr, promaddr, 6);
1188 }
1189 }
1190 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1191
1192 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1193 if (!is_valid_ether_addr(dev->perm_addr))
1194 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1195
1196 if (pcnet32_debug & NETIF_MSG_PROBE) {
1197 for (i = 0; i < 6; i++)
1198 printk(" %2.2x", dev->dev_addr[i]);
1199
1200 /* Version 0x2623 and 0x2624 */
1201 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1202 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1203 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1204 switch (i >> 10) {
1205 case 0:
1206 printk(" 20 bytes,");
1207 break;
1208 case 1:
1209 printk(" 64 bytes,");
1210 break;
1211 case 2:
1212 printk(" 128 bytes,");
1213 break;
1214 case 3:
1215 printk("~220 bytes,");
1216 break;
1217 }
1218 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1219 printk(" BCR18(%x):", i & 0xffff);
1220 if (i & (1 << 5))
1221 printk("BurstWrEn ");
1222 if (i & (1 << 6))
1223 printk("BurstRdEn ");
1224 if (i & (1 << 7))
1225 printk("DWordIO ");
1226 if (i & (1 << 11))
1227 printk("NoUFlow ");
1228 i = a->read_bcr(ioaddr, 25);
1229 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1230 i = a->read_bcr(ioaddr, 26);
1231 printk(" SRAM_BND=0x%04x,", i << 8);
1232 i = a->read_bcr(ioaddr, 27);
1233 if (i & (1 << 14))
1234 printk("LowLatRx");
1235 }
1236 }
1237
1238 dev->base_addr = ioaddr;
1239 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1240 if ((lp =
1241 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1242 if (pcnet32_debug & NETIF_MSG_PROBE)
1243 printk(KERN_ERR PFX
1244 "Consistent memory allocation failed.\n");
1245 ret = -ENOMEM;
1246 goto err_free_netdev;
1247 }
1248
1249 memset(lp, 0, sizeof(*lp));
1250 lp->dma_addr = lp_dma_addr;
1251 lp->pci_dev = pdev;
1252
1253 spin_lock_init(&lp->lock);
1254
1255 SET_MODULE_OWNER(dev);
1256 SET_NETDEV_DEV(dev, &pdev->dev);
1257 dev->priv = lp;
1258 lp->name = chipname;
1259 lp->shared_irq = shared;
1260 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1261 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1262 lp->tx_mod_mask = lp->tx_ring_size - 1;
1263 lp->rx_mod_mask = lp->rx_ring_size - 1;
1264 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1265 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1266 lp->mii_if.full_duplex = fdx;
1267 lp->mii_if.phy_id_mask = 0x1f;
1268 lp->mii_if.reg_num_mask = 0x1f;
1269 lp->dxsuflo = dxsuflo;
1270 lp->mii = mii;
1271 lp->msg_enable = pcnet32_debug;
1272 if ((cards_found >= MAX_UNITS)
1273 || (options[cards_found] > sizeof(options_mapping)))
1274 lp->options = PCNET32_PORT_ASEL;
1275 else
1276 lp->options = options_mapping[options[cards_found]];
1277 lp->mii_if.dev = dev;
1278 lp->mii_if.mdio_read = mdio_read;
1279 lp->mii_if.mdio_write = mdio_write;
1280
1281 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1282 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1283 lp->options |= PCNET32_PORT_FD;
1284
1285 if (!a) {
1286 if (pcnet32_debug & NETIF_MSG_PROBE)
1287 printk(KERN_ERR PFX "No access methods\n");
1288 ret = -ENODEV;
1289 goto err_free_consistent;
1290 }
1291 lp->a = *a;
1292
1293 /* prior to register_netdev, dev->name is not yet correct */
1294 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1295 ret = -ENOMEM;
1296 goto err_free_ring;
1297 }
1298 /* detect special T1/E1 WAN card by checking for MAC address */
1299 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1da177e4 1300 && dev->dev_addr[2] == 0x75)
4a5e8e29 1301 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1da177e4 1302
4a5e8e29
JG		 1303 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1304 lp->init_block.tlen_rlen =
1305 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1306 for (i = 0; i < 6; i++)
1307 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1308 lp->init_block.filter[0] = 0x00000000;
1309 lp->init_block.filter[1] = 0x00000000;
1310 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1311 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1312
1313 /* switch pcnet32 to 32bit mode */
1314 a->write_bcr(ioaddr, 20, 2);
1315
1316 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1317 init_block)) & 0xffff);
1318 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1319 init_block)) >> 16);
1320
1321 if (pdev) { /* use the IRQ provided by PCI */
1322 dev->irq = pdev->irq;
1323 if (pcnet32_debug & NETIF_MSG_PROBE)
1324 printk(" assigned IRQ %d.\n", dev->irq);
1325 } else {
1326 unsigned long irq_mask = probe_irq_on();
1327
1328 /*
1329 * To auto-IRQ we enable the initialization-done and DMA error
1330 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1331 * boards will work.
1332 */
1333 /* Trigger an initialization just for the interrupt. */
1334 a->write_csr(ioaddr, 0, 0x41);
1335 mdelay(1);
1336
1337 dev->irq = probe_irq_off(irq_mask);
1338 if (!dev->irq) {
1339 if (pcnet32_debug & NETIF_MSG_PROBE)
1340 printk(", failed to detect IRQ line.\n");
1341 ret = -ENODEV;
1342 goto err_free_ring;
1343 }
1344 if (pcnet32_debug & NETIF_MSG_PROBE)
1345 printk(", probed IRQ %d.\n", dev->irq);
1346 }
1da177e4 1347
4a5e8e29
JG		 1348 /* Set the mii phy_id so that we can query the link state */
1349 if (lp->mii) {
1350 /* lp->phycount and lp->phymask are set to 0 by memset above */
1351
1352 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1353 /* scan for PHYs */
1354 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1355 unsigned short id1, id2;
1356
1357 id1 = mdio_read(dev, i, MII_PHYSID1);
1358 if (id1 == 0xffff)
1359 continue;
1360 id2 = mdio_read(dev, i, MII_PHYSID2);
1361 if (id2 == 0xffff)
1362 continue;
1363 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1364 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1365 lp->phycount++;
1366 lp->phymask |= (1 << i);
1367 lp->mii_if.phy_id = i;
1368 if (pcnet32_debug & NETIF_MSG_PROBE)
1369 printk(KERN_INFO PFX
1370 "Found PHY %04x:%04x at address %d.\n",
1371 id1, id2, i);
1372 }
1373 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1374 if (lp->phycount > 1) {
1375 lp->options |= PCNET32_PORT_MII;
1376 }
1da177e4 1377 }
4a5e8e29
JG		 1378
1379 init_timer(&lp->watchdog_timer);
1380 lp->watchdog_timer.data = (unsigned long)dev;
1381 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1382
1383 /* The PCNET32-specific entries in the device structure. */
1384 dev->open = &pcnet32_open;
1385 dev->hard_start_xmit = &pcnet32_start_xmit;
1386 dev->stop = &pcnet32_close;
1387 dev->get_stats = &pcnet32_get_stats;
1388 dev->set_multicast_list = &pcnet32_set_multicast_list;
1389 dev->do_ioctl = &pcnet32_ioctl;
1390 dev->ethtool_ops = &pcnet32_ethtool_ops;
1391 dev->tx_timeout = pcnet32_tx_timeout;
1392 dev->watchdog_timeo = (5 * HZ);
1da177e4
LT		 1393
1394#ifdef CONFIG_NET_POLL_CONTROLLER
4a5e8e29 1395 dev->poll_controller = pcnet32_poll_controller;
1da177e4
LT		 1396#endif
1397
4a5e8e29
JG		 1398 /* Fill in the generic fields of the device structure. */
1399 if (register_netdev(dev))
1400 goto err_free_ring;
1401
1402 if (pdev) {
1403 pci_set_drvdata(pdev, dev);
1404 } else {
1405 lp->next = pcnet32_dev;
1406 pcnet32_dev = dev;
1407 }
1408
1409 if (pcnet32_debug & NETIF_MSG_PROBE)
1410 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1411 cards_found++;
1412
1413 /* enable LED writes */
1414 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1da177e4 1415
4a5e8e29
JG		 1416 return 0;
1417
1418 err_free_ring:
1419 pcnet32_free_ring(dev);
1420 err_free_consistent:
1421 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1422 err_free_netdev:
1423 free_netdev(dev);
1424 err_release_region:
1425 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1426 return ret;
1427}
1da177e4 1428
a88c844c
DF		 1429/* if any allocation fails, caller must also call pcnet32_free_ring */
1430static int pcnet32_alloc_ring(struct net_device *dev, char *name)
eabf0415 1431{
4a5e8e29 1432 struct pcnet32_private *lp = dev->priv;
eabf0415 1433
4a5e8e29
JG		 1434 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1435 sizeof(struct pcnet32_tx_head) *
1436 lp->tx_ring_size,
1437 &lp->tx_ring_dma_addr);
1438 if (lp->tx_ring == NULL) {
1439 if (pcnet32_debug & NETIF_MSG_DRV)
1440 printk("\n" KERN_ERR PFX
1441 "%s: Consistent memory allocation failed.\n",
1442 name);
1443 return -ENOMEM;
1444 }
eabf0415 1445
4a5e8e29
JG		 1446 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1447 sizeof(struct pcnet32_rx_head) *
1448 lp->rx_ring_size,
1449 &lp->rx_ring_dma_addr);
1450 if (lp->rx_ring == NULL) {
1451 if (pcnet32_debug & NETIF_MSG_DRV)
1452 printk("\n" KERN_ERR PFX
1453 "%s: Consistent memory allocation failed.\n",
1454 name);
1455 return -ENOMEM;
1456 }
eabf0415 1457
4a5e8e29
JG		 1458 lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size,
1459 GFP_ATOMIC);
1460 if (!lp->tx_dma_addr) {
1461 if (pcnet32_debug & NETIF_MSG_DRV)
1462 printk("\n" KERN_ERR PFX
1463 "%s: Memory allocation failed.\n", name);
1464 return -ENOMEM;
1465 }
1466 memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size);
1467
1468 lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size,
1469 GFP_ATOMIC);
1470 if (!lp->rx_dma_addr) {
1471 if (pcnet32_debug & NETIF_MSG_DRV)
1472 printk("\n" KERN_ERR PFX
1473 "%s: Memory allocation failed.\n", name);
1474 return -ENOMEM;
1475 }
1476 memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size);
1477
1478 lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size,
1479 GFP_ATOMIC);
1480 if (!lp->tx_skbuff) {
1481 if (pcnet32_debug & NETIF_MSG_DRV)
1482 printk("\n" KERN_ERR PFX
1483 "%s: Memory allocation failed.\n", name);
1484 return -ENOMEM;
1485 }
1486 memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size);
1487
1488 lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size,
1489 GFP_ATOMIC);
1490 if (!lp->rx_skbuff) {
1491 if (pcnet32_debug & NETIF_MSG_DRV)
1492 printk("\n" KERN_ERR PFX
1493 "%s: Memory allocation failed.\n", name);
1494 return -ENOMEM;
1495 }
1496 memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size);
1497
1498 return 0;
1499}
eabf0415
HWL		 1500
1501static void pcnet32_free_ring(struct net_device *dev)
1502{
4a5e8e29 1503 struct pcnet32_private *lp = dev->priv;
eabf0415 1504
4a5e8e29
JG		 1505 kfree(lp->tx_skbuff);
1506 lp->tx_skbuff = NULL;
eabf0415 1507
4a5e8e29
JG		 1508 kfree(lp->rx_skbuff);
1509 lp->rx_skbuff = NULL;
eabf0415 1510
4a5e8e29
JG		 1511 kfree(lp->tx_dma_addr);
1512 lp->tx_dma_addr = NULL;
eabf0415 1513
4a5e8e29
JG		 1514 kfree(lp->rx_dma_addr);
1515 lp->rx_dma_addr = NULL;
eabf0415 1516
4a5e8e29
JG		 1517 if (lp->tx_ring) {
1518 pci_free_consistent(lp->pci_dev,
1519 sizeof(struct pcnet32_tx_head) *
1520 lp->tx_ring_size, lp->tx_ring,
1521 lp->tx_ring_dma_addr);
1522 lp->tx_ring = NULL;
1523 }
eabf0415 1524
4a5e8e29
JG		 1525 if (lp->rx_ring) {
1526 pci_free_consistent(lp->pci_dev,
1527 sizeof(struct pcnet32_rx_head) *
1528 lp->rx_ring_size, lp->rx_ring,
1529 lp->rx_ring_dma_addr);
1530 lp->rx_ring = NULL;
1531 }
eabf0415
HWL		 1532}
1533
4a5e8e29 1534static int pcnet32_open(struct net_device *dev)
1da177e4 1535{
4a5e8e29
JG		 1536 struct pcnet32_private *lp = dev->priv;
1537 unsigned long ioaddr = dev->base_addr;
1538 u16 val;
1539 int i;
1540 int rc;
1541 unsigned long flags;
1542
1543 if (request_irq(dev->irq, &pcnet32_interrupt,
1fb9df5d 1544 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
4a5e8e29
JG		 1545 (void *)dev)) {
1546 return -EAGAIN;
1547 }
1548
1549 spin_lock_irqsave(&lp->lock, flags);
1550 /* Check for a valid station address */
1551 if (!is_valid_ether_addr(dev->dev_addr)) {
1552 rc = -EINVAL;
1553 goto err_free_irq;
1554 }
1555
1556 /* Reset the PCNET32 */
1557 lp->a.reset(ioaddr);
1558
1559 /* switch pcnet32 to 32bit mode */
1560 lp->a.write_bcr(ioaddr, 20, 2);
1561
1562 if (netif_msg_ifup(lp))
1563 printk(KERN_DEBUG
1564 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1565 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
1566 (u32) (lp->rx_ring_dma_addr),
1567 (u32) (lp->dma_addr +
1568 offsetof(struct pcnet32_private, init_block)));
1569
1570 /* set/reset autoselect bit */
1571 val = lp->a.read_bcr(ioaddr, 2) & ~2;
1572 if (lp->options & PCNET32_PORT_ASEL)
1da177e4 1573 val |= 2;
4a5e8e29
JG		 1574 lp->a.write_bcr(ioaddr, 2, val);
1575
1576 /* handle full duplex setting */
1577 if (lp->mii_if.full_duplex) {
1578 val = lp->a.read_bcr(ioaddr, 9) & ~3;
1579 if (lp->options & PCNET32_PORT_FD) {
1580 val |= 1;
1581 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1582 val |= 2;
1583 } else if (lp->options & PCNET32_PORT_ASEL) {
1584 /* workaround of xSeries250, turn on for 79C975 only */
1585 i = ((lp->a.read_csr(ioaddr, 88) |
1586 (lp->a.
1587 read_csr(ioaddr, 89) << 16)) >> 12) & 0xffff;
1588 if (i == 0x2627)
1589 val |= 3;
1590 }
1591 lp->a.write_bcr(ioaddr, 9, val);
1592 }
1593
1594 /* set/reset GPSI bit in test register */
1595 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
1596 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1597 val |= 0x10;
1598 lp->a.write_csr(ioaddr, 124, val);
1599
1600 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1601 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2964bbd7
DF		 1602 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1603 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
ac62ef04 1604 if (lp->options & PCNET32_PORT_ASEL) {
4a5e8e29
JG		 1605 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1606 if (netif_msg_link(lp))
1607 printk(KERN_DEBUG
1608 "%s: Setting 100Mb-Full Duplex.\n",
1609 dev->name);
1610 }
1611 }
1612 if (lp->phycount < 2) {
1613 /*
1614 * 24 Jun 2004 according AMD, in order to change the PHY,
1615 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1616 * duplex, and/or enable auto negotiation, and clear DANAS
1617 */
1618 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1619 lp->a.write_bcr(ioaddr, 32,
1620 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1621 /* disable Auto Negotiation, set 10Mpbs, HD */
1622 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1623 if (lp->options & PCNET32_PORT_FD)
1624 val |= 0x10;
1625 if (lp->options & PCNET32_PORT_100)
1626 val |= 0x08;
1627 lp->a.write_bcr(ioaddr, 32, val);
1628 } else {
1629 if (lp->options & PCNET32_PORT_ASEL) {
1630 lp->a.write_bcr(ioaddr, 32,
1631 lp->a.read_bcr(ioaddr,
1632 32) | 0x0080);
1633 /* enable auto negotiate, setup, disable fd */
1634 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1635 val |= 0x20;
1636 lp->a.write_bcr(ioaddr, 32, val);
1637 }
1638 }
1639 } else {
1640 int first_phy = -1;
1641 u16 bmcr;
1642 u32 bcr9;
1643 struct ethtool_cmd ecmd;
1644
1645 /*
1646 * There is really no good other way to handle multiple PHYs
1647 * other than turning off all automatics
1648 */
1649 val = lp->a.read_bcr(ioaddr, 2);
1650 lp->a.write_bcr(ioaddr, 2, val & ~2);
1651 val = lp->a.read_bcr(ioaddr, 32);
1652 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
1653
1654 if (!(lp->options & PCNET32_PORT_ASEL)) {
1655 /* setup ecmd */
1656 ecmd.port = PORT_MII;
1657 ecmd.transceiver = XCVR_INTERNAL;
1658 ecmd.autoneg = AUTONEG_DISABLE;
1659 ecmd.speed =
1660 lp->
1661 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1662 bcr9 = lp->a.read_bcr(ioaddr, 9);
1663
1664 if (lp->options & PCNET32_PORT_FD) {
1665 ecmd.duplex = DUPLEX_FULL;
1666 bcr9 |= (1 << 0);
1667 } else {
1668 ecmd.duplex = DUPLEX_HALF;
1669 bcr9 |= ~(1 << 0);
1670 }
1671 lp->a.write_bcr(ioaddr, 9, bcr9);
ac62ef04 1672 }
4a5e8e29
JG		 1673
1674 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1675 if (lp->phymask & (1 << i)) {
1676 /* isolate all but the first PHY */
1677 bmcr = mdio_read(dev, i, MII_BMCR);
1678 if (first_phy == -1) {
1679 first_phy = i;
1680 mdio_write(dev, i, MII_BMCR,
1681 bmcr & ~BMCR_ISOLATE);
1682 } else {
1683 mdio_write(dev, i, MII_BMCR,
1684 bmcr | BMCR_ISOLATE);
1685 }
1686 /* use mii_ethtool_sset to setup PHY */
1687 lp->mii_if.phy_id = i;
1688 ecmd.phy_address = i;
1689 if (lp->options & PCNET32_PORT_ASEL) {
1690 mii_ethtool_gset(&lp->mii_if, &ecmd);
1691 ecmd.autoneg = AUTONEG_ENABLE;
1692 }
1693 mii_ethtool_sset(&lp->mii_if, &ecmd);
1694 }
1695 }
1696 lp->mii_if.phy_id = first_phy;
1697 if (netif_msg_link(lp))
1698 printk(KERN_INFO "%s: Using PHY number %d.\n",
1699 dev->name, first_phy);
1700 }
1da177e4
LT		 1701
1702#ifdef DO_DXSUFLO
4a5e8e29
JG		 1703 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1704 val = lp->a.read_csr(ioaddr, 3);
1705 val |= 0x40;
1706 lp->a.write_csr(ioaddr, 3, val);
1707 }
1da177e4
LT		 1708#endif
1709
4a5e8e29
JG		 1710 lp->init_block.mode =
1711 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1712 pcnet32_load_multicast(dev);
1713
1714 if (pcnet32_init_ring(dev)) {
1715 rc = -ENOMEM;
1716 goto err_free_ring;
1717 }
1718
1719 /* Re-initialize the PCNET32, and start it when done. */
1720 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
1721 offsetof(struct pcnet32_private,
1722 init_block)) & 0xffff);
1723 lp->a.write_csr(ioaddr, 2,
1724 (lp->dma_addr +
1725 offsetof(struct pcnet32_private, init_block)) >> 16);
1726
1727 lp->a.write_csr(ioaddr, 4, 0x0915);
1728 lp->a.write_csr(ioaddr, 0, 0x0001);
1729
1730 netif_start_queue(dev);
1731
1732 /* Print the link status and start the watchdog */
1733 pcnet32_check_media(dev, 1);
1734 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1735
1736 i = 0;
1737 while (i++ < 100)
1738 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
1739 break;
1740 /*
1741 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1742 * reports that doing so triggers a bug in the '974.
1743 */
1744 lp->a.write_csr(ioaddr, 0, 0x0042);
1745
1746 if (netif_msg_ifup(lp))
1747 printk(KERN_DEBUG
1748 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1749 dev->name, i,
1750 (u32) (lp->dma_addr +
1751 offsetof(struct pcnet32_private, init_block)),
1752 lp->a.read_csr(ioaddr, 0));
1753
1754 spin_unlock_irqrestore(&lp->lock, flags);
1755
1756 return 0; /* Always succeed */
1757
1758 err_free_ring:
1759 /* free any allocated skbuffs */
1760 for (i = 0; i < lp->rx_ring_size; i++) {
1761 lp->rx_ring[i].status = 0;
1762 if (lp->rx_skbuff[i]) {
1763 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
1764 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
1765 dev_kfree_skb(lp->rx_skbuff[i]);
1766 }
1767 lp->rx_skbuff[i] = NULL;
1768 lp->rx_dma_addr[i] = 0;
1769 }
1770
4a5e8e29
JG		 1771 /*
1772 * Switch back to 16bit mode to avoid problems with dumb
1773 * DOS packet driver after a warm reboot
1774 */
1775 lp->a.write_bcr(ioaddr, 20, 4);
1776
1777 err_free_irq:
1778 spin_unlock_irqrestore(&lp->lock, flags);
1779 free_irq(dev->irq, dev);
1780 return rc;
1da177e4
LT		 1781}
1782
1783/*
1784 * The LANCE has been halted for one reason or another (busmaster memory
1785 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1786 * etc.). Modern LANCE variants always reload their ring-buffer
1787 * configuration when restarted, so we must reinitialize our ring
1788 * context before restarting. As part of this reinitialization,
1789 * find all packets still on the Tx ring and pretend that they had been
1790 * sent (in effect, drop the packets on the floor) - the higher-level
1791 * protocols will time out and retransmit. It'd be better to shuffle
1792 * these skbs to a temp list and then actually re-Tx them after
1793 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1794 */
1795
4a5e8e29 1796static void pcnet32_purge_tx_ring(struct net_device *dev)
1da177e4 1797{
4a5e8e29
JG		 1798 struct pcnet32_private *lp = dev->priv;
1799 int i;
1da177e4 1800
4a5e8e29
JG		 1801 for (i = 0; i < lp->tx_ring_size; i++) {
1802 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1803 wmb(); /* Make sure adapter sees owner change */
1804 if (lp->tx_skbuff[i]) {
1805 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1806 lp->tx_skbuff[i]->len,
1807 PCI_DMA_TODEVICE);
1808 dev_kfree_skb_any(lp->tx_skbuff[i]);
1809 }
1810 lp->tx_skbuff[i] = NULL;
1811 lp->tx_dma_addr[i] = 0;
1812 }
1813}
1da177e4
LT		 1814
1815/* Initialize the PCNET32 Rx and Tx rings. */
4a5e8e29 1816static int pcnet32_init_ring(struct net_device *dev)
1da177e4 1817{
4a5e8e29
JG		 1818 struct pcnet32_private *lp = dev->priv;
1819 int i;
1820
1821 lp->tx_full = 0;
1822 lp->cur_rx = lp->cur_tx = 0;
1823 lp->dirty_rx = lp->dirty_tx = 0;
1824
1825 for (i = 0; i < lp->rx_ring_size; i++) {
1826 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1827 if (rx_skbuff == NULL) {
1828 if (!
1829 (rx_skbuff = lp->rx_skbuff[i] =
1830 dev_alloc_skb(PKT_BUF_SZ))) {
1831 /* there is not much, we can do at this point */
1832 if (pcnet32_debug & NETIF_MSG_DRV)
1833 printk(KERN_ERR
1834 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1835 dev->name);
1836 return -1;
1837 }
1838 skb_reserve(rx_skbuff, 2);
1839 }
1840
1841 rmb();
1842 if (lp->rx_dma_addr[i] == 0)
1843 lp->rx_dma_addr[i] =
1844 pci_map_single(lp->pci_dev, rx_skbuff->data,
1845 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
1846 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
1847 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1848 wmb(); /* Make sure owner changes after all others are visible */
1849 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1850 }
1851 /* The Tx buffer address is filled in as needed, but we do need to clear
1852 * the upper ownership bit. */
1853 for (i = 0; i < lp->tx_ring_size; i++) {
1854 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1855 wmb(); /* Make sure adapter sees owner change */
1856 lp->tx_ring[i].base = 0;
1857 lp->tx_dma_addr[i] = 0;
1858 }
1859
1860 lp->init_block.tlen_rlen =
1861 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1862 for (i = 0; i < 6; i++)
1863 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1864 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1865 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1866 wmb(); /* Make sure all changes are visible */
1867 return 0;
1da177e4
LT		 1868}
1869
1870/* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1871 * then flush the pending transmit operations, re-initialize the ring,
1872 * and tell the chip to initialize.
1873 */
4a5e8e29 1874static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1da177e4 1875{
4a5e8e29
JG		 1876 struct pcnet32_private *lp = dev->priv;
1877 unsigned long ioaddr = dev->base_addr;
1878 int i;
1da177e4 1879
4a5e8e29
JG		 1880 /* wait for stop */
1881 for (i = 0; i < 100; i++)
1882 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
1883 break;
1da177e4 1884
4a5e8e29
JG		 1885 if (i >= 100 && netif_msg_drv(lp))
1886 printk(KERN_ERR
1887 "%s: pcnet32_restart timed out waiting for stop.\n",
1888 dev->name);
1da177e4 1889
4a5e8e29
JG		 1890 pcnet32_purge_tx_ring(dev);
1891 if (pcnet32_init_ring(dev))
1892 return;
1da177e4 1893
4a5e8e29
JG		 1894 /* ReInit Ring */
1895 lp->a.write_csr(ioaddr, 0, 1);
1896 i = 0;
1897 while (i++ < 1000)
1898 if (lp->a.read_csr(ioaddr, 0) & 0x0100)
1899 break;
1da177e4 1900
4a5e8e29 1901 lp->a.write_csr(ioaddr, 0, csr0_bits);
1da177e4
LT		 1902}
1903
4a5e8e29 1904static void pcnet32_tx_timeout(struct net_device *dev)
1da177e4 1905{
4a5e8e29
JG		 1906 struct pcnet32_private *lp = dev->priv;
1907 unsigned long ioaddr = dev->base_addr, flags;
1908
1909 spin_lock_irqsave(&lp->lock, flags);
1910 /* Transmitter timeout, serious problems. */
1911 if (pcnet32_debug & NETIF_MSG_DRV)
1912 printk(KERN_ERR
1913 "%s: transmit timed out, status %4.4x, resetting.\n",
1914 dev->name, lp->a.read_csr(ioaddr, 0));
1915 lp->a.write_csr(ioaddr, 0, 0x0004);
1916 lp->stats.tx_errors++;
1917 if (netif_msg_tx_err(lp)) {
1918 int i;
1919 printk(KERN_DEBUG
1920 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1921 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1922 lp->cur_rx);
1923 for (i = 0; i < lp->rx_ring_size; i++)
1924 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1925 le32_to_cpu(lp->rx_ring[i].base),
1926 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
1927 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
1928 le16_to_cpu(lp->rx_ring[i].status));
1929 for (i = 0; i < lp->tx_ring_size; i++)
1930 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1931 le32_to_cpu(lp->tx_ring[i].base),
1932 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
1933 le32_to_cpu(lp->tx_ring[i].misc),
1934 le16_to_cpu(lp->tx_ring[i].status));
1935 printk("\n");
1936 }
1937 pcnet32_restart(dev, 0x0042);
1da177e4 1938
4a5e8e29
JG		 1939 dev->trans_start = jiffies;
1940 netif_wake_queue(dev);
1da177e4 1941
4a5e8e29
JG		 1942 spin_unlock_irqrestore(&lp->lock, flags);
1943}
1944
1945static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 1946{
4a5e8e29
JG		 1947 struct pcnet32_private *lp = dev->priv;
1948 unsigned long ioaddr = dev->base_addr;
1949 u16 status;
1950 int entry;
1951 unsigned long flags;
1da177e4 1952
4a5e8e29 1953 spin_lock_irqsave(&lp->lock, flags);
1da177e4 1954
4a5e8e29
JG		 1955 if (netif_msg_tx_queued(lp)) {
1956 printk(KERN_DEBUG
1957 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1958 dev->name, lp->a.read_csr(ioaddr, 0));
1959 }
1da177e4 1960
4a5e8e29
JG		 1961 /* Default status -- will not enable Successful-TxDone
1962 * interrupt when that option is available to us.
1963 */
1964 status = 0x8300;
1da177e4 1965
4a5e8e29 1966 /* Fill in a Tx ring entry */
1da177e4 1967
4a5e8e29
JG		 1968 /* Mask to ring buffer boundary. */
1969 entry = lp->cur_tx & lp->tx_mod_mask;
1da177e4 1970
4a5e8e29
JG		 1971 /* Caution: the write order is important here, set the status
1972 * with the "ownership" bits last. */
1da177e4 1973
4a5e8e29 1974 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1da177e4 1975
4a5e8e29 1976 lp->tx_ring[entry].misc = 0x00000000;
1da177e4 1977
4a5e8e29
JG		 1978 lp->tx_skbuff[entry] = skb;
1979 lp->tx_dma_addr[entry] =
1980 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1981 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
1982 wmb(); /* Make sure owner changes after all others are visible */
1983 lp->tx_ring[entry].status = le16_to_cpu(status);
1da177e4 1984
4a5e8e29
JG		 1985 lp->cur_tx++;
1986 lp->stats.tx_bytes += skb->len;
1da177e4 1987
4a5e8e29
JG		 1988 /* Trigger an immediate send poll. */
1989 lp->a.write_csr(ioaddr, 0, 0x0048);
1da177e4 1990
4a5e8e29 1991 dev->trans_start = jiffies;
1da177e4 1992
4a5e8e29
JG		 1993 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
1994 lp->tx_full = 1;
1995 netif_stop_queue(dev);
1996 }
1997 spin_unlock_irqrestore(&lp->lock, flags);
1998 return 0;
1da177e4
LT		 1999}
2000
2001/* The PCNET32 interrupt handler. */
2002static irqreturn_t
4a5e8e29 2003pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1da177e4 2004{
4a5e8e29
JG		 2005 struct net_device *dev = dev_id;
2006 struct pcnet32_private *lp;
2007 unsigned long ioaddr;
2008 u16 csr0, rap;
2009 int boguscnt = max_interrupt_work;
2010 int must_restart;
2011
2012 if (!dev) {
2013 if (pcnet32_debug & NETIF_MSG_INTR)
2014 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2015 __FUNCTION__, irq);
2016 return IRQ_NONE;
1da177e4 2017 }
1da177e4 2018
4a5e8e29
JG		 2019 ioaddr = dev->base_addr;
2020 lp = dev->priv;
1da177e4 2021
4a5e8e29
JG		 2022 spin_lock(&lp->lock);
2023
2024 rap = lp->a.read_rap(ioaddr);
2025 while ((csr0 = lp->a.read_csr(ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2026 if (csr0 == 0xffff) {
2027 break; /* PCMCIA remove happened */
2028 }
2029 /* Acknowledge all of the current interrupt sources ASAP. */
2030 lp->a.write_csr(ioaddr, 0, csr0 & ~0x004f);
2031
2032 must_restart = 0;
2033
2034 if (netif_msg_intr(lp))
2035 printk(KERN_DEBUG
2036 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2037 dev->name, csr0, lp->a.read_csr(ioaddr, 0));
2038
2039 if (csr0 & 0x0400) /* Rx interrupt */
2040 pcnet32_rx(dev);
2041
2042 if (csr0 & 0x0200) { /* Tx-done interrupt */
2043 unsigned int dirty_tx = lp->dirty_tx;
2044 int delta;
2045
2046 while (dirty_tx != lp->cur_tx) {
2047 int entry = dirty_tx & lp->tx_mod_mask;
2048 int status =
2049 (short)le16_to_cpu(lp->tx_ring[entry].
2050 status);
2051
2052 if (status < 0)
2053 break; /* It still hasn't been Txed */
2054
2055 lp->tx_ring[entry].base = 0;
2056
2057 if (status & 0x4000) {
2058 /* There was an major error, log it. */
2059 int err_status =
2060 le32_to_cpu(lp->tx_ring[entry].
2061 misc);
2062 lp->stats.tx_errors++;
2063 if (netif_msg_tx_err(lp))
2064 printk(KERN_ERR
2065 "%s: Tx error status=%04x err_status=%08x\n",
2066 dev->name, status,
2067 err_status);
2068 if (err_status & 0x04000000)
2069 lp->stats.tx_aborted_errors++;
2070 if (err_status & 0x08000000)
2071 lp->stats.tx_carrier_errors++;
2072 if (err_status & 0x10000000)
2073 lp->stats.tx_window_errors++;
1da177e4 2074#ifndef DO_DXSUFLO
4a5e8e29
JG		 2075 if (err_status & 0x40000000) {
2076 lp->stats.tx_fifo_errors++;
2077 /* Ackk! On FIFO errors the Tx unit is turned off! */
2078 /* Remove this verbosity later! */
2079 if (netif_msg_tx_err(lp))
2080 printk(KERN_ERR
2081 "%s: Tx FIFO error! CSR0=%4.4x\n",
2082 dev->name, csr0);
2083 must_restart = 1;
2084 }
1da177e4 2085#else
4a5e8e29
JG		 2086 if (err_status & 0x40000000) {
2087 lp->stats.tx_fifo_errors++;
2088 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
2089 /* Ackk! On FIFO errors the Tx unit is turned off! */
2090 /* Remove this verbosity later! */
2091 if (netif_msg_tx_err
2092 (lp))
2093 printk(KERN_ERR
2094 "%s: Tx FIFO error! CSR0=%4.4x\n",
2095 dev->
2096 name,
2097 csr0);
2098 must_restart = 1;
2099 }
2100 }
1da177e4 2101#endif
4a5e8e29
JG		 2102 } else {
2103 if (status & 0x1800)
2104 lp->stats.collisions++;
2105 lp->stats.tx_packets++;
2106 }
2107
2108 /* We must free the original skb */
2109 if (lp->tx_skbuff[entry]) {
2110 pci_unmap_single(lp->pci_dev,
2111 lp->tx_dma_addr[entry],
2112 lp->tx_skbuff[entry]->
2113 len, PCI_DMA_TODEVICE);
2114 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2115 lp->tx_skbuff[entry] = NULL;
2116 lp->tx_dma_addr[entry] = 0;
2117 }
2118 dirty_tx++;
2119 }
2120
2121 delta =
2122 (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask +
2123 lp->tx_ring_size);
2124 if (delta > lp->tx_ring_size) {
2125 if (netif_msg_drv(lp))
2126 printk(KERN_ERR
2127 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2128 dev->name, dirty_tx, lp->cur_tx,
2129 lp->tx_full);
2130 dirty_tx += lp->tx_ring_size;
2131 delta -= lp->tx_ring_size;
2132 }
2133
2134 if (lp->tx_full &&
2135 netif_queue_stopped(dev) &&
2136 delta < lp->tx_ring_size - 2) {
2137 /* The ring is no longer full, clear tbusy. */
2138 lp->tx_full = 0;
2139 netif_wake_queue(dev);
2140 }
2141 lp->dirty_tx = dirty_tx;
2142 }
2143
2144 /* Log misc errors. */
2145 if (csr0 & 0x4000)
2146 lp->stats.tx_errors++; /* Tx babble. */
2147 if (csr0 & 0x1000) {
2148 /*
2149 * this happens when our receive ring is full. This shouldn't
2150 * be a problem as we will see normal rx interrupts for the frames
2151 * in the receive ring. But there are some PCI chipsets (I can
2152 * reproduce this on SP3G with Intel saturn chipset) which have
2153 * sometimes problems and will fill up the receive ring with
2154 * error descriptors. In this situation we don't get a rx
2155 * interrupt, but a missed frame interrupt sooner or later.
2156 * So we try to clean up our receive ring here.
2157 */
2158 pcnet32_rx(dev);
2159 lp->stats.rx_errors++; /* Missed a Rx frame. */
2160 }
2161 if (csr0 & 0x0800) {
2162 if (netif_msg_drv(lp))
2163 printk(KERN_ERR
2164 "%s: Bus master arbitration failure, status %4.4x.\n",
2165 dev->name, csr0);
2166 /* unlike for the lance, there is no restart needed */
1da177e4
LT		 2167 }
2168
4a5e8e29
JG		 2169 if (must_restart) {
2170 /* reset the chip to clear the error condition, then restart */
2171 lp->a.reset(ioaddr);
2172 lp->a.write_csr(ioaddr, 4, 0x0915);
2173 pcnet32_restart(dev, 0x0002);
2174 netif_wake_queue(dev);
1da177e4 2175 }
4a5e8e29
JG		 2176 }
2177
2178 /* Set interrupt enable. */
2179 lp->a.write_csr(ioaddr, 0, 0x0040);
2180 lp->a.write_rap(ioaddr, rap);
2181
2182 if (netif_msg_intr(lp))
2183 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2184 dev->name, lp->a.read_csr(ioaddr, 0));
2185
2186 spin_unlock(&lp->lock);
2187
2188 return IRQ_HANDLED;
1da177e4
LT		 2189}
2190
4a5e8e29 2191static int pcnet32_rx(struct net_device *dev)
1da177e4 2192{
4a5e8e29
JG		 2193 struct pcnet32_private *lp = dev->priv;
2194 int entry = lp->cur_rx & lp->rx_mod_mask;
2195 int boguscnt = lp->rx_ring_size / 2;
2196
2197 /* If we own the next entry, it's a new packet. Send it up. */
2198 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2199 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2200
2201 if (status != 0x03) { /* There was an error. */
2202 /*
2203 * There is a tricky error noted by John Murphy,
2204 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2205 * buffers it's possible for a jabber packet to use two
2206 * buffers, with only the last correctly noting the error.
2207 */
2208 if (status & 0x01) /* Only count a general error at the */
2209 lp->stats.rx_errors++; /* end of a packet. */
2210 if (status & 0x20)
2211 lp->stats.rx_frame_errors++;
2212 if (status & 0x10)
2213 lp->stats.rx_over_errors++;
2214 if (status & 0x08)
2215 lp->stats.rx_crc_errors++;
2216 if (status & 0x04)
2217 lp->stats.rx_fifo_errors++;
2218 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1da177e4 2219 } else {
4a5e8e29
JG		 2220 /* Malloc up new buffer, compatible with net-2e. */
2221 short pkt_len =
2222 (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)
2223 - 4;
2224 struct sk_buff *skb;
2225
2226 /* Discard oversize frames. */
2227 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2228 if (netif_msg_drv(lp))
2229 printk(KERN_ERR
2230 "%s: Impossible packet size %d!\n",
2231 dev->name, pkt_len);
2232 lp->stats.rx_errors++;
2233 } else if (pkt_len < 60) {
2234 if (netif_msg_rx_err(lp))
2235 printk(KERN_ERR "%s: Runt packet!\n",
2236 dev->name);
2237 lp->stats.rx_errors++;
2238 } else {
2239 int rx_in_place = 0;
2240
2241 if (pkt_len > rx_copybreak) {
2242 struct sk_buff *newskb;
2243
2244 if ((newskb =
2245 dev_alloc_skb(PKT_BUF_SZ))) {
2246 skb_reserve(newskb, 2);
2247 skb = lp->rx_skbuff[entry];
2248 pci_unmap_single(lp->pci_dev,
2249 lp->
2250 rx_dma_addr
2251 [entry],
2252 PKT_BUF_SZ - 2,
2253 PCI_DMA_FROMDEVICE);
2254 skb_put(skb, pkt_len);
2255 lp->rx_skbuff[entry] = newskb;
2256 newskb->dev = dev;
2257 lp->rx_dma_addr[entry] =
2258 pci_map_single(lp->pci_dev,
2259 newskb->data,
2260 PKT_BUF_SZ -
2261 2,
2262 PCI_DMA_FROMDEVICE);
2263 lp->rx_ring[entry].base =
2264 le32_to_cpu(lp->
2265 rx_dma_addr
2266 [entry]);
2267 rx_in_place = 1;
2268 } else
2269 skb = NULL;
2270 } else {
2271 skb = dev_alloc_skb(pkt_len + 2);
2272 }
2273
2274 if (skb == NULL) {
2275 int i;
2276 if (netif_msg_drv(lp))
2277 printk(KERN_ERR
2278 "%s: Memory squeeze, deferring packet.\n",
2279 dev->name);
2280 for (i = 0; i < lp->rx_ring_size; i++)
2281 if ((short)
2282 le16_to_cpu(lp->
2283 rx_ring[(entry +
2284 i)
2285 & lp->
2286 rx_mod_mask].
2287 status) < 0)
2288 break;
2289
2290 if (i > lp->rx_ring_size - 2) {
2291 lp->stats.rx_dropped++;
2292 lp->rx_ring[entry].status |=
2293 le16_to_cpu(0x8000);
2294 wmb(); /* Make sure adapter sees owner change */
2295 lp->cur_rx++;
2296 }
2297 break;
2298 }
2299 skb->dev = dev;
2300 if (!rx_in_place) {
2301 skb_reserve(skb, 2); /* 16 byte align */
2302 skb_put(skb, pkt_len); /* Make room */
2303 pci_dma_sync_single_for_cpu(lp->pci_dev,
2304 lp->
2305 rx_dma_addr
2306 [entry],
2307 PKT_BUF_SZ -
2308 2,
2309 PCI_DMA_FROMDEVICE);
2310 eth_copy_and_sum(skb,
2311 (unsigned char *)(lp->
2312 rx_skbuff
2313 [entry]->
2314 data),
2315 pkt_len, 0);
2316 pci_dma_sync_single_for_device(lp->
2317 pci_dev,
2318 lp->
2319 rx_dma_addr
2320 [entry],
2321 PKT_BUF_SZ
2322 - 2,
2323 PCI_DMA_FROMDEVICE);
2324 }
2325 lp->stats.rx_bytes += skb->len;
2326 skb->protocol = eth_type_trans(skb, dev);
2327 netif_rx(skb);
2328 dev->last_rx = jiffies;
2329 lp->stats.rx_packets++;
2330 }
1da177e4 2331 }
4a5e8e29
JG		 2332 /*
2333 * The docs say that the buffer length isn't touched, but Andrew Boyd
2334 * of QNX reports that some revs of the 79C965 clear it.
2335 */
2336 lp->rx_ring[entry].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2337 wmb(); /* Make sure owner changes after all others are visible */
2338 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2339 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2340 if (--boguscnt <= 0)
2341 break; /* don't stay in loop forever */
1da177e4 2342 }
4a5e8e29
JG		 2343
2344 return 0;
1da177e4
LT		 2345}
2346
4a5e8e29 2347static int pcnet32_close(struct net_device *dev)
1da177e4 2348{
4a5e8e29
JG		 2349 unsigned long ioaddr = dev->base_addr;
2350 struct pcnet32_private *lp = dev->priv;
2351 int i;
2352 unsigned long flags;
1da177e4 2353
4a5e8e29 2354 del_timer_sync(&lp->watchdog_timer);
1da177e4 2355
4a5e8e29 2356 netif_stop_queue(dev);
1da177e4 2357
4a5e8e29 2358 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2359
4a5e8e29 2360 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
1da177e4 2361
4a5e8e29
JG		 2362 if (netif_msg_ifdown(lp))
2363 printk(KERN_DEBUG
2364 "%s: Shutting down ethercard, status was %2.2x.\n",
2365 dev->name, lp->a.read_csr(ioaddr, 0));
1da177e4 2366
4a5e8e29
JG		 2367 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2368 lp->a.write_csr(ioaddr, 0, 0x0004);
1da177e4 2369
4a5e8e29
JG		 2370 /*
2371 * Switch back to 16bit mode to avoid problems with dumb
2372 * DOS packet driver after a warm reboot
2373 */
2374 lp->a.write_bcr(ioaddr, 20, 4);
1da177e4 2375
4a5e8e29 2376 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2377
4a5e8e29 2378 free_irq(dev->irq, dev);
1da177e4 2379
4a5e8e29 2380 spin_lock_irqsave(&lp->lock, flags);
1da177e4 2381
4a5e8e29
JG		 2382 /* free all allocated skbuffs */
2383 for (i = 0; i < lp->rx_ring_size; i++) {
2384 lp->rx_ring[i].status = 0;
2385 wmb(); /* Make sure adapter sees owner change */
2386 if (lp->rx_skbuff[i]) {
2387 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
2388 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2389 dev_kfree_skb(lp->rx_skbuff[i]);
2390 }
2391 lp->rx_skbuff[i] = NULL;
2392 lp->rx_dma_addr[i] = 0;
1da177e4 2393 }
1da177e4 2394
4a5e8e29
JG		 2395 for (i = 0; i < lp->tx_ring_size; i++) {
2396 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2397 wmb(); /* Make sure adapter sees owner change */
2398 if (lp->tx_skbuff[i]) {
2399 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2400 lp->tx_skbuff[i]->len,
2401 PCI_DMA_TODEVICE);
2402 dev_kfree_skb(lp->tx_skbuff[i]);
2403 }
2404 lp->tx_skbuff[i] = NULL;
2405 lp->tx_dma_addr[i] = 0;
1da177e4 2406 }
1da177e4 2407
4a5e8e29 2408 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2409
4a5e8e29 2410 return 0;
1da177e4
LT		 2411}
2412
4a5e8e29 2413static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
1da177e4 2414{
4a5e8e29
JG		 2415 struct pcnet32_private *lp = dev->priv;
2416 unsigned long ioaddr = dev->base_addr;
2417 u16 saved_addr;
2418 unsigned long flags;
2419
2420 spin_lock_irqsave(&lp->lock, flags);
2421 saved_addr = lp->a.read_rap(ioaddr);
2422 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2423 lp->a.write_rap(ioaddr, saved_addr);
2424 spin_unlock_irqrestore(&lp->lock, flags);
2425
2426 return &lp->stats;
1da177e4
LT		 2427}
2428
2429/* taken from the sunlance driver, which it took from the depca driver */
4a5e8e29 2430static void pcnet32_load_multicast(struct net_device *dev)
1da177e4 2431{
4a5e8e29
JG		 2432 struct pcnet32_private *lp = dev->priv;
2433 volatile struct pcnet32_init_block *ib = &lp->init_block;
2434 volatile u16 *mcast_table = (u16 *) & ib->filter;
2435 struct dev_mc_list *dmi = dev->mc_list;
2436 char *addrs;
2437 int i;
2438 u32 crc;
2439
2440 /* set all multicast bits */
2441 if (dev->flags & IFF_ALLMULTI) {
2442 ib->filter[0] = 0xffffffff;
2443 ib->filter[1] = 0xffffffff;
2444 return;
2445 }
2446 /* clear the multicast filter */
2447 ib->filter[0] = 0;
2448 ib->filter[1] = 0;
2449
2450 /* Add addresses */
2451 for (i = 0; i < dev->mc_count; i++) {
2452 addrs = dmi->dmi_addr;
2453 dmi = dmi->next;
2454
2455 /* multicast address? */
2456 if (!(*addrs & 1))
2457 continue;
2458
2459 crc = ether_crc_le(6, addrs);
2460 crc = crc >> 26;
2461 mcast_table[crc >> 4] =
2462 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2463 (1 << (crc & 0xf)));
2464 }
1da177e4 2465 return;
1da177e4
LT		 2466}
2467
1da177e4
LT		 2468/*
2469 * Set or clear the multicast filter for this adaptor.
2470 */
2471static void pcnet32_set_multicast_list(struct net_device *dev)
2472{
4a5e8e29
JG		 2473 unsigned long ioaddr = dev->base_addr, flags;
2474 struct pcnet32_private *lp = dev->priv;
2475
2476 spin_lock_irqsave(&lp->lock, flags);
2477 if (dev->flags & IFF_PROMISC) {
2478 /* Log any net taps. */
2479 if (netif_msg_hw(lp))
2480 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2481 dev->name);
2482 lp->init_block.mode =
2483 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2484 7);
2485 } else {
2486 lp->init_block.mode =
2487 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2488 pcnet32_load_multicast(dev);
2489 }
2490
2491 lp->a.write_csr(ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2492 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2493 netif_wake_queue(dev);
2494
2495 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4
LT		 2496}
2497
2498/* This routine assumes that the lp->lock is held */
2499static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2500{
4a5e8e29
JG		 2501 struct pcnet32_private *lp = dev->priv;
2502 unsigned long ioaddr = dev->base_addr;
2503 u16 val_out;
1da177e4 2504
4a5e8e29
JG		 2505 if (!lp->mii)
2506 return 0;
1da177e4 2507
4a5e8e29
JG		 2508 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2509 val_out = lp->a.read_bcr(ioaddr, 34);
1da177e4 2510
4a5e8e29 2511 return val_out;
1da177e4
LT		 2512}
2513
2514/* This routine assumes that the lp->lock is held */
2515static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2516{
4a5e8e29
JG		 2517 struct pcnet32_private *lp = dev->priv;
2518 unsigned long ioaddr = dev->base_addr;
1da177e4 2519
4a5e8e29
JG		 2520 if (!lp->mii)
2521 return;
1da177e4 2522
4a5e8e29
JG		 2523 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2524 lp->a.write_bcr(ioaddr, 34, val);
1da177e4
LT		 2525}
2526
2527static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2528{
4a5e8e29
JG		 2529 struct pcnet32_private *lp = dev->priv;
2530 int rc;
2531 unsigned long flags;
1da177e4 2532
4a5e8e29
JG		 2533 /* SIOC[GS]MIIxxx ioctls */
2534 if (lp->mii) {
2535 spin_lock_irqsave(&lp->lock, flags);
2536 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2537 spin_unlock_irqrestore(&lp->lock, flags);
2538 } else {
2539 rc = -EOPNOTSUPP;
2540 }
1da177e4 2541
4a5e8e29 2542 return rc;
1da177e4
LT		 2543}
2544
ac62ef04
DF		 2545static int pcnet32_check_otherphy(struct net_device *dev)
2546{
4a5e8e29
JG		 2547 struct pcnet32_private *lp = dev->priv;
2548 struct mii_if_info mii = lp->mii_if;
2549 u16 bmcr;
2550 int i;
ac62ef04 2551
4a5e8e29
JG		 2552 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2553 if (i == lp->mii_if.phy_id)
2554 continue; /* skip active phy */
2555 if (lp->phymask & (1 << i)) {
2556 mii.phy_id = i;
2557 if (mii_link_ok(&mii)) {
2558 /* found PHY with active link */
2559 if (netif_msg_link(lp))
2560 printk(KERN_INFO
2561 "%s: Using PHY number %d.\n",
2562 dev->name, i);
2563
2564 /* isolate inactive phy */
2565 bmcr =
2566 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2567 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2568 bmcr | BMCR_ISOLATE);
2569
2570 /* de-isolate new phy */
2571 bmcr = mdio_read(dev, i, MII_BMCR);
2572 mdio_write(dev, i, MII_BMCR,
2573 bmcr & ~BMCR_ISOLATE);
2574
2575 /* set new phy address */
2576 lp->mii_if.phy_id = i;
2577 return 1;
2578 }
2579 }
ac62ef04 2580 }
4a5e8e29 2581 return 0;
ac62ef04
DF		 2582}
2583
2584/*
2585 * Show the status of the media. Similar to mii_check_media however it
2586 * correctly shows the link speed for all (tested) pcnet32 variants.
2587 * Devices with no mii just report link state without speed.
2588 *
2589 * Caller is assumed to hold and release the lp->lock.
2590 */
2591
2592static void pcnet32_check_media(struct net_device *dev, int verbose)
2593{
4a5e8e29
JG		 2594 struct pcnet32_private *lp = dev->priv;
2595 int curr_link;
2596 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2597 u32 bcr9;
2598
ac62ef04 2599 if (lp->mii) {
4a5e8e29 2600 curr_link = mii_link_ok(&lp->mii_if);
ac62ef04 2601 } else {
4a5e8e29
JG		 2602 ulong ioaddr = dev->base_addr; /* card base I/O address */
2603 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2604 }
2605 if (!curr_link) {
2606 if (prev_link || verbose) {
2607 netif_carrier_off(dev);
2608 if (netif_msg_link(lp))
2609 printk(KERN_INFO "%s: link down\n", dev->name);
2610 }
2611 if (lp->phycount > 1) {
2612 curr_link = pcnet32_check_otherphy(dev);
2613 prev_link = 0;
2614 }
2615 } else if (verbose || !prev_link) {
2616 netif_carrier_on(dev);
2617 if (lp->mii) {
2618 if (netif_msg_link(lp)) {
2619 struct ethtool_cmd ecmd;
2620 mii_ethtool_gset(&lp->mii_if, &ecmd);
2621 printk(KERN_INFO
2622 "%s: link up, %sMbps, %s-duplex\n",
2623 dev->name,
2624 (ecmd.speed == SPEED_100) ? "100" : "10",
2625 (ecmd.duplex ==
2626 DUPLEX_FULL) ? "full" : "half");
2627 }
2628 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2629 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2630 if (lp->mii_if.full_duplex)
2631 bcr9 |= (1 << 0);
2632 else
2633 bcr9 &= ~(1 << 0);
2634 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2635 }
2636 } else {
2637 if (netif_msg_link(lp))
2638 printk(KERN_INFO "%s: link up\n", dev->name);
2639 }
ac62ef04 2640 }
ac62ef04
DF		 2641}
2642
2643/*
2644 * Check for loss of link and link establishment.
2645 * Can not use mii_check_media because it does nothing if mode is forced.
2646 */
2647
1da177e4
LT		 2648static void pcnet32_watchdog(struct net_device *dev)
2649{
4a5e8e29
JG		 2650 struct pcnet32_private *lp = dev->priv;
2651 unsigned long flags;
1da177e4 2652
4a5e8e29
JG		 2653 /* Print the link status if it has changed */
2654 spin_lock_irqsave(&lp->lock, flags);
2655 pcnet32_check_media(dev, 0);
2656 spin_unlock_irqrestore(&lp->lock, flags);
1da177e4 2657
4a5e8e29 2658 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1da177e4
LT		 2659}
2660
2661static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2662{
4a5e8e29
JG		 2663 struct net_device *dev = pci_get_drvdata(pdev);
2664
2665 if (dev) {
2666 struct pcnet32_private *lp = dev->priv;
2667
2668 unregister_netdev(dev);
2669 pcnet32_free_ring(dev);
2670 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2671 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2672 free_netdev(dev);
2673 pci_disable_device(pdev);
2674 pci_set_drvdata(pdev, NULL);
2675 }
1da177e4
LT		 2676}
2677
2678static struct pci_driver pcnet32_driver = {
4a5e8e29
JG		 2679 .name = DRV_NAME,
2680 .probe = pcnet32_probe_pci,
2681 .remove = __devexit_p(pcnet32_remove_one),
2682 .id_table = pcnet32_pci_tbl,
1da177e4
LT		 2683};
2684
2685/* An additional parameter that may be passed in... */
2686static int debug = -1;
2687static int tx_start_pt = -1;
2688static int pcnet32_have_pci;
2689
2690module_param(debug, int, 0);
2691MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2692module_param(max_interrupt_work, int, 0);
4a5e8e29
JG		 2693MODULE_PARM_DESC(max_interrupt_work,
2694 DRV_NAME " maximum events handled per interrupt");
1da177e4 2695module_param(rx_copybreak, int, 0);
4a5e8e29
JG		 2696MODULE_PARM_DESC(rx_copybreak,
2697 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 2698module_param(tx_start_pt, int, 0);
2699MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2700module_param(pcnet32vlb, int, 0);
2701MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2702module_param_array(options, int, NULL, 0);
2703MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2704module_param_array(full_duplex, int, NULL, 0);
2705MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2706/* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2707module_param_array(homepna, int, NULL, 0);
4a5e8e29
JG		 2708MODULE_PARM_DESC(homepna,
2709 DRV_NAME
2710 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
1da177e4
LT		 2711
2712MODULE_AUTHOR("Thomas Bogendoerfer");
2713MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2714MODULE_LICENSE("GPL");
2715
2716#define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2717
2718static int __init pcnet32_init_module(void)
2719{
4a5e8e29 2720 printk(KERN_INFO "%s", version);
1da177e4 2721
4a5e8e29 2722 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
1da177e4 2723
4a5e8e29
JG		 2724 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2725 tx_start = tx_start_pt;
1da177e4 2726
4a5e8e29
JG		 2727 /* find the PCI devices */
2728 if (!pci_module_init(&pcnet32_driver))
2729 pcnet32_have_pci = 1;
1da177e4 2730
4a5e8e29
JG		 2731 /* should we find any remaining VLbus devices ? */
2732 if (pcnet32vlb)
2733 pcnet32_probe_vlbus();
1da177e4 2734
4a5e8e29
JG		 2735 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2736 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1da177e4 2737
4a5e8e29 2738 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
1da177e4
LT		 2739}
2740
2741static void __exit pcnet32_cleanup_module(void)
2742{
4a5e8e29
JG		 2743 struct net_device *next_dev;
2744
2745 while (pcnet32_dev) {
2746 struct pcnet32_private *lp = pcnet32_dev->priv;
2747 next_dev = lp->next;
2748 unregister_netdev(pcnet32_dev);
2749 pcnet32_free_ring(pcnet32_dev);
2750 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2751 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2752 free_netdev(pcnet32_dev);
2753 pcnet32_dev = next_dev;
2754 }
1da177e4 2755
4a5e8e29
JG		 2756 if (pcnet32_have_pci)
2757 pci_unregister_driver(&pcnet32_driver);
1da177e4
LT		 2758}
2759
2760module_init(pcnet32_init_module);
2761module_exit(pcnet32_cleanup_module);
2762
2763/*
2764 * Local variables:
2765 * c-indent-level: 4
2766 * tab-width: 8
2767 * End:
2768 */
Clone of davem's net-next-2.6 tree