]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/net/pcmcia/nmclan_cs.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Massive net driver const-ification.
[net-next-2.6.git] / drivers / net / pcmcia / nmclan_cs.c
CommitLineData
1da177e4
LT		 1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define DRV_NAME "nmclan_cs"
115#define DRV_VERSION "0.16"
116
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/init.h>
134#include <linux/ptrace.h>
135#include <linux/slab.h>
136#include <linux/string.h>
137#include <linux/timer.h>
138#include <linux/interrupt.h>
139#include <linux/in.h>
140#include <linux/delay.h>
141#include <linux/ethtool.h>
142#include <linux/netdevice.h>
143#include <linux/etherdevice.h>
144#include <linux/skbuff.h>
145#include <linux/if_arp.h>
146#include <linux/ioport.h>
147#include <linux/bitops.h>
148
1da177e4
LT		 149#include <pcmcia/cs_types.h>
150#include <pcmcia/cs.h>
151#include <pcmcia/cisreg.h>
152#include <pcmcia/cistpl.h>
153#include <pcmcia/ds.h>
154
155#include <asm/uaccess.h>
156#include <asm/io.h>
157#include <asm/system.h>
158
159/* ----------------------------------------------------------------------------
160Defines
161---------------------------------------------------------------------------- */
162
163#define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165#define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168/* Loop Control Defines */
169#define MACE_MAX_IR_ITERATIONS 10
170#define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180/*
181The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182which manages the interface between the MACE and the PCMCIA bus. It
183also includes buffer management for the 32K x 8 SRAM to control up to
184four transmit and 12 receive frames at a time.
185*/
186#define AM2150_MAX_TX_FRAMES 4
187#define AM2150_MAX_RX_FRAMES 12
188
189/* Am2150 Ethernet Card I/O Mapping */
190#define AM2150_RCV 0x00
191#define AM2150_XMT 0x04
192#define AM2150_XMT_SKIP 0x09
193#define AM2150_RCV_NEXT 0x0A
194#define AM2150_RCV_FRAME_COUNT 0x0B
195#define AM2150_MACE_BANK 0x0C
196#define AM2150_MACE_BASE 0x10
197
198/* MACE Registers */
199#define MACE_RCVFIFO 0
200#define MACE_XMTFIFO 1
201#define MACE_XMTFC 2
202#define MACE_XMTFS 3
203#define MACE_XMTRC 4
204#define MACE_RCVFC 5
205#define MACE_RCVFS 6
206#define MACE_FIFOFC 7
207#define MACE_IR 8
208#define MACE_IMR 9
209#define MACE_PR 10
210#define MACE_BIUCC 11
211#define MACE_FIFOCC 12
212#define MACE_MACCC 13
213#define MACE_PLSCC 14
214#define MACE_PHYCC 15
215#define MACE_CHIPIDL 16
216#define MACE_CHIPIDH 17
217#define MACE_IAC 18
218/* Reserved */
219#define MACE_LADRF 20
220#define MACE_PADR 21
221/* Reserved */
222/* Reserved */
223#define MACE_MPC 24
224/* Reserved */
225#define MACE_RNTPC 26
226#define MACE_RCVCC 27
227/* Reserved */
228#define MACE_UTR 29
229#define MACE_RTR1 30
230#define MACE_RTR2 31
231
232/* MACE Bit Masks */
233#define MACE_XMTRC_EXDEF 0x80
234#define MACE_XMTRC_XMTRC 0x0F
235
236#define MACE_XMTFS_XMTSV 0x80
237#define MACE_XMTFS_UFLO 0x40
238#define MACE_XMTFS_LCOL 0x20
239#define MACE_XMTFS_MORE 0x10
240#define MACE_XMTFS_ONE 0x08
241#define MACE_XMTFS_DEFER 0x04
242#define MACE_XMTFS_LCAR 0x02
243#define MACE_XMTFS_RTRY 0x01
244
245#define MACE_RCVFS_RCVSTS 0xF000
246#define MACE_RCVFS_OFLO 0x8000
247#define MACE_RCVFS_CLSN 0x4000
248#define MACE_RCVFS_FRAM 0x2000
249#define MACE_RCVFS_FCS 0x1000
250
251#define MACE_FIFOFC_RCVFC 0xF0
252#define MACE_FIFOFC_XMTFC 0x0F
253
254#define MACE_IR_JAB 0x80
255#define MACE_IR_BABL 0x40
256#define MACE_IR_CERR 0x20
257#define MACE_IR_RCVCCO 0x10
258#define MACE_IR_RNTPCO 0x08
259#define MACE_IR_MPCO 0x04
260#define MACE_IR_RCVINT 0x02
261#define MACE_IR_XMTINT 0x01
262
263#define MACE_MACCC_PROM 0x80
264#define MACE_MACCC_DXMT2PD 0x40
265#define MACE_MACCC_EMBA 0x20
266#define MACE_MACCC_RESERVED 0x10
267#define MACE_MACCC_DRCVPA 0x08
268#define MACE_MACCC_DRCVBC 0x04
269#define MACE_MACCC_ENXMT 0x02
270#define MACE_MACCC_ENRCV 0x01
271
272#define MACE_PHYCC_LNKFL 0x80
273#define MACE_PHYCC_DLNKTST 0x40
274#define MACE_PHYCC_REVPOL 0x20
275#define MACE_PHYCC_DAPC 0x10
276#define MACE_PHYCC_LRT 0x08
277#define MACE_PHYCC_ASEL 0x04
278#define MACE_PHYCC_RWAKE 0x02
279#define MACE_PHYCC_AWAKE 0x01
280
281#define MACE_IAC_ADDRCHG 0x80
282#define MACE_IAC_PHYADDR 0x04
283#define MACE_IAC_LOGADDR 0x02
284
285#define MACE_UTR_RTRE 0x80
286#define MACE_UTR_RTRD 0x40
287#define MACE_UTR_RPA 0x20
288#define MACE_UTR_FCOLL 0x10
289#define MACE_UTR_RCVFCSE 0x08
290#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291#define MACE_UTR_LOOP_NO_MENDEC 0x04
292#define MACE_UTR_LOOP_EXTERNAL 0x02
293#define MACE_UTR_LOOP_NONE 0x00
294#define MACE_UTR_RESERVED 0x01
295
296/* Switch MACE register bank (only 0 and 1 are valid) */
297#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299#define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310#undef MACE_IMR_DEFAULT
311#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313#define TX_TIMEOUT ((400*HZ)/1000)
314
315/* ----------------------------------------------------------------------------
316Type Definitions
317---------------------------------------------------------------------------- */
318
319typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362} mace_statistics;
363
364typedef struct _mace_private {
365 dev_link_t link;
366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378} mace_private;
379
380/* ----------------------------------------------------------------------------
381Private Global Variables
382---------------------------------------------------------------------------- */
383
384#ifdef PCMCIA_DEBUG
385static char rcsid[] =
386"nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
387static char *version =
388DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
389#endif
390
f71e1309 391static const char *if_names[]={
1da177e4
LT		 392 "Auto", "10baseT", "BNC",
393};
394
395/* ----------------------------------------------------------------------------
396Parameters
397 These are the parameters that can be set during loading with
398 'insmod'.
399---------------------------------------------------------------------------- */
400
401MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
402MODULE_LICENSE("GPL");
403
404#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
405
406/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
407INT_MODULE_PARM(if_port, 0);
408
409#ifdef PCMCIA_DEBUG
410INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
411#define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
412#else
413#define DEBUG(n, args...)
414#endif
415
416/* ----------------------------------------------------------------------------
417Function Prototypes
418---------------------------------------------------------------------------- */
419
420static void nmclan_config(dev_link_t *link);
421static void nmclan_release(dev_link_t *link);
1da177e4
LT		 422
423static void nmclan_reset(struct net_device *dev);
424static int mace_config(struct net_device *dev, struct ifmap *map);
425static int mace_open(struct net_device *dev);
426static int mace_close(struct net_device *dev);
427static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
428static void mace_tx_timeout(struct net_device *dev);
429static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
430static struct net_device_stats *mace_get_stats(struct net_device *dev);
431static int mace_rx(struct net_device *dev, unsigned char RxCnt);
432static void restore_multicast_list(struct net_device *dev);
433static void set_multicast_list(struct net_device *dev);
434static struct ethtool_ops netdev_ethtool_ops;
435
436
cc3b4866 437static void nmclan_detach(struct pcmcia_device *p_dev);
1da177e4
LT		 438
439/* ----------------------------------------------------------------------------
440nmclan_attach
441 Creates an "instance" of the driver, allocating local data
442 structures for one device. The device is registered with Card
443 Services.
444---------------------------------------------------------------------------- */
445
f8cfa618 446static int nmclan_attach(struct pcmcia_device *p_dev)
1da177e4
LT		 447{
448 mace_private *lp;
449 dev_link_t *link;
450 struct net_device *dev;
1da177e4
LT		 451
452 DEBUG(0, "nmclan_attach()\n");
453 DEBUG(1, "%s\n", rcsid);
454
455 /* Create new ethernet device */
456 dev = alloc_etherdev(sizeof(mace_private));
457 if (!dev)
f8cfa618 458 return -ENOMEM;
1da177e4
LT		 459 lp = netdev_priv(dev);
460 link = &lp->link;
461 link->priv = dev;
462
463 spin_lock_init(&lp->bank_lock);
464 link->io.NumPorts1 = 32;
465 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
466 link->io.IOAddrLines = 5;
467 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
468 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
469 link->irq.Handler = &mace_interrupt;
470 link->irq.Instance = dev;
471 link->conf.Attributes = CONF_ENABLE_IRQ;
472 link->conf.Vcc = 50;
473 link->conf.IntType = INT_MEMORY_AND_IO;
474 link->conf.ConfigIndex = 1;
475 link->conf.Present = PRESENT_OPTION;
476
477 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
478
479 SET_MODULE_OWNER(dev);
480 dev->hard_start_xmit = &mace_start_xmit;
481 dev->set_config = &mace_config;
482 dev->get_stats = &mace_get_stats;
483 dev->set_multicast_list = &set_multicast_list;
484 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
485 dev->open = &mace_open;
486 dev->stop = &mace_close;
487#ifdef HAVE_TX_TIMEOUT
488 dev->tx_timeout = mace_tx_timeout;
489 dev->watchdog_timeo = TX_TIMEOUT;
490#endif
491
f8cfa618
DB		 492 link->handle = p_dev;
493 p_dev->instance = link;
494
495 link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
496 nmclan_config(link);
1da177e4 497
f8cfa618 498 return 0;
1da177e4
LT		 499} /* nmclan_attach */
500
501/* ----------------------------------------------------------------------------
502nmclan_detach
503 This deletes a driver "instance". The device is de-registered
504 with Card Services. If it has been released, all local data
505 structures are freed. Otherwise, the structures will be freed
506 when the device is released.
507---------------------------------------------------------------------------- */
508
cc3b4866 509static void nmclan_detach(struct pcmcia_device *p_dev)
1da177e4 510{
cc3b4866 511 dev_link_t *link = dev_to_instance(p_dev);
1da177e4 512 struct net_device *dev = link->priv;
1da177e4
LT		 513
514 DEBUG(0, "nmclan_detach(0x%p)\n", link);
515
1da177e4
LT		 516 if (link->dev)
517 unregister_netdev(dev);
518
519 if (link->state & DEV_CONFIG)
520 nmclan_release(link);
521
1da177e4
LT		 522 free_netdev(dev);
523} /* nmclan_detach */
524
525/* ----------------------------------------------------------------------------
526mace_read
527 Reads a MACE register. This is bank independent; however, the
528 caller must ensure that this call is not interruptable. We are
529 assuming that during normal operation, the MACE is always in
530 bank 0.
531---------------------------------------------------------------------------- */
532static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
533{
534 int data = 0xFF;
535 unsigned long flags;
536
537 switch (reg >> 4) {
538 case 0: /* register 0-15 */
539 data = inb(ioaddr + AM2150_MACE_BASE + reg);
540 break;
541 case 1: /* register 16-31 */
542 spin_lock_irqsave(&lp->bank_lock, flags);
543 MACEBANK(1);
544 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
545 MACEBANK(0);
546 spin_unlock_irqrestore(&lp->bank_lock, flags);
547 break;
548 }
549 return (data & 0xFF);
550} /* mace_read */
551
552/* ----------------------------------------------------------------------------
553mace_write
554 Writes to a MACE register. This is bank independent; however,
555 the caller must ensure that this call is not interruptable. We
556 are assuming that during normal operation, the MACE is always in
557 bank 0.
558---------------------------------------------------------------------------- */
559static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
560{
561 unsigned long flags;
562
563 switch (reg >> 4) {
564 case 0: /* register 0-15 */
565 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
566 break;
567 case 1: /* register 16-31 */
568 spin_lock_irqsave(&lp->bank_lock, flags);
569 MACEBANK(1);
570 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
571 MACEBANK(0);
572 spin_unlock_irqrestore(&lp->bank_lock, flags);
573 break;
574 }
575} /* mace_write */
576
577/* ----------------------------------------------------------------------------
578mace_init
579 Resets the MACE chip.
580---------------------------------------------------------------------------- */
581static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
582{
583 int i;
584 int ct = 0;
585
586 /* MACE Software reset */
587 mace_write(lp, ioaddr, MACE_BIUCC, 1);
588 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
589 /* Wait for reset bit to be cleared automatically after <= 200ns */;
590 if(++ct > 500)
591 {
592 printk(KERN_ERR "mace: reset failed, card removed ?\n");
593 return -1;
594 }
595 udelay(1);
596 }
597 mace_write(lp, ioaddr, MACE_BIUCC, 0);
598
599 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
600 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
601
602 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
603 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
604
605 /*
606 * Bit 2-1 PORTSEL[1-0] Port Select.
607 * 00 AUI/10Base-2
608 * 01 10Base-T
609 * 10 DAI Port (reserved in Am2150)
610 * 11 GPSI
611 * For this card, only the first two are valid.
612 * So, PLSCC should be set to
613 * 0x00 for 10Base-2
614 * 0x02 for 10Base-T
615 * Or just set ASEL in PHYCC below!
616 */
617 switch (if_port) {
618 case 1:
619 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
620 break;
621 case 2:
622 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
623 break;
624 default:
625 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
626 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
627 and the MACE device will automatically select the operating media
628 interface port. */
629 break;
630 }
631
632 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
633 /* Poll ADDRCHG bit */
634 ct = 0;
635 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
636 {
637 if(++ ct > 500)
638 {
639 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
640 return -1;
641 }
642 }
643 /* Set PADR register */
644 for (i = 0; i < ETHER_ADDR_LEN; i++)
645 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
646
647 /* MAC Configuration Control Register should be written last */
648 /* Let set_multicast_list set this. */
649 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
650 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
651 return 0;
652} /* mace_init */
653
654/* ----------------------------------------------------------------------------
655nmclan_config
656 This routine is scheduled to run after a CARD_INSERTION event
657 is received, to configure the PCMCIA socket, and to make the
658 ethernet device available to the system.
659---------------------------------------------------------------------------- */
660
661#define CS_CHECK(fn, ret) \
662 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
663
664static void nmclan_config(dev_link_t *link)
665{
666 client_handle_t handle = link->handle;
667 struct net_device *dev = link->priv;
668 mace_private *lp = netdev_priv(dev);
669 tuple_t tuple;
670 cisparse_t parse;
671 u_char buf[64];
672 int i, last_ret, last_fn;
673 kio_addr_t ioaddr;
674
675 DEBUG(0, "nmclan_config(0x%p)\n", link);
676
677 tuple.Attributes = 0;
678 tuple.TupleData = buf;
679 tuple.TupleDataMax = 64;
680 tuple.TupleOffset = 0;
681 tuple.DesiredTuple = CISTPL_CONFIG;
682 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
683 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
684 CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
685 link->conf.ConfigBase = parse.config.base;
686
687 /* Configure card */
688 link->state |= DEV_CONFIG;
689
690 CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
691 CS_CHECK(RequestIRQ, pcmcia_request_irq(handle, &link->irq));
692 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(handle, &link->conf));
693 dev->irq = link->irq.AssignedIRQ;
694 dev->base_addr = link->io.BasePort1;
695
696 ioaddr = dev->base_addr;
697
698 /* Read the ethernet address from the CIS. */
699 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
700 tuple.TupleData = buf;
701 tuple.TupleDataMax = 64;
702 tuple.TupleOffset = 0;
703 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
704 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
705 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
706
707 /* Verify configuration by reading the MACE ID. */
708 {
709 char sig[2];
710
711 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
712 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
713 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
714 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
715 sig[0], sig[1]);
716 } else {
717 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
718 " be 0x40 0x?9\n", sig[0], sig[1]);
719 link->state &= ~DEV_CONFIG_PENDING;
720 return;
721 }
722 }
723
724 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
725 goto failed;
726
727 /* The if_port symbol can be set when the module is loaded */
728 if (if_port <= 2)
729 dev->if_port = if_port;
730 else
731 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
732
733 link->dev = &lp->node;
734 link->state &= ~DEV_CONFIG_PENDING;
735 SET_NETDEV_DEV(dev, &handle_to_dev(handle));
736
737 i = register_netdev(dev);
738 if (i != 0) {
739 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
740 link->dev = NULL;
741 goto failed;
742 }
743
744 strcpy(lp->node.dev_name, dev->name);
745
746 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
747 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
748 for (i = 0; i < 6; i++)
749 printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
750 return;
751
752cs_failed:
753 cs_error(link->handle, last_fn, last_ret);
754failed:
755 nmclan_release(link);
756 return;
757
758} /* nmclan_config */
759
760/* ----------------------------------------------------------------------------
761nmclan_release
762 After a card is removed, nmclan_release() will unregister the
763 net device, and release the PCMCIA configuration. If the device
764 is still open, this will be postponed until it is closed.
765---------------------------------------------------------------------------- */
766static void nmclan_release(dev_link_t *link)
767{
768
769 DEBUG(0, "nmclan_release(0x%p)\n", link);
770
771 pcmcia_release_configuration(link->handle);
772 pcmcia_release_io(link->handle, &link->io);
773 pcmcia_release_irq(link->handle, &link->irq);
774
775 link->state &= ~DEV_CONFIG;
776}
777
98e4c28b
DB		 778static int nmclan_suspend(struct pcmcia_device *p_dev)
779{
780 dev_link_t *link = dev_to_instance(p_dev);
781 struct net_device *dev = link->priv;
782
783 link->state |= DEV_SUSPEND;
784 if (link->state & DEV_CONFIG) {
785 if (link->open)
786 netif_device_detach(dev);
787 pcmcia_release_configuration(link->handle);
788 }
789
790
791 return 0;
792}
793
794static int nmclan_resume(struct pcmcia_device *p_dev)
795{
796 dev_link_t *link = dev_to_instance(p_dev);
797 struct net_device *dev = link->priv;
798
799 link->state &= ~DEV_SUSPEND;
800 if (link->state & DEV_CONFIG) {
801 pcmcia_request_configuration(link->handle, &link->conf);
802 if (link->open) {
803 nmclan_reset(dev);
804 netif_device_attach(dev);
805 }
806 }
807
808 return 0;
809}
810
1da177e4
LT		 811
812/* ----------------------------------------------------------------------------
813nmclan_reset
814 Reset and restore all of the Xilinx and MACE registers.
815---------------------------------------------------------------------------- */
816static void nmclan_reset(struct net_device *dev)
817{
818 mace_private *lp = netdev_priv(dev);
819
820#if RESET_XILINX
821 dev_link_t *link = &lp->link;
822 conf_reg_t reg;
823 u_long OrigCorValue;
824
825 /* Save original COR value */
826 reg.Function = 0;
827 reg.Action = CS_READ;
828 reg.Offset = CISREG_COR;
829 reg.Value = 0;
830 pcmcia_access_configuration_register(link->handle, &reg);
831 OrigCorValue = reg.Value;
832
833 /* Reset Xilinx */
834 reg.Action = CS_WRITE;
835 reg.Offset = CISREG_COR;
836 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
837 OrigCorValue);
838 reg.Value = COR_SOFT_RESET;
839 pcmcia_access_configuration_register(link->handle, &reg);
840 /* Need to wait for 20 ms for PCMCIA to finish reset. */
841
842 /* Restore original COR configuration index */
843 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
844 pcmcia_access_configuration_register(link->handle, &reg);
845 /* Xilinx is now completely reset along with the MACE chip. */
846 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
847
848#endif /* #if RESET_XILINX */
849
850 /* Xilinx is now completely reset along with the MACE chip. */
851 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
852
853 /* Reinitialize the MACE chip for operation. */
854 mace_init(lp, dev->base_addr, dev->dev_addr);
855 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
856
857 /* Restore the multicast list and enable TX and RX. */
858 restore_multicast_list(dev);
859} /* nmclan_reset */
860
861/* ----------------------------------------------------------------------------
862mace_config
863 [Someone tell me what this is supposed to do? Is if_port a defined
864 standard? If so, there should be defines to indicate 1=10Base-T,
865 2=10Base-2, etc. including limited automatic detection.]
866---------------------------------------------------------------------------- */
867static int mace_config(struct net_device *dev, struct ifmap *map)
868{
869 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
870 if (map->port <= 2) {
871 dev->if_port = map->port;
872 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
873 if_names[dev->if_port]);
874 } else
875 return -EINVAL;
876 }
877 return 0;
878} /* mace_config */
879
880/* ----------------------------------------------------------------------------
881mace_open
882 Open device driver.
883---------------------------------------------------------------------------- */
884static int mace_open(struct net_device *dev)
885{
886 kio_addr_t ioaddr = dev->base_addr;
887 mace_private *lp = netdev_priv(dev);
888 dev_link_t *link = &lp->link;
889
890 if (!DEV_OK(link))
891 return -ENODEV;
892
893 link->open++;
894
895 MACEBANK(0);
896
897 netif_start_queue(dev);
898 nmclan_reset(dev);
899
900 return 0; /* Always succeed */
901} /* mace_open */
902
903/* ----------------------------------------------------------------------------
904mace_close
905 Closes device driver.
906---------------------------------------------------------------------------- */
907static int mace_close(struct net_device *dev)
908{
909 kio_addr_t ioaddr = dev->base_addr;
910 mace_private *lp = netdev_priv(dev);
911 dev_link_t *link = &lp->link;
912
913 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
914
915 /* Mask off all interrupts from the MACE chip. */
916 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
917
918 link->open--;
919 netif_stop_queue(dev);
920
921 return 0;
922} /* mace_close */
923
924static void netdev_get_drvinfo(struct net_device *dev,
925 struct ethtool_drvinfo *info)
926{
927 strcpy(info->driver, DRV_NAME);
928 strcpy(info->version, DRV_VERSION);
929 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
930}
931
932#ifdef PCMCIA_DEBUG
933static u32 netdev_get_msglevel(struct net_device *dev)
934{
935 return pc_debug;
936}
937
938static void netdev_set_msglevel(struct net_device *dev, u32 level)
939{
940 pc_debug = level;
941}
942#endif /* PCMCIA_DEBUG */
943
944static struct ethtool_ops netdev_ethtool_ops = {
945 .get_drvinfo = netdev_get_drvinfo,
946#ifdef PCMCIA_DEBUG
947 .get_msglevel = netdev_get_msglevel,
948 .set_msglevel = netdev_set_msglevel,
949#endif /* PCMCIA_DEBUG */
950};
951
952/* ----------------------------------------------------------------------------
953mace_start_xmit
954 This routine begins the packet transmit function. When completed,
955 it will generate a transmit interrupt.
956
957 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
958 returns 0, the "packet is now solely the responsibility of the
959 driver." If _start_xmit returns non-zero, the "transmission
960 failed, put skb back into a list."
961---------------------------------------------------------------------------- */
962
963static void mace_tx_timeout(struct net_device *dev)
964{
965 mace_private *lp = netdev_priv(dev);
966 dev_link_t *link = &lp->link;
967
968 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
969#if RESET_ON_TIMEOUT
970 printk("resetting card\n");
971 pcmcia_reset_card(link->handle, NULL);
972#else /* #if RESET_ON_TIMEOUT */
973 printk("NOT resetting card\n");
974#endif /* #if RESET_ON_TIMEOUT */
975 dev->trans_start = jiffies;
976 netif_wake_queue(dev);
977}
978
979static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
980{
981 mace_private *lp = netdev_priv(dev);
982 kio_addr_t ioaddr = dev->base_addr;
983
984 netif_stop_queue(dev);
985
986 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
987 dev->name, (long)skb->len);
988
989#if (!TX_INTERRUPTABLE)
990 /* Disable MACE TX interrupts. */
991 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
992 ioaddr + AM2150_MACE_BASE + MACE_IMR);
993 lp->tx_irq_disabled=1;
994#endif /* #if (!TX_INTERRUPTABLE) */
995
996 {
997 /* This block must not be interrupted by another transmit request!
998 mace_tx_timeout will take care of timer-based retransmissions from
999 the upper layers. The interrupt handler is guaranteed never to
1000 service a transmit interrupt while we are in here.
1001 */
1002
1003 lp->linux_stats.tx_bytes += skb->len;
1004 lp->tx_free_frames--;
1005
1006 /* WARNING: Write the _exact_ number of bytes written in the header! */
1007 /* Put out the word header [must be an outw()] . . . */
1008 outw(skb->len, ioaddr + AM2150_XMT);
1009 /* . . . and the packet [may be any combination of outw() and outb()] */
1010 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1011 if (skb->len & 1) {
1012 /* Odd byte transfer */
1013 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1014 }
1015
1016 dev->trans_start = jiffies;
1017
1018#if MULTI_TX
1019 if (lp->tx_free_frames > 0)
1020 netif_start_queue(dev);
1021#endif /* #if MULTI_TX */
1022 }
1023
1024#if (!TX_INTERRUPTABLE)
1025 /* Re-enable MACE TX interrupts. */
1026 lp->tx_irq_disabled=0;
1027 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1028#endif /* #if (!TX_INTERRUPTABLE) */
1029
1030 dev_kfree_skb(skb);
1031
1032 return 0;
1033} /* mace_start_xmit */
1034
1035/* ----------------------------------------------------------------------------
1036mace_interrupt
1037 The interrupt handler.
1038---------------------------------------------------------------------------- */
1039static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1040{
1041 struct net_device *dev = (struct net_device *) dev_id;
1042 mace_private *lp = netdev_priv(dev);
1043 kio_addr_t ioaddr = dev->base_addr;
1044 int status;
1045 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1046
1047 if (dev == NULL) {
1048 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1049 irq);
1050 return IRQ_NONE;
1051 }
1052
1053 if (lp->tx_irq_disabled) {
1054 printk(
1055 (lp->tx_irq_disabled?
1056 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1057 "[isr=%02X, imr=%02X]\n":
1058 KERN_NOTICE "%s: Re-entering the interrupt handler "
1059 "[isr=%02X, imr=%02X]\n"),
1060 dev->name,
1061 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1062 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1063 );
1064 /* WARNING: MACE_IR has been read! */
1065 return IRQ_NONE;
1066 }
1067
1068 if (!netif_device_present(dev)) {
1069 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1070 return IRQ_NONE;
1071 }
1072
1073 do {
1074 /* WARNING: MACE_IR is a READ/CLEAR port! */
1075 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1076
1077 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1078
1079 if (status & MACE_IR_RCVINT) {
1080 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1081 }
1082
1083 if (status & MACE_IR_XMTINT) {
1084 unsigned char fifofc;
1085 unsigned char xmtrc;
1086 unsigned char xmtfs;
1087
1088 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1089 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1090 lp->linux_stats.tx_errors++;
1091 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1092 }
1093
1094 /* Transmit Retry Count (XMTRC, reg 4) */
1095 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1096 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1097 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1098
1099 if (
1100 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1101 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1102 ) {
1103 lp->mace_stats.xmtsv++;
1104
1105 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1106 if (xmtfs & MACE_XMTFS_UFLO) {
1107 /* Underflow. Indicates that the Transmit FIFO emptied before
1108 the end of frame was reached. */
1109 lp->mace_stats.uflo++;
1110 }
1111 if (xmtfs & MACE_XMTFS_LCOL) {
1112 /* Late Collision */
1113 lp->mace_stats.lcol++;
1114 }
1115 if (xmtfs & MACE_XMTFS_MORE) {
1116 /* MORE than one retry was needed */
1117 lp->mace_stats.more++;
1118 }
1119 if (xmtfs & MACE_XMTFS_ONE) {
1120 /* Exactly ONE retry occurred */
1121 lp->mace_stats.one++;
1122 }
1123 if (xmtfs & MACE_XMTFS_DEFER) {
1124 /* Transmission was defered */
1125 lp->mace_stats.defer++;
1126 }
1127 if (xmtfs & MACE_XMTFS_LCAR) {
1128 /* Loss of carrier */
1129 lp->mace_stats.lcar++;
1130 }
1131 if (xmtfs & MACE_XMTFS_RTRY) {
1132 /* Retry error: transmit aborted after 16 attempts */
1133 lp->mace_stats.rtry++;
1134 }
1135 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1136
1137 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1138
1139 lp->linux_stats.tx_packets++;
1140 lp->tx_free_frames++;
1141 netif_wake_queue(dev);
1142 } /* if (status & MACE_IR_XMTINT) */
1143
1144 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1145 if (status & MACE_IR_JAB) {
1146 /* Jabber Error. Excessive transmit duration (20-150ms). */
1147 lp->mace_stats.jab++;
1148 }
1149 if (status & MACE_IR_BABL) {
1150 /* Babble Error. >1518 bytes transmitted. */
1151 lp->mace_stats.babl++;
1152 }
1153 if (status & MACE_IR_CERR) {
1154 /* Collision Error. CERR indicates the absence of the
1155 Signal Quality Error Test message after a packet
1156 transmission. */
1157 lp->mace_stats.cerr++;
1158 }
1159 if (status & MACE_IR_RCVCCO) {
1160 /* Receive Collision Count Overflow; */
1161 lp->mace_stats.rcvcco++;
1162 }
1163 if (status & MACE_IR_RNTPCO) {
1164 /* Runt Packet Count Overflow */
1165 lp->mace_stats.rntpco++;
1166 }
1167 if (status & MACE_IR_MPCO) {
1168 /* Missed Packet Count Overflow */
1169 lp->mace_stats.mpco++;
1170 }
1171 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1172
1173 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1174
1175 return IRQ_HANDLED;
1176} /* mace_interrupt */
1177
1178/* ----------------------------------------------------------------------------
1179mace_rx
1180 Receives packets.
1181---------------------------------------------------------------------------- */
1182static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1183{
1184 mace_private *lp = netdev_priv(dev);
1185 kio_addr_t ioaddr = dev->base_addr;
1186 unsigned char rx_framecnt;
1187 unsigned short rx_status;
1188
1189 while (
1190 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1191 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1192 (RxCnt--)
1193 ) {
1194 rx_status = inw(ioaddr + AM2150_RCV);
1195
1196 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1197 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1198
1199 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1200 lp->linux_stats.rx_errors++;
1201 if (rx_status & MACE_RCVFS_OFLO) {
1202 lp->mace_stats.oflo++;
1203 }
1204 if (rx_status & MACE_RCVFS_CLSN) {
1205 lp->mace_stats.clsn++;
1206 }
1207 if (rx_status & MACE_RCVFS_FRAM) {
1208 lp->mace_stats.fram++;
1209 }
1210 if (rx_status & MACE_RCVFS_FCS) {
1211 lp->mace_stats.fcs++;
1212 }
1213 } else {
1214 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1215 /* Auto Strip is off, always subtract 4 */
1216 struct sk_buff *skb;
1217
1218 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1219 /* runt packet count */
1220 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1221 /* rcv collision count */
1222
1223 DEBUG(3, " receiving packet size 0x%X rx_status"
1224 " 0x%X.\n", pkt_len, rx_status);
1225
1226 skb = dev_alloc_skb(pkt_len+2);
1227
1228 if (skb != NULL) {
1229 skb->dev = dev;
1230
1231 skb_reserve(skb, 2);
1232 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1233 if (pkt_len & 1)
1234 *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1235 skb->protocol = eth_type_trans(skb, dev);
1236
1237 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1238
1239 dev->last_rx = jiffies;
1240 lp->linux_stats.rx_packets++;
1241 lp->linux_stats.rx_bytes += skb->len;
1242 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1243 continue;
1244 } else {
1245 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1246 " %d.\n", dev->name, pkt_len);
1247 lp->linux_stats.rx_dropped++;
1248 }
1249 }
1250 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1251 } /* while */
1252
1253 return 0;
1254} /* mace_rx */
1255
1256/* ----------------------------------------------------------------------------
1257pr_linux_stats
1258---------------------------------------------------------------------------- */
1259static void pr_linux_stats(struct net_device_stats *pstats)
1260{
1261 DEBUG(2, "pr_linux_stats\n");
1262 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1263 (long)pstats->rx_packets, (long)pstats->tx_packets);
1264 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1265 (long)pstats->rx_errors, (long)pstats->tx_errors);
1266 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1267 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1268 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1269 (long)pstats->multicast, (long)pstats->collisions);
1270
1271 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1272 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1273 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1274 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1275 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1276 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1277
1278 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1279 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1280 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1281 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1282 DEBUG(2, " tx_window_errors=%ld\n",
1283 (long)pstats->tx_window_errors);
1284} /* pr_linux_stats */
1285
1286/* ----------------------------------------------------------------------------
1287pr_mace_stats
1288---------------------------------------------------------------------------- */
1289static void pr_mace_stats(mace_statistics *pstats)
1290{
1291 DEBUG(2, "pr_mace_stats\n");
1292
1293 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1294 pstats->xmtsv, pstats->uflo);
1295 DEBUG(2, " lcol=%-7d more=%d\n",
1296 pstats->lcol, pstats->more);
1297 DEBUG(2, " one=%-7d defer=%d\n",
1298 pstats->one, pstats->defer);
1299 DEBUG(2, " lcar=%-7d rtry=%d\n",
1300 pstats->lcar, pstats->rtry);
1301
1302 /* MACE_XMTRC */
1303 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1304 pstats->exdef, pstats->xmtrc);
1305
1306 /* RFS1--Receive Status (RCVSTS) */
1307 DEBUG(2, " oflo=%-7d clsn=%d\n",
1308 pstats->oflo, pstats->clsn);
1309 DEBUG(2, " fram=%-7d fcs=%d\n",
1310 pstats->fram, pstats->fcs);
1311
1312 /* RFS2--Runt Packet Count (RNTPC) */
1313 /* RFS3--Receive Collision Count (RCVCC) */
1314 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1315 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1316
1317 /* MACE_IR */
1318 DEBUG(2, " jab=%-7d babl=%d\n",
1319 pstats->jab, pstats->babl);
1320 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1321 pstats->cerr, pstats->rcvcco);
1322 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1323 pstats->rntpco, pstats->mpco);
1324
1325 /* MACE_MPC */
1326 DEBUG(2, " mpc=%d\n", pstats->mpc);
1327
1328 /* MACE_RNTPC */
1329 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1330
1331 /* MACE_RCVCC */
1332 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1333
1334} /* pr_mace_stats */
1335
1336/* ----------------------------------------------------------------------------
1337update_stats
1338 Update statistics. We change to register window 1, so this
1339 should be run single-threaded if the device is active. This is
1340 expected to be a rare operation, and it's simpler for the rest
1341 of the driver to assume that window 0 is always valid rather
1342 than use a special window-state variable.
1343
1344 oflo & uflo should _never_ occur since it would mean the Xilinx
1345 was not able to transfer data between the MACE FIFO and the
1346 card's SRAM fast enough. If this happens, something is
1347 seriously wrong with the hardware.
1348---------------------------------------------------------------------------- */
1349static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1350{
1351 mace_private *lp = netdev_priv(dev);
1352
1353 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1354 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1355 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1356 /* At this point, mace_stats is fully updated for this call.
1357 We may now update the linux_stats. */
1358
1359 /* The MACE has no equivalent for linux_stats field which are commented
1360 out. */
1361
1362 /* lp->linux_stats.multicast; */
1363 lp->linux_stats.collisions =
1364 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1365 /* Collision: The MACE may retry sending a packet 15 times
1366 before giving up. The retry count is in XMTRC.
1367 Does each retry constitute a collision?
1368 If so, why doesn't the RCVCC record these collisions? */
1369
1370 /* detailed rx_errors: */
1371 lp->linux_stats.rx_length_errors =
1372 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1373 /* lp->linux_stats.rx_over_errors */
1374 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1375 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1376 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1377 lp->linux_stats.rx_missed_errors =
1378 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1379
1380 /* detailed tx_errors */
1381 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1382 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1383 /* LCAR usually results from bad cabling. */
1384 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1385 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1386 /* lp->linux_stats.tx_window_errors; */
1387
1388 return;
1389} /* update_stats */
1390
1391/* ----------------------------------------------------------------------------
1392mace_get_stats
1393 Gathers ethernet statistics from the MACE chip.
1394---------------------------------------------------------------------------- */
1395static struct net_device_stats *mace_get_stats(struct net_device *dev)
1396{
1397 mace_private *lp = netdev_priv(dev);
1398
1399 update_stats(dev->base_addr, dev);
1400
1401 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1402 pr_linux_stats(&lp->linux_stats);
1403 pr_mace_stats(&lp->mace_stats);
1404
1405 return &lp->linux_stats;
1406} /* net_device_stats */
1407
1408/* ----------------------------------------------------------------------------
1409updateCRC
1410 Modified from Am79C90 data sheet.
1411---------------------------------------------------------------------------- */
1412
1413#ifdef BROKEN_MULTICAST
1414
1415static void updateCRC(int *CRC, int bit)
1416{
1417 int poly[]={
1418 1,1,1,0, 1,1,0,1,
1419 1,0,1,1, 1,0,0,0,
1420 1,0,0,0, 0,0,1,1,
1421 0,0,1,0, 0,0,0,0
1422 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1423 CRC generator polynomial. */
1424
1425 int j;
1426
1427 /* shift CRC and control bit (CRC[32]) */
1428 for (j = 32; j > 0; j--)
1429 CRC[j] = CRC[j-1];
1430 CRC[0] = 0;
1431
1432 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1433 if (bit ^ CRC[32])
1434 for (j = 0; j < 32; j++)
1435 CRC[j] ^= poly[j];
1436} /* updateCRC */
1437
1438/* ----------------------------------------------------------------------------
1439BuildLAF
1440 Build logical address filter.
1441 Modified from Am79C90 data sheet.
1442
1443Input
1444 ladrf: logical address filter (contents initialized to 0)
1445 adr: ethernet address
1446---------------------------------------------------------------------------- */
1447static void BuildLAF(int *ladrf, int *adr)
1448{
1449 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1450
1451 int i, byte; /* temporary array indices */
1452 int hashcode; /* the output object */
1453
1454 CRC[32]=0;
1455
1456 for (byte = 0; byte < 6; byte++)
1457 for (i = 0; i < 8; i++)
1458 updateCRC(CRC, (adr[byte] >> i) & 1);
1459
1460 hashcode = 0;
1461 for (i = 0; i < 6; i++)
1462 hashcode = (hashcode << 1) + CRC[i];
1463
1464 byte = hashcode >> 3;
1465 ladrf[byte] |= (1 << (hashcode & 7));
1466
1467#ifdef PCMCIA_DEBUG
1468 if (pc_debug > 2) {
1469 printk(KERN_DEBUG " adr =");
1470 for (i = 0; i < 6; i++)
1471 printk(" %02X", adr[i]);
1472 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1473 " =", hashcode);
1474 for (i = 0; i < 8; i++)
1475 printk(" %02X", ladrf[i]);
1476 printk("\n");
1477 }
1478#endif
1479} /* BuildLAF */
1480
1481/* ----------------------------------------------------------------------------
1482restore_multicast_list
1483 Restores the multicast filter for MACE chip to the last
1484 set_multicast_list() call.
1485
1486Input
1487 multicast_num_addrs
1488 multicast_ladrf[]
1489---------------------------------------------------------------------------- */
1490static void restore_multicast_list(struct net_device *dev)
1491{
1492 mace_private *lp = netdev_priv(dev);
1493 int num_addrs = lp->multicast_num_addrs;
1494 int *ladrf = lp->multicast_ladrf;
1495 kio_addr_t ioaddr = dev->base_addr;
1496 int i;
1497
1498 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1499 dev->name, num_addrs);
1500
1501 if (num_addrs > 0) {
1502
1503 DEBUG(1, "Attempt to restore multicast list detected.\n");
1504
1505 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1506 /* Poll ADDRCHG bit */
1507 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1508 ;
1509 /* Set LADRF register */
1510 for (i = 0; i < MACE_LADRF_LEN; i++)
1511 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1512
1513 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1514 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1515
1516 } else if (num_addrs < 0) {
1517
1518 /* Promiscuous mode: receive all packets */
1519 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1520 mace_write(lp, ioaddr, MACE_MACCC,
1521 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1522 );
1523
1524 } else {
1525
1526 /* Normal mode */
1527 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1528 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1529
1530 }
1531} /* restore_multicast_list */
1532
1533/* ----------------------------------------------------------------------------
1534set_multicast_list
1535 Set or clear the multicast filter for this adaptor.
1536
1537Input
1538 num_addrs == -1 Promiscuous mode, receive all packets
1539 num_addrs == 0 Normal mode, clear multicast list
1540 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1541 best-effort filtering.
1542Output
1543 multicast_num_addrs
1544 multicast_ladrf[]
1545---------------------------------------------------------------------------- */
1546
1547static void set_multicast_list(struct net_device *dev)
1548{
1549 mace_private *lp = netdev_priv(dev);
1550 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1551 int i;
1552 struct dev_mc_list *dmi = dev->mc_list;
1553
1554#ifdef PCMCIA_DEBUG
1555 if (pc_debug > 1) {
1556 static int old;
1557 if (dev->mc_count != old) {
1558 old = dev->mc_count;
1559 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1560 dev->name, old);
1561 }
1562 }
1563#endif
1564
1565 /* Set multicast_num_addrs. */
1566 lp->multicast_num_addrs = dev->mc_count;
1567
1568 /* Set multicast_ladrf. */
1569 if (num_addrs > 0) {
1570 /* Calculate multicast logical address filter */
1571 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1572 for (i = 0; i < dev->mc_count; i++) {
1573 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1574 dmi = dmi->next;
1575 BuildLAF(lp->multicast_ladrf, adr);
1576 }
1577 }
1578
1579 restore_multicast_list(dev);
1580
1581} /* set_multicast_list */
1582
1583#endif /* BROKEN_MULTICAST */
1584
1585static void restore_multicast_list(struct net_device *dev)
1586{
1587 kio_addr_t ioaddr = dev->base_addr;
1588 mace_private *lp = netdev_priv(dev);
1589
1590 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1591 lp->multicast_num_addrs);
1592
1593 if (dev->flags & IFF_PROMISC) {
1594 /* Promiscuous mode: receive all packets */
1595 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1596 mace_write(lp, ioaddr, MACE_MACCC,
1597 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1598 );
1599 } else {
1600 /* Normal mode */
1601 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1602 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1603 }
1604} /* restore_multicast_list */
1605
1606static void set_multicast_list(struct net_device *dev)
1607{
1608 mace_private *lp = netdev_priv(dev);
1609
1610#ifdef PCMCIA_DEBUG
1611 if (pc_debug > 1) {
1612 static int old;
1613 if (dev->mc_count != old) {
1614 old = dev->mc_count;
1615 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1616 dev->name, old);
1617 }
1618 }
1619#endif
1620
1621 lp->multicast_num_addrs = dev->mc_count;
1622 restore_multicast_list(dev);
1623
1624} /* set_multicast_list */
1625
a58e26cb
DB		 1626static struct pcmcia_device_id nmclan_ids[] = {
1627 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
d277ad0e 1628 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
a58e26cb
DB		 1629 PCMCIA_DEVICE_NULL,
1630};
1631MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1632
1da177e4
LT		 1633static struct pcmcia_driver nmclan_cs_driver = {
1634 .owner = THIS_MODULE,
1635 .drv = {
1636 .name = "nmclan_cs",
1637 },
f8cfa618 1638 .probe = nmclan_attach,
cc3b4866 1639 .remove = nmclan_detach,
a58e26cb 1640 .id_table = nmclan_ids,
98e4c28b
DB		 1641 .suspend = nmclan_suspend,
1642 .resume = nmclan_resume,
1da177e4
LT		 1643};
1644
1645static int __init init_nmclan_cs(void)
1646{
1647 return pcmcia_register_driver(&nmclan_cs_driver);
1648}
1649
1650static void __exit exit_nmclan_cs(void)
1651{
1652 pcmcia_unregister_driver(&nmclan_cs_driver);
1da177e4
LT		 1653}
1654
1655module_init(init_nmclan_cs);
1656module_exit(exit_nmclan_cs);
Clone of davem's net-next-2.6 tree