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1da177e4
LT		 1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
113aa838 72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
1da177e4
LT		 73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define DRV_NAME "nmclan_cs"
115#define DRV_VERSION "0.16"
116
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/init.h>
134#include <linux/ptrace.h>
135#include <linux/slab.h>
136#include <linux/string.h>
137#include <linux/timer.h>
138#include <linux/interrupt.h>
139#include <linux/in.h>
140#include <linux/delay.h>
141#include <linux/ethtool.h>
142#include <linux/netdevice.h>
143#include <linux/etherdevice.h>
144#include <linux/skbuff.h>
145#include <linux/if_arp.h>
146#include <linux/ioport.h>
147#include <linux/bitops.h>
148
1da177e4
LT		 149#include <pcmcia/cs_types.h>
150#include <pcmcia/cs.h>
151#include <pcmcia/cisreg.h>
152#include <pcmcia/cistpl.h>
153#include <pcmcia/ds.h>
154
155#include <asm/uaccess.h>
156#include <asm/io.h>
157#include <asm/system.h>
158
159/* ----------------------------------------------------------------------------
160Defines
161---------------------------------------------------------------------------- */
162
163#define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165#define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168/* Loop Control Defines */
169#define MACE_MAX_IR_ITERATIONS 10
170#define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180/*
181The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182which manages the interface between the MACE and the PCMCIA bus. It
183also includes buffer management for the 32K x 8 SRAM to control up to
184four transmit and 12 receive frames at a time.
185*/
186#define AM2150_MAX_TX_FRAMES 4
187#define AM2150_MAX_RX_FRAMES 12
188
189/* Am2150 Ethernet Card I/O Mapping */
190#define AM2150_RCV 0x00
191#define AM2150_XMT 0x04
192#define AM2150_XMT_SKIP 0x09
193#define AM2150_RCV_NEXT 0x0A
194#define AM2150_RCV_FRAME_COUNT 0x0B
195#define AM2150_MACE_BANK 0x0C
196#define AM2150_MACE_BASE 0x10
197
198/* MACE Registers */
199#define MACE_RCVFIFO 0
200#define MACE_XMTFIFO 1
201#define MACE_XMTFC 2
202#define MACE_XMTFS 3
203#define MACE_XMTRC 4
204#define MACE_RCVFC 5
205#define MACE_RCVFS 6
206#define MACE_FIFOFC 7
207#define MACE_IR 8
208#define MACE_IMR 9
209#define MACE_PR 10
210#define MACE_BIUCC 11
211#define MACE_FIFOCC 12
212#define MACE_MACCC 13
213#define MACE_PLSCC 14
214#define MACE_PHYCC 15
215#define MACE_CHIPIDL 16
216#define MACE_CHIPIDH 17
217#define MACE_IAC 18
218/* Reserved */
219#define MACE_LADRF 20
220#define MACE_PADR 21
221/* Reserved */
222/* Reserved */
223#define MACE_MPC 24
224/* Reserved */
225#define MACE_RNTPC 26
226#define MACE_RCVCC 27
227/* Reserved */
228#define MACE_UTR 29
229#define MACE_RTR1 30
230#define MACE_RTR2 31
231
232/* MACE Bit Masks */
233#define MACE_XMTRC_EXDEF 0x80
234#define MACE_XMTRC_XMTRC 0x0F
235
236#define MACE_XMTFS_XMTSV 0x80
237#define MACE_XMTFS_UFLO 0x40
238#define MACE_XMTFS_LCOL 0x20
239#define MACE_XMTFS_MORE 0x10
240#define MACE_XMTFS_ONE 0x08
241#define MACE_XMTFS_DEFER 0x04
242#define MACE_XMTFS_LCAR 0x02
243#define MACE_XMTFS_RTRY 0x01
244
245#define MACE_RCVFS_RCVSTS 0xF000
246#define MACE_RCVFS_OFLO 0x8000
247#define MACE_RCVFS_CLSN 0x4000
248#define MACE_RCVFS_FRAM 0x2000
249#define MACE_RCVFS_FCS 0x1000
250
251#define MACE_FIFOFC_RCVFC 0xF0
252#define MACE_FIFOFC_XMTFC 0x0F
253
254#define MACE_IR_JAB 0x80
255#define MACE_IR_BABL 0x40
256#define MACE_IR_CERR 0x20
257#define MACE_IR_RCVCCO 0x10
258#define MACE_IR_RNTPCO 0x08
259#define MACE_IR_MPCO 0x04
260#define MACE_IR_RCVINT 0x02
261#define MACE_IR_XMTINT 0x01
262
263#define MACE_MACCC_PROM 0x80
264#define MACE_MACCC_DXMT2PD 0x40
265#define MACE_MACCC_EMBA 0x20
266#define MACE_MACCC_RESERVED 0x10
267#define MACE_MACCC_DRCVPA 0x08
268#define MACE_MACCC_DRCVBC 0x04
269#define MACE_MACCC_ENXMT 0x02
270#define MACE_MACCC_ENRCV 0x01
271
272#define MACE_PHYCC_LNKFL 0x80
273#define MACE_PHYCC_DLNKTST 0x40
274#define MACE_PHYCC_REVPOL 0x20
275#define MACE_PHYCC_DAPC 0x10
276#define MACE_PHYCC_LRT 0x08
277#define MACE_PHYCC_ASEL 0x04
278#define MACE_PHYCC_RWAKE 0x02
279#define MACE_PHYCC_AWAKE 0x01
280
281#define MACE_IAC_ADDRCHG 0x80
282#define MACE_IAC_PHYADDR 0x04
283#define MACE_IAC_LOGADDR 0x02
284
285#define MACE_UTR_RTRE 0x80
286#define MACE_UTR_RTRD 0x40
287#define MACE_UTR_RPA 0x20
288#define MACE_UTR_FCOLL 0x10
289#define MACE_UTR_RCVFCSE 0x08
290#define MACE_UTR_LOOP_INCL_MENDEC 0x06
291#define MACE_UTR_LOOP_NO_MENDEC 0x04
292#define MACE_UTR_LOOP_EXTERNAL 0x02
293#define MACE_UTR_LOOP_NONE 0x00
294#define MACE_UTR_RESERVED 0x01
295
296/* Switch MACE register bank (only 0 and 1 are valid) */
297#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299#define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310#undef MACE_IMR_DEFAULT
311#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313#define TX_TIMEOUT ((400*HZ)/1000)
314
315/* ----------------------------------------------------------------------------
316Type Definitions
317---------------------------------------------------------------------------- */
318
319typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362} mace_statistics;
363
364typedef struct _mace_private {
fd238232 365 struct pcmcia_device *p_dev;
1da177e4
LT		 366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378} mace_private;
379
380/* ----------------------------------------------------------------------------
381Private Global Variables
382---------------------------------------------------------------------------- */
383
f71e1309 384static const char *if_names[]={
1da177e4
LT		 385 "Auto", "10baseT", "BNC",
386};
387
388/* ----------------------------------------------------------------------------
389Parameters
390 These are the parameters that can be set during loading with
391 'insmod'.
392---------------------------------------------------------------------------- */
393
394MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
395MODULE_LICENSE("GPL");
396
397#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
398
399/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
400INT_MODULE_PARM(if_port, 0);
401
1da177e4
LT		 402
403/* ----------------------------------------------------------------------------
404Function Prototypes
405---------------------------------------------------------------------------- */
406
15b99ac1 407static int nmclan_config(struct pcmcia_device *link);
fba395ee 408static void nmclan_release(struct pcmcia_device *link);
1da177e4
LT		 409
410static void nmclan_reset(struct net_device *dev);
411static int mace_config(struct net_device *dev, struct ifmap *map);
412static int mace_open(struct net_device *dev);
413static int mace_close(struct net_device *dev);
dbf02fae
SH		 414static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
415 struct net_device *dev);
1da177e4 416static void mace_tx_timeout(struct net_device *dev);
7d12e780 417static irqreturn_t mace_interrupt(int irq, void *dev_id);
1da177e4
LT		 418static struct net_device_stats *mace_get_stats(struct net_device *dev);
419static int mace_rx(struct net_device *dev, unsigned char RxCnt);
420static void restore_multicast_list(struct net_device *dev);
421static void set_multicast_list(struct net_device *dev);
7282d491 422static const struct ethtool_ops netdev_ethtool_ops;
1da177e4
LT		 423
424
cc3b4866 425static void nmclan_detach(struct pcmcia_device *p_dev);
1da177e4 426
28b1801d
SH		 427static const struct net_device_ops mace_netdev_ops = {
428 .ndo_open = mace_open,
429 .ndo_stop = mace_close,
430 .ndo_start_xmit = mace_start_xmit,
431 .ndo_tx_timeout = mace_tx_timeout,
432 .ndo_set_config = mace_config,
433 .ndo_get_stats = mace_get_stats,
434 .ndo_set_multicast_list = set_multicast_list,
435 .ndo_change_mtu = eth_change_mtu,
436 .ndo_set_mac_address = eth_mac_addr,
437 .ndo_validate_addr = eth_validate_addr,
438};
439
1da177e4
LT		 440/* ----------------------------------------------------------------------------
441nmclan_attach
442 Creates an "instance" of the driver, allocating local data
443 structures for one device. The device is registered with Card
444 Services.
445---------------------------------------------------------------------------- */
446
15b99ac1 447static int nmclan_probe(struct pcmcia_device *link)
1da177e4
LT		 448{
449 mace_private *lp;
1da177e4 450 struct net_device *dev;
1da177e4 451
dd0fab5b 452 dev_dbg(&link->dev, "nmclan_attach()\n");
1da177e4
LT		 453
454 /* Create new ethernet device */
455 dev = alloc_etherdev(sizeof(mace_private));
456 if (!dev)
f8cfa618 457 return -ENOMEM;
1da177e4 458 lp = netdev_priv(dev);
fba395ee 459 lp->p_dev = link;
1da177e4
LT		 460 link->priv = dev;
461
462 spin_lock_init(&lp->bank_lock);
463 link->io.NumPorts1 = 32;
464 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
465 link->io.IOAddrLines = 5;
1da177e4 466 link->conf.Attributes = CONF_ENABLE_IRQ;
1da177e4
LT		 467 link->conf.IntType = INT_MEMORY_AND_IO;
468 link->conf.ConfigIndex = 1;
469 link->conf.Present = PRESENT_OPTION;
470
471 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
472
28b1801d 473 dev->netdev_ops = &mace_netdev_ops;
1da177e4 474 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
1da177e4 475 dev->watchdog_timeo = TX_TIMEOUT;
1da177e4 476
15b99ac1 477 return nmclan_config(link);
1da177e4
LT		 478} /* nmclan_attach */
479
480/* ----------------------------------------------------------------------------
481nmclan_detach
482 This deletes a driver "instance". The device is de-registered
483 with Card Services. If it has been released, all local data
484 structures are freed. Otherwise, the structures will be freed
485 when the device is released.
486---------------------------------------------------------------------------- */
487
fba395ee 488static void nmclan_detach(struct pcmcia_device *link)
1da177e4
LT		 489{
490 struct net_device *dev = link->priv;
1da177e4 491
dd0fab5b 492 dev_dbg(&link->dev, "nmclan_detach\n");
1da177e4 493
fd238232 494 if (link->dev_node)
1da177e4
LT		 495 unregister_netdev(dev);
496
e2d40963 497 nmclan_release(link);
1da177e4 498
1da177e4
LT		 499 free_netdev(dev);
500} /* nmclan_detach */
501
502/* ----------------------------------------------------------------------------
503mace_read
504 Reads a MACE register. This is bank independent; however, the
505 caller must ensure that this call is not interruptable. We are
506 assuming that during normal operation, the MACE is always in
507 bank 0.
508---------------------------------------------------------------------------- */
906da809 509static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
1da177e4
LT		 510{
511 int data = 0xFF;
512 unsigned long flags;
513
514 switch (reg >> 4) {
515 case 0: /* register 0-15 */
516 data = inb(ioaddr + AM2150_MACE_BASE + reg);
517 break;
518 case 1: /* register 16-31 */
519 spin_lock_irqsave(&lp->bank_lock, flags);
520 MACEBANK(1);
521 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
522 MACEBANK(0);
523 spin_unlock_irqrestore(&lp->bank_lock, flags);
524 break;
525 }
526 return (data & 0xFF);
527} /* mace_read */
528
529/* ----------------------------------------------------------------------------
530mace_write
531 Writes to a MACE register. This is bank independent; however,
532 the caller must ensure that this call is not interruptable. We
533 are assuming that during normal operation, the MACE is always in
534 bank 0.
535---------------------------------------------------------------------------- */
906da809
OJ		 536static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
537 int data)
1da177e4
LT		 538{
539 unsigned long flags;
540
541 switch (reg >> 4) {
542 case 0: /* register 0-15 */
543 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
544 break;
545 case 1: /* register 16-31 */
546 spin_lock_irqsave(&lp->bank_lock, flags);
547 MACEBANK(1);
548 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
549 MACEBANK(0);
550 spin_unlock_irqrestore(&lp->bank_lock, flags);
551 break;
552 }
553} /* mace_write */
554
555/* ----------------------------------------------------------------------------
556mace_init
557 Resets the MACE chip.
558---------------------------------------------------------------------------- */
906da809 559static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
1da177e4
LT		 560{
561 int i;
562 int ct = 0;
563
564 /* MACE Software reset */
565 mace_write(lp, ioaddr, MACE_BIUCC, 1);
566 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
567 /* Wait for reset bit to be cleared automatically after <= 200ns */;
568 if(++ct > 500)
569 {
570 printk(KERN_ERR "mace: reset failed, card removed ?\n");
571 return -1;
572 }
573 udelay(1);
574 }
575 mace_write(lp, ioaddr, MACE_BIUCC, 0);
576
577 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
578 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
579
580 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
581 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
582
583 /*
584 * Bit 2-1 PORTSEL[1-0] Port Select.
585 * 00 AUI/10Base-2
586 * 01 10Base-T
587 * 10 DAI Port (reserved in Am2150)
588 * 11 GPSI
589 * For this card, only the first two are valid.
590 * So, PLSCC should be set to
591 * 0x00 for 10Base-2
592 * 0x02 for 10Base-T
593 * Or just set ASEL in PHYCC below!
594 */
595 switch (if_port) {
596 case 1:
597 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
598 break;
599 case 2:
600 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
601 break;
602 default:
603 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
604 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
605 and the MACE device will automatically select the operating media
606 interface port. */
607 break;
608 }
609
610 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
611 /* Poll ADDRCHG bit */
612 ct = 0;
613 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
614 {
615 if(++ ct > 500)
616 {
617 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
618 return -1;
619 }
620 }
621 /* Set PADR register */
622 for (i = 0; i < ETHER_ADDR_LEN; i++)
623 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
624
625 /* MAC Configuration Control Register should be written last */
626 /* Let set_multicast_list set this. */
627 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
628 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
629 return 0;
630} /* mace_init */
631
632/* ----------------------------------------------------------------------------
633nmclan_config
634 This routine is scheduled to run after a CARD_INSERTION event
635 is received, to configure the PCMCIA socket, and to make the
636 ethernet device available to the system.
637---------------------------------------------------------------------------- */
638
15b99ac1 639static int nmclan_config(struct pcmcia_device *link)
1da177e4 640{
1da177e4
LT		 641 struct net_device *dev = link->priv;
642 mace_private *lp = netdev_priv(dev);
dddfbd82
DB		 643 u8 *buf;
644 size_t len;
dd0fab5b 645 int i, ret;
906da809 646 unsigned int ioaddr;
1da177e4 647
dd0fab5b
DB		 648 dev_dbg(&link->dev, "nmclan_config\n");
649
650 ret = pcmcia_request_io(link, &link->io);
651 if (ret)
652 goto failed;
eb14120f 653 ret = pcmcia_request_exclusive_irq(link, mace_interrupt);
dd0fab5b
DB		 654 if (ret)
655 goto failed;
656 ret = pcmcia_request_configuration(link, &link->conf);
657 if (ret)
658 goto failed;
1da177e4 659
eb14120f 660 dev->irq = link->irq;
1da177e4
LT		 661 dev->base_addr = link->io.BasePort1;
662
663 ioaddr = dev->base_addr;
664
665 /* Read the ethernet address from the CIS. */
dddfbd82
DB		 666 len = pcmcia_get_tuple(link, 0x80, &buf);
667 if (!buf || len < ETHER_ADDR_LEN) {
668 kfree(buf);
669 goto failed;
670 }
671 memcpy(dev->dev_addr, buf, ETHER_ADDR_LEN);
672 kfree(buf);
1da177e4
LT		 673
674 /* Verify configuration by reading the MACE ID. */
675 {
676 char sig[2];
677
678 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
679 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
680 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
dd0fab5b 681 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
1da177e4
LT		 682 sig[0], sig[1]);
683 } else {
684 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
685 " be 0x40 0x?9\n", sig[0], sig[1]);
15b99ac1 686 return -ENODEV;
1da177e4
LT		 687 }
688 }
689
690 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
691 goto failed;
692
693 /* The if_port symbol can be set when the module is loaded */
694 if (if_port <= 2)
695 dev->if_port = if_port;
696 else
697 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
698
fd238232 699 link->dev_node = &lp->node;
dd2e5a15 700 SET_NETDEV_DEV(dev, &link->dev);
1da177e4
LT		 701
702 i = register_netdev(dev);
703 if (i != 0) {
704 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
fd238232 705 link->dev_node = NULL;
1da177e4
LT		 706 goto failed;
707 }
708
709 strcpy(lp->node.dev_name, dev->name);
710
0795af57 711 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port,"
e174961c 712 " hw_addr %pM\n",
0795af57 713 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port],
e174961c 714 dev->dev_addr);
15b99ac1 715 return 0;
1da177e4 716
1da177e4 717failed:
15b99ac1
DB		 718 nmclan_release(link);
719 return -ENODEV;
1da177e4
LT		 720} /* nmclan_config */
721
722/* ----------------------------------------------------------------------------
723nmclan_release
724 After a card is removed, nmclan_release() will unregister the
725 net device, and release the PCMCIA configuration. If the device
726 is still open, this will be postponed until it is closed.
727---------------------------------------------------------------------------- */
fba395ee 728static void nmclan_release(struct pcmcia_device *link)
1da177e4 729{
dd0fab5b 730 dev_dbg(&link->dev, "nmclan_release\n");
fba395ee 731 pcmcia_disable_device(link);
1da177e4
LT		 732}
733
fba395ee 734static int nmclan_suspend(struct pcmcia_device *link)
98e4c28b 735{
98e4c28b
DB		 736 struct net_device *dev = link->priv;
737
e2d40963 738 if (link->open)
8661bb5b 739 netif_device_detach(dev);
98e4c28b
DB		 740
741 return 0;
742}
743
fba395ee 744static int nmclan_resume(struct pcmcia_device *link)
98e4c28b 745{
98e4c28b
DB		 746 struct net_device *dev = link->priv;
747
e2d40963 748 if (link->open) {
8661bb5b
DB		 749 nmclan_reset(dev);
750 netif_device_attach(dev);
98e4c28b
DB		 751 }
752
753 return 0;
754}
755
1da177e4
LT		 756
757/* ----------------------------------------------------------------------------
758nmclan_reset
759 Reset and restore all of the Xilinx and MACE registers.
760---------------------------------------------------------------------------- */
761static void nmclan_reset(struct net_device *dev)
762{
763 mace_private *lp = netdev_priv(dev);
764
765#if RESET_XILINX
fba395ee 766 struct pcmcia_device *link = &lp->link;
1da177e4
LT		 767 conf_reg_t reg;
768 u_long OrigCorValue;
769
770 /* Save original COR value */
771 reg.Function = 0;
772 reg.Action = CS_READ;
773 reg.Offset = CISREG_COR;
774 reg.Value = 0;
fba395ee 775 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 776 OrigCorValue = reg.Value;
777
778 /* Reset Xilinx */
779 reg.Action = CS_WRITE;
780 reg.Offset = CISREG_COR;
dd0fab5b 781 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
1da177e4
LT		 782 OrigCorValue);
783 reg.Value = COR_SOFT_RESET;
fba395ee 784 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 785 /* Need to wait for 20 ms for PCMCIA to finish reset. */
786
787 /* Restore original COR configuration index */
788 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
fba395ee 789 pcmcia_access_configuration_register(link, &reg);
1da177e4
LT		 790 /* Xilinx is now completely reset along with the MACE chip. */
791 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
792
793#endif /* #if RESET_XILINX */
794
795 /* Xilinx is now completely reset along with the MACE chip. */
796 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
797
798 /* Reinitialize the MACE chip for operation. */
799 mace_init(lp, dev->base_addr, dev->dev_addr);
800 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
801
802 /* Restore the multicast list and enable TX and RX. */
803 restore_multicast_list(dev);
804} /* nmclan_reset */
805
806/* ----------------------------------------------------------------------------
807mace_config
808 [Someone tell me what this is supposed to do? Is if_port a defined
809 standard? If so, there should be defines to indicate 1=10Base-T,
810 2=10Base-2, etc. including limited automatic detection.]
811---------------------------------------------------------------------------- */
812static int mace_config(struct net_device *dev, struct ifmap *map)
813{
814 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
815 if (map->port <= 2) {
816 dev->if_port = map->port;
817 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
818 if_names[dev->if_port]);
819 } else
820 return -EINVAL;
821 }
822 return 0;
823} /* mace_config */
824
825/* ----------------------------------------------------------------------------
826mace_open
827 Open device driver.
828---------------------------------------------------------------------------- */
829static int mace_open(struct net_device *dev)
830{
906da809 831 unsigned int ioaddr = dev->base_addr;
1da177e4 832 mace_private *lp = netdev_priv(dev);
fba395ee 833 struct pcmcia_device *link = lp->p_dev;
1da177e4 834
9940ec36 835 if (!pcmcia_dev_present(link))
1da177e4
LT		 836 return -ENODEV;
837
838 link->open++;
839
840 MACEBANK(0);
841
842 netif_start_queue(dev);
843 nmclan_reset(dev);
844
845 return 0; /* Always succeed */
846} /* mace_open */
847
848/* ----------------------------------------------------------------------------
849mace_close
850 Closes device driver.
851---------------------------------------------------------------------------- */
852static int mace_close(struct net_device *dev)
853{
906da809 854 unsigned int ioaddr = dev->base_addr;
1da177e4 855 mace_private *lp = netdev_priv(dev);
fba395ee 856 struct pcmcia_device *link = lp->p_dev;
1da177e4 857
dd0fab5b 858 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
1da177e4
LT		 859
860 /* Mask off all interrupts from the MACE chip. */
861 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
862
863 link->open--;
864 netif_stop_queue(dev);
865
866 return 0;
867} /* mace_close */
868
869static void netdev_get_drvinfo(struct net_device *dev,
870 struct ethtool_drvinfo *info)
871{
872 strcpy(info->driver, DRV_NAME);
873 strcpy(info->version, DRV_VERSION);
874 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
875}
876
7282d491 877static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4 878 .get_drvinfo = netdev_get_drvinfo,
1da177e4
LT		 879};
880
881/* ----------------------------------------------------------------------------
882mace_start_xmit
883 This routine begins the packet transmit function. When completed,
884 it will generate a transmit interrupt.
885
886 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
887 returns 0, the "packet is now solely the responsibility of the
888 driver." If _start_xmit returns non-zero, the "transmission
889 failed, put skb back into a list."
890---------------------------------------------------------------------------- */
891
892static void mace_tx_timeout(struct net_device *dev)
893{
894 mace_private *lp = netdev_priv(dev);
fba395ee 895 struct pcmcia_device *link = lp->p_dev;
1da177e4
LT		 896
897 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
898#if RESET_ON_TIMEOUT
899 printk("resetting card\n");
994917f8 900 pcmcia_reset_card(link->socket);
1da177e4
LT		 901#else /* #if RESET_ON_TIMEOUT */
902 printk("NOT resetting card\n");
903#endif /* #if RESET_ON_TIMEOUT */
904 dev->trans_start = jiffies;
905 netif_wake_queue(dev);
906}
907
dbf02fae
SH		 908static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
909 struct net_device *dev)
1da177e4
LT		 910{
911 mace_private *lp = netdev_priv(dev);
906da809 912 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 913
914 netif_stop_queue(dev);
915
dd0fab5b 916 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
1da177e4
LT		 917 dev->name, (long)skb->len);
918
919#if (!TX_INTERRUPTABLE)
920 /* Disable MACE TX interrupts. */
921 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
922 ioaddr + AM2150_MACE_BASE + MACE_IMR);
923 lp->tx_irq_disabled=1;
924#endif /* #if (!TX_INTERRUPTABLE) */
925
926 {
927 /* This block must not be interrupted by another transmit request!
928 mace_tx_timeout will take care of timer-based retransmissions from
929 the upper layers. The interrupt handler is guaranteed never to
930 service a transmit interrupt while we are in here.
931 */
932
933 lp->linux_stats.tx_bytes += skb->len;
934 lp->tx_free_frames--;
935
936 /* WARNING: Write the _exact_ number of bytes written in the header! */
937 /* Put out the word header [must be an outw()] . . . */
938 outw(skb->len, ioaddr + AM2150_XMT);
939 /* . . . and the packet [may be any combination of outw() and outb()] */
940 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
941 if (skb->len & 1) {
942 /* Odd byte transfer */
943 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
944 }
945
946 dev->trans_start = jiffies;
947
948#if MULTI_TX
949 if (lp->tx_free_frames > 0)
950 netif_start_queue(dev);
951#endif /* #if MULTI_TX */
952 }
953
954#if (!TX_INTERRUPTABLE)
955 /* Re-enable MACE TX interrupts. */
956 lp->tx_irq_disabled=0;
957 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
958#endif /* #if (!TX_INTERRUPTABLE) */
959
960 dev_kfree_skb(skb);
961
6ed10654 962 return NETDEV_TX_OK;
1da177e4
LT		 963} /* mace_start_xmit */
964
965/* ----------------------------------------------------------------------------
966mace_interrupt
967 The interrupt handler.
968---------------------------------------------------------------------------- */
7d12e780 969static irqreturn_t mace_interrupt(int irq, void *dev_id)
1da177e4
LT		 970{
971 struct net_device *dev = (struct net_device *) dev_id;
972 mace_private *lp = netdev_priv(dev);
906da809 973 unsigned int ioaddr;
1da177e4
LT		 974 int status;
975 int IntrCnt = MACE_MAX_IR_ITERATIONS;
976
977 if (dev == NULL) {
dd0fab5b 978 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
1da177e4
LT		 979 irq);
980 return IRQ_NONE;
981 }
982
c196d80f
MG		 983 ioaddr = dev->base_addr;
984
1da177e4
LT		 985 if (lp->tx_irq_disabled) {
986 printk(
987 (lp->tx_irq_disabled?
988 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
989 "[isr=%02X, imr=%02X]\n":
990 KERN_NOTICE "%s: Re-entering the interrupt handler "
991 "[isr=%02X, imr=%02X]\n"),
992 dev->name,
993 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
994 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
995 );
996 /* WARNING: MACE_IR has been read! */
997 return IRQ_NONE;
998 }
999
1000 if (!netif_device_present(dev)) {
dd0fab5b 1001 pr_debug("%s: interrupt from dead card\n", dev->name);
1da177e4
LT		 1002 return IRQ_NONE;
1003 }
1004
1005 do {
1006 /* WARNING: MACE_IR is a READ/CLEAR port! */
1007 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1008
dd0fab5b 1009 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1da177e4
LT		 1010
1011 if (status & MACE_IR_RCVINT) {
1012 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1013 }
1014
1015 if (status & MACE_IR_XMTINT) {
1016 unsigned char fifofc;
1017 unsigned char xmtrc;
1018 unsigned char xmtfs;
1019
1020 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1021 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1022 lp->linux_stats.tx_errors++;
1023 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1024 }
1025
1026 /* Transmit Retry Count (XMTRC, reg 4) */
1027 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1028 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1029 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1030
1031 if (
1032 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1033 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1034 ) {
1035 lp->mace_stats.xmtsv++;
1036
1037 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1038 if (xmtfs & MACE_XMTFS_UFLO) {
1039 /* Underflow. Indicates that the Transmit FIFO emptied before
1040 the end of frame was reached. */
1041 lp->mace_stats.uflo++;
1042 }
1043 if (xmtfs & MACE_XMTFS_LCOL) {
1044 /* Late Collision */
1045 lp->mace_stats.lcol++;
1046 }
1047 if (xmtfs & MACE_XMTFS_MORE) {
1048 /* MORE than one retry was needed */
1049 lp->mace_stats.more++;
1050 }
1051 if (xmtfs & MACE_XMTFS_ONE) {
1052 /* Exactly ONE retry occurred */
1053 lp->mace_stats.one++;
1054 }
1055 if (xmtfs & MACE_XMTFS_DEFER) {
1056 /* Transmission was defered */
1057 lp->mace_stats.defer++;
1058 }
1059 if (xmtfs & MACE_XMTFS_LCAR) {
1060 /* Loss of carrier */
1061 lp->mace_stats.lcar++;
1062 }
1063 if (xmtfs & MACE_XMTFS_RTRY) {
1064 /* Retry error: transmit aborted after 16 attempts */
1065 lp->mace_stats.rtry++;
1066 }
1067 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1068
1069 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1070
1071 lp->linux_stats.tx_packets++;
1072 lp->tx_free_frames++;
1073 netif_wake_queue(dev);
1074 } /* if (status & MACE_IR_XMTINT) */
1075
1076 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1077 if (status & MACE_IR_JAB) {
1078 /* Jabber Error. Excessive transmit duration (20-150ms). */
1079 lp->mace_stats.jab++;
1080 }
1081 if (status & MACE_IR_BABL) {
1082 /* Babble Error. >1518 bytes transmitted. */
1083 lp->mace_stats.babl++;
1084 }
1085 if (status & MACE_IR_CERR) {
1086 /* Collision Error. CERR indicates the absence of the
1087 Signal Quality Error Test message after a packet
1088 transmission. */
1089 lp->mace_stats.cerr++;
1090 }
1091 if (status & MACE_IR_RCVCCO) {
1092 /* Receive Collision Count Overflow; */
1093 lp->mace_stats.rcvcco++;
1094 }
1095 if (status & MACE_IR_RNTPCO) {
1096 /* Runt Packet Count Overflow */
1097 lp->mace_stats.rntpco++;
1098 }
1099 if (status & MACE_IR_MPCO) {
1100 /* Missed Packet Count Overflow */
1101 lp->mace_stats.mpco++;
1102 }
1103 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1104
1105 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1106
1107 return IRQ_HANDLED;
1108} /* mace_interrupt */
1109
1110/* ----------------------------------------------------------------------------
1111mace_rx
1112 Receives packets.
1113---------------------------------------------------------------------------- */
1114static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1115{
1116 mace_private *lp = netdev_priv(dev);
906da809 1117 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1118 unsigned char rx_framecnt;
1119 unsigned short rx_status;
1120
1121 while (
1122 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1123 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1124 (RxCnt--)
1125 ) {
1126 rx_status = inw(ioaddr + AM2150_RCV);
1127
dd0fab5b 1128 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1da177e4
LT		 1129 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1130
1131 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1132 lp->linux_stats.rx_errors++;
1133 if (rx_status & MACE_RCVFS_OFLO) {
1134 lp->mace_stats.oflo++;
1135 }
1136 if (rx_status & MACE_RCVFS_CLSN) {
1137 lp->mace_stats.clsn++;
1138 }
1139 if (rx_status & MACE_RCVFS_FRAM) {
1140 lp->mace_stats.fram++;
1141 }
1142 if (rx_status & MACE_RCVFS_FCS) {
1143 lp->mace_stats.fcs++;
1144 }
1145 } else {
1146 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1147 /* Auto Strip is off, always subtract 4 */
1148 struct sk_buff *skb;
1149
1150 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1151 /* runt packet count */
1152 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1153 /* rcv collision count */
1154
dd0fab5b 1155 pr_debug(" receiving packet size 0x%X rx_status"
1da177e4
LT		 1156 " 0x%X.\n", pkt_len, rx_status);
1157
1158 skb = dev_alloc_skb(pkt_len+2);
1159
1160 if (skb != NULL) {
1da177e4
LT		 1161 skb_reserve(skb, 2);
1162 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1163 if (pkt_len & 1)
27a884dc 1164 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1da177e4
LT		 1165 skb->protocol = eth_type_trans(skb, dev);
1166
1167 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1168
1da177e4 1169 lp->linux_stats.rx_packets++;
6f258910 1170 lp->linux_stats.rx_bytes += pkt_len;
1da177e4
LT		 1171 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1172 continue;
1173 } else {
dd0fab5b 1174 pr_debug("%s: couldn't allocate a sk_buff of size"
1da177e4
LT		 1175 " %d.\n", dev->name, pkt_len);
1176 lp->linux_stats.rx_dropped++;
1177 }
1178 }
1179 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1180 } /* while */
1181
1182 return 0;
1183} /* mace_rx */
1184
1185/* ----------------------------------------------------------------------------
1186pr_linux_stats
1187---------------------------------------------------------------------------- */
1188static void pr_linux_stats(struct net_device_stats *pstats)
1189{
dd0fab5b
DB		 1190 pr_debug("pr_linux_stats\n");
1191 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1da177e4 1192 (long)pstats->rx_packets, (long)pstats->tx_packets);
dd0fab5b 1193 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1da177e4 1194 (long)pstats->rx_errors, (long)pstats->tx_errors);
dd0fab5b 1195 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1da177e4 1196 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
dd0fab5b 1197 pr_debug(" multicast=%-7ld collisions=%ld\n",
1da177e4
LT		 1198 (long)pstats->multicast, (long)pstats->collisions);
1199
dd0fab5b 1200 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1da177e4 1201 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
dd0fab5b 1202 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1da177e4 1203 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
dd0fab5b 1204 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1da177e4
LT		 1205 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1206
dd0fab5b 1207 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1da177e4 1208 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
dd0fab5b 1209 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1da177e4 1210 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
dd0fab5b 1211 pr_debug(" tx_window_errors=%ld\n",
1da177e4
LT		 1212 (long)pstats->tx_window_errors);
1213} /* pr_linux_stats */
1214
1215/* ----------------------------------------------------------------------------
1216pr_mace_stats
1217---------------------------------------------------------------------------- */
1218static void pr_mace_stats(mace_statistics *pstats)
1219{
dd0fab5b 1220 pr_debug("pr_mace_stats\n");
1da177e4 1221
dd0fab5b 1222 pr_debug(" xmtsv=%-7d uflo=%d\n",
1da177e4 1223 pstats->xmtsv, pstats->uflo);
dd0fab5b 1224 pr_debug(" lcol=%-7d more=%d\n",
1da177e4 1225 pstats->lcol, pstats->more);
dd0fab5b 1226 pr_debug(" one=%-7d defer=%d\n",
1da177e4 1227 pstats->one, pstats->defer);
dd0fab5b 1228 pr_debug(" lcar=%-7d rtry=%d\n",
1da177e4
LT		 1229 pstats->lcar, pstats->rtry);
1230
1231 /* MACE_XMTRC */
dd0fab5b 1232 pr_debug(" exdef=%-7d xmtrc=%d\n",
1da177e4
LT		 1233 pstats->exdef, pstats->xmtrc);
1234
1235 /* RFS1--Receive Status (RCVSTS) */
dd0fab5b 1236 pr_debug(" oflo=%-7d clsn=%d\n",
1da177e4 1237 pstats->oflo, pstats->clsn);
dd0fab5b 1238 pr_debug(" fram=%-7d fcs=%d\n",
1da177e4
LT		 1239 pstats->fram, pstats->fcs);
1240
1241 /* RFS2--Runt Packet Count (RNTPC) */
1242 /* RFS3--Receive Collision Count (RCVCC) */
dd0fab5b 1243 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1da177e4
LT		 1244 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1245
1246 /* MACE_IR */
dd0fab5b 1247 pr_debug(" jab=%-7d babl=%d\n",
1da177e4 1248 pstats->jab, pstats->babl);
dd0fab5b 1249 pr_debug(" cerr=%-7d rcvcco=%d\n",
1da177e4 1250 pstats->cerr, pstats->rcvcco);
dd0fab5b 1251 pr_debug(" rntpco=%-7d mpco=%d\n",
1da177e4
LT		 1252 pstats->rntpco, pstats->mpco);
1253
1254 /* MACE_MPC */
dd0fab5b 1255 pr_debug(" mpc=%d\n", pstats->mpc);
1da177e4
LT		 1256
1257 /* MACE_RNTPC */
dd0fab5b 1258 pr_debug(" rntpc=%d\n", pstats->rntpc);
1da177e4
LT		 1259
1260 /* MACE_RCVCC */
dd0fab5b 1261 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1da177e4
LT		 1262
1263} /* pr_mace_stats */
1264
1265/* ----------------------------------------------------------------------------
1266update_stats
1267 Update statistics. We change to register window 1, so this
1268 should be run single-threaded if the device is active. This is
1269 expected to be a rare operation, and it's simpler for the rest
1270 of the driver to assume that window 0 is always valid rather
1271 than use a special window-state variable.
1272
1273 oflo & uflo should _never_ occur since it would mean the Xilinx
1274 was not able to transfer data between the MACE FIFO and the
1275 card's SRAM fast enough. If this happens, something is
1276 seriously wrong with the hardware.
1277---------------------------------------------------------------------------- */
906da809 1278static void update_stats(unsigned int ioaddr, struct net_device *dev)
1da177e4
LT		 1279{
1280 mace_private *lp = netdev_priv(dev);
1281
1282 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1283 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1284 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1285 /* At this point, mace_stats is fully updated for this call.
1286 We may now update the linux_stats. */
1287
1288 /* The MACE has no equivalent for linux_stats field which are commented
1289 out. */
1290
1291 /* lp->linux_stats.multicast; */
1292 lp->linux_stats.collisions =
1293 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1294 /* Collision: The MACE may retry sending a packet 15 times
1295 before giving up. The retry count is in XMTRC.
1296 Does each retry constitute a collision?
1297 If so, why doesn't the RCVCC record these collisions? */
1298
1299 /* detailed rx_errors: */
1300 lp->linux_stats.rx_length_errors =
1301 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1302 /* lp->linux_stats.rx_over_errors */
1303 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1304 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1305 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1306 lp->linux_stats.rx_missed_errors =
1307 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1308
1309 /* detailed tx_errors */
1310 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1311 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1312 /* LCAR usually results from bad cabling. */
1313 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1314 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1315 /* lp->linux_stats.tx_window_errors; */
1316
1317 return;
1318} /* update_stats */
1319
1320/* ----------------------------------------------------------------------------
1321mace_get_stats
1322 Gathers ethernet statistics from the MACE chip.
1323---------------------------------------------------------------------------- */
1324static struct net_device_stats *mace_get_stats(struct net_device *dev)
1325{
1326 mace_private *lp = netdev_priv(dev);
1327
1328 update_stats(dev->base_addr, dev);
1329
dd0fab5b 1330 pr_debug("%s: updating the statistics.\n", dev->name);
1da177e4
LT		 1331 pr_linux_stats(&lp->linux_stats);
1332 pr_mace_stats(&lp->mace_stats);
1333
1334 return &lp->linux_stats;
1335} /* net_device_stats */
1336
1337/* ----------------------------------------------------------------------------
1338updateCRC
1339 Modified from Am79C90 data sheet.
1340---------------------------------------------------------------------------- */
1341
1342#ifdef BROKEN_MULTICAST
1343
1344static void updateCRC(int *CRC, int bit)
1345{
1346 int poly[]={
1347 1,1,1,0, 1,1,0,1,
1348 1,0,1,1, 1,0,0,0,
1349 1,0,0,0, 0,0,1,1,
1350 0,0,1,0, 0,0,0,0
1351 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1352 CRC generator polynomial. */
1353
1354 int j;
1355
1356 /* shift CRC and control bit (CRC[32]) */
1357 for (j = 32; j > 0; j--)
1358 CRC[j] = CRC[j-1];
1359 CRC[0] = 0;
1360
1361 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1362 if (bit ^ CRC[32])
1363 for (j = 0; j < 32; j++)
1364 CRC[j] ^= poly[j];
1365} /* updateCRC */
1366
1367/* ----------------------------------------------------------------------------
1368BuildLAF
1369 Build logical address filter.
1370 Modified from Am79C90 data sheet.
1371
1372Input
1373 ladrf: logical address filter (contents initialized to 0)
1374 adr: ethernet address
1375---------------------------------------------------------------------------- */
1376static void BuildLAF(int *ladrf, int *adr)
1377{
1378 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1379
1380 int i, byte; /* temporary array indices */
1381 int hashcode; /* the output object */
1382
1383 CRC[32]=0;
1384
1385 for (byte = 0; byte < 6; byte++)
1386 for (i = 0; i < 8; i++)
1387 updateCRC(CRC, (adr[byte] >> i) & 1);
1388
1389 hashcode = 0;
1390 for (i = 0; i < 6; i++)
1391 hashcode = (hashcode << 1) + CRC[i];
1392
1393 byte = hashcode >> 3;
1394 ladrf[byte] |= (1 << (hashcode & 7));
1395
1396#ifdef PCMCIA_DEBUG
dd0fab5b 1397 if (0)
ad361c98
JP		 1398 printk(KERN_DEBUG " adr =%pM\n", adr);
1399 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1400 for (i = 0; i < 8; i++)
1401 printk(KERN_CONT " %02X", ladrf[i]);
1402 printk(KERN_CONT "\n");
1da177e4
LT		 1403#endif
1404} /* BuildLAF */
1405
1406/* ----------------------------------------------------------------------------
1407restore_multicast_list
1408 Restores the multicast filter for MACE chip to the last
1409 set_multicast_list() call.
1410
1411Input
1412 multicast_num_addrs
1413 multicast_ladrf[]
1414---------------------------------------------------------------------------- */
1415static void restore_multicast_list(struct net_device *dev)
1416{
1417 mace_private *lp = netdev_priv(dev);
1418 int num_addrs = lp->multicast_num_addrs;
1419 int *ladrf = lp->multicast_ladrf;
906da809 1420 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1421 int i;
1422
dd0fab5b 1423 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1da177e4
LT		 1424 dev->name, num_addrs);
1425
1426 if (num_addrs > 0) {
1427
dd0fab5b 1428 pr_debug("Attempt to restore multicast list detected.\n");
1da177e4
LT		 1429
1430 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1431 /* Poll ADDRCHG bit */
1432 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1433 ;
1434 /* Set LADRF register */
1435 for (i = 0; i < MACE_LADRF_LEN; i++)
1436 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1437
1438 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1439 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1440
1441 } else if (num_addrs < 0) {
1442
1443 /* Promiscuous mode: receive all packets */
1444 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1445 mace_write(lp, ioaddr, MACE_MACCC,
1446 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1447 );
1448
1449 } else {
1450
1451 /* Normal mode */
1452 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1453 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1454
1455 }
1456} /* restore_multicast_list */
1457
1458/* ----------------------------------------------------------------------------
1459set_multicast_list
1460 Set or clear the multicast filter for this adaptor.
1461
1462Input
1463 num_addrs == -1 Promiscuous mode, receive all packets
1464 num_addrs == 0 Normal mode, clear multicast list
1465 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1466 best-effort filtering.
1467Output
1468 multicast_num_addrs
1469 multicast_ladrf[]
1470---------------------------------------------------------------------------- */
1471
1472static void set_multicast_list(struct net_device *dev)
1473{
1474 mace_private *lp = netdev_priv(dev);
1475 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
91fea585 1476 struct dev_mc_list *dmi;
1da177e4
LT		 1477
1478#ifdef PCMCIA_DEBUG
dd0fab5b 1479 {
1da177e4 1480 static int old;
4cd24eaf
JP		 1481 if (netdev_mc_count(dev) != old) {
1482 old = netdev_mc_count(dev);
dd0fab5b 1483 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1484 dev->name, old);
1485 }
1486 }
1487#endif
1488
1489 /* Set multicast_num_addrs. */
4cd24eaf 1490 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1491
1492 /* Set multicast_ladrf. */
1493 if (num_addrs > 0) {
1494 /* Calculate multicast logical address filter */
1495 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
91fea585 1496 netdev_for_each_mc_addr(dmi, dev) {
1da177e4 1497 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1da177e4
LT		 1498 BuildLAF(lp->multicast_ladrf, adr);
1499 }
1500 }
1501
1502 restore_multicast_list(dev);
1503
1504} /* set_multicast_list */
1505
1506#endif /* BROKEN_MULTICAST */
1507
1508static void restore_multicast_list(struct net_device *dev)
1509{
906da809 1510 unsigned int ioaddr = dev->base_addr;
1da177e4
LT		 1511 mace_private *lp = netdev_priv(dev);
1512
dd0fab5b 1513 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1da177e4
LT		 1514 lp->multicast_num_addrs);
1515
1516 if (dev->flags & IFF_PROMISC) {
1517 /* Promiscuous mode: receive all packets */
1518 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1519 mace_write(lp, ioaddr, MACE_MACCC,
1520 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1521 );
1522 } else {
1523 /* Normal mode */
1524 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1525 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1526 }
1527} /* restore_multicast_list */
1528
1529static void set_multicast_list(struct net_device *dev)
1530{
1531 mace_private *lp = netdev_priv(dev);
1532
1533#ifdef PCMCIA_DEBUG
dd0fab5b 1534 {
1da177e4 1535 static int old;
4cd24eaf
JP		 1536 if (netdev_mc_count(dev) != old) {
1537 old = netdev_mc_count(dev);
dd0fab5b 1538 pr_debug("%s: setting Rx mode to %d addresses.\n",
1da177e4
LT		 1539 dev->name, old);
1540 }
1541 }
1542#endif
1543
4cd24eaf 1544 lp->multicast_num_addrs = netdev_mc_count(dev);
1da177e4
LT		 1545 restore_multicast_list(dev);
1546
1547} /* set_multicast_list */
1548
a58e26cb
DB		 1549static struct pcmcia_device_id nmclan_ids[] = {
1550 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
d277ad0e 1551 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
a58e26cb
DB		 1552 PCMCIA_DEVICE_NULL,
1553};
1554MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1555
1da177e4
LT		 1556static struct pcmcia_driver nmclan_cs_driver = {
1557 .owner = THIS_MODULE,
1558 .drv = {
1559 .name = "nmclan_cs",
1560 },
15b99ac1 1561 .probe = nmclan_probe,
cc3b4866 1562 .remove = nmclan_detach,
a58e26cb 1563 .id_table = nmclan_ids,
98e4c28b
DB		 1564 .suspend = nmclan_suspend,
1565 .resume = nmclan_resume,
1da177e4
LT		 1566};
1567
1568static int __init init_nmclan_cs(void)
1569{
1570 return pcmcia_register_driver(&nmclan_cs_driver);
1571}
1572
1573static void __exit exit_nmclan_cs(void)
1574{
1575 pcmcia_unregister_driver(&nmclan_cs_driver);
1da177e4
LT		 1576}
1577
1578module_init(init_nmclan_cs);
1579module_exit(exit_nmclan_cs);
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