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pch_gbe: make local functions static
[net-next-2.6.git] / drivers / net / pch_gbe / pch_gbe.h
CommitLineData
77555ee7
MO		 1/*
2 * Copyright (C) 1999 - 2010 Intel Corporation.
3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4 *
5 * This code was derived from the Intel e1000e Linux driver.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21#ifndef _PCH_GBE_H_
22#define _PCH_GBE_H_
23
24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
25
26#include <linux/mii.h>
27#include <linux/delay.h>
28#include <linux/pci.h>
29#include <linux/netdevice.h>
30#include <linux/etherdevice.h>
31#include <linux/ethtool.h>
32#include <linux/vmalloc.h>
33#include <net/ip.h>
fc34ecd0
RD		 34#include <net/tcp.h>
35#include <net/udp.h>
77555ee7
MO		 36
37/**
38 * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
39 * @high Denotes the 1st to 4th byte from the initial of MAC address
40 * @low Denotes the 5th to 6th byte from the initial of MAC address
41 */
42struct pch_gbe_regs_mac_adr {
43 u32 high;
44 u32 low;
45};
46/**
47 * pch_udc_regs - Structure holding values of MAC registers
48 */
49struct pch_gbe_regs {
50 u32 INT_ST;
51 u32 INT_EN;
52 u32 MODE;
53 u32 RESET;
54 u32 TCPIP_ACC;
55 u32 EX_LIST;
56 u32 INT_ST_HOLD;
57 u32 PHY_INT_CTRL;
58 u32 MAC_RX_EN;
59 u32 RX_FCTRL;
60 u32 PAUSE_REQ;
61 u32 RX_MODE;
62 u32 TX_MODE;
63 u32 RX_FIFO_ST;
64 u32 TX_FIFO_ST;
65 u32 TX_FID;
66 u32 TX_RESULT;
67 u32 PAUSE_PKT1;
68 u32 PAUSE_PKT2;
69 u32 PAUSE_PKT3;
70 u32 PAUSE_PKT4;
71 u32 PAUSE_PKT5;
72 u32 reserve[2];
73 struct pch_gbe_regs_mac_adr mac_adr[16];
74 u32 ADDR_MASK;
75 u32 MIIM;
76 u32 reserve2;
77 u32 RGMII_ST;
78 u32 RGMII_CTRL;
79 u32 reserve3[3];
80 u32 DMA_CTRL;
81 u32 reserve4[3];
82 u32 RX_DSC_BASE;
83 u32 RX_DSC_SIZE;
84 u32 RX_DSC_HW_P;
85 u32 RX_DSC_HW_P_HLD;
86 u32 RX_DSC_SW_P;
87 u32 reserve5[3];
88 u32 TX_DSC_BASE;
89 u32 TX_DSC_SIZE;
90 u32 TX_DSC_HW_P;
91 u32 TX_DSC_HW_P_HLD;
92 u32 TX_DSC_SW_P;
93 u32 reserve6[3];
94 u32 RX_DMA_ST;
95 u32 TX_DMA_ST;
96 u32 reserve7[2];
97 u32 WOL_ST;
98 u32 WOL_CTRL;
99 u32 WOL_ADDR_MASK;
100};
101
102/* Interrupt Status */
103/* Interrupt Status Hold */
104/* Interrupt Enable */
105#define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 /* Receive DMA Transfer Complete */
106#define PCH_GBE_INT_RX_VALID 0x00000002 /* MAC Normal Receive Complete */
107#define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 /* Receive frame error */
108#define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 /* Receive FIFO Overflow */
109#define PCH_GBE_INT_RX_DMA_ERR 0x00000010 /* Receive DMA Transfer Error */
110#define PCH_GBE_INT_RX_DSC_EMP 0x00000020 /* Receive Descriptor Empty */
111#define PCH_GBE_INT_TX_CMPLT 0x00000100 /* MAC Transmission Complete */
112#define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 /* DMA Transfer Complete */
113#define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 /* Transmission FIFO underflow. */
114#define PCH_GBE_INT_TX_DMA_ERR 0x00000800 /* Transmission DMA Error */
115#define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 /* Pause Transmission complete */
116#define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */
117#define PCH_GBE_INT_PHY_INT 0x00100000 /* Interruption from PHY */
118#define PCH_GBE_INT_WOL_DET 0x01000000 /* Wake On LAN Event detection. */
119#define PCH_GBE_INT_TCPIP_ERR 0x10000000 /* TCP/IP Accelerator Error */
120
121/* Mode */
122#define PCH_GBE_MODE_MII_ETHER 0x00000000 /* GIGA Ethernet Mode [MII] */
123#define PCH_GBE_MODE_GMII_ETHER 0x80000000 /* GIGA Ethernet Mode [GMII] */
124#define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 /* Duplex Mode [half duplex] */
125#define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 /* Duplex Mode [full duplex] */
126#define PCH_GBE_MODE_FR_BST 0x04000000 /* Frame bursting is done */
127
128/* Reset */
129#define PCH_GBE_ALL_RST 0x80000000 /* All reset */
130#define PCH_GBE_TX_RST 0x40000000 /* TX MAC, TX FIFO, TX DMA reset */
131#define PCH_GBE_RX_RST 0x04000000 /* RX MAC, RX FIFO, RX DMA reset */
132
133/* TCP/IP Accelerator Control */
134#define PCH_GBE_EX_LIST_EN 0x00000008 /* External List Enable */
135#define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 /* RX TCP/IP ACC Disabled */
136#define PCH_GBE_TX_TCPIPACC_EN 0x00000002 /* TX TCP/IP ACC Enable */
137#define PCH_GBE_RX_TCPIPACC_EN 0x00000001 /* RX TCP/IP ACC Enable */
138
139/* MAC RX Enable */
140#define PCH_GBE_MRE_MAC_RX_EN 0x00000001 /* MAC Receive Enable */
141
142/* RX Flow Control */
143#define PCH_GBE_FL_CTRL_EN 0x80000000 /* Pause packet is enabled */
144
145/* Pause Packet Request */
146#define PCH_GBE_PS_PKT_RQ 0x80000000 /* Pause packet Request */
147
148/* RX Mode */
149#define PCH_GBE_ADD_FIL_EN 0x80000000 /* Address Filtering Enable */
150/* Multicast Filtering Enable */
151#define PCH_GBE_MLT_FIL_EN 0x40000000
152/* Receive Almost Empty Threshold */
153#define PCH_GBE_RH_ALM_EMP_4 0x00000000 /* 4 words */
154#define PCH_GBE_RH_ALM_EMP_8 0x00004000 /* 8 words */
155#define PCH_GBE_RH_ALM_EMP_16 0x00008000 /* 16 words */
156#define PCH_GBE_RH_ALM_EMP_32 0x0000C000 /* 32 words */
157/* Receive Almost Full Threshold */
158#define PCH_GBE_RH_ALM_FULL_4 0x00000000 /* 4 words */
159#define PCH_GBE_RH_ALM_FULL_8 0x00001000 /* 8 words */
160#define PCH_GBE_RH_ALM_FULL_16 0x00002000 /* 16 words */
161#define PCH_GBE_RH_ALM_FULL_32 0x00003000 /* 32 words */
162/* RX FIFO Read Triger Threshold */
163#define PCH_GBE_RH_RD_TRG_4 0x00000000 /* 4 words */
164#define PCH_GBE_RH_RD_TRG_8 0x00000200 /* 8 words */
165#define PCH_GBE_RH_RD_TRG_16 0x00000400 /* 16 words */
166#define PCH_GBE_RH_RD_TRG_32 0x00000600 /* 32 words */
167#define PCH_GBE_RH_RD_TRG_64 0x00000800 /* 64 words */
168#define PCH_GBE_RH_RD_TRG_128 0x00000A00 /* 128 words */
169#define PCH_GBE_RH_RD_TRG_256 0x00000C00 /* 256 words */
170#define PCH_GBE_RH_RD_TRG_512 0x00000E00 /* 512 words */
171
172/* Receive Descriptor bit definitions */
173#define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400
174#define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200
175#define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100
176#define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000C0
177#define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080
178#define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040
179#define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020
180#define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010
181#define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008
182#define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004
183#define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002
184#define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001
185#define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200
186#define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100
187#define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080
188#define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040
189#define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020
190#define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010
191#define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008
192#define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004
193#define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002
194#define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001
195
196/* Transmit Descriptor bit definitions */
197#define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008
198#define PCH_GBE_TXD_CTRL_ITAG 0x0004
199#define PCH_GBE_TXD_CTRL_ICRC 0x0002
200#define PCH_GBE_TXD_CTRL_APAD 0x0001
201#define PCH_GBE_TXD_WORDS_SHIFT 2
202#define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000
203#define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000
204#define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800
205#define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400
206#define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200
207#define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100
208#define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080
209#define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040
210#define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020
211#define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010
212#define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK 0x000F
213
214/* TX Mode */
215#define PCH_GBE_TM_NO_RTRY 0x80000000 /* No Retransmission */
216#define PCH_GBE_TM_LONG_PKT 0x40000000 /* Long Packt TX Enable */
217#define PCH_GBE_TM_ST_AND_FD 0x20000000 /* Stare and Forward */
218#define PCH_GBE_TM_SHORT_PKT 0x10000000 /* Short Packet TX Enable */
219#define PCH_GBE_TM_LTCOL_RETX 0x08000000 /* Retransmission at Late Collision */
220/* Frame Start Threshold */
221#define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 /* 4 words */
222#define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 /* 8 words */
223#define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 /* 16 words */
224#define PCH_GBE_TM_TH_TX_STRT_32 0x0000C000 /* 32 words */
225/* Transmit Almost Empty Threshold */
226#define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 /* 4 words */
227#define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 /* 8 words */
228#define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 /* 16 words */
229#define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 /* 32 words */
230#define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 /* 64 words */
231#define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 /* 128 words */
232#define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 /* 256 words */
233#define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 /* 512 words */
234/* Transmit Almost Full Threshold */
235#define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 /* 4 words */
236#define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 /* 8 words */
237#define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 /* 16 words */
238#define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 /* 32 words */
239
240/* RX FIFO Status */
241#define PCH_GBE_RF_ALM_FULL 0x80000000 /* RX FIFO is almost full. */
242#define PCH_GBE_RF_ALM_EMP 0x40000000 /* RX FIFO is almost empty. */
243#define PCH_GBE_RF_RD_TRG 0x20000000 /* Become more than RH_RD_TRG. */
244#define PCH_GBE_RF_STRWD 0x1FFE0000 /* The word count of RX FIFO. */
245#define PCH_GBE_RF_RCVING 0x00010000 /* Stored in RX FIFO. */
246
247/* MAC Address Mask */
248#define PCH_GBE_BUSY 0x80000000
249
250/* MIIM */
251#define PCH_GBE_MIIM_OPER_WRITE 0x04000000
252#define PCH_GBE_MIIM_OPER_READ 0x00000000
253#define PCH_GBE_MIIM_OPER_READY 0x04000000
254#define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
255#define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
256
257/* RGMII Status */
258#define PCH_GBE_LINK_UP 0x80000008
259#define PCH_GBE_RXC_SPEED_MSK 0x00000006
260#define PCH_GBE_RXC_SPEED_2_5M 0x00000000 /* 2.5MHz */
261#define PCH_GBE_RXC_SPEED_25M 0x00000002 /* 25MHz */
262#define PCH_GBE_RXC_SPEED_125M 0x00000004 /* 100MHz */
263#define PCH_GBE_DUPLEX_FULL 0x00000001
264
265/* RGMII Control */
266#define PCH_GBE_CRS_SEL 0x00000010
267#define PCH_GBE_RGMII_RATE_125M 0x00000000
268#define PCH_GBE_RGMII_RATE_25M 0x00000008
269#define PCH_GBE_RGMII_RATE_2_5M 0x0000000C
270#define PCH_GBE_RGMII_MODE_GMII 0x00000000
271#define PCH_GBE_RGMII_MODE_RGMII 0x00000002
272#define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000
273#define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001
274
275/* DMA Control */
276#define PCH_GBE_RX_DMA_EN 0x00000002 /* Enables Receive DMA */
277#define PCH_GBE_TX_DMA_EN 0x00000001 /* Enables Transmission DMA */
278
279/* Wake On LAN Status */
280#define PCH_GBE_WLS_BR 0x00000008 /* Broadcas Address */
281#define PCH_GBE_WLS_MLT 0x00000004 /* Multicast Address */
282
283/* The Frame registered in Address Recognizer */
284#define PCH_GBE_WLS_IND 0x00000002
285#define PCH_GBE_WLS_MP 0x00000001 /* Magic packet Address */
286
287/* Wake On LAN Control */
288#define PCH_GBE_WLC_WOL_MODE 0x00010000
289#define PCH_GBE_WLC_IGN_TLONG 0x00000100
290#define PCH_GBE_WLC_IGN_TSHRT 0x00000080
291#define PCH_GBE_WLC_IGN_OCTER 0x00000040
292#define PCH_GBE_WLC_IGN_NBLER 0x00000020
293#define PCH_GBE_WLC_IGN_CRCER 0x00000010
294#define PCH_GBE_WLC_BR 0x00000008
295#define PCH_GBE_WLC_MLT 0x00000004
296#define PCH_GBE_WLC_IND 0x00000002
297#define PCH_GBE_WLC_MP 0x00000001
298
299/* Wake On LAN Address Mask */
300#define PCH_GBE_WLA_BUSY 0x80000000
301
302
303
304/* TX/RX descriptor defines */
305#define PCH_GBE_MAX_TXD 4096
306#define PCH_GBE_DEFAULT_TXD 256
307#define PCH_GBE_MIN_TXD 8
308#define PCH_GBE_MAX_RXD 4096
309#define PCH_GBE_DEFAULT_RXD 256
310#define PCH_GBE_MIN_RXD 8
311
312/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
313#define PCH_GBE_TX_DESC_MULTIPLE 8
314#define PCH_GBE_RX_DESC_MULTIPLE 8
315
316/* Read/Write operation is done through MII Management IF */
317#define PCH_GBE_HAL_MIIM_READ ((u32)0x00000000)
318#define PCH_GBE_HAL_MIIM_WRITE ((u32)0x04000000)
319
320/* flow control values */
321#define PCH_GBE_FC_NONE 0
322#define PCH_GBE_FC_RX_PAUSE 1
323#define PCH_GBE_FC_TX_PAUSE 2
324#define PCH_GBE_FC_FULL 3
325#define PCH_GBE_FC_DEFAULT PCH_GBE_FC_FULL
326
327
328struct pch_gbe_hw;
329/**
330 * struct pch_gbe_functions - HAL APi function pointer
331 * @get_bus_info: for pch_gbe_hal_get_bus_info
332 * @init_hw: for pch_gbe_hal_init_hw
333 * @read_phy_reg: for pch_gbe_hal_read_phy_reg
334 * @write_phy_reg: for pch_gbe_hal_write_phy_reg
335 * @reset_phy: for pch_gbe_hal_phy_hw_reset
336 * @sw_reset_phy: for pch_gbe_hal_phy_sw_reset
337 * @power_up_phy: for pch_gbe_hal_power_up_phy
338 * @power_down_phy: for pch_gbe_hal_power_down_phy
339 * @read_mac_addr: for pch_gbe_hal_read_mac_addr
340 */
341struct pch_gbe_functions {
342 void (*get_bus_info) (struct pch_gbe_hw *);
343 s32 (*init_hw) (struct pch_gbe_hw *);
344 s32 (*read_phy_reg) (struct pch_gbe_hw *, u32, u16 *);
345 s32 (*write_phy_reg) (struct pch_gbe_hw *, u32, u16);
346 void (*reset_phy) (struct pch_gbe_hw *);
347 void (*sw_reset_phy) (struct pch_gbe_hw *);
348 void (*power_up_phy) (struct pch_gbe_hw *hw);
349 void (*power_down_phy) (struct pch_gbe_hw *hw);
350 s32 (*read_mac_addr) (struct pch_gbe_hw *);
351};
352
353/**
354 * struct pch_gbe_mac_info - MAC infomation
355 * @addr[6]: Store the MAC address
356 * @fc: Mode of flow control
357 * @fc_autoneg: Auto negotiation enable for flow control setting
358 * @tx_fc_enable: Enable flag of Transmit flow control
359 * @max_frame_size: Max transmit frame size
360 * @min_frame_size: Min transmit frame size
361 * @autoneg: Auto negotiation enable
362 * @link_speed: Link speed
363 * @link_duplex: Link duplex
364 */
365struct pch_gbe_mac_info {
366 u8 addr[6];
367 u8 fc;
368 u8 fc_autoneg;
369 u8 tx_fc_enable;
370 u32 max_frame_size;
371 u32 min_frame_size;
372 u8 autoneg;
373 u16 link_speed;
374 u16 link_duplex;
375};
376
377/**
378 * struct pch_gbe_phy_info - PHY infomation
379 * @addr: PHY address
380 * @id: PHY's identifier
381 * @revision: PHY's revision
382 * @reset_delay_us: HW reset delay time[us]
383 * @autoneg_advertised: Autoneg advertised
384 */
385struct pch_gbe_phy_info {
386 u32 addr;
387 u32 id;
388 u32 revision;
389 u32 reset_delay_us;
390 u16 autoneg_advertised;
391};
392
393/*!
394 * @ingroup Gigabit Ether driver Layer
395 * @struct pch_gbe_bus_info
396 * @brief Bus infomation
397 */
398struct pch_gbe_bus_info {
399 u8 type;
400 u8 speed;
401 u8 width;
402};
403
404/*!
405 * @ingroup Gigabit Ether driver Layer
406 * @struct pch_gbe_hw
407 * @brief Hardware infomation
408 */
409struct pch_gbe_hw {
410 void *back;
411
412 struct pch_gbe_regs __iomem *reg;
413 spinlock_t miim_lock;
414
415 const struct pch_gbe_functions *func;
416 struct pch_gbe_mac_info mac;
417 struct pch_gbe_phy_info phy;
418 struct pch_gbe_bus_info bus;
419};
420
421/**
422 * struct pch_gbe_rx_desc - Receive Descriptor
423 * @buffer_addr: RX Frame Buffer Address
424 * @tcp_ip_status: TCP/IP Accelerator Status
425 * @rx_words_eob: RX word count and Byte position
426 * @gbec_status: GMAC Status
427 * @dma_status: DMA Status
428 * @reserved1: Reserved
429 * @reserved2: Reserved
430 */
431struct pch_gbe_rx_desc {
432 u32 buffer_addr;
433 u32 tcp_ip_status;
434 u16 rx_words_eob;
435 u16 gbec_status;
436 u8 dma_status;
437 u8 reserved1;
438 u16 reserved2;
439};
440
441/**
442 * struct pch_gbe_tx_desc - Transmit Descriptor
443 * @buffer_addr: TX Frame Buffer Address
444 * @length: Data buffer length
445 * @reserved1: Reserved
446 * @tx_words_eob: TX word count and Byte position
447 * @tx_frame_ctrl: TX Frame Control
448 * @dma_status: DMA Status
449 * @reserved2: Reserved
450 * @gbec_status: GMAC Status
451 */
452struct pch_gbe_tx_desc {
453 u32 buffer_addr;
454 u16 length;
455 u16 reserved1;
456 u16 tx_words_eob;
457 u16 tx_frame_ctrl;
458 u8 dma_status;
459 u8 reserved2;
460 u16 gbec_status;
461};
462
463
464/**
465 * struct pch_gbe_buffer - Buffer infomation
466 * @skb: pointer to a socket buffer
467 * @dma: DMA address
468 * @time_stamp: time stamp
469 * @length: data size
470 */
471struct pch_gbe_buffer {
472 struct sk_buff *skb;
473 dma_addr_t dma;
474 unsigned long time_stamp;
475 u16 length;
476 bool mapped;
477};
478
479/**
480 * struct pch_gbe_tx_ring - tx ring infomation
481 * @tx_lock: spinlock structs
482 * @desc: pointer to the descriptor ring memory
483 * @dma: physical address of the descriptor ring
484 * @size: length of descriptor ring in bytes
485 * @count: number of descriptors in the ring
486 * @next_to_use: next descriptor to associate a buffer with
487 * @next_to_clean: next descriptor to check for DD status bit
488 * @buffer_info: array of buffer information structs
489 */
490struct pch_gbe_tx_ring {
491 spinlock_t tx_lock;
492 struct pch_gbe_tx_desc *desc;
493 dma_addr_t dma;
494 unsigned int size;
495 unsigned int count;
496 unsigned int next_to_use;
497 unsigned int next_to_clean;
498 struct pch_gbe_buffer *buffer_info;
499};
500
501/**
502 * struct pch_gbe_rx_ring - rx ring infomation
503 * @desc: pointer to the descriptor ring memory
504 * @dma: physical address of the descriptor ring
505 * @size: length of descriptor ring in bytes
506 * @count: number of descriptors in the ring
507 * @next_to_use: next descriptor to associate a buffer with
508 * @next_to_clean: next descriptor to check for DD status bit
509 * @buffer_info: array of buffer information structs
510 */
511struct pch_gbe_rx_ring {
512 struct pch_gbe_rx_desc *desc;
513 dma_addr_t dma;
514 unsigned int size;
515 unsigned int count;
516 unsigned int next_to_use;
517 unsigned int next_to_clean;
518 struct pch_gbe_buffer *buffer_info;
519};
520
521/**
522 * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
523 * @rx_packets: total packets received
524 * @tx_packets: total packets transmitted
525 * @rx_bytes: total bytes received
526 * @tx_bytes: total bytes transmitted
527 * @rx_errors: bad packets received
528 * @tx_errors: packet transmit problems
529 * @rx_dropped: no space in Linux buffers
530 * @tx_dropped: no space available in Linux
531 * @multicast: multicast packets received
532 * @collisions: collisions
533 * @rx_crc_errors: received packet with crc error
534 * @rx_frame_errors: received frame alignment error
535 * @rx_alloc_buff_failed: allocate failure of a receive buffer
536 * @tx_length_errors: transmit length error
537 * @tx_aborted_errors: transmit aborted error
538 * @tx_carrier_errors: transmit carrier error
539 * @tx_timeout_count: Number of transmit timeout
540 * @tx_restart_count: Number of transmit restert
541 * @intr_rx_dsc_empty_count: Interrupt count of receive descriptor empty
542 * @intr_rx_frame_err_count: Interrupt count of receive frame error
543 * @intr_rx_fifo_err_count: Interrupt count of receive FIFO error
544 * @intr_rx_dma_err_count: Interrupt count of receive DMA error
545 * @intr_tx_fifo_err_count: Interrupt count of transmit FIFO error
546 * @intr_tx_dma_err_count: Interrupt count of transmit DMA error
547 * @intr_tcpip_err_count: Interrupt count of TCP/IP Accelerator
548 */
549struct pch_gbe_hw_stats {
550 u32 rx_packets;
551 u32 tx_packets;
552 u32 rx_bytes;
553 u32 tx_bytes;
554 u32 rx_errors;
555 u32 tx_errors;
556 u32 rx_dropped;
557 u32 tx_dropped;
558 u32 multicast;
559 u32 collisions;
560 u32 rx_crc_errors;
561 u32 rx_frame_errors;
562 u32 rx_alloc_buff_failed;
563 u32 tx_length_errors;
564 u32 tx_aborted_errors;
565 u32 tx_carrier_errors;
566 u32 tx_timeout_count;
567 u32 tx_restart_count;
568 u32 intr_rx_dsc_empty_count;
569 u32 intr_rx_frame_err_count;
570 u32 intr_rx_fifo_err_count;
571 u32 intr_rx_dma_err_count;
572 u32 intr_tx_fifo_err_count;
573 u32 intr_tx_dma_err_count;
574 u32 intr_tcpip_err_count;
575};
576
577/**
578 * struct pch_gbe_adapter - board specific private data structure
579 * @stats_lock: Spinlock structure for status
580 * @tx_queue_lock: Spinlock structure for transmit
581 * @ethtool_lock: Spinlock structure for ethtool
582 * @irq_sem: Semaphore for interrupt
583 * @netdev: Pointer of network device structure
584 * @pdev: Pointer of pci device structure
585 * @polling_netdev: Pointer of polling network device structure
586 * @napi: NAPI structure
587 * @hw: Pointer of hardware structure
588 * @stats: Hardware status
589 * @reset_task: Reset task
590 * @mii: MII information structure
591 * @watchdog_timer: Watchdog timer list
592 * @wake_up_evt: Wake up event
593 * @config_space: Configuration space
594 * @msg_enable: Driver message level
595 * @led_status: LED status
596 * @tx_ring: Pointer of Tx descriptor ring structure
597 * @rx_ring: Pointer of Rx descriptor ring structure
598 * @rx_buffer_len: Receive buffer length
599 * @tx_queue_len: Transmit queue length
600 * @rx_csum: Receive TCP/IP checksum enable/disable
601 * @tx_csum: Transmit TCP/IP checksum enable/disable
602 * @have_msi: PCI MSI mode flag
603 */
604
605struct pch_gbe_adapter {
606 spinlock_t stats_lock;
607 spinlock_t tx_queue_lock;
608 spinlock_t ethtool_lock;
609 atomic_t irq_sem;
610 struct net_device *netdev;
611 struct pci_dev *pdev;
612 struct net_device *polling_netdev;
613 struct napi_struct napi;
614 struct pch_gbe_hw hw;
615 struct pch_gbe_hw_stats stats;
616 struct work_struct reset_task;
617 struct mii_if_info mii;
618 struct timer_list watchdog_timer;
619 u32 wake_up_evt;
620 u32 *config_space;
621 unsigned long led_status;
622 struct pch_gbe_tx_ring *tx_ring;
623 struct pch_gbe_rx_ring *rx_ring;
624 unsigned long rx_buffer_len;
625 unsigned long tx_queue_len;
626 bool rx_csum;
627 bool tx_csum;
628 bool have_msi;
629};
630
631extern const char pch_driver_version[];
632
633/* pch_gbe_main.c */
634extern int pch_gbe_up(struct pch_gbe_adapter *adapter);
635extern void pch_gbe_down(struct pch_gbe_adapter *adapter);
636extern void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
637extern void pch_gbe_reset(struct pch_gbe_adapter *adapter);
638extern int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
639 struct pch_gbe_tx_ring *txdr);
640extern int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
641 struct pch_gbe_rx_ring *rxdr);
642extern void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
643 struct pch_gbe_tx_ring *tx_ring);
644extern void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
645 struct pch_gbe_rx_ring *rx_ring);
646extern void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
191cc687 647
77555ee7
MO		 648/* pch_gbe_param.c */
649extern void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
650
651/* pch_gbe_ethtool.c */
652extern void pch_gbe_set_ethtool_ops(struct net_device *netdev);
653
654/* pch_gbe_mac.c */
655extern s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
656extern s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw);
657extern u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw,
658 u32 addr, u32 dir, u32 reg, u16 data);
659#endif /* _PCH_GBE_H_ */
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