[net-next-2.6.git] / drivers / net / pasemi_mac.h

/*
 * Copyright (C) 2006 PA Semi, Inc
 *
 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
 * hardware register layouts.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#ifndef PASEMI_MAC_H
#define PASEMI_MAC_H

#include <linux/ethtool.h>
#include <linux/netdevice.h>
#include <linux/spinlock.h>
#include <linux/phy.h>

struct pasemi_mac_txring {
	spinlock_t	 lock;
	struct pas_dma_xct_descr	*desc;
	dma_addr_t	 dma;
	unsigned int	 size;
	unsigned int	 next_to_use;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *desc_info;
	char		 irq_name[10];  /* "eth%d tx" */
};

struct pasemi_mac_rxring {
	spinlock_t	 lock;
	struct pas_dma_xct_descr	*desc;	/* RX channel descriptor ring */
	dma_addr_t	 dma;
	u64		*buffers;	/* RX interface buffer ring */
	dma_addr_t	 buf_dma;
	unsigned int	 size;
	unsigned int	 next_to_fill;
	unsigned int	 next_to_clean;
	struct pasemi_mac_buffer *desc_info;
	char		 irq_name[10];  /* "eth%d rx" */
};

struct pasemi_mac {
	struct net_device *netdev;
	struct pci_dev *pdev;
	struct pci_dev *dma_pdev;
	struct pci_dev *iob_pdev;
	struct phy_device *phydev;
	struct napi_struct napi;
	struct net_device_stats stats;

	/* Pointer to the cacheable per-channel status registers */
	u64	*rx_status;
	u64	*tx_status;

	u8		type;
#define MAC_TYPE_GMAC	1
#define MAC_TYPE_XAUI	2
	u32	dma_txch;
	u32	dma_if;
	u32	dma_rxch;

	u8		mac_addr[6];

	struct timer_list	rxtimer;

	struct pasemi_mac_txring *tx;
	struct pasemi_mac_rxring *rx;
	unsigned long	tx_irq;
	unsigned long	rx_irq;
	int	link;
	int	speed;
	int	duplex;

	unsigned int	msg_enable;
	char	phy_id[BUS_ID_SIZE];
};

/* Software status descriptor (desc_info) */
struct pasemi_mac_buffer {
	struct sk_buff *skb;
	dma_addr_t	dma;
};


/* status register layout in IOB region, at 0xfb800000 */
struct pasdma_status {
	u64 rx_sta[64];
	u64 tx_sta[20];
};

/* descriptor structure */
struct pas_dma_xct_descr {
	union {
		u64	mactx;
		u64	macrx;
	};
	union {
		u64	ptr;
		u64	rxb;
	};
};

/* MAC CFG register offsets */

enum {
	PAS_MAC_CFG_PCFG = 0x80,
	PAS_MAC_CFG_TXP = 0x98,
	PAS_MAC_IPC_CHNL = 0x208,
};

/* MAC CFG register fields */
#define PAS_MAC_CFG_PCFG_PE		0x80000000
#define PAS_MAC_CFG_PCFG_CE		0x40000000
#define PAS_MAC_CFG_PCFG_BU		0x20000000
#define PAS_MAC_CFG_PCFG_TT		0x10000000
#define PAS_MAC_CFG_PCFG_TSR_M		0x0c000000
#define PAS_MAC_CFG_PCFG_TSR_10M	0x00000000
#define PAS_MAC_CFG_PCFG_TSR_100M	0x04000000
#define PAS_MAC_CFG_PCFG_TSR_1G		0x08000000
#define PAS_MAC_CFG_PCFG_TSR_10G	0x0c000000
#define PAS_MAC_CFG_PCFG_T24		0x02000000
#define PAS_MAC_CFG_PCFG_PR		0x01000000
#define PAS_MAC_CFG_PCFG_CRO_M		0x00ff0000
#define PAS_MAC_CFG_PCFG_CRO_S	16
#define PAS_MAC_CFG_PCFG_IPO_M		0x0000ff00
#define PAS_MAC_CFG_PCFG_IPO_S	8
#define PAS_MAC_CFG_PCFG_S1		0x00000080
#define PAS_MAC_CFG_PCFG_IO_M		0x00000060
#define PAS_MAC_CFG_PCFG_IO_MAC		0x00000000
#define PAS_MAC_CFG_PCFG_IO_OFF		0x00000020
#define PAS_MAC_CFG_PCFG_IO_IND_ETH	0x00000040
#define PAS_MAC_CFG_PCFG_IO_IND_IP	0x00000060
#define PAS_MAC_CFG_PCFG_LP		0x00000010
#define PAS_MAC_CFG_PCFG_TS		0x00000008
#define PAS_MAC_CFG_PCFG_HD		0x00000004
#define PAS_MAC_CFG_PCFG_SPD_M		0x00000003
#define PAS_MAC_CFG_PCFG_SPD_10M	0x00000000
#define PAS_MAC_CFG_PCFG_SPD_100M	0x00000001
#define PAS_MAC_CFG_PCFG_SPD_1G		0x00000002
#define PAS_MAC_CFG_PCFG_SPD_10G	0x00000003
#define PAS_MAC_CFG_TXP_FCF		0x01000000
#define PAS_MAC_CFG_TXP_FCE		0x00800000
#define PAS_MAC_CFG_TXP_FC		0x00400000
#define PAS_MAC_CFG_TXP_FPC_M		0x00300000
#define PAS_MAC_CFG_TXP_FPC_S		20
#define PAS_MAC_CFG_TXP_FPC(x)		(((x) << PAS_MAC_CFG_TXP_FPC_S) & \
					 PAS_MAC_CFG_TXP_FPC_M)
#define PAS_MAC_CFG_TXP_RT		0x00080000
#define PAS_MAC_CFG_TXP_BL		0x00040000
#define PAS_MAC_CFG_TXP_SL_M		0x00030000
#define PAS_MAC_CFG_TXP_SL_S		16
#define PAS_MAC_CFG_TXP_SL(x)		(((x) << PAS_MAC_CFG_TXP_SL_S) & \
					 PAS_MAC_CFG_TXP_SL_M)
#define PAS_MAC_CFG_TXP_COB_M		0x0000f000
#define PAS_MAC_CFG_TXP_COB_S		12
#define PAS_MAC_CFG_TXP_COB(x)		(((x) << PAS_MAC_CFG_TXP_COB_S) & \
					 PAS_MAC_CFG_TXP_COB_M)
#define PAS_MAC_CFG_TXP_TIFT_M		0x00000f00
#define PAS_MAC_CFG_TXP_TIFT_S		8
#define PAS_MAC_CFG_TXP_TIFT(x)		(((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
					 PAS_MAC_CFG_TXP_TIFT_M)
#define PAS_MAC_CFG_TXP_TIFG_M		0x000000ff
#define PAS_MAC_CFG_TXP_TIFG_S		0
#define PAS_MAC_CFG_TXP_TIFG(x)		(((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
					 PAS_MAC_CFG_TXP_TIFG_M)

#define PAS_MAC_IPC_CHNL_DCHNO_M	0x003f0000
#define PAS_MAC_IPC_CHNL_DCHNO_S	16
#define PAS_MAC_IPC_CHNL_DCHNO(x)	(((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
					 PAS_MAC_IPC_CHNL_DCHNO_M)
#define PAS_MAC_IPC_CHNL_BCH_M		0x0000003f
#define PAS_MAC_IPC_CHNL_BCH_S		0
#define PAS_MAC_IPC_CHNL_BCH(x)		(((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
					 PAS_MAC_IPC_CHNL_BCH_M)

/* All these registers live in the PCI configuration space for the DMA PCI
 * device. Use the normal PCI config access functions for them.
 */
enum {
	PAS_DMA_COM_TXCMD = 0x100,	/* Transmit Command Register  */
	PAS_DMA_COM_TXSTA = 0x104,	/* Transmit Status Register   */
	PAS_DMA_COM_RXCMD = 0x108,	/* Receive Command Register   */
	PAS_DMA_COM_RXSTA = 0x10c,	/* Receive Status Register    */
};
#define PAS_DMA_COM_TXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_TXSTA_ACT	0x00000001 /* active */
#define PAS_DMA_COM_RXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_RXSTA_ACT	0x00000001 /* active */


/* Per-interface and per-channel registers */
#define _PAS_DMA_RXINT_STRIDE		0x20
#define PAS_DMA_RXINT_RCMDSTA(i)	(0x200+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_RCMDSTA_EN	0x00000001
#define    PAS_DMA_RXINT_RCMDSTA_ST	0x00000002
#define    PAS_DMA_RXINT_RCMDSTA_MBT	0x00000008
#define    PAS_DMA_RXINT_RCMDSTA_MDR	0x00000010
#define    PAS_DMA_RXINT_RCMDSTA_MOO	0x00000020
#define    PAS_DMA_RXINT_RCMDSTA_MBP	0x00000040
#define    PAS_DMA_RXINT_RCMDSTA_BT	0x00000800
#define    PAS_DMA_RXINT_RCMDSTA_DR	0x00001000
#define    PAS_DMA_RXINT_RCMDSTA_OO	0x00002000
#define    PAS_DMA_RXINT_RCMDSTA_BP	0x00004000
#define    PAS_DMA_RXINT_RCMDSTA_TB	0x00008000
#define    PAS_DMA_RXINT_RCMDSTA_ACT	0x00010000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_M	0xfffe0000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_S	17
#define PAS_DMA_RXINT_INCR(i)		(0x210+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_INCR_INCR_M	0x0000ffff
#define    PAS_DMA_RXINT_INCR_INCR_S	0
#define    PAS_DMA_RXINT_INCR_INCR(x)	((x) & 0x0000ffff)
#define PAS_DMA_RXINT_BASEL(i)		(0x218+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEL_BRBL(x)	((x) & ~0x3f)
#define PAS_DMA_RXINT_BASEU(i)		(0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEU_BRBH(x)	((x) & 0xfff)
#define    PAS_DMA_RXINT_BASEU_SIZ_M	0x3fff0000	/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXINT_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXINT_BASEU_SIZ(x)	(((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
					 PAS_DMA_RXINT_BASEU_SIZ_M)


#define _PAS_DMA_TXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_TXCHAN_TCMDSTA	0x300	/* Command / Status		*/
#define _PAS_DMA_TXCHAN_CFG	0x304	/* Configuration		*/
#define _PAS_DMA_TXCHAN_DSCRBU	0x308	/* Descriptor BU Allocation	*/
#define _PAS_DMA_TXCHAN_INCR	0x310	/* Descriptor increment		*/
#define _PAS_DMA_TXCHAN_CNT	0x314	/* Descriptor count/offset	*/
#define _PAS_DMA_TXCHAN_BASEL	0x318	/* Descriptor ring base (low)	*/
#define _PAS_DMA_TXCHAN_BASEU	0x31c	/*			(high)	*/
#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_TCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_TXCHAN_TCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_TXCHAN_TCMDSTA_ACT	0x00010000	/* Active */
#define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_CFG_TY_IFACE	0x00000000	/* Type = interface */
#define    PAS_DMA_TXCHAN_CFG_TATTR_M	0x0000003c
#define    PAS_DMA_TXCHAN_CFG_TATTR_S	2
#define    PAS_DMA_TXCHAN_CFG_TATTR(x)	(((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
					 PAS_DMA_TXCHAN_CFG_TATTR_M)
#define    PAS_DMA_TXCHAN_CFG_WT_M	0x000001c0
#define    PAS_DMA_TXCHAN_CFG_WT_S	6
#define    PAS_DMA_TXCHAN_CFG_WT(x)	(((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
					 PAS_DMA_TXCHAN_CFG_WT_M)
#define    PAS_DMA_TXCHAN_CFG_CF	0x00001000	/* Clean first line */
#define    PAS_DMA_TXCHAN_CFG_CL	0x00002000	/* Clean last line */
#define    PAS_DMA_TXCHAN_CFG_UP	0x00004000	/* update tx descr when sent */
#define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_TXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_TXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_TXCHAN_BASEL_BRBL_M)
#define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_TXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_TXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_TXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_TXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_TXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_TXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_TXCHAN_BASEU_SIZ_M)

#define _PAS_DMA_RXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_RXCHAN_CCMDSTA	0x800	/* Command / Status		*/
#define _PAS_DMA_RXCHAN_CFG	0x804	/* Configuration		*/
#define _PAS_DMA_RXCHAN_INCR	0x810	/* Descriptor increment		*/
#define _PAS_DMA_RXCHAN_CNT	0x814	/* Descriptor count/offset	*/
#define _PAS_DMA_RXCHAN_BASEL	0x818	/* Descriptor ring base (low)	*/
#define _PAS_DMA_RXCHAN_BASEU	0x81c	/*			(high)	*/
#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_RXCHAN_CCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_RXCHAN_CCMDSTA_ACT	0x00010000	/* Active */
#define    PAS_DMA_RXCHAN_CCMDSTA_DU	0x00020000
#define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CFG_HBU_M	0x00000380
#define    PAS_DMA_RXCHAN_CFG_HBU_S	7
#define    PAS_DMA_RXCHAN_CFG_HBU(x)	(((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
					 PAS_DMA_RXCHAN_CFG_HBU_M)
#define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_RXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_RXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_RXCHAN_BASEL_BRBL_M)
#define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_RXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_RXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_RXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_RXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_RXCHAN_BASEU_SIZ_M)

#define    PAS_STATUS_PCNT_M		0x000000000000ffffull
#define    PAS_STATUS_PCNT_S		0
#define    PAS_STATUS_DCNT_M		0x00000000ffff0000ull
#define    PAS_STATUS_DCNT_S		16
#define    PAS_STATUS_BPCNT_M		0x0000ffff00000000ull
#define    PAS_STATUS_BPCNT_S		32
#define    PAS_STATUS_CAUSE_M		0xf000000000000000ull
#define    PAS_STATUS_TIMER		0x1000000000000000ull
#define    PAS_STATUS_ERROR		0x2000000000000000ull
#define    PAS_STATUS_SOFT		0x4000000000000000ull
#define    PAS_STATUS_INT		0x8000000000000000ull

#define PAS_IOB_DMA_RXCH_CFG(i)		(0x1100 + (i)*4)
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_TXCH_CFG(i)		(0x1200 + (i)*4)
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_RXCH_STAT(i)	(0x1300 + (i)*4)
#define    PAS_IOB_DMA_RXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_TXCH_STAT(i)	(0x1400 + (i)*4)
#define    PAS_IOB_DMA_TXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_RXCH_RESET(i)	(0x1500 + (i)*4)
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_RXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_RXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_RXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_RXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_RXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_RXCH_RESET_PINTC		0x00000001
#define PAS_IOB_DMA_TXCH_RESET(i)	(0x1600 + (i)*4)
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_TXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_TXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_TXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_TXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_TXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_TXCH_RESET_PINTC		0x00000001

#define PAS_IOB_DMA_COM_TIMEOUTCFG		0x1700
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M	0x00ffffff
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S	0
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)	(((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
						 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)

/* Transmit descriptor fields */
#define	XCT_MACTX_T		0x8000000000000000ull
#define	XCT_MACTX_ST		0x4000000000000000ull
#define XCT_MACTX_NORES		0x0000000000000000ull
#define XCT_MACTX_8BRES		0x1000000000000000ull
#define XCT_MACTX_24BRES	0x2000000000000000ull
#define XCT_MACTX_40BRES	0x3000000000000000ull
#define XCT_MACTX_I		0x0800000000000000ull
#define XCT_MACTX_O		0x0400000000000000ull
#define XCT_MACTX_E		0x0200000000000000ull
#define XCT_MACTX_VLAN_M	0x0180000000000000ull
#define XCT_MACTX_VLAN_NOP	0x0000000000000000ull
#define XCT_MACTX_VLAN_REMOVE	0x0080000000000000ull
#define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
#define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
#define XCT_MACTX_CRC_M		0x0060000000000000ull
#define XCT_MACTX_CRC_NOP	0x0000000000000000ull
#define XCT_MACTX_CRC_INSERT	0x0020000000000000ull
#define XCT_MACTX_CRC_PAD	0x0040000000000000ull
#define XCT_MACTX_CRC_REPLACE	0x0060000000000000ull
#define XCT_MACTX_SS		0x0010000000000000ull
#define XCT_MACTX_LLEN_M	0x00007fff00000000ull
#define XCT_MACTX_LLEN_S	32ull
#define XCT_MACTX_LLEN(x)	((((long)(x)) << XCT_MACTX_LLEN_S) & \
				 XCT_MACTX_LLEN_M)
#define XCT_MACTX_IPH_M		0x00000000f8000000ull
#define XCT_MACTX_IPH_S		27ull
#define XCT_MACTX_IPH(x)	((((long)(x)) << XCT_MACTX_IPH_S) & \
				 XCT_MACTX_IPH_M)
#define XCT_MACTX_IPO_M		0x0000000007c00000ull
#define XCT_MACTX_IPO_S		22ull
#define XCT_MACTX_IPO(x)	((((long)(x)) << XCT_MACTX_IPO_S) & \
				 XCT_MACTX_IPO_M)
#define XCT_MACTX_CSUM_M	0x0000000000000060ull
#define XCT_MACTX_CSUM_NOP	0x0000000000000000ull
#define XCT_MACTX_CSUM_TCP	0x0000000000000040ull
#define XCT_MACTX_CSUM_UDP	0x0000000000000060ull
#define XCT_MACTX_V6		0x0000000000000010ull
#define XCT_MACTX_C		0x0000000000000004ull
#define XCT_MACTX_AL2		0x0000000000000002ull

/* Receive descriptor fields */
#define	XCT_MACRX_T		0x8000000000000000ull
#define	XCT_MACRX_ST		0x4000000000000000ull
#define XCT_MACRX_NORES		0x0000000000000000ull
#define XCT_MACRX_8BRES		0x1000000000000000ull
#define XCT_MACRX_24BRES	0x2000000000000000ull
#define XCT_MACRX_40BRES	0x3000000000000000ull
#define XCT_MACRX_O		0x0400000000000000ull
#define XCT_MACRX_E		0x0200000000000000ull
#define XCT_MACRX_FF		0x0100000000000000ull
#define XCT_MACRX_PF		0x0080000000000000ull
#define XCT_MACRX_OB		0x0040000000000000ull
#define XCT_MACRX_OD		0x0020000000000000ull
#define XCT_MACRX_FS		0x0010000000000000ull
#define XCT_MACRX_NB_M		0x000fc00000000000ull
#define XCT_MACRX_NB_S		46ULL
#define XCT_MACRX_NB(x)		((((long)(x)) << XCT_MACRX_NB_S) & \
				 XCT_MACRX_NB_M)
#define XCT_MACRX_LLEN_M	0x00003fff00000000ull
#define XCT_MACRX_LLEN_S	32ULL
#define XCT_MACRX_LLEN(x)	((((long)(x)) << XCT_MACRX_LLEN_S) & \
				 XCT_MACRX_LLEN_M)
#define XCT_MACRX_CRC		0x0000000080000000ull
#define XCT_MACRX_LEN_M		0x0000000060000000ull
#define XCT_MACRX_LEN_TOOSHORT	0x0000000020000000ull
#define XCT_MACRX_LEN_BELOWMIN	0x0000000040000000ull
#define XCT_MACRX_LEN_TRUNC	0x0000000060000000ull
#define XCT_MACRX_CAST_M	0x0000000018000000ull
#define XCT_MACRX_CAST_UNI	0x0000000000000000ull
#define XCT_MACRX_CAST_MULTI	0x0000000008000000ull
#define XCT_MACRX_CAST_BROAD	0x0000000010000000ull
#define XCT_MACRX_CAST_PAUSE	0x0000000018000000ull
#define XCT_MACRX_VLC_M		0x0000000006000000ull
#define XCT_MACRX_FM		0x0000000001000000ull
#define XCT_MACRX_HTY_M		0x0000000000c00000ull
#define XCT_MACRX_HTY_IPV4_OK	0x0000000000000000ull
#define XCT_MACRX_HTY_IPV6 	0x0000000000400000ull
#define XCT_MACRX_HTY_IPV4_BAD	0x0000000000800000ull
#define XCT_MACRX_HTY_NONIP	0x0000000000c00000ull
#define XCT_MACRX_IPP_M		0x00000000003f0000ull
#define XCT_MACRX_IPP_S		16
#define XCT_MACRX_CSUM_M	0x000000000000ffffull
#define XCT_MACRX_CSUM_S	0

#define XCT_PTR_T		0x8000000000000000ull
#define XCT_PTR_LEN_M		0x7ffff00000000000ull
#define XCT_PTR_LEN_S		44
#define XCT_PTR_LEN(x)		((((long)(x)) << XCT_PTR_LEN_S) & \
				 XCT_PTR_LEN_M)
#define XCT_PTR_ADDR_M		0x00000fffffffffffull
#define XCT_PTR_ADDR_S		0
#define XCT_PTR_ADDR(x)		((((long)(x)) << XCT_PTR_ADDR_S) & \
				 XCT_PTR_ADDR_M)

/* Receive interface buffer fields */
#define XCT_RXB_LEN_M		0x0ffff00000000000ull
#define XCT_RXB_LEN_S		44
#define XCT_RXB_LEN(x)		((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
#define XCT_RXB_ADDR_M		0x00000fffffffffffull
#define XCT_RXB_ADDR_S		0
#define XCT_RXB_ADDR(x)		((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)


#endif /* PASEMI_MAC_H */
Commit	Line	Data
f5cd7872 OJ	1	/*
	2	* Copyright (C) 2006 PA Semi, Inc
	3	*
	4	* Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
	5	* hardware register layouts.
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20
	21	#ifndef PASEMI_MAC_H
	22	#define PASEMI_MAC_H
	23
	24	#include <linux/ethtool.h>
	25	#include <linux/netdevice.h>
	26	#include <linux/spinlock.h>
bb6e9590	27	#include <linux/phy.h>
f5cd7872 OJ	28
	29	struct pasemi_mac_txring {
	30	spinlock_t lock;
	31	struct pas_dma_xct_descr *desc;
	32	dma_addr_t dma;
	33	unsigned int size;
	34	unsigned int next_to_use;
	35	unsigned int next_to_clean;
	36	struct pasemi_mac_buffer *desc_info;
	37	char irq_name[10]; /* "eth%d tx" */
	38	};
	39
	40	struct pasemi_mac_rxring {
	41	spinlock_t lock;
	42	struct pas_dma_xct_descr desc; / RX channel descriptor ring */
	43	dma_addr_t dma;
	44	u64 buffers; / RX interface buffer ring */
	45	dma_addr_t buf_dma;
	46	unsigned int size;
	47	unsigned int next_to_fill;
	48	unsigned int next_to_clean;
	49	struct pasemi_mac_buffer *desc_info;
	50	char irq_name[10]; /* "eth%d rx" */
	51	};
	52
	53	struct pasemi_mac {
	54	struct net_device *netdev;
	55	struct pci_dev *pdev;
	56	struct pci_dev *dma_pdev;
	57	struct pci_dev *iob_pdev;
bb6e9590	58	struct phy_device *phydev;
bea3348e	59	struct napi_struct napi;
f5cd7872 OJ	60	struct net_device_stats stats;
	61
	62	/* Pointer to the cacheable per-channel status registers */
	63	u64 *rx_status;
	64	u64 *tx_status;
	65
	66	u8 type;
	67	#define MAC_TYPE_GMAC 1
	68	#define MAC_TYPE_XAUI 2
	69	u32 dma_txch;
	70	u32 dma_if;
	71	u32 dma_rxch;
	72
	73	u8 mac_addr[6];
	74
	75	struct timer_list rxtimer;
	76
	77	struct pasemi_mac_txring *tx;
	78	struct pasemi_mac_rxring *rx;
771f7404 OJ	79	unsigned long tx_irq;
771f7404 OJ	80	unsigned long rx_irq;
bb6e9590 OJ	81	int link;
	82	int speed;
	83	int duplex;
ceb51361 OJ	84
ceb51361 OJ	85	unsigned int msg_enable;
bb6e9590	86	char phy_id[BUS_ID_SIZE];
f5cd7872 OJ	87	};
	88
	89	/* Software status descriptor (desc_info) */
	90	struct pasemi_mac_buffer {
	91	struct sk_buff *skb;
	92	dma_addr_t dma;
	93	};
	94
	95
	96	/* status register layout in IOB region, at 0xfb800000 */
	97	struct pasdma_status {
	98	u64 rx_sta[64];
	99	u64 tx_sta[20];
	100	};
	101
	102	/* descriptor structure */
	103	struct pas_dma_xct_descr {
	104	union {
	105	u64 mactx;
	106	u64 macrx;
	107	};
	108	union {
	109	u64 ptr;
	110	u64 rxb;
	111	};
	112	};
	113
	114	/* MAC CFG register offsets */
	115
	116	enum {
	117	PAS_MAC_CFG_PCFG = 0x80,
	118	PAS_MAC_CFG_TXP = 0x98,
	119	PAS_MAC_IPC_CHNL = 0x208,
	120	};
	121
	122	/* MAC CFG register fields */
	123	#define PAS_MAC_CFG_PCFG_PE 0x80000000
	124	#define PAS_MAC_CFG_PCFG_CE 0x40000000
	125	#define PAS_MAC_CFG_PCFG_BU 0x20000000
	126	#define PAS_MAC_CFG_PCFG_TT 0x10000000
	127	#define PAS_MAC_CFG_PCFG_TSR_M 0x0c000000
	128	#define PAS_MAC_CFG_PCFG_TSR_10M 0x00000000
	129	#define PAS_MAC_CFG_PCFG_TSR_100M 0x04000000
	130	#define PAS_MAC_CFG_PCFG_TSR_1G 0x08000000
	131	#define PAS_MAC_CFG_PCFG_TSR_10G 0x0c000000
	132	#define PAS_MAC_CFG_PCFG_T24 0x02000000
	133	#define PAS_MAC_CFG_PCFG_PR 0x01000000
	134	#define PAS_MAC_CFG_PCFG_CRO_M 0x00ff0000
	135	#define PAS_MAC_CFG_PCFG_CRO_S 16
	136	#define PAS_MAC_CFG_PCFG_IPO_M 0x0000ff00
	137	#define PAS_MAC_CFG_PCFG_IPO_S 8
	138	#define PAS_MAC_CFG_PCFG_S1 0x00000080
	139	#define PAS_MAC_CFG_PCFG_IO_M 0x00000060
	140	#define PAS_MAC_CFG_PCFG_IO_MAC 0x00000000
	141	#define PAS_MAC_CFG_PCFG_IO_OFF 0x00000020
	142	#define PAS_MAC_CFG_PCFG_IO_IND_ETH 0x00000040
	143	#define PAS_MAC_CFG_PCFG_IO_IND_IP 0x00000060
	144	#define PAS_MAC_CFG_PCFG_LP 0x00000010
	145	#define PAS_MAC_CFG_PCFG_TS 0x00000008
	146	#define PAS_MAC_CFG_PCFG_HD 0x00000004
	147	#define PAS_MAC_CFG_PCFG_SPD_M 0x00000003
	148	#define PAS_MAC_CFG_PCFG_SPD_10M 0x00000000
	149	#define PAS_MAC_CFG_PCFG_SPD_100M 0x00000001
	150	#define PAS_MAC_CFG_PCFG_SPD_1G 0x00000002
151	#define PAS_MAC_CFG_PCFG_SPD_10G 0x00000003
152	#define PAS_MAC_CFG_TXP_FCF 0x01000000
153	#define PAS_MAC_CFG_TXP_FCE 0x00800000
154	#define PAS_MAC_CFG_TXP_FC 0x00400000
155	#define PAS_MAC_CFG_TXP_FPC_M 0x00300000
156	#define PAS_MAC_CFG_TXP_FPC_S 20
157	#define PAS_MAC_CFG_TXP_FPC(x) (((x) << PAS_MAC_CFG_TXP_FPC_S) & \
158	PAS_MAC_CFG_TXP_FPC_M)
159	#define PAS_MAC_CFG_TXP_RT 0x00080000
160	#define PAS_MAC_CFG_TXP_BL 0x00040000
161	#define PAS_MAC_CFG_TXP_SL_M 0x00030000
162	#define PAS_MAC_CFG_TXP_SL_S 16
163	#define PAS_MAC_CFG_TXP_SL(x) (((x) << PAS_MAC_CFG_TXP_SL_S) & \
164	PAS_MAC_CFG_TXP_SL_M)
165	#define PAS_MAC_CFG_TXP_COB_M 0x0000f000
166	#define PAS_MAC_CFG_TXP_COB_S 12
167	#define PAS_MAC_CFG_TXP_COB(x) (((x) << PAS_MAC_CFG_TXP_COB_S) & \
168	PAS_MAC_CFG_TXP_COB_M)
169	#define PAS_MAC_CFG_TXP_TIFT_M 0x00000f00
170	#define PAS_MAC_CFG_TXP_TIFT_S 8
171	#define PAS_MAC_CFG_TXP_TIFT(x) (((x) << PAS_MAC_CFG_TXP_TIFT_S) & \
172	PAS_MAC_CFG_TXP_TIFT_M)
173	#define PAS_MAC_CFG_TXP_TIFG_M 0x000000ff
174	#define PAS_MAC_CFG_TXP_TIFG_S 0
175	#define PAS_MAC_CFG_TXP_TIFG(x) (((x) << PAS_MAC_CFG_TXP_TIFG_S) & \
176	PAS_MAC_CFG_TXP_TIFG_M)
177
178	#define PAS_MAC_IPC_CHNL_DCHNO_M 0x003f0000
179	#define PAS_MAC_IPC_CHNL_DCHNO_S 16
180	#define PAS_MAC_IPC_CHNL_DCHNO(x) (((x) << PAS_MAC_IPC_CHNL_DCHNO_S) & \
181	PAS_MAC_IPC_CHNL_DCHNO_M)
182	#define PAS_MAC_IPC_CHNL_BCH_M 0x0000003f
183	#define PAS_MAC_IPC_CHNL_BCH_S 0
184	#define PAS_MAC_IPC_CHNL_BCH(x) (((x) << PAS_MAC_IPC_CHNL_BCH_S) & \
185	PAS_MAC_IPC_CHNL_BCH_M)
186
187	/* All these registers live in the PCI configuration space for the DMA PCI
188	* device. Use the normal PCI config access functions for them.
189	*/
190	enum {
191	PAS_DMA_COM_TXCMD = 0x100, /* Transmit Command Register */
192	PAS_DMA_COM_TXSTA = 0x104, /* Transmit Status Register */
193	PAS_DMA_COM_RXCMD = 0x108, /* Receive Command Register */
194	PAS_DMA_COM_RXSTA = 0x10c, /* Receive Status Register */
195	};
196	#define PAS_DMA_COM_TXCMD_EN 0x00000001 /* enable */
197	#define PAS_DMA_COM_TXSTA_ACT 0x00000001 /* active */
198	#define PAS_DMA_COM_RXCMD_EN 0x00000001 /* enable */
199	#define PAS_DMA_COM_RXSTA_ACT 0x00000001 /* active */
200
201
202	/* Per-interface and per-channel registers */
203	#define _PAS_DMA_RXINT_STRIDE 0x20
204	#define PAS_DMA_RXINT_RCMDSTA(i) (0x200+(i)*_PAS_DMA_RXINT_STRIDE)
205	#define PAS_DMA_RXINT_RCMDSTA_EN 0x00000001
206	#define PAS_DMA_RXINT_RCMDSTA_ST 0x00000002
cfa8007d OJ	207	#define PAS_DMA_RXINT_RCMDSTA_MBT 0x00000008
	208	#define PAS_DMA_RXINT_RCMDSTA_MDR 0x00000010
	209	#define PAS_DMA_RXINT_RCMDSTA_MOO 0x00000020
	210	#define PAS_DMA_RXINT_RCMDSTA_MBP 0x00000040
f5cd7872	211	#define PAS_DMA_RXINT_RCMDSTA_BT 0x00000800
cfa8007d OJ	212	#define PAS_DMA_RXINT_RCMDSTA_DR 0x00001000
	213	#define PAS_DMA_RXINT_RCMDSTA_OO 0x00002000
	214	#define PAS_DMA_RXINT_RCMDSTA_BP 0x00004000
	215	#define PAS_DMA_RXINT_RCMDSTA_TB 0x00008000
f5cd7872 OJ	216	#define PAS_DMA_RXINT_RCMDSTA_ACT 0x00010000
	217	#define PAS_DMA_RXINT_RCMDSTA_DROPS_M 0xfffe0000
	218	#define PAS_DMA_RXINT_RCMDSTA_DROPS_S 17
	219	#define PAS_DMA_RXINT_INCR(i) (0x210+(i)*_PAS_DMA_RXINT_STRIDE)
	220	#define PAS_DMA_RXINT_INCR_INCR_M 0x0000ffff
	221	#define PAS_DMA_RXINT_INCR_INCR_S 0
	222	#define PAS_DMA_RXINT_INCR_INCR(x) ((x) & 0x0000ffff)
	223	#define PAS_DMA_RXINT_BASEL(i) (0x218+(i)*_PAS_DMA_RXINT_STRIDE)
	224	#define PAS_DMA_RXINT_BASEL_BRBL(x) ((x) & ~0x3f)
	225	#define PAS_DMA_RXINT_BASEU(i) (0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
	226	#define PAS_DMA_RXINT_BASEU_BRBH(x) ((x) & 0xfff)
	227	#define PAS_DMA_RXINT_BASEU_SIZ_M 0x3fff0000 /* # of cache lines worth of buffer ring */
	228	#define PAS_DMA_RXINT_BASEU_SIZ_S 16 /* 0 = 16K */
	229	#define PAS_DMA_RXINT_BASEU_SIZ(x) (((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
	230	PAS_DMA_RXINT_BASEU_SIZ_M)
	231
	232
	233	#define _PAS_DMA_TXCHAN_STRIDE 0x20 /* Size per channel */
	234	#define _PAS_DMA_TXCHAN_TCMDSTA 0x300 /* Command / Status */
	235	#define _PAS_DMA_TXCHAN_CFG 0x304 /* Configuration */
	236	#define _PAS_DMA_TXCHAN_DSCRBU 0x308 /* Descriptor BU Allocation */
	237	#define _PAS_DMA_TXCHAN_INCR 0x310 /* Descriptor increment */
	238	#define _PAS_DMA_TXCHAN_CNT 0x314 /* Descriptor count/offset */
	239	#define _PAS_DMA_TXCHAN_BASEL 0x318 /* Descriptor ring base (low) */
	240	#define _PAS_DMA_TXCHAN_BASEU 0x31c /* (high) */
	241	#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
	242	#define PAS_DMA_TXCHAN_TCMDSTA_EN 0x00000001 /* Enabled */
	243	#define PAS_DMA_TXCHAN_TCMDSTA_ST 0x00000002 /* Stop interface */
	244	#define PAS_DMA_TXCHAN_TCMDSTA_ACT 0x00010000 /* Active */
	245	#define PAS_DMA_TXCHAN_CFG(c) (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
	246	#define PAS_DMA_TXCHAN_CFG_TY_IFACE 0x00000000 /* Type = interface */
	247	#define PAS_DMA_TXCHAN_CFG_TATTR_M 0x0000003c
	248	#define PAS_DMA_TXCHAN_CFG_TATTR_S 2
	249	#define PAS_DMA_TXCHAN_CFG_TATTR(x) (((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
	250	PAS_DMA_TXCHAN_CFG_TATTR_M)
	251	#define PAS_DMA_TXCHAN_CFG_WT_M 0x000001c0
	252	#define PAS_DMA_TXCHAN_CFG_WT_S 6
	253	#define PAS_DMA_TXCHAN_CFG_WT(x) (((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
	254	PAS_DMA_TXCHAN_CFG_WT_M)
	255	#define PAS_DMA_TXCHAN_CFG_CF 0x00001000 /* Clean first line */
	256	#define PAS_DMA_TXCHAN_CFG_CL 0x00002000 /* Clean last line */
	257	#define PAS_DMA_TXCHAN_CFG_UP 0x00004000 /* update tx descr when sent */
	258	#define PAS_DMA_TXCHAN_INCR(c) (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
	259	#define PAS_DMA_TXCHAN_BASEL(c) (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
	260	#define PAS_DMA_TXCHAN_BASEL_BRBL_M 0xffffffc0
	261	#define PAS_DMA_TXCHAN_BASEL_BRBL_S 0
	262	#define PAS_DMA_TXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
	263	PAS_DMA_TXCHAN_BASEL_BRBL_M)
	264	#define PAS_DMA_TXCHAN_BASEU(c) (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
	265	#define PAS_DMA_TXCHAN_BASEU_BRBH_M 0x00000fff
	266	#define PAS_DMA_TXCHAN_BASEU_BRBH_S 0
	267	#define PAS_DMA_TXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
	268	PAS_DMA_TXCHAN_BASEU_BRBH_M)
	269	/* # of cache lines worth of buffer ring */
	270	#define PAS_DMA_TXCHAN_BASEU_SIZ_M 0x3fff0000
	271	#define PAS_DMA_TXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
	272	#define PAS_DMA_TXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
	273	PAS_DMA_TXCHAN_BASEU_SIZ_M)
	274
	275	#define _PAS_DMA_RXCHAN_STRIDE 0x20 /* Size per channel */
	276	#define _PAS_DMA_RXCHAN_CCMDSTA 0x800 /* Command / Status */
	277	#define _PAS_DMA_RXCHAN_CFG 0x804 /* Configuration */
	278	#define _PAS_DMA_RXCHAN_INCR 0x810 /* Descriptor increment */
	279	#define _PAS_DMA_RXCHAN_CNT 0x814 /* Descriptor count/offset */
280	#define _PAS_DMA_RXCHAN_BASEL 0x818 /* Descriptor ring base (low) */
281	#define _PAS_DMA_RXCHAN_BASEU 0x81c /* (high) */
282	#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
283	#define PAS_DMA_RXCHAN_CCMDSTA_EN 0x00000001 /* Enabled */
284	#define PAS_DMA_RXCHAN_CCMDSTA_ST 0x00000002 /* Stop interface */
285	#define PAS_DMA_RXCHAN_CCMDSTA_ACT 0x00010000 /* Active */
286	#define PAS_DMA_RXCHAN_CCMDSTA_DU 0x00020000
287	#define PAS_DMA_RXCHAN_CFG(c) (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
288	#define PAS_DMA_RXCHAN_CFG_HBU_M 0x00000380
289	#define PAS_DMA_RXCHAN_CFG_HBU_S 7
290	#define PAS_DMA_RXCHAN_CFG_HBU(x) (((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
291	PAS_DMA_RXCHAN_CFG_HBU_M)
292	#define PAS_DMA_RXCHAN_INCR(c) (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
293	#define PAS_DMA_RXCHAN_BASEL(c) (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
294	#define PAS_DMA_RXCHAN_BASEL_BRBL_M 0xffffffc0
295	#define PAS_DMA_RXCHAN_BASEL_BRBL_S 0
296	#define PAS_DMA_RXCHAN_BASEL_BRBL(x) (((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
297	PAS_DMA_RXCHAN_BASEL_BRBL_M)
298	#define PAS_DMA_RXCHAN_BASEU(c) (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
299	#define PAS_DMA_RXCHAN_BASEU_BRBH_M 0x00000fff
300	#define PAS_DMA_RXCHAN_BASEU_BRBH_S 0
301	#define PAS_DMA_RXCHAN_BASEU_BRBH(x) (((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
302	PAS_DMA_RXCHAN_BASEU_BRBH_M)
303	/* # of cache lines worth of buffer ring */
304	#define PAS_DMA_RXCHAN_BASEU_SIZ_M 0x3fff0000
305	#define PAS_DMA_RXCHAN_BASEU_SIZ_S 16 /* 0 = 16K */
306	#define PAS_DMA_RXCHAN_BASEU_SIZ(x) (((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
307	PAS_DMA_RXCHAN_BASEU_SIZ_M)
308
309	#define PAS_STATUS_PCNT_M 0x000000000000ffffull
310	#define PAS_STATUS_PCNT_S 0
311	#define PAS_STATUS_DCNT_M 0x00000000ffff0000ull
312	#define PAS_STATUS_DCNT_S 16
313	#define PAS_STATUS_BPCNT_M 0x0000ffff00000000ull
314	#define PAS_STATUS_BPCNT_S 32
6dfa7522	315	#define PAS_STATUS_CAUSE_M 0xf000000000000000ull
f5cd7872 OJ	316	#define PAS_STATUS_TIMER 0x1000000000000000ull
	317	#define PAS_STATUS_ERROR 0x2000000000000000ull
	318	#define PAS_STATUS_SOFT 0x4000000000000000ull
	319	#define PAS_STATUS_INT 0x8000000000000000ull
	320
	321	#define PAS_IOB_DMA_RXCH_CFG(i) (0x1100 + (i)*4)
	322	#define PAS_IOB_DMA_RXCH_CFG_CNTTH_M 0x00000fff
	323	#define PAS_IOB_DMA_RXCH_CFG_CNTTH_S 0
	324	#define PAS_IOB_DMA_RXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
	325	PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
	326	#define PAS_IOB_DMA_TXCH_CFG(i) (0x1200 + (i)*4)
	327	#define PAS_IOB_DMA_TXCH_CFG_CNTTH_M 0x00000fff
	328	#define PAS_IOB_DMA_TXCH_CFG_CNTTH_S 0
	329	#define PAS_IOB_DMA_TXCH_CFG_CNTTH(x) (((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
	330	PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
	331	#define PAS_IOB_DMA_RXCH_STAT(i) (0x1300 + (i)*4)
	332	#define PAS_IOB_DMA_RXCH_STAT_INTGEN 0x00001000
	333	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_M 0x00000fff
	334	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL_S 0
	335	#define PAS_IOB_DMA_RXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
	336	PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
	337	#define PAS_IOB_DMA_TXCH_STAT(i) (0x1400 + (i)*4)
	338	#define PAS_IOB_DMA_TXCH_STAT_INTGEN 0x00001000
	339	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_M 0x00000fff
	340	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL_S 0
	341	#define PAS_IOB_DMA_TXCH_STAT_CNTDEL(x) (((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
	342	PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
	343	#define PAS_IOB_DMA_RXCH_RESET(i) (0x1500 + (i)*4)
	344	#define PAS_IOB_DMA_RXCH_RESET_PCNT_M 0xffff0000
a54c5451	345	#define PAS_IOB_DMA_RXCH_RESET_PCNT_S 16
f5cd7872 OJ	346	#define PAS_IOB_DMA_RXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
	347	PAS_IOB_DMA_RXCH_RESET_PCNT_M)
	348	#define PAS_IOB_DMA_RXCH_RESET_PCNTRST 0x00000020
	349	#define PAS_IOB_DMA_RXCH_RESET_DCNTRST 0x00000010
	350	#define PAS_IOB_DMA_RXCH_RESET_TINTC 0x00000008
	351	#define PAS_IOB_DMA_RXCH_RESET_DINTC 0x00000004
	352	#define PAS_IOB_DMA_RXCH_RESET_SINTC 0x00000002
	353	#define PAS_IOB_DMA_RXCH_RESET_PINTC 0x00000001
	354	#define PAS_IOB_DMA_TXCH_RESET(i) (0x1600 + (i)*4)
	355	#define PAS_IOB_DMA_TXCH_RESET_PCNT_M 0xffff0000
a54c5451	356	#define PAS_IOB_DMA_TXCH_RESET_PCNT_S 16
f5cd7872 OJ	357	#define PAS_IOB_DMA_TXCH_RESET_PCNT(x) (((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
	358	PAS_IOB_DMA_TXCH_RESET_PCNT_M)
	359	#define PAS_IOB_DMA_TXCH_RESET_PCNTRST 0x00000020
	360	#define PAS_IOB_DMA_TXCH_RESET_DCNTRST 0x00000010
	361	#define PAS_IOB_DMA_TXCH_RESET_TINTC 0x00000008
	362	#define PAS_IOB_DMA_TXCH_RESET_DINTC 0x00000004
	363	#define PAS_IOB_DMA_TXCH_RESET_SINTC 0x00000002
	364	#define PAS_IOB_DMA_TXCH_RESET_PINTC 0x00000001
	365
	366	#define PAS_IOB_DMA_COM_TIMEOUTCFG 0x1700
	367	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M 0x00ffffff
	368	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S 0
	369	#define PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x) (((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
	370	PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)
	371
	372	/* Transmit descriptor fields */
	373	#define XCT_MACTX_T 0x8000000000000000ull
	374	#define XCT_MACTX_ST 0x4000000000000000ull
	375	#define XCT_MACTX_NORES 0x0000000000000000ull
	376	#define XCT_MACTX_8BRES 0x1000000000000000ull
	377	#define XCT_MACTX_24BRES 0x2000000000000000ull
	378	#define XCT_MACTX_40BRES 0x3000000000000000ull
	379	#define XCT_MACTX_I 0x0800000000000000ull
	380	#define XCT_MACTX_O 0x0400000000000000ull
	381	#define XCT_MACTX_E 0x0200000000000000ull
	382	#define XCT_MACTX_VLAN_M 0x0180000000000000ull
	383	#define XCT_MACTX_VLAN_NOP 0x0000000000000000ull
	384	#define XCT_MACTX_VLAN_REMOVE 0x0080000000000000ull
	385	#define XCT_MACTX_VLAN_INSERT 0x0100000000000000ull
	386	#define XCT_MACTX_VLAN_REPLACE 0x0180000000000000ull
	387	#define XCT_MACTX_CRC_M 0x0060000000000000ull
	388	#define XCT_MACTX_CRC_NOP 0x0000000000000000ull
	389	#define XCT_MACTX_CRC_INSERT 0x0020000000000000ull
	390	#define XCT_MACTX_CRC_PAD 0x0040000000000000ull
	391	#define XCT_MACTX_CRC_REPLACE 0x0060000000000000ull
	392	#define XCT_MACTX_SS 0x0010000000000000ull
	393	#define XCT_MACTX_LLEN_M 0x00007fff00000000ull
	394	#define XCT_MACTX_LLEN_S 32ull
	395	#define XCT_MACTX_LLEN(x) ((((long)(x)) << XCT_MACTX_LLEN_S) & \
	396	XCT_MACTX_LLEN_M)
	397	#define XCT_MACTX_IPH_M 0x00000000f8000000ull
	398	#define XCT_MACTX_IPH_S 27ull
	399	#define XCT_MACTX_IPH(x) ((((long)(x)) << XCT_MACTX_IPH_S) & \
	400	XCT_MACTX_IPH_M)
	401	#define XCT_MACTX_IPO_M 0x0000000007c00000ull
	402	#define XCT_MACTX_IPO_S 22ull
	403	#define XCT_MACTX_IPO(x) ((((long)(x)) << XCT_MACTX_IPO_S) & \
	404	XCT_MACTX_IPO_M)
	405	#define XCT_MACTX_CSUM_M 0x0000000000000060ull
	406	#define XCT_MACTX_CSUM_NOP 0x0000000000000000ull
	407	#define XCT_MACTX_CSUM_TCP 0x0000000000000040ull
	408	#define XCT_MACTX_CSUM_UDP 0x0000000000000060ull
	409	#define XCT_MACTX_V6 0x0000000000000010ull
	410	#define XCT_MACTX_C 0x0000000000000004ull
	411	#define XCT_MACTX_AL2 0x0000000000000002ull
	412
	413	/* Receive descriptor fields */
	414	#define XCT_MACRX_T 0x8000000000000000ull
	415	#define XCT_MACRX_ST 0x4000000000000000ull
	416	#define XCT_MACRX_NORES 0x0000000000000000ull
	417	#define XCT_MACRX_8BRES 0x1000000000000000ull
	418	#define XCT_MACRX_24BRES 0x2000000000000000ull
	419	#define XCT_MACRX_40BRES 0x3000000000000000ull
	420	#define XCT_MACRX_O 0x0400000000000000ull
421	#define XCT_MACRX_E 0x0200000000000000ull
422	#define XCT_MACRX_FF 0x0100000000000000ull
423	#define XCT_MACRX_PF 0x0080000000000000ull
424	#define XCT_MACRX_OB 0x0040000000000000ull
425	#define XCT_MACRX_OD 0x0020000000000000ull
426	#define XCT_MACRX_FS 0x0010000000000000ull
427	#define XCT_MACRX_NB_M 0x000fc00000000000ull
428	#define XCT_MACRX_NB_S 46ULL
429	#define XCT_MACRX_NB(x) ((((long)(x)) << XCT_MACRX_NB_S) & \
430	XCT_MACRX_NB_M)
431	#define XCT_MACRX_LLEN_M 0x00003fff00000000ull
432	#define XCT_MACRX_LLEN_S 32ULL
433	#define XCT_MACRX_LLEN(x) ((((long)(x)) << XCT_MACRX_LLEN_S) & \
434	XCT_MACRX_LLEN_M)
435	#define XCT_MACRX_CRC 0x0000000080000000ull
436	#define XCT_MACRX_LEN_M 0x0000000060000000ull
437	#define XCT_MACRX_LEN_TOOSHORT 0x0000000020000000ull
438	#define XCT_MACRX_LEN_BELOWMIN 0x0000000040000000ull
439	#define XCT_MACRX_LEN_TRUNC 0x0000000060000000ull
440	#define XCT_MACRX_CAST_M 0x0000000018000000ull
441	#define XCT_MACRX_CAST_UNI 0x0000000000000000ull
442	#define XCT_MACRX_CAST_MULTI 0x0000000008000000ull
443	#define XCT_MACRX_CAST_BROAD 0x0000000010000000ull
444	#define XCT_MACRX_CAST_PAUSE 0x0000000018000000ull
445	#define XCT_MACRX_VLC_M 0x0000000006000000ull
446	#define XCT_MACRX_FM 0x0000000001000000ull
447	#define XCT_MACRX_HTY_M 0x0000000000c00000ull
448	#define XCT_MACRX_HTY_IPV4_OK 0x0000000000000000ull
449	#define XCT_MACRX_HTY_IPV6 0x0000000000400000ull
450	#define XCT_MACRX_HTY_IPV4_BAD 0x0000000000800000ull
451	#define XCT_MACRX_HTY_NONIP 0x0000000000c00000ull
452	#define XCT_MACRX_IPP_M 0x00000000003f0000ull
453	#define XCT_MACRX_IPP_S 16
454	#define XCT_MACRX_CSUM_M 0x000000000000ffffull
455	#define XCT_MACRX_CSUM_S 0
456
457	#define XCT_PTR_T 0x8000000000000000ull
458	#define XCT_PTR_LEN_M 0x7ffff00000000000ull
459	#define XCT_PTR_LEN_S 44
460	#define XCT_PTR_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & \
461	XCT_PTR_LEN_M)
462	#define XCT_PTR_ADDR_M 0x00000fffffffffffull
463	#define XCT_PTR_ADDR_S 0
464	#define XCT_PTR_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & \
465	XCT_PTR_ADDR_M)
466
467	/* Receive interface buffer fields */
468	#define XCT_RXB_LEN_M 0x0ffff00000000000ull
469	#define XCT_RXB_LEN_S 44
470	#define XCT_RXB_LEN(x) ((((long)(x)) << XCT_PTR_LEN_S) & XCT_PTR_LEN_M)
471	#define XCT_RXB_ADDR_M 0x00000fffffffffffull
472	#define XCT_RXB_ADDR_S 0
473	#define XCT_RXB_ADDR(x) ((((long)(x)) << XCT_PTR_ADDR_S) & XCT_PTR_ADDR_M)
474
475
476	#endif /* PASEMI_MAC_H */