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[net-next-2.6.git] / drivers / net / niu.c
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a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/dma-mapping.h>
10#include <linux/netdevice.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/bitops.h>
16#include <linux/mii.h>
17#include <linux/if_ether.h>
18#include <linux/if_vlan.h>
19#include <linux/ip.h>
20#include <linux/in.h>
21#include <linux/ipv6.h>
22#include <linux/log2.h>
23#include <linux/jiffies.h>
24#include <linux/crc32.h>
25
26#include <linux/io.h>
27
28#ifdef CONFIG_SPARC64
29#include <linux/of_device.h>
30#endif
31
32#include "niu.h"
33
34#define DRV_MODULE_NAME "niu"
35#define PFX DRV_MODULE_NAME ": "
d8c3e23d
DM		 36#define DRV_MODULE_VERSION "1.0"
37#define DRV_MODULE_RELDATE "Nov 14, 2008"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
47#ifndef DMA_44BIT_MASK
48#define DMA_44BIT_MASK 0x00000fffffffffffULL
49#endif
50
51#ifndef readq
52static u64 readq(void __iomem *reg)
53{
e23a59e1 54 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 55}
56
57static void writeq(u64 val, void __iomem *reg)
58{
59 writel(val & 0xffffffff, reg);
60 writel(val >> 32, reg + 0x4UL);
61}
62#endif
63
64static struct pci_device_id niu_pci_tbl[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
66 {}
67};
68
69MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
70
71#define NIU_TX_TIMEOUT (5 * HZ)
72
73#define nr64(reg) readq(np->regs + (reg))
74#define nw64(reg, val) writeq((val), np->regs + (reg))
75
76#define nr64_mac(reg) readq(np->mac_regs + (reg))
77#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
78
79#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
81
82#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
84
85#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
87
88#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
89
90static int niu_debug;
91static int debug = -1;
92module_param(debug, int, 0);
93MODULE_PARM_DESC(debug, "NIU debug level");
94
95#define niudbg(TYPE, f, a...) \
96do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
98} while (0)
99
100#define niuinfo(TYPE, f, a...) \
101do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
103} while (0)
104
105#define niuwarn(TYPE, f, a...) \
106do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
108} while (0)
109
110#define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112#define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
114
5fbd7e24
MW		 115static int serdes_init_10g_serdes(struct niu *np);
116
a3138df9
DM		 117static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
118 u64 bits, int limit, int delay)
119{
120 while (--limit >= 0) {
121 u64 val = nr64_mac(reg);
122
123 if (!(val & bits))
124 break;
125 udelay(delay);
126 }
127 if (limit < 0)
128 return -ENODEV;
129 return 0;
130}
131
132static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
133 u64 bits, int limit, int delay,
134 const char *reg_name)
135{
136 int err;
137
138 nw64_mac(reg, bits);
139 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
140 if (err)
141 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np->dev->name, (unsigned long long) bits, reg_name,
144 (unsigned long long) nr64_mac(reg));
145 return err;
146}
147
148#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
151})
152
153static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
154 u64 bits, int limit, int delay)
155{
156 while (--limit >= 0) {
157 u64 val = nr64_ipp(reg);
158
159 if (!(val & bits))
160 break;
161 udelay(delay);
162 }
163 if (limit < 0)
164 return -ENODEV;
165 return 0;
166}
167
168static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
169 u64 bits, int limit, int delay,
170 const char *reg_name)
171{
172 int err;
173 u64 val;
174
175 val = nr64_ipp(reg);
176 val |= bits;
177 nw64_ipp(reg, val);
178
179 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
180 if (err)
181 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np->dev->name, (unsigned long long) bits, reg_name,
184 (unsigned long long) nr64_ipp(reg));
185 return err;
186}
187
188#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
191})
192
193static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
194 u64 bits, int limit, int delay)
195{
196 while (--limit >= 0) {
197 u64 val = nr64(reg);
198
199 if (!(val & bits))
200 break;
201 udelay(delay);
202 }
203 if (limit < 0)
204 return -ENODEV;
205 return 0;
206}
207
208#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
211})
212
213static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
214 u64 bits, int limit, int delay,
215 const char *reg_name)
216{
217 int err;
218
219 nw64(reg, bits);
220 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
221 if (err)
222 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np->dev->name, (unsigned long long) bits, reg_name,
225 (unsigned long long) nr64(reg));
226 return err;
227}
228
229#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
232})
233
234static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
235{
236 u64 val = (u64) lp->timer;
237
238 if (on)
239 val |= LDG_IMGMT_ARM;
240
241 nw64(LDG_IMGMT(lp->ldg_num), val);
242}
243
244static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
245{
246 unsigned long mask_reg, bits;
247 u64 val;
248
249 if (ldn < 0 || ldn > LDN_MAX)
250 return -EINVAL;
251
252 if (ldn < 64) {
253 mask_reg = LD_IM0(ldn);
254 bits = LD_IM0_MASK;
255 } else {
256 mask_reg = LD_IM1(ldn - 64);
257 bits = LD_IM1_MASK;
258 }
259
260 val = nr64(mask_reg);
261 if (on)
262 val &= ~bits;
263 else
264 val |= bits;
265 nw64(mask_reg, val);
266
267 return 0;
268}
269
270static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
271{
272 struct niu_parent *parent = np->parent;
273 int i;
274
275 for (i = 0; i <= LDN_MAX; i++) {
276 int err;
277
278 if (parent->ldg_map[i] != lp->ldg_num)
279 continue;
280
281 err = niu_ldn_irq_enable(np, i, on);
282 if (err)
283 return err;
284 }
285 return 0;
286}
287
288static int niu_enable_interrupts(struct niu *np, int on)
289{
290 int i;
291
292 for (i = 0; i < np->num_ldg; i++) {
293 struct niu_ldg *lp = &np->ldg[i];
294 int err;
295
296 err = niu_enable_ldn_in_ldg(np, lp, on);
297 if (err)
298 return err;
299 }
300 for (i = 0; i < np->num_ldg; i++)
301 niu_ldg_rearm(np, &np->ldg[i], on);
302
303 return 0;
304}
305
306static u32 phy_encode(u32 type, int port)
307{
308 return (type << (port * 2));
309}
310
311static u32 phy_decode(u32 val, int port)
312{
313 return (val >> (port * 2)) & PORT_TYPE_MASK;
314}
315
316static int mdio_wait(struct niu *np)
317{
318 int limit = 1000;
319 u64 val;
320
321 while (--limit > 0) {
322 val = nr64(MIF_FRAME_OUTPUT);
323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
324 return val & MIF_FRAME_OUTPUT_DATA;
325
326 udelay(10);
327 }
328
329 return -ENODEV;
330}
331
332static int mdio_read(struct niu *np, int port, int dev, int reg)
333{
334 int err;
335
336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
337 err = mdio_wait(np);
338 if (err < 0)
339 return err;
340
341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
342 return mdio_wait(np);
343}
344
345static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
346{
347 int err;
348
349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
350 err = mdio_wait(np);
351 if (err < 0)
352 return err;
353
354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
355 err = mdio_wait(np);
356 if (err < 0)
357 return err;
358
359 return 0;
360}
361
362static int mii_read(struct niu *np, int port, int reg)
363{
364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
365 return mdio_wait(np);
366}
367
368static int mii_write(struct niu *np, int port, int reg, int data)
369{
370 int err;
371
372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
373 err = mdio_wait(np);
374 if (err < 0)
375 return err;
376
377 return 0;
378}
379
380static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
381{
382 int err;
383
384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
385 ESR2_TI_PLL_TX_CFG_L(channel),
386 val & 0xffff);
387 if (!err)
388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
389 ESR2_TI_PLL_TX_CFG_H(channel),
390 val >> 16);
391 return err;
392}
393
394static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
395{
396 int err;
397
398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
399 ESR2_TI_PLL_RX_CFG_L(channel),
400 val & 0xffff);
401 if (!err)
402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
403 ESR2_TI_PLL_RX_CFG_H(channel),
404 val >> 16);
405 return err;
406}
407
408/* Mode is always 10G fiber. */
e3e081e1 409static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 410{
411 struct niu_link_config *lp = &np->link_config;
412 u32 tx_cfg, rx_cfg;
413 unsigned long i;
414
415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
418 PLL_RX_CFG_EQ_LP_ADAPTIVE);
419
420 if (lp->loopback_mode == LOOPBACK_PHY) {
421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
422
423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
424 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
425
426 tx_cfg |= PLL_TX_CFG_ENTEST;
427 rx_cfg |= PLL_RX_CFG_ENTEST;
428 }
429
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i = 0; i < 4; i++) {
432 int err = esr2_set_tx_cfg(np, i, tx_cfg);
433 if (err)
434 return err;
435 }
436
437 for (i = 0; i < 4; i++) {
438 int err = esr2_set_rx_cfg(np, i, rx_cfg);
439 if (err)
440 return err;
441 }
442
443 return 0;
444}
445
e3e081e1
SB		 446static int serdes_init_niu_1g_serdes(struct niu *np)
447{
448 struct niu_link_config *lp = &np->link_config;
449 u16 pll_cfg, pll_sts;
450 int max_retry = 100;
51e0f058 451 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 452 u32 tx_cfg, rx_cfg;
453 unsigned long i;
454 int err;
455
456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
457 PLL_TX_CFG_RATE_HALF);
458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
460 PLL_RX_CFG_RATE_HALF);
461
462 if (np->port == 0)
463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
464
465 if (lp->loopback_mode == LOOPBACK_PHY) {
466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
467
468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
469 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
470
471 tx_cfg |= PLL_TX_CFG_ENTEST;
472 rx_cfg |= PLL_RX_CFG_ENTEST;
473 }
474
475 /* Initialize PLL for 1G */
476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
477
478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
479 ESR2_TI_PLL_CFG_L, pll_cfg);
480 if (err) {
481 dev_err(np->device, PFX "NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
484 return err;
485 }
486
487 pll_sts = PLL_CFG_ENPLL;
488
489 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
490 ESR2_TI_PLL_STS_L, pll_sts);
491 if (err) {
492 dev_err(np->device, PFX "NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
495 return err;
496 }
497
498 udelay(200);
499
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i = 0; i < 4; i++) {
502 err = esr2_set_tx_cfg(np, i, tx_cfg);
503 if (err)
504 return err;
505 }
506
507 for (i = 0; i < 4; i++) {
508 err = esr2_set_rx_cfg(np, i, rx_cfg);
509 if (err)
510 return err;
511 }
512
513 switch (np->port) {
514 case 0:
515 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
516 mask = val;
517 break;
518
519 case 1:
520 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
521 mask = val;
522 break;
523
524 default:
525 return -EINVAL;
526 }
527
528 while (max_retry--) {
529 sig = nr64(ESR_INT_SIGNALS);
530 if ((sig & mask) == val)
531 break;
532
533 mdelay(500);
534 }
535
536 if ((sig & mask) != val) {
537 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
538 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
539 return -ENODEV;
540 }
541
542 return 0;
543}
544
545static int serdes_init_niu_10g_serdes(struct niu *np)
546{
547 struct niu_link_config *lp = &np->link_config;
548 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
549 int max_retry = 100;
51e0f058 550 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 551 unsigned long i;
552 int err;
553
554 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
555 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
556 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
557 PLL_RX_CFG_EQ_LP_ADAPTIVE);
558
559 if (lp->loopback_mode == LOOPBACK_PHY) {
560 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
561
562 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
564
565 tx_cfg |= PLL_TX_CFG_ENTEST;
566 rx_cfg |= PLL_RX_CFG_ENTEST;
567 }
568
569 /* Initialize PLL for 10G */
570 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
571
572 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
573 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
574 if (err) {
575 dev_err(np->device, PFX "NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np->port);
578 return err;
579 }
580
581 pll_sts = PLL_CFG_ENPLL;
582
583 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
584 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
585 if (err) {
586 dev_err(np->device, PFX "NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np->port);
589 return err;
590 }
591
592 udelay(200);
593
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i = 0; i < 4; i++) {
596 err = esr2_set_tx_cfg(np, i, tx_cfg);
597 if (err)
598 return err;
599 }
600
601 for (i = 0; i < 4; i++) {
602 err = esr2_set_rx_cfg(np, i, rx_cfg);
603 if (err)
604 return err;
605 }
606
607 /* check if serdes is ready */
608
609 switch (np->port) {
610 case 0:
611 mask = ESR_INT_SIGNALS_P0_BITS;
612 val = (ESR_INT_SRDY0_P0 |
613 ESR_INT_DET0_P0 |
614 ESR_INT_XSRDY_P0 |
615 ESR_INT_XDP_P0_CH3 |
616 ESR_INT_XDP_P0_CH2 |
617 ESR_INT_XDP_P0_CH1 |
618 ESR_INT_XDP_P0_CH0);
619 break;
620
621 case 1:
622 mask = ESR_INT_SIGNALS_P1_BITS;
623 val = (ESR_INT_SRDY0_P1 |
624 ESR_INT_DET0_P1 |
625 ESR_INT_XSRDY_P1 |
626 ESR_INT_XDP_P1_CH3 |
627 ESR_INT_XDP_P1_CH2 |
628 ESR_INT_XDP_P1_CH1 |
629 ESR_INT_XDP_P1_CH0);
630 break;
631
632 default:
633 return -EINVAL;
634 }
635
636 while (max_retry--) {
637 sig = nr64(ESR_INT_SIGNALS);
638 if ((sig & mask) == val)
639 break;
640
641 mdelay(500);
642 }
643
644 if ((sig & mask) != val) {
645 pr_info(PFX "NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np->port, (int) (sig & mask), (int) val);
648
649 /* 10G failed, try initializing at 1G */
650 err = serdes_init_niu_1g_serdes(np);
651 if (!err) {
652 np->flags &= ~NIU_FLAGS_10G;
653 np->mac_xcvr = MAC_XCVR_PCS;
654 } else {
655 dev_err(np->device, PFX "Port %u 10G/1G SERDES "
656 "Link Failed \n", np->port);
657 return -ENODEV;
658 }
659 }
660 return 0;
661}
662
a3138df9
DM		 663static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
664{
665 int err;
666
667 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
668 if (err >= 0) {
669 *val = (err & 0xffff);
670 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
671 ESR_RXTX_CTRL_H(chan));
672 if (err >= 0)
673 *val |= ((err & 0xffff) << 16);
674 err = 0;
675 }
676 return err;
677}
678
679static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
680{
681 int err;
682
683 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
684 ESR_GLUE_CTRL0_L(chan));
685 if (err >= 0) {
686 *val = (err & 0xffff);
687 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
688 ESR_GLUE_CTRL0_H(chan));
689 if (err >= 0) {
690 *val |= ((err & 0xffff) << 16);
691 err = 0;
692 }
693 }
694 return err;
695}
696
697static int esr_read_reset(struct niu *np, u32 *val)
698{
699 int err;
700
701 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
702 ESR_RXTX_RESET_CTRL_L);
703 if (err >= 0) {
704 *val = (err & 0xffff);
705 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
706 ESR_RXTX_RESET_CTRL_H);
707 if (err >= 0) {
708 *val |= ((err & 0xffff) << 16);
709 err = 0;
710 }
711 }
712 return err;
713}
714
715static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
716{
717 int err;
718
719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 ESR_RXTX_CTRL_L(chan), val & 0xffff);
721 if (!err)
722 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
723 ESR_RXTX_CTRL_H(chan), (val >> 16));
724 return err;
725}
726
727static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
728{
729 int err;
730
731 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
733 if (!err)
734 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
735 ESR_GLUE_CTRL0_H(chan), (val >> 16));
736 return err;
737}
738
739static int esr_reset(struct niu *np)
740{
f166400b 741 u32 uninitialized_var(reset);
a3138df9
DM		 742 int err;
743
744 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
745 ESR_RXTX_RESET_CTRL_L, 0x0000);
746 if (err)
747 return err;
748 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
749 ESR_RXTX_RESET_CTRL_H, 0xffff);
750 if (err)
751 return err;
752 udelay(200);
753
754 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
755 ESR_RXTX_RESET_CTRL_L, 0xffff);
756 if (err)
757 return err;
758 udelay(200);
759
760 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
761 ESR_RXTX_RESET_CTRL_H, 0x0000);
762 if (err)
763 return err;
764 udelay(200);
765
766 err = esr_read_reset(np, &reset);
767 if (err)
768 return err;
769 if (reset != 0) {
770 dev_err(np->device, PFX "Port %u ESR_RESET "
771 "did not clear [%08x]\n",
772 np->port, reset);
773 return -ENODEV;
774 }
775
776 return 0;
777}
778
779static int serdes_init_10g(struct niu *np)
780{
781 struct niu_link_config *lp = &np->link_config;
782 unsigned long ctrl_reg, test_cfg_reg, i;
783 u64 ctrl_val, test_cfg_val, sig, mask, val;
784 int err;
785
786 switch (np->port) {
787 case 0:
788 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
789 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
790 break;
791 case 1:
792 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
793 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
794 break;
795
796 default:
797 return -EINVAL;
798 }
799 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
800 ENET_SERDES_CTRL_SDET_1 |
801 ENET_SERDES_CTRL_SDET_2 |
802 ENET_SERDES_CTRL_SDET_3 |
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
811 test_cfg_val = 0;
812
813 if (lp->loopback_mode == LOOPBACK_PHY) {
814 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
815 ENET_SERDES_TEST_MD_0_SHIFT) |
816 (ENET_TEST_MD_PAD_LOOPBACK <<
817 ENET_SERDES_TEST_MD_1_SHIFT) |
818 (ENET_TEST_MD_PAD_LOOPBACK <<
819 ENET_SERDES_TEST_MD_2_SHIFT) |
820 (ENET_TEST_MD_PAD_LOOPBACK <<
821 ENET_SERDES_TEST_MD_3_SHIFT));
822 }
823
824 nw64(ctrl_reg, ctrl_val);
825 nw64(test_cfg_reg, test_cfg_val);
826
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i = 0; i < 4; i++) {
829 u32 rxtx_ctrl, glue0;
830
831 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
832 if (err)
833 return err;
834 err = esr_read_glue0(np, i, &glue0);
835 if (err)
836 return err;
837
838 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
839 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
841
842 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
843 ESR_GLUE_CTRL0_THCNT |
844 ESR_GLUE_CTRL0_BLTIME);
845 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
848 (BLTIME_300_CYCLES <<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT));
850
851 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
852 if (err)
853 return err;
854 err = esr_write_glue0(np, i, glue0);
855 if (err)
856 return err;
857 }
858
859 err = esr_reset(np);
860 if (err)
861 return err;
862
863 sig = nr64(ESR_INT_SIGNALS);
864 switch (np->port) {
865 case 0:
866 mask = ESR_INT_SIGNALS_P0_BITS;
867 val = (ESR_INT_SRDY0_P0 |
868 ESR_INT_DET0_P0 |
869 ESR_INT_XSRDY_P0 |
870 ESR_INT_XDP_P0_CH3 |
871 ESR_INT_XDP_P0_CH2 |
872 ESR_INT_XDP_P0_CH1 |
873 ESR_INT_XDP_P0_CH0);
874 break;
875
876 case 1:
877 mask = ESR_INT_SIGNALS_P1_BITS;
878 val = (ESR_INT_SRDY0_P1 |
879 ESR_INT_DET0_P1 |
880 ESR_INT_XSRDY_P1 |
881 ESR_INT_XDP_P1_CH3 |
882 ESR_INT_XDP_P1_CH2 |
883 ESR_INT_XDP_P1_CH1 |
884 ESR_INT_XDP_P1_CH0);
885 break;
886
887 default:
888 return -EINVAL;
889 }
890
891 if ((sig & mask) != val) {
a5d6ab56
MW		 892 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
893 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
894 return 0;
895 }
a3138df9
DM		 896 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
897 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
898 return -ENODEV;
899 }
a5d6ab56
MW		 900 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
901 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 902 return 0;
903}
904
905static int serdes_init_1g(struct niu *np)
906{
907 u64 val;
908
909 val = nr64(ENET_SERDES_1_PLL_CFG);
910 val &= ~ENET_SERDES_PLL_FBDIV2;
911 switch (np->port) {
912 case 0:
913 val |= ENET_SERDES_PLL_HRATE0;
914 break;
915 case 1:
916 val |= ENET_SERDES_PLL_HRATE1;
917 break;
918 case 2:
919 val |= ENET_SERDES_PLL_HRATE2;
920 break;
921 case 3:
922 val |= ENET_SERDES_PLL_HRATE3;
923 break;
924 default:
925 return -EINVAL;
926 }
927 nw64(ENET_SERDES_1_PLL_CFG, val);
928
929 return 0;
930}
931
5fbd7e24
MW		 932static int serdes_init_1g_serdes(struct niu *np)
933{
934 struct niu_link_config *lp = &np->link_config;
935 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
936 u64 ctrl_val, test_cfg_val, sig, mask, val;
937 int err;
938 u64 reset_val, val_rd;
939
940 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
941 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
942 ENET_SERDES_PLL_FBDIV0;
943 switch (np->port) {
944 case 0:
945 reset_val = ENET_SERDES_RESET_0;
946 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
947 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
948 pll_cfg = ENET_SERDES_0_PLL_CFG;
949 break;
950 case 1:
951 reset_val = ENET_SERDES_RESET_1;
952 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
953 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
954 pll_cfg = ENET_SERDES_1_PLL_CFG;
955 break;
956
957 default:
958 return -EINVAL;
959 }
960 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
961 ENET_SERDES_CTRL_SDET_1 |
962 ENET_SERDES_CTRL_SDET_2 |
963 ENET_SERDES_CTRL_SDET_3 |
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
972 test_cfg_val = 0;
973
974 if (lp->loopback_mode == LOOPBACK_PHY) {
975 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
976 ENET_SERDES_TEST_MD_0_SHIFT) |
977 (ENET_TEST_MD_PAD_LOOPBACK <<
978 ENET_SERDES_TEST_MD_1_SHIFT) |
979 (ENET_TEST_MD_PAD_LOOPBACK <<
980 ENET_SERDES_TEST_MD_2_SHIFT) |
981 (ENET_TEST_MD_PAD_LOOPBACK <<
982 ENET_SERDES_TEST_MD_3_SHIFT));
983 }
984
985 nw64(ENET_SERDES_RESET, reset_val);
986 mdelay(20);
987 val_rd = nr64(ENET_SERDES_RESET);
988 val_rd &= ~reset_val;
989 nw64(pll_cfg, val);
990 nw64(ctrl_reg, ctrl_val);
991 nw64(test_cfg_reg, test_cfg_val);
992 nw64(ENET_SERDES_RESET, val_rd);
993 mdelay(2000);
994
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i = 0; i < 4; i++) {
997 u32 rxtx_ctrl, glue0;
998
999 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
1000 if (err)
1001 return err;
1002 err = esr_read_glue0(np, i, &glue0);
1003 if (err)
1004 return err;
1005
1006 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
1007 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
1009
1010 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
1011 ESR_GLUE_CTRL0_THCNT |
1012 ESR_GLUE_CTRL0_BLTIME);
1013 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
1016 (BLTIME_300_CYCLES <<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT));
1018
1019 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
1020 if (err)
1021 return err;
1022 err = esr_write_glue0(np, i, glue0);
1023 if (err)
1024 return err;
1025 }
1026
1027
1028 sig = nr64(ESR_INT_SIGNALS);
1029 switch (np->port) {
1030 case 0:
1031 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1032 mask = val;
1033 break;
1034
1035 case 1:
1036 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1037 mask = val;
1038 break;
1039
1040 default:
1041 return -EINVAL;
1042 }
1043
1044 if ((sig & mask) != val) {
1045 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
1047 return -ENODEV;
1048 }
1049
1050 return 0;
1051}
1052
1053static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1054{
1055 struct niu_link_config *lp = &np->link_config;
1056 int link_up;
1057 u64 val;
1058 u16 current_speed;
1059 unsigned long flags;
1060 u8 current_duplex;
1061
1062 link_up = 0;
1063 current_speed = SPEED_INVALID;
1064 current_duplex = DUPLEX_INVALID;
1065
1066 spin_lock_irqsave(&np->lock, flags);
1067
1068 val = nr64_pcs(PCS_MII_STAT);
1069
1070 if (val & PCS_MII_STAT_LINK_STATUS) {
1071 link_up = 1;
1072 current_speed = SPEED_1000;
1073 current_duplex = DUPLEX_FULL;
1074 }
1075
1076 lp->active_speed = current_speed;
1077 lp->active_duplex = current_duplex;
1078 spin_unlock_irqrestore(&np->lock, flags);
1079
1080 *link_up_p = link_up;
1081 return 0;
1082}
1083
5fbd7e24
MW		 1084static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1085{
1086 unsigned long flags;
1087 struct niu_link_config *lp = &np->link_config;
1088 int link_up = 0;
1089 int link_ok = 1;
1090 u64 val, val2;
1091 u16 current_speed;
1092 u8 current_duplex;
1093
1094 if (!(np->flags & NIU_FLAGS_10G))
1095 return link_status_1g_serdes(np, link_up_p);
1096
1097 current_speed = SPEED_INVALID;
1098 current_duplex = DUPLEX_INVALID;
1099 spin_lock_irqsave(&np->lock, flags);
1100
1101 val = nr64_xpcs(XPCS_STATUS(0));
1102 val2 = nr64_mac(XMAC_INTER2);
1103 if (val2 & 0x01000000)
1104 link_ok = 0;
1105
1106 if ((val & 0x1000ULL) && link_ok) {
1107 link_up = 1;
1108 current_speed = SPEED_10000;
1109 current_duplex = DUPLEX_FULL;
1110 }
1111 lp->active_speed = current_speed;
1112 lp->active_duplex = current_duplex;
1113 spin_unlock_irqrestore(&np->lock, flags);
1114 *link_up_p = link_up;
1115 return 0;
1116}
1117
5fbd7e24
MW		 1118static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1119{
1120 struct niu_link_config *lp = &np->link_config;
1121 u16 current_speed, bmsr;
1122 unsigned long flags;
1123 u8 current_duplex;
1124 int err, link_up;
1125
1126 link_up = 0;
1127 current_speed = SPEED_INVALID;
1128 current_duplex = DUPLEX_INVALID;
1129
1130 spin_lock_irqsave(&np->lock, flags);
1131
1132 err = -EINVAL;
1133
1134 err = mii_read(np, np->phy_addr, MII_BMSR);
1135 if (err < 0)
1136 goto out;
1137
1138 bmsr = err;
1139 if (bmsr & BMSR_LSTATUS) {
1140 u16 adv, lpa, common, estat;
1141
1142 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1143 if (err < 0)
1144 goto out;
1145 adv = err;
1146
1147 err = mii_read(np, np->phy_addr, MII_LPA);
1148 if (err < 0)
1149 goto out;
1150 lpa = err;
1151
1152 common = adv & lpa;
1153
1154 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1155 if (err < 0)
1156 goto out;
1157 estat = err;
1158 link_up = 1;
1159 current_speed = SPEED_1000;
1160 current_duplex = DUPLEX_FULL;
1161
1162 }
1163 lp->active_speed = current_speed;
1164 lp->active_duplex = current_duplex;
1165 err = 0;
1166
1167out:
1168 spin_unlock_irqrestore(&np->lock, flags);
1169
1170 *link_up_p = link_up;
1171 return err;
1172}
1173
a3138df9
DM		 1174static int bcm8704_reset(struct niu *np)
1175{
1176 int err, limit;
1177
1178 err = mdio_read(np, np->phy_addr,
1179 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1180 if (err < 0)
1181 return err;
1182 err |= BMCR_RESET;
1183 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1184 MII_BMCR, err);
1185 if (err)
1186 return err;
1187
1188 limit = 1000;
1189 while (--limit >= 0) {
1190 err = mdio_read(np, np->phy_addr,
1191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1192 if (err < 0)
1193 return err;
1194 if (!(err & BMCR_RESET))
1195 break;
1196 }
1197 if (limit < 0) {
1198 dev_err(np->device, PFX "Port %u PHY will not reset "
1199 "(bmcr=%04x)\n", np->port, (err & 0xffff));
1200 return -ENODEV;
1201 }
1202 return 0;
1203}
1204
1205/* When written, certain PHY registers need to be read back twice
1206 * in order for the bits to settle properly.
1207 */
1208static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1209{
1210 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1211 if (err < 0)
1212 return err;
1213 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1214 if (err < 0)
1215 return err;
1216 return 0;
1217}
1218
a5d6ab56
MW		 1219static int bcm8706_init_user_dev3(struct niu *np)
1220{
1221 int err;
1222
1223
1224 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1225 BCM8704_USER_OPT_DIGITAL_CTRL);
1226 if (err < 0)
1227 return err;
1228 err &= ~USER_ODIG_CTRL_GPIOS;
1229 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1230 err |= USER_ODIG_CTRL_RESV2;
1231 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1232 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1233 if (err)
1234 return err;
1235
1236 mdelay(1000);
1237
1238 return 0;
1239}
1240
a3138df9
DM		 1241static int bcm8704_init_user_dev3(struct niu *np)
1242{
1243 int err;
1244
1245 err = mdio_write(np, np->phy_addr,
1246 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1247 (USER_CONTROL_OPTXRST_LVL |
1248 USER_CONTROL_OPBIASFLT_LVL |
1249 USER_CONTROL_OBTMPFLT_LVL |
1250 USER_CONTROL_OPPRFLT_LVL |
1251 USER_CONTROL_OPTXFLT_LVL |
1252 USER_CONTROL_OPRXLOS_LVL |
1253 USER_CONTROL_OPRXFLT_LVL |
1254 USER_CONTROL_OPTXON_LVL |
1255 (0x3f << USER_CONTROL_RES1_SHIFT)));
1256 if (err)
1257 return err;
1258
1259 err = mdio_write(np, np->phy_addr,
1260 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1261 (USER_PMD_TX_CTL_XFP_CLKEN |
1262 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1263 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1264 USER_PMD_TX_CTL_TSCK_LPWREN));
1265 if (err)
1266 return err;
1267
1268 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1269 if (err)
1270 return err;
1271 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1272 if (err)
1273 return err;
1274
1275 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1276 BCM8704_USER_OPT_DIGITAL_CTRL);
1277 if (err < 0)
1278 return err;
1279 err &= ~USER_ODIG_CTRL_GPIOS;
1280 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1281 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1282 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1283 if (err)
1284 return err;
1285
1286 mdelay(1000);
1287
1288 return 0;
1289}
1290
b0de8e40
ML		 1291static int mrvl88x2011_act_led(struct niu *np, int val)
1292{
1293 int err;
1294
1295 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1296 MRVL88X2011_LED_8_TO_11_CTL);
1297 if (err < 0)
1298 return err;
1299
1300 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1301 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1302
1303 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1304 MRVL88X2011_LED_8_TO_11_CTL, err);
1305}
1306
1307static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1308{
1309 int err;
1310
1311 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1312 MRVL88X2011_LED_BLINK_CTL);
1313 if (err >= 0) {
1314 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1315 err |= (rate << 4);
1316
1317 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1318 MRVL88X2011_LED_BLINK_CTL, err);
1319 }
1320
1321 return err;
1322}
1323
1324static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1325{
1326 int err;
1327
1328 /* Set LED functions */
1329 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1330 if (err)
1331 return err;
1332
1333 /* led activity */
1334 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1335 if (err)
1336 return err;
1337
1338 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1339 MRVL88X2011_GENERAL_CTL);
1340 if (err < 0)
1341 return err;
1342
1343 err |= MRVL88X2011_ENA_XFPREFCLK;
1344
1345 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1346 MRVL88X2011_GENERAL_CTL, err);
1347 if (err < 0)
1348 return err;
1349
1350 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1351 MRVL88X2011_PMA_PMD_CTL_1);
1352 if (err < 0)
1353 return err;
1354
1355 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1356 err |= MRVL88X2011_LOOPBACK;
1357 else
1358 err &= ~MRVL88X2011_LOOPBACK;
1359
1360 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1361 MRVL88X2011_PMA_PMD_CTL_1, err);
1362 if (err < 0)
1363 return err;
1364
1365 /* Enable PMD */
1366 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1367 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1368}
1369
a5d6ab56
MW		 1370
1371static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1372{
a3138df9 1373 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1374 int err = 0;
a3138df9
DM		 1375
1376#if 1
1377 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1378 MII_STAT1000);
1379 if (err < 0)
1380 return err;
1381 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1382 np->port, err);
1383
1384 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1385 if (err < 0)
1386 return err;
1387 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
1388 np->port, err);
1389
1390 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1391 MII_NWAYTEST);
1392 if (err < 0)
1393 return err;
1394 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1395 np->port, err);
1396#endif
1397
1398 /* XXX dig this out it might not be so useful XXX */
1399 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1400 BCM8704_USER_ANALOG_STATUS0);
1401 if (err < 0)
1402 return err;
1403 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1404 BCM8704_USER_ANALOG_STATUS0);
1405 if (err < 0)
1406 return err;
1407 analog_stat0 = err;
1408
1409 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1410 BCM8704_USER_TX_ALARM_STATUS);
1411 if (err < 0)
1412 return err;
1413 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1414 BCM8704_USER_TX_ALARM_STATUS);
1415 if (err < 0)
1416 return err;
1417 tx_alarm_status = err;
1418
1419 if (analog_stat0 != 0x03fc) {
1420 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
1421 pr_info(PFX "Port %u cable not connected "
1422 "or bad cable.\n", np->port);
1423 } else if (analog_stat0 == 0x639c) {
1424 pr_info(PFX "Port %u optical module is bad "
1425 "or missing.\n", np->port);
1426 }
1427 }
1428
1429 return 0;
1430}
1431
a5d6ab56
MW		 1432static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1433{
1434 struct niu_link_config *lp = &np->link_config;
1435 int err;
1436
1437 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1438 MII_BMCR);
1439 if (err < 0)
1440 return err;
1441
1442 err &= ~BMCR_LOOPBACK;
1443
1444 if (lp->loopback_mode == LOOPBACK_MAC)
1445 err |= BMCR_LOOPBACK;
1446
1447 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1448 MII_BMCR, err);
1449 if (err)
1450 return err;
1451
1452 return 0;
1453}
1454
1455static int xcvr_init_10g_bcm8706(struct niu *np)
1456{
1457 int err = 0;
1458 u64 val;
1459
1460 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1461 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1462 return err;
1463
1464 val = nr64_mac(XMAC_CONFIG);
1465 val &= ~XMAC_CONFIG_LED_POLARITY;
1466 val |= XMAC_CONFIG_FORCE_LED_ON;
1467 nw64_mac(XMAC_CONFIG, val);
1468
1469 val = nr64(MIF_CONFIG);
1470 val |= MIF_CONFIG_INDIRECT_MODE;
1471 nw64(MIF_CONFIG, val);
1472
1473 err = bcm8704_reset(np);
1474 if (err)
1475 return err;
1476
1477 err = xcvr_10g_set_lb_bcm870x(np);
1478 if (err)
1479 return err;
1480
1481 err = bcm8706_init_user_dev3(np);
1482 if (err)
1483 return err;
1484
1485 err = xcvr_diag_bcm870x(np);
1486 if (err)
1487 return err;
1488
1489 return 0;
1490}
1491
1492static int xcvr_init_10g_bcm8704(struct niu *np)
1493{
1494 int err;
1495
1496 err = bcm8704_reset(np);
1497 if (err)
1498 return err;
1499
1500 err = bcm8704_init_user_dev3(np);
1501 if (err)
1502 return err;
1503
1504 err = xcvr_10g_set_lb_bcm870x(np);
1505 if (err)
1506 return err;
1507
1508 err = xcvr_diag_bcm870x(np);
1509 if (err)
1510 return err;
1511
1512 return 0;
1513}
1514
b0de8e40
ML		 1515static int xcvr_init_10g(struct niu *np)
1516{
1517 int phy_id, err;
1518 u64 val;
1519
1520 val = nr64_mac(XMAC_CONFIG);
1521 val &= ~XMAC_CONFIG_LED_POLARITY;
1522 val |= XMAC_CONFIG_FORCE_LED_ON;
1523 nw64_mac(XMAC_CONFIG, val);
1524
1525 /* XXX shared resource, lock parent XXX */
1526 val = nr64(MIF_CONFIG);
1527 val |= MIF_CONFIG_INDIRECT_MODE;
1528 nw64(MIF_CONFIG, val);
1529
1530 phy_id = phy_decode(np->parent->port_phy, np->port);
1531 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1532
1533 /* handle different phy types */
1534 switch (phy_id & NIU_PHY_ID_MASK) {
1535 case NIU_PHY_ID_MRVL88X2011:
1536 err = xcvr_init_10g_mrvl88x2011(np);
1537 break;
1538
1539 default: /* bcom 8704 */
1540 err = xcvr_init_10g_bcm8704(np);
1541 break;
1542 }
1543
1544 return 0;
1545}
1546
a3138df9
DM		 1547static int mii_reset(struct niu *np)
1548{
1549 int limit, err;
1550
1551 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1552 if (err)
1553 return err;
1554
1555 limit = 1000;
1556 while (--limit >= 0) {
1557 udelay(500);
1558 err = mii_read(np, np->phy_addr, MII_BMCR);
1559 if (err < 0)
1560 return err;
1561 if (!(err & BMCR_RESET))
1562 break;
1563 }
1564 if (limit < 0) {
1565 dev_err(np->device, PFX "Port %u MII would not reset, "
1566 "bmcr[%04x]\n", np->port, err);
1567 return -ENODEV;
1568 }
1569
1570 return 0;
1571}
1572
5fbd7e24
MW		 1573static int xcvr_init_1g_rgmii(struct niu *np)
1574{
1575 int err;
1576 u64 val;
1577 u16 bmcr, bmsr, estat;
1578
1579 val = nr64(MIF_CONFIG);
1580 val &= ~MIF_CONFIG_INDIRECT_MODE;
1581 nw64(MIF_CONFIG, val);
1582
1583 err = mii_reset(np);
1584 if (err)
1585 return err;
1586
1587 err = mii_read(np, np->phy_addr, MII_BMSR);
1588 if (err < 0)
1589 return err;
1590 bmsr = err;
1591
1592 estat = 0;
1593 if (bmsr & BMSR_ESTATEN) {
1594 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1595 if (err < 0)
1596 return err;
1597 estat = err;
1598 }
1599
1600 bmcr = 0;
1601 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1602 if (err)
1603 return err;
1604
1605 if (bmsr & BMSR_ESTATEN) {
1606 u16 ctrl1000 = 0;
1607
1608 if (estat & ESTATUS_1000_TFULL)
1609 ctrl1000 |= ADVERTISE_1000FULL;
1610 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1611 if (err)
1612 return err;
1613 }
1614
1615 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1616
1617 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1618 if (err)
1619 return err;
1620
1621 err = mii_read(np, np->phy_addr, MII_BMCR);
1622 if (err < 0)
1623 return err;
1624 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1625
1626 err = mii_read(np, np->phy_addr, MII_BMSR);
1627 if (err < 0)
1628 return err;
1629
1630 return 0;
1631}
1632
a3138df9
DM		 1633static int mii_init_common(struct niu *np)
1634{
1635 struct niu_link_config *lp = &np->link_config;
1636 u16 bmcr, bmsr, adv, estat;
1637 int err;
1638
1639 err = mii_reset(np);
1640 if (err)
1641 return err;
1642
1643 err = mii_read(np, np->phy_addr, MII_BMSR);
1644 if (err < 0)
1645 return err;
1646 bmsr = err;
1647
1648 estat = 0;
1649 if (bmsr & BMSR_ESTATEN) {
1650 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1651 if (err < 0)
1652 return err;
1653 estat = err;
1654 }
1655
1656 bmcr = 0;
1657 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1658 if (err)
1659 return err;
1660
1661 if (lp->loopback_mode == LOOPBACK_MAC) {
1662 bmcr |= BMCR_LOOPBACK;
1663 if (lp->active_speed == SPEED_1000)
1664 bmcr |= BMCR_SPEED1000;
1665 if (lp->active_duplex == DUPLEX_FULL)
1666 bmcr |= BMCR_FULLDPLX;
1667 }
1668
1669 if (lp->loopback_mode == LOOPBACK_PHY) {
1670 u16 aux;
1671
1672 aux = (BCM5464R_AUX_CTL_EXT_LB |
1673 BCM5464R_AUX_CTL_WRITE_1);
1674 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1675 if (err)
1676 return err;
1677 }
1678
1679 /* XXX configurable XXX */
1680 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1681 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1682 if (bmsr & BMSR_10FULL)
1683 adv |= ADVERTISE_10FULL;
1684 if (bmsr & BMSR_100FULL)
1685 adv |= ADVERTISE_100FULL;
1686 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1687 if (err)
1688 return err;
1689
1690 if (bmsr & BMSR_ESTATEN) {
1691 u16 ctrl1000 = 0;
1692
1693 if (estat & ESTATUS_1000_TFULL)
1694 ctrl1000 |= ADVERTISE_1000FULL;
1695 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1696 if (err)
1697 return err;
1698 }
1699 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1700
1701 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1702 if (err)
1703 return err;
1704
1705 err = mii_read(np, np->phy_addr, MII_BMCR);
1706 if (err < 0)
1707 return err;
1708 err = mii_read(np, np->phy_addr, MII_BMSR);
1709 if (err < 0)
1710 return err;
1711#if 0
1712 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1713 np->port, bmcr, bmsr);
1714#endif
1715
1716 return 0;
1717}
1718
1719static int xcvr_init_1g(struct niu *np)
1720{
1721 u64 val;
1722
1723 /* XXX shared resource, lock parent XXX */
1724 val = nr64(MIF_CONFIG);
1725 val &= ~MIF_CONFIG_INDIRECT_MODE;
1726 nw64(MIF_CONFIG, val);
1727
1728 return mii_init_common(np);
1729}
1730
1731static int niu_xcvr_init(struct niu *np)
1732{
1733 const struct niu_phy_ops *ops = np->phy_ops;
1734 int err;
1735
1736 err = 0;
1737 if (ops->xcvr_init)
1738 err = ops->xcvr_init(np);
1739
1740 return err;
1741}
1742
1743static int niu_serdes_init(struct niu *np)
1744{
1745 const struct niu_phy_ops *ops = np->phy_ops;
1746 int err;
1747
1748 err = 0;
1749 if (ops->serdes_init)
1750 err = ops->serdes_init(np);
1751
1752 return err;
1753}
1754
1755static void niu_init_xif(struct niu *);
0c3b091b 1756static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1757
1758static int niu_link_status_common(struct niu *np, int link_up)
1759{
1760 struct niu_link_config *lp = &np->link_config;
1761 struct net_device *dev = np->dev;
1762 unsigned long flags;
1763
1764 if (!netif_carrier_ok(dev) && link_up) {
1765 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1766 dev->name,
1767 (lp->active_speed == SPEED_10000 ?
1768 "10Gb/sec" :
1769 (lp->active_speed == SPEED_1000 ?
1770 "1Gb/sec" :
1771 (lp->active_speed == SPEED_100 ?
1772 "100Mbit/sec" : "10Mbit/sec"))),
1773 (lp->active_duplex == DUPLEX_FULL ?
1774 "full" : "half"));
1775
1776 spin_lock_irqsave(&np->lock, flags);
1777 niu_init_xif(np);
0c3b091b 1778 niu_handle_led(np, 1);
a3138df9
DM		 1779 spin_unlock_irqrestore(&np->lock, flags);
1780
1781 netif_carrier_on(dev);
1782 } else if (netif_carrier_ok(dev) && !link_up) {
1783 niuwarn(LINK, "%s: Link is down\n", dev->name);
0c3b091b
ML		 1784 spin_lock_irqsave(&np->lock, flags);
1785 niu_handle_led(np, 0);
1786 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1787 netif_carrier_off(dev);
1788 }
1789
1790 return 0;
1791}
1792
b0de8e40 1793static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1794{
b0de8e40 1795 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1796
1797 link_up = 0;
1798
b0de8e40
ML		 1799 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1800 MRVL88X2011_10G_PMD_STATUS_2);
1801 if (err < 0)
1802 goto out;
a3138df9 1803
b0de8e40
ML		 1804 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1805 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1806 MRVL88X2011_PMA_PMD_STATUS_1);
1807 if (err < 0)
1808 goto out;
1809
1810 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1811
1812 /* Check PMC Register : 3.0001.2 == 1: read twice */
1813 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1814 MRVL88X2011_PMA_PMD_STATUS_1);
1815 if (err < 0)
1816 goto out;
1817
1818 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1819 MRVL88X2011_PMA_PMD_STATUS_1);
1820 if (err < 0)
1821 goto out;
1822
1823 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1824
1825 /* Check XGXS Register : 4.0018.[0-3,12] */
1826 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1827 MRVL88X2011_10G_XGXS_LANE_STAT);
1828 if (err < 0)
a3138df9
DM		 1829 goto out;
1830
b0de8e40
ML		 1831 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1832 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1833 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1834 0x800))
1835 link_up = (pma_status && pcs_status) ? 1 : 0;
1836
1837 np->link_config.active_speed = SPEED_10000;
1838 np->link_config.active_duplex = DUPLEX_FULL;
1839 err = 0;
1840out:
1841 mrvl88x2011_act_led(np, (link_up ?
1842 MRVL88X2011_LED_CTL_PCS_ACT :
1843 MRVL88X2011_LED_CTL_OFF));
1844
1845 *link_up_p = link_up;
1846 return err;
1847}
1848
a5d6ab56
MW		 1849static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
1850{
1851 int err, link_up;
1852 link_up = 0;
1853
1854 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1855 BCM8704_PMD_RCV_SIGDET);
1856 if (err < 0)
1857 goto out;
1858 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1859 err = 0;
1860 goto out;
1861 }
1862
1863 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1864 BCM8704_PCS_10G_R_STATUS);
1865 if (err < 0)
1866 goto out;
1867
1868 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1869 err = 0;
1870 goto out;
1871 }
1872
1873 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1874 BCM8704_PHYXS_XGXS_LANE_STAT);
1875 if (err < 0)
1876 goto out;
1877 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1878 PHYXS_XGXS_LANE_STAT_MAGIC |
1879 PHYXS_XGXS_LANE_STAT_PATTEST |
1880 PHYXS_XGXS_LANE_STAT_LANE3 |
1881 PHYXS_XGXS_LANE_STAT_LANE2 |
1882 PHYXS_XGXS_LANE_STAT_LANE1 |
1883 PHYXS_XGXS_LANE_STAT_LANE0)) {
1884 err = 0;
1885 np->link_config.active_speed = SPEED_INVALID;
1886 np->link_config.active_duplex = DUPLEX_INVALID;
1887 goto out;
1888 }
1889
1890 link_up = 1;
1891 np->link_config.active_speed = SPEED_10000;
1892 np->link_config.active_duplex = DUPLEX_FULL;
1893 err = 0;
1894
1895out:
1896 *link_up_p = link_up;
1897 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
1898 err = 0;
1899 return err;
1900}
1901
b0de8e40
ML		 1902static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1903{
1904 int err, link_up;
1905
1906 link_up = 0;
1907
a3138df9
DM		 1908 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1909 BCM8704_PMD_RCV_SIGDET);
1910 if (err < 0)
1911 goto out;
1912 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1913 err = 0;
1914 goto out;
1915 }
1916
1917 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1918 BCM8704_PCS_10G_R_STATUS);
1919 if (err < 0)
1920 goto out;
1921 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1922 err = 0;
1923 goto out;
1924 }
1925
1926 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1927 BCM8704_PHYXS_XGXS_LANE_STAT);
1928 if (err < 0)
1929 goto out;
1930
1931 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1932 PHYXS_XGXS_LANE_STAT_MAGIC |
1933 PHYXS_XGXS_LANE_STAT_LANE3 |
1934 PHYXS_XGXS_LANE_STAT_LANE2 |
1935 PHYXS_XGXS_LANE_STAT_LANE1 |
1936 PHYXS_XGXS_LANE_STAT_LANE0)) {
1937 err = 0;
1938 goto out;
1939 }
1940
1941 link_up = 1;
1942 np->link_config.active_speed = SPEED_10000;
1943 np->link_config.active_duplex = DUPLEX_FULL;
1944 err = 0;
1945
1946out:
b0de8e40
ML		 1947 *link_up_p = link_up;
1948 return err;
1949}
1950
1951static int link_status_10g(struct niu *np, int *link_up_p)
1952{
1953 unsigned long flags;
1954 int err = -EINVAL;
1955
1956 spin_lock_irqsave(&np->lock, flags);
1957
1958 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1959 int phy_id;
1960
1961 phy_id = phy_decode(np->parent->port_phy, np->port);
1962 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1963
1964 /* handle different phy types */
1965 switch (phy_id & NIU_PHY_ID_MASK) {
1966 case NIU_PHY_ID_MRVL88X2011:
1967 err = link_status_10g_mrvl(np, link_up_p);
1968 break;
1969
1970 default: /* bcom 8704 */
1971 err = link_status_10g_bcom(np, link_up_p);
1972 break;
1973 }
1974 }
1975
a3138df9
DM		 1976 spin_unlock_irqrestore(&np->lock, flags);
1977
a3138df9
DM		 1978 return err;
1979}
1980
a5d6ab56
MW		 1981static int niu_10g_phy_present(struct niu *np)
1982{
1983 u64 sig, mask, val;
1984
1985 sig = nr64(ESR_INT_SIGNALS);
1986 switch (np->port) {
1987 case 0:
1988 mask = ESR_INT_SIGNALS_P0_BITS;
1989 val = (ESR_INT_SRDY0_P0 |
1990 ESR_INT_DET0_P0 |
1991 ESR_INT_XSRDY_P0 |
1992 ESR_INT_XDP_P0_CH3 |
1993 ESR_INT_XDP_P0_CH2 |
1994 ESR_INT_XDP_P0_CH1 |
1995 ESR_INT_XDP_P0_CH0);
1996 break;
1997
1998 case 1:
1999 mask = ESR_INT_SIGNALS_P1_BITS;
2000 val = (ESR_INT_SRDY0_P1 |
2001 ESR_INT_DET0_P1 |
2002 ESR_INT_XSRDY_P1 |
2003 ESR_INT_XDP_P1_CH3 |
2004 ESR_INT_XDP_P1_CH2 |
2005 ESR_INT_XDP_P1_CH1 |
2006 ESR_INT_XDP_P1_CH0);
2007 break;
2008
2009 default:
2010 return 0;
2011 }
2012
2013 if ((sig & mask) != val)
2014 return 0;
2015 return 1;
2016}
2017
2018static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2019{
2020 unsigned long flags;
2021 int err = 0;
2022 int phy_present;
2023 int phy_present_prev;
2024
2025 spin_lock_irqsave(&np->lock, flags);
2026
2027 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2028 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2029 1 : 0;
2030 phy_present = niu_10g_phy_present(np);
2031 if (phy_present != phy_present_prev) {
2032 /* state change */
2033 if (phy_present) {
2034 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2035 if (np->phy_ops->xcvr_init)
2036 err = np->phy_ops->xcvr_init(np);
2037 if (err) {
2038 /* debounce */
2039 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2040 }
2041 } else {
2042 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2043 *link_up_p = 0;
2044 niuwarn(LINK, "%s: Hotplug PHY Removed\n",
2045 np->dev->name);
2046 }
2047 }
2048 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT)
2049 err = link_status_10g_bcm8706(np, link_up_p);
2050 }
2051
2052 spin_unlock_irqrestore(&np->lock, flags);
2053
2054 return err;
2055}
2056
a3138df9
DM		 2057static int link_status_1g(struct niu *np, int *link_up_p)
2058{
e415e6ea 2059 struct niu_link_config *lp = &np->link_config;
a3138df9
DM		 2060 u16 current_speed, bmsr;
2061 unsigned long flags;
2062 u8 current_duplex;
2063 int err, link_up;
2064
2065 link_up = 0;
2066 current_speed = SPEED_INVALID;
2067 current_duplex = DUPLEX_INVALID;
2068
2069 spin_lock_irqsave(&np->lock, flags);
2070
2071 err = -EINVAL;
2072 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
2073 goto out;
2074
2075 err = mii_read(np, np->phy_addr, MII_BMSR);
2076 if (err < 0)
2077 goto out;
2078
2079 bmsr = err;
2080 if (bmsr & BMSR_LSTATUS) {
2081 u16 adv, lpa, common, estat;
2082
2083 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
2084 if (err < 0)
2085 goto out;
2086 adv = err;
2087
2088 err = mii_read(np, np->phy_addr, MII_LPA);
2089 if (err < 0)
2090 goto out;
2091 lpa = err;
2092
2093 common = adv & lpa;
2094
2095 err = mii_read(np, np->phy_addr, MII_ESTATUS);
2096 if (err < 0)
2097 goto out;
2098 estat = err;
2099
2100 link_up = 1;
2101 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
2102 current_speed = SPEED_1000;
2103 if (estat & ESTATUS_1000_TFULL)
2104 current_duplex = DUPLEX_FULL;
2105 else
2106 current_duplex = DUPLEX_HALF;
2107 } else {
2108 if (common & ADVERTISE_100BASE4) {
2109 current_speed = SPEED_100;
2110 current_duplex = DUPLEX_HALF;
2111 } else if (common & ADVERTISE_100FULL) {
2112 current_speed = SPEED_100;
2113 current_duplex = DUPLEX_FULL;
2114 } else if (common & ADVERTISE_100HALF) {
2115 current_speed = SPEED_100;
2116 current_duplex = DUPLEX_HALF;
2117 } else if (common & ADVERTISE_10FULL) {
2118 current_speed = SPEED_10;
2119 current_duplex = DUPLEX_FULL;
2120 } else if (common & ADVERTISE_10HALF) {
2121 current_speed = SPEED_10;
2122 current_duplex = DUPLEX_HALF;
2123 } else
2124 link_up = 0;
2125 }
2126 }
e415e6ea
DM		 2127 lp->active_speed = current_speed;
2128 lp->active_duplex = current_duplex;
a3138df9
DM		 2129 err = 0;
2130
2131out:
2132 spin_unlock_irqrestore(&np->lock, flags);
2133
2134 *link_up_p = link_up;
2135 return err;
2136}
2137
2138static int niu_link_status(struct niu *np, int *link_up_p)
2139{
2140 const struct niu_phy_ops *ops = np->phy_ops;
2141 int err;
2142
2143 err = 0;
2144 if (ops->link_status)
2145 err = ops->link_status(np, link_up_p);
2146
2147 return err;
2148}
2149
2150static void niu_timer(unsigned long __opaque)
2151{
2152 struct niu *np = (struct niu *) __opaque;
2153 unsigned long off;
2154 int err, link_up;
2155
2156 err = niu_link_status(np, &link_up);
2157 if (!err)
2158 niu_link_status_common(np, link_up);
2159
2160 if (netif_carrier_ok(np->dev))
2161 off = 5 * HZ;
2162 else
2163 off = 1 * HZ;
2164 np->timer.expires = jiffies + off;
2165
2166 add_timer(&np->timer);
2167}
2168
5fbd7e24
MW		 2169static const struct niu_phy_ops phy_ops_10g_serdes = {
2170 .serdes_init = serdes_init_10g_serdes,
2171 .link_status = link_status_10g_serdes,
2172};
2173
e3e081e1
SB		 2174static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2175 .serdes_init = serdes_init_niu_10g_serdes,
2176 .link_status = link_status_10g_serdes,
2177};
2178
2179static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2180 .serdes_init = serdes_init_niu_1g_serdes,
2181 .link_status = link_status_1g_serdes,
2182};
2183
5fbd7e24
MW		 2184static const struct niu_phy_ops phy_ops_1g_rgmii = {
2185 .xcvr_init = xcvr_init_1g_rgmii,
2186 .link_status = link_status_1g_rgmii,
2187};
2188
a3138df9 2189static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2190 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2191 .xcvr_init = xcvr_init_10g,
2192 .link_status = link_status_10g,
2193};
2194
2195static const struct niu_phy_ops phy_ops_10g_fiber = {
2196 .serdes_init = serdes_init_10g,
2197 .xcvr_init = xcvr_init_10g,
2198 .link_status = link_status_10g,
2199};
2200
a5d6ab56
MW		 2201static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2202 .serdes_init = serdes_init_10g,
2203 .xcvr_init = xcvr_init_10g_bcm8706,
2204 .link_status = link_status_10g_hotplug,
2205};
2206
a3138df9
DM		 2207static const struct niu_phy_ops phy_ops_10g_copper = {
2208 .serdes_init = serdes_init_10g,
2209 .link_status = link_status_10g, /* XXX */
2210};
2211
2212static const struct niu_phy_ops phy_ops_1g_fiber = {
2213 .serdes_init = serdes_init_1g,
2214 .xcvr_init = xcvr_init_1g,
2215 .link_status = link_status_1g,
2216};
2217
2218static const struct niu_phy_ops phy_ops_1g_copper = {
2219 .xcvr_init = xcvr_init_1g,
2220 .link_status = link_status_1g,
2221};
2222
2223struct niu_phy_template {
2224 const struct niu_phy_ops *ops;
2225 u32 phy_addr_base;
2226};
2227
e3e081e1 2228static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2229 .ops = &phy_ops_10g_fiber_niu,
2230 .phy_addr_base = 16,
2231};
2232
e3e081e1
SB		 2233static const struct niu_phy_template phy_template_niu_10g_serdes = {
2234 .ops = &phy_ops_10g_serdes_niu,
2235 .phy_addr_base = 0,
2236};
2237
2238static const struct niu_phy_template phy_template_niu_1g_serdes = {
2239 .ops = &phy_ops_1g_serdes_niu,
2240 .phy_addr_base = 0,
2241};
2242
a3138df9
DM		 2243static const struct niu_phy_template phy_template_10g_fiber = {
2244 .ops = &phy_ops_10g_fiber,
2245 .phy_addr_base = 8,
2246};
2247
a5d6ab56
MW		 2248static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2249 .ops = &phy_ops_10g_fiber_hotplug,
2250 .phy_addr_base = 8,
2251};
2252
a3138df9
DM		 2253static const struct niu_phy_template phy_template_10g_copper = {
2254 .ops = &phy_ops_10g_copper,
2255 .phy_addr_base = 10,
2256};
2257
2258static const struct niu_phy_template phy_template_1g_fiber = {
2259 .ops = &phy_ops_1g_fiber,
2260 .phy_addr_base = 0,
2261};
2262
2263static const struct niu_phy_template phy_template_1g_copper = {
2264 .ops = &phy_ops_1g_copper,
2265 .phy_addr_base = 0,
2266};
2267
5fbd7e24
MW		 2268static const struct niu_phy_template phy_template_1g_rgmii = {
2269 .ops = &phy_ops_1g_rgmii,
2270 .phy_addr_base = 0,
2271};
2272
2273static const struct niu_phy_template phy_template_10g_serdes = {
2274 .ops = &phy_ops_10g_serdes,
2275 .phy_addr_base = 0,
2276};
2277
2278static int niu_atca_port_num[4] = {
2279 0, 0, 11, 10
2280};
2281
2282static int serdes_init_10g_serdes(struct niu *np)
2283{
2284 struct niu_link_config *lp = &np->link_config;
2285 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2286 u64 ctrl_val, test_cfg_val, sig, mask, val;
2287 int err;
2288 u64 reset_val;
2289
2290 switch (np->port) {
2291 case 0:
2292 reset_val = ENET_SERDES_RESET_0;
2293 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2294 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2295 pll_cfg = ENET_SERDES_0_PLL_CFG;
2296 break;
2297 case 1:
2298 reset_val = ENET_SERDES_RESET_1;
2299 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2300 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2301 pll_cfg = ENET_SERDES_1_PLL_CFG;
2302 break;
2303
2304 default:
2305 return -EINVAL;
2306 }
2307 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2308 ENET_SERDES_CTRL_SDET_1 |
2309 ENET_SERDES_CTRL_SDET_2 |
2310 ENET_SERDES_CTRL_SDET_3 |
2311 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2312 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2313 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2314 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2315 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2316 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2317 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2318 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2319 test_cfg_val = 0;
2320
2321 if (lp->loopback_mode == LOOPBACK_PHY) {
2322 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2323 ENET_SERDES_TEST_MD_0_SHIFT) |
2324 (ENET_TEST_MD_PAD_LOOPBACK <<
2325 ENET_SERDES_TEST_MD_1_SHIFT) |
2326 (ENET_TEST_MD_PAD_LOOPBACK <<
2327 ENET_SERDES_TEST_MD_2_SHIFT) |
2328 (ENET_TEST_MD_PAD_LOOPBACK <<
2329 ENET_SERDES_TEST_MD_3_SHIFT));
2330 }
2331
2332 esr_reset(np);
2333 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2334 nw64(ctrl_reg, ctrl_val);
2335 nw64(test_cfg_reg, test_cfg_val);
2336
2337 /* Initialize all 4 lanes of the SERDES. */
2338 for (i = 0; i < 4; i++) {
2339 u32 rxtx_ctrl, glue0;
2340
2341 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2342 if (err)
2343 return err;
2344 err = esr_read_glue0(np, i, &glue0);
2345 if (err)
2346 return err;
2347
2348 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2349 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2350 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2351
2352 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2353 ESR_GLUE_CTRL0_THCNT |
2354 ESR_GLUE_CTRL0_BLTIME);
2355 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2356 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2357 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2358 (BLTIME_300_CYCLES <<
2359 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2360
2361 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2362 if (err)
2363 return err;
2364 err = esr_write_glue0(np, i, glue0);
2365 if (err)
2366 return err;
2367 }
2368
2369
2370 sig = nr64(ESR_INT_SIGNALS);
2371 switch (np->port) {
2372 case 0:
2373 mask = ESR_INT_SIGNALS_P0_BITS;
2374 val = (ESR_INT_SRDY0_P0 |
2375 ESR_INT_DET0_P0 |
2376 ESR_INT_XSRDY_P0 |
2377 ESR_INT_XDP_P0_CH3 |
2378 ESR_INT_XDP_P0_CH2 |
2379 ESR_INT_XDP_P0_CH1 |
2380 ESR_INT_XDP_P0_CH0);
2381 break;
2382
2383 case 1:
2384 mask = ESR_INT_SIGNALS_P1_BITS;
2385 val = (ESR_INT_SRDY0_P1 |
2386 ESR_INT_DET0_P1 |
2387 ESR_INT_XSRDY_P1 |
2388 ESR_INT_XDP_P1_CH3 |
2389 ESR_INT_XDP_P1_CH2 |
2390 ESR_INT_XDP_P1_CH1 |
2391 ESR_INT_XDP_P1_CH0);
2392 break;
2393
2394 default:
2395 return -EINVAL;
2396 }
2397
2398 if ((sig & mask) != val) {
2399 int err;
2400 err = serdes_init_1g_serdes(np);
2401 if (!err) {
2402 np->flags &= ~NIU_FLAGS_10G;
2403 np->mac_xcvr = MAC_XCVR_PCS;
2404 } else {
2405 dev_err(np->device, PFX "Port %u 10G/1G SERDES Link Failed \n",
2406 np->port);
2407 return -ENODEV;
2408 }
2409 }
2410
2411 return 0;
2412}
2413
a3138df9
DM		 2414static int niu_determine_phy_disposition(struct niu *np)
2415{
2416 struct niu_parent *parent = np->parent;
2417 u8 plat_type = parent->plat_type;
2418 const struct niu_phy_template *tp;
2419 u32 phy_addr_off = 0;
2420
2421 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2422 switch (np->flags &
2423 (NIU_FLAGS_10G |
2424 NIU_FLAGS_FIBER |
2425 NIU_FLAGS_XCVR_SERDES)) {
2426 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2427 /* 10G Serdes */
2428 tp = &phy_template_niu_10g_serdes;
2429 break;
2430 case NIU_FLAGS_XCVR_SERDES:
2431 /* 1G Serdes */
2432 tp = &phy_template_niu_1g_serdes;
2433 break;
2434 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2435 /* 10G Fiber */
2436 default:
2437 tp = &phy_template_niu_10g_fiber;
2438 phy_addr_off += np->port;
2439 break;
2440 }
a3138df9 2441 } else {
5fbd7e24
MW		 2442 switch (np->flags &
2443 (NIU_FLAGS_10G |
2444 NIU_FLAGS_FIBER |
2445 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2446 case 0:
2447 /* 1G copper */
2448 tp = &phy_template_1g_copper;
2449 if (plat_type == PLAT_TYPE_VF_P0)
2450 phy_addr_off = 10;
2451 else if (plat_type == PLAT_TYPE_VF_P1)
2452 phy_addr_off = 26;
2453
2454 phy_addr_off += (np->port ^ 0x3);
2455 break;
2456
2457 case NIU_FLAGS_10G:
2458 /* 10G copper */
2459 tp = &phy_template_1g_copper;
2460 break;
2461
2462 case NIU_FLAGS_FIBER:
2463 /* 1G fiber */
2464 tp = &phy_template_1g_fiber;
2465 break;
2466
2467 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2468 /* 10G fiber */
2469 tp = &phy_template_10g_fiber;
2470 if (plat_type == PLAT_TYPE_VF_P0 ||
2471 plat_type == PLAT_TYPE_VF_P1)
2472 phy_addr_off = 8;
2473 phy_addr_off += np->port;
a5d6ab56
MW		 2474 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2475 tp = &phy_template_10g_fiber_hotplug;
2476 if (np->port == 0)
2477 phy_addr_off = 8;
2478 if (np->port == 1)
2479 phy_addr_off = 12;
2480 }
a3138df9
DM		 2481 break;
2482
5fbd7e24
MW		 2483 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2484 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2485 case NIU_FLAGS_XCVR_SERDES:
2486 switch(np->port) {
2487 case 0:
2488 case 1:
2489 tp = &phy_template_10g_serdes;
2490 break;
2491 case 2:
2492 case 3:
2493 tp = &phy_template_1g_rgmii;
2494 break;
2495 default:
2496 return -EINVAL;
2497 break;
2498 }
2499 phy_addr_off = niu_atca_port_num[np->port];
2500 break;
2501
a3138df9
DM		 2502 default:
2503 return -EINVAL;
2504 }
2505 }
2506
2507 np->phy_ops = tp->ops;
2508 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2509
2510 return 0;
2511}
2512
2513static int niu_init_link(struct niu *np)
2514{
2515 struct niu_parent *parent = np->parent;
2516 int err, ignore;
2517
2518 if (parent->plat_type == PLAT_TYPE_NIU) {
2519 err = niu_xcvr_init(np);
2520 if (err)
2521 return err;
2522 msleep(200);
2523 }
2524 err = niu_serdes_init(np);
2525 if (err)
2526 return err;
2527 msleep(200);
2528 err = niu_xcvr_init(np);
2529 if (!err)
2530 niu_link_status(np, &ignore);
2531 return 0;
2532}
2533
2534static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2535{
2536 u16 reg0 = addr[4] << 8 | addr[5];
2537 u16 reg1 = addr[2] << 8 | addr[3];
2538 u16 reg2 = addr[0] << 8 | addr[1];
2539
2540 if (np->flags & NIU_FLAGS_XMAC) {
2541 nw64_mac(XMAC_ADDR0, reg0);
2542 nw64_mac(XMAC_ADDR1, reg1);
2543 nw64_mac(XMAC_ADDR2, reg2);
2544 } else {
2545 nw64_mac(BMAC_ADDR0, reg0);
2546 nw64_mac(BMAC_ADDR1, reg1);
2547 nw64_mac(BMAC_ADDR2, reg2);
2548 }
2549}
2550
2551static int niu_num_alt_addr(struct niu *np)
2552{
2553 if (np->flags & NIU_FLAGS_XMAC)
2554 return XMAC_NUM_ALT_ADDR;
2555 else
2556 return BMAC_NUM_ALT_ADDR;
2557}
2558
2559static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2560{
2561 u16 reg0 = addr[4] << 8 | addr[5];
2562 u16 reg1 = addr[2] << 8 | addr[3];
2563 u16 reg2 = addr[0] << 8 | addr[1];
2564
2565 if (index >= niu_num_alt_addr(np))
2566 return -EINVAL;
2567
2568 if (np->flags & NIU_FLAGS_XMAC) {
2569 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2570 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2571 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2572 } else {
2573 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2574 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2575 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2576 }
2577
2578 return 0;
2579}
2580
2581static int niu_enable_alt_mac(struct niu *np, int index, int on)
2582{
2583 unsigned long reg;
2584 u64 val, mask;
2585
2586 if (index >= niu_num_alt_addr(np))
2587 return -EINVAL;
2588
fa907895 2589 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2590 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2591 mask = 1 << index;
2592 } else {
a3138df9 2593 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2594 mask = 1 << (index + 1);
2595 }
a3138df9
DM		 2596
2597 val = nr64_mac(reg);
2598 if (on)
2599 val |= mask;
2600 else
2601 val &= ~mask;
2602 nw64_mac(reg, val);
2603
2604 return 0;
2605}
2606
2607static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2608 int num, int mac_pref)
2609{
2610 u64 val = nr64_mac(reg);
2611 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2612 val |= num;
2613 if (mac_pref)
2614 val |= HOST_INFO_MPR;
2615 nw64_mac(reg, val);
2616}
2617
2618static int __set_rdc_table_num(struct niu *np,
2619 int xmac_index, int bmac_index,
2620 int rdc_table_num, int mac_pref)
2621{
2622 unsigned long reg;
2623
2624 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2625 return -EINVAL;
2626 if (np->flags & NIU_FLAGS_XMAC)
2627 reg = XMAC_HOST_INFO(xmac_index);
2628 else
2629 reg = BMAC_HOST_INFO(bmac_index);
2630 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2631 return 0;
2632}
2633
2634static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2635 int mac_pref)
2636{
2637 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2638}
2639
2640static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2641 int mac_pref)
2642{
2643 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2644}
2645
2646static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2647 int table_num, int mac_pref)
2648{
2649 if (idx >= niu_num_alt_addr(np))
2650 return -EINVAL;
2651 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2652}
2653
2654static u64 vlan_entry_set_parity(u64 reg_val)
2655{
2656 u64 port01_mask;
2657 u64 port23_mask;
2658
2659 port01_mask = 0x00ff;
2660 port23_mask = 0xff00;
2661
2662 if (hweight64(reg_val & port01_mask) & 1)
2663 reg_val |= ENET_VLAN_TBL_PARITY0;
2664 else
2665 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2666
2667 if (hweight64(reg_val & port23_mask) & 1)
2668 reg_val |= ENET_VLAN_TBL_PARITY1;
2669 else
2670 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2671
2672 return reg_val;
2673}
2674
2675static void vlan_tbl_write(struct niu *np, unsigned long index,
2676 int port, int vpr, int rdc_table)
2677{
2678 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2679
2680 reg_val &= ~((ENET_VLAN_TBL_VPR |
2681 ENET_VLAN_TBL_VLANRDCTBLN) <<
2682 ENET_VLAN_TBL_SHIFT(port));
2683 if (vpr)
2684 reg_val |= (ENET_VLAN_TBL_VPR <<
2685 ENET_VLAN_TBL_SHIFT(port));
2686 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2687
2688 reg_val = vlan_entry_set_parity(reg_val);
2689
2690 nw64(ENET_VLAN_TBL(index), reg_val);
2691}
2692
2693static void vlan_tbl_clear(struct niu *np)
2694{
2695 int i;
2696
2697 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2698 nw64(ENET_VLAN_TBL(i), 0);
2699}
2700
2701static int tcam_wait_bit(struct niu *np, u64 bit)
2702{
2703 int limit = 1000;
2704
2705 while (--limit > 0) {
2706 if (nr64(TCAM_CTL) & bit)
2707 break;
2708 udelay(1);
2709 }
2710 if (limit < 0)
2711 return -ENODEV;
2712
2713 return 0;
2714}
2715
2716static int tcam_flush(struct niu *np, int index)
2717{
2718 nw64(TCAM_KEY_0, 0x00);
2719 nw64(TCAM_KEY_MASK_0, 0xff);
2720 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2721
2722 return tcam_wait_bit(np, TCAM_CTL_STAT);
2723}
2724
2725#if 0
2726static int tcam_read(struct niu *np, int index,
2727 u64 *key, u64 *mask)
2728{
2729 int err;
2730
2731 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2732 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2733 if (!err) {
2734 key[0] = nr64(TCAM_KEY_0);
2735 key[1] = nr64(TCAM_KEY_1);
2736 key[2] = nr64(TCAM_KEY_2);
2737 key[3] = nr64(TCAM_KEY_3);
2738 mask[0] = nr64(TCAM_KEY_MASK_0);
2739 mask[1] = nr64(TCAM_KEY_MASK_1);
2740 mask[2] = nr64(TCAM_KEY_MASK_2);
2741 mask[3] = nr64(TCAM_KEY_MASK_3);
2742 }
2743 return err;
2744}
2745#endif
2746
2747static int tcam_write(struct niu *np, int index,
2748 u64 *key, u64 *mask)
2749{
2750 nw64(TCAM_KEY_0, key[0]);
2751 nw64(TCAM_KEY_1, key[1]);
2752 nw64(TCAM_KEY_2, key[2]);
2753 nw64(TCAM_KEY_3, key[3]);
2754 nw64(TCAM_KEY_MASK_0, mask[0]);
2755 nw64(TCAM_KEY_MASK_1, mask[1]);
2756 nw64(TCAM_KEY_MASK_2, mask[2]);
2757 nw64(TCAM_KEY_MASK_3, mask[3]);
2758 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2759
2760 return tcam_wait_bit(np, TCAM_CTL_STAT);
2761}
2762
2763#if 0
2764static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2765{
2766 int err;
2767
2768 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2769 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2770 if (!err)
2771 *data = nr64(TCAM_KEY_1);
2772
2773 return err;
2774}
2775#endif
2776
2777static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2778{
2779 nw64(TCAM_KEY_1, assoc_data);
2780 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2781
2782 return tcam_wait_bit(np, TCAM_CTL_STAT);
2783}
2784
2785static void tcam_enable(struct niu *np, int on)
2786{
2787 u64 val = nr64(FFLP_CFG_1);
2788
2789 if (on)
2790 val &= ~FFLP_CFG_1_TCAM_DIS;
2791 else
2792 val |= FFLP_CFG_1_TCAM_DIS;
2793 nw64(FFLP_CFG_1, val);
2794}
2795
2796static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2797{
2798 u64 val = nr64(FFLP_CFG_1);
2799
2800 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2801 FFLP_CFG_1_CAMLAT |
2802 FFLP_CFG_1_CAMRATIO);
2803 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2804 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2805 nw64(FFLP_CFG_1, val);
2806
2807 val = nr64(FFLP_CFG_1);
2808 val |= FFLP_CFG_1_FFLPINITDONE;
2809 nw64(FFLP_CFG_1, val);
2810}
2811
2812static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2813 int on)
2814{
2815 unsigned long reg;
2816 u64 val;
2817
2818 if (class < CLASS_CODE_ETHERTYPE1 ||
2819 class > CLASS_CODE_ETHERTYPE2)
2820 return -EINVAL;
2821
2822 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2823 val = nr64(reg);
2824 if (on)
2825 val |= L2_CLS_VLD;
2826 else
2827 val &= ~L2_CLS_VLD;
2828 nw64(reg, val);
2829
2830 return 0;
2831}
2832
2833#if 0
2834static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2835 u64 ether_type)
2836{
2837 unsigned long reg;
2838 u64 val;
2839
2840 if (class < CLASS_CODE_ETHERTYPE1 ||
2841 class > CLASS_CODE_ETHERTYPE2 ||
2842 (ether_type & ~(u64)0xffff) != 0)
2843 return -EINVAL;
2844
2845 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2846 val = nr64(reg);
2847 val &= ~L2_CLS_ETYPE;
2848 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2849 nw64(reg, val);
2850
2851 return 0;
2852}
2853#endif
2854
2855static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2856 int on)
2857{
2858 unsigned long reg;
2859 u64 val;
2860
2861 if (class < CLASS_CODE_USER_PROG1 ||
2862 class > CLASS_CODE_USER_PROG4)
2863 return -EINVAL;
2864
2865 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2866 val = nr64(reg);
2867 if (on)
2868 val |= L3_CLS_VALID;
2869 else
2870 val &= ~L3_CLS_VALID;
2871 nw64(reg, val);
2872
2873 return 0;
2874}
2875
2876#if 0
2877static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2878 int ipv6, u64 protocol_id,
2879 u64 tos_mask, u64 tos_val)
2880{
2881 unsigned long reg;
2882 u64 val;
2883
2884 if (class < CLASS_CODE_USER_PROG1 ||
2885 class > CLASS_CODE_USER_PROG4 ||
2886 (protocol_id & ~(u64)0xff) != 0 ||
2887 (tos_mask & ~(u64)0xff) != 0 ||
2888 (tos_val & ~(u64)0xff) != 0)
2889 return -EINVAL;
2890
2891 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2892 val = nr64(reg);
2893 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2894 L3_CLS_TOSMASK | L3_CLS_TOS);
2895 if (ipv6)
2896 val |= L3_CLS_IPVER;
2897 val |= (protocol_id << L3_CLS_PID_SHIFT);
2898 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2899 val |= (tos_val << L3_CLS_TOS_SHIFT);
2900 nw64(reg, val);
2901
2902 return 0;
2903}
2904#endif
2905
2906static int tcam_early_init(struct niu *np)
2907{
2908 unsigned long i;
2909 int err;
2910
2911 tcam_enable(np, 0);
2912 tcam_set_lat_and_ratio(np,
2913 DEFAULT_TCAM_LATENCY,
2914 DEFAULT_TCAM_ACCESS_RATIO);
2915 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
2916 err = tcam_user_eth_class_enable(np, i, 0);
2917 if (err)
2918 return err;
2919 }
2920 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
2921 err = tcam_user_ip_class_enable(np, i, 0);
2922 if (err)
2923 return err;
2924 }
2925
2926 return 0;
2927}
2928
2929static int tcam_flush_all(struct niu *np)
2930{
2931 unsigned long i;
2932
2933 for (i = 0; i < np->parent->tcam_num_entries; i++) {
2934 int err = tcam_flush(np, i);
2935 if (err)
2936 return err;
2937 }
2938 return 0;
2939}
2940
2941static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
2942{
2943 return ((u64)index | (num_entries == 1 ?
2944 HASH_TBL_ADDR_AUTOINC : 0));
2945}
2946
2947#if 0
2948static int hash_read(struct niu *np, unsigned long partition,
2949 unsigned long index, unsigned long num_entries,
2950 u64 *data)
2951{
2952 u64 val = hash_addr_regval(index, num_entries);
2953 unsigned long i;
2954
2955 if (partition >= FCRAM_NUM_PARTITIONS ||
2956 index + num_entries > FCRAM_SIZE)
2957 return -EINVAL;
2958
2959 nw64(HASH_TBL_ADDR(partition), val);
2960 for (i = 0; i < num_entries; i++)
2961 data[i] = nr64(HASH_TBL_DATA(partition));
2962
2963 return 0;
2964}
2965#endif
2966
2967static int hash_write(struct niu *np, unsigned long partition,
2968 unsigned long index, unsigned long num_entries,
2969 u64 *data)
2970{
2971 u64 val = hash_addr_regval(index, num_entries);
2972 unsigned long i;
2973
2974 if (partition >= FCRAM_NUM_PARTITIONS ||
2975 index + (num_entries * 8) > FCRAM_SIZE)
2976 return -EINVAL;
2977
2978 nw64(HASH_TBL_ADDR(partition), val);
2979 for (i = 0; i < num_entries; i++)
2980 nw64(HASH_TBL_DATA(partition), data[i]);
2981
2982 return 0;
2983}
2984
2985static void fflp_reset(struct niu *np)
2986{
2987 u64 val;
2988
2989 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2990 udelay(10);
2991 nw64(FFLP_CFG_1, 0);
2992
2993 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2994 nw64(FFLP_CFG_1, val);
2995}
2996
2997static void fflp_set_timings(struct niu *np)
2998{
2999 u64 val = nr64(FFLP_CFG_1);
3000
3001 val &= ~FFLP_CFG_1_FFLPINITDONE;
3002 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3003 nw64(FFLP_CFG_1, val);
3004
3005 val = nr64(FFLP_CFG_1);
3006 val |= FFLP_CFG_1_FFLPINITDONE;
3007 nw64(FFLP_CFG_1, val);
3008
3009 val = nr64(FCRAM_REF_TMR);
3010 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3011 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3012 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3013 nw64(FCRAM_REF_TMR, val);
3014}
3015
3016static int fflp_set_partition(struct niu *np, u64 partition,
3017 u64 mask, u64 base, int enable)
3018{
3019 unsigned long reg;
3020 u64 val;
3021
3022 if (partition >= FCRAM_NUM_PARTITIONS ||
3023 (mask & ~(u64)0x1f) != 0 ||
3024 (base & ~(u64)0x1f) != 0)
3025 return -EINVAL;
3026
3027 reg = FLW_PRT_SEL(partition);
3028
3029 val = nr64(reg);
3030 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3031 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3032 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3033 if (enable)
3034 val |= FLW_PRT_SEL_EXT;
3035 nw64(reg, val);
3036
3037 return 0;
3038}
3039
3040static int fflp_disable_all_partitions(struct niu *np)
3041{
3042 unsigned long i;
3043
3044 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3045 int err = fflp_set_partition(np, 0, 0, 0, 0);
3046 if (err)
3047 return err;
3048 }
3049 return 0;
3050}
3051
3052static void fflp_llcsnap_enable(struct niu *np, int on)
3053{
3054 u64 val = nr64(FFLP_CFG_1);
3055
3056 if (on)
3057 val |= FFLP_CFG_1_LLCSNAP;
3058 else
3059 val &= ~FFLP_CFG_1_LLCSNAP;
3060 nw64(FFLP_CFG_1, val);
3061}
3062
3063static void fflp_errors_enable(struct niu *np, int on)
3064{
3065 u64 val = nr64(FFLP_CFG_1);
3066
3067 if (on)
3068 val &= ~FFLP_CFG_1_ERRORDIS;
3069 else
3070 val |= FFLP_CFG_1_ERRORDIS;
3071 nw64(FFLP_CFG_1, val);
3072}
3073
3074static int fflp_hash_clear(struct niu *np)
3075{
3076 struct fcram_hash_ipv4 ent;
3077 unsigned long i;
3078
3079 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3080 memset(&ent, 0, sizeof(ent));
3081 ent.header = HASH_HEADER_EXT;
3082
3083 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3084 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3085 if (err)
3086 return err;
3087 }
3088 return 0;
3089}
3090
3091static int fflp_early_init(struct niu *np)
3092{
3093 struct niu_parent *parent;
3094 unsigned long flags;
3095 int err;
3096
3097 niu_lock_parent(np, flags);
3098
3099 parent = np->parent;
3100 err = 0;
3101 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
3102 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
3103 np->port);
3104 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3105 fflp_reset(np);
3106 fflp_set_timings(np);
3107 err = fflp_disable_all_partitions(np);
3108 if (err) {
3109 niudbg(PROBE, "fflp_disable_all_partitions "
3110 "failed, err=%d\n", err);
3111 goto out;
3112 }
3113 }
3114
3115 err = tcam_early_init(np);
3116 if (err) {
3117 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
3118 err);
3119 goto out;
3120 }
3121 fflp_llcsnap_enable(np, 1);
3122 fflp_errors_enable(np, 0);
3123 nw64(H1POLY, 0);
3124 nw64(H2POLY, 0);
3125
3126 err = tcam_flush_all(np);
3127 if (err) {
3128 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
3129 err);
3130 goto out;
3131 }
3132 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3133 err = fflp_hash_clear(np);
3134 if (err) {
3135 niudbg(PROBE, "fflp_hash_clear failed, "
3136 "err=%d\n", err);
3137 goto out;
3138 }
3139 }
3140
3141 vlan_tbl_clear(np);
3142
3143 niudbg(PROBE, "fflp_early_init: Success\n");
3144 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3145 }
3146out:
3147 niu_unlock_parent(np, flags);
3148 return err;
3149}
3150
3151static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3152{
3153 if (class_code < CLASS_CODE_USER_PROG1 ||
3154 class_code > CLASS_CODE_SCTP_IPV6)
3155 return -EINVAL;
3156
3157 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3158 return 0;
3159}
3160
3161static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3162{
3163 if (class_code < CLASS_CODE_USER_PROG1 ||
3164 class_code > CLASS_CODE_SCTP_IPV6)
3165 return -EINVAL;
3166
3167 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3168 return 0;
3169}
3170
3171static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3172 u32 offset, u32 size)
3173{
3174 int i = skb_shinfo(skb)->nr_frags;
3175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3176
3177 frag->page = page;
3178 frag->page_offset = offset;
3179 frag->size = size;
3180
3181 skb->len += size;
3182 skb->data_len += size;
3183 skb->truesize += size;
3184
3185 skb_shinfo(skb)->nr_frags = i + 1;
3186}
3187
3188static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3189{
3190 a >>= PAGE_SHIFT;
3191 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3192
3193 return (a & (MAX_RBR_RING_SIZE - 1));
3194}
3195
3196static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3197 struct page ***link)
3198{
3199 unsigned int h = niu_hash_rxaddr(rp, addr);
3200 struct page *p, **pp;
3201
3202 addr &= PAGE_MASK;
3203 pp = &rp->rxhash[h];
3204 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3205 if (p->index == addr) {
3206 *link = pp;
3207 break;
3208 }
3209 }
3210
3211 return p;
3212}
3213
3214static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3215{
3216 unsigned int h = niu_hash_rxaddr(rp, base);
3217
3218 page->index = base;
3219 page->mapping = (struct address_space *) rp->rxhash[h];
3220 rp->rxhash[h] = page;
3221}
3222
3223static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3224 gfp_t mask, int start_index)
3225{
3226 struct page *page;
3227 u64 addr;
3228 int i;
3229
3230 page = alloc_page(mask);
3231 if (!page)
3232 return -ENOMEM;
3233
3234 addr = np->ops->map_page(np->device, page, 0,
3235 PAGE_SIZE, DMA_FROM_DEVICE);
3236
3237 niu_hash_page(rp, page, addr);
3238 if (rp->rbr_blocks_per_page > 1)
3239 atomic_add(rp->rbr_blocks_per_page - 1,
3240 &compound_head(page)->_count);
3241
3242 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3243 __le32 *rbr = &rp->rbr[start_index + i];
3244
3245 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3246 addr += rp->rbr_block_size;
3247 }
3248
3249 return 0;
3250}
3251
3252static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3253{
3254 int index = rp->rbr_index;
3255
3256 rp->rbr_pending++;
3257 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3258 int err = niu_rbr_add_page(np, rp, mask, index);
3259
3260 if (unlikely(err)) {
3261 rp->rbr_pending--;
3262 return;
3263 }
3264
3265 rp->rbr_index += rp->rbr_blocks_per_page;
3266 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3267 if (rp->rbr_index == rp->rbr_table_size)
3268 rp->rbr_index = 0;
3269
3270 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3271 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3272 rp->rbr_pending = 0;
3273 }
3274 }
3275}
3276
3277static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3278{
3279 unsigned int index = rp->rcr_index;
3280 int num_rcr = 0;
3281
3282 rp->rx_dropped++;
3283 while (1) {
3284 struct page *page, **link;
3285 u64 addr, val;
3286 u32 rcr_size;
3287
3288 num_rcr++;
3289
3290 val = le64_to_cpup(&rp->rcr[index]);
3291 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3292 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3293 page = niu_find_rxpage(rp, addr, &link);
3294
3295 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3296 RCR_ENTRY_PKTBUFSZ_SHIFT];
3297 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3298 *link = (struct page *) page->mapping;
3299 np->ops->unmap_page(np->device, page->index,
3300 PAGE_SIZE, DMA_FROM_DEVICE);
3301 page->index = 0;
3302 page->mapping = NULL;
3303 __free_page(page);
3304 rp->rbr_refill_pending++;
3305 }
3306
3307 index = NEXT_RCR(rp, index);
3308 if (!(val & RCR_ENTRY_MULTI))
3309 break;
3310
3311 }
3312 rp->rcr_index = index;
3313
3314 return num_rcr;
3315}
3316
3317static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
3318{
3319 unsigned int index = rp->rcr_index;
3320 struct sk_buff *skb;
3321 int len, num_rcr;
3322
3323 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3324 if (unlikely(!skb))
3325 return niu_rx_pkt_ignore(np, rp);
3326
3327 num_rcr = 0;
3328 while (1) {
3329 struct page *page, **link;
3330 u32 rcr_size, append_size;
3331 u64 addr, val, off;
3332
3333 num_rcr++;
3334
3335 val = le64_to_cpup(&rp->rcr[index]);
3336
3337 len = (val & RCR_ENTRY_L2_LEN) >>
3338 RCR_ENTRY_L2_LEN_SHIFT;
3339 len -= ETH_FCS_LEN;
3340
3341 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3342 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3343 page = niu_find_rxpage(rp, addr, &link);
3344
3345 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3346 RCR_ENTRY_PKTBUFSZ_SHIFT];
3347
3348 off = addr & ~PAGE_MASK;
3349 append_size = rcr_size;
3350 if (num_rcr == 1) {
3351 int ptype;
3352
3353 off += 2;
3354 append_size -= 2;
3355
3356 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3357 if ((ptype == RCR_PKT_TYPE_TCP ||
3358 ptype == RCR_PKT_TYPE_UDP) &&
3359 !(val & (RCR_ENTRY_NOPORT |
3360 RCR_ENTRY_ERROR)))
3361 skb->ip_summed = CHECKSUM_UNNECESSARY;
3362 else
3363 skb->ip_summed = CHECKSUM_NONE;
3364 }
3365 if (!(val & RCR_ENTRY_MULTI))
3366 append_size = len - skb->len;
3367
3368 niu_rx_skb_append(skb, page, off, append_size);
3369 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3370 *link = (struct page *) page->mapping;
3371 np->ops->unmap_page(np->device, page->index,
3372 PAGE_SIZE, DMA_FROM_DEVICE);
3373 page->index = 0;
3374 page->mapping = NULL;
3375 rp->rbr_refill_pending++;
3376 } else
3377 get_page(page);
3378
3379 index = NEXT_RCR(rp, index);
3380 if (!(val & RCR_ENTRY_MULTI))
3381 break;
3382
3383 }
3384 rp->rcr_index = index;
3385
3386 skb_reserve(skb, NET_IP_ALIGN);
3387 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
3388
3389 rp->rx_packets++;
3390 rp->rx_bytes += skb->len;
3391
3392 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3393 skb_record_rx_queue(skb, rp->rx_channel);
a3138df9
DM		 3394 netif_receive_skb(skb);
3395
3396 return num_rcr;
3397}
3398
3399static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3400{
3401 int blocks_per_page = rp->rbr_blocks_per_page;
3402 int err, index = rp->rbr_index;
3403
3404 err = 0;
3405 while (index < (rp->rbr_table_size - blocks_per_page)) {
3406 err = niu_rbr_add_page(np, rp, mask, index);
3407 if (err)
3408 break;
3409
3410 index += blocks_per_page;
3411 }
3412
3413 rp->rbr_index = index;
3414 return err;
3415}
3416
3417static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3418{
3419 int i;
3420
3421 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3422 struct page *page;
3423
3424 page = rp->rxhash[i];
3425 while (page) {
3426 struct page *next = (struct page *) page->mapping;
3427 u64 base = page->index;
3428
3429 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3430 DMA_FROM_DEVICE);
3431 page->index = 0;
3432 page->mapping = NULL;
3433
3434 __free_page(page);
3435
3436 page = next;
3437 }
3438 }
3439
3440 for (i = 0; i < rp->rbr_table_size; i++)
3441 rp->rbr[i] = cpu_to_le32(0);
3442 rp->rbr_index = 0;
3443}
3444
3445static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3446{
3447 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3448 struct sk_buff *skb = tb->skb;
3449 struct tx_pkt_hdr *tp;
3450 u64 tx_flags;
3451 int i, len;
3452
3453 tp = (struct tx_pkt_hdr *) skb->data;
3454 tx_flags = le64_to_cpup(&tp->flags);
3455
3456 rp->tx_packets++;
3457 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3458 ((tx_flags & TXHDR_PAD) / 2));
3459
3460 len = skb_headlen(skb);
3461 np->ops->unmap_single(np->device, tb->mapping,
3462 len, DMA_TO_DEVICE);
3463
3464 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3465 rp->mark_pending--;
3466
3467 tb->skb = NULL;
3468 do {
3469 idx = NEXT_TX(rp, idx);
3470 len -= MAX_TX_DESC_LEN;
3471 } while (len > 0);
3472
3473 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3474 tb = &rp->tx_buffs[idx];
3475 BUG_ON(tb->skb != NULL);
3476 np->ops->unmap_page(np->device, tb->mapping,
3477 skb_shinfo(skb)->frags[i].size,
3478 DMA_TO_DEVICE);
3479 idx = NEXT_TX(rp, idx);
3480 }
3481
3482 dev_kfree_skb(skb);
3483
3484 return idx;
3485}
3486
3487#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3488
3489static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3490{
b4c21639 3491 struct netdev_queue *txq;
a3138df9 3492 u16 pkt_cnt, tmp;
b4c21639 3493 int cons, index;
a3138df9
DM		 3494 u64 cs;
3495
b4c21639
DM		 3496 index = (rp - np->tx_rings);
3497 txq = netdev_get_tx_queue(np->dev, index);
3498
a3138df9
DM		 3499 cs = rp->tx_cs;
3500 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3501 goto out;
3502
3503 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3504 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3505 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3506
3507 rp->last_pkt_cnt = tmp;
3508
3509 cons = rp->cons;
3510
3511 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3512 np->dev->name, pkt_cnt, cons);
3513
3514 while (pkt_cnt--)
3515 cons = release_tx_packet(np, rp, cons);
3516
3517 rp->cons = cons;
3518 smp_mb();
3519
3520out:
b4c21639 3521 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3522 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3523 __netif_tx_lock(txq, smp_processor_id());
3524 if (netif_tx_queue_stopped(txq) &&
a3138df9 3525 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3526 netif_tx_wake_queue(txq);
3527 __netif_tx_unlock(txq);
a3138df9
DM		 3528 }
3529}
3530
b8a606b8
JDB		 3531static inline void niu_sync_rx_discard_stats(struct niu *np,
3532 struct rx_ring_info *rp,
3533 const int limit)
3534{
3535 /* This elaborate scheme is needed for reading the RX discard
3536 * counters, as they are only 16-bit and can overflow quickly,
3537 * and because the overflow indication bit is not usable as
3538 * the counter value does not wrap, but remains at max value
3539 * 0xFFFF.
3540 *
3541 * In theory and in practice counters can be lost in between
3542 * reading nr64() and clearing the counter nw64(). For this
3543 * reason, the number of counter clearings nw64() is
3544 * limited/reduced though the limit parameter.
3545 */
3546 int rx_channel = rp->rx_channel;
3547 u32 misc, wred;
3548
3549 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3550 * following discard events: IPP (Input Port Process),
3551 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3552 * Block Ring) prefetch buffer is empty.
3553 */
3554 misc = nr64(RXMISC(rx_channel));
3555 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3556 nw64(RXMISC(rx_channel), 0);
3557 rp->rx_errors += misc & RXMISC_COUNT;
3558
3559 if (unlikely(misc & RXMISC_OFLOW))
3560 dev_err(np->device, "rx-%d: Counter overflow "
3561 "RXMISC discard\n", rx_channel);
d231776f
JDB		 3562
3563 niudbg(RX_ERR, "%s-rx-%d: MISC drop=%u over=%u\n",
3564 np->dev->name, rx_channel, misc, misc-limit);
b8a606b8
JDB		 3565 }
3566
3567 /* WRED (Weighted Random Early Discard) by hardware */
3568 wred = nr64(RED_DIS_CNT(rx_channel));
3569 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3570 nw64(RED_DIS_CNT(rx_channel), 0);
3571 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3572
3573 if (unlikely(wred & RED_DIS_CNT_OFLOW))
3574 dev_err(np->device, "rx-%d: Counter overflow "
3575 "WRED discard\n", rx_channel);
d231776f
JDB		 3576
3577 niudbg(RX_ERR, "%s-rx-%d: WRED drop=%u over=%u\n",
3578 np->dev->name, rx_channel, wred, wred-limit);
b8a606b8
JDB		 3579 }
3580}
3581
a3138df9
DM		 3582static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
3583{
3584 int qlen, rcr_done = 0, work_done = 0;
3585 struct rxdma_mailbox *mbox = rp->mbox;
3586 u64 stat;
3587
3588#if 1
3589 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3590 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3591#else
3592 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3593 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3594#endif
3595 mbox->rx_dma_ctl_stat = 0;
3596 mbox->rcrstat_a = 0;
3597
3598 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3599 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
3600
3601 rcr_done = work_done = 0;
3602 qlen = min(qlen, budget);
3603 while (work_done < qlen) {
3604 rcr_done += niu_process_rx_pkt(np, rp);
3605 work_done++;
3606 }
3607
3608 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3609 unsigned int i;
3610
3611 for (i = 0; i < rp->rbr_refill_pending; i++)
3612 niu_rbr_refill(np, rp, GFP_ATOMIC);
3613 rp->rbr_refill_pending = 0;
3614 }
3615
3616 stat = (RX_DMA_CTL_STAT_MEX |
3617 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3618 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3619
3620 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3621
e98def1f
JDB		 3622 /* Only sync discards stats when qlen indicate potential for drops */
3623 if (qlen > 10)
3624 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3625
a3138df9
DM		 3626 return work_done;
3627}
3628
3629static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3630{
3631 u64 v0 = lp->v0;
3632 u32 tx_vec = (v0 >> 32);
3633 u32 rx_vec = (v0 & 0xffffffff);
3634 int i, work_done = 0;
3635
3636 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
3637 np->dev->name, (unsigned long long) v0);
3638
3639 for (i = 0; i < np->num_tx_rings; i++) {
3640 struct tx_ring_info *rp = &np->tx_rings[i];
3641 if (tx_vec & (1 << rp->tx_channel))
3642 niu_tx_work(np, rp);
3643 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3644 }
3645
3646 for (i = 0; i < np->num_rx_rings; i++) {
3647 struct rx_ring_info *rp = &np->rx_rings[i];
3648
3649 if (rx_vec & (1 << rp->rx_channel)) {
3650 int this_work_done;
3651
3652 this_work_done = niu_rx_work(np, rp,
3653 budget);
3654
3655 budget -= this_work_done;
3656 work_done += this_work_done;
3657 }
3658 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3659 }
3660
3661 return work_done;
3662}
3663
3664static int niu_poll(struct napi_struct *napi, int budget)
3665{
3666 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3667 struct niu *np = lp->np;
3668 int work_done;
3669
3670 work_done = niu_poll_core(np, lp, budget);
3671
3672 if (work_done < budget) {
288379f0 3673 napi_complete(napi);
a3138df9
DM		 3674 niu_ldg_rearm(np, lp, 1);
3675 }
3676 return work_done;
3677}
3678
3679static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3680 u64 stat)
3681{
3682 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
3683 np->dev->name, rp->rx_channel);
3684
3685 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
3686 printk("RBR_TMOUT ");
3687 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
3688 printk("RSP_CNT ");
3689 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
3690 printk("BYTE_EN_BUS ");
3691 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
3692 printk("RSP_DAT ");
3693 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
3694 printk("RCR_ACK ");
3695 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
3696 printk("RCR_SHA_PAR ");
3697 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
3698 printk("RBR_PRE_PAR ");
3699 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
3700 printk("CONFIG ");
3701 if (stat & RX_DMA_CTL_STAT_RCRINCON)
3702 printk("RCRINCON ");
3703 if (stat & RX_DMA_CTL_STAT_RCRFULL)
3704 printk("RCRFULL ");
3705 if (stat & RX_DMA_CTL_STAT_RBRFULL)
3706 printk("RBRFULL ");
3707 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
3708 printk("RBRLOGPAGE ");
3709 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
3710 printk("CFIGLOGPAGE ");
3711 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
3712 printk("DC_FIDO ");
3713
3714 printk(")\n");
3715}
3716
3717static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3718{
3719 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3720 int err = 0;
3721
a3138df9
DM		 3722
3723 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3724 RX_DMA_CTL_STAT_PORT_FATAL))
3725 err = -EINVAL;
3726
406f353c
MW		 3727 if (err) {
3728 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
3729 np->dev->name, rp->rx_channel,
3730 (unsigned long long) stat);
3731
3732 niu_log_rxchan_errors(np, rp, stat);
3733 }
3734
a3138df9
DM		 3735 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3736 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3737
3738 return err;
3739}
3740
3741static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3742 u64 cs)
3743{
3744 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
3745 np->dev->name, rp->tx_channel);
3746
3747 if (cs & TX_CS_MBOX_ERR)
3748 printk("MBOX ");
3749 if (cs & TX_CS_PKT_SIZE_ERR)
3750 printk("PKT_SIZE ");
3751 if (cs & TX_CS_TX_RING_OFLOW)
3752 printk("TX_RING_OFLOW ");
3753 if (cs & TX_CS_PREF_BUF_PAR_ERR)
3754 printk("PREF_BUF_PAR ");
3755 if (cs & TX_CS_NACK_PREF)
3756 printk("NACK_PREF ");
3757 if (cs & TX_CS_NACK_PKT_RD)
3758 printk("NACK_PKT_RD ");
3759 if (cs & TX_CS_CONF_PART_ERR)
3760 printk("CONF_PART ");
3761 if (cs & TX_CS_PKT_PRT_ERR)
3762 printk("PKT_PTR ");
3763
3764 printk(")\n");
3765}
3766
3767static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3768{
3769 u64 cs, logh, logl;
3770
3771 cs = nr64(TX_CS(rp->tx_channel));
3772 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3773 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3774
3775 dev_err(np->device, PFX "%s: TX channel %u error, "
3776 "cs[%llx] logh[%llx] logl[%llx]\n",
3777 np->dev->name, rp->tx_channel,
3778 (unsigned long long) cs,
3779 (unsigned long long) logh,
3780 (unsigned long long) logl);
3781
3782 niu_log_txchan_errors(np, rp, cs);
3783
3784 return -ENODEV;
3785}
3786
3787static int niu_mif_interrupt(struct niu *np)
3788{
3789 u64 mif_status = nr64(MIF_STATUS);
3790 int phy_mdint = 0;
3791
3792 if (np->flags & NIU_FLAGS_XMAC) {
3793 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3794
3795 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3796 phy_mdint = 1;
3797 }
3798
3799 dev_err(np->device, PFX "%s: MIF interrupt, "
3800 "stat[%llx] phy_mdint(%d)\n",
3801 np->dev->name, (unsigned long long) mif_status, phy_mdint);
3802
3803 return -ENODEV;
3804}
3805
3806static void niu_xmac_interrupt(struct niu *np)
3807{
3808 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3809 u64 val;
3810
3811 val = nr64_mac(XTXMAC_STATUS);
3812 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3813 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3814 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3815 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3816 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3817 mp->tx_fifo_errors++;
3818 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3819 mp->tx_overflow_errors++;
3820 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3821 mp->tx_max_pkt_size_errors++;
3822 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3823 mp->tx_underflow_errors++;
3824
3825 val = nr64_mac(XRXMAC_STATUS);
3826 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3827 mp->rx_local_faults++;
3828 if (val & XRXMAC_STATUS_RFLT_DET)
3829 mp->rx_remote_faults++;
3830 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3831 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3832 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3833 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3834 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3835 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3836 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3837 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3838 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3839 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3840 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3841 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3842 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3843 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3844 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3845 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3846 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3847 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3848 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3849 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3850 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3851 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3852 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3853 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3854 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3855 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
3856 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
3857 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3858 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3859 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3860 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3861 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3862 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3863 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3864 if (val & XRXMAC_STATUS_RXUFLOW)
3865 mp->rx_underflows++;
3866 if (val & XRXMAC_STATUS_RXOFLOW)
3867 mp->rx_overflows++;
3868
3869 val = nr64_mac(XMAC_FC_STAT);
3870 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3871 mp->pause_off_state++;
3872 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3873 mp->pause_on_state++;
3874 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3875 mp->pause_received++;
3876}
3877
3878static void niu_bmac_interrupt(struct niu *np)
3879{
3880 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
3881 u64 val;
3882
3883 val = nr64_mac(BTXMAC_STATUS);
3884 if (val & BTXMAC_STATUS_UNDERRUN)
3885 mp->tx_underflow_errors++;
3886 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3887 mp->tx_max_pkt_size_errors++;
3888 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3889 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
3890 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3891 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
3892
3893 val = nr64_mac(BRXMAC_STATUS);
3894 if (val & BRXMAC_STATUS_OVERFLOW)
3895 mp->rx_overflows++;
3896 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3897 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
3898 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3899 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3900 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3901 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
3902 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3903 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
3904
3905 val = nr64_mac(BMAC_CTRL_STATUS);
3906 if (val & BMAC_CTRL_STATUS_NOPAUSE)
3907 mp->pause_off_state++;
3908 if (val & BMAC_CTRL_STATUS_PAUSE)
3909 mp->pause_on_state++;
3910 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
3911 mp->pause_received++;
3912}
3913
3914static int niu_mac_interrupt(struct niu *np)
3915{
3916 if (np->flags & NIU_FLAGS_XMAC)
3917 niu_xmac_interrupt(np);
3918 else
3919 niu_bmac_interrupt(np);
3920
3921 return 0;
3922}
3923
3924static void niu_log_device_error(struct niu *np, u64 stat)
3925{
3926 dev_err(np->device, PFX "%s: Core device errors ( ",
3927 np->dev->name);
3928
3929 if (stat & SYS_ERR_MASK_META2)
3930 printk("META2 ");
3931 if (stat & SYS_ERR_MASK_META1)
3932 printk("META1 ");
3933 if (stat & SYS_ERR_MASK_PEU)
3934 printk("PEU ");
3935 if (stat & SYS_ERR_MASK_TXC)
3936 printk("TXC ");
3937 if (stat & SYS_ERR_MASK_RDMC)
3938 printk("RDMC ");
3939 if (stat & SYS_ERR_MASK_TDMC)
3940 printk("TDMC ");
3941 if (stat & SYS_ERR_MASK_ZCP)
3942 printk("ZCP ");
3943 if (stat & SYS_ERR_MASK_FFLP)
3944 printk("FFLP ");
3945 if (stat & SYS_ERR_MASK_IPP)
3946 printk("IPP ");
3947 if (stat & SYS_ERR_MASK_MAC)
3948 printk("MAC ");
3949 if (stat & SYS_ERR_MASK_SMX)
3950 printk("SMX ");
3951
3952 printk(")\n");
3953}
3954
3955static int niu_device_error(struct niu *np)
3956{
3957 u64 stat = nr64(SYS_ERR_STAT);
3958
3959 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
3960 np->dev->name, (unsigned long long) stat);
3961
3962 niu_log_device_error(np, stat);
3963
3964 return -ENODEV;
3965}
3966
406f353c
MW		 3967static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
3968 u64 v0, u64 v1, u64 v2)
a3138df9 3969{
406f353c 3970
a3138df9
DM		 3971 int i, err = 0;
3972
406f353c
MW		 3973 lp->v0 = v0;
3974 lp->v1 = v1;
3975 lp->v2 = v2;
3976
a3138df9
DM		 3977 if (v1 & 0x00000000ffffffffULL) {
3978 u32 rx_vec = (v1 & 0xffffffff);
3979
3980 for (i = 0; i < np->num_rx_rings; i++) {
3981 struct rx_ring_info *rp = &np->rx_rings[i];
3982
3983 if (rx_vec & (1 << rp->rx_channel)) {
3984 int r = niu_rx_error(np, rp);
406f353c 3985 if (r) {
a3138df9 3986 err = r;
406f353c
MW		 3987 } else {
3988 if (!v0)
3989 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3990 RX_DMA_CTL_STAT_MEX);
3991 }
a3138df9
DM		 3992 }
3993 }
3994 }
3995 if (v1 & 0x7fffffff00000000ULL) {
3996 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
3997
3998 for (i = 0; i < np->num_tx_rings; i++) {
3999 struct tx_ring_info *rp = &np->tx_rings[i];
4000
4001 if (tx_vec & (1 << rp->tx_channel)) {
4002 int r = niu_tx_error(np, rp);
4003 if (r)
4004 err = r;
4005 }
4006 }
4007 }
4008 if ((v0 | v1) & 0x8000000000000000ULL) {
4009 int r = niu_mif_interrupt(np);
4010 if (r)
4011 err = r;
4012 }
4013 if (v2) {
4014 if (v2 & 0x01ef) {
4015 int r = niu_mac_interrupt(np);
4016 if (r)
4017 err = r;
4018 }
4019 if (v2 & 0x0210) {
4020 int r = niu_device_error(np);
4021 if (r)
4022 err = r;
4023 }
4024 }
4025
4026 if (err)
4027 niu_enable_interrupts(np, 0);
4028
406f353c 4029 return err;
a3138df9
DM		 4030}
4031
4032static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4033 int ldn)
4034{
4035 struct rxdma_mailbox *mbox = rp->mbox;
4036 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4037
4038 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4039 RX_DMA_CTL_STAT_RCRTO);
4040 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4041
4042 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
4043 np->dev->name, (unsigned long long) stat);
4044}
4045
4046static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4047 int ldn)
4048{
4049 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4050
4051 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
4052 np->dev->name, (unsigned long long) rp->tx_cs);
4053}
4054
4055static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4056{
4057 struct niu_parent *parent = np->parent;
4058 u32 rx_vec, tx_vec;
4059 int i;
4060
4061 tx_vec = (v0 >> 32);
4062 rx_vec = (v0 & 0xffffffff);
4063
4064 for (i = 0; i < np->num_rx_rings; i++) {
4065 struct rx_ring_info *rp = &np->rx_rings[i];
4066 int ldn = LDN_RXDMA(rp->rx_channel);
4067
4068 if (parent->ldg_map[ldn] != ldg)
4069 continue;
4070
4071 nw64(LD_IM0(ldn), LD_IM0_MASK);
4072 if (rx_vec & (1 << rp->rx_channel))
4073 niu_rxchan_intr(np, rp, ldn);
4074 }
4075
4076 for (i = 0; i < np->num_tx_rings; i++) {
4077 struct tx_ring_info *rp = &np->tx_rings[i];
4078 int ldn = LDN_TXDMA(rp->tx_channel);
4079
4080 if (parent->ldg_map[ldn] != ldg)
4081 continue;
4082
4083 nw64(LD_IM0(ldn), LD_IM0_MASK);
4084 if (tx_vec & (1 << rp->tx_channel))
4085 niu_txchan_intr(np, rp, ldn);
4086 }
4087}
4088
4089static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4090 u64 v0, u64 v1, u64 v2)
4091{
288379f0 4092 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4093 lp->v0 = v0;
4094 lp->v1 = v1;
4095 lp->v2 = v2;
4096 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4097 __napi_schedule(&lp->napi);
a3138df9
DM		 4098 }
4099}
4100
4101static irqreturn_t niu_interrupt(int irq, void *dev_id)
4102{
4103 struct niu_ldg *lp = dev_id;
4104 struct niu *np = lp->np;
4105 int ldg = lp->ldg_num;
4106 unsigned long flags;
4107 u64 v0, v1, v2;
4108
4109 if (netif_msg_intr(np))
4110 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
4111 lp, ldg);
4112
4113 spin_lock_irqsave(&np->lock, flags);
4114
4115 v0 = nr64(LDSV0(ldg));
4116 v1 = nr64(LDSV1(ldg));
4117 v2 = nr64(LDSV2(ldg));
4118
4119 if (netif_msg_intr(np))
4120 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4121 (unsigned long long) v0,
4122 (unsigned long long) v1,
4123 (unsigned long long) v2);
4124
4125 if (unlikely(!v0 && !v1 && !v2)) {
4126 spin_unlock_irqrestore(&np->lock, flags);
4127 return IRQ_NONE;
4128 }
4129
4130 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4131 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4132 if (err)
4133 goto out;
4134 }
4135 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4136 niu_schedule_napi(np, lp, v0, v1, v2);
4137 else
4138 niu_ldg_rearm(np, lp, 1);
4139out:
4140 spin_unlock_irqrestore(&np->lock, flags);
4141
4142 return IRQ_HANDLED;
4143}
4144
4145static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4146{
4147 if (rp->mbox) {
4148 np->ops->free_coherent(np->device,
4149 sizeof(struct rxdma_mailbox),
4150 rp->mbox, rp->mbox_dma);
4151 rp->mbox = NULL;
4152 }
4153 if (rp->rcr) {
4154 np->ops->free_coherent(np->device,
4155 MAX_RCR_RING_SIZE * sizeof(__le64),
4156 rp->rcr, rp->rcr_dma);
4157 rp->rcr = NULL;
4158 rp->rcr_table_size = 0;
4159 rp->rcr_index = 0;
4160 }
4161 if (rp->rbr) {
4162 niu_rbr_free(np, rp);
4163
4164 np->ops->free_coherent(np->device,
4165 MAX_RBR_RING_SIZE * sizeof(__le32),
4166 rp->rbr, rp->rbr_dma);
4167 rp->rbr = NULL;
4168 rp->rbr_table_size = 0;
4169 rp->rbr_index = 0;
4170 }
4171 kfree(rp->rxhash);
4172 rp->rxhash = NULL;
4173}
4174
4175static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4176{
4177 if (rp->mbox) {
4178 np->ops->free_coherent(np->device,
4179 sizeof(struct txdma_mailbox),
4180 rp->mbox, rp->mbox_dma);
4181 rp->mbox = NULL;
4182 }
4183 if (rp->descr) {
4184 int i;
4185
4186 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4187 if (rp->tx_buffs[i].skb)
4188 (void) release_tx_packet(np, rp, i);
4189 }
4190
4191 np->ops->free_coherent(np->device,
4192 MAX_TX_RING_SIZE * sizeof(__le64),
4193 rp->descr, rp->descr_dma);
4194 rp->descr = NULL;
4195 rp->pending = 0;
4196 rp->prod = 0;
4197 rp->cons = 0;
4198 rp->wrap_bit = 0;
4199 }
4200}
4201
4202static void niu_free_channels(struct niu *np)
4203{
4204 int i;
4205
4206 if (np->rx_rings) {
4207 for (i = 0; i < np->num_rx_rings; i++) {
4208 struct rx_ring_info *rp = &np->rx_rings[i];
4209
4210 niu_free_rx_ring_info(np, rp);
4211 }
4212 kfree(np->rx_rings);
4213 np->rx_rings = NULL;
4214 np->num_rx_rings = 0;
4215 }
4216
4217 if (np->tx_rings) {
4218 for (i = 0; i < np->num_tx_rings; i++) {
4219 struct tx_ring_info *rp = &np->tx_rings[i];
4220
4221 niu_free_tx_ring_info(np, rp);
4222 }
4223 kfree(np->tx_rings);
4224 np->tx_rings = NULL;
4225 np->num_tx_rings = 0;
4226 }
4227}
4228
4229static int niu_alloc_rx_ring_info(struct niu *np,
4230 struct rx_ring_info *rp)
4231{
4232 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4233
4234 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4235 GFP_KERNEL);
4236 if (!rp->rxhash)
4237 return -ENOMEM;
4238
4239 rp->mbox = np->ops->alloc_coherent(np->device,
4240 sizeof(struct rxdma_mailbox),
4241 &rp->mbox_dma, GFP_KERNEL);
4242 if (!rp->mbox)
4243 return -ENOMEM;
4244 if ((unsigned long)rp->mbox & (64UL - 1)) {
4245 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4246 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
4247 return -EINVAL;
4248 }
4249
4250 rp->rcr = np->ops->alloc_coherent(np->device,
4251 MAX_RCR_RING_SIZE * sizeof(__le64),
4252 &rp->rcr_dma, GFP_KERNEL);
4253 if (!rp->rcr)
4254 return -ENOMEM;
4255 if ((unsigned long)rp->rcr & (64UL - 1)) {
4256 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4257 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
4258 return -EINVAL;
4259 }
4260 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4261 rp->rcr_index = 0;
4262
4263 rp->rbr = np->ops->alloc_coherent(np->device,
4264 MAX_RBR_RING_SIZE * sizeof(__le32),
4265 &rp->rbr_dma, GFP_KERNEL);
4266 if (!rp->rbr)
4267 return -ENOMEM;
4268 if ((unsigned long)rp->rbr & (64UL - 1)) {
4269 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4270 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
4271 return -EINVAL;
4272 }
4273 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4274 rp->rbr_index = 0;
4275 rp->rbr_pending = 0;
4276
4277 return 0;
4278}
4279
4280static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4281{
4282 int mtu = np->dev->mtu;
4283
4284 /* These values are recommended by the HW designers for fair
4285 * utilization of DRR amongst the rings.
4286 */
4287 rp->max_burst = mtu + 32;
4288 if (rp->max_burst > 4096)
4289 rp->max_burst = 4096;
4290}
4291
4292static int niu_alloc_tx_ring_info(struct niu *np,
4293 struct tx_ring_info *rp)
4294{
4295 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4296
4297 rp->mbox = np->ops->alloc_coherent(np->device,
4298 sizeof(struct txdma_mailbox),
4299 &rp->mbox_dma, GFP_KERNEL);
4300 if (!rp->mbox)
4301 return -ENOMEM;
4302 if ((unsigned long)rp->mbox & (64UL - 1)) {
4303 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4304 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
4305 return -EINVAL;
4306 }
4307
4308 rp->descr = np->ops->alloc_coherent(np->device,
4309 MAX_TX_RING_SIZE * sizeof(__le64),
4310 &rp->descr_dma, GFP_KERNEL);
4311 if (!rp->descr)
4312 return -ENOMEM;
4313 if ((unsigned long)rp->descr & (64UL - 1)) {
4314 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
4315 "TXDMA descr table %p\n", np->dev->name, rp->descr);
4316 return -EINVAL;
4317 }
4318
4319 rp->pending = MAX_TX_RING_SIZE;
4320 rp->prod = 0;
4321 rp->cons = 0;
4322 rp->wrap_bit = 0;
4323
4324 /* XXX make these configurable... XXX */
4325 rp->mark_freq = rp->pending / 4;
4326
4327 niu_set_max_burst(np, rp);
4328
4329 return 0;
4330}
4331
4332static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4333{
81429973 4334 u16 bss;
a3138df9 4335
81429973 4336 bss = min(PAGE_SHIFT, 15);
a3138df9 4337
81429973
OJ		 4338 rp->rbr_block_size = 1 << bss;
4339 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4340
4341 rp->rbr_sizes[0] = 256;
4342 rp->rbr_sizes[1] = 1024;
4343 if (np->dev->mtu > ETH_DATA_LEN) {
4344 switch (PAGE_SIZE) {
4345 case 4 * 1024:
4346 rp->rbr_sizes[2] = 4096;
4347 break;
4348
4349 default:
4350 rp->rbr_sizes[2] = 8192;
4351 break;
4352 }
4353 } else {
4354 rp->rbr_sizes[2] = 2048;
4355 }
4356 rp->rbr_sizes[3] = rp->rbr_block_size;
4357}
4358
4359static int niu_alloc_channels(struct niu *np)
4360{
4361 struct niu_parent *parent = np->parent;
4362 int first_rx_channel, first_tx_channel;
4363 int i, port, err;
4364
4365 port = np->port;
4366 first_rx_channel = first_tx_channel = 0;
4367 for (i = 0; i < port; i++) {
4368 first_rx_channel += parent->rxchan_per_port[i];
4369 first_tx_channel += parent->txchan_per_port[i];
4370 }
4371
4372 np->num_rx_rings = parent->rxchan_per_port[port];
4373 np->num_tx_rings = parent->txchan_per_port[port];
4374
b4c21639
DM		 4375 np->dev->real_num_tx_queues = np->num_tx_rings;
4376
a3138df9
DM		 4377 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
4378 GFP_KERNEL);
4379 err = -ENOMEM;
4380 if (!np->rx_rings)
4381 goto out_err;
4382
4383 for (i = 0; i < np->num_rx_rings; i++) {
4384 struct rx_ring_info *rp = &np->rx_rings[i];
4385
4386 rp->np = np;
4387 rp->rx_channel = first_rx_channel + i;
4388
4389 err = niu_alloc_rx_ring_info(np, rp);
4390 if (err)
4391 goto out_err;
4392
4393 niu_size_rbr(np, rp);
4394
4395 /* XXX better defaults, configurable, etc... XXX */
4396 rp->nonsyn_window = 64;
4397 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4398 rp->syn_window = 64;
4399 rp->syn_threshold = rp->rcr_table_size - 64;
4400 rp->rcr_pkt_threshold = 16;
4401 rp->rcr_timeout = 8;
4402 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4403 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4404 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4405
4406 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4407 if (err)
4408 return err;
4409 }
4410
4411 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
4412 GFP_KERNEL);
4413 err = -ENOMEM;
4414 if (!np->tx_rings)
4415 goto out_err;
4416
4417 for (i = 0; i < np->num_tx_rings; i++) {
4418 struct tx_ring_info *rp = &np->tx_rings[i];
4419
4420 rp->np = np;
4421 rp->tx_channel = first_tx_channel + i;
4422
4423 err = niu_alloc_tx_ring_info(np, rp);
4424 if (err)
4425 goto out_err;
4426 }
4427
4428 return 0;
4429
4430out_err:
4431 niu_free_channels(np);
4432 return err;
4433}
4434
4435static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4436{
4437 int limit = 1000;
4438
4439 while (--limit > 0) {
4440 u64 val = nr64(TX_CS(channel));
4441 if (val & TX_CS_SNG_STATE)
4442 return 0;
4443 }
4444 return -ENODEV;
4445}
4446
4447static int niu_tx_channel_stop(struct niu *np, int channel)
4448{
4449 u64 val = nr64(TX_CS(channel));
4450
4451 val |= TX_CS_STOP_N_GO;
4452 nw64(TX_CS(channel), val);
4453
4454 return niu_tx_cs_sng_poll(np, channel);
4455}
4456
4457static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4458{
4459 int limit = 1000;
4460
4461 while (--limit > 0) {
4462 u64 val = nr64(TX_CS(channel));
4463 if (!(val & TX_CS_RST))
4464 return 0;
4465 }
4466 return -ENODEV;
4467}
4468
4469static int niu_tx_channel_reset(struct niu *np, int channel)
4470{
4471 u64 val = nr64(TX_CS(channel));
4472 int err;
4473
4474 val |= TX_CS_RST;
4475 nw64(TX_CS(channel), val);
4476
4477 err = niu_tx_cs_reset_poll(np, channel);
4478 if (!err)
4479 nw64(TX_RING_KICK(channel), 0);
4480
4481 return err;
4482}
4483
4484static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4485{
4486 u64 val;
4487
4488 nw64(TX_LOG_MASK1(channel), 0);
4489 nw64(TX_LOG_VAL1(channel), 0);
4490 nw64(TX_LOG_MASK2(channel), 0);
4491 nw64(TX_LOG_VAL2(channel), 0);
4492 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4493 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4494 nw64(TX_LOG_PAGE_HDL(channel), 0);
4495
4496 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4497 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4498 nw64(TX_LOG_PAGE_VLD(channel), val);
4499
4500 /* XXX TXDMA 32bit mode? XXX */
4501
4502 return 0;
4503}
4504
4505static void niu_txc_enable_port(struct niu *np, int on)
4506{
4507 unsigned long flags;
4508 u64 val, mask;
4509
4510 niu_lock_parent(np, flags);
4511 val = nr64(TXC_CONTROL);
4512 mask = (u64)1 << np->port;
4513 if (on) {
4514 val |= TXC_CONTROL_ENABLE | mask;
4515 } else {
4516 val &= ~mask;
4517 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4518 val &= ~TXC_CONTROL_ENABLE;
4519 }
4520 nw64(TXC_CONTROL, val);
4521 niu_unlock_parent(np, flags);
4522}
4523
4524static void niu_txc_set_imask(struct niu *np, u64 imask)
4525{
4526 unsigned long flags;
4527 u64 val;
4528
4529 niu_lock_parent(np, flags);
4530 val = nr64(TXC_INT_MASK);
4531 val &= ~TXC_INT_MASK_VAL(np->port);
4532 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4533 niu_unlock_parent(np, flags);
4534}
4535
4536static void niu_txc_port_dma_enable(struct niu *np, int on)
4537{
4538 u64 val = 0;
4539
4540 if (on) {
4541 int i;
4542
4543 for (i = 0; i < np->num_tx_rings; i++)
4544 val |= (1 << np->tx_rings[i].tx_channel);
4545 }
4546 nw64(TXC_PORT_DMA(np->port), val);
4547}
4548
4549static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4550{
4551 int err, channel = rp->tx_channel;
4552 u64 val, ring_len;
4553
4554 err = niu_tx_channel_stop(np, channel);
4555 if (err)
4556 return err;
4557
4558 err = niu_tx_channel_reset(np, channel);
4559 if (err)
4560 return err;
4561
4562 err = niu_tx_channel_lpage_init(np, channel);
4563 if (err)
4564 return err;
4565
4566 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4567 nw64(TX_ENT_MSK(channel), 0);
4568
4569 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4570 TX_RNG_CFIG_STADDR)) {
4571 dev_err(np->device, PFX "%s: TX ring channel %d "
4572 "DMA addr (%llx) is not aligned.\n",
4573 np->dev->name, channel,
4574 (unsigned long long) rp->descr_dma);
4575 return -EINVAL;
4576 }
4577
4578 /* The length field in TX_RNG_CFIG is measured in 64-byte
4579 * blocks. rp->pending is the number of TX descriptors in
4580 * our ring, 8 bytes each, thus we divide by 8 bytes more
4581 * to get the proper value the chip wants.
4582 */
4583 ring_len = (rp->pending / 8);
4584
4585 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4586 rp->descr_dma);
4587 nw64(TX_RNG_CFIG(channel), val);
4588
4589 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4590 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
4591 dev_err(np->device, PFX "%s: TX ring channel %d "
4592 "MBOX addr (%llx) is has illegal bits.\n",
4593 np->dev->name, channel,
4594 (unsigned long long) rp->mbox_dma);
4595 return -EINVAL;
4596 }
4597 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4598 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4599
4600 nw64(TX_CS(channel), 0);
4601
4602 rp->last_pkt_cnt = 0;
4603
4604 return 0;
4605}
4606
4607static void niu_init_rdc_groups(struct niu *np)
4608{
4609 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4610 int i, first_table_num = tp->first_table_num;
4611
4612 for (i = 0; i < tp->num_tables; i++) {
4613 struct rdc_table *tbl = &tp->tables[i];
4614 int this_table = first_table_num + i;
4615 int slot;
4616
4617 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4618 nw64(RDC_TBL(this_table, slot),
4619 tbl->rxdma_channel[slot]);
4620 }
4621
4622 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4623}
4624
4625static void niu_init_drr_weight(struct niu *np)
4626{
4627 int type = phy_decode(np->parent->port_phy, np->port);
4628 u64 val;
4629
4630 switch (type) {
4631 case PORT_TYPE_10G:
4632 val = PT_DRR_WEIGHT_DEFAULT_10G;
4633 break;
4634
4635 case PORT_TYPE_1G:
4636 default:
4637 val = PT_DRR_WEIGHT_DEFAULT_1G;
4638 break;
4639 }
4640 nw64(PT_DRR_WT(np->port), val);
4641}
4642
4643static int niu_init_hostinfo(struct niu *np)
4644{
4645 struct niu_parent *parent = np->parent;
4646 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4647 int i, err, num_alt = niu_num_alt_addr(np);
4648 int first_rdc_table = tp->first_table_num;
4649
4650 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4651 if (err)
4652 return err;
4653
4654 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4655 if (err)
4656 return err;
4657
4658 for (i = 0; i < num_alt; i++) {
4659 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4660 if (err)
4661 return err;
4662 }
4663
4664 return 0;
4665}
4666
4667static int niu_rx_channel_reset(struct niu *np, int channel)
4668{
4669 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4670 RXDMA_CFIG1_RST, 1000, 10,
4671 "RXDMA_CFIG1");
4672}
4673
4674static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4675{
4676 u64 val;
4677
4678 nw64(RX_LOG_MASK1(channel), 0);
4679 nw64(RX_LOG_VAL1(channel), 0);
4680 nw64(RX_LOG_MASK2(channel), 0);
4681 nw64(RX_LOG_VAL2(channel), 0);
4682 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4683 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4684 nw64(RX_LOG_PAGE_HDL(channel), 0);
4685
4686 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4687 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4688 nw64(RX_LOG_PAGE_VLD(channel), val);
4689
4690 return 0;
4691}
4692
4693static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4694{
4695 u64 val;
4696
4697 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4698 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4699 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4700 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4701 nw64(RDC_RED_PARA(rp->rx_channel), val);
4702}
4703
4704static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4705{
4706 u64 val = 0;
4707
4708 switch (rp->rbr_block_size) {
4709 case 4 * 1024:
4710 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4711 break;
4712 case 8 * 1024:
4713 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4714 break;
4715 case 16 * 1024:
4716 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4717 break;
4718 case 32 * 1024:
4719 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4720 break;
4721 default:
4722 return -EINVAL;
4723 }
4724 val |= RBR_CFIG_B_VLD2;
4725 switch (rp->rbr_sizes[2]) {
4726 case 2 * 1024:
4727 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4728 break;
4729 case 4 * 1024:
4730 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4731 break;
4732 case 8 * 1024:
4733 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4734 break;
4735 case 16 * 1024:
4736 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4737 break;
4738
4739 default:
4740 return -EINVAL;
4741 }
4742 val |= RBR_CFIG_B_VLD1;
4743 switch (rp->rbr_sizes[1]) {
4744 case 1 * 1024:
4745 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4746 break;
4747 case 2 * 1024:
4748 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4749 break;
4750 case 4 * 1024:
4751 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4752 break;
4753 case 8 * 1024:
4754 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4755 break;
4756
4757 default:
4758 return -EINVAL;
4759 }
4760 val |= RBR_CFIG_B_VLD0;
4761 switch (rp->rbr_sizes[0]) {
4762 case 256:
4763 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4764 break;
4765 case 512:
4766 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4767 break;
4768 case 1 * 1024:
4769 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4770 break;
4771 case 2 * 1024:
4772 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4773 break;
4774
4775 default:
4776 return -EINVAL;
4777 }
4778
4779 *ret = val;
4780 return 0;
4781}
4782
4783static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4784{
4785 u64 val = nr64(RXDMA_CFIG1(channel));
4786 int limit;
4787
4788 if (on)
4789 val |= RXDMA_CFIG1_EN;
4790 else
4791 val &= ~RXDMA_CFIG1_EN;
4792 nw64(RXDMA_CFIG1(channel), val);
4793
4794 limit = 1000;
4795 while (--limit > 0) {
4796 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4797 break;
4798 udelay(10);
4799 }
4800 if (limit <= 0)
4801 return -ENODEV;
4802 return 0;
4803}
4804
4805static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4806{
4807 int err, channel = rp->rx_channel;
4808 u64 val;
4809
4810 err = niu_rx_channel_reset(np, channel);
4811 if (err)
4812 return err;
4813
4814 err = niu_rx_channel_lpage_init(np, channel);
4815 if (err)
4816 return err;
4817
4818 niu_rx_channel_wred_init(np, rp);
4819
4820 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4821 nw64(RX_DMA_CTL_STAT(channel),
4822 (RX_DMA_CTL_STAT_MEX |
4823 RX_DMA_CTL_STAT_RCRTHRES |
4824 RX_DMA_CTL_STAT_RCRTO |
4825 RX_DMA_CTL_STAT_RBR_EMPTY));
4826 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4827 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
4828 nw64(RBR_CFIG_A(channel),
4829 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4830 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4831 err = niu_compute_rbr_cfig_b(rp, &val);
4832 if (err)
4833 return err;
4834 nw64(RBR_CFIG_B(channel), val);
4835 nw64(RCRCFIG_A(channel),
4836 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4837 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4838 nw64(RCRCFIG_B(channel),
4839 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4840 RCRCFIG_B_ENTOUT |
4841 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4842
4843 err = niu_enable_rx_channel(np, channel, 1);
4844 if (err)
4845 return err;
4846
4847 nw64(RBR_KICK(channel), rp->rbr_index);
4848
4849 val = nr64(RX_DMA_CTL_STAT(channel));
4850 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4851 nw64(RX_DMA_CTL_STAT(channel), val);
4852
4853 return 0;
4854}
4855
4856static int niu_init_rx_channels(struct niu *np)
4857{
4858 unsigned long flags;
4859 u64 seed = jiffies_64;
4860 int err, i;
4861
4862 niu_lock_parent(np, flags);
4863 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4864 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4865 niu_unlock_parent(np, flags);
4866
4867 /* XXX RXDMA 32bit mode? XXX */
4868
4869 niu_init_rdc_groups(np);
4870 niu_init_drr_weight(np);
4871
4872 err = niu_init_hostinfo(np);
4873 if (err)
4874 return err;
4875
4876 for (i = 0; i < np->num_rx_rings; i++) {
4877 struct rx_ring_info *rp = &np->rx_rings[i];
4878
4879 err = niu_init_one_rx_channel(np, rp);
4880 if (err)
4881 return err;
4882 }
4883
4884 return 0;
4885}
4886
4887static int niu_set_ip_frag_rule(struct niu *np)
4888{
4889 struct niu_parent *parent = np->parent;
4890 struct niu_classifier *cp = &np->clas;
4891 struct niu_tcam_entry *tp;
4892 int index, err;
4893
4894 /* XXX fix this allocation scheme XXX */
4895 index = cp->tcam_index;
4896 tp = &parent->tcam[index];
4897
4898 /* Note that the noport bit is the same in both ipv4 and
4899 * ipv6 format TCAM entries.
4900 */
4901 memset(tp, 0, sizeof(*tp));
4902 tp->key[1] = TCAM_V4KEY1_NOPORT;
4903 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
4904 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
4905 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
4906 err = tcam_write(np, index, tp->key, tp->key_mask);
4907 if (err)
4908 return err;
4909 err = tcam_assoc_write(np, index, tp->assoc_data);
4910 if (err)
4911 return err;
4912
4913 return 0;
4914}
4915
4916static int niu_init_classifier_hw(struct niu *np)
4917{
4918 struct niu_parent *parent = np->parent;
4919 struct niu_classifier *cp = &np->clas;
4920 int i, err;
4921
4922 nw64(H1POLY, cp->h1_init);
4923 nw64(H2POLY, cp->h2_init);
4924
4925 err = niu_init_hostinfo(np);
4926 if (err)
4927 return err;
4928
4929 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
4930 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
4931
4932 vlan_tbl_write(np, i, np->port,
4933 vp->vlan_pref, vp->rdc_num);
4934 }
4935
4936 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
4937 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
4938
4939 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
4940 ap->rdc_num, ap->mac_pref);
4941 if (err)
4942 return err;
4943 }
4944
4945 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
4946 int index = i - CLASS_CODE_USER_PROG1;
4947
4948 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
4949 if (err)
4950 return err;
4951 err = niu_set_flow_key(np, i, parent->flow_key[index]);
4952 if (err)
4953 return err;
4954 }
4955
4956 err = niu_set_ip_frag_rule(np);
4957 if (err)
4958 return err;
4959
4960 tcam_enable(np, 1);
4961
4962 return 0;
4963}
4964
4965static int niu_zcp_write(struct niu *np, int index, u64 *data)
4966{
4967 nw64(ZCP_RAM_DATA0, data[0]);
4968 nw64(ZCP_RAM_DATA1, data[1]);
4969 nw64(ZCP_RAM_DATA2, data[2]);
4970 nw64(ZCP_RAM_DATA3, data[3]);
4971 nw64(ZCP_RAM_DATA4, data[4]);
4972 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
4973 nw64(ZCP_RAM_ACC,
4974 (ZCP_RAM_ACC_WRITE |
4975 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4976 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4977
4978 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4979 1000, 100);
4980}
4981
4982static int niu_zcp_read(struct niu *np, int index, u64 *data)
4983{
4984 int err;
4985
4986 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
4987 1000, 100);
4988 if (err) {
4989 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
4990 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
4991 (unsigned long long) nr64(ZCP_RAM_ACC));
4992 return err;
4993 }
4994
4995 nw64(ZCP_RAM_ACC,
4996 (ZCP_RAM_ACC_READ |
4997 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
4998 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
4999
5000 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5001 1000, 100);
5002 if (err) {
5003 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
5004 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
5005 (unsigned long long) nr64(ZCP_RAM_ACC));
5006 return err;
5007 }
5008
5009 data[0] = nr64(ZCP_RAM_DATA0);
5010 data[1] = nr64(ZCP_RAM_DATA1);
5011 data[2] = nr64(ZCP_RAM_DATA2);
5012 data[3] = nr64(ZCP_RAM_DATA3);
5013 data[4] = nr64(ZCP_RAM_DATA4);
5014
5015 return 0;
5016}
5017
5018static void niu_zcp_cfifo_reset(struct niu *np)
5019{
5020 u64 val = nr64(RESET_CFIFO);
5021
5022 val |= RESET_CFIFO_RST(np->port);
5023 nw64(RESET_CFIFO, val);
5024 udelay(10);
5025
5026 val &= ~RESET_CFIFO_RST(np->port);
5027 nw64(RESET_CFIFO, val);
5028}
5029
5030static int niu_init_zcp(struct niu *np)
5031{
5032 u64 data[5], rbuf[5];
5033 int i, max, err;
5034
5035 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5036 if (np->port == 0 || np->port == 1)
5037 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5038 else
5039 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5040 } else
5041 max = NIU_CFIFO_ENTRIES;
5042
5043 data[0] = 0;
5044 data[1] = 0;
5045 data[2] = 0;
5046 data[3] = 0;
5047 data[4] = 0;
5048
5049 for (i = 0; i < max; i++) {
5050 err = niu_zcp_write(np, i, data);
5051 if (err)
5052 return err;
5053 err = niu_zcp_read(np, i, rbuf);
5054 if (err)
5055 return err;
5056 }
5057
5058 niu_zcp_cfifo_reset(np);
5059 nw64(CFIFO_ECC(np->port), 0);
5060 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5061 (void) nr64(ZCP_INT_STAT);
5062 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5063
5064 return 0;
5065}
5066
5067static void niu_ipp_write(struct niu *np, int index, u64 *data)
5068{
5069 u64 val = nr64_ipp(IPP_CFIG);
5070
5071 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5072 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5073 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5074 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5075 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5076 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5077 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5078 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5079}
5080
5081static void niu_ipp_read(struct niu *np, int index, u64 *data)
5082{
5083 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5084 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5085 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5086 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5087 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5088 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5089}
5090
5091static int niu_ipp_reset(struct niu *np)
5092{
5093 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5094 1000, 100, "IPP_CFIG");
5095}
5096
5097static int niu_init_ipp(struct niu *np)
5098{
5099 u64 data[5], rbuf[5], val;
5100 int i, max, err;
5101
5102 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5103 if (np->port == 0 || np->port == 1)
5104 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5105 else
5106 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5107 } else
5108 max = NIU_DFIFO_ENTRIES;
5109
5110 data[0] = 0;
5111 data[1] = 0;
5112 data[2] = 0;
5113 data[3] = 0;
5114 data[4] = 0;
5115
5116 for (i = 0; i < max; i++) {
5117 niu_ipp_write(np, i, data);
5118 niu_ipp_read(np, i, rbuf);
5119 }
5120
5121 (void) nr64_ipp(IPP_INT_STAT);
5122 (void) nr64_ipp(IPP_INT_STAT);
5123
5124 err = niu_ipp_reset(np);
5125 if (err)
5126 return err;
5127
5128 (void) nr64_ipp(IPP_PKT_DIS);
5129 (void) nr64_ipp(IPP_BAD_CS_CNT);
5130 (void) nr64_ipp(IPP_ECC);
5131
5132 (void) nr64_ipp(IPP_INT_STAT);
5133
5134 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5135
5136 val = nr64_ipp(IPP_CFIG);
5137 val &= ~IPP_CFIG_IP_MAX_PKT;
5138 val |= (IPP_CFIG_IPP_ENABLE |
5139 IPP_CFIG_DFIFO_ECC_EN |
5140 IPP_CFIG_DROP_BAD_CRC |
5141 IPP_CFIG_CKSUM_EN |
5142 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5143 nw64_ipp(IPP_CFIG, val);
5144
5145 return 0;
5146}
5147
0c3b091b 5148static void niu_handle_led(struct niu *np, int status)
a3138df9 5149{
a3138df9 5150 u64 val;
a3138df9
DM		 5151 val = nr64_mac(XMAC_CONFIG);
5152
5153 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5154 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5155 if (status) {
a3138df9
DM		 5156 val |= XMAC_CONFIG_LED_POLARITY;
5157 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5158 } else {
5159 val |= XMAC_CONFIG_FORCE_LED_ON;
5160 val &= ~XMAC_CONFIG_LED_POLARITY;
5161 }
5162 }
5163
0c3b091b
ML		 5164 nw64_mac(XMAC_CONFIG, val);
5165}
5166
5167static void niu_init_xif_xmac(struct niu *np)
5168{
5169 struct niu_link_config *lp = &np->link_config;
5170 u64 val;
5171
5fbd7e24
MW		 5172 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5173 val = nr64(MIF_CONFIG);
5174 val |= MIF_CONFIG_ATCA_GE;
5175 nw64(MIF_CONFIG, val);
5176 }
5177
0c3b091b 5178 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5179 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5180
5181 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5182
5183 if (lp->loopback_mode == LOOPBACK_MAC) {
5184 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5185 val |= XMAC_CONFIG_LOOPBACK;
5186 } else {
5187 val &= ~XMAC_CONFIG_LOOPBACK;
5188 }
5189
5190 if (np->flags & NIU_FLAGS_10G) {
5191 val &= ~XMAC_CONFIG_LFS_DISABLE;
5192 } else {
5193 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5194 if (!(np->flags & NIU_FLAGS_FIBER) &&
5195 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5196 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5197 else
5198 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5199 }
5200
5201 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5202
5203 if (lp->active_speed == SPEED_100)
5204 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5205 else
5206 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5207
5208 nw64_mac(XMAC_CONFIG, val);
5209
5210 val = nr64_mac(XMAC_CONFIG);
5211 val &= ~XMAC_CONFIG_MODE_MASK;
5212 if (np->flags & NIU_FLAGS_10G) {
5213 val |= XMAC_CONFIG_MODE_XGMII;
5214 } else {
5215 if (lp->active_speed == SPEED_100)
5216 val |= XMAC_CONFIG_MODE_MII;
5217 else
5218 val |= XMAC_CONFIG_MODE_GMII;
5219 }
5220
5221 nw64_mac(XMAC_CONFIG, val);
5222}
5223
5224static void niu_init_xif_bmac(struct niu *np)
5225{
5226 struct niu_link_config *lp = &np->link_config;
5227 u64 val;
5228
5229 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5230
5231 if (lp->loopback_mode == LOOPBACK_MAC)
5232 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5233 else
5234 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5235
5236 if (lp->active_speed == SPEED_1000)
5237 val |= BMAC_XIF_CONFIG_GMII_MODE;
5238 else
5239 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5240
5241 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5242 BMAC_XIF_CONFIG_LED_POLARITY);
5243
5244 if (!(np->flags & NIU_FLAGS_10G) &&
5245 !(np->flags & NIU_FLAGS_FIBER) &&
5246 lp->active_speed == SPEED_100)
5247 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5248 else
5249 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5250
5251 nw64_mac(BMAC_XIF_CONFIG, val);
5252}
5253
5254static void niu_init_xif(struct niu *np)
5255{
5256 if (np->flags & NIU_FLAGS_XMAC)
5257 niu_init_xif_xmac(np);
5258 else
5259 niu_init_xif_bmac(np);
5260}
5261
5262static void niu_pcs_mii_reset(struct niu *np)
5263{
5fbd7e24 5264 int limit = 1000;
a3138df9
DM		 5265 u64 val = nr64_pcs(PCS_MII_CTL);
5266 val |= PCS_MII_CTL_RST;
5267 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5268 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5269 udelay(100);
5270 val = nr64_pcs(PCS_MII_CTL);
5271 }
a3138df9
DM		 5272}
5273
5274static void niu_xpcs_reset(struct niu *np)
5275{
5fbd7e24 5276 int limit = 1000;
a3138df9
DM		 5277 u64 val = nr64_xpcs(XPCS_CONTROL1);
5278 val |= XPCS_CONTROL1_RESET;
5279 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5280 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5281 udelay(100);
5282 val = nr64_xpcs(XPCS_CONTROL1);
5283 }
a3138df9
DM		 5284}
5285
5286static int niu_init_pcs(struct niu *np)
5287{
5288 struct niu_link_config *lp = &np->link_config;
5289 u64 val;
5290
5fbd7e24
MW		 5291 switch (np->flags & (NIU_FLAGS_10G |
5292 NIU_FLAGS_FIBER |
5293 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5294 case NIU_FLAGS_FIBER:
5295 /* 1G fiber */
5296 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5297 nw64_pcs(PCS_DPATH_MODE, 0);
5298 niu_pcs_mii_reset(np);
5299 break;
5300
5301 case NIU_FLAGS_10G:
5302 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5303 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5304 /* 10G SERDES */
a3138df9
DM		 5305 if (!(np->flags & NIU_FLAGS_XMAC))
5306 return -EINVAL;
5307
5308 /* 10G copper or fiber */
5309 val = nr64_mac(XMAC_CONFIG);
5310 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5311 nw64_mac(XMAC_CONFIG, val);
5312
5313 niu_xpcs_reset(np);
5314
5315 val = nr64_xpcs(XPCS_CONTROL1);
5316 if (lp->loopback_mode == LOOPBACK_PHY)
5317 val |= XPCS_CONTROL1_LOOPBACK;
5318 else
5319 val &= ~XPCS_CONTROL1_LOOPBACK;
5320 nw64_xpcs(XPCS_CONTROL1, val);
5321
5322 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5323 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5324 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5325 break;
5326
5fbd7e24
MW		 5327
5328 case NIU_FLAGS_XCVR_SERDES:
5329 /* 1G SERDES */
5330 niu_pcs_mii_reset(np);
5331 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5332 nw64_pcs(PCS_DPATH_MODE, 0);
5333 break;
5334
a3138df9
DM		 5335 case 0:
5336 /* 1G copper */
5fbd7e24
MW		 5337 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5338 /* 1G RGMII FIBER */
a3138df9
DM		 5339 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5340 niu_pcs_mii_reset(np);
5341 break;
5342
5343 default:
5344 return -EINVAL;
5345 }
5346
5347 return 0;
5348}
5349
5350static int niu_reset_tx_xmac(struct niu *np)
5351{
5352 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5353 (XTXMAC_SW_RST_REG_RS |
5354 XTXMAC_SW_RST_SOFT_RST),
5355 1000, 100, "XTXMAC_SW_RST");
5356}
5357
5358static int niu_reset_tx_bmac(struct niu *np)
5359{
5360 int limit;
5361
5362 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5363 limit = 1000;
5364 while (--limit >= 0) {
5365 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5366 break;
5367 udelay(100);
5368 }
5369 if (limit < 0) {
5370 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
5371 "BTXMAC_SW_RST[%llx]\n",
5372 np->port,
5373 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5374 return -ENODEV;
5375 }
5376
5377 return 0;
5378}
5379
5380static int niu_reset_tx_mac(struct niu *np)
5381{
5382 if (np->flags & NIU_FLAGS_XMAC)
5383 return niu_reset_tx_xmac(np);
5384 else
5385 return niu_reset_tx_bmac(np);
5386}
5387
5388static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5389{
5390 u64 val;
5391
5392 val = nr64_mac(XMAC_MIN);
5393 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5394 XMAC_MIN_RX_MIN_PKT_SIZE);
5395 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5396 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5397 nw64_mac(XMAC_MIN, val);
5398
5399 nw64_mac(XMAC_MAX, max);
5400
5401 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5402
5403 val = nr64_mac(XMAC_IPG);
5404 if (np->flags & NIU_FLAGS_10G) {
5405 val &= ~XMAC_IPG_IPG_XGMII;
5406 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5407 } else {
5408 val &= ~XMAC_IPG_IPG_MII_GMII;
5409 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5410 }
5411 nw64_mac(XMAC_IPG, val);
5412
5413 val = nr64_mac(XMAC_CONFIG);
5414 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5415 XMAC_CONFIG_STRETCH_MODE |
5416 XMAC_CONFIG_VAR_MIN_IPG_EN |
5417 XMAC_CONFIG_TX_ENABLE);
5418 nw64_mac(XMAC_CONFIG, val);
5419
5420 nw64_mac(TXMAC_FRM_CNT, 0);
5421 nw64_mac(TXMAC_BYTE_CNT, 0);
5422}
5423
5424static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5425{
5426 u64 val;
5427
5428 nw64_mac(BMAC_MIN_FRAME, min);
5429 nw64_mac(BMAC_MAX_FRAME, max);
5430
5431 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5432 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5433 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5434
5435 val = nr64_mac(BTXMAC_CONFIG);
5436 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5437 BTXMAC_CONFIG_ENABLE);
5438 nw64_mac(BTXMAC_CONFIG, val);
5439}
5440
5441static void niu_init_tx_mac(struct niu *np)
5442{
5443 u64 min, max;
5444
5445 min = 64;
5446 if (np->dev->mtu > ETH_DATA_LEN)
5447 max = 9216;
5448 else
5449 max = 1522;
5450
5451 /* The XMAC_MIN register only accepts values for TX min which
5452 * have the low 3 bits cleared.
5453 */
5454 BUILD_BUG_ON(min & 0x7);
5455
5456 if (np->flags & NIU_FLAGS_XMAC)
5457 niu_init_tx_xmac(np, min, max);
5458 else
5459 niu_init_tx_bmac(np, min, max);
5460}
5461
5462static int niu_reset_rx_xmac(struct niu *np)
5463{
5464 int limit;
5465
5466 nw64_mac(XRXMAC_SW_RST,
5467 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5468 limit = 1000;
5469 while (--limit >= 0) {
5470 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5471 XRXMAC_SW_RST_SOFT_RST)))
5472 break;
5473 udelay(100);
5474 }
5475 if (limit < 0) {
5476 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
5477 "XRXMAC_SW_RST[%llx]\n",
5478 np->port,
5479 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5480 return -ENODEV;
5481 }
5482
5483 return 0;
5484}
5485
5486static int niu_reset_rx_bmac(struct niu *np)
5487{
5488 int limit;
5489
5490 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5491 limit = 1000;
5492 while (--limit >= 0) {
5493 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5494 break;
5495 udelay(100);
5496 }
5497 if (limit < 0) {
5498 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
5499 "BRXMAC_SW_RST[%llx]\n",
5500 np->port,
5501 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5502 return -ENODEV;
5503 }
5504
5505 return 0;
5506}
5507
5508static int niu_reset_rx_mac(struct niu *np)
5509{
5510 if (np->flags & NIU_FLAGS_XMAC)
5511 return niu_reset_rx_xmac(np);
5512 else
5513 return niu_reset_rx_bmac(np);
5514}
5515
5516static void niu_init_rx_xmac(struct niu *np)
5517{
5518 struct niu_parent *parent = np->parent;
5519 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5520 int first_rdc_table = tp->first_table_num;
5521 unsigned long i;
5522 u64 val;
5523
5524 nw64_mac(XMAC_ADD_FILT0, 0);
5525 nw64_mac(XMAC_ADD_FILT1, 0);
5526 nw64_mac(XMAC_ADD_FILT2, 0);
5527 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5528 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5529 for (i = 0; i < MAC_NUM_HASH; i++)
5530 nw64_mac(XMAC_HASH_TBL(i), 0);
5531 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5532 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5533 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5534
5535 val = nr64_mac(XMAC_CONFIG);
5536 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5537 XMAC_CONFIG_PROMISCUOUS |
5538 XMAC_CONFIG_PROMISC_GROUP |
5539 XMAC_CONFIG_ERR_CHK_DIS |
5540 XMAC_CONFIG_RX_CRC_CHK_DIS |
5541 XMAC_CONFIG_RESERVED_MULTICAST |
5542 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5543 XMAC_CONFIG_ADDR_FILTER_EN |
5544 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5545 XMAC_CONFIG_STRIP_CRC |
5546 XMAC_CONFIG_PASS_FLOW_CTRL |
5547 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5548 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5549 nw64_mac(XMAC_CONFIG, val);
5550
5551 nw64_mac(RXMAC_BT_CNT, 0);
5552 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5553 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5554 nw64_mac(RXMAC_FRAG_CNT, 0);
5555 nw64_mac(RXMAC_HIST_CNT1, 0);
5556 nw64_mac(RXMAC_HIST_CNT2, 0);
5557 nw64_mac(RXMAC_HIST_CNT3, 0);
5558 nw64_mac(RXMAC_HIST_CNT4, 0);
5559 nw64_mac(RXMAC_HIST_CNT5, 0);
5560 nw64_mac(RXMAC_HIST_CNT6, 0);
5561 nw64_mac(RXMAC_HIST_CNT7, 0);
5562 nw64_mac(RXMAC_MPSZER_CNT, 0);
5563 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5564 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5565 nw64_mac(LINK_FAULT_CNT, 0);
5566}
5567
5568static void niu_init_rx_bmac(struct niu *np)
5569{
5570 struct niu_parent *parent = np->parent;
5571 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5572 int first_rdc_table = tp->first_table_num;
5573 unsigned long i;
5574 u64 val;
5575
5576 nw64_mac(BMAC_ADD_FILT0, 0);
5577 nw64_mac(BMAC_ADD_FILT1, 0);
5578 nw64_mac(BMAC_ADD_FILT2, 0);
5579 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5580 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5581 for (i = 0; i < MAC_NUM_HASH; i++)
5582 nw64_mac(BMAC_HASH_TBL(i), 0);
5583 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5584 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5585 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5586
5587 val = nr64_mac(BRXMAC_CONFIG);
5588 val &= ~(BRXMAC_CONFIG_ENABLE |
5589 BRXMAC_CONFIG_STRIP_PAD |
5590 BRXMAC_CONFIG_STRIP_FCS |
5591 BRXMAC_CONFIG_PROMISC |
5592 BRXMAC_CONFIG_PROMISC_GRP |
5593 BRXMAC_CONFIG_ADDR_FILT_EN |
5594 BRXMAC_CONFIG_DISCARD_DIS);
5595 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5596 nw64_mac(BRXMAC_CONFIG, val);
5597
5598 val = nr64_mac(BMAC_ADDR_CMPEN);
5599 val |= BMAC_ADDR_CMPEN_EN0;
5600 nw64_mac(BMAC_ADDR_CMPEN, val);
5601}
5602
5603static void niu_init_rx_mac(struct niu *np)
5604{
5605 niu_set_primary_mac(np, np->dev->dev_addr);
5606
5607 if (np->flags & NIU_FLAGS_XMAC)
5608 niu_init_rx_xmac(np);
5609 else
5610 niu_init_rx_bmac(np);
5611}
5612
5613static void niu_enable_tx_xmac(struct niu *np, int on)
5614{
5615 u64 val = nr64_mac(XMAC_CONFIG);
5616
5617 if (on)
5618 val |= XMAC_CONFIG_TX_ENABLE;
5619 else
5620 val &= ~XMAC_CONFIG_TX_ENABLE;
5621 nw64_mac(XMAC_CONFIG, val);
5622}
5623
5624static void niu_enable_tx_bmac(struct niu *np, int on)
5625{
5626 u64 val = nr64_mac(BTXMAC_CONFIG);
5627
5628 if (on)
5629 val |= BTXMAC_CONFIG_ENABLE;
5630 else
5631 val &= ~BTXMAC_CONFIG_ENABLE;
5632 nw64_mac(BTXMAC_CONFIG, val);
5633}
5634
5635static void niu_enable_tx_mac(struct niu *np, int on)
5636{
5637 if (np->flags & NIU_FLAGS_XMAC)
5638 niu_enable_tx_xmac(np, on);
5639 else
5640 niu_enable_tx_bmac(np, on);
5641}
5642
5643static void niu_enable_rx_xmac(struct niu *np, int on)
5644{
5645 u64 val = nr64_mac(XMAC_CONFIG);
5646
5647 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5648 XMAC_CONFIG_PROMISCUOUS);
5649
5650 if (np->flags & NIU_FLAGS_MCAST)
5651 val |= XMAC_CONFIG_HASH_FILTER_EN;
5652 if (np->flags & NIU_FLAGS_PROMISC)
5653 val |= XMAC_CONFIG_PROMISCUOUS;
5654
5655 if (on)
5656 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5657 else
5658 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5659 nw64_mac(XMAC_CONFIG, val);
5660}
5661
5662static void niu_enable_rx_bmac(struct niu *np, int on)
5663{
5664 u64 val = nr64_mac(BRXMAC_CONFIG);
5665
5666 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5667 BRXMAC_CONFIG_PROMISC);
5668
5669 if (np->flags & NIU_FLAGS_MCAST)
5670 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5671 if (np->flags & NIU_FLAGS_PROMISC)
5672 val |= BRXMAC_CONFIG_PROMISC;
5673
5674 if (on)
5675 val |= BRXMAC_CONFIG_ENABLE;
5676 else
5677 val &= ~BRXMAC_CONFIG_ENABLE;
5678 nw64_mac(BRXMAC_CONFIG, val);
5679}
5680
5681static void niu_enable_rx_mac(struct niu *np, int on)
5682{
5683 if (np->flags & NIU_FLAGS_XMAC)
5684 niu_enable_rx_xmac(np, on);
5685 else
5686 niu_enable_rx_bmac(np, on);
5687}
5688
5689static int niu_init_mac(struct niu *np)
5690{
5691 int err;
5692
5693 niu_init_xif(np);
5694 err = niu_init_pcs(np);
5695 if (err)
5696 return err;
5697
5698 err = niu_reset_tx_mac(np);
5699 if (err)
5700 return err;
5701 niu_init_tx_mac(np);
5702 err = niu_reset_rx_mac(np);
5703 if (err)
5704 return err;
5705 niu_init_rx_mac(np);
5706
5707 /* This looks hookey but the RX MAC reset we just did will
5708 * undo some of the state we setup in niu_init_tx_mac() so we
5709 * have to call it again. In particular, the RX MAC reset will
5710 * set the XMAC_MAX register back to it's default value.
5711 */
5712 niu_init_tx_mac(np);
5713 niu_enable_tx_mac(np, 1);
5714
5715 niu_enable_rx_mac(np, 1);
5716
5717 return 0;
5718}
5719
5720static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5721{
5722 (void) niu_tx_channel_stop(np, rp->tx_channel);
5723}
5724
5725static void niu_stop_tx_channels(struct niu *np)
5726{
5727 int i;
5728
5729 for (i = 0; i < np->num_tx_rings; i++) {
5730 struct tx_ring_info *rp = &np->tx_rings[i];
5731
5732 niu_stop_one_tx_channel(np, rp);
5733 }
5734}
5735
5736static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5737{
5738 (void) niu_tx_channel_reset(np, rp->tx_channel);
5739}
5740
5741static void niu_reset_tx_channels(struct niu *np)
5742{
5743 int i;
5744
5745 for (i = 0; i < np->num_tx_rings; i++) {
5746 struct tx_ring_info *rp = &np->tx_rings[i];
5747
5748 niu_reset_one_tx_channel(np, rp);
5749 }
5750}
5751
5752static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5753{
5754 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5755}
5756
5757static void niu_stop_rx_channels(struct niu *np)
5758{
5759 int i;
5760
5761 for (i = 0; i < np->num_rx_rings; i++) {
5762 struct rx_ring_info *rp = &np->rx_rings[i];
5763
5764 niu_stop_one_rx_channel(np, rp);
5765 }
5766}
5767
5768static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5769{
5770 int channel = rp->rx_channel;
5771
5772 (void) niu_rx_channel_reset(np, channel);
5773 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5774 nw64(RX_DMA_CTL_STAT(channel), 0);
5775 (void) niu_enable_rx_channel(np, channel, 0);
5776}
5777
5778static void niu_reset_rx_channels(struct niu *np)
5779{
5780 int i;
5781
5782 for (i = 0; i < np->num_rx_rings; i++) {
5783 struct rx_ring_info *rp = &np->rx_rings[i];
5784
5785 niu_reset_one_rx_channel(np, rp);
5786 }
5787}
5788
5789static void niu_disable_ipp(struct niu *np)
5790{
5791 u64 rd, wr, val;
5792 int limit;
5793
5794 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5795 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5796 limit = 100;
5797 while (--limit >= 0 && (rd != wr)) {
5798 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5799 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5800 }
5801 if (limit < 0 &&
5802 (rd != 0 && wr != 1)) {
5803 dev_err(np->device, PFX "%s: IPP would not quiesce, "
5804 "rd_ptr[%llx] wr_ptr[%llx]\n",
5805 np->dev->name,
5806 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
5807 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
5808 }
5809
5810 val = nr64_ipp(IPP_CFIG);
5811 val &= ~(IPP_CFIG_IPP_ENABLE |
5812 IPP_CFIG_DFIFO_ECC_EN |
5813 IPP_CFIG_DROP_BAD_CRC |
5814 IPP_CFIG_CKSUM_EN);
5815 nw64_ipp(IPP_CFIG, val);
5816
5817 (void) niu_ipp_reset(np);
5818}
5819
5820static int niu_init_hw(struct niu *np)
5821{
5822 int i, err;
5823
5824 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
5825 niu_txc_enable_port(np, 1);
5826 niu_txc_port_dma_enable(np, 1);
5827 niu_txc_set_imask(np, 0);
5828
5829 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
5830 for (i = 0; i < np->num_tx_rings; i++) {
5831 struct tx_ring_info *rp = &np->tx_rings[i];
5832
5833 err = niu_init_one_tx_channel(np, rp);
5834 if (err)
5835 return err;
5836 }
5837
5838 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
5839 err = niu_init_rx_channels(np);
5840 if (err)
5841 goto out_uninit_tx_channels;
5842
5843 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
5844 err = niu_init_classifier_hw(np);
5845 if (err)
5846 goto out_uninit_rx_channels;
5847
5848 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
5849 err = niu_init_zcp(np);
5850 if (err)
5851 goto out_uninit_rx_channels;
5852
5853 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
5854 err = niu_init_ipp(np);
5855 if (err)
5856 goto out_uninit_rx_channels;
5857
5858 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
5859 err = niu_init_mac(np);
5860 if (err)
5861 goto out_uninit_ipp;
5862
5863 return 0;
5864
5865out_uninit_ipp:
5866 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
5867 niu_disable_ipp(np);
5868
5869out_uninit_rx_channels:
5870 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
5871 niu_stop_rx_channels(np);
5872 niu_reset_rx_channels(np);
5873
5874out_uninit_tx_channels:
5875 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
5876 niu_stop_tx_channels(np);
5877 niu_reset_tx_channels(np);
5878
5879 return err;
5880}
5881
5882static void niu_stop_hw(struct niu *np)
5883{
5884 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
5885 niu_enable_interrupts(np, 0);
5886
5887 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
5888 niu_enable_rx_mac(np, 0);
5889
5890 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
5891 niu_disable_ipp(np);
5892
5893 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
5894 niu_stop_tx_channels(np);
5895
5896 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
5897 niu_stop_rx_channels(np);
5898
5899 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
5900 niu_reset_tx_channels(np);
5901
5902 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
5903 niu_reset_rx_channels(np);
5904}
5905
70340d72
RO		 5906static void niu_set_irq_name(struct niu *np)
5907{
5908 int port = np->port;
5909 int i, j = 1;
5910
5911 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
5912
5913 if (port == 0) {
5914 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
5915 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
5916 j = 3;
5917 }
5918
5919 for (i = 0; i < np->num_ldg - j; i++) {
5920 if (i < np->num_rx_rings)
5921 sprintf(np->irq_name[i+j], "%s-rx-%d",
5922 np->dev->name, i);
5923 else if (i < np->num_tx_rings + np->num_rx_rings)
5924 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
5925 i - np->num_rx_rings);
5926 }
5927}
5928
a3138df9
DM		 5929static int niu_request_irq(struct niu *np)
5930{
5931 int i, j, err;
5932
70340d72
RO		 5933 niu_set_irq_name(np);
5934
a3138df9
DM		 5935 err = 0;
5936 for (i = 0; i < np->num_ldg; i++) {
5937 struct niu_ldg *lp = &np->ldg[i];
5938
5939 err = request_irq(lp->irq, niu_interrupt,
5940 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 5941 np->irq_name[i], lp);
a3138df9
DM		 5942 if (err)
5943 goto out_free_irqs;
5944
5945 }
5946
5947 return 0;
5948
5949out_free_irqs:
5950 for (j = 0; j < i; j++) {
5951 struct niu_ldg *lp = &np->ldg[j];
5952
5953 free_irq(lp->irq, lp);
5954 }
5955 return err;
5956}
5957
5958static void niu_free_irq(struct niu *np)
5959{
5960 int i;
5961
5962 for (i = 0; i < np->num_ldg; i++) {
5963 struct niu_ldg *lp = &np->ldg[i];
5964
5965 free_irq(lp->irq, lp);
5966 }
5967}
5968
5969static void niu_enable_napi(struct niu *np)
5970{
5971 int i;
5972
5973 for (i = 0; i < np->num_ldg; i++)
5974 napi_enable(&np->ldg[i].napi);
5975}
5976
5977static void niu_disable_napi(struct niu *np)
5978{
5979 int i;
5980
5981 for (i = 0; i < np->num_ldg; i++)
5982 napi_disable(&np->ldg[i].napi);
5983}
5984
5985static int niu_open(struct net_device *dev)
5986{
5987 struct niu *np = netdev_priv(dev);
5988 int err;
5989
5990 netif_carrier_off(dev);
5991
5992 err = niu_alloc_channels(np);
5993 if (err)
5994 goto out_err;
5995
5996 err = niu_enable_interrupts(np, 0);
5997 if (err)
5998 goto out_free_channels;
5999
6000 err = niu_request_irq(np);
6001 if (err)
6002 goto out_free_channels;
6003
6004 niu_enable_napi(np);
6005
6006 spin_lock_irq(&np->lock);
6007
6008 err = niu_init_hw(np);
6009 if (!err) {
6010 init_timer(&np->timer);
6011 np->timer.expires = jiffies + HZ;
6012 np->timer.data = (unsigned long) np;
6013 np->timer.function = niu_timer;
6014
6015 err = niu_enable_interrupts(np, 1);
6016 if (err)
6017 niu_stop_hw(np);
6018 }
6019
6020 spin_unlock_irq(&np->lock);
6021
6022 if (err) {
6023 niu_disable_napi(np);
6024 goto out_free_irq;
6025 }
6026
b4c21639 6027 netif_tx_start_all_queues(dev);
a3138df9
DM		 6028
6029 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6030 netif_carrier_on(dev);
6031
6032 add_timer(&np->timer);
6033
6034 return 0;
6035
6036out_free_irq:
6037 niu_free_irq(np);
6038
6039out_free_channels:
6040 niu_free_channels(np);
6041
6042out_err:
6043 return err;
6044}
6045
6046static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6047{
6048 cancel_work_sync(&np->reset_task);
6049
6050 niu_disable_napi(np);
b4c21639 6051 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6052
6053 del_timer_sync(&np->timer);
6054
6055 spin_lock_irq(&np->lock);
6056
6057 niu_stop_hw(np);
6058
6059 spin_unlock_irq(&np->lock);
6060}
6061
6062static int niu_close(struct net_device *dev)
6063{
6064 struct niu *np = netdev_priv(dev);
6065
6066 niu_full_shutdown(np, dev);
6067
6068 niu_free_irq(np);
6069
6070 niu_free_channels(np);
6071
0c3b091b
ML		 6072 niu_handle_led(np, 0);
6073
a3138df9
DM		 6074 return 0;
6075}
6076
6077static void niu_sync_xmac_stats(struct niu *np)
6078{
6079 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6080
6081 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6082 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6083
6084 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6085 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6086 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6087 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6088 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6089 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6090 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6091 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6092 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6093 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6094 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6095 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6096 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6097 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6098 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6099 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6100}
6101
6102static void niu_sync_bmac_stats(struct niu *np)
6103{
6104 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6105
6106 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6107 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6108
6109 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6110 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6111 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6112 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6113}
6114
6115static void niu_sync_mac_stats(struct niu *np)
6116{
6117 if (np->flags & NIU_FLAGS_XMAC)
6118 niu_sync_xmac_stats(np);
6119 else
6120 niu_sync_bmac_stats(np);
6121}
6122
6123static void niu_get_rx_stats(struct niu *np)
6124{
6125 unsigned long pkts, dropped, errors, bytes;
6126 int i;
6127
6128 pkts = dropped = errors = bytes = 0;
6129 for (i = 0; i < np->num_rx_rings; i++) {
6130 struct rx_ring_info *rp = &np->rx_rings[i];
6131
b8a606b8
JDB		 6132 niu_sync_rx_discard_stats(np, rp, 0);
6133
a3138df9
DM		 6134 pkts += rp->rx_packets;
6135 bytes += rp->rx_bytes;
6136 dropped += rp->rx_dropped;
6137 errors += rp->rx_errors;
6138 }
9fd42876
IJ		 6139 np->dev->stats.rx_packets = pkts;
6140 np->dev->stats.rx_bytes = bytes;
6141 np->dev->stats.rx_dropped = dropped;
6142 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6143}
6144
6145static void niu_get_tx_stats(struct niu *np)
6146{
6147 unsigned long pkts, errors, bytes;
6148 int i;
6149
6150 pkts = errors = bytes = 0;
6151 for (i = 0; i < np->num_tx_rings; i++) {
6152 struct tx_ring_info *rp = &np->tx_rings[i];
6153
6154 pkts += rp->tx_packets;
6155 bytes += rp->tx_bytes;
6156 errors += rp->tx_errors;
6157 }
9fd42876
IJ		 6158 np->dev->stats.tx_packets = pkts;
6159 np->dev->stats.tx_bytes = bytes;
6160 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6161}
6162
6163static struct net_device_stats *niu_get_stats(struct net_device *dev)
6164{
6165 struct niu *np = netdev_priv(dev);
6166
6167 niu_get_rx_stats(np);
6168 niu_get_tx_stats(np);
6169
9fd42876 6170 return &dev->stats;
a3138df9
DM		 6171}
6172
6173static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6174{
6175 int i;
6176
6177 for (i = 0; i < 16; i++)
6178 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6179}
6180
6181static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6182{
6183 int i;
6184
6185 for (i = 0; i < 16; i++)
6186 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6187}
6188
6189static void niu_load_hash(struct niu *np, u16 *hash)
6190{
6191 if (np->flags & NIU_FLAGS_XMAC)
6192 niu_load_hash_xmac(np, hash);
6193 else
6194 niu_load_hash_bmac(np, hash);
6195}
6196
6197static void niu_set_rx_mode(struct net_device *dev)
6198{
6199 struct niu *np = netdev_priv(dev);
6200 int i, alt_cnt, err;
6201 struct dev_addr_list *addr;
6202 unsigned long flags;
6203 u16 hash[16] = { 0, };
6204
6205 spin_lock_irqsave(&np->lock, flags);
6206 niu_enable_rx_mac(np, 0);
6207
6208 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6209 if (dev->flags & IFF_PROMISC)
6210 np->flags |= NIU_FLAGS_PROMISC;
6211 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
6212 np->flags |= NIU_FLAGS_MCAST;
6213
6214 alt_cnt = dev->uc_count;
6215 if (alt_cnt > niu_num_alt_addr(np)) {
6216 alt_cnt = 0;
6217 np->flags |= NIU_FLAGS_PROMISC;
6218 }
6219
6220 if (alt_cnt) {
6221 int index = 0;
6222
6223 for (addr = dev->uc_list; addr; addr = addr->next) {
6224 err = niu_set_alt_mac(np, index,
6225 addr->da_addr);
6226 if (err)
6227 printk(KERN_WARNING PFX "%s: Error %d "
6228 "adding alt mac %d\n",
6229 dev->name, err, index);
6230 err = niu_enable_alt_mac(np, index, 1);
6231 if (err)
6232 printk(KERN_WARNING PFX "%s: Error %d "
6233 "enabling alt mac %d\n",
6234 dev->name, err, index);
6235
6236 index++;
6237 }
6238 } else {
3b5bcede
MW		 6239 int alt_start;
6240 if (np->flags & NIU_FLAGS_XMAC)
6241 alt_start = 0;
6242 else
6243 alt_start = 1;
6244 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6245 err = niu_enable_alt_mac(np, i, 0);
6246 if (err)
6247 printk(KERN_WARNING PFX "%s: Error %d "
6248 "disabling alt mac %d\n",
6249 dev->name, err, i);
6250 }
6251 }
6252 if (dev->flags & IFF_ALLMULTI) {
6253 for (i = 0; i < 16; i++)
6254 hash[i] = 0xffff;
6255 } else if (dev->mc_count > 0) {
6256 for (addr = dev->mc_list; addr; addr = addr->next) {
6257 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
6258
6259 crc >>= 24;
6260 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6261 }
6262 }
6263
6264 if (np->flags & NIU_FLAGS_MCAST)
6265 niu_load_hash(np, hash);
6266
6267 niu_enable_rx_mac(np, 1);
6268 spin_unlock_irqrestore(&np->lock, flags);
6269}
6270
6271static int niu_set_mac_addr(struct net_device *dev, void *p)
6272{
6273 struct niu *np = netdev_priv(dev);
6274 struct sockaddr *addr = p;
6275 unsigned long flags;
6276
6277 if (!is_valid_ether_addr(addr->sa_data))
6278 return -EINVAL;
6279
6280 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6281
6282 if (!netif_running(dev))
6283 return 0;
6284
6285 spin_lock_irqsave(&np->lock, flags);
6286 niu_enable_rx_mac(np, 0);
6287 niu_set_primary_mac(np, dev->dev_addr);
6288 niu_enable_rx_mac(np, 1);
6289 spin_unlock_irqrestore(&np->lock, flags);
6290
6291 return 0;
6292}
6293
6294static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6295{
6296 return -EOPNOTSUPP;
6297}
6298
6299static void niu_netif_stop(struct niu *np)
6300{
6301 np->dev->trans_start = jiffies; /* prevent tx timeout */
6302
6303 niu_disable_napi(np);
6304
6305 netif_tx_disable(np->dev);
6306}
6307
6308static void niu_netif_start(struct niu *np)
6309{
6310 /* NOTE: unconditional netif_wake_queue is only appropriate
6311 * so long as all callers are assured to have free tx slots
6312 * (such as after niu_init_hw).
6313 */
b4c21639 6314 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6315
6316 niu_enable_napi(np);
6317
6318 niu_enable_interrupts(np, 1);
6319}
6320
cff502a3
SB		 6321static void niu_reset_buffers(struct niu *np)
6322{
6323 int i, j, k, err;
6324
6325 if (np->rx_rings) {
6326 for (i = 0; i < np->num_rx_rings; i++) {
6327 struct rx_ring_info *rp = &np->rx_rings[i];
6328
6329 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6330 struct page *page;
6331
6332 page = rp->rxhash[j];
6333 while (page) {
6334 struct page *next =
6335 (struct page *) page->mapping;
6336 u64 base = page->index;
6337 base = base >> RBR_DESCR_ADDR_SHIFT;
6338 rp->rbr[k++] = cpu_to_le32(base);
6339 page = next;
6340 }
6341 }
6342 for (; k < MAX_RBR_RING_SIZE; k++) {
6343 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6344 if (unlikely(err))
6345 break;
6346 }
6347
6348 rp->rbr_index = rp->rbr_table_size - 1;
6349 rp->rcr_index = 0;
6350 rp->rbr_pending = 0;
6351 rp->rbr_refill_pending = 0;
6352 }
6353 }
6354 if (np->tx_rings) {
6355 for (i = 0; i < np->num_tx_rings; i++) {
6356 struct tx_ring_info *rp = &np->tx_rings[i];
6357
6358 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6359 if (rp->tx_buffs[j].skb)
6360 (void) release_tx_packet(np, rp, j);
6361 }
6362
6363 rp->pending = MAX_TX_RING_SIZE;
6364 rp->prod = 0;
6365 rp->cons = 0;
6366 rp->wrap_bit = 0;
6367 }
6368 }
6369}
6370
a3138df9
DM		 6371static void niu_reset_task(struct work_struct *work)
6372{
6373 struct niu *np = container_of(work, struct niu, reset_task);
6374 unsigned long flags;
6375 int err;
6376
6377 spin_lock_irqsave(&np->lock, flags);
6378 if (!netif_running(np->dev)) {
6379 spin_unlock_irqrestore(&np->lock, flags);
6380 return;
6381 }
6382
6383 spin_unlock_irqrestore(&np->lock, flags);
6384
6385 del_timer_sync(&np->timer);
6386
6387 niu_netif_stop(np);
6388
6389 spin_lock_irqsave(&np->lock, flags);
6390
6391 niu_stop_hw(np);
6392
cff502a3
SB		 6393 spin_unlock_irqrestore(&np->lock, flags);
6394
6395 niu_reset_buffers(np);
6396
6397 spin_lock_irqsave(&np->lock, flags);
6398
a3138df9
DM		 6399 err = niu_init_hw(np);
6400 if (!err) {
6401 np->timer.expires = jiffies + HZ;
6402 add_timer(&np->timer);
6403 niu_netif_start(np);
6404 }
6405
6406 spin_unlock_irqrestore(&np->lock, flags);
6407}
6408
6409static void niu_tx_timeout(struct net_device *dev)
6410{
6411 struct niu *np = netdev_priv(dev);
6412
6413 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
6414 dev->name);
6415
6416 schedule_work(&np->reset_task);
6417}
6418
6419static void niu_set_txd(struct tx_ring_info *rp, int index,
6420 u64 mapping, u64 len, u64 mark,
6421 u64 n_frags)
6422{
6423 __le64 *desc = &rp->descr[index];
6424
6425 *desc = cpu_to_le64(mark |
6426 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6427 (len << TX_DESC_TR_LEN_SHIFT) |
6428 (mapping & TX_DESC_SAD));
6429}
6430
6431static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6432 u64 pad_bytes, u64 len)
6433{
6434 u16 eth_proto, eth_proto_inner;
6435 u64 csum_bits, l3off, ihl, ret;
6436 u8 ip_proto;
6437 int ipv6;
6438
6439 eth_proto = be16_to_cpu(ehdr->h_proto);
6440 eth_proto_inner = eth_proto;
6441 if (eth_proto == ETH_P_8021Q) {
6442 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6443 __be16 val = vp->h_vlan_encapsulated_proto;
6444
6445 eth_proto_inner = be16_to_cpu(val);
6446 }
6447
6448 ipv6 = ihl = 0;
6449 switch (skb->protocol) {
09640e63 6450 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6451 ip_proto = ip_hdr(skb)->protocol;
6452 ihl = ip_hdr(skb)->ihl;
6453 break;
09640e63 6454 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6455 ip_proto = ipv6_hdr(skb)->nexthdr;
6456 ihl = (40 >> 2);
6457 ipv6 = 1;
6458 break;
6459 default:
6460 ip_proto = ihl = 0;
6461 break;
6462 }
6463
6464 csum_bits = TXHDR_CSUM_NONE;
6465 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6466 u64 start, stuff;
6467
6468 csum_bits = (ip_proto == IPPROTO_TCP ?
6469 TXHDR_CSUM_TCP :
6470 (ip_proto == IPPROTO_UDP ?
6471 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6472
6473 start = skb_transport_offset(skb) -
6474 (pad_bytes + sizeof(struct tx_pkt_hdr));
6475 stuff = start + skb->csum_offset;
6476
6477 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6478 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6479 }
6480
6481 l3off = skb_network_offset(skb) -
6482 (pad_bytes + sizeof(struct tx_pkt_hdr));
6483
6484 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6485 (len << TXHDR_LEN_SHIFT) |
6486 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6487 (ihl << TXHDR_IHL_SHIFT) |
6488 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6489 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6490 (ipv6 ? TXHDR_IP_VER : 0) |
6491 csum_bits);
6492
6493 return ret;
6494}
6495
a3138df9
DM		 6496static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
6497{
6498 struct niu *np = netdev_priv(dev);
6499 unsigned long align, headroom;
b4c21639 6500 struct netdev_queue *txq;
a3138df9
DM		 6501 struct tx_ring_info *rp;
6502 struct tx_pkt_hdr *tp;
6503 unsigned int len, nfg;
6504 struct ethhdr *ehdr;
6505 int prod, i, tlen;
6506 u64 mapping, mrk;
6507
b4c21639
DM		 6508 i = skb_get_queue_mapping(skb);
6509 rp = &np->tx_rings[i];
6510 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6511
6512 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6513 netif_tx_stop_queue(txq);
a3138df9
DM		 6514 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
6515 "queue awake!\n", dev->name);
6516 rp->tx_errors++;
6517 return NETDEV_TX_BUSY;
6518 }
6519
6520 if (skb->len < ETH_ZLEN) {
6521 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6522
6523 if (skb_pad(skb, pad_bytes))
6524 goto out;
6525 skb_put(skb, pad_bytes);
6526 }
6527
6528 len = sizeof(struct tx_pkt_hdr) + 15;
6529 if (skb_headroom(skb) < len) {
6530 struct sk_buff *skb_new;
6531
6532 skb_new = skb_realloc_headroom(skb, len);
6533 if (!skb_new) {
6534 rp->tx_errors++;
6535 goto out_drop;
6536 }
6537 kfree_skb(skb);
6538 skb = skb_new;
3ebebccf
DM		 6539 } else
6540 skb_orphan(skb);
a3138df9
DM		 6541
6542 align = ((unsigned long) skb->data & (16 - 1));
6543 headroom = align + sizeof(struct tx_pkt_hdr);
6544
6545 ehdr = (struct ethhdr *) skb->data;
6546 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6547
6548 len = skb->len - sizeof(struct tx_pkt_hdr);
6549 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6550 tp->resv = 0;
6551
6552 len = skb_headlen(skb);
6553 mapping = np->ops->map_single(np->device, skb->data,
6554 len, DMA_TO_DEVICE);
6555
6556 prod = rp->prod;
6557
6558 rp->tx_buffs[prod].skb = skb;
6559 rp->tx_buffs[prod].mapping = mapping;
6560
6561 mrk = TX_DESC_SOP;
6562 if (++rp->mark_counter == rp->mark_freq) {
6563 rp->mark_counter = 0;
6564 mrk |= TX_DESC_MARK;
6565 rp->mark_pending++;
6566 }
6567
6568 tlen = len;
6569 nfg = skb_shinfo(skb)->nr_frags;
6570 while (tlen > 0) {
6571 tlen -= MAX_TX_DESC_LEN;
6572 nfg++;
6573 }
6574
6575 while (len > 0) {
6576 unsigned int this_len = len;
6577
6578 if (this_len > MAX_TX_DESC_LEN)
6579 this_len = MAX_TX_DESC_LEN;
6580
6581 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6582 mrk = nfg = 0;
6583
6584 prod = NEXT_TX(rp, prod);
6585 mapping += this_len;
6586 len -= this_len;
6587 }
6588
6589 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6590 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6591
6592 len = frag->size;
6593 mapping = np->ops->map_page(np->device, frag->page,
6594 frag->page_offset, len,
6595 DMA_TO_DEVICE);
6596
6597 rp->tx_buffs[prod].skb = NULL;
6598 rp->tx_buffs[prod].mapping = mapping;
6599
6600 niu_set_txd(rp, prod, mapping, len, 0, 0);
6601
6602 prod = NEXT_TX(rp, prod);
6603 }
6604
6605 if (prod < rp->prod)
6606 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6607 rp->prod = prod;
6608
6609 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6610
6611 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6612 netif_tx_stop_queue(txq);
a3138df9 6613 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6614 netif_tx_wake_queue(txq);
a3138df9
DM		 6615 }
6616
6617 dev->trans_start = jiffies;
6618
6619out:
6620 return NETDEV_TX_OK;
6621
6622out_drop:
6623 rp->tx_errors++;
6624 kfree_skb(skb);
6625 goto out;
6626}
6627
6628static int niu_change_mtu(struct net_device *dev, int new_mtu)
6629{
6630 struct niu *np = netdev_priv(dev);
6631 int err, orig_jumbo, new_jumbo;
6632
6633 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6634 return -EINVAL;
6635
6636 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6637 new_jumbo = (new_mtu > ETH_DATA_LEN);
6638
6639 dev->mtu = new_mtu;
6640
6641 if (!netif_running(dev) ||
6642 (orig_jumbo == new_jumbo))
6643 return 0;
6644
6645 niu_full_shutdown(np, dev);
6646
6647 niu_free_channels(np);
6648
6649 niu_enable_napi(np);
6650
6651 err = niu_alloc_channels(np);
6652 if (err)
6653 return err;
6654
6655 spin_lock_irq(&np->lock);
6656
6657 err = niu_init_hw(np);
6658 if (!err) {
6659 init_timer(&np->timer);
6660 np->timer.expires = jiffies + HZ;
6661 np->timer.data = (unsigned long) np;
6662 np->timer.function = niu_timer;
6663
6664 err = niu_enable_interrupts(np, 1);
6665 if (err)
6666 niu_stop_hw(np);
6667 }
6668
6669 spin_unlock_irq(&np->lock);
6670
6671 if (!err) {
b4c21639 6672 netif_tx_start_all_queues(dev);
a3138df9
DM		 6673 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6674 netif_carrier_on(dev);
6675
6676 add_timer(&np->timer);
6677 }
6678
6679 return err;
6680}
6681
6682static void niu_get_drvinfo(struct net_device *dev,
6683 struct ethtool_drvinfo *info)
6684{
6685 struct niu *np = netdev_priv(dev);
6686 struct niu_vpd *vpd = &np->vpd;
6687
6688 strcpy(info->driver, DRV_MODULE_NAME);
6689 strcpy(info->version, DRV_MODULE_VERSION);
6690 sprintf(info->fw_version, "%d.%d",
6691 vpd->fcode_major, vpd->fcode_minor);
6692 if (np->parent->plat_type != PLAT_TYPE_NIU)
6693 strcpy(info->bus_info, pci_name(np->pdev));
6694}
6695
6696static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6697{
6698 struct niu *np = netdev_priv(dev);
6699 struct niu_link_config *lp;
6700
6701 lp = &np->link_config;
6702
6703 memset(cmd, 0, sizeof(*cmd));
6704 cmd->phy_address = np->phy_addr;
6705 cmd->supported = lp->supported;
6706 cmd->advertising = lp->advertising;
6707 cmd->autoneg = lp->autoneg;
6708 cmd->speed = lp->active_speed;
6709 cmd->duplex = lp->active_duplex;
6710
6711 return 0;
6712}
6713
6714static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6715{
6716 return -EINVAL;
6717}
6718
6719static u32 niu_get_msglevel(struct net_device *dev)
6720{
6721 struct niu *np = netdev_priv(dev);
6722 return np->msg_enable;
6723}
6724
6725static void niu_set_msglevel(struct net_device *dev, u32 value)
6726{
6727 struct niu *np = netdev_priv(dev);
6728 np->msg_enable = value;
6729}
6730
6731static int niu_get_eeprom_len(struct net_device *dev)
6732{
6733 struct niu *np = netdev_priv(dev);
6734
6735 return np->eeprom_len;
6736}
6737
6738static int niu_get_eeprom(struct net_device *dev,
6739 struct ethtool_eeprom *eeprom, u8 *data)
6740{
6741 struct niu *np = netdev_priv(dev);
6742 u32 offset, len, val;
6743
6744 offset = eeprom->offset;
6745 len = eeprom->len;
6746
6747 if (offset + len < offset)
6748 return -EINVAL;
6749 if (offset >= np->eeprom_len)
6750 return -EINVAL;
6751 if (offset + len > np->eeprom_len)
6752 len = eeprom->len = np->eeprom_len - offset;
6753
6754 if (offset & 3) {
6755 u32 b_offset, b_count;
6756
6757 b_offset = offset & 3;
6758 b_count = 4 - b_offset;
6759 if (b_count > len)
6760 b_count = len;
6761
6762 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6763 memcpy(data, ((char *)&val) + b_offset, b_count);
6764 data += b_count;
6765 len -= b_count;
6766 offset += b_count;
6767 }
6768 while (len >= 4) {
6769 val = nr64(ESPC_NCR(offset / 4));
6770 memcpy(data, &val, 4);
6771 data += 4;
6772 len -= 4;
6773 offset += 4;
6774 }
6775 if (len) {
6776 val = nr64(ESPC_NCR(offset / 4));
6777 memcpy(data, &val, len);
6778 }
6779 return 0;
6780}
6781
b4653e99
SB		 6782static int niu_ethflow_to_class(int flow_type, u64 *class)
6783{
6784 switch (flow_type) {
6785 case TCP_V4_FLOW:
6786 *class = CLASS_CODE_TCP_IPV4;
6787 break;
6788 case UDP_V4_FLOW:
6789 *class = CLASS_CODE_UDP_IPV4;
6790 break;
6791 case AH_ESP_V4_FLOW:
6792 *class = CLASS_CODE_AH_ESP_IPV4;
6793 break;
6794 case SCTP_V4_FLOW:
6795 *class = CLASS_CODE_SCTP_IPV4;
6796 break;
6797 case TCP_V6_FLOW:
6798 *class = CLASS_CODE_TCP_IPV6;
6799 break;
6800 case UDP_V6_FLOW:
6801 *class = CLASS_CODE_UDP_IPV6;
6802 break;
6803 case AH_ESP_V6_FLOW:
6804 *class = CLASS_CODE_AH_ESP_IPV6;
6805 break;
6806 case SCTP_V6_FLOW:
6807 *class = CLASS_CODE_SCTP_IPV6;
6808 break;
6809 default:
38c080ff 6810 return 0;
b4653e99
SB		 6811 }
6812
6813 return 1;
6814}
6815
6816static u64 niu_flowkey_to_ethflow(u64 flow_key)
6817{
6818 u64 ethflow = 0;
6819
6820 if (flow_key & FLOW_KEY_PORT)
6821 ethflow |= RXH_DEV_PORT;
6822 if (flow_key & FLOW_KEY_L2DA)
6823 ethflow |= RXH_L2DA;
6824 if (flow_key & FLOW_KEY_VLAN)
6825 ethflow |= RXH_VLAN;
6826 if (flow_key & FLOW_KEY_IPSA)
6827 ethflow |= RXH_IP_SRC;
6828 if (flow_key & FLOW_KEY_IPDA)
6829 ethflow |= RXH_IP_DST;
6830 if (flow_key & FLOW_KEY_PROTO)
6831 ethflow |= RXH_L3_PROTO;
6832 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
6833 ethflow |= RXH_L4_B_0_1;
6834 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
6835 ethflow |= RXH_L4_B_2_3;
6836
6837 return ethflow;
6838
6839}
6840
6841static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
6842{
6843 u64 key = 0;
6844
6845 if (ethflow & RXH_DEV_PORT)
6846 key |= FLOW_KEY_PORT;
6847 if (ethflow & RXH_L2DA)
6848 key |= FLOW_KEY_L2DA;
6849 if (ethflow & RXH_VLAN)
6850 key |= FLOW_KEY_VLAN;
6851 if (ethflow & RXH_IP_SRC)
6852 key |= FLOW_KEY_IPSA;
6853 if (ethflow & RXH_IP_DST)
6854 key |= FLOW_KEY_IPDA;
6855 if (ethflow & RXH_L3_PROTO)
6856 key |= FLOW_KEY_PROTO;
6857 if (ethflow & RXH_L4_B_0_1)
6858 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
6859 if (ethflow & RXH_L4_B_2_3)
6860 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
6861
6862 *flow_key = key;
6863
6864 return 1;
6865
6866}
6867
6868static int niu_get_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6869{
6870 struct niu *np = netdev_priv(dev);
6871 u64 class;
6872
6873 cmd->data = 0;
6874
6875 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6876 return -EINVAL;
6877
6878 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6879 TCAM_KEY_DISC)
6880 cmd->data = RXH_DISCARD;
6881 else
6882
6883 cmd->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
6884 CLASS_CODE_USER_PROG1]);
6885 return 0;
6886}
6887
6888static int niu_set_hash_opts(struct net_device *dev, struct ethtool_rxnfc *cmd)
6889{
6890 struct niu *np = netdev_priv(dev);
6891 u64 class;
6892 u64 flow_key = 0;
6893 unsigned long flags;
6894
6895 if (!niu_ethflow_to_class(cmd->flow_type, &class))
6896 return -EINVAL;
6897
6898 if (class < CLASS_CODE_USER_PROG1 ||
6899 class > CLASS_CODE_SCTP_IPV6)
6900 return -EINVAL;
6901
6902 if (cmd->data & RXH_DISCARD) {
6903 niu_lock_parent(np, flags);
6904 flow_key = np->parent->tcam_key[class -
6905 CLASS_CODE_USER_PROG1];
6906 flow_key |= TCAM_KEY_DISC;
6907 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6908 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6909 niu_unlock_parent(np, flags);
6910 return 0;
6911 } else {
6912 /* Discard was set before, but is not set now */
6913 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
6914 TCAM_KEY_DISC) {
6915 niu_lock_parent(np, flags);
6916 flow_key = np->parent->tcam_key[class -
6917 CLASS_CODE_USER_PROG1];
6918 flow_key &= ~TCAM_KEY_DISC;
6919 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
6920 flow_key);
6921 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
6922 flow_key;
6923 niu_unlock_parent(np, flags);
6924 }
6925 }
6926
6927 if (!niu_ethflow_to_flowkey(cmd->data, &flow_key))
6928 return -EINVAL;
6929
6930 niu_lock_parent(np, flags);
6931 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
6932 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
6933 niu_unlock_parent(np, flags);
6934
6935 return 0;
6936}
6937
a3138df9
DM		 6938static const struct {
6939 const char string[ETH_GSTRING_LEN];
6940} niu_xmac_stat_keys[] = {
6941 { "tx_frames" },
6942 { "tx_bytes" },
6943 { "tx_fifo_errors" },
6944 { "tx_overflow_errors" },
6945 { "tx_max_pkt_size_errors" },
6946 { "tx_underflow_errors" },
6947 { "rx_local_faults" },
6948 { "rx_remote_faults" },
6949 { "rx_link_faults" },
6950 { "rx_align_errors" },
6951 { "rx_frags" },
6952 { "rx_mcasts" },
6953 { "rx_bcasts" },
6954 { "rx_hist_cnt1" },
6955 { "rx_hist_cnt2" },
6956 { "rx_hist_cnt3" },
6957 { "rx_hist_cnt4" },
6958 { "rx_hist_cnt5" },
6959 { "rx_hist_cnt6" },
6960 { "rx_hist_cnt7" },
6961 { "rx_octets" },
6962 { "rx_code_violations" },
6963 { "rx_len_errors" },
6964 { "rx_crc_errors" },
6965 { "rx_underflows" },
6966 { "rx_overflows" },
6967 { "pause_off_state" },
6968 { "pause_on_state" },
6969 { "pause_received" },
6970};
6971
6972#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
6973
6974static const struct {
6975 const char string[ETH_GSTRING_LEN];
6976} niu_bmac_stat_keys[] = {
6977 { "tx_underflow_errors" },
6978 { "tx_max_pkt_size_errors" },
6979 { "tx_bytes" },
6980 { "tx_frames" },
6981 { "rx_overflows" },
6982 { "rx_frames" },
6983 { "rx_align_errors" },
6984 { "rx_crc_errors" },
6985 { "rx_len_errors" },
6986 { "pause_off_state" },
6987 { "pause_on_state" },
6988 { "pause_received" },
6989};
6990
6991#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
6992
6993static const struct {
6994 const char string[ETH_GSTRING_LEN];
6995} niu_rxchan_stat_keys[] = {
6996 { "rx_channel" },
6997 { "rx_packets" },
6998 { "rx_bytes" },
6999 { "rx_dropped" },
7000 { "rx_errors" },
7001};
7002
7003#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7004
7005static const struct {
7006 const char string[ETH_GSTRING_LEN];
7007} niu_txchan_stat_keys[] = {
7008 { "tx_channel" },
7009 { "tx_packets" },
7010 { "tx_bytes" },
7011 { "tx_errors" },
7012};
7013
7014#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7015
7016static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7017{
7018 struct niu *np = netdev_priv(dev);
7019 int i;
7020
7021 if (stringset != ETH_SS_STATS)
7022 return;
7023
7024 if (np->flags & NIU_FLAGS_XMAC) {
7025 memcpy(data, niu_xmac_stat_keys,
7026 sizeof(niu_xmac_stat_keys));
7027 data += sizeof(niu_xmac_stat_keys);
7028 } else {
7029 memcpy(data, niu_bmac_stat_keys,
7030 sizeof(niu_bmac_stat_keys));
7031 data += sizeof(niu_bmac_stat_keys);
7032 }
7033 for (i = 0; i < np->num_rx_rings; i++) {
7034 memcpy(data, niu_rxchan_stat_keys,
7035 sizeof(niu_rxchan_stat_keys));
7036 data += sizeof(niu_rxchan_stat_keys);
7037 }
7038 for (i = 0; i < np->num_tx_rings; i++) {
7039 memcpy(data, niu_txchan_stat_keys,
7040 sizeof(niu_txchan_stat_keys));
7041 data += sizeof(niu_txchan_stat_keys);
7042 }
7043}
7044
7045static int niu_get_stats_count(struct net_device *dev)
7046{
7047 struct niu *np = netdev_priv(dev);
7048
7049 return ((np->flags & NIU_FLAGS_XMAC ?
7050 NUM_XMAC_STAT_KEYS :
7051 NUM_BMAC_STAT_KEYS) +
7052 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
7053 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
7054}
7055
7056static void niu_get_ethtool_stats(struct net_device *dev,
7057 struct ethtool_stats *stats, u64 *data)
7058{
7059 struct niu *np = netdev_priv(dev);
7060 int i;
7061
7062 niu_sync_mac_stats(np);
7063 if (np->flags & NIU_FLAGS_XMAC) {
7064 memcpy(data, &np->mac_stats.xmac,
7065 sizeof(struct niu_xmac_stats));
7066 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7067 } else {
7068 memcpy(data, &np->mac_stats.bmac,
7069 sizeof(struct niu_bmac_stats));
7070 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7071 }
7072 for (i = 0; i < np->num_rx_rings; i++) {
7073 struct rx_ring_info *rp = &np->rx_rings[i];
7074
b8a606b8
JDB		 7075 niu_sync_rx_discard_stats(np, rp, 0);
7076
a3138df9
DM		 7077 data[0] = rp->rx_channel;
7078 data[1] = rp->rx_packets;
7079 data[2] = rp->rx_bytes;
7080 data[3] = rp->rx_dropped;
7081 data[4] = rp->rx_errors;
7082 data += 5;
7083 }
7084 for (i = 0; i < np->num_tx_rings; i++) {
7085 struct tx_ring_info *rp = &np->tx_rings[i];
7086
7087 data[0] = rp->tx_channel;
7088 data[1] = rp->tx_packets;
7089 data[2] = rp->tx_bytes;
7090 data[3] = rp->tx_errors;
7091 data += 4;
7092 }
7093}
7094
7095static u64 niu_led_state_save(struct niu *np)
7096{
7097 if (np->flags & NIU_FLAGS_XMAC)
7098 return nr64_mac(XMAC_CONFIG);
7099 else
7100 return nr64_mac(BMAC_XIF_CONFIG);
7101}
7102
7103static void niu_led_state_restore(struct niu *np, u64 val)
7104{
7105 if (np->flags & NIU_FLAGS_XMAC)
7106 nw64_mac(XMAC_CONFIG, val);
7107 else
7108 nw64_mac(BMAC_XIF_CONFIG, val);
7109}
7110
7111static void niu_force_led(struct niu *np, int on)
7112{
7113 u64 val, reg, bit;
7114
7115 if (np->flags & NIU_FLAGS_XMAC) {
7116 reg = XMAC_CONFIG;
7117 bit = XMAC_CONFIG_FORCE_LED_ON;
7118 } else {
7119 reg = BMAC_XIF_CONFIG;
7120 bit = BMAC_XIF_CONFIG_LINK_LED;
7121 }
7122
7123 val = nr64_mac(reg);
7124 if (on)
7125 val |= bit;
7126 else
7127 val &= ~bit;
7128 nw64_mac(reg, val);
7129}
7130
7131static int niu_phys_id(struct net_device *dev, u32 data)
7132{
7133 struct niu *np = netdev_priv(dev);
7134 u64 orig_led_state;
7135 int i;
7136
7137 if (!netif_running(dev))
7138 return -EAGAIN;
7139
7140 if (data == 0)
7141 data = 2;
7142
7143 orig_led_state = niu_led_state_save(np);
7144 for (i = 0; i < (data * 2); i++) {
7145 int on = ((i % 2) == 0);
7146
7147 niu_force_led(np, on);
7148
7149 if (msleep_interruptible(500))
7150 break;
7151 }
7152 niu_led_state_restore(np, orig_led_state);
7153
7154 return 0;
7155}
7156
7157static const struct ethtool_ops niu_ethtool_ops = {
7158 .get_drvinfo = niu_get_drvinfo,
7159 .get_link = ethtool_op_get_link,
7160 .get_msglevel = niu_get_msglevel,
7161 .set_msglevel = niu_set_msglevel,
7162 .get_eeprom_len = niu_get_eeprom_len,
7163 .get_eeprom = niu_get_eeprom,
7164 .get_settings = niu_get_settings,
7165 .set_settings = niu_set_settings,
7166 .get_strings = niu_get_strings,
7167 .get_stats_count = niu_get_stats_count,
7168 .get_ethtool_stats = niu_get_ethtool_stats,
7169 .phys_id = niu_phys_id,
b4653e99
SB		 7170 .get_rxhash = niu_get_hash_opts,
7171 .set_rxhash = niu_set_hash_opts,
a3138df9
DM		 7172};
7173
7174static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7175 int ldg, int ldn)
7176{
7177 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7178 return -EINVAL;
7179 if (ldn < 0 || ldn > LDN_MAX)
7180 return -EINVAL;
7181
7182 parent->ldg_map[ldn] = ldg;
7183
7184 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7185 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7186 * the firmware, and we're not supposed to change them.
7187 * Validate the mapping, because if it's wrong we probably
7188 * won't get any interrupts and that's painful to debug.
7189 */
7190 if (nr64(LDG_NUM(ldn)) != ldg) {
7191 dev_err(np->device, PFX "Port %u, mis-matched "
7192 "LDG assignment "
7193 "for ldn %d, should be %d is %llu\n",
7194 np->port, ldn, ldg,
7195 (unsigned long long) nr64(LDG_NUM(ldn)));
7196 return -EINVAL;
7197 }
7198 } else
7199 nw64(LDG_NUM(ldn), ldg);
7200
7201 return 0;
7202}
7203
7204static int niu_set_ldg_timer_res(struct niu *np, int res)
7205{
7206 if (res < 0 || res > LDG_TIMER_RES_VAL)
7207 return -EINVAL;
7208
7209
7210 nw64(LDG_TIMER_RES, res);
7211
7212 return 0;
7213}
7214
7215static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7216{
7217 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7218 (func < 0 || func > 3) ||
7219 (vector < 0 || vector > 0x1f))
7220 return -EINVAL;
7221
7222 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7223
7224 return 0;
7225}
7226
7227static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7228{
7229 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7230 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7231 int limit;
7232
7233 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7234 return -EINVAL;
7235
7236 frame = frame_base;
7237 nw64(ESPC_PIO_STAT, frame);
7238 limit = 64;
7239 do {
7240 udelay(5);
7241 frame = nr64(ESPC_PIO_STAT);
7242 if (frame & ESPC_PIO_STAT_READ_END)
7243 break;
7244 } while (limit--);
7245 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7246 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7247 (unsigned long long) frame);
7248 return -ENODEV;
7249 }
7250
7251 frame = frame_base;
7252 nw64(ESPC_PIO_STAT, frame);
7253 limit = 64;
7254 do {
7255 udelay(5);
7256 frame = nr64(ESPC_PIO_STAT);
7257 if (frame & ESPC_PIO_STAT_READ_END)
7258 break;
7259 } while (limit--);
7260 if (!(frame & ESPC_PIO_STAT_READ_END)) {
7261 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
7262 (unsigned long long) frame);
7263 return -ENODEV;
7264 }
7265
7266 frame = nr64(ESPC_PIO_STAT);
7267 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
7268}
7269
7270static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
7271{
7272 int err = niu_pci_eeprom_read(np, off);
7273 u16 val;
7274
7275 if (err < 0)
7276 return err;
7277 val = (err << 8);
7278 err = niu_pci_eeprom_read(np, off + 1);
7279 if (err < 0)
7280 return err;
7281 val |= (err & 0xff);
7282
7283 return val;
7284}
7285
7286static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
7287{
7288 int err = niu_pci_eeprom_read(np, off);
7289 u16 val;
7290
7291 if (err < 0)
7292 return err;
7293
7294 val = (err & 0xff);
7295 err = niu_pci_eeprom_read(np, off + 1);
7296 if (err < 0)
7297 return err;
7298
7299 val |= (err & 0xff) << 8;
7300
7301 return val;
7302}
7303
7304static int __devinit niu_pci_vpd_get_propname(struct niu *np,
7305 u32 off,
7306 char *namebuf,
7307 int namebuf_len)
7308{
7309 int i;
7310
7311 for (i = 0; i < namebuf_len; i++) {
7312 int err = niu_pci_eeprom_read(np, off + i);
7313 if (err < 0)
7314 return err;
7315 *namebuf++ = err;
7316 if (!err)
7317 break;
7318 }
7319 if (i >= namebuf_len)
7320 return -EINVAL;
7321
7322 return i + 1;
7323}
7324
7325static void __devinit niu_vpd_parse_version(struct niu *np)
7326{
7327 struct niu_vpd *vpd = &np->vpd;
7328 int len = strlen(vpd->version) + 1;
7329 const char *s = vpd->version;
7330 int i;
7331
7332 for (i = 0; i < len - 5; i++) {
7333 if (!strncmp(s + i, "FCode ", 5))
7334 break;
7335 }
7336 if (i >= len - 5)
7337 return;
7338
7339 s += i + 5;
7340 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
7341
7342 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
7343 vpd->fcode_major, vpd->fcode_minor);
7344 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
7345 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
7346 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
7347 np->flags |= NIU_FLAGS_VPD_VALID;
7348}
7349
7350/* ESPC_PIO_EN_ENABLE must be set */
7351static int __devinit niu_pci_vpd_scan_props(struct niu *np,
7352 u32 start, u32 end)
7353{
7354 unsigned int found_mask = 0;
7355#define FOUND_MASK_MODEL 0x00000001
7356#define FOUND_MASK_BMODEL 0x00000002
7357#define FOUND_MASK_VERS 0x00000004
7358#define FOUND_MASK_MAC 0x00000008
7359#define FOUND_MASK_NMAC 0x00000010
7360#define FOUND_MASK_PHY 0x00000020
7361#define FOUND_MASK_ALL 0x0000003f
7362
7363 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
7364 start, end);
7365 while (start < end) {
7366 int len, err, instance, type, prop_len;
7367 char namebuf[64];
7368 u8 *prop_buf;
7369 int max_len;
7370
7371 if (found_mask == FOUND_MASK_ALL) {
7372 niu_vpd_parse_version(np);
7373 return 1;
7374 }
7375
7376 err = niu_pci_eeprom_read(np, start + 2);
7377 if (err < 0)
7378 return err;
7379 len = err;
7380 start += 3;
7381
7382 instance = niu_pci_eeprom_read(np, start);
7383 type = niu_pci_eeprom_read(np, start + 3);
7384 prop_len = niu_pci_eeprom_read(np, start + 4);
7385 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
7386 if (err < 0)
7387 return err;
7388
7389 prop_buf = NULL;
7390 max_len = 0;
7391 if (!strcmp(namebuf, "model")) {
7392 prop_buf = np->vpd.model;
7393 max_len = NIU_VPD_MODEL_MAX;
7394 found_mask |= FOUND_MASK_MODEL;
7395 } else if (!strcmp(namebuf, "board-model")) {
7396 prop_buf = np->vpd.board_model;
7397 max_len = NIU_VPD_BD_MODEL_MAX;
7398 found_mask |= FOUND_MASK_BMODEL;
7399 } else if (!strcmp(namebuf, "version")) {
7400 prop_buf = np->vpd.version;
7401 max_len = NIU_VPD_VERSION_MAX;
7402 found_mask |= FOUND_MASK_VERS;
7403 } else if (!strcmp(namebuf, "local-mac-address")) {
7404 prop_buf = np->vpd.local_mac;
7405 max_len = ETH_ALEN;
7406 found_mask |= FOUND_MASK_MAC;
7407 } else if (!strcmp(namebuf, "num-mac-addresses")) {
7408 prop_buf = &np->vpd.mac_num;
7409 max_len = 1;
7410 found_mask |= FOUND_MASK_NMAC;
7411 } else if (!strcmp(namebuf, "phy-type")) {
7412 prop_buf = np->vpd.phy_type;
7413 max_len = NIU_VPD_PHY_TYPE_MAX;
7414 found_mask |= FOUND_MASK_PHY;
7415 }
7416
7417 if (max_len && prop_len > max_len) {
7418 dev_err(np->device, PFX "Property '%s' length (%d) is "
7419 "too long.\n", namebuf, prop_len);
7420 return -EINVAL;
7421 }
7422
7423 if (prop_buf) {
7424 u32 off = start + 5 + err;
7425 int i;
7426
7427 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
7428 "len[%d]\n", namebuf, prop_len);
7429 for (i = 0; i < prop_len; i++)
7430 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
7431 }
7432
7433 start += len;
7434 }
7435
7436 return 0;
7437}
7438
7439/* ESPC_PIO_EN_ENABLE must be set */
7440static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
7441{
7442 u32 offset;
7443 int err;
7444
7445 err = niu_pci_eeprom_read16_swp(np, start + 1);
7446 if (err < 0)
7447 return;
7448
7449 offset = err + 3;
7450
7451 while (start + offset < ESPC_EEPROM_SIZE) {
7452 u32 here = start + offset;
7453 u32 end;
7454
7455 err = niu_pci_eeprom_read(np, here);
7456 if (err != 0x90)
7457 return;
7458
7459 err = niu_pci_eeprom_read16_swp(np, here + 1);
7460 if (err < 0)
7461 return;
7462
7463 here = start + offset + 3;
7464 end = start + offset + err;
7465
7466 offset += err;
7467
7468 err = niu_pci_vpd_scan_props(np, here, end);
7469 if (err < 0 || err == 1)
7470 return;
7471 }
7472}
7473
7474/* ESPC_PIO_EN_ENABLE must be set */
7475static u32 __devinit niu_pci_vpd_offset(struct niu *np)
7476{
7477 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
7478 int err;
7479
7480 while (start < end) {
7481 ret = start;
7482
7483 /* ROM header signature? */
7484 err = niu_pci_eeprom_read16(np, start + 0);
7485 if (err != 0x55aa)
7486 return 0;
7487
7488 /* Apply offset to PCI data structure. */
7489 err = niu_pci_eeprom_read16(np, start + 23);
7490 if (err < 0)
7491 return 0;
7492 start += err;
7493
7494 /* Check for "PCIR" signature. */
7495 err = niu_pci_eeprom_read16(np, start + 0);
7496 if (err != 0x5043)
7497 return 0;
7498 err = niu_pci_eeprom_read16(np, start + 2);
7499 if (err != 0x4952)
7500 return 0;
7501
7502 /* Check for OBP image type. */
7503 err = niu_pci_eeprom_read(np, start + 20);
7504 if (err < 0)
7505 return 0;
7506 if (err != 0x01) {
7507 err = niu_pci_eeprom_read(np, ret + 2);
7508 if (err < 0)
7509 return 0;
7510
7511 start = ret + (err * 512);
7512 continue;
7513 }
7514
7515 err = niu_pci_eeprom_read16_swp(np, start + 8);
7516 if (err < 0)
7517 return err;
7518 ret += err;
7519
7520 err = niu_pci_eeprom_read(np, ret + 0);
7521 if (err != 0x82)
7522 return 0;
7523
7524 return ret;
7525 }
7526
7527 return 0;
7528}
7529
7530static int __devinit niu_phy_type_prop_decode(struct niu *np,
7531 const char *phy_prop)
7532{
7533 if (!strcmp(phy_prop, "mif")) {
7534 /* 1G copper, MII */
7535 np->flags &= ~(NIU_FLAGS_FIBER |
7536 NIU_FLAGS_10G);
7537 np->mac_xcvr = MAC_XCVR_MII;
7538 } else if (!strcmp(phy_prop, "xgf")) {
7539 /* 10G fiber, XPCS */
7540 np->flags |= (NIU_FLAGS_10G |
7541 NIU_FLAGS_FIBER);
7542 np->mac_xcvr = MAC_XCVR_XPCS;
7543 } else if (!strcmp(phy_prop, "pcs")) {
7544 /* 1G fiber, PCS */
7545 np->flags &= ~NIU_FLAGS_10G;
7546 np->flags |= NIU_FLAGS_FIBER;
7547 np->mac_xcvr = MAC_XCVR_PCS;
7548 } else if (!strcmp(phy_prop, "xgc")) {
7549 /* 10G copper, XPCS */
7550 np->flags |= NIU_FLAGS_10G;
7551 np->flags &= ~NIU_FLAGS_FIBER;
7552 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 7553 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
7554 /* 10G Serdes or 1G Serdes, default to 10G */
7555 np->flags |= NIU_FLAGS_10G;
7556 np->flags &= ~NIU_FLAGS_FIBER;
7557 np->flags |= NIU_FLAGS_XCVR_SERDES;
7558 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 7559 } else {
7560 return -EINVAL;
7561 }
7562 return 0;
7563}
7564
7f7c4072
MW		 7565static int niu_pci_vpd_get_nports(struct niu *np)
7566{
7567 int ports = 0;
7568
f9af8574
MW		 7569 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
7570 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
7571 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
7572 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
7573 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 7574 ports = 4;
f9af8574
MW		 7575 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
7576 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
7577 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
7578 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 7579 ports = 2;
7580 }
7581
7582 return ports;
7583}
7584
a3138df9
DM		 7585static void __devinit niu_pci_vpd_validate(struct niu *np)
7586{
7587 struct net_device *dev = np->dev;
7588 struct niu_vpd *vpd = &np->vpd;
7589 u8 val8;
7590
7591 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
7592 dev_err(np->device, PFX "VPD MAC invalid, "
7593 "falling back to SPROM.\n");
7594
7595 np->flags &= ~NIU_FLAGS_VPD_VALID;
7596 return;
7597 }
7598
f9af8574
MW		 7599 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
7600 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 7601 np->flags |= NIU_FLAGS_10G;
7602 np->flags &= ~NIU_FLAGS_FIBER;
7603 np->flags |= NIU_FLAGS_XCVR_SERDES;
7604 np->mac_xcvr = MAC_XCVR_PCS;
7605 if (np->port > 1) {
7606 np->flags |= NIU_FLAGS_FIBER;
7607 np->flags &= ~NIU_FLAGS_10G;
7608 }
7609 if (np->flags & NIU_FLAGS_10G)
7610 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 7611 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 7612 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
7613 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 7614 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
a3138df9
DM		 7615 dev_err(np->device, PFX "Illegal phy string [%s].\n",
7616 np->vpd.phy_type);
7617 dev_err(np->device, PFX "Falling back to SPROM.\n");
7618 np->flags &= ~NIU_FLAGS_VPD_VALID;
7619 return;
7620 }
7621
7622 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
7623
7624 val8 = dev->perm_addr[5];
7625 dev->perm_addr[5] += np->port;
7626 if (dev->perm_addr[5] < val8)
7627 dev->perm_addr[4]++;
7628
7629 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7630}
7631
7632static int __devinit niu_pci_probe_sprom(struct niu *np)
7633{
7634 struct net_device *dev = np->dev;
7635 int len, i;
7636 u64 val, sum;
7637 u8 val8;
7638
7639 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
7640 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
7641 len = val / 4;
7642
7643 np->eeprom_len = len;
7644
7645 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
7646
7647 sum = 0;
7648 for (i = 0; i < len; i++) {
7649 val = nr64(ESPC_NCR(i));
7650 sum += (val >> 0) & 0xff;
7651 sum += (val >> 8) & 0xff;
7652 sum += (val >> 16) & 0xff;
7653 sum += (val >> 24) & 0xff;
7654 }
7655 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
7656 if ((sum & 0xff) != 0xab) {
7657 dev_err(np->device, PFX "Bad SPROM checksum "
7658 "(%x, should be 0xab)\n", (int) (sum & 0xff));
7659 return -EINVAL;
7660 }
7661
7662 val = nr64(ESPC_PHY_TYPE);
7663 switch (np->port) {
7664 case 0:
a9d41192 7665 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 7666 ESPC_PHY_TYPE_PORT0_SHIFT;
7667 break;
7668 case 1:
a9d41192 7669 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 7670 ESPC_PHY_TYPE_PORT1_SHIFT;
7671 break;
7672 case 2:
a9d41192 7673 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 7674 ESPC_PHY_TYPE_PORT2_SHIFT;
7675 break;
7676 case 3:
a9d41192 7677 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 7678 ESPC_PHY_TYPE_PORT3_SHIFT;
7679 break;
7680 default:
7681 dev_err(np->device, PFX "Bogus port number %u\n",
7682 np->port);
7683 return -EINVAL;
7684 }
a9d41192 7685 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
a3138df9 7686
a9d41192 7687 switch (val8) {
a3138df9
DM		 7688 case ESPC_PHY_TYPE_1G_COPPER:
7689 /* 1G copper, MII */
7690 np->flags &= ~(NIU_FLAGS_FIBER |
7691 NIU_FLAGS_10G);
7692 np->mac_xcvr = MAC_XCVR_MII;
7693 break;
7694
7695 case ESPC_PHY_TYPE_1G_FIBER:
7696 /* 1G fiber, PCS */
7697 np->flags &= ~NIU_FLAGS_10G;
7698 np->flags |= NIU_FLAGS_FIBER;
7699 np->mac_xcvr = MAC_XCVR_PCS;
7700 break;
7701
7702 case ESPC_PHY_TYPE_10G_COPPER:
7703 /* 10G copper, XPCS */
7704 np->flags |= NIU_FLAGS_10G;
7705 np->flags &= ~NIU_FLAGS_FIBER;
7706 np->mac_xcvr = MAC_XCVR_XPCS;
7707 break;
7708
7709 case ESPC_PHY_TYPE_10G_FIBER:
7710 /* 10G fiber, XPCS */
7711 np->flags |= (NIU_FLAGS_10G |
7712 NIU_FLAGS_FIBER);
7713 np->mac_xcvr = MAC_XCVR_XPCS;
7714 break;
7715
7716 default:
a9d41192 7717 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 7718 return -EINVAL;
7719 }
7720
7721 val = nr64(ESPC_MAC_ADDR0);
7722 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
7723 (unsigned long long) val);
7724 dev->perm_addr[0] = (val >> 0) & 0xff;
7725 dev->perm_addr[1] = (val >> 8) & 0xff;
7726 dev->perm_addr[2] = (val >> 16) & 0xff;
7727 dev->perm_addr[3] = (val >> 24) & 0xff;
7728
7729 val = nr64(ESPC_MAC_ADDR1);
7730 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
7731 (unsigned long long) val);
7732 dev->perm_addr[4] = (val >> 0) & 0xff;
7733 dev->perm_addr[5] = (val >> 8) & 0xff;
7734
7735 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7736 dev_err(np->device, PFX "SPROM MAC address invalid\n");
7737 dev_err(np->device, PFX "[ \n");
7738 for (i = 0; i < 6; i++)
7739 printk("%02x ", dev->perm_addr[i]);
7740 printk("]\n");
7741 return -EINVAL;
7742 }
7743
7744 val8 = dev->perm_addr[5];
7745 dev->perm_addr[5] += np->port;
7746 if (dev->perm_addr[5] < val8)
7747 dev->perm_addr[4]++;
7748
7749 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7750
7751 val = nr64(ESPC_MOD_STR_LEN);
7752 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
7753 (unsigned long long) val);
e6a5fdf5 7754 if (val >= 8 * 4)
a3138df9
DM		 7755 return -EINVAL;
7756
7757 for (i = 0; i < val; i += 4) {
7758 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
7759
7760 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
7761 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
7762 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
7763 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
7764 }
7765 np->vpd.model[val] = '\0';
7766
7767 val = nr64(ESPC_BD_MOD_STR_LEN);
7768 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
7769 (unsigned long long) val);
e6a5fdf5 7770 if (val >= 4 * 4)
a3138df9
DM		 7771 return -EINVAL;
7772
7773 for (i = 0; i < val; i += 4) {
7774 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
7775
7776 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
7777 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
7778 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
7779 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
7780 }
7781 np->vpd.board_model[val] = '\0';
7782
7783 np->vpd.mac_num =
7784 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
7785 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
7786 np->vpd.mac_num);
7787
7788 return 0;
7789}
7790
7791static int __devinit niu_get_and_validate_port(struct niu *np)
7792{
7793 struct niu_parent *parent = np->parent;
7794
7795 if (np->port <= 1)
7796 np->flags |= NIU_FLAGS_XMAC;
7797
7798 if (!parent->num_ports) {
7799 if (parent->plat_type == PLAT_TYPE_NIU) {
7800 parent->num_ports = 2;
7801 } else {
7f7c4072
MW		 7802 parent->num_ports = niu_pci_vpd_get_nports(np);
7803 if (!parent->num_ports) {
7804 /* Fall back to SPROM as last resort.
7805 * This will fail on most cards.
7806 */
7807 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
7808 ESPC_NUM_PORTS_MACS_VAL;
7809
be0c007a
DM		 7810 /* All of the current probing methods fail on
7811 * Maramba on-board parts.
7812 */
7f7c4072 7813 if (!parent->num_ports)
be0c007a 7814 parent->num_ports = 4;
7f7c4072 7815 }
a3138df9
DM		 7816 }
7817 }
7818
7819 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
7820 np->port, parent->num_ports);
7821 if (np->port >= parent->num_ports)
7822 return -ENODEV;
7823
7824 return 0;
7825}
7826
7827static int __devinit phy_record(struct niu_parent *parent,
7828 struct phy_probe_info *p,
7829 int dev_id_1, int dev_id_2, u8 phy_port,
7830 int type)
7831{
7832 u32 id = (dev_id_1 << 16) | dev_id_2;
7833 u8 idx;
7834
7835 if (dev_id_1 < 0 || dev_id_2 < 0)
7836 return 0;
7837 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 7838 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 7839 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
7840 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 7841 return 0;
7842 } else {
7843 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
7844 return 0;
7845 }
7846
7847 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
7848 parent->index, id,
7849 (type == PHY_TYPE_PMA_PMD ?
7850 "PMA/PMD" :
7851 (type == PHY_TYPE_PCS ?
7852 "PCS" : "MII")),
7853 phy_port);
7854
7855 if (p->cur[type] >= NIU_MAX_PORTS) {
7856 printk(KERN_ERR PFX "Too many PHY ports.\n");
7857 return -EINVAL;
7858 }
7859 idx = p->cur[type];
7860 p->phy_id[type][idx] = id;
7861 p->phy_port[type][idx] = phy_port;
7862 p->cur[type] = idx + 1;
7863 return 0;
7864}
7865
7866static int __devinit port_has_10g(struct phy_probe_info *p, int port)
7867{
7868 int i;
7869
7870 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
7871 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
7872 return 1;
7873 }
7874 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
7875 if (p->phy_port[PHY_TYPE_PCS][i] == port)
7876 return 1;
7877 }
7878
7879 return 0;
7880}
7881
7882static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
7883{
7884 int port, cnt;
7885
7886 cnt = 0;
7887 *lowest = 32;
7888 for (port = 8; port < 32; port++) {
7889 if (port_has_10g(p, port)) {
7890 if (!cnt)
7891 *lowest = port;
7892 cnt++;
7893 }
7894 }
7895
7896 return cnt;
7897}
7898
7899static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
7900{
7901 *lowest = 32;
7902 if (p->cur[PHY_TYPE_MII])
7903 *lowest = p->phy_port[PHY_TYPE_MII][0];
7904
7905 return p->cur[PHY_TYPE_MII];
7906}
7907
7908static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
7909{
7910 int num_ports = parent->num_ports;
7911 int i;
7912
7913 for (i = 0; i < num_ports; i++) {
7914 parent->rxchan_per_port[i] = (16 / num_ports);
7915 parent->txchan_per_port[i] = (16 / num_ports);
7916
7917 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7918 "[%u TX chans]\n",
7919 parent->index, i,
7920 parent->rxchan_per_port[i],
7921 parent->txchan_per_port[i]);
7922 }
7923}
7924
7925static void __devinit niu_divide_channels(struct niu_parent *parent,
7926 int num_10g, int num_1g)
7927{
7928 int num_ports = parent->num_ports;
7929 int rx_chans_per_10g, rx_chans_per_1g;
7930 int tx_chans_per_10g, tx_chans_per_1g;
7931 int i, tot_rx, tot_tx;
7932
7933 if (!num_10g || !num_1g) {
7934 rx_chans_per_10g = rx_chans_per_1g =
7935 (NIU_NUM_RXCHAN / num_ports);
7936 tx_chans_per_10g = tx_chans_per_1g =
7937 (NIU_NUM_TXCHAN / num_ports);
7938 } else {
7939 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
7940 rx_chans_per_10g = (NIU_NUM_RXCHAN -
7941 (rx_chans_per_1g * num_1g)) /
7942 num_10g;
7943
7944 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
7945 tx_chans_per_10g = (NIU_NUM_TXCHAN -
7946 (tx_chans_per_1g * num_1g)) /
7947 num_10g;
7948 }
7949
7950 tot_rx = tot_tx = 0;
7951 for (i = 0; i < num_ports; i++) {
7952 int type = phy_decode(parent->port_phy, i);
7953
7954 if (type == PORT_TYPE_10G) {
7955 parent->rxchan_per_port[i] = rx_chans_per_10g;
7956 parent->txchan_per_port[i] = tx_chans_per_10g;
7957 } else {
7958 parent->rxchan_per_port[i] = rx_chans_per_1g;
7959 parent->txchan_per_port[i] = tx_chans_per_1g;
7960 }
7961 pr_info(PFX "niu%d: Port %u [%u RX chans] "
7962 "[%u TX chans]\n",
7963 parent->index, i,
7964 parent->rxchan_per_port[i],
7965 parent->txchan_per_port[i]);
7966 tot_rx += parent->rxchan_per_port[i];
7967 tot_tx += parent->txchan_per_port[i];
7968 }
7969
7970 if (tot_rx > NIU_NUM_RXCHAN) {
7971 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
7972 "resetting to one per port.\n",
7973 parent->index, tot_rx);
7974 for (i = 0; i < num_ports; i++)
7975 parent->rxchan_per_port[i] = 1;
7976 }
7977 if (tot_tx > NIU_NUM_TXCHAN) {
7978 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
7979 "resetting to one per port.\n",
7980 parent->index, tot_tx);
7981 for (i = 0; i < num_ports; i++)
7982 parent->txchan_per_port[i] = 1;
7983 }
7984 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
7985 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
7986 "RX[%d] TX[%d]\n",
7987 parent->index, tot_rx, tot_tx);
7988 }
7989}
7990
7991static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
7992 int num_10g, int num_1g)
7993{
7994 int i, num_ports = parent->num_ports;
7995 int rdc_group, rdc_groups_per_port;
7996 int rdc_channel_base;
7997
7998 rdc_group = 0;
7999 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8000
8001 rdc_channel_base = 0;
8002
8003 for (i = 0; i < num_ports; i++) {
8004 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8005 int grp, num_channels = parent->rxchan_per_port[i];
8006 int this_channel_offset;
8007
8008 tp->first_table_num = rdc_group;
8009 tp->num_tables = rdc_groups_per_port;
8010 this_channel_offset = 0;
8011 for (grp = 0; grp < tp->num_tables; grp++) {
8012 struct rdc_table *rt = &tp->tables[grp];
8013 int slot;
8014
8015 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
8016 parent->index, i, tp->first_table_num + grp);
8017 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8018 rt->rxdma_channel[slot] =
8019 rdc_channel_base + this_channel_offset;
8020
8021 printk("%d ", rt->rxdma_channel[slot]);
8022
8023 if (++this_channel_offset == num_channels)
8024 this_channel_offset = 0;
8025 }
8026 printk("]\n");
8027 }
8028
8029 parent->rdc_default[i] = rdc_channel_base;
8030
8031 rdc_channel_base += num_channels;
8032 rdc_group += rdc_groups_per_port;
8033 }
8034}
8035
8036static int __devinit fill_phy_probe_info(struct niu *np,
8037 struct niu_parent *parent,
8038 struct phy_probe_info *info)
8039{
8040 unsigned long flags;
8041 int port, err;
8042
8043 memset(info, 0, sizeof(*info));
8044
8045 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8046 niu_lock_parent(np, flags);
8047 err = 0;
8048 for (port = 8; port < 32; port++) {
8049 int dev_id_1, dev_id_2;
8050
8051 dev_id_1 = mdio_read(np, port,
8052 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8053 dev_id_2 = mdio_read(np, port,
8054 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8055 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8056 PHY_TYPE_PMA_PMD);
8057 if (err)
8058 break;
8059 dev_id_1 = mdio_read(np, port,
8060 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8061 dev_id_2 = mdio_read(np, port,
8062 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8063 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8064 PHY_TYPE_PCS);
8065 if (err)
8066 break;
8067 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8068 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8069 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8070 PHY_TYPE_MII);
8071 if (err)
8072 break;
8073 }
8074 niu_unlock_parent(np, flags);
8075
8076 return err;
8077}
8078
8079static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8080{
8081 struct phy_probe_info *info = &parent->phy_probe_info;
8082 int lowest_10g, lowest_1g;
8083 int num_10g, num_1g;
8084 u32 val;
8085 int err;
8086
e3e081e1
SB		 8087 num_10g = num_1g = 0;
8088
f9af8574
MW		 8089 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8090 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8091 num_10g = 0;
8092 num_1g = 2;
8093 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8094 parent->num_ports = 4;
8095 val = (phy_encode(PORT_TYPE_1G, 0) |
8096 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8097 phy_encode(PORT_TYPE_1G, 2) |
8098 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8099 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8100 num_10g = 2;
8101 num_1g = 0;
8102 parent->num_ports = 2;
8103 val = (phy_encode(PORT_TYPE_10G, 0) |
8104 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8105 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8106 (parent->plat_type == PLAT_TYPE_NIU)) {
8107 /* this is the Monza case */
8108 if (np->flags & NIU_FLAGS_10G) {
8109 val = (phy_encode(PORT_TYPE_10G, 0) |
8110 phy_encode(PORT_TYPE_10G, 1));
8111 } else {
8112 val = (phy_encode(PORT_TYPE_1G, 0) |
8113 phy_encode(PORT_TYPE_1G, 1));
8114 }
5fbd7e24
MW		 8115 } else {
8116 err = fill_phy_probe_info(np, parent, info);
8117 if (err)
8118 return err;
a3138df9 8119
5fbd7e24
MW		 8120 num_10g = count_10g_ports(info, &lowest_10g);
8121 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8122
5fbd7e24
MW		 8123 switch ((num_10g << 4) | num_1g) {
8124 case 0x24:
8125 if (lowest_1g == 10)
8126 parent->plat_type = PLAT_TYPE_VF_P0;
8127 else if (lowest_1g == 26)
8128 parent->plat_type = PLAT_TYPE_VF_P1;
8129 else
8130 goto unknown_vg_1g_port;
a3138df9 8131
5fbd7e24
MW		 8132 /* fallthru */
8133 case 0x22:
a3138df9 8134 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8135 phy_encode(PORT_TYPE_10G, 1) |
8136 phy_encode(PORT_TYPE_1G, 2) |
8137 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8138 break;
a3138df9 8139
5fbd7e24
MW		 8140 case 0x20:
8141 val = (phy_encode(PORT_TYPE_10G, 0) |
8142 phy_encode(PORT_TYPE_10G, 1));
8143 break;
a3138df9 8144
5fbd7e24
MW		 8145 case 0x10:
8146 val = phy_encode(PORT_TYPE_10G, np->port);
8147 break;
a3138df9 8148
5fbd7e24
MW		 8149 case 0x14:
8150 if (lowest_1g == 10)
8151 parent->plat_type = PLAT_TYPE_VF_P0;
8152 else if (lowest_1g == 26)
8153 parent->plat_type = PLAT_TYPE_VF_P1;
8154 else
8155 goto unknown_vg_1g_port;
8156
8157 /* fallthru */
8158 case 0x13:
8159 if ((lowest_10g & 0x7) == 0)
8160 val = (phy_encode(PORT_TYPE_10G, 0) |
8161 phy_encode(PORT_TYPE_1G, 1) |
8162 phy_encode(PORT_TYPE_1G, 2) |
8163 phy_encode(PORT_TYPE_1G, 3));
8164 else
8165 val = (phy_encode(PORT_TYPE_1G, 0) |
8166 phy_encode(PORT_TYPE_10G, 1) |
8167 phy_encode(PORT_TYPE_1G, 2) |
8168 phy_encode(PORT_TYPE_1G, 3));
8169 break;
8170
8171 case 0x04:
8172 if (lowest_1g == 10)
8173 parent->plat_type = PLAT_TYPE_VF_P0;
8174 else if (lowest_1g == 26)
8175 parent->plat_type = PLAT_TYPE_VF_P1;
8176 else
8177 goto unknown_vg_1g_port;
8178
8179 val = (phy_encode(PORT_TYPE_1G, 0) |
8180 phy_encode(PORT_TYPE_1G, 1) |
8181 phy_encode(PORT_TYPE_1G, 2) |
8182 phy_encode(PORT_TYPE_1G, 3));
8183 break;
8184
8185 default:
8186 printk(KERN_ERR PFX "Unsupported port config "
8187 "10G[%d] 1G[%d]\n",
8188 num_10g, num_1g);
8189 return -EINVAL;
8190 }
a3138df9
DM		 8191 }
8192
8193 parent->port_phy = val;
8194
8195 if (parent->plat_type == PLAT_TYPE_NIU)
8196 niu_n2_divide_channels(parent);
8197 else
8198 niu_divide_channels(parent, num_10g, num_1g);
8199
8200 niu_divide_rdc_groups(parent, num_10g, num_1g);
8201
8202 return 0;
8203
8204unknown_vg_1g_port:
8205 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
8206 lowest_1g);
8207 return -EINVAL;
8208}
8209
8210static int __devinit niu_probe_ports(struct niu *np)
8211{
8212 struct niu_parent *parent = np->parent;
8213 int err, i;
8214
8215 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
8216 parent->port_phy);
8217
8218 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8219 err = walk_phys(np, parent);
8220 if (err)
8221 return err;
8222
8223 niu_set_ldg_timer_res(np, 2);
8224 for (i = 0; i <= LDN_MAX; i++)
8225 niu_ldn_irq_enable(np, i, 0);
8226 }
8227
8228 if (parent->port_phy == PORT_PHY_INVALID)
8229 return -EINVAL;
8230
8231 return 0;
8232}
8233
8234static int __devinit niu_classifier_swstate_init(struct niu *np)
8235{
8236 struct niu_classifier *cp = &np->clas;
8237
8238 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
8239 np->parent->tcam_num_entries);
8240
8241 cp->tcam_index = (u16) np->port;
8242 cp->h1_init = 0xffffffff;
8243 cp->h2_init = 0xffff;
8244
8245 return fflp_early_init(np);
8246}
8247
8248static void __devinit niu_link_config_init(struct niu *np)
8249{
8250 struct niu_link_config *lp = &np->link_config;
8251
8252 lp->advertising = (ADVERTISED_10baseT_Half |
8253 ADVERTISED_10baseT_Full |
8254 ADVERTISED_100baseT_Half |
8255 ADVERTISED_100baseT_Full |
8256 ADVERTISED_1000baseT_Half |
8257 ADVERTISED_1000baseT_Full |
8258 ADVERTISED_10000baseT_Full |
8259 ADVERTISED_Autoneg);
8260 lp->speed = lp->active_speed = SPEED_INVALID;
8261 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
8262#if 0
8263 lp->loopback_mode = LOOPBACK_MAC;
8264 lp->active_speed = SPEED_10000;
8265 lp->active_duplex = DUPLEX_FULL;
8266#else
8267 lp->loopback_mode = LOOPBACK_DISABLED;
8268#endif
8269}
8270
8271static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8272{
8273 switch (np->port) {
8274 case 0:
8275 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8276 np->ipp_off = 0x00000;
8277 np->pcs_off = 0x04000;
8278 np->xpcs_off = 0x02000;
8279 break;
8280
8281 case 1:
8282 np->mac_regs = np->regs + XMAC_PORT1_OFF;
8283 np->ipp_off = 0x08000;
8284 np->pcs_off = 0x0a000;
8285 np->xpcs_off = 0x08000;
8286 break;
8287
8288 case 2:
8289 np->mac_regs = np->regs + BMAC_PORT2_OFF;
8290 np->ipp_off = 0x04000;
8291 np->pcs_off = 0x0e000;
8292 np->xpcs_off = ~0UL;
8293 break;
8294
8295 case 3:
8296 np->mac_regs = np->regs + BMAC_PORT3_OFF;
8297 np->ipp_off = 0x0c000;
8298 np->pcs_off = 0x12000;
8299 np->xpcs_off = ~0UL;
8300 break;
8301
8302 default:
8303 dev_err(np->device, PFX "Port %u is invalid, cannot "
8304 "compute MAC block offset.\n", np->port);
8305 return -EINVAL;
8306 }
8307
8308 return 0;
8309}
8310
8311static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
8312{
8313 struct msix_entry msi_vec[NIU_NUM_LDG];
8314 struct niu_parent *parent = np->parent;
8315 struct pci_dev *pdev = np->pdev;
8316 int i, num_irqs, err;
8317 u8 first_ldg;
8318
8319 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
8320 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
8321 ldg_num_map[i] = first_ldg + i;
8322
8323 num_irqs = (parent->rxchan_per_port[np->port] +
8324 parent->txchan_per_port[np->port] +
8325 (np->port == 0 ? 3 : 1));
8326 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
8327
8328retry:
8329 for (i = 0; i < num_irqs; i++) {
8330 msi_vec[i].vector = 0;
8331 msi_vec[i].entry = i;
8332 }
8333
8334 err = pci_enable_msix(pdev, msi_vec, num_irqs);
8335 if (err < 0) {
8336 np->flags &= ~NIU_FLAGS_MSIX;
8337 return;
8338 }
8339 if (err > 0) {
8340 num_irqs = err;
8341 goto retry;
8342 }
8343
8344 np->flags |= NIU_FLAGS_MSIX;
8345 for (i = 0; i < num_irqs; i++)
8346 np->ldg[i].irq = msi_vec[i].vector;
8347 np->num_ldg = num_irqs;
8348}
8349
8350static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
8351{
8352#ifdef CONFIG_SPARC64
8353 struct of_device *op = np->op;
8354 const u32 *int_prop;
8355 int i;
8356
8357 int_prop = of_get_property(op->node, "interrupts", NULL);
8358 if (!int_prop)
8359 return -ENODEV;
8360
8361 for (i = 0; i < op->num_irqs; i++) {
8362 ldg_num_map[i] = int_prop[i];
8363 np->ldg[i].irq = op->irqs[i];
8364 }
8365
8366 np->num_ldg = op->num_irqs;
8367
8368 return 0;
8369#else
8370 return -EINVAL;
8371#endif
8372}
8373
8374static int __devinit niu_ldg_init(struct niu *np)
8375{
8376 struct niu_parent *parent = np->parent;
8377 u8 ldg_num_map[NIU_NUM_LDG];
8378 int first_chan, num_chan;
8379 int i, err, ldg_rotor;
8380 u8 port;
8381
8382 np->num_ldg = 1;
8383 np->ldg[0].irq = np->dev->irq;
8384 if (parent->plat_type == PLAT_TYPE_NIU) {
8385 err = niu_n2_irq_init(np, ldg_num_map);
8386 if (err)
8387 return err;
8388 } else
8389 niu_try_msix(np, ldg_num_map);
8390
8391 port = np->port;
8392 for (i = 0; i < np->num_ldg; i++) {
8393 struct niu_ldg *lp = &np->ldg[i];
8394
8395 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
8396
8397 lp->np = np;
8398 lp->ldg_num = ldg_num_map[i];
8399 lp->timer = 2; /* XXX */
8400
8401 /* On N2 NIU the firmware has setup the SID mappings so they go
8402 * to the correct values that will route the LDG to the proper
8403 * interrupt in the NCU interrupt table.
8404 */
8405 if (np->parent->plat_type != PLAT_TYPE_NIU) {
8406 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
8407 if (err)
8408 return err;
8409 }
8410 }
8411
8412 /* We adopt the LDG assignment ordering used by the N2 NIU
8413 * 'interrupt' properties because that simplifies a lot of
8414 * things. This ordering is:
8415 *
8416 * MAC
8417 * MIF (if port zero)
8418 * SYSERR (if port zero)
8419 * RX channels
8420 * TX channels
8421 */
8422
8423 ldg_rotor = 0;
8424
8425 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
8426 LDN_MAC(port));
8427 if (err)
8428 return err;
8429
8430 ldg_rotor++;
8431 if (ldg_rotor == np->num_ldg)
8432 ldg_rotor = 0;
8433
8434 if (port == 0) {
8435 err = niu_ldg_assign_ldn(np, parent,
8436 ldg_num_map[ldg_rotor],
8437 LDN_MIF);
8438 if (err)
8439 return err;
8440
8441 ldg_rotor++;
8442 if (ldg_rotor == np->num_ldg)
8443 ldg_rotor = 0;
8444
8445 err = niu_ldg_assign_ldn(np, parent,
8446 ldg_num_map[ldg_rotor],
8447 LDN_DEVICE_ERROR);
8448 if (err)
8449 return err;
8450
8451 ldg_rotor++;
8452 if (ldg_rotor == np->num_ldg)
8453 ldg_rotor = 0;
8454
8455 }
8456
8457 first_chan = 0;
8458 for (i = 0; i < port; i++)
8459 first_chan += parent->rxchan_per_port[port];
8460 num_chan = parent->rxchan_per_port[port];
8461
8462 for (i = first_chan; i < (first_chan + num_chan); i++) {
8463 err = niu_ldg_assign_ldn(np, parent,
8464 ldg_num_map[ldg_rotor],
8465 LDN_RXDMA(i));
8466 if (err)
8467 return err;
8468 ldg_rotor++;
8469 if (ldg_rotor == np->num_ldg)
8470 ldg_rotor = 0;
8471 }
8472
8473 first_chan = 0;
8474 for (i = 0; i < port; i++)
8475 first_chan += parent->txchan_per_port[port];
8476 num_chan = parent->txchan_per_port[port];
8477 for (i = first_chan; i < (first_chan + num_chan); i++) {
8478 err = niu_ldg_assign_ldn(np, parent,
8479 ldg_num_map[ldg_rotor],
8480 LDN_TXDMA(i));
8481 if (err)
8482 return err;
8483 ldg_rotor++;
8484 if (ldg_rotor == np->num_ldg)
8485 ldg_rotor = 0;
8486 }
8487
8488 return 0;
8489}
8490
8491static void __devexit niu_ldg_free(struct niu *np)
8492{
8493 if (np->flags & NIU_FLAGS_MSIX)
8494 pci_disable_msix(np->pdev);
8495}
8496
8497static int __devinit niu_get_of_props(struct niu *np)
8498{
8499#ifdef CONFIG_SPARC64
8500 struct net_device *dev = np->dev;
8501 struct device_node *dp;
8502 const char *phy_type;
8503 const u8 *mac_addr;
f9af8574 8504 const char *model;
a3138df9
DM		 8505 int prop_len;
8506
8507 if (np->parent->plat_type == PLAT_TYPE_NIU)
8508 dp = np->op->node;
8509 else
8510 dp = pci_device_to_OF_node(np->pdev);
8511
8512 phy_type = of_get_property(dp, "phy-type", &prop_len);
8513 if (!phy_type) {
8514 dev_err(np->device, PFX "%s: OF node lacks "
8515 "phy-type property\n",
8516 dp->full_name);
8517 return -EINVAL;
8518 }
8519
8520 if (!strcmp(phy_type, "none"))
8521 return -ENODEV;
8522
8523 strcpy(np->vpd.phy_type, phy_type);
8524
8525 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
8526 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
8527 dp->full_name, np->vpd.phy_type);
8528 return -EINVAL;
8529 }
8530
8531 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
8532 if (!mac_addr) {
8533 dev_err(np->device, PFX "%s: OF node lacks "
8534 "local-mac-address property\n",
8535 dp->full_name);
8536 return -EINVAL;
8537 }
8538 if (prop_len != dev->addr_len) {
8539 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
8540 "is wrong.\n",
8541 dp->full_name, prop_len);
8542 }
8543 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
8544 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
8545 int i;
8546
8547 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
8548 dp->full_name);
8549 dev_err(np->device, PFX "%s: [ \n",
8550 dp->full_name);
8551 for (i = 0; i < 6; i++)
8552 printk("%02x ", dev->perm_addr[i]);
8553 printk("]\n");
8554 return -EINVAL;
8555 }
8556
8557 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 8558
8559 model = of_get_property(dp, "model", &prop_len);
8560
8561 if (model)
8562 strcpy(np->vpd.model, model);
a3138df9
DM		 8563
8564 return 0;
8565#else
8566 return -EINVAL;
8567#endif
8568}
8569
8570static int __devinit niu_get_invariants(struct niu *np)
8571{
8572 int err, have_props;
8573 u32 offset;
8574
8575 err = niu_get_of_props(np);
8576 if (err == -ENODEV)
8577 return err;
8578
8579 have_props = !err;
8580
a3138df9
DM		 8581 err = niu_init_mac_ipp_pcs_base(np);
8582 if (err)
8583 return err;
8584
7f7c4072
MW		 8585 if (have_props) {
8586 err = niu_get_and_validate_port(np);
8587 if (err)
8588 return err;
8589
8590 } else {
a3138df9
DM		 8591 if (np->parent->plat_type == PLAT_TYPE_NIU)
8592 return -EINVAL;
8593
8594 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
8595 offset = niu_pci_vpd_offset(np);
8596 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
8597 offset);
8598 if (offset)
8599 niu_pci_vpd_fetch(np, offset);
8600 nw64(ESPC_PIO_EN, 0);
8601
7f7c4072 8602 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 8603 niu_pci_vpd_validate(np);
7f7c4072
MW		 8604 err = niu_get_and_validate_port(np);
8605 if (err)
8606 return err;
8607 }
a3138df9
DM		 8608
8609 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 8610 err = niu_get_and_validate_port(np);
8611 if (err)
8612 return err;
a3138df9
DM		 8613 err = niu_pci_probe_sprom(np);
8614 if (err)
8615 return err;
8616 }
8617 }
8618
8619 err = niu_probe_ports(np);
8620 if (err)
8621 return err;
8622
8623 niu_ldg_init(np);
8624
8625 niu_classifier_swstate_init(np);
8626 niu_link_config_init(np);
8627
8628 err = niu_determine_phy_disposition(np);
8629 if (!err)
8630 err = niu_init_link(np);
8631
8632 return err;
8633}
8634
8635static LIST_HEAD(niu_parent_list);
8636static DEFINE_MUTEX(niu_parent_lock);
8637static int niu_parent_index;
8638
8639static ssize_t show_port_phy(struct device *dev,
8640 struct device_attribute *attr, char *buf)
8641{
8642 struct platform_device *plat_dev = to_platform_device(dev);
8643 struct niu_parent *p = plat_dev->dev.platform_data;
8644 u32 port_phy = p->port_phy;
8645 char *orig_buf = buf;
8646 int i;
8647
8648 if (port_phy == PORT_PHY_UNKNOWN ||
8649 port_phy == PORT_PHY_INVALID)
8650 return 0;
8651
8652 for (i = 0; i < p->num_ports; i++) {
8653 const char *type_str;
8654 int type;
8655
8656 type = phy_decode(port_phy, i);
8657 if (type == PORT_TYPE_10G)
8658 type_str = "10G";
8659 else
8660 type_str = "1G";
8661 buf += sprintf(buf,
8662 (i == 0) ? "%s" : " %s",
8663 type_str);
8664 }
8665 buf += sprintf(buf, "\n");
8666 return buf - orig_buf;
8667}
8668
8669static ssize_t show_plat_type(struct device *dev,
8670 struct device_attribute *attr, char *buf)
8671{
8672 struct platform_device *plat_dev = to_platform_device(dev);
8673 struct niu_parent *p = plat_dev->dev.platform_data;
8674 const char *type_str;
8675
8676 switch (p->plat_type) {
8677 case PLAT_TYPE_ATLAS:
8678 type_str = "atlas";
8679 break;
8680 case PLAT_TYPE_NIU:
8681 type_str = "niu";
8682 break;
8683 case PLAT_TYPE_VF_P0:
8684 type_str = "vf_p0";
8685 break;
8686 case PLAT_TYPE_VF_P1:
8687 type_str = "vf_p1";
8688 break;
8689 default:
8690 type_str = "unknown";
8691 break;
8692 }
8693
8694 return sprintf(buf, "%s\n", type_str);
8695}
8696
8697static ssize_t __show_chan_per_port(struct device *dev,
8698 struct device_attribute *attr, char *buf,
8699 int rx)
8700{
8701 struct platform_device *plat_dev = to_platform_device(dev);
8702 struct niu_parent *p = plat_dev->dev.platform_data;
8703 char *orig_buf = buf;
8704 u8 *arr;
8705 int i;
8706
8707 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
8708
8709 for (i = 0; i < p->num_ports; i++) {
8710 buf += sprintf(buf,
8711 (i == 0) ? "%d" : " %d",
8712 arr[i]);
8713 }
8714 buf += sprintf(buf, "\n");
8715
8716 return buf - orig_buf;
8717}
8718
8719static ssize_t show_rxchan_per_port(struct device *dev,
8720 struct device_attribute *attr, char *buf)
8721{
8722 return __show_chan_per_port(dev, attr, buf, 1);
8723}
8724
8725static ssize_t show_txchan_per_port(struct device *dev,
8726 struct device_attribute *attr, char *buf)
8727{
8728 return __show_chan_per_port(dev, attr, buf, 1);
8729}
8730
8731static ssize_t show_num_ports(struct device *dev,
8732 struct device_attribute *attr, char *buf)
8733{
8734 struct platform_device *plat_dev = to_platform_device(dev);
8735 struct niu_parent *p = plat_dev->dev.platform_data;
8736
8737 return sprintf(buf, "%d\n", p->num_ports);
8738}
8739
8740static struct device_attribute niu_parent_attributes[] = {
8741 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
8742 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
8743 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
8744 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
8745 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
8746 {}
8747};
8748
8749static struct niu_parent * __devinit niu_new_parent(struct niu *np,
8750 union niu_parent_id *id,
8751 u8 ptype)
8752{
8753 struct platform_device *plat_dev;
8754 struct niu_parent *p;
8755 int i;
8756
8757 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
8758
8759 plat_dev = platform_device_register_simple("niu", niu_parent_index,
8760 NULL, 0);
8761 if (!plat_dev)
8762 return NULL;
8763
8764 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
8765 int err = device_create_file(&plat_dev->dev,
8766 &niu_parent_attributes[i]);
8767 if (err)
8768 goto fail_unregister;
8769 }
8770
8771 p = kzalloc(sizeof(*p), GFP_KERNEL);
8772 if (!p)
8773 goto fail_unregister;
8774
8775 p->index = niu_parent_index++;
8776
8777 plat_dev->dev.platform_data = p;
8778 p->plat_dev = plat_dev;
8779
8780 memcpy(&p->id, id, sizeof(*id));
8781 p->plat_type = ptype;
8782 INIT_LIST_HEAD(&p->list);
8783 atomic_set(&p->refcnt, 0);
8784 list_add(&p->list, &niu_parent_list);
8785 spin_lock_init(&p->lock);
8786
8787 p->rxdma_clock_divider = 7500;
8788
8789 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
8790 if (p->plat_type == PLAT_TYPE_NIU)
8791 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
8792
8793 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
8794 int index = i - CLASS_CODE_USER_PROG1;
8795
8796 p->tcam_key[index] = TCAM_KEY_TSEL;
8797 p->flow_key[index] = (FLOW_KEY_IPSA |
8798 FLOW_KEY_IPDA |
8799 FLOW_KEY_PROTO |
8800 (FLOW_KEY_L4_BYTE12 <<
8801 FLOW_KEY_L4_0_SHIFT) |
8802 (FLOW_KEY_L4_BYTE12 <<
8803 FLOW_KEY_L4_1_SHIFT));
8804 }
8805
8806 for (i = 0; i < LDN_MAX + 1; i++)
8807 p->ldg_map[i] = LDG_INVALID;
8808
8809 return p;
8810
8811fail_unregister:
8812 platform_device_unregister(plat_dev);
8813 return NULL;
8814}
8815
8816static struct niu_parent * __devinit niu_get_parent(struct niu *np,
8817 union niu_parent_id *id,
8818 u8 ptype)
8819{
8820 struct niu_parent *p, *tmp;
8821 int port = np->port;
8822
8823 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
8824 ptype, port);
8825
8826 mutex_lock(&niu_parent_lock);
8827 p = NULL;
8828 list_for_each_entry(tmp, &niu_parent_list, list) {
8829 if (!memcmp(id, &tmp->id, sizeof(*id))) {
8830 p = tmp;
8831 break;
8832 }
8833 }
8834 if (!p)
8835 p = niu_new_parent(np, id, ptype);
8836
8837 if (p) {
8838 char port_name[6];
8839 int err;
8840
8841 sprintf(port_name, "port%d", port);
8842 err = sysfs_create_link(&p->plat_dev->dev.kobj,
8843 &np->device->kobj,
8844 port_name);
8845 if (!err) {
8846 p->ports[port] = np;
8847 atomic_inc(&p->refcnt);
8848 }
8849 }
8850 mutex_unlock(&niu_parent_lock);
8851
8852 return p;
8853}
8854
8855static void niu_put_parent(struct niu *np)
8856{
8857 struct niu_parent *p = np->parent;
8858 u8 port = np->port;
8859 char port_name[6];
8860
8861 BUG_ON(!p || p->ports[port] != np);
8862
8863 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
8864
8865 sprintf(port_name, "port%d", port);
8866
8867 mutex_lock(&niu_parent_lock);
8868
8869 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
8870
8871 p->ports[port] = NULL;
8872 np->parent = NULL;
8873
8874 if (atomic_dec_and_test(&p->refcnt)) {
8875 list_del(&p->list);
8876 platform_device_unregister(p->plat_dev);
8877 }
8878
8879 mutex_unlock(&niu_parent_lock);
8880}
8881
8882static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
8883 u64 *handle, gfp_t flag)
8884{
8885 dma_addr_t dh;
8886 void *ret;
8887
8888 ret = dma_alloc_coherent(dev, size, &dh, flag);
8889 if (ret)
8890 *handle = dh;
8891 return ret;
8892}
8893
8894static void niu_pci_free_coherent(struct device *dev, size_t size,
8895 void *cpu_addr, u64 handle)
8896{
8897 dma_free_coherent(dev, size, cpu_addr, handle);
8898}
8899
8900static u64 niu_pci_map_page(struct device *dev, struct page *page,
8901 unsigned long offset, size_t size,
8902 enum dma_data_direction direction)
8903{
8904 return dma_map_page(dev, page, offset, size, direction);
8905}
8906
8907static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
8908 size_t size, enum dma_data_direction direction)
8909{
a08b32df 8910 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 8911}
8912
8913static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
8914 size_t size,
8915 enum dma_data_direction direction)
8916{
8917 return dma_map_single(dev, cpu_addr, size, direction);
8918}
8919
8920static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
8921 size_t size,
8922 enum dma_data_direction direction)
8923{
8924 dma_unmap_single(dev, dma_address, size, direction);
8925}
8926
8927static const struct niu_ops niu_pci_ops = {
8928 .alloc_coherent = niu_pci_alloc_coherent,
8929 .free_coherent = niu_pci_free_coherent,
8930 .map_page = niu_pci_map_page,
8931 .unmap_page = niu_pci_unmap_page,
8932 .map_single = niu_pci_map_single,
8933 .unmap_single = niu_pci_unmap_single,
8934};
8935
8936static void __devinit niu_driver_version(void)
8937{
8938 static int niu_version_printed;
8939
8940 if (niu_version_printed++ == 0)
8941 pr_info("%s", version);
8942}
8943
8944static struct net_device * __devinit niu_alloc_and_init(
8945 struct device *gen_dev, struct pci_dev *pdev,
8946 struct of_device *op, const struct niu_ops *ops,
8947 u8 port)
8948{
b4c21639 8949 struct net_device *dev;
a3138df9
DM		 8950 struct niu *np;
8951
b4c21639 8952 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9
DM		 8953 if (!dev) {
8954 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
8955 return NULL;
8956 }
8957
8958 SET_NETDEV_DEV(dev, gen_dev);
8959
8960 np = netdev_priv(dev);
8961 np->dev = dev;
8962 np->pdev = pdev;
8963 np->op = op;
8964 np->device = gen_dev;
8965 np->ops = ops;
8966
8967 np->msg_enable = niu_debug;
8968
8969 spin_lock_init(&np->lock);
8970 INIT_WORK(&np->reset_task, niu_reset_task);
8971
8972 np->port = port;
8973
8974 return dev;
8975}
8976
2c9171d4
SH		 8977static const struct net_device_ops niu_netdev_ops = {
8978 .ndo_open = niu_open,
8979 .ndo_stop = niu_close,
00829823 8980 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 8981 .ndo_get_stats = niu_get_stats,
8982 .ndo_set_multicast_list = niu_set_rx_mode,
8983 .ndo_validate_addr = eth_validate_addr,
8984 .ndo_set_mac_address = niu_set_mac_addr,
8985 .ndo_do_ioctl = niu_ioctl,
8986 .ndo_tx_timeout = niu_tx_timeout,
8987 .ndo_change_mtu = niu_change_mtu,
8988};
8989
a3138df9
DM		 8990static void __devinit niu_assign_netdev_ops(struct net_device *dev)
8991{
2c9171d4 8992 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 8993 dev->ethtool_ops = &niu_ethtool_ops;
8994 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 8995}
8996
8997static void __devinit niu_device_announce(struct niu *np)
8998{
8999 struct net_device *dev = np->dev;
a3138df9 9000
e174961c 9001 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9002
5fbd7e24
MW		 9003 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9004 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9005 dev->name,
9006 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9007 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9008 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9009 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9010 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9011 np->vpd.phy_type);
9012 } else {
9013 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9014 dev->name,
9015 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9016 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9017 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9018 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9019 "COPPER")),
5fbd7e24
MW		 9020 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9021 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9022 np->vpd.phy_type);
9023 }
a3138df9
DM		 9024}
9025
9026static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9027 const struct pci_device_id *ent)
9028{
a3138df9
DM		 9029 union niu_parent_id parent_id;
9030 struct net_device *dev;
9031 struct niu *np;
9032 int err, pos;
9033 u64 dma_mask;
9034 u16 val16;
9035
9036 niu_driver_version();
9037
9038 err = pci_enable_device(pdev);
9039 if (err) {
9040 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
9041 "aborting.\n");
9042 return err;
9043 }
9044
9045 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9046 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9047 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
9048 "base addresses, aborting.\n");
9049 err = -ENODEV;
9050 goto err_out_disable_pdev;
9051 }
9052
9053 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9054 if (err) {
9055 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
9056 "aborting.\n");
9057 goto err_out_disable_pdev;
9058 }
9059
9060 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9061 if (pos <= 0) {
9062 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
9063 "aborting.\n");
9064 goto err_out_free_res;
9065 }
9066
9067 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9068 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9069 if (!dev) {
9070 err = -ENOMEM;
9071 goto err_out_free_res;
9072 }
9073 np = netdev_priv(dev);
9074
9075 memset(&parent_id, 0, sizeof(parent_id));
9076 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9077 parent_id.pci.bus = pdev->bus->number;
9078 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9079
9080 np->parent = niu_get_parent(np, &parent_id,
9081 PLAT_TYPE_ATLAS);
9082 if (!np->parent) {
9083 err = -ENOMEM;
9084 goto err_out_free_dev;
9085 }
9086
9087 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9088 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9089 val16 |= (PCI_EXP_DEVCTL_CERE |
9090 PCI_EXP_DEVCTL_NFERE |
9091 PCI_EXP_DEVCTL_FERE |
9092 PCI_EXP_DEVCTL_URRE |
9093 PCI_EXP_DEVCTL_RELAX_EN);
9094 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9095
9096 dma_mask = DMA_44BIT_MASK;
9097 err = pci_set_dma_mask(pdev, dma_mask);
9098 if (!err) {
9099 dev->features |= NETIF_F_HIGHDMA;
9100 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9101 if (err) {
9102 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
9103 "DMA for consistent allocations, "
9104 "aborting.\n");
9105 goto err_out_release_parent;
9106 }
9107 }
9108 if (err || dma_mask == DMA_32BIT_MASK) {
9109 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
9110 if (err) {
9111 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
9112 "aborting.\n");
9113 goto err_out_release_parent;
9114 }
9115 }
9116
9117 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9118
19ecb6ba 9119 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9
DM		 9120 if (!np->regs) {
9121 dev_err(&pdev->dev, PFX "Cannot map device registers, "
9122 "aborting.\n");
9123 err = -ENOMEM;
9124 goto err_out_release_parent;
9125 }
9126
9127 pci_set_master(pdev);
9128 pci_save_state(pdev);
9129
9130 dev->irq = pdev->irq;
9131
9132 niu_assign_netdev_ops(dev);
9133
9134 err = niu_get_invariants(np);
9135 if (err) {
9136 if (err != -ENODEV)
9137 dev_err(&pdev->dev, PFX "Problem fetching invariants "
9138 "of chip, aborting.\n");
9139 goto err_out_iounmap;
9140 }
9141
9142 err = register_netdev(dev);
9143 if (err) {
9144 dev_err(&pdev->dev, PFX "Cannot register net device, "
9145 "aborting.\n");
9146 goto err_out_iounmap;
9147 }
9148
9149 pci_set_drvdata(pdev, dev);
9150
9151 niu_device_announce(np);
9152
9153 return 0;
9154
9155err_out_iounmap:
9156 if (np->regs) {
9157 iounmap(np->regs);
9158 np->regs = NULL;
9159 }
9160
9161err_out_release_parent:
9162 niu_put_parent(np);
9163
9164err_out_free_dev:
9165 free_netdev(dev);
9166
9167err_out_free_res:
9168 pci_release_regions(pdev);
9169
9170err_out_disable_pdev:
9171 pci_disable_device(pdev);
9172 pci_set_drvdata(pdev, NULL);
9173
9174 return err;
9175}
9176
9177static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9178{
9179 struct net_device *dev = pci_get_drvdata(pdev);
9180
9181 if (dev) {
9182 struct niu *np = netdev_priv(dev);
9183
9184 unregister_netdev(dev);
9185 if (np->regs) {
9186 iounmap(np->regs);
9187 np->regs = NULL;
9188 }
9189
9190 niu_ldg_free(np);
9191
9192 niu_put_parent(np);
9193
9194 free_netdev(dev);
9195 pci_release_regions(pdev);
9196 pci_disable_device(pdev);
9197 pci_set_drvdata(pdev, NULL);
9198 }
9199}
9200
9201static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9202{
9203 struct net_device *dev = pci_get_drvdata(pdev);
9204 struct niu *np = netdev_priv(dev);
9205 unsigned long flags;
9206
9207 if (!netif_running(dev))
9208 return 0;
9209
9210 flush_scheduled_work();
9211 niu_netif_stop(np);
9212
9213 del_timer_sync(&np->timer);
9214
9215 spin_lock_irqsave(&np->lock, flags);
9216 niu_enable_interrupts(np, 0);
9217 spin_unlock_irqrestore(&np->lock, flags);
9218
9219 netif_device_detach(dev);
9220
9221 spin_lock_irqsave(&np->lock, flags);
9222 niu_stop_hw(np);
9223 spin_unlock_irqrestore(&np->lock, flags);
9224
9225 pci_save_state(pdev);
9226
9227 return 0;
9228}
9229
9230static int niu_resume(struct pci_dev *pdev)
9231{
9232 struct net_device *dev = pci_get_drvdata(pdev);
9233 struct niu *np = netdev_priv(dev);
9234 unsigned long flags;
9235 int err;
9236
9237 if (!netif_running(dev))
9238 return 0;
9239
9240 pci_restore_state(pdev);
9241
9242 netif_device_attach(dev);
9243
9244 spin_lock_irqsave(&np->lock, flags);
9245
9246 err = niu_init_hw(np);
9247 if (!err) {
9248 np->timer.expires = jiffies + HZ;
9249 add_timer(&np->timer);
9250 niu_netif_start(np);
9251 }
9252
9253 spin_unlock_irqrestore(&np->lock, flags);
9254
9255 return err;
9256}
9257
9258static struct pci_driver niu_pci_driver = {
9259 .name = DRV_MODULE_NAME,
9260 .id_table = niu_pci_tbl,
9261 .probe = niu_pci_init_one,
9262 .remove = __devexit_p(niu_pci_remove_one),
9263 .suspend = niu_suspend,
9264 .resume = niu_resume,
9265};
9266
9267#ifdef CONFIG_SPARC64
9268static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9269 u64 *dma_addr, gfp_t flag)
9270{
9271 unsigned long order = get_order(size);
9272 unsigned long page = __get_free_pages(flag, order);
9273
9274 if (page == 0UL)
9275 return NULL;
9276 memset((char *)page, 0, PAGE_SIZE << order);
9277 *dma_addr = __pa(page);
9278
9279 return (void *) page;
9280}
9281
9282static void niu_phys_free_coherent(struct device *dev, size_t size,
9283 void *cpu_addr, u64 handle)
9284{
9285 unsigned long order = get_order(size);
9286
9287 free_pages((unsigned long) cpu_addr, order);
9288}
9289
9290static u64 niu_phys_map_page(struct device *dev, struct page *page,
9291 unsigned long offset, size_t size,
9292 enum dma_data_direction direction)
9293{
9294 return page_to_phys(page) + offset;
9295}
9296
9297static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
9298 size_t size, enum dma_data_direction direction)
9299{
9300 /* Nothing to do. */
9301}
9302
9303static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
9304 size_t size,
9305 enum dma_data_direction direction)
9306{
9307 return __pa(cpu_addr);
9308}
9309
9310static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
9311 size_t size,
9312 enum dma_data_direction direction)
9313{
9314 /* Nothing to do. */
9315}
9316
9317static const struct niu_ops niu_phys_ops = {
9318 .alloc_coherent = niu_phys_alloc_coherent,
9319 .free_coherent = niu_phys_free_coherent,
9320 .map_page = niu_phys_map_page,
9321 .unmap_page = niu_phys_unmap_page,
9322 .map_single = niu_phys_map_single,
9323 .unmap_single = niu_phys_unmap_single,
9324};
9325
9326static unsigned long res_size(struct resource *r)
9327{
9328 return r->end - r->start + 1UL;
9329}
9330
9331static int __devinit niu_of_probe(struct of_device *op,
9332 const struct of_device_id *match)
9333{
9334 union niu_parent_id parent_id;
9335 struct net_device *dev;
9336 struct niu *np;
9337 const u32 *reg;
9338 int err;
9339
9340 niu_driver_version();
9341
9342 reg = of_get_property(op->node, "reg", NULL);
9343 if (!reg) {
9344 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
9345 op->node->full_name);
9346 return -ENODEV;
9347 }
9348
9349 dev = niu_alloc_and_init(&op->dev, NULL, op,
9350 &niu_phys_ops, reg[0] & 0x1);
9351 if (!dev) {
9352 err = -ENOMEM;
9353 goto err_out;
9354 }
9355 np = netdev_priv(dev);
9356
9357 memset(&parent_id, 0, sizeof(parent_id));
9358 parent_id.of = of_get_parent(op->node);
9359
9360 np->parent = niu_get_parent(np, &parent_id,
9361 PLAT_TYPE_NIU);
9362 if (!np->parent) {
9363 err = -ENOMEM;
9364 goto err_out_free_dev;
9365 }
9366
9367 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
9368
9369 np->regs = of_ioremap(&op->resource[1], 0,
9370 res_size(&op->resource[1]),
9371 "niu regs");
9372 if (!np->regs) {
9373 dev_err(&op->dev, PFX "Cannot map device registers, "
9374 "aborting.\n");
9375 err = -ENOMEM;
9376 goto err_out_release_parent;
9377 }
9378
9379 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
9380 res_size(&op->resource[2]),
9381 "niu vregs-1");
9382 if (!np->vir_regs_1) {
9383 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
9384 "aborting.\n");
9385 err = -ENOMEM;
9386 goto err_out_iounmap;
9387 }
9388
9389 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
9390 res_size(&op->resource[3]),
9391 "niu vregs-2");
9392 if (!np->vir_regs_2) {
9393 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
9394 "aborting.\n");
9395 err = -ENOMEM;
9396 goto err_out_iounmap;
9397 }
9398
9399 niu_assign_netdev_ops(dev);
9400
9401 err = niu_get_invariants(np);
9402 if (err) {
9403 if (err != -ENODEV)
9404 dev_err(&op->dev, PFX "Problem fetching invariants "
9405 "of chip, aborting.\n");
9406 goto err_out_iounmap;
9407 }
9408
9409 err = register_netdev(dev);
9410 if (err) {
9411 dev_err(&op->dev, PFX "Cannot register net device, "
9412 "aborting.\n");
9413 goto err_out_iounmap;
9414 }
9415
9416 dev_set_drvdata(&op->dev, dev);
9417
9418 niu_device_announce(np);
9419
9420 return 0;
9421
9422err_out_iounmap:
9423 if (np->vir_regs_1) {
9424 of_iounmap(&op->resource[2], np->vir_regs_1,
9425 res_size(&op->resource[2]));
9426 np->vir_regs_1 = NULL;
9427 }
9428
9429 if (np->vir_regs_2) {
9430 of_iounmap(&op->resource[3], np->vir_regs_2,
9431 res_size(&op->resource[3]));
9432 np->vir_regs_2 = NULL;
9433 }
9434
9435 if (np->regs) {
9436 of_iounmap(&op->resource[1], np->regs,
9437 res_size(&op->resource[1]));
9438 np->regs = NULL;
9439 }
9440
9441err_out_release_parent:
9442 niu_put_parent(np);
9443
9444err_out_free_dev:
9445 free_netdev(dev);
9446
9447err_out:
9448 return err;
9449}
9450
9451static int __devexit niu_of_remove(struct of_device *op)
9452{
9453 struct net_device *dev = dev_get_drvdata(&op->dev);
9454
9455 if (dev) {
9456 struct niu *np = netdev_priv(dev);
9457
9458 unregister_netdev(dev);
9459
9460 if (np->vir_regs_1) {
9461 of_iounmap(&op->resource[2], np->vir_regs_1,
9462 res_size(&op->resource[2]));
9463 np->vir_regs_1 = NULL;
9464 }
9465
9466 if (np->vir_regs_2) {
9467 of_iounmap(&op->resource[3], np->vir_regs_2,
9468 res_size(&op->resource[3]));
9469 np->vir_regs_2 = NULL;
9470 }
9471
9472 if (np->regs) {
9473 of_iounmap(&op->resource[1], np->regs,
9474 res_size(&op->resource[1]));
9475 np->regs = NULL;
9476 }
9477
9478 niu_ldg_free(np);
9479
9480 niu_put_parent(np);
9481
9482 free_netdev(dev);
9483 dev_set_drvdata(&op->dev, NULL);
9484 }
9485 return 0;
9486}
9487
fd098316 9488static const struct of_device_id niu_match[] = {
a3138df9
DM		 9489 {
9490 .name = "network",
9491 .compatible = "SUNW,niusl",
9492 },
9493 {},
9494};
9495MODULE_DEVICE_TABLE(of, niu_match);
9496
9497static struct of_platform_driver niu_of_driver = {
9498 .name = "niu",
9499 .match_table = niu_match,
9500 .probe = niu_of_probe,
9501 .remove = __devexit_p(niu_of_remove),
9502};
9503
9504#endif /* CONFIG_SPARC64 */
9505
9506static int __init niu_init(void)
9507{
9508 int err = 0;
9509
81429973 9510 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 9511
9512 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
9513
9514#ifdef CONFIG_SPARC64
9515 err = of_register_driver(&niu_of_driver, &of_bus_type);
9516#endif
9517
9518 if (!err) {
9519 err = pci_register_driver(&niu_pci_driver);
9520#ifdef CONFIG_SPARC64
9521 if (err)
9522 of_unregister_driver(&niu_of_driver);
9523#endif
9524 }
9525
9526 return err;
9527}
9528
9529static void __exit niu_exit(void)
9530{
9531 pci_unregister_driver(&niu_pci_driver);
9532#ifdef CONFIG_SPARC64
9533 of_unregister_driver(&niu_of_driver);
9534#endif
9535}
9536
9537module_init(niu_init);
9538module_exit(niu_exit);
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