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a3138df9
DM		 1/* niu.c: Neptune ethernet driver.
2 *
be0c007a 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
a3138df9
DM		 4 */
5
f10a1f2e
JP		 6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
a3138df9
DM		 8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/dma-mapping.h>
12#include <linux/netdevice.h>
13#include <linux/ethtool.h>
14#include <linux/etherdevice.h>
15#include <linux/platform_device.h>
16#include <linux/delay.h>
17#include <linux/bitops.h>
18#include <linux/mii.h>
19#include <linux/if_ether.h>
20#include <linux/if_vlan.h>
21#include <linux/ip.h>
22#include <linux/in.h>
23#include <linux/ipv6.h>
24#include <linux/log2.h>
25#include <linux/jiffies.h>
26#include <linux/crc32.h>
ccffad25 27#include <linux/list.h>
5a0e3ad6 28#include <linux/slab.h>
a3138df9
DM		 29
30#include <linux/io.h>
a3138df9 31#include <linux/of_device.h>
a3138df9
DM		 32
33#include "niu.h"
34
35#define DRV_MODULE_NAME "niu"
3cfa856d
DM		 36#define DRV_MODULE_VERSION "1.1"
37#define DRV_MODULE_RELDATE "Apr 22, 2010"
a3138df9
DM		 38
39static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43MODULE_DESCRIPTION("NIU ethernet driver");
44MODULE_LICENSE("GPL");
45MODULE_VERSION(DRV_MODULE_VERSION);
46
a3138df9
DM		 47#ifndef readq
48static u64 readq(void __iomem *reg)
49{
e23a59e1 50 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
a3138df9
DM		 51}
52
53static void writeq(u64 val, void __iomem *reg)
54{
55 writel(val & 0xffffffff, reg);
56 writel(val >> 32, reg + 0x4UL);
57}
58#endif
59
a3aa1884 60static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = {
a3138df9
DM		 61 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
62 {}
63};
64
65MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
66
67#define NIU_TX_TIMEOUT (5 * HZ)
68
69#define nr64(reg) readq(np->regs + (reg))
70#define nw64(reg, val) writeq((val), np->regs + (reg))
71
72#define nr64_mac(reg) readq(np->mac_regs + (reg))
73#define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
74
75#define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76#define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
77
78#define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79#define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
80
81#define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82#define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
83
84#define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
85
86static int niu_debug;
87static int debug = -1;
88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "NIU debug level");
90
a3138df9
DM		 91#define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93#define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
95
5fbd7e24
MW		 96static int serdes_init_10g_serdes(struct niu *np);
97
a3138df9
DM		 98static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
99 u64 bits, int limit, int delay)
100{
101 while (--limit >= 0) {
102 u64 val = nr64_mac(reg);
103
104 if (!(val & bits))
105 break;
106 udelay(delay);
107 }
108 if (limit < 0)
109 return -ENODEV;
110 return 0;
111}
112
113static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
114 u64 bits, int limit, int delay,
115 const char *reg_name)
116{
117 int err;
118
119 nw64_mac(reg, bits);
120 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
121 if (err)
f10a1f2e
JP		 122 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits, reg_name,
124 (unsigned long long)nr64_mac(reg));
a3138df9
DM		 125 return err;
126}
127
128#define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
131})
132
133static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
134 u64 bits, int limit, int delay)
135{
136 while (--limit >= 0) {
137 u64 val = nr64_ipp(reg);
138
139 if (!(val & bits))
140 break;
141 udelay(delay);
142 }
143 if (limit < 0)
144 return -ENODEV;
145 return 0;
146}
147
148static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
149 u64 bits, int limit, int delay,
150 const char *reg_name)
151{
152 int err;
153 u64 val;
154
155 val = nr64_ipp(reg);
156 val |= bits;
157 nw64_ipp(reg, val);
158
159 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
160 if (err)
f10a1f2e
JP		 161 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits, reg_name,
163 (unsigned long long)nr64_ipp(reg));
a3138df9
DM		 164 return err;
165}
166
167#define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
170})
171
172static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
173 u64 bits, int limit, int delay)
174{
175 while (--limit >= 0) {
176 u64 val = nr64(reg);
177
178 if (!(val & bits))
179 break;
180 udelay(delay);
181 }
182 if (limit < 0)
183 return -ENODEV;
184 return 0;
185}
186
187#define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
190})
191
192static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay,
194 const char *reg_name)
195{
196 int err;
197
198 nw64(reg, bits);
199 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
200 if (err)
f10a1f2e
JP		 201 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits, reg_name,
203 (unsigned long long)nr64(reg));
a3138df9
DM		 204 return err;
205}
206
207#define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
210})
211
212static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
213{
214 u64 val = (u64) lp->timer;
215
216 if (on)
217 val |= LDG_IMGMT_ARM;
218
219 nw64(LDG_IMGMT(lp->ldg_num), val);
220}
221
222static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
223{
224 unsigned long mask_reg, bits;
225 u64 val;
226
227 if (ldn < 0 || ldn > LDN_MAX)
228 return -EINVAL;
229
230 if (ldn < 64) {
231 mask_reg = LD_IM0(ldn);
232 bits = LD_IM0_MASK;
233 } else {
234 mask_reg = LD_IM1(ldn - 64);
235 bits = LD_IM1_MASK;
236 }
237
238 val = nr64(mask_reg);
239 if (on)
240 val &= ~bits;
241 else
242 val |= bits;
243 nw64(mask_reg, val);
244
245 return 0;
246}
247
248static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
249{
250 struct niu_parent *parent = np->parent;
251 int i;
252
253 for (i = 0; i <= LDN_MAX; i++) {
254 int err;
255
256 if (parent->ldg_map[i] != lp->ldg_num)
257 continue;
258
259 err = niu_ldn_irq_enable(np, i, on);
260 if (err)
261 return err;
262 }
263 return 0;
264}
265
266static int niu_enable_interrupts(struct niu *np, int on)
267{
268 int i;
269
270 for (i = 0; i < np->num_ldg; i++) {
271 struct niu_ldg *lp = &np->ldg[i];
272 int err;
273
274 err = niu_enable_ldn_in_ldg(np, lp, on);
275 if (err)
276 return err;
277 }
278 for (i = 0; i < np->num_ldg; i++)
279 niu_ldg_rearm(np, &np->ldg[i], on);
280
281 return 0;
282}
283
284static u32 phy_encode(u32 type, int port)
285{
807540ba 286 return type << (port * 2);
a3138df9
DM		 287}
288
289static u32 phy_decode(u32 val, int port)
290{
291 return (val >> (port * 2)) & PORT_TYPE_MASK;
292}
293
294static int mdio_wait(struct niu *np)
295{
296 int limit = 1000;
297 u64 val;
298
299 while (--limit > 0) {
300 val = nr64(MIF_FRAME_OUTPUT);
301 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
302 return val & MIF_FRAME_OUTPUT_DATA;
303
304 udelay(10);
305 }
306
307 return -ENODEV;
308}
309
310static int mdio_read(struct niu *np, int port, int dev, int reg)
311{
312 int err;
313
314 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
315 err = mdio_wait(np);
316 if (err < 0)
317 return err;
318
319 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
320 return mdio_wait(np);
321}
322
323static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
324{
325 int err;
326
327 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
328 err = mdio_wait(np);
329 if (err < 0)
330 return err;
331
332 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
333 err = mdio_wait(np);
334 if (err < 0)
335 return err;
336
337 return 0;
338}
339
340static int mii_read(struct niu *np, int port, int reg)
341{
342 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
343 return mdio_wait(np);
344}
345
346static int mii_write(struct niu *np, int port, int reg, int data)
347{
348 int err;
349
350 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
351 err = mdio_wait(np);
352 if (err < 0)
353 return err;
354
355 return 0;
356}
357
358static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
359{
360 int err;
361
362 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
363 ESR2_TI_PLL_TX_CFG_L(channel),
364 val & 0xffff);
365 if (!err)
366 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
367 ESR2_TI_PLL_TX_CFG_H(channel),
368 val >> 16);
369 return err;
370}
371
372static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
373{
374 int err;
375
376 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
377 ESR2_TI_PLL_RX_CFG_L(channel),
378 val & 0xffff);
379 if (!err)
380 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
381 ESR2_TI_PLL_RX_CFG_H(channel),
382 val >> 16);
383 return err;
384}
385
386/* Mode is always 10G fiber. */
e3e081e1 387static int serdes_init_niu_10g_fiber(struct niu *np)
a3138df9
DM		 388{
389 struct niu_link_config *lp = &np->link_config;
390 u32 tx_cfg, rx_cfg;
391 unsigned long i;
392
393 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
394 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
395 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
396 PLL_RX_CFG_EQ_LP_ADAPTIVE);
397
398 if (lp->loopback_mode == LOOPBACK_PHY) {
399 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
400
401 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
403
404 tx_cfg |= PLL_TX_CFG_ENTEST;
405 rx_cfg |= PLL_RX_CFG_ENTEST;
406 }
407
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i = 0; i < 4; i++) {
410 int err = esr2_set_tx_cfg(np, i, tx_cfg);
411 if (err)
412 return err;
413 }
414
415 for (i = 0; i < 4; i++) {
416 int err = esr2_set_rx_cfg(np, i, rx_cfg);
417 if (err)
418 return err;
419 }
420
421 return 0;
422}
423
e3e081e1
SB		 424static int serdes_init_niu_1g_serdes(struct niu *np)
425{
426 struct niu_link_config *lp = &np->link_config;
427 u16 pll_cfg, pll_sts;
428 int max_retry = 100;
51e0f058 429 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 430 u32 tx_cfg, rx_cfg;
431 unsigned long i;
432 int err;
433
434 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV |
435 PLL_TX_CFG_RATE_HALF);
436 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
437 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
438 PLL_RX_CFG_RATE_HALF);
439
440 if (np->port == 0)
441 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE;
442
443 if (lp->loopback_mode == LOOPBACK_PHY) {
444 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
445
446 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
447 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
448
449 tx_cfg |= PLL_TX_CFG_ENTEST;
450 rx_cfg |= PLL_RX_CFG_ENTEST;
451 }
452
453 /* Initialize PLL for 1G */
454 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
455
456 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
457 ESR2_TI_PLL_CFG_L, pll_cfg);
458 if (err) {
f10a1f2e
JP		 459 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
460 np->port, __func__);
e3e081e1
SB		 461 return err;
462 }
463
464 pll_sts = PLL_CFG_ENPLL;
465
466 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
467 ESR2_TI_PLL_STS_L, pll_sts);
468 if (err) {
f10a1f2e
JP		 469 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
470 np->port, __func__);
e3e081e1
SB		 471 return err;
472 }
473
474 udelay(200);
475
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i = 0; i < 4; i++) {
478 err = esr2_set_tx_cfg(np, i, tx_cfg);
479 if (err)
480 return err;
481 }
482
483 for (i = 0; i < 4; i++) {
484 err = esr2_set_rx_cfg(np, i, rx_cfg);
485 if (err)
486 return err;
487 }
488
489 switch (np->port) {
490 case 0:
491 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
492 mask = val;
493 break;
494
495 case 1:
496 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
497 mask = val;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503
504 while (max_retry--) {
505 sig = nr64(ESR_INT_SIGNALS);
506 if ((sig & mask) == val)
507 break;
508
509 mdelay(500);
510 }
511
512 if ((sig & mask) != val) {
f10a1f2e
JP		 513 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
514 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 515 return -ENODEV;
516 }
517
518 return 0;
519}
520
521static int serdes_init_niu_10g_serdes(struct niu *np)
522{
523 struct niu_link_config *lp = &np->link_config;
524 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
525 int max_retry = 100;
51e0f058 526 u64 uninitialized_var(sig), mask, val;
e3e081e1
SB		 527 unsigned long i;
528 int err;
529
530 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
531 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
532 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
533 PLL_RX_CFG_EQ_LP_ADAPTIVE);
534
535 if (lp->loopback_mode == LOOPBACK_PHY) {
536 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
537
538 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
539 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
540
541 tx_cfg |= PLL_TX_CFG_ENTEST;
542 rx_cfg |= PLL_RX_CFG_ENTEST;
543 }
544
545 /* Initialize PLL for 10G */
546 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
547
548 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
549 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
550 if (err) {
f10a1f2e
JP		 551 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
552 np->port, __func__);
e3e081e1
SB		 553 return err;
554 }
555
556 pll_sts = PLL_CFG_ENPLL;
557
558 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
559 ESR2_TI_PLL_STS_L, pll_sts & 0xffff);
560 if (err) {
f10a1f2e
JP		 561 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
562 np->port, __func__);
e3e081e1
SB		 563 return err;
564 }
565
566 udelay(200);
567
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i = 0; i < 4; i++) {
570 err = esr2_set_tx_cfg(np, i, tx_cfg);
571 if (err)
572 return err;
573 }
574
575 for (i = 0; i < 4; i++) {
576 err = esr2_set_rx_cfg(np, i, rx_cfg);
577 if (err)
578 return err;
579 }
580
581 /* check if serdes is ready */
582
583 switch (np->port) {
584 case 0:
585 mask = ESR_INT_SIGNALS_P0_BITS;
586 val = (ESR_INT_SRDY0_P0 |
587 ESR_INT_DET0_P0 |
588 ESR_INT_XSRDY_P0 |
589 ESR_INT_XDP_P0_CH3 |
590 ESR_INT_XDP_P0_CH2 |
591 ESR_INT_XDP_P0_CH1 |
592 ESR_INT_XDP_P0_CH0);
593 break;
594
595 case 1:
596 mask = ESR_INT_SIGNALS_P1_BITS;
597 val = (ESR_INT_SRDY0_P1 |
598 ESR_INT_DET0_P1 |
599 ESR_INT_XSRDY_P1 |
600 ESR_INT_XDP_P1_CH3 |
601 ESR_INT_XDP_P1_CH2 |
602 ESR_INT_XDP_P1_CH1 |
603 ESR_INT_XDP_P1_CH0);
604 break;
605
606 default:
607 return -EINVAL;
608 }
609
610 while (max_retry--) {
611 sig = nr64(ESR_INT_SIGNALS);
612 if ((sig & mask) == val)
613 break;
614
615 mdelay(500);
616 }
617
618 if ((sig & mask) != val) {
f10a1f2e
JP		 619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np->port, (int)(sig & mask), (int)val);
e3e081e1
SB		 621
622 /* 10G failed, try initializing at 1G */
623 err = serdes_init_niu_1g_serdes(np);
624 if (!err) {
625 np->flags &= ~NIU_FLAGS_10G;
626 np->mac_xcvr = MAC_XCVR_PCS;
627 } else {
f10a1f2e
JP		 628 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
629 np->port);
e3e081e1
SB		 630 return -ENODEV;
631 }
632 }
633 return 0;
634}
635
a3138df9
DM		 636static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
637{
638 int err;
639
640 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
641 if (err >= 0) {
642 *val = (err & 0xffff);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
644 ESR_RXTX_CTRL_H(chan));
645 if (err >= 0)
646 *val |= ((err & 0xffff) << 16);
647 err = 0;
648 }
649 return err;
650}
651
652static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
653{
654 int err;
655
656 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
657 ESR_GLUE_CTRL0_L(chan));
658 if (err >= 0) {
659 *val = (err & 0xffff);
660 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 ESR_GLUE_CTRL0_H(chan));
662 if (err >= 0) {
663 *val |= ((err & 0xffff) << 16);
664 err = 0;
665 }
666 }
667 return err;
668}
669
670static int esr_read_reset(struct niu *np, u32 *val)
671{
672 int err;
673
674 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
675 ESR_RXTX_RESET_CTRL_L);
676 if (err >= 0) {
677 *val = (err & 0xffff);
678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 ESR_RXTX_RESET_CTRL_H);
680 if (err >= 0) {
681 *val |= ((err & 0xffff) << 16);
682 err = 0;
683 }
684 }
685 return err;
686}
687
688static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
689{
690 int err;
691
692 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
693 ESR_RXTX_CTRL_L(chan), val & 0xffff);
694 if (!err)
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
696 ESR_RXTX_CTRL_H(chan), (val >> 16));
697 return err;
698}
699
700static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
701{
702 int err;
703
704 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
705 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
706 if (!err)
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
708 ESR_GLUE_CTRL0_H(chan), (val >> 16));
709 return err;
710}
711
712static int esr_reset(struct niu *np)
713{
f166400b 714 u32 uninitialized_var(reset);
a3138df9
DM		 715 int err;
716
717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
718 ESR_RXTX_RESET_CTRL_L, 0x0000);
719 if (err)
720 return err;
721 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 ESR_RXTX_RESET_CTRL_H, 0xffff);
723 if (err)
724 return err;
725 udelay(200);
726
727 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
728 ESR_RXTX_RESET_CTRL_L, 0xffff);
729 if (err)
730 return err;
731 udelay(200);
732
733 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
734 ESR_RXTX_RESET_CTRL_H, 0x0000);
735 if (err)
736 return err;
737 udelay(200);
738
739 err = esr_read_reset(np, &reset);
740 if (err)
741 return err;
742 if (reset != 0) {
f10a1f2e
JP		 743 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n",
744 np->port, reset);
a3138df9
DM		 745 return -ENODEV;
746 }
747
748 return 0;
749}
750
751static int serdes_init_10g(struct niu *np)
752{
753 struct niu_link_config *lp = &np->link_config;
754 unsigned long ctrl_reg, test_cfg_reg, i;
755 u64 ctrl_val, test_cfg_val, sig, mask, val;
756 int err;
757
758 switch (np->port) {
759 case 0:
760 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
761 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
762 break;
763 case 1:
764 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
765 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
766 break;
767
768 default:
769 return -EINVAL;
770 }
771 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
772 ENET_SERDES_CTRL_SDET_1 |
773 ENET_SERDES_CTRL_SDET_2 |
774 ENET_SERDES_CTRL_SDET_3 |
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
783 test_cfg_val = 0;
784
785 if (lp->loopback_mode == LOOPBACK_PHY) {
786 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
787 ENET_SERDES_TEST_MD_0_SHIFT) |
788 (ENET_TEST_MD_PAD_LOOPBACK <<
789 ENET_SERDES_TEST_MD_1_SHIFT) |
790 (ENET_TEST_MD_PAD_LOOPBACK <<
791 ENET_SERDES_TEST_MD_2_SHIFT) |
792 (ENET_TEST_MD_PAD_LOOPBACK <<
793 ENET_SERDES_TEST_MD_3_SHIFT));
794 }
795
796 nw64(ctrl_reg, ctrl_val);
797 nw64(test_cfg_reg, test_cfg_val);
798
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i = 0; i < 4; i++) {
801 u32 rxtx_ctrl, glue0;
802
803 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
804 if (err)
805 return err;
806 err = esr_read_glue0(np, i, &glue0);
807 if (err)
808 return err;
809
810 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
811 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
813
814 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
815 ESR_GLUE_CTRL0_THCNT |
816 ESR_GLUE_CTRL0_BLTIME);
817 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
820 (BLTIME_300_CYCLES <<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT));
822
823 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
824 if (err)
825 return err;
826 err = esr_write_glue0(np, i, glue0);
827 if (err)
828 return err;
829 }
830
831 err = esr_reset(np);
832 if (err)
833 return err;
834
835 sig = nr64(ESR_INT_SIGNALS);
836 switch (np->port) {
837 case 0:
838 mask = ESR_INT_SIGNALS_P0_BITS;
839 val = (ESR_INT_SRDY0_P0 |
840 ESR_INT_DET0_P0 |
841 ESR_INT_XSRDY_P0 |
842 ESR_INT_XDP_P0_CH3 |
843 ESR_INT_XDP_P0_CH2 |
844 ESR_INT_XDP_P0_CH1 |
845 ESR_INT_XDP_P0_CH0);
846 break;
847
848 case 1:
849 mask = ESR_INT_SIGNALS_P1_BITS;
850 val = (ESR_INT_SRDY0_P1 |
851 ESR_INT_DET0_P1 |
852 ESR_INT_XSRDY_P1 |
853 ESR_INT_XDP_P1_CH3 |
854 ESR_INT_XDP_P1_CH2 |
855 ESR_INT_XDP_P1_CH1 |
856 ESR_INT_XDP_P1_CH0);
857 break;
858
859 default:
860 return -EINVAL;
861 }
862
863 if ((sig & mask) != val) {
a5d6ab56
MW		 864 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
865 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
866 return 0;
867 }
f10a1f2e
JP		 868 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
869 np->port, (int)(sig & mask), (int)val);
a3138df9
DM		 870 return -ENODEV;
871 }
a5d6ab56
MW		 872 if (np->flags & NIU_FLAGS_HOTPLUG_PHY)
873 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
a3138df9
DM		 874 return 0;
875}
876
877static int serdes_init_1g(struct niu *np)
878{
879 u64 val;
880
881 val = nr64(ENET_SERDES_1_PLL_CFG);
882 val &= ~ENET_SERDES_PLL_FBDIV2;
883 switch (np->port) {
884 case 0:
885 val |= ENET_SERDES_PLL_HRATE0;
886 break;
887 case 1:
888 val |= ENET_SERDES_PLL_HRATE1;
889 break;
890 case 2:
891 val |= ENET_SERDES_PLL_HRATE2;
892 break;
893 case 3:
894 val |= ENET_SERDES_PLL_HRATE3;
895 break;
896 default:
897 return -EINVAL;
898 }
899 nw64(ENET_SERDES_1_PLL_CFG, val);
900
901 return 0;
902}
903
5fbd7e24
MW		 904static int serdes_init_1g_serdes(struct niu *np)
905{
906 struct niu_link_config *lp = &np->link_config;
907 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
908 u64 ctrl_val, test_cfg_val, sig, mask, val;
909 int err;
910 u64 reset_val, val_rd;
911
912 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
913 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 |
914 ENET_SERDES_PLL_FBDIV0;
915 switch (np->port) {
916 case 0:
917 reset_val = ENET_SERDES_RESET_0;
918 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
919 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
920 pll_cfg = ENET_SERDES_0_PLL_CFG;
921 break;
922 case 1:
923 reset_val = ENET_SERDES_RESET_1;
924 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
925 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
926 pll_cfg = ENET_SERDES_1_PLL_CFG;
927 break;
928
929 default:
930 return -EINVAL;
931 }
932 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
933 ENET_SERDES_CTRL_SDET_1 |
934 ENET_SERDES_CTRL_SDET_2 |
935 ENET_SERDES_CTRL_SDET_3 |
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
944 test_cfg_val = 0;
945
946 if (lp->loopback_mode == LOOPBACK_PHY) {
947 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
948 ENET_SERDES_TEST_MD_0_SHIFT) |
949 (ENET_TEST_MD_PAD_LOOPBACK <<
950 ENET_SERDES_TEST_MD_1_SHIFT) |
951 (ENET_TEST_MD_PAD_LOOPBACK <<
952 ENET_SERDES_TEST_MD_2_SHIFT) |
953 (ENET_TEST_MD_PAD_LOOPBACK <<
954 ENET_SERDES_TEST_MD_3_SHIFT));
955 }
956
957 nw64(ENET_SERDES_RESET, reset_val);
958 mdelay(20);
959 val_rd = nr64(ENET_SERDES_RESET);
960 val_rd &= ~reset_val;
961 nw64(pll_cfg, val);
962 nw64(ctrl_reg, ctrl_val);
963 nw64(test_cfg_reg, test_cfg_val);
964 nw64(ENET_SERDES_RESET, val_rd);
965 mdelay(2000);
966
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i = 0; i < 4; i++) {
969 u32 rxtx_ctrl, glue0;
970
971 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
972 if (err)
973 return err;
974 err = esr_read_glue0(np, i, &glue0);
975 if (err)
976 return err;
977
978 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
979 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
981
982 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
983 ESR_GLUE_CTRL0_THCNT |
984 ESR_GLUE_CTRL0_BLTIME);
985 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
988 (BLTIME_300_CYCLES <<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT));
990
991 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
992 if (err)
993 return err;
994 err = esr_write_glue0(np, i, glue0);
995 if (err)
996 return err;
997 }
998
999
1000 sig = nr64(ESR_INT_SIGNALS);
1001 switch (np->port) {
1002 case 0:
1003 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1004 mask = val;
1005 break;
1006
1007 case 1:
1008 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1009 mask = val;
1010 break;
1011
1012 default:
1013 return -EINVAL;
1014 }
1015
1016 if ((sig & mask) != val) {
f10a1f2e
JP		 1017 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np->port, (int)(sig & mask), (int)val);
5fbd7e24
MW		 1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023}
1024
1025static int link_status_1g_serdes(struct niu *np, int *link_up_p)
1026{
1027 struct niu_link_config *lp = &np->link_config;
1028 int link_up;
1029 u64 val;
1030 u16 current_speed;
1031 unsigned long flags;
1032 u8 current_duplex;
1033
1034 link_up = 0;
1035 current_speed = SPEED_INVALID;
1036 current_duplex = DUPLEX_INVALID;
1037
1038 spin_lock_irqsave(&np->lock, flags);
1039
1040 val = nr64_pcs(PCS_MII_STAT);
1041
1042 if (val & PCS_MII_STAT_LINK_STATUS) {
1043 link_up = 1;
1044 current_speed = SPEED_1000;
1045 current_duplex = DUPLEX_FULL;
1046 }
1047
1048 lp->active_speed = current_speed;
1049 lp->active_duplex = current_duplex;
1050 spin_unlock_irqrestore(&np->lock, flags);
1051
1052 *link_up_p = link_up;
1053 return 0;
1054}
1055
5fbd7e24
MW		 1056static int link_status_10g_serdes(struct niu *np, int *link_up_p)
1057{
1058 unsigned long flags;
1059 struct niu_link_config *lp = &np->link_config;
1060 int link_up = 0;
1061 int link_ok = 1;
1062 u64 val, val2;
1063 u16 current_speed;
1064 u8 current_duplex;
1065
1066 if (!(np->flags & NIU_FLAGS_10G))
1067 return link_status_1g_serdes(np, link_up_p);
1068
1069 current_speed = SPEED_INVALID;
1070 current_duplex = DUPLEX_INVALID;
1071 spin_lock_irqsave(&np->lock, flags);
1072
1073 val = nr64_xpcs(XPCS_STATUS(0));
1074 val2 = nr64_mac(XMAC_INTER2);
1075 if (val2 & 0x01000000)
1076 link_ok = 0;
1077
1078 if ((val & 0x1000ULL) && link_ok) {
1079 link_up = 1;
1080 current_speed = SPEED_10000;
1081 current_duplex = DUPLEX_FULL;
1082 }
1083 lp->active_speed = current_speed;
1084 lp->active_duplex = current_duplex;
1085 spin_unlock_irqrestore(&np->lock, flags);
1086 *link_up_p = link_up;
1087 return 0;
1088}
1089
38bb045d
CB		 1090static int link_status_mii(struct niu *np, int *link_up_p)
1091{
1092 struct niu_link_config *lp = &np->link_config;
1093 int err;
1094 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus;
1095 int supported, advertising, active_speed, active_duplex;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (unlikely(err < 0))
1099 return err;
1100 bmcr = err;
1101
1102 err = mii_read(np, np->phy_addr, MII_BMSR);
1103 if (unlikely(err < 0))
1104 return err;
1105 bmsr = err;
1106
1107 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1108 if (unlikely(err < 0))
1109 return err;
1110 advert = err;
1111
1112 err = mii_read(np, np->phy_addr, MII_LPA);
1113 if (unlikely(err < 0))
1114 return err;
1115 lpa = err;
1116
1117 if (likely(bmsr & BMSR_ESTATEN)) {
1118 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1119 if (unlikely(err < 0))
1120 return err;
1121 estatus = err;
1122
1123 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1124 if (unlikely(err < 0))
1125 return err;
1126 ctrl1000 = err;
1127
1128 err = mii_read(np, np->phy_addr, MII_STAT1000);
1129 if (unlikely(err < 0))
1130 return err;
1131 stat1000 = err;
1132 } else
1133 estatus = ctrl1000 = stat1000 = 0;
1134
1135 supported = 0;
1136 if (bmsr & BMSR_ANEGCAPABLE)
1137 supported |= SUPPORTED_Autoneg;
1138 if (bmsr & BMSR_10HALF)
1139 supported |= SUPPORTED_10baseT_Half;
1140 if (bmsr & BMSR_10FULL)
1141 supported |= SUPPORTED_10baseT_Full;
1142 if (bmsr & BMSR_100HALF)
1143 supported |= SUPPORTED_100baseT_Half;
1144 if (bmsr & BMSR_100FULL)
1145 supported |= SUPPORTED_100baseT_Full;
1146 if (estatus & ESTATUS_1000_THALF)
1147 supported |= SUPPORTED_1000baseT_Half;
1148 if (estatus & ESTATUS_1000_TFULL)
1149 supported |= SUPPORTED_1000baseT_Full;
1150 lp->supported = supported;
1151
1152 advertising = 0;
1153 if (advert & ADVERTISE_10HALF)
1154 advertising |= ADVERTISED_10baseT_Half;
1155 if (advert & ADVERTISE_10FULL)
1156 advertising |= ADVERTISED_10baseT_Full;
1157 if (advert & ADVERTISE_100HALF)
1158 advertising |= ADVERTISED_100baseT_Half;
1159 if (advert & ADVERTISE_100FULL)
1160 advertising |= ADVERTISED_100baseT_Full;
1161 if (ctrl1000 & ADVERTISE_1000HALF)
1162 advertising |= ADVERTISED_1000baseT_Half;
1163 if (ctrl1000 & ADVERTISE_1000FULL)
1164 advertising |= ADVERTISED_1000baseT_Full;
1165
1166 if (bmcr & BMCR_ANENABLE) {
1167 int neg, neg1000;
1168
1169 lp->active_autoneg = 1;
1170 advertising |= ADVERTISED_Autoneg;
1171
1172 neg = advert & lpa;
1173 neg1000 = (ctrl1000 << 2) & stat1000;
1174
1175 if (neg1000 & (LPA_1000FULL | LPA_1000HALF))
1176 active_speed = SPEED_1000;
1177 else if (neg & LPA_100)
1178 active_speed = SPEED_100;
1179 else if (neg & (LPA_10HALF | LPA_10FULL))
1180 active_speed = SPEED_10;
1181 else
1182 active_speed = SPEED_INVALID;
1183
1184 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX))
1185 active_duplex = DUPLEX_FULL;
1186 else if (active_speed != SPEED_INVALID)
1187 active_duplex = DUPLEX_HALF;
1188 else
1189 active_duplex = DUPLEX_INVALID;
1190 } else {
1191 lp->active_autoneg = 0;
1192
1193 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100))
1194 active_speed = SPEED_1000;
1195 else if (bmcr & BMCR_SPEED100)
1196 active_speed = SPEED_100;
1197 else
1198 active_speed = SPEED_10;
1199
1200 if (bmcr & BMCR_FULLDPLX)
1201 active_duplex = DUPLEX_FULL;
1202 else
1203 active_duplex = DUPLEX_HALF;
1204 }
1205
1206 lp->active_advertising = advertising;
1207 lp->active_speed = active_speed;
1208 lp->active_duplex = active_duplex;
1209 *link_up_p = !!(bmsr & BMSR_LSTATUS);
1210
1211 return 0;
1212}
1213
5fbd7e24
MW		 1214static int link_status_1g_rgmii(struct niu *np, int *link_up_p)
1215{
1216 struct niu_link_config *lp = &np->link_config;
1217 u16 current_speed, bmsr;
1218 unsigned long flags;
1219 u8 current_duplex;
1220 int err, link_up;
1221
1222 link_up = 0;
1223 current_speed = SPEED_INVALID;
1224 current_duplex = DUPLEX_INVALID;
1225
1226 spin_lock_irqsave(&np->lock, flags);
1227
1228 err = -EINVAL;
1229
1230 err = mii_read(np, np->phy_addr, MII_BMSR);
1231 if (err < 0)
1232 goto out;
1233
1234 bmsr = err;
1235 if (bmsr & BMSR_LSTATUS) {
1236 u16 adv, lpa, common, estat;
1237
1238 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1239 if (err < 0)
1240 goto out;
1241 adv = err;
1242
1243 err = mii_read(np, np->phy_addr, MII_LPA);
1244 if (err < 0)
1245 goto out;
1246 lpa = err;
1247
1248 common = adv & lpa;
1249
1250 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1251 if (err < 0)
1252 goto out;
1253 estat = err;
1254 link_up = 1;
1255 current_speed = SPEED_1000;
1256 current_duplex = DUPLEX_FULL;
1257
1258 }
1259 lp->active_speed = current_speed;
1260 lp->active_duplex = current_duplex;
1261 err = 0;
1262
1263out:
1264 spin_unlock_irqrestore(&np->lock, flags);
1265
1266 *link_up_p = link_up;
1267 return err;
1268}
1269
38bb045d
CB		 1270static int link_status_1g(struct niu *np, int *link_up_p)
1271{
1272 struct niu_link_config *lp = &np->link_config;
1273 unsigned long flags;
1274 int err;
1275
1276 spin_lock_irqsave(&np->lock, flags);
1277
1278 err = link_status_mii(np, link_up_p);
1279 lp->supported |= SUPPORTED_TP;
1280 lp->active_advertising |= ADVERTISED_TP;
1281
1282 spin_unlock_irqrestore(&np->lock, flags);
1283 return err;
1284}
1285
a3138df9
DM		 1286static int bcm8704_reset(struct niu *np)
1287{
1288 int err, limit;
1289
1290 err = mdio_read(np, np->phy_addr,
1291 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
9c5cd670 1292 if (err < 0 || err == 0xffff)
a3138df9
DM		 1293 return err;
1294 err |= BMCR_RESET;
1295 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1296 MII_BMCR, err);
1297 if (err)
1298 return err;
1299
1300 limit = 1000;
1301 while (--limit >= 0) {
1302 err = mdio_read(np, np->phy_addr,
1303 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
1304 if (err < 0)
1305 return err;
1306 if (!(err & BMCR_RESET))
1307 break;
1308 }
1309 if (limit < 0) {
f10a1f2e
JP		 1310 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np->port, (err & 0xffff));
a3138df9
DM		 1312 return -ENODEV;
1313 }
1314 return 0;
1315}
1316
1317/* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1319 */
1320static int bcm8704_user_dev3_readback(struct niu *np, int reg)
1321{
1322 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1323 if (err < 0)
1324 return err;
1325 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1326 if (err < 0)
1327 return err;
1328 return 0;
1329}
1330
a5d6ab56
MW		 1331static int bcm8706_init_user_dev3(struct niu *np)
1332{
1333 int err;
1334
1335
1336 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1337 BCM8704_USER_OPT_DIGITAL_CTRL);
1338 if (err < 0)
1339 return err;
1340 err &= ~USER_ODIG_CTRL_GPIOS;
1341 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1342 err |= USER_ODIG_CTRL_RESV2;
1343 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1344 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1345 if (err)
1346 return err;
1347
1348 mdelay(1000);
1349
1350 return 0;
1351}
1352
a3138df9
DM		 1353static int bcm8704_init_user_dev3(struct niu *np)
1354{
1355 int err;
1356
1357 err = mdio_write(np, np->phy_addr,
1358 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
1359 (USER_CONTROL_OPTXRST_LVL |
1360 USER_CONTROL_OPBIASFLT_LVL |
1361 USER_CONTROL_OBTMPFLT_LVL |
1362 USER_CONTROL_OPPRFLT_LVL |
1363 USER_CONTROL_OPTXFLT_LVL |
1364 USER_CONTROL_OPRXLOS_LVL |
1365 USER_CONTROL_OPRXFLT_LVL |
1366 USER_CONTROL_OPTXON_LVL |
1367 (0x3f << USER_CONTROL_RES1_SHIFT)));
1368 if (err)
1369 return err;
1370
1371 err = mdio_write(np, np->phy_addr,
1372 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
1373 (USER_PMD_TX_CTL_XFP_CLKEN |
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN));
1377 if (err)
1378 return err;
1379
1380 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1381 if (err)
1382 return err;
1383 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1384 if (err)
1385 return err;
1386
1387 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1388 BCM8704_USER_OPT_DIGITAL_CTRL);
1389 if (err < 0)
1390 return err;
1391 err &= ~USER_ODIG_CTRL_GPIOS;
1392 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1393 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1394 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1395 if (err)
1396 return err;
1397
1398 mdelay(1000);
1399
1400 return 0;
1401}
1402
b0de8e40
ML		 1403static int mrvl88x2011_act_led(struct niu *np, int val)
1404{
1405 int err;
1406
1407 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1408 MRVL88X2011_LED_8_TO_11_CTL);
1409 if (err < 0)
1410 return err;
1411
1412 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1413 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1414
1415 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1416 MRVL88X2011_LED_8_TO_11_CTL, err);
1417}
1418
1419static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
1420{
1421 int err;
1422
1423 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1424 MRVL88X2011_LED_BLINK_CTL);
1425 if (err >= 0) {
1426 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1427 err |= (rate << 4);
1428
1429 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1430 MRVL88X2011_LED_BLINK_CTL, err);
1431 }
1432
1433 return err;
1434}
1435
1436static int xcvr_init_10g_mrvl88x2011(struct niu *np)
1437{
1438 int err;
1439
1440 /* Set LED functions */
1441 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1442 if (err)
1443 return err;
1444
1445 /* led activity */
1446 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1447 if (err)
1448 return err;
1449
1450 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1451 MRVL88X2011_GENERAL_CTL);
1452 if (err < 0)
1453 return err;
1454
1455 err |= MRVL88X2011_ENA_XFPREFCLK;
1456
1457 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1458 MRVL88X2011_GENERAL_CTL, err);
1459 if (err < 0)
1460 return err;
1461
1462 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1463 MRVL88X2011_PMA_PMD_CTL_1);
1464 if (err < 0)
1465 return err;
1466
1467 if (np->link_config.loopback_mode == LOOPBACK_MAC)
1468 err |= MRVL88X2011_LOOPBACK;
1469 else
1470 err &= ~MRVL88X2011_LOOPBACK;
1471
1472 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1473 MRVL88X2011_PMA_PMD_CTL_1, err);
1474 if (err < 0)
1475 return err;
1476
1477 /* Enable PMD */
1478 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1479 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
1480}
1481
a5d6ab56
MW		 1482
1483static int xcvr_diag_bcm870x(struct niu *np)
a3138df9 1484{
a3138df9 1485 u16 analog_stat0, tx_alarm_status;
a5d6ab56 1486 int err = 0;
a3138df9
DM		 1487
1488#if 1
1489 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1490 MII_STAT1000);
1491 if (err < 0)
1492 return err;
f10a1f2e 1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
a3138df9
DM		 1494
1495 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1496 if (err < 0)
1497 return err;
f10a1f2e 1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
a3138df9
DM		 1499
1500 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1501 MII_NWAYTEST);
1502 if (err < 0)
1503 return err;
f10a1f2e 1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
a3138df9
DM		 1505#endif
1506
1507 /* XXX dig this out it might not be so useful XXX */
1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1509 BCM8704_USER_ANALOG_STATUS0);
1510 if (err < 0)
1511 return err;
1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1513 BCM8704_USER_ANALOG_STATUS0);
1514 if (err < 0)
1515 return err;
1516 analog_stat0 = err;
1517
1518 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1519 BCM8704_USER_TX_ALARM_STATUS);
1520 if (err < 0)
1521 return err;
1522 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1523 BCM8704_USER_TX_ALARM_STATUS);
1524 if (err < 0)
1525 return err;
1526 tx_alarm_status = err;
1527
1528 if (analog_stat0 != 0x03fc) {
1529 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
f10a1f2e
JP		 1530 pr_info("Port %u cable not connected or bad cable\n",
1531 np->port);
a3138df9 1532 } else if (analog_stat0 == 0x639c) {
f10a1f2e
JP		 1533 pr_info("Port %u optical module is bad or missing\n",
1534 np->port);
a3138df9
DM		 1535 }
1536 }
1537
1538 return 0;
1539}
1540
a5d6ab56
MW		 1541static int xcvr_10g_set_lb_bcm870x(struct niu *np)
1542{
1543 struct niu_link_config *lp = &np->link_config;
1544 int err;
1545
1546 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1547 MII_BMCR);
1548 if (err < 0)
1549 return err;
1550
1551 err &= ~BMCR_LOOPBACK;
1552
1553 if (lp->loopback_mode == LOOPBACK_MAC)
1554 err |= BMCR_LOOPBACK;
1555
1556 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1557 MII_BMCR, err);
1558 if (err)
1559 return err;
1560
1561 return 0;
1562}
1563
1564static int xcvr_init_10g_bcm8706(struct niu *np)
1565{
1566 int err = 0;
1567 u64 val;
1568
1569 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) &&
1570 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0)
1571 return err;
1572
1573 val = nr64_mac(XMAC_CONFIG);
1574 val &= ~XMAC_CONFIG_LED_POLARITY;
1575 val |= XMAC_CONFIG_FORCE_LED_ON;
1576 nw64_mac(XMAC_CONFIG, val);
1577
1578 val = nr64(MIF_CONFIG);
1579 val |= MIF_CONFIG_INDIRECT_MODE;
1580 nw64(MIF_CONFIG, val);
1581
1582 err = bcm8704_reset(np);
1583 if (err)
1584 return err;
1585
1586 err = xcvr_10g_set_lb_bcm870x(np);
1587 if (err)
1588 return err;
1589
1590 err = bcm8706_init_user_dev3(np);
1591 if (err)
1592 return err;
1593
1594 err = xcvr_diag_bcm870x(np);
1595 if (err)
1596 return err;
1597
1598 return 0;
1599}
1600
1601static int xcvr_init_10g_bcm8704(struct niu *np)
1602{
1603 int err;
1604
1605 err = bcm8704_reset(np);
1606 if (err)
1607 return err;
1608
1609 err = bcm8704_init_user_dev3(np);
1610 if (err)
1611 return err;
1612
1613 err = xcvr_10g_set_lb_bcm870x(np);
1614 if (err)
1615 return err;
1616
1617 err = xcvr_diag_bcm870x(np);
1618 if (err)
1619 return err;
1620
1621 return 0;
1622}
1623
b0de8e40
ML		 1624static int xcvr_init_10g(struct niu *np)
1625{
1626 int phy_id, err;
1627 u64 val;
1628
1629 val = nr64_mac(XMAC_CONFIG);
1630 val &= ~XMAC_CONFIG_LED_POLARITY;
1631 val |= XMAC_CONFIG_FORCE_LED_ON;
1632 nw64_mac(XMAC_CONFIG, val);
1633
1634 /* XXX shared resource, lock parent XXX */
1635 val = nr64(MIF_CONFIG);
1636 val |= MIF_CONFIG_INDIRECT_MODE;
1637 nw64(MIF_CONFIG, val);
1638
1639 phy_id = phy_decode(np->parent->port_phy, np->port);
1640 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1641
1642 /* handle different phy types */
1643 switch (phy_id & NIU_PHY_ID_MASK) {
1644 case NIU_PHY_ID_MRVL88X2011:
1645 err = xcvr_init_10g_mrvl88x2011(np);
1646 break;
1647
1648 default: /* bcom 8704 */
1649 err = xcvr_init_10g_bcm8704(np);
1650 break;
1651 }
1652
1653 return 0;
1654}
1655
a3138df9
DM		 1656static int mii_reset(struct niu *np)
1657{
1658 int limit, err;
1659
1660 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1661 if (err)
1662 return err;
1663
1664 limit = 1000;
1665 while (--limit >= 0) {
1666 udelay(500);
1667 err = mii_read(np, np->phy_addr, MII_BMCR);
1668 if (err < 0)
1669 return err;
1670 if (!(err & BMCR_RESET))
1671 break;
1672 }
1673 if (limit < 0) {
f10a1f2e
JP		 1674 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n",
1675 np->port, err);
a3138df9
DM		 1676 return -ENODEV;
1677 }
1678
1679 return 0;
1680}
1681
5fbd7e24
MW		 1682static int xcvr_init_1g_rgmii(struct niu *np)
1683{
1684 int err;
1685 u64 val;
1686 u16 bmcr, bmsr, estat;
1687
1688 val = nr64(MIF_CONFIG);
1689 val &= ~MIF_CONFIG_INDIRECT_MODE;
1690 nw64(MIF_CONFIG, val);
1691
1692 err = mii_reset(np);
1693 if (err)
1694 return err;
1695
1696 err = mii_read(np, np->phy_addr, MII_BMSR);
1697 if (err < 0)
1698 return err;
1699 bmsr = err;
1700
1701 estat = 0;
1702 if (bmsr & BMSR_ESTATEN) {
1703 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1704 if (err < 0)
1705 return err;
1706 estat = err;
1707 }
1708
1709 bmcr = 0;
1710 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1711 if (err)
1712 return err;
1713
1714 if (bmsr & BMSR_ESTATEN) {
1715 u16 ctrl1000 = 0;
1716
1717 if (estat & ESTATUS_1000_TFULL)
1718 ctrl1000 |= ADVERTISE_1000FULL;
1719 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1720 if (err)
1721 return err;
1722 }
1723
1724 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX);
1725
1726 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1727 if (err)
1728 return err;
1729
1730 err = mii_read(np, np->phy_addr, MII_BMCR);
1731 if (err < 0)
1732 return err;
1733 bmcr = mii_read(np, np->phy_addr, MII_BMCR);
1734
1735 err = mii_read(np, np->phy_addr, MII_BMSR);
1736 if (err < 0)
1737 return err;
1738
1739 return 0;
1740}
1741
a3138df9
DM		 1742static int mii_init_common(struct niu *np)
1743{
1744 struct niu_link_config *lp = &np->link_config;
1745 u16 bmcr, bmsr, adv, estat;
1746 int err;
1747
1748 err = mii_reset(np);
1749 if (err)
1750 return err;
1751
1752 err = mii_read(np, np->phy_addr, MII_BMSR);
1753 if (err < 0)
1754 return err;
1755 bmsr = err;
1756
1757 estat = 0;
1758 if (bmsr & BMSR_ESTATEN) {
1759 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1760 if (err < 0)
1761 return err;
1762 estat = err;
1763 }
1764
1765 bmcr = 0;
1766 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1767 if (err)
1768 return err;
1769
1770 if (lp->loopback_mode == LOOPBACK_MAC) {
1771 bmcr |= BMCR_LOOPBACK;
1772 if (lp->active_speed == SPEED_1000)
1773 bmcr |= BMCR_SPEED1000;
1774 if (lp->active_duplex == DUPLEX_FULL)
1775 bmcr |= BMCR_FULLDPLX;
1776 }
1777
1778 if (lp->loopback_mode == LOOPBACK_PHY) {
1779 u16 aux;
1780
1781 aux = (BCM5464R_AUX_CTL_EXT_LB |
1782 BCM5464R_AUX_CTL_WRITE_1);
1783 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1784 if (err)
1785 return err;
1786 }
1787
38bb045d
CB		 1788 if (lp->autoneg) {
1789 u16 ctrl1000;
1790
1791 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1792 if ((bmsr & BMSR_10HALF) &&
1793 (lp->advertising & ADVERTISED_10baseT_Half))
1794 adv |= ADVERTISE_10HALF;
1795 if ((bmsr & BMSR_10FULL) &&
1796 (lp->advertising & ADVERTISED_10baseT_Full))
1797 adv |= ADVERTISE_10FULL;
1798 if ((bmsr & BMSR_100HALF) &&
1799 (lp->advertising & ADVERTISED_100baseT_Half))
1800 adv |= ADVERTISE_100HALF;
1801 if ((bmsr & BMSR_100FULL) &&
1802 (lp->advertising & ADVERTISED_100baseT_Full))
1803 adv |= ADVERTISE_100FULL;
1804 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
a3138df9
DM		 1805 if (err)
1806 return err;
38bb045d
CB		 1807
1808 if (likely(bmsr & BMSR_ESTATEN)) {
1809 ctrl1000 = 0;
1810 if ((estat & ESTATUS_1000_THALF) &&
1811 (lp->advertising & ADVERTISED_1000baseT_Half))
1812 ctrl1000 |= ADVERTISE_1000HALF;
1813 if ((estat & ESTATUS_1000_TFULL) &&
1814 (lp->advertising & ADVERTISED_1000baseT_Full))
1815 ctrl1000 |= ADVERTISE_1000FULL;
1816 err = mii_write(np, np->phy_addr,
1817 MII_CTRL1000, ctrl1000);
1818 if (err)
1819 return err;
1820 }
1821
1822 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1823 } else {
1824 /* !lp->autoneg */
1825 int fulldpx;
1826
1827 if (lp->duplex == DUPLEX_FULL) {
1828 bmcr |= BMCR_FULLDPLX;
1829 fulldpx = 1;
1830 } else if (lp->duplex == DUPLEX_HALF)
1831 fulldpx = 0;
1832 else
1833 return -EINVAL;
1834
1835 if (lp->speed == SPEED_1000) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) ||
1839 (!fulldpx && !(estat & ESTATUS_1000_THALF)))
1840 return -EINVAL;
1841 bmcr |= BMCR_SPEED1000;
1842 } else if (lp->speed == SPEED_100) {
1843 if ((fulldpx && !(bmsr & BMSR_100FULL)) ||
1844 (!fulldpx && !(bmsr & BMSR_100HALF)))
1845 return -EINVAL;
1846 bmcr |= BMCR_SPEED100;
1847 } else if (lp->speed == SPEED_10) {
1848 if ((fulldpx && !(bmsr & BMSR_10FULL)) ||
1849 (!fulldpx && !(bmsr & BMSR_10HALF)))
1850 return -EINVAL;
1851 } else
1852 return -EINVAL;
a3138df9 1853 }
a3138df9
DM		 1854
1855 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1856 if (err)
1857 return err;
1858
38bb045d 1859#if 0
a3138df9
DM		 1860 err = mii_read(np, np->phy_addr, MII_BMCR);
1861 if (err < 0)
1862 return err;
38bb045d
CB		 1863 bmcr = err;
1864
a3138df9
DM		 1865 err = mii_read(np, np->phy_addr, MII_BMSR);
1866 if (err < 0)
1867 return err;
38bb045d
CB		 1868 bmsr = err;
1869
f10a1f2e 1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
a3138df9
DM		 1871 np->port, bmcr, bmsr);
1872#endif
1873
1874 return 0;
1875}
1876
1877static int xcvr_init_1g(struct niu *np)
1878{
1879 u64 val;
1880
1881 /* XXX shared resource, lock parent XXX */
1882 val = nr64(MIF_CONFIG);
1883 val &= ~MIF_CONFIG_INDIRECT_MODE;
1884 nw64(MIF_CONFIG, val);
1885
1886 return mii_init_common(np);
1887}
1888
1889static int niu_xcvr_init(struct niu *np)
1890{
1891 const struct niu_phy_ops *ops = np->phy_ops;
1892 int err;
1893
1894 err = 0;
1895 if (ops->xcvr_init)
1896 err = ops->xcvr_init(np);
1897
1898 return err;
1899}
1900
1901static int niu_serdes_init(struct niu *np)
1902{
1903 const struct niu_phy_ops *ops = np->phy_ops;
1904 int err;
1905
1906 err = 0;
1907 if (ops->serdes_init)
1908 err = ops->serdes_init(np);
1909
1910 return err;
1911}
1912
1913static void niu_init_xif(struct niu *);
0c3b091b 1914static void niu_handle_led(struct niu *, int status);
a3138df9
DM		 1915
1916static int niu_link_status_common(struct niu *np, int link_up)
1917{
1918 struct niu_link_config *lp = &np->link_config;
1919 struct net_device *dev = np->dev;
1920 unsigned long flags;
1921
1922 if (!netif_carrier_ok(dev) && link_up) {
f10a1f2e
JP		 1923 netif_info(np, link, dev, "Link is up at %s, %s duplex\n",
1924 lp->active_speed == SPEED_10000 ? "10Gb/sec" :
1925 lp->active_speed == SPEED_1000 ? "1Gb/sec" :
1926 lp->active_speed == SPEED_100 ? "100Mbit/sec" :
1927 "10Mbit/sec",
1928 lp->active_duplex == DUPLEX_FULL ? "full" : "half");
a3138df9
DM		 1929
1930 spin_lock_irqsave(&np->lock, flags);
1931 niu_init_xif(np);
0c3b091b 1932 niu_handle_led(np, 1);
a3138df9
DM		 1933 spin_unlock_irqrestore(&np->lock, flags);
1934
1935 netif_carrier_on(dev);
1936 } else if (netif_carrier_ok(dev) && !link_up) {
f10a1f2e 1937 netif_warn(np, link, dev, "Link is down\n");
0c3b091b
ML		 1938 spin_lock_irqsave(&np->lock, flags);
1939 niu_handle_led(np, 0);
1940 spin_unlock_irqrestore(&np->lock, flags);
a3138df9
DM		 1941 netif_carrier_off(dev);
1942 }
1943
1944 return 0;
1945}
1946
b0de8e40 1947static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
a3138df9 1948{
b0de8e40 1949 int err, link_up, pma_status, pcs_status;
a3138df9
DM		 1950
1951 link_up = 0;
1952
b0de8e40
ML		 1953 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1954 MRVL88X2011_10G_PMD_STATUS_2);
1955 if (err < 0)
1956 goto out;
a3138df9 1957
b0de8e40
ML		 1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1960 MRVL88X2011_PMA_PMD_STATUS_1);
1961 if (err < 0)
1962 goto out;
1963
1964 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1965
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1968 MRVL88X2011_PMA_PMD_STATUS_1);
1969 if (err < 0)
1970 goto out;
1971
1972 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1973 MRVL88X2011_PMA_PMD_STATUS_1);
1974 if (err < 0)
1975 goto out;
1976
1977 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1978
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1981 MRVL88X2011_10G_XGXS_LANE_STAT);
1982 if (err < 0)
a3138df9
DM		 1983 goto out;
1984
b0de8e40
ML		 1985 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1986 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1987 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1988 0x800))
1989 link_up = (pma_status && pcs_status) ? 1 : 0;
1990
1991 np->link_config.active_speed = SPEED_10000;
1992 np->link_config.active_duplex = DUPLEX_FULL;
1993 err = 0;
1994out:
1995 mrvl88x2011_act_led(np, (link_up ?
1996 MRVL88X2011_LED_CTL_PCS_ACT :
1997 MRVL88X2011_LED_CTL_OFF));
1998
1999 *link_up_p = link_up;
2000 return err;
2001}
2002
a5d6ab56
MW		 2003static int link_status_10g_bcm8706(struct niu *np, int *link_up_p)
2004{
2005 int err, link_up;
2006 link_up = 0;
2007
2008 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2009 BCM8704_PMD_RCV_SIGDET);
9c5cd670 2010 if (err < 0 || err == 0xffff)
a5d6ab56
MW		 2011 goto out;
2012 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2013 err = 0;
2014 goto out;
2015 }
2016
2017 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2018 BCM8704_PCS_10G_R_STATUS);
2019 if (err < 0)
2020 goto out;
2021
2022 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2023 err = 0;
2024 goto out;
2025 }
2026
2027 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2028 BCM8704_PHYXS_XGXS_LANE_STAT);
2029 if (err < 0)
2030 goto out;
2031 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2032 PHYXS_XGXS_LANE_STAT_MAGIC |
2033 PHYXS_XGXS_LANE_STAT_PATTEST |
2034 PHYXS_XGXS_LANE_STAT_LANE3 |
2035 PHYXS_XGXS_LANE_STAT_LANE2 |
2036 PHYXS_XGXS_LANE_STAT_LANE1 |
2037 PHYXS_XGXS_LANE_STAT_LANE0)) {
2038 err = 0;
2039 np->link_config.active_speed = SPEED_INVALID;
2040 np->link_config.active_duplex = DUPLEX_INVALID;
2041 goto out;
2042 }
2043
2044 link_up = 1;
2045 np->link_config.active_speed = SPEED_10000;
2046 np->link_config.active_duplex = DUPLEX_FULL;
2047 err = 0;
2048
2049out:
2050 *link_up_p = link_up;
a5d6ab56
MW		 2051 return err;
2052}
2053
b0de8e40
ML		 2054static int link_status_10g_bcom(struct niu *np, int *link_up_p)
2055{
2056 int err, link_up;
2057
2058 link_up = 0;
2059
a3138df9
DM		 2060 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2061 BCM8704_PMD_RCV_SIGDET);
2062 if (err < 0)
2063 goto out;
2064 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2065 err = 0;
2066 goto out;
2067 }
2068
2069 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2070 BCM8704_PCS_10G_R_STATUS);
2071 if (err < 0)
2072 goto out;
2073 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2074 err = 0;
2075 goto out;
2076 }
2077
2078 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2079 BCM8704_PHYXS_XGXS_LANE_STAT);
2080 if (err < 0)
2081 goto out;
2082
2083 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2084 PHYXS_XGXS_LANE_STAT_MAGIC |
2085 PHYXS_XGXS_LANE_STAT_LANE3 |
2086 PHYXS_XGXS_LANE_STAT_LANE2 |
2087 PHYXS_XGXS_LANE_STAT_LANE1 |
2088 PHYXS_XGXS_LANE_STAT_LANE0)) {
2089 err = 0;
2090 goto out;
2091 }
2092
2093 link_up = 1;
2094 np->link_config.active_speed = SPEED_10000;
2095 np->link_config.active_duplex = DUPLEX_FULL;
2096 err = 0;
2097
2098out:
b0de8e40
ML		 2099 *link_up_p = link_up;
2100 return err;
2101}
2102
2103static int link_status_10g(struct niu *np, int *link_up_p)
2104{
2105 unsigned long flags;
2106 int err = -EINVAL;
2107
2108 spin_lock_irqsave(&np->lock, flags);
2109
2110 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2111 int phy_id;
2112
2113 phy_id = phy_decode(np->parent->port_phy, np->port);
2114 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2115
2116 /* handle different phy types */
2117 switch (phy_id & NIU_PHY_ID_MASK) {
2118 case NIU_PHY_ID_MRVL88X2011:
2119 err = link_status_10g_mrvl(np, link_up_p);
2120 break;
2121
2122 default: /* bcom 8704 */
2123 err = link_status_10g_bcom(np, link_up_p);
2124 break;
2125 }
2126 }
2127
a3138df9
DM		 2128 spin_unlock_irqrestore(&np->lock, flags);
2129
a3138df9
DM		 2130 return err;
2131}
2132
a5d6ab56
MW		 2133static int niu_10g_phy_present(struct niu *np)
2134{
2135 u64 sig, mask, val;
2136
2137 sig = nr64(ESR_INT_SIGNALS);
2138 switch (np->port) {
2139 case 0:
2140 mask = ESR_INT_SIGNALS_P0_BITS;
2141 val = (ESR_INT_SRDY0_P0 |
2142 ESR_INT_DET0_P0 |
2143 ESR_INT_XSRDY_P0 |
2144 ESR_INT_XDP_P0_CH3 |
2145 ESR_INT_XDP_P0_CH2 |
2146 ESR_INT_XDP_P0_CH1 |
2147 ESR_INT_XDP_P0_CH0);
2148 break;
2149
2150 case 1:
2151 mask = ESR_INT_SIGNALS_P1_BITS;
2152 val = (ESR_INT_SRDY0_P1 |
2153 ESR_INT_DET0_P1 |
2154 ESR_INT_XSRDY_P1 |
2155 ESR_INT_XDP_P1_CH3 |
2156 ESR_INT_XDP_P1_CH2 |
2157 ESR_INT_XDP_P1_CH1 |
2158 ESR_INT_XDP_P1_CH0);
2159 break;
2160
2161 default:
2162 return 0;
2163 }
2164
2165 if ((sig & mask) != val)
2166 return 0;
2167 return 1;
2168}
2169
2170static int link_status_10g_hotplug(struct niu *np, int *link_up_p)
2171{
2172 unsigned long flags;
2173 int err = 0;
2174 int phy_present;
2175 int phy_present_prev;
2176
2177 spin_lock_irqsave(&np->lock, flags);
2178
2179 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
2180 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ?
2181 1 : 0;
2182 phy_present = niu_10g_phy_present(np);
2183 if (phy_present != phy_present_prev) {
2184 /* state change */
2185 if (phy_present) {
9c5cd670 2186 /* A NEM was just plugged in */
a5d6ab56
MW		 2187 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2188 if (np->phy_ops->xcvr_init)
2189 err = np->phy_ops->xcvr_init(np);
2190 if (err) {
9c5cd670
TC		 2191 err = mdio_read(np, np->phy_addr,
2192 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
2193 if (err == 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2195 goto out;
2196 }
a5d6ab56
MW		 2197 /* debounce */
2198 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2199 }
2200 } else {
2201 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT;
2202 *link_up_p = 0;
f10a1f2e
JP		 2203 netif_warn(np, link, np->dev,
2204 "Hotplug PHY Removed\n");
a5d6ab56
MW		 2205 }
2206 }
9c5cd670
TC		 2207out:
2208 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) {
a5d6ab56 2209 err = link_status_10g_bcm8706(np, link_up_p);
9c5cd670
TC		 2210 if (err == 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2212 *link_up_p = 1;
2213 np->link_config.active_speed = SPEED_10000;
2214 np->link_config.active_duplex = DUPLEX_FULL;
2215 }
2216 }
a5d6ab56
MW		 2217 }
2218
2219 spin_unlock_irqrestore(&np->lock, flags);
2220
9c5cd670 2221 return 0;
a5d6ab56
MW		 2222}
2223
a3138df9
DM		 2224static int niu_link_status(struct niu *np, int *link_up_p)
2225{
2226 const struct niu_phy_ops *ops = np->phy_ops;
2227 int err;
2228
2229 err = 0;
2230 if (ops->link_status)
2231 err = ops->link_status(np, link_up_p);
2232
2233 return err;
2234}
2235
2236static void niu_timer(unsigned long __opaque)
2237{
2238 struct niu *np = (struct niu *) __opaque;
2239 unsigned long off;
2240 int err, link_up;
2241
2242 err = niu_link_status(np, &link_up);
2243 if (!err)
2244 niu_link_status_common(np, link_up);
2245
2246 if (netif_carrier_ok(np->dev))
2247 off = 5 * HZ;
2248 else
2249 off = 1 * HZ;
2250 np->timer.expires = jiffies + off;
2251
2252 add_timer(&np->timer);
2253}
2254
5fbd7e24
MW		 2255static const struct niu_phy_ops phy_ops_10g_serdes = {
2256 .serdes_init = serdes_init_10g_serdes,
2257 .link_status = link_status_10g_serdes,
2258};
2259
e3e081e1
SB		 2260static const struct niu_phy_ops phy_ops_10g_serdes_niu = {
2261 .serdes_init = serdes_init_niu_10g_serdes,
2262 .link_status = link_status_10g_serdes,
2263};
2264
2265static const struct niu_phy_ops phy_ops_1g_serdes_niu = {
2266 .serdes_init = serdes_init_niu_1g_serdes,
2267 .link_status = link_status_1g_serdes,
2268};
2269
5fbd7e24
MW		 2270static const struct niu_phy_ops phy_ops_1g_rgmii = {
2271 .xcvr_init = xcvr_init_1g_rgmii,
2272 .link_status = link_status_1g_rgmii,
2273};
2274
a3138df9 2275static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
e3e081e1 2276 .serdes_init = serdes_init_niu_10g_fiber,
a3138df9
DM		 2277 .xcvr_init = xcvr_init_10g,
2278 .link_status = link_status_10g,
2279};
2280
2281static const struct niu_phy_ops phy_ops_10g_fiber = {
2282 .serdes_init = serdes_init_10g,
2283 .xcvr_init = xcvr_init_10g,
2284 .link_status = link_status_10g,
2285};
2286
a5d6ab56
MW		 2287static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = {
2288 .serdes_init = serdes_init_10g,
2289 .xcvr_init = xcvr_init_10g_bcm8706,
2290 .link_status = link_status_10g_hotplug,
2291};
2292
9c5cd670
TC		 2293static const struct niu_phy_ops phy_ops_niu_10g_hotplug = {
2294 .serdes_init = serdes_init_niu_10g_fiber,
2295 .xcvr_init = xcvr_init_10g_bcm8706,
2296 .link_status = link_status_10g_hotplug,
2297};
2298
a3138df9
DM		 2299static const struct niu_phy_ops phy_ops_10g_copper = {
2300 .serdes_init = serdes_init_10g,
2301 .link_status = link_status_10g, /* XXX */
2302};
2303
2304static const struct niu_phy_ops phy_ops_1g_fiber = {
2305 .serdes_init = serdes_init_1g,
2306 .xcvr_init = xcvr_init_1g,
2307 .link_status = link_status_1g,
2308};
2309
2310static const struct niu_phy_ops phy_ops_1g_copper = {
2311 .xcvr_init = xcvr_init_1g,
2312 .link_status = link_status_1g,
2313};
2314
2315struct niu_phy_template {
2316 const struct niu_phy_ops *ops;
2317 u32 phy_addr_base;
2318};
2319
e3e081e1 2320static const struct niu_phy_template phy_template_niu_10g_fiber = {
a3138df9
DM		 2321 .ops = &phy_ops_10g_fiber_niu,
2322 .phy_addr_base = 16,
2323};
2324
e3e081e1
SB		 2325static const struct niu_phy_template phy_template_niu_10g_serdes = {
2326 .ops = &phy_ops_10g_serdes_niu,
2327 .phy_addr_base = 0,
2328};
2329
2330static const struct niu_phy_template phy_template_niu_1g_serdes = {
2331 .ops = &phy_ops_1g_serdes_niu,
2332 .phy_addr_base = 0,
2333};
2334
a3138df9
DM		 2335static const struct niu_phy_template phy_template_10g_fiber = {
2336 .ops = &phy_ops_10g_fiber,
2337 .phy_addr_base = 8,
2338};
2339
a5d6ab56
MW		 2340static const struct niu_phy_template phy_template_10g_fiber_hotplug = {
2341 .ops = &phy_ops_10g_fiber_hotplug,
2342 .phy_addr_base = 8,
2343};
2344
9c5cd670
TC		 2345static const struct niu_phy_template phy_template_niu_10g_hotplug = {
2346 .ops = &phy_ops_niu_10g_hotplug,
2347 .phy_addr_base = 8,
2348};
2349
a3138df9
DM		 2350static const struct niu_phy_template phy_template_10g_copper = {
2351 .ops = &phy_ops_10g_copper,
2352 .phy_addr_base = 10,
2353};
2354
2355static const struct niu_phy_template phy_template_1g_fiber = {
2356 .ops = &phy_ops_1g_fiber,
2357 .phy_addr_base = 0,
2358};
2359
2360static const struct niu_phy_template phy_template_1g_copper = {
2361 .ops = &phy_ops_1g_copper,
2362 .phy_addr_base = 0,
2363};
2364
5fbd7e24
MW		 2365static const struct niu_phy_template phy_template_1g_rgmii = {
2366 .ops = &phy_ops_1g_rgmii,
2367 .phy_addr_base = 0,
2368};
2369
2370static const struct niu_phy_template phy_template_10g_serdes = {
2371 .ops = &phy_ops_10g_serdes,
2372 .phy_addr_base = 0,
2373};
2374
2375static int niu_atca_port_num[4] = {
2376 0, 0, 11, 10
2377};
2378
2379static int serdes_init_10g_serdes(struct niu *np)
2380{
2381 struct niu_link_config *lp = &np->link_config;
2382 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2383 u64 ctrl_val, test_cfg_val, sig, mask, val;
5fbd7e24
MW		 2384 u64 reset_val;
2385
2386 switch (np->port) {
2387 case 0:
2388 reset_val = ENET_SERDES_RESET_0;
2389 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
2390 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
2391 pll_cfg = ENET_SERDES_0_PLL_CFG;
2392 break;
2393 case 1:
2394 reset_val = ENET_SERDES_RESET_1;
2395 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
2396 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
2397 pll_cfg = ENET_SERDES_1_PLL_CFG;
2398 break;
2399
2400 default:
2401 return -EINVAL;
2402 }
2403 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
2404 ENET_SERDES_CTRL_SDET_1 |
2405 ENET_SERDES_CTRL_SDET_2 |
2406 ENET_SERDES_CTRL_SDET_3 |
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
2415 test_cfg_val = 0;
2416
2417 if (lp->loopback_mode == LOOPBACK_PHY) {
2418 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
2419 ENET_SERDES_TEST_MD_0_SHIFT) |
2420 (ENET_TEST_MD_PAD_LOOPBACK <<
2421 ENET_SERDES_TEST_MD_1_SHIFT) |
2422 (ENET_TEST_MD_PAD_LOOPBACK <<
2423 ENET_SERDES_TEST_MD_2_SHIFT) |
2424 (ENET_TEST_MD_PAD_LOOPBACK <<
2425 ENET_SERDES_TEST_MD_3_SHIFT));
2426 }
2427
2428 esr_reset(np);
2429 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2430 nw64(ctrl_reg, ctrl_val);
2431 nw64(test_cfg_reg, test_cfg_val);
2432
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i = 0; i < 4; i++) {
2435 u32 rxtx_ctrl, glue0;
7c34eb89 2436 int err;
5fbd7e24
MW		 2437
2438 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2439 if (err)
2440 return err;
2441 err = esr_read_glue0(np, i, &glue0);
2442 if (err)
2443 return err;
2444
2445 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
2446 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
2448
2449 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
2450 ESR_GLUE_CTRL0_THCNT |
2451 ESR_GLUE_CTRL0_BLTIME);
2452 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
2455 (BLTIME_300_CYCLES <<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT));
2457
2458 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2459 if (err)
2460 return err;
2461 err = esr_write_glue0(np, i, glue0);
2462 if (err)
2463 return err;
2464 }
2465
2466
2467 sig = nr64(ESR_INT_SIGNALS);
2468 switch (np->port) {
2469 case 0:
2470 mask = ESR_INT_SIGNALS_P0_BITS;
2471 val = (ESR_INT_SRDY0_P0 |
2472 ESR_INT_DET0_P0 |
2473 ESR_INT_XSRDY_P0 |
2474 ESR_INT_XDP_P0_CH3 |
2475 ESR_INT_XDP_P0_CH2 |
2476 ESR_INT_XDP_P0_CH1 |
2477 ESR_INT_XDP_P0_CH0);
2478 break;
2479
2480 case 1:
2481 mask = ESR_INT_SIGNALS_P1_BITS;
2482 val = (ESR_INT_SRDY0_P1 |
2483 ESR_INT_DET0_P1 |
2484 ESR_INT_XSRDY_P1 |
2485 ESR_INT_XDP_P1_CH3 |
2486 ESR_INT_XDP_P1_CH2 |
2487 ESR_INT_XDP_P1_CH1 |
2488 ESR_INT_XDP_P1_CH0);
2489 break;
2490
2491 default:
2492 return -EINVAL;
2493 }
2494
2495 if ((sig & mask) != val) {
2496 int err;
2497 err = serdes_init_1g_serdes(np);
2498 if (!err) {
2499 np->flags &= ~NIU_FLAGS_10G;
2500 np->mac_xcvr = MAC_XCVR_PCS;
2501 } else {
f10a1f2e
JP		 2502 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n",
2503 np->port);
5fbd7e24
MW		 2504 return -ENODEV;
2505 }
2506 }
2507
2508 return 0;
2509}
2510
a3138df9
DM		 2511static int niu_determine_phy_disposition(struct niu *np)
2512{
2513 struct niu_parent *parent = np->parent;
2514 u8 plat_type = parent->plat_type;
2515 const struct niu_phy_template *tp;
2516 u32 phy_addr_off = 0;
2517
2518 if (plat_type == PLAT_TYPE_NIU) {
e3e081e1
SB		 2519 switch (np->flags &
2520 (NIU_FLAGS_10G |
2521 NIU_FLAGS_FIBER |
2522 NIU_FLAGS_XCVR_SERDES)) {
2523 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2524 /* 10G Serdes */
2525 tp = &phy_template_niu_10g_serdes;
2526 break;
2527 case NIU_FLAGS_XCVR_SERDES:
2528 /* 1G Serdes */
2529 tp = &phy_template_niu_1g_serdes;
2530 break;
2531 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2532 /* 10G Fiber */
2533 default:
9c5cd670
TC		 2534 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2535 tp = &phy_template_niu_10g_hotplug;
2536 if (np->port == 0)
2537 phy_addr_off = 8;
2538 if (np->port == 1)
2539 phy_addr_off = 12;
2540 } else {
2541 tp = &phy_template_niu_10g_fiber;
2542 phy_addr_off += np->port;
2543 }
e3e081e1
SB		 2544 break;
2545 }
a3138df9 2546 } else {
5fbd7e24
MW		 2547 switch (np->flags &
2548 (NIU_FLAGS_10G |
2549 NIU_FLAGS_FIBER |
2550 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 2551 case 0:
2552 /* 1G copper */
2553 tp = &phy_template_1g_copper;
2554 if (plat_type == PLAT_TYPE_VF_P0)
2555 phy_addr_off = 10;
2556 else if (plat_type == PLAT_TYPE_VF_P1)
2557 phy_addr_off = 26;
2558
2559 phy_addr_off += (np->port ^ 0x3);
2560 break;
2561
2562 case NIU_FLAGS_10G:
2563 /* 10G copper */
e0d8496a 2564 tp = &phy_template_10g_copper;
a3138df9
DM		 2565 break;
2566
2567 case NIU_FLAGS_FIBER:
2568 /* 1G fiber */
2569 tp = &phy_template_1g_fiber;
2570 break;
2571
2572 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
2573 /* 10G fiber */
2574 tp = &phy_template_10g_fiber;
2575 if (plat_type == PLAT_TYPE_VF_P0 ||
2576 plat_type == PLAT_TYPE_VF_P1)
2577 phy_addr_off = 8;
2578 phy_addr_off += np->port;
a5d6ab56
MW		 2579 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) {
2580 tp = &phy_template_10g_fiber_hotplug;
2581 if (np->port == 0)
2582 phy_addr_off = 8;
2583 if (np->port == 1)
2584 phy_addr_off = 12;
2585 }
a3138df9
DM		 2586 break;
2587
5fbd7e24
MW		 2588 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
2589 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
2590 case NIU_FLAGS_XCVR_SERDES:
2591 switch(np->port) {
2592 case 0:
2593 case 1:
2594 tp = &phy_template_10g_serdes;
2595 break;
2596 case 2:
2597 case 3:
2598 tp = &phy_template_1g_rgmii;
2599 break;
2600 default:
2601 return -EINVAL;
2602 break;
2603 }
2604 phy_addr_off = niu_atca_port_num[np->port];
2605 break;
2606
a3138df9
DM		 2607 default:
2608 return -EINVAL;
2609 }
2610 }
2611
2612 np->phy_ops = tp->ops;
2613 np->phy_addr = tp->phy_addr_base + phy_addr_off;
2614
2615 return 0;
2616}
2617
2618static int niu_init_link(struct niu *np)
2619{
2620 struct niu_parent *parent = np->parent;
2621 int err, ignore;
2622
2623 if (parent->plat_type == PLAT_TYPE_NIU) {
2624 err = niu_xcvr_init(np);
2625 if (err)
2626 return err;
2627 msleep(200);
2628 }
2629 err = niu_serdes_init(np);
9c5cd670 2630 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2631 return err;
2632 msleep(200);
2633 err = niu_xcvr_init(np);
9c5cd670 2634 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
a3138df9
DM		 2635 niu_link_status(np, &ignore);
2636 return 0;
2637}
2638
2639static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
2640{
2641 u16 reg0 = addr[4] << 8 | addr[5];
2642 u16 reg1 = addr[2] << 8 | addr[3];
2643 u16 reg2 = addr[0] << 8 | addr[1];
2644
2645 if (np->flags & NIU_FLAGS_XMAC) {
2646 nw64_mac(XMAC_ADDR0, reg0);
2647 nw64_mac(XMAC_ADDR1, reg1);
2648 nw64_mac(XMAC_ADDR2, reg2);
2649 } else {
2650 nw64_mac(BMAC_ADDR0, reg0);
2651 nw64_mac(BMAC_ADDR1, reg1);
2652 nw64_mac(BMAC_ADDR2, reg2);
2653 }
2654}
2655
2656static int niu_num_alt_addr(struct niu *np)
2657{
2658 if (np->flags & NIU_FLAGS_XMAC)
2659 return XMAC_NUM_ALT_ADDR;
2660 else
2661 return BMAC_NUM_ALT_ADDR;
2662}
2663
2664static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
2665{
2666 u16 reg0 = addr[4] << 8 | addr[5];
2667 u16 reg1 = addr[2] << 8 | addr[3];
2668 u16 reg2 = addr[0] << 8 | addr[1];
2669
2670 if (index >= niu_num_alt_addr(np))
2671 return -EINVAL;
2672
2673 if (np->flags & NIU_FLAGS_XMAC) {
2674 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
2675 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
2676 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
2677 } else {
2678 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
2679 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
2680 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
2681 }
2682
2683 return 0;
2684}
2685
2686static int niu_enable_alt_mac(struct niu *np, int index, int on)
2687{
2688 unsigned long reg;
2689 u64 val, mask;
2690
2691 if (index >= niu_num_alt_addr(np))
2692 return -EINVAL;
2693
fa907895 2694 if (np->flags & NIU_FLAGS_XMAC) {
a3138df9 2695 reg = XMAC_ADDR_CMPEN;
fa907895
MW		 2696 mask = 1 << index;
2697 } else {
a3138df9 2698 reg = BMAC_ADDR_CMPEN;
fa907895
MW		 2699 mask = 1 << (index + 1);
2700 }
a3138df9
DM		 2701
2702 val = nr64_mac(reg);
2703 if (on)
2704 val |= mask;
2705 else
2706 val &= ~mask;
2707 nw64_mac(reg, val);
2708
2709 return 0;
2710}
2711
2712static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
2713 int num, int mac_pref)
2714{
2715 u64 val = nr64_mac(reg);
2716 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2717 val |= num;
2718 if (mac_pref)
2719 val |= HOST_INFO_MPR;
2720 nw64_mac(reg, val);
2721}
2722
2723static int __set_rdc_table_num(struct niu *np,
2724 int xmac_index, int bmac_index,
2725 int rdc_table_num, int mac_pref)
2726{
2727 unsigned long reg;
2728
2729 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
2730 return -EINVAL;
2731 if (np->flags & NIU_FLAGS_XMAC)
2732 reg = XMAC_HOST_INFO(xmac_index);
2733 else
2734 reg = BMAC_HOST_INFO(bmac_index);
2735 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
2736 return 0;
2737}
2738
2739static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
2740 int mac_pref)
2741{
2742 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
2743}
2744
2745static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
2746 int mac_pref)
2747{
2748 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
2749}
2750
2751static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
2752 int table_num, int mac_pref)
2753{
2754 if (idx >= niu_num_alt_addr(np))
2755 return -EINVAL;
2756 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
2757}
2758
2759static u64 vlan_entry_set_parity(u64 reg_val)
2760{
2761 u64 port01_mask;
2762 u64 port23_mask;
2763
2764 port01_mask = 0x00ff;
2765 port23_mask = 0xff00;
2766
2767 if (hweight64(reg_val & port01_mask) & 1)
2768 reg_val |= ENET_VLAN_TBL_PARITY0;
2769 else
2770 reg_val &= ~ENET_VLAN_TBL_PARITY0;
2771
2772 if (hweight64(reg_val & port23_mask) & 1)
2773 reg_val |= ENET_VLAN_TBL_PARITY1;
2774 else
2775 reg_val &= ~ENET_VLAN_TBL_PARITY1;
2776
2777 return reg_val;
2778}
2779
2780static void vlan_tbl_write(struct niu *np, unsigned long index,
2781 int port, int vpr, int rdc_table)
2782{
2783 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2784
2785 reg_val &= ~((ENET_VLAN_TBL_VPR |
2786 ENET_VLAN_TBL_VLANRDCTBLN) <<
2787 ENET_VLAN_TBL_SHIFT(port));
2788 if (vpr)
2789 reg_val |= (ENET_VLAN_TBL_VPR <<
2790 ENET_VLAN_TBL_SHIFT(port));
2791 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
2792
2793 reg_val = vlan_entry_set_parity(reg_val);
2794
2795 nw64(ENET_VLAN_TBL(index), reg_val);
2796}
2797
2798static void vlan_tbl_clear(struct niu *np)
2799{
2800 int i;
2801
2802 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
2803 nw64(ENET_VLAN_TBL(i), 0);
2804}
2805
2806static int tcam_wait_bit(struct niu *np, u64 bit)
2807{
2808 int limit = 1000;
2809
2810 while (--limit > 0) {
2811 if (nr64(TCAM_CTL) & bit)
2812 break;
2813 udelay(1);
2814 }
d2a928e4 2815 if (limit <= 0)
a3138df9
DM		 2816 return -ENODEV;
2817
2818 return 0;
2819}
2820
2821static int tcam_flush(struct niu *np, int index)
2822{
2823 nw64(TCAM_KEY_0, 0x00);
2824 nw64(TCAM_KEY_MASK_0, 0xff);
2825 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2826
2827 return tcam_wait_bit(np, TCAM_CTL_STAT);
2828}
2829
2830#if 0
2831static int tcam_read(struct niu *np, int index,
2832 u64 *key, u64 *mask)
2833{
2834 int err;
2835
2836 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2837 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2838 if (!err) {
2839 key[0] = nr64(TCAM_KEY_0);
2840 key[1] = nr64(TCAM_KEY_1);
2841 key[2] = nr64(TCAM_KEY_2);
2842 key[3] = nr64(TCAM_KEY_3);
2843 mask[0] = nr64(TCAM_KEY_MASK_0);
2844 mask[1] = nr64(TCAM_KEY_MASK_1);
2845 mask[2] = nr64(TCAM_KEY_MASK_2);
2846 mask[3] = nr64(TCAM_KEY_MASK_3);
2847 }
2848 return err;
2849}
2850#endif
2851
2852static int tcam_write(struct niu *np, int index,
2853 u64 *key, u64 *mask)
2854{
2855 nw64(TCAM_KEY_0, key[0]);
2856 nw64(TCAM_KEY_1, key[1]);
2857 nw64(TCAM_KEY_2, key[2]);
2858 nw64(TCAM_KEY_3, key[3]);
2859 nw64(TCAM_KEY_MASK_0, mask[0]);
2860 nw64(TCAM_KEY_MASK_1, mask[1]);
2861 nw64(TCAM_KEY_MASK_2, mask[2]);
2862 nw64(TCAM_KEY_MASK_3, mask[3]);
2863 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2864
2865 return tcam_wait_bit(np, TCAM_CTL_STAT);
2866}
2867
2868#if 0
2869static int tcam_assoc_read(struct niu *np, int index, u64 *data)
2870{
2871 int err;
2872
2873 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2874 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2875 if (!err)
2876 *data = nr64(TCAM_KEY_1);
2877
2878 return err;
2879}
2880#endif
2881
2882static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
2883{
2884 nw64(TCAM_KEY_1, assoc_data);
2885 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2886
2887 return tcam_wait_bit(np, TCAM_CTL_STAT);
2888}
2889
2890static void tcam_enable(struct niu *np, int on)
2891{
2892 u64 val = nr64(FFLP_CFG_1);
2893
2894 if (on)
2895 val &= ~FFLP_CFG_1_TCAM_DIS;
2896 else
2897 val |= FFLP_CFG_1_TCAM_DIS;
2898 nw64(FFLP_CFG_1, val);
2899}
2900
2901static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
2902{
2903 u64 val = nr64(FFLP_CFG_1);
2904
2905 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2906 FFLP_CFG_1_CAMLAT |
2907 FFLP_CFG_1_CAMRATIO);
2908 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2909 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2910 nw64(FFLP_CFG_1, val);
2911
2912 val = nr64(FFLP_CFG_1);
2913 val |= FFLP_CFG_1_FFLPINITDONE;
2914 nw64(FFLP_CFG_1, val);
2915}
2916
2917static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
2918 int on)
2919{
2920 unsigned long reg;
2921 u64 val;
2922
2923 if (class < CLASS_CODE_ETHERTYPE1 ||
2924 class > CLASS_CODE_ETHERTYPE2)
2925 return -EINVAL;
2926
2927 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2928 val = nr64(reg);
2929 if (on)
2930 val |= L2_CLS_VLD;
2931 else
2932 val &= ~L2_CLS_VLD;
2933 nw64(reg, val);
2934
2935 return 0;
2936}
2937
2938#if 0
2939static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
2940 u64 ether_type)
2941{
2942 unsigned long reg;
2943 u64 val;
2944
2945 if (class < CLASS_CODE_ETHERTYPE1 ||
2946 class > CLASS_CODE_ETHERTYPE2 ||
2947 (ether_type & ~(u64)0xffff) != 0)
2948 return -EINVAL;
2949
2950 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
2951 val = nr64(reg);
2952 val &= ~L2_CLS_ETYPE;
2953 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2954 nw64(reg, val);
2955
2956 return 0;
2957}
2958#endif
2959
2960static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
2961 int on)
2962{
2963 unsigned long reg;
2964 u64 val;
2965
2966 if (class < CLASS_CODE_USER_PROG1 ||
2967 class > CLASS_CODE_USER_PROG4)
2968 return -EINVAL;
2969
2970 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2971 val = nr64(reg);
2972 if (on)
2973 val |= L3_CLS_VALID;
2974 else
2975 val &= ~L3_CLS_VALID;
2976 nw64(reg, val);
2977
2978 return 0;
2979}
2980
a3138df9
DM		 2981static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
2982 int ipv6, u64 protocol_id,
2983 u64 tos_mask, u64 tos_val)
2984{
2985 unsigned long reg;
2986 u64 val;
2987
2988 if (class < CLASS_CODE_USER_PROG1 ||
2989 class > CLASS_CODE_USER_PROG4 ||
2990 (protocol_id & ~(u64)0xff) != 0 ||
2991 (tos_mask & ~(u64)0xff) != 0 ||
2992 (tos_val & ~(u64)0xff) != 0)
2993 return -EINVAL;
2994
2995 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
2996 val = nr64(reg);
2997 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2998 L3_CLS_TOSMASK | L3_CLS_TOS);
2999 if (ipv6)
3000 val |= L3_CLS_IPVER;
3001 val |= (protocol_id << L3_CLS_PID_SHIFT);
3002 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
3003 val |= (tos_val << L3_CLS_TOS_SHIFT);
3004 nw64(reg, val);
3005
3006 return 0;
3007}
a3138df9
DM		 3008
3009static int tcam_early_init(struct niu *np)
3010{
3011 unsigned long i;
3012 int err;
3013
3014 tcam_enable(np, 0);
3015 tcam_set_lat_and_ratio(np,
3016 DEFAULT_TCAM_LATENCY,
3017 DEFAULT_TCAM_ACCESS_RATIO);
3018 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
3019 err = tcam_user_eth_class_enable(np, i, 0);
3020 if (err)
3021 return err;
3022 }
3023 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
3024 err = tcam_user_ip_class_enable(np, i, 0);
3025 if (err)
3026 return err;
3027 }
3028
3029 return 0;
3030}
3031
3032static int tcam_flush_all(struct niu *np)
3033{
3034 unsigned long i;
3035
3036 for (i = 0; i < np->parent->tcam_num_entries; i++) {
3037 int err = tcam_flush(np, i);
3038 if (err)
3039 return err;
3040 }
3041 return 0;
3042}
3043
3044static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
3045{
807540ba 3046 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0);
a3138df9
DM		 3047}
3048
3049#if 0
3050static int hash_read(struct niu *np, unsigned long partition,
3051 unsigned long index, unsigned long num_entries,
3052 u64 *data)
3053{
3054 u64 val = hash_addr_regval(index, num_entries);
3055 unsigned long i;
3056
3057 if (partition >= FCRAM_NUM_PARTITIONS ||
3058 index + num_entries > FCRAM_SIZE)
3059 return -EINVAL;
3060
3061 nw64(HASH_TBL_ADDR(partition), val);
3062 for (i = 0; i < num_entries; i++)
3063 data[i] = nr64(HASH_TBL_DATA(partition));
3064
3065 return 0;
3066}
3067#endif
3068
3069static int hash_write(struct niu *np, unsigned long partition,
3070 unsigned long index, unsigned long num_entries,
3071 u64 *data)
3072{
3073 u64 val = hash_addr_regval(index, num_entries);
3074 unsigned long i;
3075
3076 if (partition >= FCRAM_NUM_PARTITIONS ||
3077 index + (num_entries * 8) > FCRAM_SIZE)
3078 return -EINVAL;
3079
3080 nw64(HASH_TBL_ADDR(partition), val);
3081 for (i = 0; i < num_entries; i++)
3082 nw64(HASH_TBL_DATA(partition), data[i]);
3083
3084 return 0;
3085}
3086
3087static void fflp_reset(struct niu *np)
3088{
3089 u64 val;
3090
3091 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3092 udelay(10);
3093 nw64(FFLP_CFG_1, 0);
3094
3095 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3096 nw64(FFLP_CFG_1, val);
3097}
3098
3099static void fflp_set_timings(struct niu *np)
3100{
3101 u64 val = nr64(FFLP_CFG_1);
3102
3103 val &= ~FFLP_CFG_1_FFLPINITDONE;
3104 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3105 nw64(FFLP_CFG_1, val);
3106
3107 val = nr64(FFLP_CFG_1);
3108 val |= FFLP_CFG_1_FFLPINITDONE;
3109 nw64(FFLP_CFG_1, val);
3110
3111 val = nr64(FCRAM_REF_TMR);
3112 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3113 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3114 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3115 nw64(FCRAM_REF_TMR, val);
3116}
3117
3118static int fflp_set_partition(struct niu *np, u64 partition,
3119 u64 mask, u64 base, int enable)
3120{
3121 unsigned long reg;
3122 u64 val;
3123
3124 if (partition >= FCRAM_NUM_PARTITIONS ||
3125 (mask & ~(u64)0x1f) != 0 ||
3126 (base & ~(u64)0x1f) != 0)
3127 return -EINVAL;
3128
3129 reg = FLW_PRT_SEL(partition);
3130
3131 val = nr64(reg);
3132 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3133 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3134 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3135 if (enable)
3136 val |= FLW_PRT_SEL_EXT;
3137 nw64(reg, val);
3138
3139 return 0;
3140}
3141
3142static int fflp_disable_all_partitions(struct niu *np)
3143{
3144 unsigned long i;
3145
3146 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
3147 int err = fflp_set_partition(np, 0, 0, 0, 0);
3148 if (err)
3149 return err;
3150 }
3151 return 0;
3152}
3153
3154static void fflp_llcsnap_enable(struct niu *np, int on)
3155{
3156 u64 val = nr64(FFLP_CFG_1);
3157
3158 if (on)
3159 val |= FFLP_CFG_1_LLCSNAP;
3160 else
3161 val &= ~FFLP_CFG_1_LLCSNAP;
3162 nw64(FFLP_CFG_1, val);
3163}
3164
3165static void fflp_errors_enable(struct niu *np, int on)
3166{
3167 u64 val = nr64(FFLP_CFG_1);
3168
3169 if (on)
3170 val &= ~FFLP_CFG_1_ERRORDIS;
3171 else
3172 val |= FFLP_CFG_1_ERRORDIS;
3173 nw64(FFLP_CFG_1, val);
3174}
3175
3176static int fflp_hash_clear(struct niu *np)
3177{
3178 struct fcram_hash_ipv4 ent;
3179 unsigned long i;
3180
3181 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3182 memset(&ent, 0, sizeof(ent));
3183 ent.header = HASH_HEADER_EXT;
3184
3185 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
3186 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3187 if (err)
3188 return err;
3189 }
3190 return 0;
3191}
3192
3193static int fflp_early_init(struct niu *np)
3194{
3195 struct niu_parent *parent;
3196 unsigned long flags;
3197 int err;
3198
3199 niu_lock_parent(np, flags);
3200
3201 parent = np->parent;
3202 err = 0;
3203 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
a3138df9
DM		 3204 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3205 fflp_reset(np);
3206 fflp_set_timings(np);
3207 err = fflp_disable_all_partitions(np);
3208 if (err) {
f10a1f2e
JP		 3209 netif_printk(np, probe, KERN_DEBUG, np->dev,
3210 "fflp_disable_all_partitions failed, err=%d\n",
3211 err);
a3138df9
DM		 3212 goto out;
3213 }
3214 }
3215
3216 err = tcam_early_init(np);
3217 if (err) {
f10a1f2e
JP		 3218 netif_printk(np, probe, KERN_DEBUG, np->dev,
3219 "tcam_early_init failed, err=%d\n", err);
a3138df9
DM		 3220 goto out;
3221 }
3222 fflp_llcsnap_enable(np, 1);
3223 fflp_errors_enable(np, 0);
3224 nw64(H1POLY, 0);
3225 nw64(H2POLY, 0);
3226
3227 err = tcam_flush_all(np);
3228 if (err) {
f10a1f2e
JP		 3229 netif_printk(np, probe, KERN_DEBUG, np->dev,
3230 "tcam_flush_all failed, err=%d\n", err);
a3138df9
DM		 3231 goto out;
3232 }
3233 if (np->parent->plat_type != PLAT_TYPE_NIU) {
3234 err = fflp_hash_clear(np);
3235 if (err) {
f10a1f2e
JP		 3236 netif_printk(np, probe, KERN_DEBUG, np->dev,
3237 "fflp_hash_clear failed, err=%d\n",
3238 err);
a3138df9
DM		 3239 goto out;
3240 }
3241 }
3242
3243 vlan_tbl_clear(np);
3244
a3138df9
DM		 3245 parent->flags |= PARENT_FLGS_CLS_HWINIT;
3246 }
3247out:
3248 niu_unlock_parent(np, flags);
3249 return err;
3250}
3251
3252static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
3253{
3254 if (class_code < CLASS_CODE_USER_PROG1 ||
3255 class_code > CLASS_CODE_SCTP_IPV6)
3256 return -EINVAL;
3257
3258 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3259 return 0;
3260}
3261
3262static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
3263{
3264 if (class_code < CLASS_CODE_USER_PROG1 ||
3265 class_code > CLASS_CODE_SCTP_IPV6)
3266 return -EINVAL;
3267
3268 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3269 return 0;
3270}
3271
2d96cf8c
SB		 3272/* Entries for the ports are interleaved in the TCAM */
3273static u16 tcam_get_index(struct niu *np, u16 idx)
3274{
3275 /* One entry reserved for IP fragment rule */
3276 if (idx >= (np->clas.tcam_sz - 1))
3277 idx = 0;
807540ba 3278 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports);
2d96cf8c
SB		 3279}
3280
3281static u16 tcam_get_size(struct niu *np)
3282{
3283 /* One entry reserved for IP fragment rule */
3284 return np->clas.tcam_sz - 1;
3285}
3286
3287static u16 tcam_get_valid_entry_cnt(struct niu *np)
3288{
3289 /* One entry reserved for IP fragment rule */
3290 return np->clas.tcam_valid_entries - 1;
3291}
3292
a3138df9
DM		 3293static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
3294 u32 offset, u32 size)
3295{
3296 int i = skb_shinfo(skb)->nr_frags;
3297 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3298
3299 frag->page = page;
3300 frag->page_offset = offset;
3301 frag->size = size;
3302
3303 skb->len += size;
3304 skb->data_len += size;
3305 skb->truesize += size;
3306
3307 skb_shinfo(skb)->nr_frags = i + 1;
3308}
3309
3310static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
3311{
3312 a >>= PAGE_SHIFT;
3313 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
3314
807540ba 3315 return a & (MAX_RBR_RING_SIZE - 1);
a3138df9
DM		 3316}
3317
3318static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
3319 struct page ***link)
3320{
3321 unsigned int h = niu_hash_rxaddr(rp, addr);
3322 struct page *p, **pp;
3323
3324 addr &= PAGE_MASK;
3325 pp = &rp->rxhash[h];
3326 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
3327 if (p->index == addr) {
3328 *link = pp;
a0387169 3329 goto found;
a3138df9
DM		 3330 }
3331 }
a0387169 3332 BUG();
a3138df9 3333
a0387169 3334found:
a3138df9
DM		 3335 return p;
3336}
3337
3338static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
3339{
3340 unsigned int h = niu_hash_rxaddr(rp, base);
3341
3342 page->index = base;
3343 page->mapping = (struct address_space *) rp->rxhash[h];
3344 rp->rxhash[h] = page;
3345}
3346
3347static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
3348 gfp_t mask, int start_index)
3349{
3350 struct page *page;
3351 u64 addr;
3352 int i;
3353
3354 page = alloc_page(mask);
3355 if (!page)
3356 return -ENOMEM;
3357
3358 addr = np->ops->map_page(np->device, page, 0,
3359 PAGE_SIZE, DMA_FROM_DEVICE);
3360
3361 niu_hash_page(rp, page, addr);
3362 if (rp->rbr_blocks_per_page > 1)
3363 atomic_add(rp->rbr_blocks_per_page - 1,
3364 &compound_head(page)->_count);
3365
3366 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
3367 __le32 *rbr = &rp->rbr[start_index + i];
3368
3369 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
3370 addr += rp->rbr_block_size;
3371 }
3372
3373 return 0;
3374}
3375
3376static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3377{
3378 int index = rp->rbr_index;
3379
3380 rp->rbr_pending++;
3381 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
3382 int err = niu_rbr_add_page(np, rp, mask, index);
3383
3384 if (unlikely(err)) {
3385 rp->rbr_pending--;
3386 return;
3387 }
3388
3389 rp->rbr_index += rp->rbr_blocks_per_page;
3390 BUG_ON(rp->rbr_index > rp->rbr_table_size);
3391 if (rp->rbr_index == rp->rbr_table_size)
3392 rp->rbr_index = 0;
3393
3394 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
3395 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3396 rp->rbr_pending = 0;
3397 }
3398 }
3399}
3400
3401static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
3402{
3403 unsigned int index = rp->rcr_index;
3404 int num_rcr = 0;
3405
3406 rp->rx_dropped++;
3407 while (1) {
3408 struct page *page, **link;
3409 u64 addr, val;
3410 u32 rcr_size;
3411
3412 num_rcr++;
3413
3414 val = le64_to_cpup(&rp->rcr[index]);
3415 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3416 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3417 page = niu_find_rxpage(rp, addr, &link);
3418
3419 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3420 RCR_ENTRY_PKTBUFSZ_SHIFT];
3421 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
3422 *link = (struct page *) page->mapping;
3423 np->ops->unmap_page(np->device, page->index,
3424 PAGE_SIZE, DMA_FROM_DEVICE);
3425 page->index = 0;
3426 page->mapping = NULL;
3427 __free_page(page);
3428 rp->rbr_refill_pending++;
3429 }
3430
3431 index = NEXT_RCR(rp, index);
3432 if (!(val & RCR_ENTRY_MULTI))
3433 break;
3434
3435 }
3436 rp->rcr_index = index;
3437
3438 return num_rcr;
3439}
3440
4099e012
DM		 3441static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np,
3442 struct rx_ring_info *rp)
a3138df9
DM		 3443{
3444 unsigned int index = rp->rcr_index;
3cfa856d 3445 struct rx_pkt_hdr1 *rh;
a3138df9
DM		 3446 struct sk_buff *skb;
3447 int len, num_rcr;
3448
3449 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
3450 if (unlikely(!skb))
3451 return niu_rx_pkt_ignore(np, rp);
3452
3453 num_rcr = 0;
3454 while (1) {
3455 struct page *page, **link;
3456 u32 rcr_size, append_size;
3457 u64 addr, val, off;
3458
3459 num_rcr++;
3460
3461 val = le64_to_cpup(&rp->rcr[index]);
3462
3463 len = (val & RCR_ENTRY_L2_LEN) >>
3464 RCR_ENTRY_L2_LEN_SHIFT;
3465 len -= ETH_FCS_LEN;
3466
3467 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3468 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
3469 page = niu_find_rxpage(rp, addr, &link);
3470
3471 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3472 RCR_ENTRY_PKTBUFSZ_SHIFT];
3473
3474 off = addr & ~PAGE_MASK;
3475 append_size = rcr_size;
3476 if (num_rcr == 1) {
3477 int ptype;
3478
a3138df9
DM		 3479 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3480 if ((ptype == RCR_PKT_TYPE_TCP ||
3481 ptype == RCR_PKT_TYPE_UDP) &&
3482 !(val & (RCR_ENTRY_NOPORT |
3483 RCR_ENTRY_ERROR)))
3484 skb->ip_summed = CHECKSUM_UNNECESSARY;
3485 else
bc8acf2c 3486 skb_checksum_none_assert(skb);
3cfa856d 3487 } else if (!(val & RCR_ENTRY_MULTI))
a3138df9
DM		 3488 append_size = len - skb->len;
3489
3490 niu_rx_skb_append(skb, page, off, append_size);
3491 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
3492 *link = (struct page *) page->mapping;
3493 np->ops->unmap_page(np->device, page->index,
3494 PAGE_SIZE, DMA_FROM_DEVICE);
3495 page->index = 0;
3496 page->mapping = NULL;
3497 rp->rbr_refill_pending++;
3498 } else
3499 get_page(page);
3500
3501 index = NEXT_RCR(rp, index);
3502 if (!(val & RCR_ENTRY_MULTI))
3503 break;
3504
3505 }
3506 rp->rcr_index = index;
3507
3cfa856d
DM		 3508 len += sizeof(*rh);
3509 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN);
3510 __pskb_pull_tail(skb, len);
3511
3512 rh = (struct rx_pkt_hdr1 *) skb->data;
3513 if (np->dev->features & NETIF_F_RXHASH)
3514 skb->rxhash = ((u32)rh->hashval2_0 << 24 |
3515 (u32)rh->hashval2_1 << 16 |
3516 (u32)rh->hashval1_1 << 8 |
3517 (u32)rh->hashval1_2 << 0);
3518 skb_pull(skb, sizeof(*rh));
a3138df9
DM		 3519
3520 rp->rx_packets++;
3521 rp->rx_bytes += skb->len;
3522
3523 skb->protocol = eth_type_trans(skb, np->dev);
0c8dfc83 3524 skb_record_rx_queue(skb, rp->rx_channel);
4099e012 3525 napi_gro_receive(napi, skb);
a3138df9
DM		 3526
3527 return num_rcr;
3528}
3529
3530static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
3531{
3532 int blocks_per_page = rp->rbr_blocks_per_page;
3533 int err, index = rp->rbr_index;
3534
3535 err = 0;
3536 while (index < (rp->rbr_table_size - blocks_per_page)) {
3537 err = niu_rbr_add_page(np, rp, mask, index);
3538 if (err)
3539 break;
3540
3541 index += blocks_per_page;
3542 }
3543
3544 rp->rbr_index = index;
3545 return err;
3546}
3547
3548static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
3549{
3550 int i;
3551
3552 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
3553 struct page *page;
3554
3555 page = rp->rxhash[i];
3556 while (page) {
3557 struct page *next = (struct page *) page->mapping;
3558 u64 base = page->index;
3559
3560 np->ops->unmap_page(np->device, base, PAGE_SIZE,
3561 DMA_FROM_DEVICE);
3562 page->index = 0;
3563 page->mapping = NULL;
3564
3565 __free_page(page);
3566
3567 page = next;
3568 }
3569 }
3570
3571 for (i = 0; i < rp->rbr_table_size; i++)
3572 rp->rbr[i] = cpu_to_le32(0);
3573 rp->rbr_index = 0;
3574}
3575
3576static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
3577{
3578 struct tx_buff_info *tb = &rp->tx_buffs[idx];
3579 struct sk_buff *skb = tb->skb;
3580 struct tx_pkt_hdr *tp;
3581 u64 tx_flags;
3582 int i, len;
3583
3584 tp = (struct tx_pkt_hdr *) skb->data;
3585 tx_flags = le64_to_cpup(&tp->flags);
3586
3587 rp->tx_packets++;
3588 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
3589 ((tx_flags & TXHDR_PAD) / 2));
3590
3591 len = skb_headlen(skb);
3592 np->ops->unmap_single(np->device, tb->mapping,
3593 len, DMA_TO_DEVICE);
3594
3595 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
3596 rp->mark_pending--;
3597
3598 tb->skb = NULL;
3599 do {
3600 idx = NEXT_TX(rp, idx);
3601 len -= MAX_TX_DESC_LEN;
3602 } while (len > 0);
3603
3604 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3605 tb = &rp->tx_buffs[idx];
3606 BUG_ON(tb->skb != NULL);
3607 np->ops->unmap_page(np->device, tb->mapping,
3608 skb_shinfo(skb)->frags[i].size,
3609 DMA_TO_DEVICE);
3610 idx = NEXT_TX(rp, idx);
3611 }
3612
3613 dev_kfree_skb(skb);
3614
3615 return idx;
3616}
3617
3618#define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3619
3620static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
3621{
b4c21639 3622 struct netdev_queue *txq;
a3138df9 3623 u16 pkt_cnt, tmp;
b4c21639 3624 int cons, index;
a3138df9
DM		 3625 u64 cs;
3626
b4c21639
DM		 3627 index = (rp - np->tx_rings);
3628 txq = netdev_get_tx_queue(np->dev, index);
3629
a3138df9
DM		 3630 cs = rp->tx_cs;
3631 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
3632 goto out;
3633
3634 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
3635 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
3636 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
3637
3638 rp->last_pkt_cnt = tmp;
3639
3640 cons = rp->cons;
3641
f10a1f2e
JP		 3642 netif_printk(np, tx_done, KERN_DEBUG, np->dev,
3643 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons);
a3138df9
DM		 3644
3645 while (pkt_cnt--)
3646 cons = release_tx_packet(np, rp, cons);
3647
3648 rp->cons = cons;
3649 smp_mb();
3650
3651out:
b4c21639 3652 if (unlikely(netif_tx_queue_stopped(txq) &&
a3138df9 3653 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
b4c21639
DM		 3654 __netif_tx_lock(txq, smp_processor_id());
3655 if (netif_tx_queue_stopped(txq) &&
a3138df9 3656 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
b4c21639
DM		 3657 netif_tx_wake_queue(txq);
3658 __netif_tx_unlock(txq);
a3138df9
DM		 3659 }
3660}
3661
b8a606b8
JDB		 3662static inline void niu_sync_rx_discard_stats(struct niu *np,
3663 struct rx_ring_info *rp,
3664 const int limit)
3665{
3666 /* This elaborate scheme is needed for reading the RX discard
3667 * counters, as they are only 16-bit and can overflow quickly,
3668 * and because the overflow indication bit is not usable as
3669 * the counter value does not wrap, but remains at max value
3670 * 0xFFFF.
3671 *
3672 * In theory and in practice counters can be lost in between
3673 * reading nr64() and clearing the counter nw64(). For this
3674 * reason, the number of counter clearings nw64() is
3675 * limited/reduced though the limit parameter.
3676 */
3677 int rx_channel = rp->rx_channel;
3678 u32 misc, wred;
3679
3680 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3681 * following discard events: IPP (Input Port Process),
3682 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3683 * Block Ring) prefetch buffer is empty.
3684 */
3685 misc = nr64(RXMISC(rx_channel));
3686 if (unlikely((misc & RXMISC_COUNT) > limit)) {
3687 nw64(RXMISC(rx_channel), 0);
3688 rp->rx_errors += misc & RXMISC_COUNT;
3689
3690 if (unlikely(misc & RXMISC_OFLOW))
f10a1f2e
JP		 3691 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n",
3692 rx_channel);
d231776f 3693
f10a1f2e
JP		 3694 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3695 "rx-%d: MISC drop=%u over=%u\n",
3696 rx_channel, misc, misc-limit);
b8a606b8
JDB		 3697 }
3698
3699 /* WRED (Weighted Random Early Discard) by hardware */
3700 wred = nr64(RED_DIS_CNT(rx_channel));
3701 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) {
3702 nw64(RED_DIS_CNT(rx_channel), 0);
3703 rp->rx_dropped += wred & RED_DIS_CNT_COUNT;
3704
3705 if (unlikely(wred & RED_DIS_CNT_OFLOW))
f10a1f2e 3706 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel);
d231776f 3707
f10a1f2e
JP		 3708 netif_printk(np, rx_err, KERN_DEBUG, np->dev,
3709 "rx-%d: WRED drop=%u over=%u\n",
3710 rx_channel, wred, wred-limit);
b8a606b8
JDB		 3711 }
3712}
3713
4099e012
DM		 3714static int niu_rx_work(struct napi_struct *napi, struct niu *np,
3715 struct rx_ring_info *rp, int budget)
a3138df9
DM		 3716{
3717 int qlen, rcr_done = 0, work_done = 0;
3718 struct rxdma_mailbox *mbox = rp->mbox;
3719 u64 stat;
3720
3721#if 1
3722 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3723 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3724#else
3725 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3726 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
3727#endif
3728 mbox->rx_dma_ctl_stat = 0;
3729 mbox->rcrstat_a = 0;
3730
f10a1f2e
JP		 3731 netif_printk(np, rx_status, KERN_DEBUG, np->dev,
3732 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3733 __func__, rp->rx_channel, (unsigned long long)stat, qlen);
a3138df9
DM		 3734
3735 rcr_done = work_done = 0;
3736 qlen = min(qlen, budget);
3737 while (work_done < qlen) {
4099e012 3738 rcr_done += niu_process_rx_pkt(napi, np, rp);
a3138df9
DM		 3739 work_done++;
3740 }
3741
3742 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
3743 unsigned int i;
3744
3745 for (i = 0; i < rp->rbr_refill_pending; i++)
3746 niu_rbr_refill(np, rp, GFP_ATOMIC);
3747 rp->rbr_refill_pending = 0;
3748 }
3749
3750 stat = (RX_DMA_CTL_STAT_MEX |
3751 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
3752 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
3753
3754 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3755
e98def1f
JDB		 3756 /* Only sync discards stats when qlen indicate potential for drops */
3757 if (qlen > 10)
3758 niu_sync_rx_discard_stats(np, rp, 0x7FFF);
b8a606b8 3759
a3138df9
DM		 3760 return work_done;
3761}
3762
3763static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
3764{
3765 u64 v0 = lp->v0;
3766 u32 tx_vec = (v0 >> 32);
3767 u32 rx_vec = (v0 & 0xffffffff);
3768 int i, work_done = 0;
3769
f10a1f2e
JP		 3770 netif_printk(np, intr, KERN_DEBUG, np->dev,
3771 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0);
a3138df9
DM		 3772
3773 for (i = 0; i < np->num_tx_rings; i++) {
3774 struct tx_ring_info *rp = &np->tx_rings[i];
3775 if (tx_vec & (1 << rp->tx_channel))
3776 niu_tx_work(np, rp);
3777 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3778 }
3779
3780 for (i = 0; i < np->num_rx_rings; i++) {
3781 struct rx_ring_info *rp = &np->rx_rings[i];
3782
3783 if (rx_vec & (1 << rp->rx_channel)) {
3784 int this_work_done;
3785
4099e012 3786 this_work_done = niu_rx_work(&lp->napi, np, rp,
a3138df9
DM		 3787 budget);
3788
3789 budget -= this_work_done;
3790 work_done += this_work_done;
3791 }
3792 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3793 }
3794
3795 return work_done;
3796}
3797
3798static int niu_poll(struct napi_struct *napi, int budget)
3799{
3800 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
3801 struct niu *np = lp->np;
3802 int work_done;
3803
3804 work_done = niu_poll_core(np, lp, budget);
3805
3806 if (work_done < budget) {
288379f0 3807 napi_complete(napi);
a3138df9
DM		 3808 niu_ldg_rearm(np, lp, 1);
3809 }
3810 return work_done;
3811}
3812
3813static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
3814 u64 stat)
3815{
f10a1f2e 3816 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel);
a3138df9
DM		 3817
3818 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
f10a1f2e 3819 pr_cont("RBR_TMOUT ");
a3138df9 3820 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
f10a1f2e 3821 pr_cont("RSP_CNT ");
a3138df9 3822 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
f10a1f2e 3823 pr_cont("BYTE_EN_BUS ");
a3138df9 3824 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
f10a1f2e 3825 pr_cont("RSP_DAT ");
a3138df9 3826 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
f10a1f2e 3827 pr_cont("RCR_ACK ");
a3138df9 3828 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
f10a1f2e 3829 pr_cont("RCR_SHA_PAR ");
a3138df9 3830 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
f10a1f2e 3831 pr_cont("RBR_PRE_PAR ");
a3138df9 3832 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
f10a1f2e 3833 pr_cont("CONFIG ");
a3138df9 3834 if (stat & RX_DMA_CTL_STAT_RCRINCON)
f10a1f2e 3835 pr_cont("RCRINCON ");
a3138df9 3836 if (stat & RX_DMA_CTL_STAT_RCRFULL)
f10a1f2e 3837 pr_cont("RCRFULL ");
a3138df9 3838 if (stat & RX_DMA_CTL_STAT_RBRFULL)
f10a1f2e 3839 pr_cont("RBRFULL ");
a3138df9 3840 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
f10a1f2e 3841 pr_cont("RBRLOGPAGE ");
a3138df9 3842 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
f10a1f2e 3843 pr_cont("CFIGLOGPAGE ");
a3138df9 3844 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
f10a1f2e 3845 pr_cont("DC_FIDO ");
a3138df9 3846
f10a1f2e 3847 pr_cont(")\n");
a3138df9
DM		 3848}
3849
3850static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
3851{
3852 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3853 int err = 0;
3854
a3138df9
DM		 3855
3856 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
3857 RX_DMA_CTL_STAT_PORT_FATAL))
3858 err = -EINVAL;
3859
406f353c 3860 if (err) {
f10a1f2e
JP		 3861 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n",
3862 rp->rx_channel,
3863 (unsigned long long) stat);
406f353c
MW		 3864
3865 niu_log_rxchan_errors(np, rp, stat);
3866 }
3867
a3138df9
DM		 3868 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
3869 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
3870
3871 return err;
3872}
3873
3874static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
3875 u64 cs)
3876{
f10a1f2e 3877 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel);
a3138df9
DM		 3878
3879 if (cs & TX_CS_MBOX_ERR)
f10a1f2e 3880 pr_cont("MBOX ");
a3138df9 3881 if (cs & TX_CS_PKT_SIZE_ERR)
f10a1f2e 3882 pr_cont("PKT_SIZE ");
a3138df9 3883 if (cs & TX_CS_TX_RING_OFLOW)
f10a1f2e 3884 pr_cont("TX_RING_OFLOW ");
a3138df9 3885 if (cs & TX_CS_PREF_BUF_PAR_ERR)
f10a1f2e 3886 pr_cont("PREF_BUF_PAR ");
a3138df9 3887 if (cs & TX_CS_NACK_PREF)
f10a1f2e 3888 pr_cont("NACK_PREF ");
a3138df9 3889 if (cs & TX_CS_NACK_PKT_RD)
f10a1f2e 3890 pr_cont("NACK_PKT_RD ");
a3138df9 3891 if (cs & TX_CS_CONF_PART_ERR)
f10a1f2e 3892 pr_cont("CONF_PART ");
a3138df9 3893 if (cs & TX_CS_PKT_PRT_ERR)
f10a1f2e 3894 pr_cont("PKT_PTR ");
a3138df9 3895
f10a1f2e 3896 pr_cont(")\n");
a3138df9
DM		 3897}
3898
3899static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
3900{
3901 u64 cs, logh, logl;
3902
3903 cs = nr64(TX_CS(rp->tx_channel));
3904 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3905 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3906
f10a1f2e
JP		 3907 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3908 rp->tx_channel,
3909 (unsigned long long)cs,
3910 (unsigned long long)logh,
3911 (unsigned long long)logl);
a3138df9
DM		 3912
3913 niu_log_txchan_errors(np, rp, cs);
3914
3915 return -ENODEV;
3916}
3917
3918static int niu_mif_interrupt(struct niu *np)
3919{
3920 u64 mif_status = nr64(MIF_STATUS);
3921 int phy_mdint = 0;
3922
3923 if (np->flags & NIU_FLAGS_XMAC) {
3924 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
3925
3926 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
3927 phy_mdint = 1;
3928 }
3929
f10a1f2e
JP		 3930 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3931 (unsigned long long)mif_status, phy_mdint);
a3138df9
DM		 3932
3933 return -ENODEV;
3934}
3935
3936static void niu_xmac_interrupt(struct niu *np)
3937{
3938 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
3939 u64 val;
3940
3941 val = nr64_mac(XTXMAC_STATUS);
3942 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3943 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
3944 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3945 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
3946 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3947 mp->tx_fifo_errors++;
3948 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3949 mp->tx_overflow_errors++;
3950 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3951 mp->tx_max_pkt_size_errors++;
3952 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3953 mp->tx_underflow_errors++;
3954
3955 val = nr64_mac(XRXMAC_STATUS);
3956 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3957 mp->rx_local_faults++;
3958 if (val & XRXMAC_STATUS_RFLT_DET)
3959 mp->rx_remote_faults++;
3960 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3961 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
3962 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3963 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
3964 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3965 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
3966 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3967 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
3968 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3969 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3970 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3971 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
3972 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3973 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
3974 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3975 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
3976 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3977 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
3978 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3979 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
3980 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3981 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
3982 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3983 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
3984 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3985 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
176edd52 3986 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
a3138df9
DM		 3987 mp->rx_octets += RXMAC_BT_CNT_COUNT;
3988 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3989 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
3990 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3991 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
3992 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3993 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
3994 if (val & XRXMAC_STATUS_RXUFLOW)
3995 mp->rx_underflows++;
3996 if (val & XRXMAC_STATUS_RXOFLOW)
3997 mp->rx_overflows++;
3998
3999 val = nr64_mac(XMAC_FC_STAT);
4000 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
4001 mp->pause_off_state++;
4002 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
4003 mp->pause_on_state++;
4004 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
4005 mp->pause_received++;
4006}
4007
4008static void niu_bmac_interrupt(struct niu *np)
4009{
4010 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
4011 u64 val;
4012
4013 val = nr64_mac(BTXMAC_STATUS);
4014 if (val & BTXMAC_STATUS_UNDERRUN)
4015 mp->tx_underflow_errors++;
4016 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
4017 mp->tx_max_pkt_size_errors++;
4018 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
4019 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
4020 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
4021 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
4022
4023 val = nr64_mac(BRXMAC_STATUS);
4024 if (val & BRXMAC_STATUS_OVERFLOW)
4025 mp->rx_overflows++;
4026 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
4027 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
4028 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
4029 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4030 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
4031 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
4032 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
4033 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
4034
4035 val = nr64_mac(BMAC_CTRL_STATUS);
4036 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4037 mp->pause_off_state++;
4038 if (val & BMAC_CTRL_STATUS_PAUSE)
4039 mp->pause_on_state++;
4040 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4041 mp->pause_received++;
4042}
4043
4044static int niu_mac_interrupt(struct niu *np)
4045{
4046 if (np->flags & NIU_FLAGS_XMAC)
4047 niu_xmac_interrupt(np);
4048 else
4049 niu_bmac_interrupt(np);
4050
4051 return 0;
4052}
4053
4054static void niu_log_device_error(struct niu *np, u64 stat)
4055{
f10a1f2e 4056 netdev_err(np->dev, "Core device errors ( ");
a3138df9
DM		 4057
4058 if (stat & SYS_ERR_MASK_META2)
f10a1f2e 4059 pr_cont("META2 ");
a3138df9 4060 if (stat & SYS_ERR_MASK_META1)
f10a1f2e 4061 pr_cont("META1 ");
a3138df9 4062 if (stat & SYS_ERR_MASK_PEU)
f10a1f2e 4063 pr_cont("PEU ");
a3138df9 4064 if (stat & SYS_ERR_MASK_TXC)
f10a1f2e 4065 pr_cont("TXC ");
a3138df9 4066 if (stat & SYS_ERR_MASK_RDMC)
f10a1f2e 4067 pr_cont("RDMC ");
a3138df9 4068 if (stat & SYS_ERR_MASK_TDMC)
f10a1f2e 4069 pr_cont("TDMC ");
a3138df9 4070 if (stat & SYS_ERR_MASK_ZCP)
f10a1f2e 4071 pr_cont("ZCP ");
a3138df9 4072 if (stat & SYS_ERR_MASK_FFLP)
f10a1f2e 4073 pr_cont("FFLP ");
a3138df9 4074 if (stat & SYS_ERR_MASK_IPP)
f10a1f2e 4075 pr_cont("IPP ");
a3138df9 4076 if (stat & SYS_ERR_MASK_MAC)
f10a1f2e 4077 pr_cont("MAC ");
a3138df9 4078 if (stat & SYS_ERR_MASK_SMX)
f10a1f2e 4079 pr_cont("SMX ");
a3138df9 4080
f10a1f2e 4081 pr_cont(")\n");
a3138df9
DM		 4082}
4083
4084static int niu_device_error(struct niu *np)
4085{
4086 u64 stat = nr64(SYS_ERR_STAT);
4087
f10a1f2e
JP		 4088 netdev_err(np->dev, "Core device error, stat[%llx]\n",
4089 (unsigned long long)stat);
a3138df9
DM		 4090
4091 niu_log_device_error(np, stat);
4092
4093 return -ENODEV;
4094}
4095
406f353c
MW		 4096static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
4097 u64 v0, u64 v1, u64 v2)
a3138df9 4098{
406f353c 4099
a3138df9
DM		 4100 int i, err = 0;
4101
406f353c
MW		 4102 lp->v0 = v0;
4103 lp->v1 = v1;
4104 lp->v2 = v2;
4105
a3138df9
DM		 4106 if (v1 & 0x00000000ffffffffULL) {
4107 u32 rx_vec = (v1 & 0xffffffff);
4108
4109 for (i = 0; i < np->num_rx_rings; i++) {
4110 struct rx_ring_info *rp = &np->rx_rings[i];
4111
4112 if (rx_vec & (1 << rp->rx_channel)) {
4113 int r = niu_rx_error(np, rp);
406f353c 4114 if (r) {
a3138df9 4115 err = r;
406f353c
MW		 4116 } else {
4117 if (!v0)
4118 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4119 RX_DMA_CTL_STAT_MEX);
4120 }
a3138df9
DM		 4121 }
4122 }
4123 }
4124 if (v1 & 0x7fffffff00000000ULL) {
4125 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
4126
4127 for (i = 0; i < np->num_tx_rings; i++) {
4128 struct tx_ring_info *rp = &np->tx_rings[i];
4129
4130 if (tx_vec & (1 << rp->tx_channel)) {
4131 int r = niu_tx_error(np, rp);
4132 if (r)
4133 err = r;
4134 }
4135 }
4136 }
4137 if ((v0 | v1) & 0x8000000000000000ULL) {
4138 int r = niu_mif_interrupt(np);
4139 if (r)
4140 err = r;
4141 }
4142 if (v2) {
4143 if (v2 & 0x01ef) {
4144 int r = niu_mac_interrupt(np);
4145 if (r)
4146 err = r;
4147 }
4148 if (v2 & 0x0210) {
4149 int r = niu_device_error(np);
4150 if (r)
4151 err = r;
4152 }
4153 }
4154
4155 if (err)
4156 niu_enable_interrupts(np, 0);
4157
406f353c 4158 return err;
a3138df9
DM		 4159}
4160
4161static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
4162 int ldn)
4163{
4164 struct rxdma_mailbox *mbox = rp->mbox;
4165 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
4166
4167 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
4168 RX_DMA_CTL_STAT_RCRTO);
4169 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4170
f10a1f2e
JP		 4171 netif_printk(np, intr, KERN_DEBUG, np->dev,
4172 "%s() stat[%llx]\n", __func__, (unsigned long long)stat);
a3138df9
DM		 4173}
4174
4175static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
4176 int ldn)
4177{
4178 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4179
f10a1f2e
JP		 4180 netif_printk(np, intr, KERN_DEBUG, np->dev,
4181 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs);
a3138df9
DM		 4182}
4183
4184static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
4185{
4186 struct niu_parent *parent = np->parent;
4187 u32 rx_vec, tx_vec;
4188 int i;
4189
4190 tx_vec = (v0 >> 32);
4191 rx_vec = (v0 & 0xffffffff);
4192
4193 for (i = 0; i < np->num_rx_rings; i++) {
4194 struct rx_ring_info *rp = &np->rx_rings[i];
4195 int ldn = LDN_RXDMA(rp->rx_channel);
4196
4197 if (parent->ldg_map[ldn] != ldg)
4198 continue;
4199
4200 nw64(LD_IM0(ldn), LD_IM0_MASK);
4201 if (rx_vec & (1 << rp->rx_channel))
4202 niu_rxchan_intr(np, rp, ldn);
4203 }
4204
4205 for (i = 0; i < np->num_tx_rings; i++) {
4206 struct tx_ring_info *rp = &np->tx_rings[i];
4207 int ldn = LDN_TXDMA(rp->tx_channel);
4208
4209 if (parent->ldg_map[ldn] != ldg)
4210 continue;
4211
4212 nw64(LD_IM0(ldn), LD_IM0_MASK);
4213 if (tx_vec & (1 << rp->tx_channel))
4214 niu_txchan_intr(np, rp, ldn);
4215 }
4216}
4217
4218static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
4219 u64 v0, u64 v1, u64 v2)
4220{
288379f0 4221 if (likely(napi_schedule_prep(&lp->napi))) {
a3138df9
DM		 4222 lp->v0 = v0;
4223 lp->v1 = v1;
4224 lp->v2 = v2;
4225 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
288379f0 4226 __napi_schedule(&lp->napi);
a3138df9
DM		 4227 }
4228}
4229
4230static irqreturn_t niu_interrupt(int irq, void *dev_id)
4231{
4232 struct niu_ldg *lp = dev_id;
4233 struct niu *np = lp->np;
4234 int ldg = lp->ldg_num;
4235 unsigned long flags;
4236 u64 v0, v1, v2;
4237
4238 if (netif_msg_intr(np))
f10a1f2e
JP		 4239 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)",
4240 __func__, lp, ldg);
a3138df9
DM		 4241
4242 spin_lock_irqsave(&np->lock, flags);
4243
4244 v0 = nr64(LDSV0(ldg));
4245 v1 = nr64(LDSV1(ldg));
4246 v2 = nr64(LDSV2(ldg));
4247
4248 if (netif_msg_intr(np))
02b1bae5 4249 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
a3138df9
DM		 4250 (unsigned long long) v0,
4251 (unsigned long long) v1,
4252 (unsigned long long) v2);
4253
4254 if (unlikely(!v0 && !v1 && !v2)) {
4255 spin_unlock_irqrestore(&np->lock, flags);
4256 return IRQ_NONE;
4257 }
4258
4259 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
406f353c 4260 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
a3138df9
DM		 4261 if (err)
4262 goto out;
4263 }
4264 if (likely(v0 & ~((u64)1 << LDN_MIF)))
4265 niu_schedule_napi(np, lp, v0, v1, v2);
4266 else
4267 niu_ldg_rearm(np, lp, 1);
4268out:
4269 spin_unlock_irqrestore(&np->lock, flags);
4270
4271 return IRQ_HANDLED;
4272}
4273
4274static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
4275{
4276 if (rp->mbox) {
4277 np->ops->free_coherent(np->device,
4278 sizeof(struct rxdma_mailbox),
4279 rp->mbox, rp->mbox_dma);
4280 rp->mbox = NULL;
4281 }
4282 if (rp->rcr) {
4283 np->ops->free_coherent(np->device,
4284 MAX_RCR_RING_SIZE * sizeof(__le64),
4285 rp->rcr, rp->rcr_dma);
4286 rp->rcr = NULL;
4287 rp->rcr_table_size = 0;
4288 rp->rcr_index = 0;
4289 }
4290 if (rp->rbr) {
4291 niu_rbr_free(np, rp);
4292
4293 np->ops->free_coherent(np->device,
4294 MAX_RBR_RING_SIZE * sizeof(__le32),
4295 rp->rbr, rp->rbr_dma);
4296 rp->rbr = NULL;
4297 rp->rbr_table_size = 0;
4298 rp->rbr_index = 0;
4299 }
4300 kfree(rp->rxhash);
4301 rp->rxhash = NULL;
4302}
4303
4304static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
4305{
4306 if (rp->mbox) {
4307 np->ops->free_coherent(np->device,
4308 sizeof(struct txdma_mailbox),
4309 rp->mbox, rp->mbox_dma);
4310 rp->mbox = NULL;
4311 }
4312 if (rp->descr) {
4313 int i;
4314
4315 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
4316 if (rp->tx_buffs[i].skb)
4317 (void) release_tx_packet(np, rp, i);
4318 }
4319
4320 np->ops->free_coherent(np->device,
4321 MAX_TX_RING_SIZE * sizeof(__le64),
4322 rp->descr, rp->descr_dma);
4323 rp->descr = NULL;
4324 rp->pending = 0;
4325 rp->prod = 0;
4326 rp->cons = 0;
4327 rp->wrap_bit = 0;
4328 }
4329}
4330
4331static void niu_free_channels(struct niu *np)
4332{
4333 int i;
4334
4335 if (np->rx_rings) {
4336 for (i = 0; i < np->num_rx_rings; i++) {
4337 struct rx_ring_info *rp = &np->rx_rings[i];
4338
4339 niu_free_rx_ring_info(np, rp);
4340 }
4341 kfree(np->rx_rings);
4342 np->rx_rings = NULL;
4343 np->num_rx_rings = 0;
4344 }
4345
4346 if (np->tx_rings) {
4347 for (i = 0; i < np->num_tx_rings; i++) {
4348 struct tx_ring_info *rp = &np->tx_rings[i];
4349
4350 niu_free_tx_ring_info(np, rp);
4351 }
4352 kfree(np->tx_rings);
4353 np->tx_rings = NULL;
4354 np->num_tx_rings = 0;
4355 }
4356}
4357
4358static int niu_alloc_rx_ring_info(struct niu *np,
4359 struct rx_ring_info *rp)
4360{
4361 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
4362
4363 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
4364 GFP_KERNEL);
4365 if (!rp->rxhash)
4366 return -ENOMEM;
4367
4368 rp->mbox = np->ops->alloc_coherent(np->device,
4369 sizeof(struct rxdma_mailbox),
4370 &rp->mbox_dma, GFP_KERNEL);
4371 if (!rp->mbox)
4372 return -ENOMEM;
4373 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4374 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4375 rp->mbox);
a3138df9
DM		 4376 return -EINVAL;
4377 }
4378
4379 rp->rcr = np->ops->alloc_coherent(np->device,
4380 MAX_RCR_RING_SIZE * sizeof(__le64),
4381 &rp->rcr_dma, GFP_KERNEL);
4382 if (!rp->rcr)
4383 return -ENOMEM;
4384 if ((unsigned long)rp->rcr & (64UL - 1)) {
f10a1f2e
JP		 4385 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4386 rp->rcr);
a3138df9
DM		 4387 return -EINVAL;
4388 }
4389 rp->rcr_table_size = MAX_RCR_RING_SIZE;
4390 rp->rcr_index = 0;
4391
4392 rp->rbr = np->ops->alloc_coherent(np->device,
4393 MAX_RBR_RING_SIZE * sizeof(__le32),
4394 &rp->rbr_dma, GFP_KERNEL);
4395 if (!rp->rbr)
4396 return -ENOMEM;
4397 if ((unsigned long)rp->rbr & (64UL - 1)) {
f10a1f2e
JP		 4398 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4399 rp->rbr);
a3138df9
DM		 4400 return -EINVAL;
4401 }
4402 rp->rbr_table_size = MAX_RBR_RING_SIZE;
4403 rp->rbr_index = 0;
4404 rp->rbr_pending = 0;
4405
4406 return 0;
4407}
4408
4409static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
4410{
4411 int mtu = np->dev->mtu;
4412
4413 /* These values are recommended by the HW designers for fair
4414 * utilization of DRR amongst the rings.
4415 */
4416 rp->max_burst = mtu + 32;
4417 if (rp->max_burst > 4096)
4418 rp->max_burst = 4096;
4419}
4420
4421static int niu_alloc_tx_ring_info(struct niu *np,
4422 struct tx_ring_info *rp)
4423{
4424 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
4425
4426 rp->mbox = np->ops->alloc_coherent(np->device,
4427 sizeof(struct txdma_mailbox),
4428 &rp->mbox_dma, GFP_KERNEL);
4429 if (!rp->mbox)
4430 return -ENOMEM;
4431 if ((unsigned long)rp->mbox & (64UL - 1)) {
f10a1f2e
JP		 4432 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4433 rp->mbox);
a3138df9
DM		 4434 return -EINVAL;
4435 }
4436
4437 rp->descr = np->ops->alloc_coherent(np->device,
4438 MAX_TX_RING_SIZE * sizeof(__le64),
4439 &rp->descr_dma, GFP_KERNEL);
4440 if (!rp->descr)
4441 return -ENOMEM;
4442 if ((unsigned long)rp->descr & (64UL - 1)) {
f10a1f2e
JP		 4443 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4444 rp->descr);
a3138df9
DM		 4445 return -EINVAL;
4446 }
4447
4448 rp->pending = MAX_TX_RING_SIZE;
4449 rp->prod = 0;
4450 rp->cons = 0;
4451 rp->wrap_bit = 0;
4452
4453 /* XXX make these configurable... XXX */
4454 rp->mark_freq = rp->pending / 4;
4455
4456 niu_set_max_burst(np, rp);
4457
4458 return 0;
4459}
4460
4461static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
4462{
81429973 4463 u16 bss;
a3138df9 4464
81429973 4465 bss = min(PAGE_SHIFT, 15);
a3138df9 4466
81429973
OJ		 4467 rp->rbr_block_size = 1 << bss;
4468 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
a3138df9
DM		 4469
4470 rp->rbr_sizes[0] = 256;
4471 rp->rbr_sizes[1] = 1024;
4472 if (np->dev->mtu > ETH_DATA_LEN) {
4473 switch (PAGE_SIZE) {
4474 case 4 * 1024:
4475 rp->rbr_sizes[2] = 4096;
4476 break;
4477
4478 default:
4479 rp->rbr_sizes[2] = 8192;
4480 break;
4481 }
4482 } else {
4483 rp->rbr_sizes[2] = 2048;
4484 }
4485 rp->rbr_sizes[3] = rp->rbr_block_size;
4486}
4487
4488static int niu_alloc_channels(struct niu *np)
4489{
4490 struct niu_parent *parent = np->parent;
4491 int first_rx_channel, first_tx_channel;
4492 int i, port, err;
4493
4494 port = np->port;
4495 first_rx_channel = first_tx_channel = 0;
4496 for (i = 0; i < port; i++) {
4497 first_rx_channel += parent->rxchan_per_port[i];
4498 first_tx_channel += parent->txchan_per_port[i];
4499 }
4500
4501 np->num_rx_rings = parent->rxchan_per_port[port];
4502 np->num_tx_rings = parent->txchan_per_port[port];
4503
e2209ba3
BH		 4504 netif_set_real_num_rx_queues(np->dev, np->num_rx_rings);
4505 netif_set_real_num_tx_queues(np->dev, np->num_tx_rings);
b4c21639 4506
baeb2ffa 4507 np->rx_rings = kcalloc(np->num_rx_rings, sizeof(struct rx_ring_info),
a3138df9
DM		 4508 GFP_KERNEL);
4509 err = -ENOMEM;
4510 if (!np->rx_rings)
4511 goto out_err;
4512
4513 for (i = 0; i < np->num_rx_rings; i++) {
4514 struct rx_ring_info *rp = &np->rx_rings[i];
4515
4516 rp->np = np;
4517 rp->rx_channel = first_rx_channel + i;
4518
4519 err = niu_alloc_rx_ring_info(np, rp);
4520 if (err)
4521 goto out_err;
4522
4523 niu_size_rbr(np, rp);
4524
4525 /* XXX better defaults, configurable, etc... XXX */
4526 rp->nonsyn_window = 64;
4527 rp->nonsyn_threshold = rp->rcr_table_size - 64;
4528 rp->syn_window = 64;
4529 rp->syn_threshold = rp->rcr_table_size - 64;
4530 rp->rcr_pkt_threshold = 16;
4531 rp->rcr_timeout = 8;
4532 rp->rbr_kick_thresh = RBR_REFILL_MIN;
4533 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
4534 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
4535
4536 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4537 if (err)
4538 return err;
4539 }
4540
baeb2ffa 4541 np->tx_rings = kcalloc(np->num_tx_rings, sizeof(struct tx_ring_info),
a3138df9
DM		 4542 GFP_KERNEL);
4543 err = -ENOMEM;
4544 if (!np->tx_rings)
4545 goto out_err;
4546
4547 for (i = 0; i < np->num_tx_rings; i++) {
4548 struct tx_ring_info *rp = &np->tx_rings[i];
4549
4550 rp->np = np;
4551 rp->tx_channel = first_tx_channel + i;
4552
4553 err = niu_alloc_tx_ring_info(np, rp);
4554 if (err)
4555 goto out_err;
4556 }
4557
4558 return 0;
4559
4560out_err:
4561 niu_free_channels(np);
4562 return err;
4563}
4564
4565static int niu_tx_cs_sng_poll(struct niu *np, int channel)
4566{
4567 int limit = 1000;
4568
4569 while (--limit > 0) {
4570 u64 val = nr64(TX_CS(channel));
4571 if (val & TX_CS_SNG_STATE)
4572 return 0;
4573 }
4574 return -ENODEV;
4575}
4576
4577static int niu_tx_channel_stop(struct niu *np, int channel)
4578{
4579 u64 val = nr64(TX_CS(channel));
4580
4581 val |= TX_CS_STOP_N_GO;
4582 nw64(TX_CS(channel), val);
4583
4584 return niu_tx_cs_sng_poll(np, channel);
4585}
4586
4587static int niu_tx_cs_reset_poll(struct niu *np, int channel)
4588{
4589 int limit = 1000;
4590
4591 while (--limit > 0) {
4592 u64 val = nr64(TX_CS(channel));
4593 if (!(val & TX_CS_RST))
4594 return 0;
4595 }
4596 return -ENODEV;
4597}
4598
4599static int niu_tx_channel_reset(struct niu *np, int channel)
4600{
4601 u64 val = nr64(TX_CS(channel));
4602 int err;
4603
4604 val |= TX_CS_RST;
4605 nw64(TX_CS(channel), val);
4606
4607 err = niu_tx_cs_reset_poll(np, channel);
4608 if (!err)
4609 nw64(TX_RING_KICK(channel), 0);
4610
4611 return err;
4612}
4613
4614static int niu_tx_channel_lpage_init(struct niu *np, int channel)
4615{
4616 u64 val;
4617
4618 nw64(TX_LOG_MASK1(channel), 0);
4619 nw64(TX_LOG_VAL1(channel), 0);
4620 nw64(TX_LOG_MASK2(channel), 0);
4621 nw64(TX_LOG_VAL2(channel), 0);
4622 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4623 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4624 nw64(TX_LOG_PAGE_HDL(channel), 0);
4625
4626 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4627 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4628 nw64(TX_LOG_PAGE_VLD(channel), val);
4629
4630 /* XXX TXDMA 32bit mode? XXX */
4631
4632 return 0;
4633}
4634
4635static void niu_txc_enable_port(struct niu *np, int on)
4636{
4637 unsigned long flags;
4638 u64 val, mask;
4639
4640 niu_lock_parent(np, flags);
4641 val = nr64(TXC_CONTROL);
4642 mask = (u64)1 << np->port;
4643 if (on) {
4644 val |= TXC_CONTROL_ENABLE | mask;
4645 } else {
4646 val &= ~mask;
4647 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4648 val &= ~TXC_CONTROL_ENABLE;
4649 }
4650 nw64(TXC_CONTROL, val);
4651 niu_unlock_parent(np, flags);
4652}
4653
4654static void niu_txc_set_imask(struct niu *np, u64 imask)
4655{
4656 unsigned long flags;
4657 u64 val;
4658
4659 niu_lock_parent(np, flags);
4660 val = nr64(TXC_INT_MASK);
4661 val &= ~TXC_INT_MASK_VAL(np->port);
4662 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4663 niu_unlock_parent(np, flags);
4664}
4665
4666static void niu_txc_port_dma_enable(struct niu *np, int on)
4667{
4668 u64 val = 0;
4669
4670 if (on) {
4671 int i;
4672
4673 for (i = 0; i < np->num_tx_rings; i++)
4674 val |= (1 << np->tx_rings[i].tx_channel);
4675 }
4676 nw64(TXC_PORT_DMA(np->port), val);
4677}
4678
4679static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4680{
4681 int err, channel = rp->tx_channel;
4682 u64 val, ring_len;
4683
4684 err = niu_tx_channel_stop(np, channel);
4685 if (err)
4686 return err;
4687
4688 err = niu_tx_channel_reset(np, channel);
4689 if (err)
4690 return err;
4691
4692 err = niu_tx_channel_lpage_init(np, channel);
4693 if (err)
4694 return err;
4695
4696 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4697 nw64(TX_ENT_MSK(channel), 0);
4698
4699 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
4700 TX_RNG_CFIG_STADDR)) {
f10a1f2e
JP		 4701 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4702 channel, (unsigned long long)rp->descr_dma);
a3138df9
DM		 4703 return -EINVAL;
4704 }
4705
4706 /* The length field in TX_RNG_CFIG is measured in 64-byte
4707 * blocks. rp->pending is the number of TX descriptors in
4708 * our ring, 8 bytes each, thus we divide by 8 bytes more
4709 * to get the proper value the chip wants.
4710 */
4711 ring_len = (rp->pending / 8);
4712
4713 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4714 rp->descr_dma);
4715 nw64(TX_RNG_CFIG(channel), val);
4716
4717 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
4718 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
f10a1f2e
JP		 4719 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4720 channel, (unsigned long long)rp->mbox_dma);
a3138df9
DM		 4721 return -EINVAL;
4722 }
4723 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4724 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4725
4726 nw64(TX_CS(channel), 0);
4727
4728 rp->last_pkt_cnt = 0;
4729
4730 return 0;
4731}
4732
4733static void niu_init_rdc_groups(struct niu *np)
4734{
4735 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4736 int i, first_table_num = tp->first_table_num;
4737
4738 for (i = 0; i < tp->num_tables; i++) {
4739 struct rdc_table *tbl = &tp->tables[i];
4740 int this_table = first_table_num + i;
4741 int slot;
4742
4743 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
4744 nw64(RDC_TBL(this_table, slot),
4745 tbl->rxdma_channel[slot]);
4746 }
4747
4748 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4749}
4750
4751static void niu_init_drr_weight(struct niu *np)
4752{
4753 int type = phy_decode(np->parent->port_phy, np->port);
4754 u64 val;
4755
4756 switch (type) {
4757 case PORT_TYPE_10G:
4758 val = PT_DRR_WEIGHT_DEFAULT_10G;
4759 break;
4760
4761 case PORT_TYPE_1G:
4762 default:
4763 val = PT_DRR_WEIGHT_DEFAULT_1G;
4764 break;
4765 }
4766 nw64(PT_DRR_WT(np->port), val);
4767}
4768
4769static int niu_init_hostinfo(struct niu *np)
4770{
4771 struct niu_parent *parent = np->parent;
4772 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4773 int i, err, num_alt = niu_num_alt_addr(np);
4774 int first_rdc_table = tp->first_table_num;
4775
4776 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4777 if (err)
4778 return err;
4779
4780 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4781 if (err)
4782 return err;
4783
4784 for (i = 0; i < num_alt; i++) {
4785 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4786 if (err)
4787 return err;
4788 }
4789
4790 return 0;
4791}
4792
4793static int niu_rx_channel_reset(struct niu *np, int channel)
4794{
4795 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
4796 RXDMA_CFIG1_RST, 1000, 10,
4797 "RXDMA_CFIG1");
4798}
4799
4800static int niu_rx_channel_lpage_init(struct niu *np, int channel)
4801{
4802 u64 val;
4803
4804 nw64(RX_LOG_MASK1(channel), 0);
4805 nw64(RX_LOG_VAL1(channel), 0);
4806 nw64(RX_LOG_MASK2(channel), 0);
4807 nw64(RX_LOG_VAL2(channel), 0);
4808 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4809 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4810 nw64(RX_LOG_PAGE_HDL(channel), 0);
4811
4812 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4813 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4814 nw64(RX_LOG_PAGE_VLD(channel), val);
4815
4816 return 0;
4817}
4818
4819static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
4820{
4821 u64 val;
4822
4823 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4824 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
4825 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
4826 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
4827 nw64(RDC_RED_PARA(rp->rx_channel), val);
4828}
4829
4830static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
4831{
4832 u64 val = 0;
4833
efb6c736 4834 *ret = 0;
a3138df9
DM		 4835 switch (rp->rbr_block_size) {
4836 case 4 * 1024:
4837 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4838 break;
4839 case 8 * 1024:
4840 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4841 break;
4842 case 16 * 1024:
4843 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4844 break;
4845 case 32 * 1024:
4846 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4847 break;
4848 default:
4849 return -EINVAL;
4850 }
4851 val |= RBR_CFIG_B_VLD2;
4852 switch (rp->rbr_sizes[2]) {
4853 case 2 * 1024:
4854 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4855 break;
4856 case 4 * 1024:
4857 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4858 break;
4859 case 8 * 1024:
4860 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4861 break;
4862 case 16 * 1024:
4863 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4864 break;
4865
4866 default:
4867 return -EINVAL;
4868 }
4869 val |= RBR_CFIG_B_VLD1;
4870 switch (rp->rbr_sizes[1]) {
4871 case 1 * 1024:
4872 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4873 break;
4874 case 2 * 1024:
4875 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4876 break;
4877 case 4 * 1024:
4878 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4879 break;
4880 case 8 * 1024:
4881 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4882 break;
4883
4884 default:
4885 return -EINVAL;
4886 }
4887 val |= RBR_CFIG_B_VLD0;
4888 switch (rp->rbr_sizes[0]) {
4889 case 256:
4890 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4891 break;
4892 case 512:
4893 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4894 break;
4895 case 1 * 1024:
4896 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4897 break;
4898 case 2 * 1024:
4899 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4900 break;
4901
4902 default:
4903 return -EINVAL;
4904 }
4905
4906 *ret = val;
4907 return 0;
4908}
4909
4910static int niu_enable_rx_channel(struct niu *np, int channel, int on)
4911{
4912 u64 val = nr64(RXDMA_CFIG1(channel));
4913 int limit;
4914
4915 if (on)
4916 val |= RXDMA_CFIG1_EN;
4917 else
4918 val &= ~RXDMA_CFIG1_EN;
4919 nw64(RXDMA_CFIG1(channel), val);
4920
4921 limit = 1000;
4922 while (--limit > 0) {
4923 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4924 break;
4925 udelay(10);
4926 }
4927 if (limit <= 0)
4928 return -ENODEV;
4929 return 0;
4930}
4931
4932static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4933{
4934 int err, channel = rp->rx_channel;
4935 u64 val;
4936
4937 err = niu_rx_channel_reset(np, channel);
4938 if (err)
4939 return err;
4940
4941 err = niu_rx_channel_lpage_init(np, channel);
4942 if (err)
4943 return err;
4944
4945 niu_rx_channel_wred_init(np, rp);
4946
4947 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4948 nw64(RX_DMA_CTL_STAT(channel),
4949 (RX_DMA_CTL_STAT_MEX |
4950 RX_DMA_CTL_STAT_RCRTHRES |
4951 RX_DMA_CTL_STAT_RCRTO |
4952 RX_DMA_CTL_STAT_RBR_EMPTY));
4953 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3cfa856d
DM		 4954 nw64(RXDMA_CFIG2(channel),
4955 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) |
4956 RXDMA_CFIG2_FULL_HDR));
a3138df9
DM		 4957 nw64(RBR_CFIG_A(channel),
4958 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
4959 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
4960 err = niu_compute_rbr_cfig_b(rp, &val);
4961 if (err)
4962 return err;
4963 nw64(RBR_CFIG_B(channel), val);
4964 nw64(RCRCFIG_A(channel),
4965 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
4966 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
4967 nw64(RCRCFIG_B(channel),
4968 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
4969 RCRCFIG_B_ENTOUT |
4970 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
4971
4972 err = niu_enable_rx_channel(np, channel, 1);
4973 if (err)
4974 return err;
4975
4976 nw64(RBR_KICK(channel), rp->rbr_index);
4977
4978 val = nr64(RX_DMA_CTL_STAT(channel));
4979 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4980 nw64(RX_DMA_CTL_STAT(channel), val);
4981
4982 return 0;
4983}
4984
4985static int niu_init_rx_channels(struct niu *np)
4986{
4987 unsigned long flags;
4988 u64 seed = jiffies_64;
4989 int err, i;
4990
4991 niu_lock_parent(np, flags);
4992 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4993 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
4994 niu_unlock_parent(np, flags);
4995
4996 /* XXX RXDMA 32bit mode? XXX */
4997
4998 niu_init_rdc_groups(np);
4999 niu_init_drr_weight(np);
5000
5001 err = niu_init_hostinfo(np);
5002 if (err)
5003 return err;
5004
5005 for (i = 0; i < np->num_rx_rings; i++) {
5006 struct rx_ring_info *rp = &np->rx_rings[i];
5007
5008 err = niu_init_one_rx_channel(np, rp);
5009 if (err)
5010 return err;
5011 }
5012
5013 return 0;
5014}
5015
5016static int niu_set_ip_frag_rule(struct niu *np)
5017{
5018 struct niu_parent *parent = np->parent;
5019 struct niu_classifier *cp = &np->clas;
5020 struct niu_tcam_entry *tp;
5021 int index, err;
5022
2d96cf8c 5023 index = cp->tcam_top;
a3138df9
DM		 5024 tp = &parent->tcam[index];
5025
5026 /* Note that the noport bit is the same in both ipv4 and
5027 * ipv6 format TCAM entries.
5028 */
5029 memset(tp, 0, sizeof(*tp));
5030 tp->key[1] = TCAM_V4KEY1_NOPORT;
5031 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
5032 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
5033 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
5034 err = tcam_write(np, index, tp->key, tp->key_mask);
5035 if (err)
5036 return err;
5037 err = tcam_assoc_write(np, index, tp->assoc_data);
5038 if (err)
5039 return err;
2d96cf8c
SB		 5040 tp->valid = 1;
5041 cp->tcam_valid_entries++;
a3138df9
DM		 5042
5043 return 0;
5044}
5045
5046static int niu_init_classifier_hw(struct niu *np)
5047{
5048 struct niu_parent *parent = np->parent;
5049 struct niu_classifier *cp = &np->clas;
5050 int i, err;
5051
5052 nw64(H1POLY, cp->h1_init);
5053 nw64(H2POLY, cp->h2_init);
5054
5055 err = niu_init_hostinfo(np);
5056 if (err)
5057 return err;
5058
5059 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
5060 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
5061
5062 vlan_tbl_write(np, i, np->port,
5063 vp->vlan_pref, vp->rdc_num);
5064 }
5065
5066 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
5067 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
5068
5069 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5070 ap->rdc_num, ap->mac_pref);
5071 if (err)
5072 return err;
5073 }
5074
5075 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
5076 int index = i - CLASS_CODE_USER_PROG1;
5077
5078 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5079 if (err)
5080 return err;
5081 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5082 if (err)
5083 return err;
5084 }
5085
5086 err = niu_set_ip_frag_rule(np);
5087 if (err)
5088 return err;
5089
5090 tcam_enable(np, 1);
5091
5092 return 0;
5093}
5094
5095static int niu_zcp_write(struct niu *np, int index, u64 *data)
5096{
5097 nw64(ZCP_RAM_DATA0, data[0]);
5098 nw64(ZCP_RAM_DATA1, data[1]);
5099 nw64(ZCP_RAM_DATA2, data[2]);
5100 nw64(ZCP_RAM_DATA3, data[3]);
5101 nw64(ZCP_RAM_DATA4, data[4]);
5102 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5103 nw64(ZCP_RAM_ACC,
5104 (ZCP_RAM_ACC_WRITE |
5105 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5106 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5107
5108 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5109 1000, 100);
5110}
5111
5112static int niu_zcp_read(struct niu *np, int index, u64 *data)
5113{
5114 int err;
5115
5116 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5117 1000, 100);
5118 if (err) {
f10a1f2e
JP		 5119 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5120 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5121 return err;
5122 }
5123
5124 nw64(ZCP_RAM_ACC,
5125 (ZCP_RAM_ACC_READ |
5126 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
5127 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5128
5129 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5130 1000, 100);
5131 if (err) {
f10a1f2e
JP		 5132 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5133 (unsigned long long)nr64(ZCP_RAM_ACC));
a3138df9
DM		 5134 return err;
5135 }
5136
5137 data[0] = nr64(ZCP_RAM_DATA0);
5138 data[1] = nr64(ZCP_RAM_DATA1);
5139 data[2] = nr64(ZCP_RAM_DATA2);
5140 data[3] = nr64(ZCP_RAM_DATA3);
5141 data[4] = nr64(ZCP_RAM_DATA4);
5142
5143 return 0;
5144}
5145
5146static void niu_zcp_cfifo_reset(struct niu *np)
5147{
5148 u64 val = nr64(RESET_CFIFO);
5149
5150 val |= RESET_CFIFO_RST(np->port);
5151 nw64(RESET_CFIFO, val);
5152 udelay(10);
5153
5154 val &= ~RESET_CFIFO_RST(np->port);
5155 nw64(RESET_CFIFO, val);
5156}
5157
5158static int niu_init_zcp(struct niu *np)
5159{
5160 u64 data[5], rbuf[5];
5161 int i, max, err;
5162
5163 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5164 if (np->port == 0 || np->port == 1)
5165 max = ATLAS_P0_P1_CFIFO_ENTRIES;
5166 else
5167 max = ATLAS_P2_P3_CFIFO_ENTRIES;
5168 } else
5169 max = NIU_CFIFO_ENTRIES;
5170
5171 data[0] = 0;
5172 data[1] = 0;
5173 data[2] = 0;
5174 data[3] = 0;
5175 data[4] = 0;
5176
5177 for (i = 0; i < max; i++) {
5178 err = niu_zcp_write(np, i, data);
5179 if (err)
5180 return err;
5181 err = niu_zcp_read(np, i, rbuf);
5182 if (err)
5183 return err;
5184 }
5185
5186 niu_zcp_cfifo_reset(np);
5187 nw64(CFIFO_ECC(np->port), 0);
5188 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5189 (void) nr64(ZCP_INT_STAT);
5190 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5191
5192 return 0;
5193}
5194
5195static void niu_ipp_write(struct niu *np, int index, u64 *data)
5196{
5197 u64 val = nr64_ipp(IPP_CFIG);
5198
5199 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5200 nw64_ipp(IPP_DFIFO_WR_PTR, index);
5201 nw64_ipp(IPP_DFIFO_WR0, data[0]);
5202 nw64_ipp(IPP_DFIFO_WR1, data[1]);
5203 nw64_ipp(IPP_DFIFO_WR2, data[2]);
5204 nw64_ipp(IPP_DFIFO_WR3, data[3]);
5205 nw64_ipp(IPP_DFIFO_WR4, data[4]);
5206 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5207}
5208
5209static void niu_ipp_read(struct niu *np, int index, u64 *data)
5210{
5211 nw64_ipp(IPP_DFIFO_RD_PTR, index);
5212 data[0] = nr64_ipp(IPP_DFIFO_RD0);
5213 data[1] = nr64_ipp(IPP_DFIFO_RD1);
5214 data[2] = nr64_ipp(IPP_DFIFO_RD2);
5215 data[3] = nr64_ipp(IPP_DFIFO_RD3);
5216 data[4] = nr64_ipp(IPP_DFIFO_RD4);
5217}
5218
5219static int niu_ipp_reset(struct niu *np)
5220{
5221 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
5222 1000, 100, "IPP_CFIG");
5223}
5224
5225static int niu_init_ipp(struct niu *np)
5226{
5227 u64 data[5], rbuf[5], val;
5228 int i, max, err;
5229
5230 if (np->parent->plat_type != PLAT_TYPE_NIU) {
5231 if (np->port == 0 || np->port == 1)
5232 max = ATLAS_P0_P1_DFIFO_ENTRIES;
5233 else
5234 max = ATLAS_P2_P3_DFIFO_ENTRIES;
5235 } else
5236 max = NIU_DFIFO_ENTRIES;
5237
5238 data[0] = 0;
5239 data[1] = 0;
5240 data[2] = 0;
5241 data[3] = 0;
5242 data[4] = 0;
5243
5244 for (i = 0; i < max; i++) {
5245 niu_ipp_write(np, i, data);
5246 niu_ipp_read(np, i, rbuf);
5247 }
5248
5249 (void) nr64_ipp(IPP_INT_STAT);
5250 (void) nr64_ipp(IPP_INT_STAT);
5251
5252 err = niu_ipp_reset(np);
5253 if (err)
5254 return err;
5255
5256 (void) nr64_ipp(IPP_PKT_DIS);
5257 (void) nr64_ipp(IPP_BAD_CS_CNT);
5258 (void) nr64_ipp(IPP_ECC);
5259
5260 (void) nr64_ipp(IPP_INT_STAT);
5261
5262 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
5263
5264 val = nr64_ipp(IPP_CFIG);
5265 val &= ~IPP_CFIG_IP_MAX_PKT;
5266 val |= (IPP_CFIG_IPP_ENABLE |
5267 IPP_CFIG_DFIFO_ECC_EN |
5268 IPP_CFIG_DROP_BAD_CRC |
5269 IPP_CFIG_CKSUM_EN |
5270 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
5271 nw64_ipp(IPP_CFIG, val);
5272
5273 return 0;
5274}
5275
0c3b091b 5276static void niu_handle_led(struct niu *np, int status)
a3138df9 5277{
a3138df9 5278 u64 val;
a3138df9
DM		 5279 val = nr64_mac(XMAC_CONFIG);
5280
5281 if ((np->flags & NIU_FLAGS_10G) != 0 &&
5282 (np->flags & NIU_FLAGS_FIBER) != 0) {
0c3b091b 5283 if (status) {
a3138df9
DM		 5284 val |= XMAC_CONFIG_LED_POLARITY;
5285 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5286 } else {
5287 val |= XMAC_CONFIG_FORCE_LED_ON;
5288 val &= ~XMAC_CONFIG_LED_POLARITY;
5289 }
5290 }
5291
0c3b091b
ML		 5292 nw64_mac(XMAC_CONFIG, val);
5293}
5294
5295static void niu_init_xif_xmac(struct niu *np)
5296{
5297 struct niu_link_config *lp = &np->link_config;
5298 u64 val;
5299
5fbd7e24
MW		 5300 if (np->flags & NIU_FLAGS_XCVR_SERDES) {
5301 val = nr64(MIF_CONFIG);
5302 val |= MIF_CONFIG_ATCA_GE;
5303 nw64(MIF_CONFIG, val);
5304 }
5305
0c3b091b 5306 val = nr64_mac(XMAC_CONFIG);
a3138df9
DM		 5307 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5308
5309 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5310
5311 if (lp->loopback_mode == LOOPBACK_MAC) {
5312 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5313 val |= XMAC_CONFIG_LOOPBACK;
5314 } else {
5315 val &= ~XMAC_CONFIG_LOOPBACK;
5316 }
5317
5318 if (np->flags & NIU_FLAGS_10G) {
5319 val &= ~XMAC_CONFIG_LFS_DISABLE;
5320 } else {
5321 val |= XMAC_CONFIG_LFS_DISABLE;
5fbd7e24
MW		 5322 if (!(np->flags & NIU_FLAGS_FIBER) &&
5323 !(np->flags & NIU_FLAGS_XCVR_SERDES))
a3138df9
DM		 5324 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5325 else
5326 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5327 }
5328
5329 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5330
5331 if (lp->active_speed == SPEED_100)
5332 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5333 else
5334 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5335
5336 nw64_mac(XMAC_CONFIG, val);
5337
5338 val = nr64_mac(XMAC_CONFIG);
5339 val &= ~XMAC_CONFIG_MODE_MASK;
5340 if (np->flags & NIU_FLAGS_10G) {
5341 val |= XMAC_CONFIG_MODE_XGMII;
5342 } else {
38bb045d 5343 if (lp->active_speed == SPEED_1000)
a3138df9 5344 val |= XMAC_CONFIG_MODE_GMII;
38bb045d
CB		 5345 else
5346 val |= XMAC_CONFIG_MODE_MII;
a3138df9
DM		 5347 }
5348
5349 nw64_mac(XMAC_CONFIG, val);
5350}
5351
5352static void niu_init_xif_bmac(struct niu *np)
5353{
5354 struct niu_link_config *lp = &np->link_config;
5355 u64 val;
5356
5357 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5358
5359 if (lp->loopback_mode == LOOPBACK_MAC)
5360 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5361 else
5362 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5363
5364 if (lp->active_speed == SPEED_1000)
5365 val |= BMAC_XIF_CONFIG_GMII_MODE;
5366 else
5367 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5368
5369 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5370 BMAC_XIF_CONFIG_LED_POLARITY);
5371
5372 if (!(np->flags & NIU_FLAGS_10G) &&
5373 !(np->flags & NIU_FLAGS_FIBER) &&
5374 lp->active_speed == SPEED_100)
5375 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5376 else
5377 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5378
5379 nw64_mac(BMAC_XIF_CONFIG, val);
5380}
5381
5382static void niu_init_xif(struct niu *np)
5383{
5384 if (np->flags & NIU_FLAGS_XMAC)
5385 niu_init_xif_xmac(np);
5386 else
5387 niu_init_xif_bmac(np);
5388}
5389
5390static void niu_pcs_mii_reset(struct niu *np)
5391{
5fbd7e24 5392 int limit = 1000;
a3138df9
DM		 5393 u64 val = nr64_pcs(PCS_MII_CTL);
5394 val |= PCS_MII_CTL_RST;
5395 nw64_pcs(PCS_MII_CTL, val);
5fbd7e24
MW		 5396 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5397 udelay(100);
5398 val = nr64_pcs(PCS_MII_CTL);
5399 }
a3138df9
DM		 5400}
5401
5402static void niu_xpcs_reset(struct niu *np)
5403{
5fbd7e24 5404 int limit = 1000;
a3138df9
DM		 5405 u64 val = nr64_xpcs(XPCS_CONTROL1);
5406 val |= XPCS_CONTROL1_RESET;
5407 nw64_xpcs(XPCS_CONTROL1, val);
5fbd7e24
MW		 5408 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5409 udelay(100);
5410 val = nr64_xpcs(XPCS_CONTROL1);
5411 }
a3138df9
DM		 5412}
5413
5414static int niu_init_pcs(struct niu *np)
5415{
5416 struct niu_link_config *lp = &np->link_config;
5417 u64 val;
5418
5fbd7e24
MW		 5419 switch (np->flags & (NIU_FLAGS_10G |
5420 NIU_FLAGS_FIBER |
5421 NIU_FLAGS_XCVR_SERDES)) {
a3138df9
DM		 5422 case NIU_FLAGS_FIBER:
5423 /* 1G fiber */
5424 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5425 nw64_pcs(PCS_DPATH_MODE, 0);
5426 niu_pcs_mii_reset(np);
5427 break;
5428
5429 case NIU_FLAGS_10G:
5430 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
5fbd7e24
MW		 5431 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES:
5432 /* 10G SERDES */
a3138df9
DM		 5433 if (!(np->flags & NIU_FLAGS_XMAC))
5434 return -EINVAL;
5435
5436 /* 10G copper or fiber */
5437 val = nr64_mac(XMAC_CONFIG);
5438 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5439 nw64_mac(XMAC_CONFIG, val);
5440
5441 niu_xpcs_reset(np);
5442
5443 val = nr64_xpcs(XPCS_CONTROL1);
5444 if (lp->loopback_mode == LOOPBACK_PHY)
5445 val |= XPCS_CONTROL1_LOOPBACK;
5446 else
5447 val &= ~XPCS_CONTROL1_LOOPBACK;
5448 nw64_xpcs(XPCS_CONTROL1, val);
5449
5450 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
5452 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
5453 break;
5454
5fbd7e24
MW		 5455
5456 case NIU_FLAGS_XCVR_SERDES:
5457 /* 1G SERDES */
5458 niu_pcs_mii_reset(np);
5459 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
5460 nw64_pcs(PCS_DPATH_MODE, 0);
5461 break;
5462
a3138df9
DM		 5463 case 0:
5464 /* 1G copper */
5fbd7e24
MW		 5465 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER:
5466 /* 1G RGMII FIBER */
a3138df9
DM		 5467 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
5468 niu_pcs_mii_reset(np);
5469 break;
5470
5471 default:
5472 return -EINVAL;
5473 }
5474
5475 return 0;
5476}
5477
5478static int niu_reset_tx_xmac(struct niu *np)
5479{
5480 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
5481 (XTXMAC_SW_RST_REG_RS |
5482 XTXMAC_SW_RST_SOFT_RST),
5483 1000, 100, "XTXMAC_SW_RST");
5484}
5485
5486static int niu_reset_tx_bmac(struct niu *np)
5487{
5488 int limit;
5489
5490 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
5491 limit = 1000;
5492 while (--limit >= 0) {
5493 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
5494 break;
5495 udelay(100);
5496 }
5497 if (limit < 0) {
f10a1f2e 5498 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5499 np->port,
5500 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
5501 return -ENODEV;
5502 }
5503
5504 return 0;
5505}
5506
5507static int niu_reset_tx_mac(struct niu *np)
5508{
5509 if (np->flags & NIU_FLAGS_XMAC)
5510 return niu_reset_tx_xmac(np);
5511 else
5512 return niu_reset_tx_bmac(np);
5513}
5514
5515static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
5516{
5517 u64 val;
5518
5519 val = nr64_mac(XMAC_MIN);
5520 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5521 XMAC_MIN_RX_MIN_PKT_SIZE);
5522 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5523 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5524 nw64_mac(XMAC_MIN, val);
5525
5526 nw64_mac(XMAC_MAX, max);
5527
5528 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
5529
5530 val = nr64_mac(XMAC_IPG);
5531 if (np->flags & NIU_FLAGS_10G) {
5532 val &= ~XMAC_IPG_IPG_XGMII;
5533 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5534 } else {
5535 val &= ~XMAC_IPG_IPG_MII_GMII;
5536 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5537 }
5538 nw64_mac(XMAC_IPG, val);
5539
5540 val = nr64_mac(XMAC_CONFIG);
5541 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5542 XMAC_CONFIG_STRETCH_MODE |
5543 XMAC_CONFIG_VAR_MIN_IPG_EN |
5544 XMAC_CONFIG_TX_ENABLE);
5545 nw64_mac(XMAC_CONFIG, val);
5546
5547 nw64_mac(TXMAC_FRM_CNT, 0);
5548 nw64_mac(TXMAC_BYTE_CNT, 0);
5549}
5550
5551static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
5552{
5553 u64 val;
5554
5555 nw64_mac(BMAC_MIN_FRAME, min);
5556 nw64_mac(BMAC_MAX_FRAME, max);
5557
5558 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
5559 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
5560 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
5561
5562 val = nr64_mac(BTXMAC_CONFIG);
5563 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5564 BTXMAC_CONFIG_ENABLE);
5565 nw64_mac(BTXMAC_CONFIG, val);
5566}
5567
5568static void niu_init_tx_mac(struct niu *np)
5569{
5570 u64 min, max;
5571
5572 min = 64;
5573 if (np->dev->mtu > ETH_DATA_LEN)
5574 max = 9216;
5575 else
5576 max = 1522;
5577
5578 /* The XMAC_MIN register only accepts values for TX min which
5579 * have the low 3 bits cleared.
5580 */
8c87df45 5581 BUG_ON(min & 0x7);
a3138df9
DM		 5582
5583 if (np->flags & NIU_FLAGS_XMAC)
5584 niu_init_tx_xmac(np, min, max);
5585 else
5586 niu_init_tx_bmac(np, min, max);
5587}
5588
5589static int niu_reset_rx_xmac(struct niu *np)
5590{
5591 int limit;
5592
5593 nw64_mac(XRXMAC_SW_RST,
5594 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
5595 limit = 1000;
5596 while (--limit >= 0) {
5597 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
5598 XRXMAC_SW_RST_SOFT_RST)))
f10a1f2e 5599 break;
a3138df9
DM		 5600 udelay(100);
5601 }
5602 if (limit < 0) {
f10a1f2e 5603 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5604 np->port,
5605 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
5606 return -ENODEV;
5607 }
5608
5609 return 0;
5610}
5611
5612static int niu_reset_rx_bmac(struct niu *np)
5613{
5614 int limit;
5615
5616 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
5617 limit = 1000;
5618 while (--limit >= 0) {
5619 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
5620 break;
5621 udelay(100);
5622 }
5623 if (limit < 0) {
f10a1f2e 5624 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
a3138df9
DM		 5625 np->port,
5626 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
5627 return -ENODEV;
5628 }
5629
5630 return 0;
5631}
5632
5633static int niu_reset_rx_mac(struct niu *np)
5634{
5635 if (np->flags & NIU_FLAGS_XMAC)
5636 return niu_reset_rx_xmac(np);
5637 else
5638 return niu_reset_rx_bmac(np);
5639}
5640
5641static void niu_init_rx_xmac(struct niu *np)
5642{
5643 struct niu_parent *parent = np->parent;
5644 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5645 int first_rdc_table = tp->first_table_num;
5646 unsigned long i;
5647 u64 val;
5648
5649 nw64_mac(XMAC_ADD_FILT0, 0);
5650 nw64_mac(XMAC_ADD_FILT1, 0);
5651 nw64_mac(XMAC_ADD_FILT2, 0);
5652 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
5653 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
5654 for (i = 0; i < MAC_NUM_HASH; i++)
5655 nw64_mac(XMAC_HASH_TBL(i), 0);
5656 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
5657 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5658 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5659
5660 val = nr64_mac(XMAC_CONFIG);
5661 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5662 XMAC_CONFIG_PROMISCUOUS |
5663 XMAC_CONFIG_PROMISC_GROUP |
5664 XMAC_CONFIG_ERR_CHK_DIS |
5665 XMAC_CONFIG_RX_CRC_CHK_DIS |
5666 XMAC_CONFIG_RESERVED_MULTICAST |
5667 XMAC_CONFIG_RX_CODEV_CHK_DIS |
5668 XMAC_CONFIG_ADDR_FILTER_EN |
5669 XMAC_CONFIG_RCV_PAUSE_ENABLE |
5670 XMAC_CONFIG_STRIP_CRC |
5671 XMAC_CONFIG_PASS_FLOW_CTRL |
5672 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
5673 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5674 nw64_mac(XMAC_CONFIG, val);
5675
5676 nw64_mac(RXMAC_BT_CNT, 0);
5677 nw64_mac(RXMAC_BC_FRM_CNT, 0);
5678 nw64_mac(RXMAC_MC_FRM_CNT, 0);
5679 nw64_mac(RXMAC_FRAG_CNT, 0);
5680 nw64_mac(RXMAC_HIST_CNT1, 0);
5681 nw64_mac(RXMAC_HIST_CNT2, 0);
5682 nw64_mac(RXMAC_HIST_CNT3, 0);
5683 nw64_mac(RXMAC_HIST_CNT4, 0);
5684 nw64_mac(RXMAC_HIST_CNT5, 0);
5685 nw64_mac(RXMAC_HIST_CNT6, 0);
5686 nw64_mac(RXMAC_HIST_CNT7, 0);
5687 nw64_mac(RXMAC_MPSZER_CNT, 0);
5688 nw64_mac(RXMAC_CRC_ER_CNT, 0);
5689 nw64_mac(RXMAC_CD_VIO_CNT, 0);
5690 nw64_mac(LINK_FAULT_CNT, 0);
5691}
5692
5693static void niu_init_rx_bmac(struct niu *np)
5694{
5695 struct niu_parent *parent = np->parent;
5696 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5697 int first_rdc_table = tp->first_table_num;
5698 unsigned long i;
5699 u64 val;
5700
5701 nw64_mac(BMAC_ADD_FILT0, 0);
5702 nw64_mac(BMAC_ADD_FILT1, 0);
5703 nw64_mac(BMAC_ADD_FILT2, 0);
5704 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
5705 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
5706 for (i = 0; i < MAC_NUM_HASH; i++)
5707 nw64_mac(BMAC_HASH_TBL(i), 0);
5708 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
5709 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
5710 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
5711
5712 val = nr64_mac(BRXMAC_CONFIG);
5713 val &= ~(BRXMAC_CONFIG_ENABLE |
5714 BRXMAC_CONFIG_STRIP_PAD |
5715 BRXMAC_CONFIG_STRIP_FCS |
5716 BRXMAC_CONFIG_PROMISC |
5717 BRXMAC_CONFIG_PROMISC_GRP |
5718 BRXMAC_CONFIG_ADDR_FILT_EN |
5719 BRXMAC_CONFIG_DISCARD_DIS);
5720 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5721 nw64_mac(BRXMAC_CONFIG, val);
5722
5723 val = nr64_mac(BMAC_ADDR_CMPEN);
5724 val |= BMAC_ADDR_CMPEN_EN0;
5725 nw64_mac(BMAC_ADDR_CMPEN, val);
5726}
5727
5728static void niu_init_rx_mac(struct niu *np)
5729{
5730 niu_set_primary_mac(np, np->dev->dev_addr);
5731
5732 if (np->flags & NIU_FLAGS_XMAC)
5733 niu_init_rx_xmac(np);
5734 else
5735 niu_init_rx_bmac(np);
5736}
5737
5738static void niu_enable_tx_xmac(struct niu *np, int on)
5739{
5740 u64 val = nr64_mac(XMAC_CONFIG);
5741
5742 if (on)
5743 val |= XMAC_CONFIG_TX_ENABLE;
5744 else
5745 val &= ~XMAC_CONFIG_TX_ENABLE;
5746 nw64_mac(XMAC_CONFIG, val);
5747}
5748
5749static void niu_enable_tx_bmac(struct niu *np, int on)
5750{
5751 u64 val = nr64_mac(BTXMAC_CONFIG);
5752
5753 if (on)
5754 val |= BTXMAC_CONFIG_ENABLE;
5755 else
5756 val &= ~BTXMAC_CONFIG_ENABLE;
5757 nw64_mac(BTXMAC_CONFIG, val);
5758}
5759
5760static void niu_enable_tx_mac(struct niu *np, int on)
5761{
5762 if (np->flags & NIU_FLAGS_XMAC)
5763 niu_enable_tx_xmac(np, on);
5764 else
5765 niu_enable_tx_bmac(np, on);
5766}
5767
5768static void niu_enable_rx_xmac(struct niu *np, int on)
5769{
5770 u64 val = nr64_mac(XMAC_CONFIG);
5771
5772 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5773 XMAC_CONFIG_PROMISCUOUS);
5774
5775 if (np->flags & NIU_FLAGS_MCAST)
5776 val |= XMAC_CONFIG_HASH_FILTER_EN;
5777 if (np->flags & NIU_FLAGS_PROMISC)
5778 val |= XMAC_CONFIG_PROMISCUOUS;
5779
5780 if (on)
5781 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5782 else
5783 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5784 nw64_mac(XMAC_CONFIG, val);
5785}
5786
5787static void niu_enable_rx_bmac(struct niu *np, int on)
5788{
5789 u64 val = nr64_mac(BRXMAC_CONFIG);
5790
5791 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5792 BRXMAC_CONFIG_PROMISC);
5793
5794 if (np->flags & NIU_FLAGS_MCAST)
5795 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5796 if (np->flags & NIU_FLAGS_PROMISC)
5797 val |= BRXMAC_CONFIG_PROMISC;
5798
5799 if (on)
5800 val |= BRXMAC_CONFIG_ENABLE;
5801 else
5802 val &= ~BRXMAC_CONFIG_ENABLE;
5803 nw64_mac(BRXMAC_CONFIG, val);
5804}
5805
5806static void niu_enable_rx_mac(struct niu *np, int on)
5807{
5808 if (np->flags & NIU_FLAGS_XMAC)
5809 niu_enable_rx_xmac(np, on);
5810 else
5811 niu_enable_rx_bmac(np, on);
5812}
5813
5814static int niu_init_mac(struct niu *np)
5815{
5816 int err;
5817
5818 niu_init_xif(np);
5819 err = niu_init_pcs(np);
5820 if (err)
5821 return err;
5822
5823 err = niu_reset_tx_mac(np);
5824 if (err)
5825 return err;
5826 niu_init_tx_mac(np);
5827 err = niu_reset_rx_mac(np);
5828 if (err)
5829 return err;
5830 niu_init_rx_mac(np);
5831
5832 /* This looks hookey but the RX MAC reset we just did will
5833 * undo some of the state we setup in niu_init_tx_mac() so we
5834 * have to call it again. In particular, the RX MAC reset will
5835 * set the XMAC_MAX register back to it's default value.
5836 */
5837 niu_init_tx_mac(np);
5838 niu_enable_tx_mac(np, 1);
5839
5840 niu_enable_rx_mac(np, 1);
5841
5842 return 0;
5843}
5844
5845static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5846{
5847 (void) niu_tx_channel_stop(np, rp->tx_channel);
5848}
5849
5850static void niu_stop_tx_channels(struct niu *np)
5851{
5852 int i;
5853
5854 for (i = 0; i < np->num_tx_rings; i++) {
5855 struct tx_ring_info *rp = &np->tx_rings[i];
5856
5857 niu_stop_one_tx_channel(np, rp);
5858 }
5859}
5860
5861static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
5862{
5863 (void) niu_tx_channel_reset(np, rp->tx_channel);
5864}
5865
5866static void niu_reset_tx_channels(struct niu *np)
5867{
5868 int i;
5869
5870 for (i = 0; i < np->num_tx_rings; i++) {
5871 struct tx_ring_info *rp = &np->tx_rings[i];
5872
5873 niu_reset_one_tx_channel(np, rp);
5874 }
5875}
5876
5877static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5878{
5879 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
5880}
5881
5882static void niu_stop_rx_channels(struct niu *np)
5883{
5884 int i;
5885
5886 for (i = 0; i < np->num_rx_rings; i++) {
5887 struct rx_ring_info *rp = &np->rx_rings[i];
5888
5889 niu_stop_one_rx_channel(np, rp);
5890 }
5891}
5892
5893static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
5894{
5895 int channel = rp->rx_channel;
5896
5897 (void) niu_rx_channel_reset(np, channel);
5898 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5899 nw64(RX_DMA_CTL_STAT(channel), 0);
5900 (void) niu_enable_rx_channel(np, channel, 0);
5901}
5902
5903static void niu_reset_rx_channels(struct niu *np)
5904{
5905 int i;
5906
5907 for (i = 0; i < np->num_rx_rings; i++) {
5908 struct rx_ring_info *rp = &np->rx_rings[i];
5909
5910 niu_reset_one_rx_channel(np, rp);
5911 }
5912}
5913
5914static void niu_disable_ipp(struct niu *np)
5915{
5916 u64 rd, wr, val;
5917 int limit;
5918
5919 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5920 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5921 limit = 100;
5922 while (--limit >= 0 && (rd != wr)) {
5923 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
5924 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
5925 }
5926 if (limit < 0 &&
5927 (rd != 0 && wr != 1)) {
f10a1f2e
JP		 5928 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5929 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR),
5930 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR));
a3138df9
DM		 5931 }
5932
5933 val = nr64_ipp(IPP_CFIG);
5934 val &= ~(IPP_CFIG_IPP_ENABLE |
5935 IPP_CFIG_DFIFO_ECC_EN |
5936 IPP_CFIG_DROP_BAD_CRC |
5937 IPP_CFIG_CKSUM_EN);
5938 nw64_ipp(IPP_CFIG, val);
5939
5940 (void) niu_ipp_reset(np);
5941}
5942
5943static int niu_init_hw(struct niu *np)
5944{
5945 int i, err;
5946
f10a1f2e 5947 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n");
a3138df9
DM		 5948 niu_txc_enable_port(np, 1);
5949 niu_txc_port_dma_enable(np, 1);
5950 niu_txc_set_imask(np, 0);
5951
f10a1f2e 5952 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n");
a3138df9
DM		 5953 for (i = 0; i < np->num_tx_rings; i++) {
5954 struct tx_ring_info *rp = &np->tx_rings[i];
5955
5956 err = niu_init_one_tx_channel(np, rp);
5957 if (err)
5958 return err;
5959 }
5960
f10a1f2e 5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n");
a3138df9
DM		 5962 err = niu_init_rx_channels(np);
5963 if (err)
5964 goto out_uninit_tx_channels;
5965
f10a1f2e 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n");
a3138df9
DM		 5967 err = niu_init_classifier_hw(np);
5968 if (err)
5969 goto out_uninit_rx_channels;
5970
f10a1f2e 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n");
a3138df9
DM		 5972 err = niu_init_zcp(np);
5973 if (err)
5974 goto out_uninit_rx_channels;
5975
f10a1f2e 5976 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n");
a3138df9
DM		 5977 err = niu_init_ipp(np);
5978 if (err)
5979 goto out_uninit_rx_channels;
5980
f10a1f2e 5981 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n");
a3138df9
DM		 5982 err = niu_init_mac(np);
5983 if (err)
5984 goto out_uninit_ipp;
5985
5986 return 0;
5987
5988out_uninit_ipp:
f10a1f2e 5989 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n");
a3138df9
DM		 5990 niu_disable_ipp(np);
5991
5992out_uninit_rx_channels:
f10a1f2e 5993 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n");
a3138df9
DM		 5994 niu_stop_rx_channels(np);
5995 niu_reset_rx_channels(np);
5996
5997out_uninit_tx_channels:
f10a1f2e 5998 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n");
a3138df9
DM		 5999 niu_stop_tx_channels(np);
6000 niu_reset_tx_channels(np);
6001
6002 return err;
6003}
6004
6005static void niu_stop_hw(struct niu *np)
6006{
f10a1f2e 6007 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n");
a3138df9
DM		 6008 niu_enable_interrupts(np, 0);
6009
f10a1f2e 6010 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n");
a3138df9
DM		 6011 niu_enable_rx_mac(np, 0);
6012
f10a1f2e 6013 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n");
a3138df9
DM		 6014 niu_disable_ipp(np);
6015
f10a1f2e 6016 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n");
a3138df9
DM		 6017 niu_stop_tx_channels(np);
6018
f10a1f2e 6019 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n");
a3138df9
DM		 6020 niu_stop_rx_channels(np);
6021
f10a1f2e 6022 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n");
a3138df9
DM		 6023 niu_reset_tx_channels(np);
6024
f10a1f2e 6025 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n");
a3138df9
DM		 6026 niu_reset_rx_channels(np);
6027}
6028
70340d72
RO		 6029static void niu_set_irq_name(struct niu *np)
6030{
6031 int port = np->port;
6032 int i, j = 1;
6033
6034 sprintf(np->irq_name[0], "%s:MAC", np->dev->name);
6035
6036 if (port == 0) {
6037 sprintf(np->irq_name[1], "%s:MIF", np->dev->name);
6038 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name);
6039 j = 3;
6040 }
6041
6042 for (i = 0; i < np->num_ldg - j; i++) {
6043 if (i < np->num_rx_rings)
6044 sprintf(np->irq_name[i+j], "%s-rx-%d",
6045 np->dev->name, i);
6046 else if (i < np->num_tx_rings + np->num_rx_rings)
6047 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name,
6048 i - np->num_rx_rings);
6049 }
6050}
6051
a3138df9
DM		 6052static int niu_request_irq(struct niu *np)
6053{
6054 int i, j, err;
6055
70340d72
RO		 6056 niu_set_irq_name(np);
6057
a3138df9
DM		 6058 err = 0;
6059 for (i = 0; i < np->num_ldg; i++) {
6060 struct niu_ldg *lp = &np->ldg[i];
6061
6062 err = request_irq(lp->irq, niu_interrupt,
6063 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
70340d72 6064 np->irq_name[i], lp);
a3138df9
DM		 6065 if (err)
6066 goto out_free_irqs;
6067
6068 }
6069
6070 return 0;
6071
6072out_free_irqs:
6073 for (j = 0; j < i; j++) {
6074 struct niu_ldg *lp = &np->ldg[j];
6075
6076 free_irq(lp->irq, lp);
6077 }
6078 return err;
6079}
6080
6081static void niu_free_irq(struct niu *np)
6082{
6083 int i;
6084
6085 for (i = 0; i < np->num_ldg; i++) {
6086 struct niu_ldg *lp = &np->ldg[i];
6087
6088 free_irq(lp->irq, lp);
6089 }
6090}
6091
6092static void niu_enable_napi(struct niu *np)
6093{
6094 int i;
6095
6096 for (i = 0; i < np->num_ldg; i++)
6097 napi_enable(&np->ldg[i].napi);
6098}
6099
6100static void niu_disable_napi(struct niu *np)
6101{
6102 int i;
6103
6104 for (i = 0; i < np->num_ldg; i++)
6105 napi_disable(&np->ldg[i].napi);
6106}
6107
6108static int niu_open(struct net_device *dev)
6109{
6110 struct niu *np = netdev_priv(dev);
6111 int err;
6112
6113 netif_carrier_off(dev);
6114
6115 err = niu_alloc_channels(np);
6116 if (err)
6117 goto out_err;
6118
6119 err = niu_enable_interrupts(np, 0);
6120 if (err)
6121 goto out_free_channels;
6122
6123 err = niu_request_irq(np);
6124 if (err)
6125 goto out_free_channels;
6126
6127 niu_enable_napi(np);
6128
6129 spin_lock_irq(&np->lock);
6130
6131 err = niu_init_hw(np);
6132 if (!err) {
6133 init_timer(&np->timer);
6134 np->timer.expires = jiffies + HZ;
6135 np->timer.data = (unsigned long) np;
6136 np->timer.function = niu_timer;
6137
6138 err = niu_enable_interrupts(np, 1);
6139 if (err)
6140 niu_stop_hw(np);
6141 }
6142
6143 spin_unlock_irq(&np->lock);
6144
6145 if (err) {
6146 niu_disable_napi(np);
6147 goto out_free_irq;
6148 }
6149
b4c21639 6150 netif_tx_start_all_queues(dev);
a3138df9
DM		 6151
6152 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6153 netif_carrier_on(dev);
6154
6155 add_timer(&np->timer);
6156
6157 return 0;
6158
6159out_free_irq:
6160 niu_free_irq(np);
6161
6162out_free_channels:
6163 niu_free_channels(np);
6164
6165out_err:
6166 return err;
6167}
6168
6169static void niu_full_shutdown(struct niu *np, struct net_device *dev)
6170{
6171 cancel_work_sync(&np->reset_task);
6172
6173 niu_disable_napi(np);
b4c21639 6174 netif_tx_stop_all_queues(dev);
a3138df9
DM		 6175
6176 del_timer_sync(&np->timer);
6177
6178 spin_lock_irq(&np->lock);
6179
6180 niu_stop_hw(np);
6181
6182 spin_unlock_irq(&np->lock);
6183}
6184
6185static int niu_close(struct net_device *dev)
6186{
6187 struct niu *np = netdev_priv(dev);
6188
6189 niu_full_shutdown(np, dev);
6190
6191 niu_free_irq(np);
6192
6193 niu_free_channels(np);
6194
0c3b091b
ML		 6195 niu_handle_led(np, 0);
6196
a3138df9
DM		 6197 return 0;
6198}
6199
6200static void niu_sync_xmac_stats(struct niu *np)
6201{
6202 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
6203
6204 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
6205 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
6206
6207 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
6208 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
6209 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
6210 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
6211 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
6212 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
6213 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
6214 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
6215 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
6216 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
6217 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
6218 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
6219 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
6220 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
6221 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
6222 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
6223}
6224
6225static void niu_sync_bmac_stats(struct niu *np)
6226{
6227 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
6228
6229 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
6230 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
6231
6232 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
6233 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6234 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
6235 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
6236}
6237
6238static void niu_sync_mac_stats(struct niu *np)
6239{
6240 if (np->flags & NIU_FLAGS_XMAC)
6241 niu_sync_xmac_stats(np);
6242 else
6243 niu_sync_bmac_stats(np);
6244}
6245
6246static void niu_get_rx_stats(struct niu *np)
6247{
6248 unsigned long pkts, dropped, errors, bytes;
6249 int i;
6250
6251 pkts = dropped = errors = bytes = 0;
6252 for (i = 0; i < np->num_rx_rings; i++) {
6253 struct rx_ring_info *rp = &np->rx_rings[i];
6254
b8a606b8
JDB		 6255 niu_sync_rx_discard_stats(np, rp, 0);
6256
a3138df9
DM		 6257 pkts += rp->rx_packets;
6258 bytes += rp->rx_bytes;
6259 dropped += rp->rx_dropped;
6260 errors += rp->rx_errors;
6261 }
9fd42876
IJ		 6262 np->dev->stats.rx_packets = pkts;
6263 np->dev->stats.rx_bytes = bytes;
6264 np->dev->stats.rx_dropped = dropped;
6265 np->dev->stats.rx_errors = errors;
a3138df9
DM		 6266}
6267
6268static void niu_get_tx_stats(struct niu *np)
6269{
6270 unsigned long pkts, errors, bytes;
6271 int i;
6272
6273 pkts = errors = bytes = 0;
6274 for (i = 0; i < np->num_tx_rings; i++) {
6275 struct tx_ring_info *rp = &np->tx_rings[i];
6276
6277 pkts += rp->tx_packets;
6278 bytes += rp->tx_bytes;
6279 errors += rp->tx_errors;
6280 }
9fd42876
IJ		 6281 np->dev->stats.tx_packets = pkts;
6282 np->dev->stats.tx_bytes = bytes;
6283 np->dev->stats.tx_errors = errors;
a3138df9
DM		 6284}
6285
6286static struct net_device_stats *niu_get_stats(struct net_device *dev)
6287{
6288 struct niu *np = netdev_priv(dev);
6289
6290 niu_get_rx_stats(np);
6291 niu_get_tx_stats(np);
6292
9fd42876 6293 return &dev->stats;
a3138df9
DM		 6294}
6295
6296static void niu_load_hash_xmac(struct niu *np, u16 *hash)
6297{
6298 int i;
6299
6300 for (i = 0; i < 16; i++)
6301 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
6302}
6303
6304static void niu_load_hash_bmac(struct niu *np, u16 *hash)
6305{
6306 int i;
6307
6308 for (i = 0; i < 16; i++)
6309 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
6310}
6311
6312static void niu_load_hash(struct niu *np, u16 *hash)
6313{
6314 if (np->flags & NIU_FLAGS_XMAC)
6315 niu_load_hash_xmac(np, hash);
6316 else
6317 niu_load_hash_bmac(np, hash);
6318}
6319
6320static void niu_set_rx_mode(struct net_device *dev)
6321{
6322 struct niu *np = netdev_priv(dev);
6323 int i, alt_cnt, err;
ccffad25 6324 struct netdev_hw_addr *ha;
a3138df9
DM		 6325 unsigned long flags;
6326 u16 hash[16] = { 0, };
6327
6328 spin_lock_irqsave(&np->lock, flags);
6329 niu_enable_rx_mac(np, 0);
6330
6331 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
6332 if (dev->flags & IFF_PROMISC)
6333 np->flags |= NIU_FLAGS_PROMISC;
4cd24eaf 6334 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev)))
a3138df9
DM		 6335 np->flags |= NIU_FLAGS_MCAST;
6336
32e7bfc4 6337 alt_cnt = netdev_uc_count(dev);
a3138df9
DM		 6338 if (alt_cnt > niu_num_alt_addr(np)) {
6339 alt_cnt = 0;
6340 np->flags |= NIU_FLAGS_PROMISC;
6341 }
6342
6343 if (alt_cnt) {
6344 int index = 0;
6345
32e7bfc4 6346 netdev_for_each_uc_addr(ha, dev) {
ccffad25 6347 err = niu_set_alt_mac(np, index, ha->addr);
a3138df9 6348 if (err)
f10a1f2e
JP		 6349 netdev_warn(dev, "Error %d adding alt mac %d\n",
6350 err, index);
a3138df9
DM		 6351 err = niu_enable_alt_mac(np, index, 1);
6352 if (err)
f10a1f2e
JP		 6353 netdev_warn(dev, "Error %d enabling alt mac %d\n",
6354 err, index);
a3138df9
DM		 6355
6356 index++;
6357 }
6358 } else {
3b5bcede
MW		 6359 int alt_start;
6360 if (np->flags & NIU_FLAGS_XMAC)
6361 alt_start = 0;
6362 else
6363 alt_start = 1;
6364 for (i = alt_start; i < niu_num_alt_addr(np); i++) {
a3138df9
DM		 6365 err = niu_enable_alt_mac(np, i, 0);
6366 if (err)
f10a1f2e
JP		 6367 netdev_warn(dev, "Error %d disabling alt mac %d\n",
6368 err, i);
a3138df9
DM		 6369 }
6370 }
6371 if (dev->flags & IFF_ALLMULTI) {
6372 for (i = 0; i < 16; i++)
6373 hash[i] = 0xffff;
4cd24eaf 6374 } else if (!netdev_mc_empty(dev)) {
22bedad3
JP		 6375 netdev_for_each_mc_addr(ha, dev) {
6376 u32 crc = ether_crc_le(ETH_ALEN, ha->addr);
a3138df9
DM		 6377
6378 crc >>= 24;
6379 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
6380 }
6381 }
6382
6383 if (np->flags & NIU_FLAGS_MCAST)
6384 niu_load_hash(np, hash);
6385
6386 niu_enable_rx_mac(np, 1);
6387 spin_unlock_irqrestore(&np->lock, flags);
6388}
6389
6390static int niu_set_mac_addr(struct net_device *dev, void *p)
6391{
6392 struct niu *np = netdev_priv(dev);
6393 struct sockaddr *addr = p;
6394 unsigned long flags;
6395
6396 if (!is_valid_ether_addr(addr->sa_data))
6397 return -EINVAL;
6398
6399 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
6400
6401 if (!netif_running(dev))
6402 return 0;
6403
6404 spin_lock_irqsave(&np->lock, flags);
6405 niu_enable_rx_mac(np, 0);
6406 niu_set_primary_mac(np, dev->dev_addr);
6407 niu_enable_rx_mac(np, 1);
6408 spin_unlock_irqrestore(&np->lock, flags);
6409
6410 return 0;
6411}
6412
6413static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6414{
6415 return -EOPNOTSUPP;
6416}
6417
6418static void niu_netif_stop(struct niu *np)
6419{
6420 np->dev->trans_start = jiffies; /* prevent tx timeout */
6421
6422 niu_disable_napi(np);
6423
6424 netif_tx_disable(np->dev);
6425}
6426
6427static void niu_netif_start(struct niu *np)
6428{
6429 /* NOTE: unconditional netif_wake_queue is only appropriate
6430 * so long as all callers are assured to have free tx slots
6431 * (such as after niu_init_hw).
6432 */
b4c21639 6433 netif_tx_wake_all_queues(np->dev);
a3138df9
DM		 6434
6435 niu_enable_napi(np);
6436
6437 niu_enable_interrupts(np, 1);
6438}
6439
cff502a3
SB		 6440static void niu_reset_buffers(struct niu *np)
6441{
6442 int i, j, k, err;
6443
6444 if (np->rx_rings) {
6445 for (i = 0; i < np->num_rx_rings; i++) {
6446 struct rx_ring_info *rp = &np->rx_rings[i];
6447
6448 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) {
6449 struct page *page;
6450
6451 page = rp->rxhash[j];
6452 while (page) {
6453 struct page *next =
6454 (struct page *) page->mapping;
6455 u64 base = page->index;
6456 base = base >> RBR_DESCR_ADDR_SHIFT;
6457 rp->rbr[k++] = cpu_to_le32(base);
6458 page = next;
6459 }
6460 }
6461 for (; k < MAX_RBR_RING_SIZE; k++) {
6462 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6463 if (unlikely(err))
6464 break;
6465 }
6466
6467 rp->rbr_index = rp->rbr_table_size - 1;
6468 rp->rcr_index = 0;
6469 rp->rbr_pending = 0;
6470 rp->rbr_refill_pending = 0;
6471 }
6472 }
6473 if (np->tx_rings) {
6474 for (i = 0; i < np->num_tx_rings; i++) {
6475 struct tx_ring_info *rp = &np->tx_rings[i];
6476
6477 for (j = 0; j < MAX_TX_RING_SIZE; j++) {
6478 if (rp->tx_buffs[j].skb)
6479 (void) release_tx_packet(np, rp, j);
6480 }
6481
6482 rp->pending = MAX_TX_RING_SIZE;
6483 rp->prod = 0;
6484 rp->cons = 0;
6485 rp->wrap_bit = 0;
6486 }
6487 }
6488}
6489
a3138df9
DM		 6490static void niu_reset_task(struct work_struct *work)
6491{
6492 struct niu *np = container_of(work, struct niu, reset_task);
6493 unsigned long flags;
6494 int err;
6495
6496 spin_lock_irqsave(&np->lock, flags);
6497 if (!netif_running(np->dev)) {
6498 spin_unlock_irqrestore(&np->lock, flags);
6499 return;
6500 }
6501
6502 spin_unlock_irqrestore(&np->lock, flags);
6503
6504 del_timer_sync(&np->timer);
6505
6506 niu_netif_stop(np);
6507
6508 spin_lock_irqsave(&np->lock, flags);
6509
6510 niu_stop_hw(np);
6511
cff502a3
SB		 6512 spin_unlock_irqrestore(&np->lock, flags);
6513
6514 niu_reset_buffers(np);
6515
6516 spin_lock_irqsave(&np->lock, flags);
6517
a3138df9
DM		 6518 err = niu_init_hw(np);
6519 if (!err) {
6520 np->timer.expires = jiffies + HZ;
6521 add_timer(&np->timer);
6522 niu_netif_start(np);
6523 }
6524
6525 spin_unlock_irqrestore(&np->lock, flags);
6526}
6527
6528static void niu_tx_timeout(struct net_device *dev)
6529{
6530 struct niu *np = netdev_priv(dev);
6531
f10a1f2e 6532 dev_err(np->device, "%s: Transmit timed out, resetting\n",
a3138df9
DM		 6533 dev->name);
6534
6535 schedule_work(&np->reset_task);
6536}
6537
6538static void niu_set_txd(struct tx_ring_info *rp, int index,
6539 u64 mapping, u64 len, u64 mark,
6540 u64 n_frags)
6541{
6542 __le64 *desc = &rp->descr[index];
6543
6544 *desc = cpu_to_le64(mark |
6545 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
6546 (len << TX_DESC_TR_LEN_SHIFT) |
6547 (mapping & TX_DESC_SAD));
6548}
6549
6550static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
6551 u64 pad_bytes, u64 len)
6552{
6553 u16 eth_proto, eth_proto_inner;
6554 u64 csum_bits, l3off, ihl, ret;
6555 u8 ip_proto;
6556 int ipv6;
6557
6558 eth_proto = be16_to_cpu(ehdr->h_proto);
6559 eth_proto_inner = eth_proto;
6560 if (eth_proto == ETH_P_8021Q) {
6561 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
6562 __be16 val = vp->h_vlan_encapsulated_proto;
6563
6564 eth_proto_inner = be16_to_cpu(val);
6565 }
6566
6567 ipv6 = ihl = 0;
6568 switch (skb->protocol) {
09640e63 6569 case cpu_to_be16(ETH_P_IP):
a3138df9
DM		 6570 ip_proto = ip_hdr(skb)->protocol;
6571 ihl = ip_hdr(skb)->ihl;
6572 break;
09640e63 6573 case cpu_to_be16(ETH_P_IPV6):
a3138df9
DM		 6574 ip_proto = ipv6_hdr(skb)->nexthdr;
6575 ihl = (40 >> 2);
6576 ipv6 = 1;
6577 break;
6578 default:
6579 ip_proto = ihl = 0;
6580 break;
6581 }
6582
6583 csum_bits = TXHDR_CSUM_NONE;
6584 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6585 u64 start, stuff;
6586
6587 csum_bits = (ip_proto == IPPROTO_TCP ?
6588 TXHDR_CSUM_TCP :
6589 (ip_proto == IPPROTO_UDP ?
6590 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
6591
6592 start = skb_transport_offset(skb) -
6593 (pad_bytes + sizeof(struct tx_pkt_hdr));
6594 stuff = start + skb->csum_offset;
6595
6596 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
6597 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
6598 }
6599
6600 l3off = skb_network_offset(skb) -
6601 (pad_bytes + sizeof(struct tx_pkt_hdr));
6602
6603 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
6604 (len << TXHDR_LEN_SHIFT) |
6605 ((l3off / 2) << TXHDR_L3START_SHIFT) |
6606 (ihl << TXHDR_IHL_SHIFT) |
6607 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
6608 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
6609 (ipv6 ? TXHDR_IP_VER : 0) |
6610 csum_bits);
6611
6612 return ret;
6613}
6614
61357325
SH		 6615static netdev_tx_t niu_start_xmit(struct sk_buff *skb,
6616 struct net_device *dev)
a3138df9
DM		 6617{
6618 struct niu *np = netdev_priv(dev);
6619 unsigned long align, headroom;
b4c21639 6620 struct netdev_queue *txq;
a3138df9
DM		 6621 struct tx_ring_info *rp;
6622 struct tx_pkt_hdr *tp;
6623 unsigned int len, nfg;
6624 struct ethhdr *ehdr;
6625 int prod, i, tlen;
6626 u64 mapping, mrk;
6627
b4c21639
DM		 6628 i = skb_get_queue_mapping(skb);
6629 rp = &np->tx_rings[i];
6630 txq = netdev_get_tx_queue(dev, i);
a3138df9
DM		 6631
6632 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
b4c21639 6633 netif_tx_stop_queue(txq);
f10a1f2e 6634 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name);
a3138df9
DM		 6635 rp->tx_errors++;
6636 return NETDEV_TX_BUSY;
6637 }
6638
6639 if (skb->len < ETH_ZLEN) {
6640 unsigned int pad_bytes = ETH_ZLEN - skb->len;
6641
6642 if (skb_pad(skb, pad_bytes))
6643 goto out;
6644 skb_put(skb, pad_bytes);
6645 }
6646
6647 len = sizeof(struct tx_pkt_hdr) + 15;
6648 if (skb_headroom(skb) < len) {
6649 struct sk_buff *skb_new;
6650
6651 skb_new = skb_realloc_headroom(skb, len);
6652 if (!skb_new) {
6653 rp->tx_errors++;
6654 goto out_drop;
6655 }
6656 kfree_skb(skb);
6657 skb = skb_new;
3ebebccf
DM		 6658 } else
6659 skb_orphan(skb);
a3138df9
DM		 6660
6661 align = ((unsigned long) skb->data & (16 - 1));
6662 headroom = align + sizeof(struct tx_pkt_hdr);
6663
6664 ehdr = (struct ethhdr *) skb->data;
6665 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
6666
6667 len = skb->len - sizeof(struct tx_pkt_hdr);
6668 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
6669 tp->resv = 0;
6670
6671 len = skb_headlen(skb);
6672 mapping = np->ops->map_single(np->device, skb->data,
6673 len, DMA_TO_DEVICE);
6674
6675 prod = rp->prod;
6676
6677 rp->tx_buffs[prod].skb = skb;
6678 rp->tx_buffs[prod].mapping = mapping;
6679
6680 mrk = TX_DESC_SOP;
6681 if (++rp->mark_counter == rp->mark_freq) {
6682 rp->mark_counter = 0;
6683 mrk |= TX_DESC_MARK;
6684 rp->mark_pending++;
6685 }
6686
6687 tlen = len;
6688 nfg = skb_shinfo(skb)->nr_frags;
6689 while (tlen > 0) {
6690 tlen -= MAX_TX_DESC_LEN;
6691 nfg++;
6692 }
6693
6694 while (len > 0) {
6695 unsigned int this_len = len;
6696
6697 if (this_len > MAX_TX_DESC_LEN)
6698 this_len = MAX_TX_DESC_LEN;
6699
6700 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
6701 mrk = nfg = 0;
6702
6703 prod = NEXT_TX(rp, prod);
6704 mapping += this_len;
6705 len -= this_len;
6706 }
6707
6708 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6709 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6710
6711 len = frag->size;
6712 mapping = np->ops->map_page(np->device, frag->page,
6713 frag->page_offset, len,
6714 DMA_TO_DEVICE);
6715
6716 rp->tx_buffs[prod].skb = NULL;
6717 rp->tx_buffs[prod].mapping = mapping;
6718
6719 niu_set_txd(rp, prod, mapping, len, 0, 0);
6720
6721 prod = NEXT_TX(rp, prod);
6722 }
6723
6724 if (prod < rp->prod)
6725 rp->wrap_bit ^= TX_RING_KICK_WRAP;
6726 rp->prod = prod;
6727
6728 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
6729
6730 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
b4c21639 6731 netif_tx_stop_queue(txq);
a3138df9 6732 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
b4c21639 6733 netif_tx_wake_queue(txq);
a3138df9
DM		 6734 }
6735
a3138df9
DM		 6736out:
6737 return NETDEV_TX_OK;
6738
6739out_drop:
6740 rp->tx_errors++;
6741 kfree_skb(skb);
6742 goto out;
6743}
6744
6745static int niu_change_mtu(struct net_device *dev, int new_mtu)
6746{
6747 struct niu *np = netdev_priv(dev);
6748 int err, orig_jumbo, new_jumbo;
6749
6750 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
6751 return -EINVAL;
6752
6753 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
6754 new_jumbo = (new_mtu > ETH_DATA_LEN);
6755
6756 dev->mtu = new_mtu;
6757
6758 if (!netif_running(dev) ||
6759 (orig_jumbo == new_jumbo))
6760 return 0;
6761
6762 niu_full_shutdown(np, dev);
6763
6764 niu_free_channels(np);
6765
6766 niu_enable_napi(np);
6767
6768 err = niu_alloc_channels(np);
6769 if (err)
6770 return err;
6771
6772 spin_lock_irq(&np->lock);
6773
6774 err = niu_init_hw(np);
6775 if (!err) {
6776 init_timer(&np->timer);
6777 np->timer.expires = jiffies + HZ;
6778 np->timer.data = (unsigned long) np;
6779 np->timer.function = niu_timer;
6780
6781 err = niu_enable_interrupts(np, 1);
6782 if (err)
6783 niu_stop_hw(np);
6784 }
6785
6786 spin_unlock_irq(&np->lock);
6787
6788 if (!err) {
b4c21639 6789 netif_tx_start_all_queues(dev);
a3138df9
DM		 6790 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
6791 netif_carrier_on(dev);
6792
6793 add_timer(&np->timer);
6794 }
6795
6796 return err;
6797}
6798
6799static void niu_get_drvinfo(struct net_device *dev,
6800 struct ethtool_drvinfo *info)
6801{
6802 struct niu *np = netdev_priv(dev);
6803 struct niu_vpd *vpd = &np->vpd;
6804
6805 strcpy(info->driver, DRV_MODULE_NAME);
6806 strcpy(info->version, DRV_MODULE_VERSION);
6807 sprintf(info->fw_version, "%d.%d",
6808 vpd->fcode_major, vpd->fcode_minor);
6809 if (np->parent->plat_type != PLAT_TYPE_NIU)
6810 strcpy(info->bus_info, pci_name(np->pdev));
6811}
6812
6813static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6814{
6815 struct niu *np = netdev_priv(dev);
6816 struct niu_link_config *lp;
6817
6818 lp = &np->link_config;
6819
6820 memset(cmd, 0, sizeof(*cmd));
6821 cmd->phy_address = np->phy_addr;
6822 cmd->supported = lp->supported;
38bb045d
CB		 6823 cmd->advertising = lp->active_advertising;
6824 cmd->autoneg = lp->active_autoneg;
a3138df9
DM		 6825 cmd->speed = lp->active_speed;
6826 cmd->duplex = lp->active_duplex;
38bb045d
CB		 6827 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
6828 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ?
6829 XCVR_EXTERNAL : XCVR_INTERNAL;
a3138df9
DM		 6830
6831 return 0;
6832}
6833
6834static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6835{
38bb045d
CB		 6836 struct niu *np = netdev_priv(dev);
6837 struct niu_link_config *lp = &np->link_config;
6838
6839 lp->advertising = cmd->advertising;
6840 lp->speed = cmd->speed;
6841 lp->duplex = cmd->duplex;
6842 lp->autoneg = cmd->autoneg;
6843 return niu_init_link(np);
a3138df9
DM		 6844}
6845
6846static u32 niu_get_msglevel(struct net_device *dev)
6847{
6848 struct niu *np = netdev_priv(dev);
6849 return np->msg_enable;
6850}
6851
6852static void niu_set_msglevel(struct net_device *dev, u32 value)
6853{
6854 struct niu *np = netdev_priv(dev);
6855 np->msg_enable = value;
6856}
6857
38bb045d
CB		 6858static int niu_nway_reset(struct net_device *dev)
6859{
6860 struct niu *np = netdev_priv(dev);
6861
6862 if (np->link_config.autoneg)
6863 return niu_init_link(np);
6864
6865 return 0;
6866}
6867
a3138df9
DM		 6868static int niu_get_eeprom_len(struct net_device *dev)
6869{
6870 struct niu *np = netdev_priv(dev);
6871
6872 return np->eeprom_len;
6873}
6874
6875static int niu_get_eeprom(struct net_device *dev,
6876 struct ethtool_eeprom *eeprom, u8 *data)
6877{
6878 struct niu *np = netdev_priv(dev);
6879 u32 offset, len, val;
6880
6881 offset = eeprom->offset;
6882 len = eeprom->len;
6883
6884 if (offset + len < offset)
6885 return -EINVAL;
6886 if (offset >= np->eeprom_len)
6887 return -EINVAL;
6888 if (offset + len > np->eeprom_len)
6889 len = eeprom->len = np->eeprom_len - offset;
6890
6891 if (offset & 3) {
6892 u32 b_offset, b_count;
6893
6894 b_offset = offset & 3;
6895 b_count = 4 - b_offset;
6896 if (b_count > len)
6897 b_count = len;
6898
6899 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6900 memcpy(data, ((char *)&val) + b_offset, b_count);
6901 data += b_count;
6902 len -= b_count;
6903 offset += b_count;
6904 }
6905 while (len >= 4) {
6906 val = nr64(ESPC_NCR(offset / 4));
6907 memcpy(data, &val, 4);
6908 data += 4;
6909 len -= 4;
6910 offset += 4;
6911 }
6912 if (len) {
6913 val = nr64(ESPC_NCR(offset / 4));
6914 memcpy(data, &val, len);
6915 }
6916 return 0;
6917}
6918
2d96cf8c
SB		 6919static void niu_ethflow_to_l3proto(int flow_type, u8 *pid)
6920{
6921 switch (flow_type) {
6922 case TCP_V4_FLOW:
6923 case TCP_V6_FLOW:
6924 *pid = IPPROTO_TCP;
6925 break;
6926 case UDP_V4_FLOW:
6927 case UDP_V6_FLOW:
6928 *pid = IPPROTO_UDP;
6929 break;
6930 case SCTP_V4_FLOW:
6931 case SCTP_V6_FLOW:
6932 *pid = IPPROTO_SCTP;
6933 break;
6934 case AH_V4_FLOW:
6935 case AH_V6_FLOW:
6936 *pid = IPPROTO_AH;
6937 break;
6938 case ESP_V4_FLOW:
6939 case ESP_V6_FLOW:
6940 *pid = IPPROTO_ESP;
6941 break;
6942 default:
6943 *pid = 0;
6944 break;
6945 }
6946}
6947
6948static int niu_class_to_ethflow(u64 class, int *flow_type)
6949{
6950 switch (class) {
6951 case CLASS_CODE_TCP_IPV4:
6952 *flow_type = TCP_V4_FLOW;
6953 break;
6954 case CLASS_CODE_UDP_IPV4:
6955 *flow_type = UDP_V4_FLOW;
6956 break;
6957 case CLASS_CODE_AH_ESP_IPV4:
6958 *flow_type = AH_V4_FLOW;
6959 break;
6960 case CLASS_CODE_SCTP_IPV4:
6961 *flow_type = SCTP_V4_FLOW;
6962 break;
6963 case CLASS_CODE_TCP_IPV6:
6964 *flow_type = TCP_V6_FLOW;
6965 break;
6966 case CLASS_CODE_UDP_IPV6:
6967 *flow_type = UDP_V6_FLOW;
6968 break;
6969 case CLASS_CODE_AH_ESP_IPV6:
6970 *flow_type = AH_V6_FLOW;
6971 break;
6972 case CLASS_CODE_SCTP_IPV6:
6973 *flow_type = SCTP_V6_FLOW;
6974 break;
6975 case CLASS_CODE_USER_PROG1:
6976 case CLASS_CODE_USER_PROG2:
6977 case CLASS_CODE_USER_PROG3:
6978 case CLASS_CODE_USER_PROG4:
6979 *flow_type = IP_USER_FLOW;
6980 break;
6981 default:
6982 return 0;
6983 }
6984
6985 return 1;
6986}
6987
b4653e99
SB		 6988static int niu_ethflow_to_class(int flow_type, u64 *class)
6989{
6990 switch (flow_type) {
6991 case TCP_V4_FLOW:
6992 *class = CLASS_CODE_TCP_IPV4;
6993 break;
6994 case UDP_V4_FLOW:
6995 *class = CLASS_CODE_UDP_IPV4;
6996 break;
2d96cf8c
SB		 6997 case AH_V4_FLOW:
6998 case ESP_V4_FLOW:
b4653e99
SB		 6999 *class = CLASS_CODE_AH_ESP_IPV4;
7000 break;
7001 case SCTP_V4_FLOW:
7002 *class = CLASS_CODE_SCTP_IPV4;
7003 break;
7004 case TCP_V6_FLOW:
7005 *class = CLASS_CODE_TCP_IPV6;
7006 break;
7007 case UDP_V6_FLOW:
7008 *class = CLASS_CODE_UDP_IPV6;
7009 break;
2d96cf8c
SB		 7010 case AH_V6_FLOW:
7011 case ESP_V6_FLOW:
b4653e99
SB		 7012 *class = CLASS_CODE_AH_ESP_IPV6;
7013 break;
7014 case SCTP_V6_FLOW:
7015 *class = CLASS_CODE_SCTP_IPV6;
7016 break;
7017 default:
38c080ff 7018 return 0;
b4653e99
SB		 7019 }
7020
7021 return 1;
7022}
7023
7024static u64 niu_flowkey_to_ethflow(u64 flow_key)
7025{
7026 u64 ethflow = 0;
7027
b4653e99
SB		 7028 if (flow_key & FLOW_KEY_L2DA)
7029 ethflow |= RXH_L2DA;
7030 if (flow_key & FLOW_KEY_VLAN)
7031 ethflow |= RXH_VLAN;
7032 if (flow_key & FLOW_KEY_IPSA)
7033 ethflow |= RXH_IP_SRC;
7034 if (flow_key & FLOW_KEY_IPDA)
7035 ethflow |= RXH_IP_DST;
7036 if (flow_key & FLOW_KEY_PROTO)
7037 ethflow |= RXH_L3_PROTO;
7038 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT))
7039 ethflow |= RXH_L4_B_0_1;
7040 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT))
7041 ethflow |= RXH_L4_B_2_3;
7042
7043 return ethflow;
7044
7045}
7046
7047static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key)
7048{
7049 u64 key = 0;
7050
b4653e99
SB		 7051 if (ethflow & RXH_L2DA)
7052 key |= FLOW_KEY_L2DA;
7053 if (ethflow & RXH_VLAN)
7054 key |= FLOW_KEY_VLAN;
7055 if (ethflow & RXH_IP_SRC)
7056 key |= FLOW_KEY_IPSA;
7057 if (ethflow & RXH_IP_DST)
7058 key |= FLOW_KEY_IPDA;
7059 if (ethflow & RXH_L3_PROTO)
7060 key |= FLOW_KEY_PROTO;
7061 if (ethflow & RXH_L4_B_0_1)
7062 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT);
7063 if (ethflow & RXH_L4_B_2_3)
7064 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT);
7065
7066 *flow_key = key;
7067
7068 return 1;
7069
7070}
7071
2d96cf8c 7072static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
b4653e99 7073{
b4653e99
SB		 7074 u64 class;
7075
2d96cf8c 7076 nfc->data = 0;
b4653e99 7077
2d96cf8c 7078 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7079 return -EINVAL;
7080
7081 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7082 TCAM_KEY_DISC)
2d96cf8c 7083 nfc->data = RXH_DISCARD;
b4653e99 7084 else
2d96cf8c 7085 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class -
b4653e99
SB		 7086 CLASS_CODE_USER_PROG1]);
7087 return 0;
7088}
7089
2d96cf8c
SB		 7090static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp,
7091 struct ethtool_rx_flow_spec *fsp)
7092{
ed440e82
HH		 7093 u32 tmp;
7094 u16 prt;
2d96cf8c 7095
ed440e82
HH		 7096 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7097 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7098
7099 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7100 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
7101
7102 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT;
7103 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp);
7104
7105 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT;
7106 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp);
2d96cf8c
SB		 7107
7108 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >>
7109 TCAM_V4KEY2_TOS_SHIFT;
7110 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >>
7111 TCAM_V4KEY2_TOS_SHIFT;
7112
7113 switch (fsp->flow_type) {
7114 case TCP_V4_FLOW:
7115 case UDP_V4_FLOW:
7116 case SCTP_V4_FLOW:
ed440e82
HH		 7117 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7118 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7119 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7120
7121 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
7122 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7123 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c 7124
ed440e82
HH		 7125 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7126 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16;
7127 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt);
7128
7129 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7130 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff;
7131 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt);
2d96cf8c
SB		 7132 break;
7133 case AH_V4_FLOW:
7134 case ESP_V4_FLOW:
ed440e82 7135 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7136 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7137 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c 7138
ed440e82
HH		 7139 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7140 TCAM_V4KEY2_PORT_SPI_SHIFT;
7141 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp);
2d96cf8c
SB		 7142 break;
7143 case IP_USER_FLOW:
ed440e82 7144 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >>
2d96cf8c 7145 TCAM_V4KEY2_PORT_SPI_SHIFT;
ed440e82 7146 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c 7147
ed440e82
HH		 7148 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT;
7150 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp);
2d96cf8c
SB		 7151
7152 fsp->h_u.usr_ip4_spec.proto =
7153 (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7154 TCAM_V4KEY2_PROTO_SHIFT;
7155 fsp->m_u.usr_ip4_spec.proto =
7156 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >>
7157 TCAM_V4KEY2_PROTO_SHIFT;
7158
7159 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
7160 break;
7161 default:
7162 break;
7163 }
7164}
7165
7166static int niu_get_ethtool_tcam_entry(struct niu *np,
7167 struct ethtool_rxnfc *nfc)
7168{
7169 struct niu_parent *parent = np->parent;
7170 struct niu_tcam_entry *tp;
7171 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7172 u16 idx;
7173 u64 class;
7174 int ret = 0;
7175
7176 idx = tcam_get_index(np, (u16)nfc->fs.location);
7177
7178 tp = &parent->tcam[idx];
7179 if (!tp->valid) {
f10a1f2e
JP		 7180 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n",
7181 parent->index, (u16)nfc->fs.location, idx);
2d96cf8c
SB		 7182 return -EINVAL;
7183 }
7184
7185 /* fill the flow spec entry */
7186 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7187 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7188 ret = niu_class_to_ethflow(class, &fsp->flow_type);
7189
7190 if (ret < 0) {
f10a1f2e
JP		 7191 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n",
7192 parent->index);
2d96cf8c
SB		 7193 ret = -EINVAL;
7194 goto out;
7195 }
7196
7197 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) {
7198 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >>
7199 TCAM_V4KEY2_PROTO_SHIFT;
7200 if (proto == IPPROTO_ESP) {
7201 if (fsp->flow_type == AH_V4_FLOW)
7202 fsp->flow_type = ESP_V4_FLOW;
7203 else
7204 fsp->flow_type = ESP_V6_FLOW;
7205 }
7206 }
7207
7208 switch (fsp->flow_type) {
7209 case TCP_V4_FLOW:
7210 case UDP_V4_FLOW:
7211 case SCTP_V4_FLOW:
7212 case AH_V4_FLOW:
7213 case ESP_V4_FLOW:
7214 niu_get_ip4fs_from_tcam_key(tp, fsp);
7215 break;
7216 case TCP_V6_FLOW:
7217 case UDP_V6_FLOW:
7218 case SCTP_V6_FLOW:
7219 case AH_V6_FLOW:
7220 case ESP_V6_FLOW:
7221 /* Not yet implemented */
7222 ret = -EINVAL;
7223 break;
7224 case IP_USER_FLOW:
7225 niu_get_ip4fs_from_tcam_key(tp, fsp);
7226 break;
7227 default:
7228 ret = -EINVAL;
7229 break;
7230 }
7231
7232 if (ret < 0)
7233 goto out;
7234
7235 if (tp->assoc_data & TCAM_ASSOCDATA_DISC)
7236 fsp->ring_cookie = RX_CLS_FLOW_DISC;
7237 else
7238 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >>
7239 TCAM_ASSOCDATA_OFFSET_SHIFT;
7240
7241 /* put the tcam size here */
7242 nfc->data = tcam_get_size(np);
7243out:
7244 return ret;
7245}
7246
7247static int niu_get_ethtool_tcam_all(struct niu *np,
7248 struct ethtool_rxnfc *nfc,
7249 u32 *rule_locs)
7250{
7251 struct niu_parent *parent = np->parent;
7252 struct niu_tcam_entry *tp;
7253 int i, idx, cnt;
2d96cf8c 7254 unsigned long flags;
ee9c5cfa 7255 int ret = 0;
2d96cf8c
SB		 7256
7257 /* put the tcam size here */
7258 nfc->data = tcam_get_size(np);
7259
7260 niu_lock_parent(np, flags);
2d96cf8c
SB		 7261 for (cnt = 0, i = 0; i < nfc->data; i++) {
7262 idx = tcam_get_index(np, i);
7263 tp = &parent->tcam[idx];
7264 if (!tp->valid)
7265 continue;
ee9c5cfa
BH		 7266 if (cnt == nfc->rule_cnt) {
7267 ret = -EMSGSIZE;
7268 break;
7269 }
2d96cf8c
SB		 7270 rule_locs[cnt] = i;
7271 cnt++;
7272 }
7273 niu_unlock_parent(np, flags);
7274
ee9c5cfa 7275 return ret;
2d96cf8c
SB		 7276}
7277
7278static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
7279 void *rule_locs)
b4653e99
SB		 7280{
7281 struct niu *np = netdev_priv(dev);
2d96cf8c
SB		 7282 int ret = 0;
7283
7284 switch (cmd->cmd) {
7285 case ETHTOOL_GRXFH:
7286 ret = niu_get_hash_opts(np, cmd);
7287 break;
7288 case ETHTOOL_GRXRINGS:
7289 cmd->data = np->num_rx_rings;
7290 break;
7291 case ETHTOOL_GRXCLSRLCNT:
7292 cmd->rule_cnt = tcam_get_valid_entry_cnt(np);
7293 break;
7294 case ETHTOOL_GRXCLSRULE:
7295 ret = niu_get_ethtool_tcam_entry(np, cmd);
7296 break;
7297 case ETHTOOL_GRXCLSRLALL:
7298 ret = niu_get_ethtool_tcam_all(np, cmd, (u32 *)rule_locs);
7299 break;
7300 default:
7301 ret = -EINVAL;
7302 break;
7303 }
7304
7305 return ret;
7306}
7307
7308static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc)
7309{
b4653e99
SB		 7310 u64 class;
7311 u64 flow_key = 0;
7312 unsigned long flags;
7313
2d96cf8c 7314 if (!niu_ethflow_to_class(nfc->flow_type, &class))
b4653e99
SB		 7315 return -EINVAL;
7316
7317 if (class < CLASS_CODE_USER_PROG1 ||
7318 class > CLASS_CODE_SCTP_IPV6)
7319 return -EINVAL;
7320
2d96cf8c 7321 if (nfc->data & RXH_DISCARD) {
b4653e99
SB		 7322 niu_lock_parent(np, flags);
7323 flow_key = np->parent->tcam_key[class -
7324 CLASS_CODE_USER_PROG1];
7325 flow_key |= TCAM_KEY_DISC;
7326 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7327 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7328 niu_unlock_parent(np, flags);
7329 return 0;
7330 } else {
7331 /* Discard was set before, but is not set now */
7332 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] &
7333 TCAM_KEY_DISC) {
7334 niu_lock_parent(np, flags);
7335 flow_key = np->parent->tcam_key[class -
7336 CLASS_CODE_USER_PROG1];
7337 flow_key &= ~TCAM_KEY_DISC;
7338 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7339 flow_key);
7340 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] =
7341 flow_key;
7342 niu_unlock_parent(np, flags);
7343 }
7344 }
7345
2d96cf8c 7346 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key))
b4653e99
SB		 7347 return -EINVAL;
7348
7349 niu_lock_parent(np, flags);
7350 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7351 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key;
7352 niu_unlock_parent(np, flags);
7353
7354 return 0;
7355}
7356
2d96cf8c
SB		 7357static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp,
7358 struct niu_tcam_entry *tp,
7359 int l2_rdc_tab, u64 class)
7360{
7361 u8 pid = 0;
7362 u32 sip, dip, sipm, dipm, spi, spim;
7363 u16 sport, dport, spm, dpm;
7364
7365 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src);
7366 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src);
7367 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst);
7368 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst);
7369
7370 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT;
7371 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE;
7372 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT;
7373 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM;
7374
7375 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT;
7376 tp->key[3] |= dip;
7377
7378 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT;
7379 tp->key_mask[3] |= dipm;
7380
7381 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos <<
7382 TCAM_V4KEY2_TOS_SHIFT);
7383 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos <<
7384 TCAM_V4KEY2_TOS_SHIFT);
7385 switch (fsp->flow_type) {
7386 case TCP_V4_FLOW:
7387 case UDP_V4_FLOW:
7388 case SCTP_V4_FLOW:
7389 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc);
7390 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc);
7391 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst);
7392 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst);
7393
7394 tp->key[2] |= (((u64)sport << 16) | dport);
7395 tp->key_mask[2] |= (((u64)spm << 16) | dpm);
7396 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7397 break;
7398 case AH_V4_FLOW:
7399 case ESP_V4_FLOW:
7400 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi);
7401 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi);
7402
7403 tp->key[2] |= spi;
7404 tp->key_mask[2] |= spim;
7405 niu_ethflow_to_l3proto(fsp->flow_type, &pid);
7406 break;
7407 case IP_USER_FLOW:
7408 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes);
7409 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes);
7410
7411 tp->key[2] |= spi;
7412 tp->key_mask[2] |= spim;
7413 pid = fsp->h_u.usr_ip4_spec.proto;
7414 break;
7415 default:
7416 break;
7417 }
7418
7419 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT);
7420 if (pid) {
7421 tp->key_mask[2] |= TCAM_V4KEY2_PROTO;
7422 }
7423}
7424
7425static int niu_add_ethtool_tcam_entry(struct niu *np,
7426 struct ethtool_rxnfc *nfc)
7427{
7428 struct niu_parent *parent = np->parent;
7429 struct niu_tcam_entry *tp;
7430 struct ethtool_rx_flow_spec *fsp = &nfc->fs;
7431 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7432 int l2_rdc_table = rdc_table->first_table_num;
7433 u16 idx;
7434 u64 class;
7435 unsigned long flags;
7436 int err, ret;
7437
7438 ret = 0;
7439
7440 idx = nfc->fs.location;
7441 if (idx >= tcam_get_size(np))
7442 return -EINVAL;
7443
7444 if (fsp->flow_type == IP_USER_FLOW) {
7445 int i;
7446 int add_usr_cls = 0;
2d96cf8c
SB		 7447 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec;
7448 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec;
7449
e0de7c93
BH		 7450 if (uspec->ip_ver != ETH_RX_NFC_IP4)
7451 return -EINVAL;
7452
2d96cf8c
SB		 7453 niu_lock_parent(np, flags);
7454
7455 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7456 if (parent->l3_cls[i]) {
7457 if (uspec->proto == parent->l3_cls_pid[i]) {
7458 class = parent->l3_cls[i];
7459 parent->l3_cls_refcnt[i]++;
7460 add_usr_cls = 1;
7461 break;
7462 }
7463 } else {
7464 /* Program new user IP class */
7465 switch (i) {
7466 case 0:
7467 class = CLASS_CODE_USER_PROG1;
7468 break;
7469 case 1:
7470 class = CLASS_CODE_USER_PROG2;
7471 break;
7472 case 2:
7473 class = CLASS_CODE_USER_PROG3;
7474 break;
7475 case 3:
7476 class = CLASS_CODE_USER_PROG4;
7477 break;
7478 default:
7479 break;
7480 }
e0de7c93 7481 ret = tcam_user_ip_class_set(np, class, 0,
2d96cf8c
SB		 7482 uspec->proto,
7483 uspec->tos,
7484 umask->tos);
7485 if (ret)
7486 goto out;
7487
7488 ret = tcam_user_ip_class_enable(np, class, 1);
7489 if (ret)
7490 goto out;
7491 parent->l3_cls[i] = class;
7492 parent->l3_cls_pid[i] = uspec->proto;
7493 parent->l3_cls_refcnt[i]++;
7494 add_usr_cls = 1;
7495 break;
7496 }
7497 }
7498 if (!add_usr_cls) {
f10a1f2e
JP		 7499 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n",
7500 parent->index, __func__, uspec->proto);
2d96cf8c
SB		 7501 ret = -EINVAL;
7502 goto out;
7503 }
7504 niu_unlock_parent(np, flags);
7505 } else {
7506 if (!niu_ethflow_to_class(fsp->flow_type, &class)) {
7507 return -EINVAL;
7508 }
7509 }
7510
7511 niu_lock_parent(np, flags);
7512
7513 idx = tcam_get_index(np, idx);
7514 tp = &parent->tcam[idx];
7515
7516 memset(tp, 0, sizeof(*tp));
7517
7518 /* fill in the tcam key and mask */
7519 switch (fsp->flow_type) {
7520 case TCP_V4_FLOW:
7521 case UDP_V4_FLOW:
7522 case SCTP_V4_FLOW:
7523 case AH_V4_FLOW:
7524 case ESP_V4_FLOW:
7525 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
7526 break;
7527 case TCP_V6_FLOW:
7528 case UDP_V6_FLOW:
7529 case SCTP_V6_FLOW:
7530 case AH_V6_FLOW:
7531 case ESP_V6_FLOW:
7532 /* Not yet implemented */
f10a1f2e
JP		 7533 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7534 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7535 ret = -EINVAL;
7536 goto out;
7537 case IP_USER_FLOW:
e0de7c93 7538 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class);
2d96cf8c
SB		 7539 break;
7540 default:
f10a1f2e
JP		 7541 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n",
7542 parent->index, __func__, fsp->flow_type);
2d96cf8c
SB		 7543 ret = -EINVAL;
7544 goto out;
7545 }
7546
7547 /* fill in the assoc data */
7548 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) {
7549 tp->assoc_data = TCAM_ASSOCDATA_DISC;
7550 } else {
7551 if (fsp->ring_cookie >= np->num_rx_rings) {
f10a1f2e
JP		 7552 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n",
7553 parent->index, __func__,
7554 (long long)fsp->ring_cookie);
2d96cf8c
SB		 7555 ret = -EINVAL;
7556 goto out;
7557 }
7558 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
7559 (fsp->ring_cookie <<
7560 TCAM_ASSOCDATA_OFFSET_SHIFT));
7561 }
7562
7563 err = tcam_write(np, idx, tp->key, tp->key_mask);
7564 if (err) {
7565 ret = -EINVAL;
7566 goto out;
7567 }
7568 err = tcam_assoc_write(np, idx, tp->assoc_data);
7569 if (err) {
7570 ret = -EINVAL;
7571 goto out;
7572 }
7573
7574 /* validate the entry */
7575 tp->valid = 1;
7576 np->clas.tcam_valid_entries++;
7577out:
7578 niu_unlock_parent(np, flags);
7579
7580 return ret;
7581}
7582
7583static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc)
7584{
7585 struct niu_parent *parent = np->parent;
7586 struct niu_tcam_entry *tp;
7587 u16 idx;
7588 unsigned long flags;
7589 u64 class;
7590 int ret = 0;
7591
7592 if (loc >= tcam_get_size(np))
7593 return -EINVAL;
7594
7595 niu_lock_parent(np, flags);
7596
7597 idx = tcam_get_index(np, loc);
7598 tp = &parent->tcam[idx];
7599
7600 /* if the entry is of a user defined class, then update*/
7601 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >>
7602 TCAM_V4KEY0_CLASS_CODE_SHIFT;
7603
7604 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) {
7605 int i;
7606 for (i = 0; i < NIU_L3_PROG_CLS; i++) {
7607 if (parent->l3_cls[i] == class) {
7608 parent->l3_cls_refcnt[i]--;
7609 if (!parent->l3_cls_refcnt[i]) {
7610 /* disable class */
7611 ret = tcam_user_ip_class_enable(np,
7612 class,
7613 0);
7614 if (ret)
7615 goto out;
7616 parent->l3_cls[i] = 0;
7617 parent->l3_cls_pid[i] = 0;
7618 }
7619 break;
7620 }
7621 }
7622 if (i == NIU_L3_PROG_CLS) {
f10a1f2e
JP		 7623 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n",
7624 parent->index, __func__,
7625 (unsigned long long)class);
2d96cf8c
SB		 7626 ret = -EINVAL;
7627 goto out;
7628 }
7629 }
7630
7631 ret = tcam_flush(np, idx);
7632 if (ret)
7633 goto out;
7634
7635 /* invalidate the entry */
7636 tp->valid = 0;
7637 np->clas.tcam_valid_entries--;
7638out:
7639 niu_unlock_parent(np, flags);
7640
7641 return ret;
7642}
7643
7644static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
7645{
7646 struct niu *np = netdev_priv(dev);
7647 int ret = 0;
7648
7649 switch (cmd->cmd) {
7650 case ETHTOOL_SRXFH:
7651 ret = niu_set_hash_opts(np, cmd);
7652 break;
7653 case ETHTOOL_SRXCLSRLINS:
7654 ret = niu_add_ethtool_tcam_entry(np, cmd);
7655 break;
7656 case ETHTOOL_SRXCLSRLDEL:
7657 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location);
7658 break;
7659 default:
7660 ret = -EINVAL;
7661 break;
7662 }
7663
7664 return ret;
7665}
7666
a3138df9
DM		 7667static const struct {
7668 const char string[ETH_GSTRING_LEN];
7669} niu_xmac_stat_keys[] = {
7670 { "tx_frames" },
7671 { "tx_bytes" },
7672 { "tx_fifo_errors" },
7673 { "tx_overflow_errors" },
7674 { "tx_max_pkt_size_errors" },
7675 { "tx_underflow_errors" },
7676 { "rx_local_faults" },
7677 { "rx_remote_faults" },
7678 { "rx_link_faults" },
7679 { "rx_align_errors" },
7680 { "rx_frags" },
7681 { "rx_mcasts" },
7682 { "rx_bcasts" },
7683 { "rx_hist_cnt1" },
7684 { "rx_hist_cnt2" },
7685 { "rx_hist_cnt3" },
7686 { "rx_hist_cnt4" },
7687 { "rx_hist_cnt5" },
7688 { "rx_hist_cnt6" },
7689 { "rx_hist_cnt7" },
7690 { "rx_octets" },
7691 { "rx_code_violations" },
7692 { "rx_len_errors" },
7693 { "rx_crc_errors" },
7694 { "rx_underflows" },
7695 { "rx_overflows" },
7696 { "pause_off_state" },
7697 { "pause_on_state" },
7698 { "pause_received" },
7699};
7700
7701#define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7702
7703static const struct {
7704 const char string[ETH_GSTRING_LEN];
7705} niu_bmac_stat_keys[] = {
7706 { "tx_underflow_errors" },
7707 { "tx_max_pkt_size_errors" },
7708 { "tx_bytes" },
7709 { "tx_frames" },
7710 { "rx_overflows" },
7711 { "rx_frames" },
7712 { "rx_align_errors" },
7713 { "rx_crc_errors" },
7714 { "rx_len_errors" },
7715 { "pause_off_state" },
7716 { "pause_on_state" },
7717 { "pause_received" },
7718};
7719
7720#define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7721
7722static const struct {
7723 const char string[ETH_GSTRING_LEN];
7724} niu_rxchan_stat_keys[] = {
7725 { "rx_channel" },
7726 { "rx_packets" },
7727 { "rx_bytes" },
7728 { "rx_dropped" },
7729 { "rx_errors" },
7730};
7731
7732#define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7733
7734static const struct {
7735 const char string[ETH_GSTRING_LEN];
7736} niu_txchan_stat_keys[] = {
7737 { "tx_channel" },
7738 { "tx_packets" },
7739 { "tx_bytes" },
7740 { "tx_errors" },
7741};
7742
7743#define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7744
7745static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
7746{
7747 struct niu *np = netdev_priv(dev);
7748 int i;
7749
7750 if (stringset != ETH_SS_STATS)
7751 return;
7752
7753 if (np->flags & NIU_FLAGS_XMAC) {
7754 memcpy(data, niu_xmac_stat_keys,
7755 sizeof(niu_xmac_stat_keys));
7756 data += sizeof(niu_xmac_stat_keys);
7757 } else {
7758 memcpy(data, niu_bmac_stat_keys,
7759 sizeof(niu_bmac_stat_keys));
7760 data += sizeof(niu_bmac_stat_keys);
7761 }
7762 for (i = 0; i < np->num_rx_rings; i++) {
7763 memcpy(data, niu_rxchan_stat_keys,
7764 sizeof(niu_rxchan_stat_keys));
7765 data += sizeof(niu_rxchan_stat_keys);
7766 }
7767 for (i = 0; i < np->num_tx_rings; i++) {
7768 memcpy(data, niu_txchan_stat_keys,
7769 sizeof(niu_txchan_stat_keys));
7770 data += sizeof(niu_txchan_stat_keys);
7771 }
7772}
7773
15f0a394 7774static int niu_get_sset_count(struct net_device *dev, int stringset)
a3138df9
DM		 7775{
7776 struct niu *np = netdev_priv(dev);
7777
15f0a394
BH		 7778 if (stringset != ETH_SS_STATS)
7779 return -EINVAL;
7780
807540ba 7781 return (np->flags & NIU_FLAGS_XMAC ?
a3138df9
DM		 7782 NUM_XMAC_STAT_KEYS :
7783 NUM_BMAC_STAT_KEYS) +
7784 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
807540ba 7785 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS);
a3138df9
DM		 7786}
7787
7788static void niu_get_ethtool_stats(struct net_device *dev,
7789 struct ethtool_stats *stats, u64 *data)
7790{
7791 struct niu *np = netdev_priv(dev);
7792 int i;
7793
7794 niu_sync_mac_stats(np);
7795 if (np->flags & NIU_FLAGS_XMAC) {
7796 memcpy(data, &np->mac_stats.xmac,
7797 sizeof(struct niu_xmac_stats));
7798 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
7799 } else {
7800 memcpy(data, &np->mac_stats.bmac,
7801 sizeof(struct niu_bmac_stats));
7802 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
7803 }
7804 for (i = 0; i < np->num_rx_rings; i++) {
7805 struct rx_ring_info *rp = &np->rx_rings[i];
7806
b8a606b8
JDB		 7807 niu_sync_rx_discard_stats(np, rp, 0);
7808
a3138df9
DM		 7809 data[0] = rp->rx_channel;
7810 data[1] = rp->rx_packets;
7811 data[2] = rp->rx_bytes;
7812 data[3] = rp->rx_dropped;
7813 data[4] = rp->rx_errors;
7814 data += 5;
7815 }
7816 for (i = 0; i < np->num_tx_rings; i++) {
7817 struct tx_ring_info *rp = &np->tx_rings[i];
7818
7819 data[0] = rp->tx_channel;
7820 data[1] = rp->tx_packets;
7821 data[2] = rp->tx_bytes;
7822 data[3] = rp->tx_errors;
7823 data += 4;
7824 }
7825}
7826
7827static u64 niu_led_state_save(struct niu *np)
7828{
7829 if (np->flags & NIU_FLAGS_XMAC)
7830 return nr64_mac(XMAC_CONFIG);
7831 else
7832 return nr64_mac(BMAC_XIF_CONFIG);
7833}
7834
7835static void niu_led_state_restore(struct niu *np, u64 val)
7836{
7837 if (np->flags & NIU_FLAGS_XMAC)
7838 nw64_mac(XMAC_CONFIG, val);
7839 else
7840 nw64_mac(BMAC_XIF_CONFIG, val);
7841}
7842
7843static void niu_force_led(struct niu *np, int on)
7844{
7845 u64 val, reg, bit;
7846
7847 if (np->flags & NIU_FLAGS_XMAC) {
7848 reg = XMAC_CONFIG;
7849 bit = XMAC_CONFIG_FORCE_LED_ON;
7850 } else {
7851 reg = BMAC_XIF_CONFIG;
7852 bit = BMAC_XIF_CONFIG_LINK_LED;
7853 }
7854
7855 val = nr64_mac(reg);
7856 if (on)
7857 val |= bit;
7858 else
7859 val &= ~bit;
7860 nw64_mac(reg, val);
7861}
7862
7863static int niu_phys_id(struct net_device *dev, u32 data)
7864{
7865 struct niu *np = netdev_priv(dev);
7866 u64 orig_led_state;
7867 int i;
7868
7869 if (!netif_running(dev))
7870 return -EAGAIN;
7871
7872 if (data == 0)
7873 data = 2;
7874
7875 orig_led_state = niu_led_state_save(np);
7876 for (i = 0; i < (data * 2); i++) {
7877 int on = ((i % 2) == 0);
7878
7879 niu_force_led(np, on);
7880
7881 if (msleep_interruptible(500))
7882 break;
7883 }
7884 niu_led_state_restore(np, orig_led_state);
7885
7886 return 0;
7887}
7888
3cfa856d
DM		 7889static int niu_set_flags(struct net_device *dev, u32 data)
7890{
1437ce39 7891 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
3cfa856d
DM		 7892}
7893
a3138df9
DM		 7894static const struct ethtool_ops niu_ethtool_ops = {
7895 .get_drvinfo = niu_get_drvinfo,
7896 .get_link = ethtool_op_get_link,
7897 .get_msglevel = niu_get_msglevel,
7898 .set_msglevel = niu_set_msglevel,
38bb045d 7899 .nway_reset = niu_nway_reset,
a3138df9
DM		 7900 .get_eeprom_len = niu_get_eeprom_len,
7901 .get_eeprom = niu_get_eeprom,
7902 .get_settings = niu_get_settings,
7903 .set_settings = niu_set_settings,
7904 .get_strings = niu_get_strings,
15f0a394 7905 .get_sset_count = niu_get_sset_count,
a3138df9
DM		 7906 .get_ethtool_stats = niu_get_ethtool_stats,
7907 .phys_id = niu_phys_id,
2d96cf8c
SB		 7908 .get_rxnfc = niu_get_nfc,
7909 .set_rxnfc = niu_set_nfc,
3cfa856d
DM		 7910 .set_flags = niu_set_flags,
7911 .get_flags = ethtool_op_get_flags,
a3138df9
DM		 7912};
7913
7914static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
7915 int ldg, int ldn)
7916{
7917 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
7918 return -EINVAL;
7919 if (ldn < 0 || ldn > LDN_MAX)
7920 return -EINVAL;
7921
7922 parent->ldg_map[ldn] = ldg;
7923
7924 if (np->parent->plat_type == PLAT_TYPE_NIU) {
7925 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7926 * the firmware, and we're not supposed to change them.
7927 * Validate the mapping, because if it's wrong we probably
7928 * won't get any interrupts and that's painful to debug.
7929 */
7930 if (nr64(LDG_NUM(ldn)) != ldg) {
f10a1f2e 7931 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
a3138df9
DM		 7932 np->port, ldn, ldg,
7933 (unsigned long long) nr64(LDG_NUM(ldn)));
7934 return -EINVAL;
7935 }
7936 } else
7937 nw64(LDG_NUM(ldn), ldg);
7938
7939 return 0;
7940}
7941
7942static int niu_set_ldg_timer_res(struct niu *np, int res)
7943{
7944 if (res < 0 || res > LDG_TIMER_RES_VAL)
7945 return -EINVAL;
7946
7947
7948 nw64(LDG_TIMER_RES, res);
7949
7950 return 0;
7951}
7952
7953static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
7954{
7955 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
7956 (func < 0 || func > 3) ||
7957 (vector < 0 || vector > 0x1f))
7958 return -EINVAL;
7959
7960 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7961
7962 return 0;
7963}
7964
7965static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
7966{
7967 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
7968 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
7969 int limit;
7970
7971 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
7972 return -EINVAL;
7973
7974 frame = frame_base;
7975 nw64(ESPC_PIO_STAT, frame);
7976 limit = 64;
7977 do {
7978 udelay(5);
7979 frame = nr64(ESPC_PIO_STAT);
7980 if (frame & ESPC_PIO_STAT_READ_END)
7981 break;
7982 } while (limit--);
7983 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 7984 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 7985 (unsigned long long) frame);
7986 return -ENODEV;
7987 }
7988
7989 frame = frame_base;
7990 nw64(ESPC_PIO_STAT, frame);
7991 limit = 64;
7992 do {
7993 udelay(5);
7994 frame = nr64(ESPC_PIO_STAT);
7995 if (frame & ESPC_PIO_STAT_READ_END)
7996 break;
7997 } while (limit--);
7998 if (!(frame & ESPC_PIO_STAT_READ_END)) {
f10a1f2e 7999 dev_err(np->device, "EEPROM read timeout frame[%llx]\n",
a3138df9
DM		 8000 (unsigned long long) frame);
8001 return -ENODEV;
8002 }
8003
8004 frame = nr64(ESPC_PIO_STAT);
8005 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
8006}
8007
8008static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
8009{
8010 int err = niu_pci_eeprom_read(np, off);
8011 u16 val;
8012
8013 if (err < 0)
8014 return err;
8015 val = (err << 8);
8016 err = niu_pci_eeprom_read(np, off + 1);
8017 if (err < 0)
8018 return err;
8019 val |= (err & 0xff);
8020
8021 return val;
8022}
8023
8024static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
8025{
8026 int err = niu_pci_eeprom_read(np, off);
8027 u16 val;
8028
8029 if (err < 0)
8030 return err;
8031
8032 val = (err & 0xff);
8033 err = niu_pci_eeprom_read(np, off + 1);
8034 if (err < 0)
8035 return err;
8036
8037 val |= (err & 0xff) << 8;
8038
8039 return val;
8040}
8041
8042static int __devinit niu_pci_vpd_get_propname(struct niu *np,
8043 u32 off,
8044 char *namebuf,
8045 int namebuf_len)
8046{
8047 int i;
8048
8049 for (i = 0; i < namebuf_len; i++) {
8050 int err = niu_pci_eeprom_read(np, off + i);
8051 if (err < 0)
8052 return err;
8053 *namebuf++ = err;
8054 if (!err)
8055 break;
8056 }
8057 if (i >= namebuf_len)
8058 return -EINVAL;
8059
8060 return i + 1;
8061}
8062
8063static void __devinit niu_vpd_parse_version(struct niu *np)
8064{
8065 struct niu_vpd *vpd = &np->vpd;
8066 int len = strlen(vpd->version) + 1;
8067 const char *s = vpd->version;
8068 int i;
8069
8070 for (i = 0; i < len - 5; i++) {
9ea2bdab 8071 if (!strncmp(s + i, "FCode ", 6))
a3138df9
DM		 8072 break;
8073 }
8074 if (i >= len - 5)
8075 return;
8076
8077 s += i + 5;
8078 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
8079
f10a1f2e
JP		 8080 netif_printk(np, probe, KERN_DEBUG, np->dev,
8081 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8082 vpd->fcode_major, vpd->fcode_minor);
a3138df9
DM		 8083 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
8084 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
8085 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
8086 np->flags |= NIU_FLAGS_VPD_VALID;
8087}
8088
8089/* ESPC_PIO_EN_ENABLE must be set */
8090static int __devinit niu_pci_vpd_scan_props(struct niu *np,
8091 u32 start, u32 end)
8092{
8093 unsigned int found_mask = 0;
8094#define FOUND_MASK_MODEL 0x00000001
8095#define FOUND_MASK_BMODEL 0x00000002
8096#define FOUND_MASK_VERS 0x00000004
8097#define FOUND_MASK_MAC 0x00000008
8098#define FOUND_MASK_NMAC 0x00000010
8099#define FOUND_MASK_PHY 0x00000020
8100#define FOUND_MASK_ALL 0x0000003f
8101
f10a1f2e
JP		 8102 netif_printk(np, probe, KERN_DEBUG, np->dev,
8103 "VPD_SCAN: start[%x] end[%x]\n", start, end);
a3138df9
DM		 8104 while (start < end) {
8105 int len, err, instance, type, prop_len;
8106 char namebuf[64];
8107 u8 *prop_buf;
8108 int max_len;
8109
8110 if (found_mask == FOUND_MASK_ALL) {
8111 niu_vpd_parse_version(np);
8112 return 1;
8113 }
8114
8115 err = niu_pci_eeprom_read(np, start + 2);
8116 if (err < 0)
8117 return err;
8118 len = err;
8119 start += 3;
8120
8121 instance = niu_pci_eeprom_read(np, start);
8122 type = niu_pci_eeprom_read(np, start + 3);
8123 prop_len = niu_pci_eeprom_read(np, start + 4);
8124 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8125 if (err < 0)
8126 return err;
8127
8128 prop_buf = NULL;
8129 max_len = 0;
8130 if (!strcmp(namebuf, "model")) {
8131 prop_buf = np->vpd.model;
8132 max_len = NIU_VPD_MODEL_MAX;
8133 found_mask |= FOUND_MASK_MODEL;
8134 } else if (!strcmp(namebuf, "board-model")) {
8135 prop_buf = np->vpd.board_model;
8136 max_len = NIU_VPD_BD_MODEL_MAX;
8137 found_mask |= FOUND_MASK_BMODEL;
8138 } else if (!strcmp(namebuf, "version")) {
8139 prop_buf = np->vpd.version;
8140 max_len = NIU_VPD_VERSION_MAX;
8141 found_mask |= FOUND_MASK_VERS;
8142 } else if (!strcmp(namebuf, "local-mac-address")) {
8143 prop_buf = np->vpd.local_mac;
8144 max_len = ETH_ALEN;
8145 found_mask |= FOUND_MASK_MAC;
8146 } else if (!strcmp(namebuf, "num-mac-addresses")) {
8147 prop_buf = &np->vpd.mac_num;
8148 max_len = 1;
8149 found_mask |= FOUND_MASK_NMAC;
8150 } else if (!strcmp(namebuf, "phy-type")) {
8151 prop_buf = np->vpd.phy_type;
8152 max_len = NIU_VPD_PHY_TYPE_MAX;
8153 found_mask |= FOUND_MASK_PHY;
8154 }
8155
8156 if (max_len && prop_len > max_len) {
f10a1f2e 8157 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len);
a3138df9
DM		 8158 return -EINVAL;
8159 }
8160
8161 if (prop_buf) {
8162 u32 off = start + 5 + err;
8163 int i;
8164
f10a1f2e
JP		 8165 netif_printk(np, probe, KERN_DEBUG, np->dev,
8166 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8167 namebuf, prop_len);
a3138df9
DM		 8168 for (i = 0; i < prop_len; i++)
8169 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
8170 }
8171
8172 start += len;
8173 }
8174
8175 return 0;
8176}
8177
8178/* ESPC_PIO_EN_ENABLE must be set */
8179static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
8180{
8181 u32 offset;
8182 int err;
8183
8184 err = niu_pci_eeprom_read16_swp(np, start + 1);
8185 if (err < 0)
8186 return;
8187
8188 offset = err + 3;
8189
8190 while (start + offset < ESPC_EEPROM_SIZE) {
8191 u32 here = start + offset;
8192 u32 end;
8193
8194 err = niu_pci_eeprom_read(np, here);
8195 if (err != 0x90)
8196 return;
8197
8198 err = niu_pci_eeprom_read16_swp(np, here + 1);
8199 if (err < 0)
8200 return;
8201
8202 here = start + offset + 3;
8203 end = start + offset + err;
8204
8205 offset += err;
8206
8207 err = niu_pci_vpd_scan_props(np, here, end);
8208 if (err < 0 || err == 1)
8209 return;
8210 }
8211}
8212
8213/* ESPC_PIO_EN_ENABLE must be set */
8214static u32 __devinit niu_pci_vpd_offset(struct niu *np)
8215{
8216 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
8217 int err;
8218
8219 while (start < end) {
8220 ret = start;
8221
8222 /* ROM header signature? */
8223 err = niu_pci_eeprom_read16(np, start + 0);
8224 if (err != 0x55aa)
8225 return 0;
8226
8227 /* Apply offset to PCI data structure. */
8228 err = niu_pci_eeprom_read16(np, start + 23);
8229 if (err < 0)
8230 return 0;
8231 start += err;
8232
8233 /* Check for "PCIR" signature. */
8234 err = niu_pci_eeprom_read16(np, start + 0);
8235 if (err != 0x5043)
8236 return 0;
8237 err = niu_pci_eeprom_read16(np, start + 2);
8238 if (err != 0x4952)
8239 return 0;
8240
8241 /* Check for OBP image type. */
8242 err = niu_pci_eeprom_read(np, start + 20);
8243 if (err < 0)
8244 return 0;
8245 if (err != 0x01) {
8246 err = niu_pci_eeprom_read(np, ret + 2);
8247 if (err < 0)
8248 return 0;
8249
8250 start = ret + (err * 512);
8251 continue;
8252 }
8253
8254 err = niu_pci_eeprom_read16_swp(np, start + 8);
8255 if (err < 0)
8256 return err;
8257 ret += err;
8258
8259 err = niu_pci_eeprom_read(np, ret + 0);
8260 if (err != 0x82)
8261 return 0;
8262
8263 return ret;
8264 }
8265
8266 return 0;
8267}
8268
8269static int __devinit niu_phy_type_prop_decode(struct niu *np,
8270 const char *phy_prop)
8271{
8272 if (!strcmp(phy_prop, "mif")) {
8273 /* 1G copper, MII */
8274 np->flags &= ~(NIU_FLAGS_FIBER |
8275 NIU_FLAGS_10G);
8276 np->mac_xcvr = MAC_XCVR_MII;
8277 } else if (!strcmp(phy_prop, "xgf")) {
8278 /* 10G fiber, XPCS */
8279 np->flags |= (NIU_FLAGS_10G |
8280 NIU_FLAGS_FIBER);
8281 np->mac_xcvr = MAC_XCVR_XPCS;
8282 } else if (!strcmp(phy_prop, "pcs")) {
8283 /* 1G fiber, PCS */
8284 np->flags &= ~NIU_FLAGS_10G;
8285 np->flags |= NIU_FLAGS_FIBER;
8286 np->mac_xcvr = MAC_XCVR_PCS;
8287 } else if (!strcmp(phy_prop, "xgc")) {
8288 /* 10G copper, XPCS */
8289 np->flags |= NIU_FLAGS_10G;
8290 np->flags &= ~NIU_FLAGS_FIBER;
8291 np->mac_xcvr = MAC_XCVR_XPCS;
e3e081e1
SB		 8292 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) {
8293 /* 10G Serdes or 1G Serdes, default to 10G */
8294 np->flags |= NIU_FLAGS_10G;
8295 np->flags &= ~NIU_FLAGS_FIBER;
8296 np->flags |= NIU_FLAGS_XCVR_SERDES;
8297 np->mac_xcvr = MAC_XCVR_XPCS;
a3138df9
DM		 8298 } else {
8299 return -EINVAL;
8300 }
8301 return 0;
8302}
8303
7f7c4072
MW		 8304static int niu_pci_vpd_get_nports(struct niu *np)
8305{
8306 int ports = 0;
8307
f9af8574
MW		 8308 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) ||
8309 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) ||
8310 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) ||
8311 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) ||
8312 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) {
7f7c4072 8313 ports = 4;
f9af8574
MW		 8314 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) ||
8315 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) ||
8316 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) ||
8317 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) {
7f7c4072
MW		 8318 ports = 2;
8319 }
8320
8321 return ports;
8322}
8323
a3138df9
DM		 8324static void __devinit niu_pci_vpd_validate(struct niu *np)
8325{
8326 struct net_device *dev = np->dev;
8327 struct niu_vpd *vpd = &np->vpd;
8328 u8 val8;
8329
8330 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
f10a1f2e 8331 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n");
a3138df9
DM		 8332
8333 np->flags &= ~NIU_FLAGS_VPD_VALID;
8334 return;
8335 }
8336
f9af8574
MW		 8337 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8338 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8339 np->flags |= NIU_FLAGS_10G;
8340 np->flags &= ~NIU_FLAGS_FIBER;
8341 np->flags |= NIU_FLAGS_XCVR_SERDES;
8342 np->mac_xcvr = MAC_XCVR_PCS;
8343 if (np->port > 1) {
8344 np->flags |= NIU_FLAGS_FIBER;
8345 np->flags &= ~NIU_FLAGS_10G;
8346 }
8347 if (np->flags & NIU_FLAGS_10G)
f10a1f2e 8348 np->mac_xcvr = MAC_XCVR_XPCS;
f9af8574 8349 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8350 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
8351 NIU_FLAGS_HOTPLUG_PHY);
5fbd7e24 8352 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e 8353 dev_err(np->device, "Illegal phy string [%s]\n",
a3138df9 8354 np->vpd.phy_type);
f10a1f2e 8355 dev_err(np->device, "Falling back to SPROM\n");
a3138df9
DM		 8356 np->flags &= ~NIU_FLAGS_VPD_VALID;
8357 return;
8358 }
8359
8360 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
8361
8362 val8 = dev->perm_addr[5];
8363 dev->perm_addr[5] += np->port;
8364 if (dev->perm_addr[5] < val8)
8365 dev->perm_addr[4]++;
8366
8367 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8368}
8369
8370static int __devinit niu_pci_probe_sprom(struct niu *np)
8371{
8372 struct net_device *dev = np->dev;
8373 int len, i;
8374 u64 val, sum;
8375 u8 val8;
8376
8377 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8378 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8379 len = val / 4;
8380
8381 np->eeprom_len = len;
8382
f10a1f2e
JP		 8383 netif_printk(np, probe, KERN_DEBUG, np->dev,
8384 "SPROM: Image size %llu\n", (unsigned long long)val);
a3138df9
DM		 8385
8386 sum = 0;
8387 for (i = 0; i < len; i++) {
8388 val = nr64(ESPC_NCR(i));
8389 sum += (val >> 0) & 0xff;
8390 sum += (val >> 8) & 0xff;
8391 sum += (val >> 16) & 0xff;
8392 sum += (val >> 24) & 0xff;
8393 }
f10a1f2e
JP		 8394 netif_printk(np, probe, KERN_DEBUG, np->dev,
8395 "SPROM: Checksum %x\n", (int)(sum & 0xff));
a3138df9 8396 if ((sum & 0xff) != 0xab) {
f10a1f2e 8397 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff));
a3138df9
DM		 8398 return -EINVAL;
8399 }
8400
8401 val = nr64(ESPC_PHY_TYPE);
8402 switch (np->port) {
8403 case 0:
a9d41192 8404 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
a3138df9
DM		 8405 ESPC_PHY_TYPE_PORT0_SHIFT;
8406 break;
8407 case 1:
a9d41192 8408 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
a3138df9
DM		 8409 ESPC_PHY_TYPE_PORT1_SHIFT;
8410 break;
8411 case 2:
a9d41192 8412 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
a3138df9
DM		 8413 ESPC_PHY_TYPE_PORT2_SHIFT;
8414 break;
8415 case 3:
a9d41192 8416 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
a3138df9
DM		 8417 ESPC_PHY_TYPE_PORT3_SHIFT;
8418 break;
8419 default:
f10a1f2e 8420 dev_err(np->device, "Bogus port number %u\n",
a3138df9
DM		 8421 np->port);
8422 return -EINVAL;
8423 }
f10a1f2e
JP		 8424 netif_printk(np, probe, KERN_DEBUG, np->dev,
8425 "SPROM: PHY type %x\n", val8);
a3138df9 8426
a9d41192 8427 switch (val8) {
a3138df9
DM		 8428 case ESPC_PHY_TYPE_1G_COPPER:
8429 /* 1G copper, MII */
8430 np->flags &= ~(NIU_FLAGS_FIBER |
8431 NIU_FLAGS_10G);
8432 np->mac_xcvr = MAC_XCVR_MII;
8433 break;
8434
8435 case ESPC_PHY_TYPE_1G_FIBER:
8436 /* 1G fiber, PCS */
8437 np->flags &= ~NIU_FLAGS_10G;
8438 np->flags |= NIU_FLAGS_FIBER;
8439 np->mac_xcvr = MAC_XCVR_PCS;
8440 break;
8441
8442 case ESPC_PHY_TYPE_10G_COPPER:
8443 /* 10G copper, XPCS */
8444 np->flags |= NIU_FLAGS_10G;
8445 np->flags &= ~NIU_FLAGS_FIBER;
8446 np->mac_xcvr = MAC_XCVR_XPCS;
8447 break;
8448
8449 case ESPC_PHY_TYPE_10G_FIBER:
8450 /* 10G fiber, XPCS */
8451 np->flags |= (NIU_FLAGS_10G |
8452 NIU_FLAGS_FIBER);
8453 np->mac_xcvr = MAC_XCVR_XPCS;
8454 break;
8455
8456 default:
f10a1f2e 8457 dev_err(np->device, "Bogus SPROM phy type %u\n", val8);
a3138df9
DM		 8458 return -EINVAL;
8459 }
8460
8461 val = nr64(ESPC_MAC_ADDR0);
f10a1f2e
JP		 8462 netif_printk(np, probe, KERN_DEBUG, np->dev,
8463 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8464 dev->perm_addr[0] = (val >> 0) & 0xff;
8465 dev->perm_addr[1] = (val >> 8) & 0xff;
8466 dev->perm_addr[2] = (val >> 16) & 0xff;
8467 dev->perm_addr[3] = (val >> 24) & 0xff;
8468
8469 val = nr64(ESPC_MAC_ADDR1);
f10a1f2e
JP		 8470 netif_printk(np, probe, KERN_DEBUG, np->dev,
8471 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
a3138df9
DM		 8472 dev->perm_addr[4] = (val >> 0) & 0xff;
8473 dev->perm_addr[5] = (val >> 8) & 0xff;
8474
8475 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 8476 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n",
8477 dev->perm_addr);
a3138df9
DM		 8478 return -EINVAL;
8479 }
8480
8481 val8 = dev->perm_addr[5];
8482 dev->perm_addr[5] += np->port;
8483 if (dev->perm_addr[5] < val8)
8484 dev->perm_addr[4]++;
8485
8486 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
8487
8488 val = nr64(ESPC_MOD_STR_LEN);
f10a1f2e
JP		 8489 netif_printk(np, probe, KERN_DEBUG, np->dev,
8490 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8491 if (val >= 8 * 4)
a3138df9
DM		 8492 return -EINVAL;
8493
8494 for (i = 0; i < val; i += 4) {
8495 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8496
8497 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
8498 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
8499 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
8500 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
8501 }
8502 np->vpd.model[val] = '\0';
8503
8504 val = nr64(ESPC_BD_MOD_STR_LEN);
f10a1f2e
JP		 8505 netif_printk(np, probe, KERN_DEBUG, np->dev,
8506 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
e6a5fdf5 8507 if (val >= 4 * 4)
a3138df9
DM		 8508 return -EINVAL;
8509
8510 for (i = 0; i < val; i += 4) {
8511 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8512
8513 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
8514 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
8515 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
8516 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
8517 }
8518 np->vpd.board_model[val] = '\0';
8519
8520 np->vpd.mac_num =
8521 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
f10a1f2e
JP		 8522 netif_printk(np, probe, KERN_DEBUG, np->dev,
8523 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num);
a3138df9
DM		 8524
8525 return 0;
8526}
8527
8528static int __devinit niu_get_and_validate_port(struct niu *np)
8529{
8530 struct niu_parent *parent = np->parent;
8531
8532 if (np->port <= 1)
8533 np->flags |= NIU_FLAGS_XMAC;
8534
8535 if (!parent->num_ports) {
8536 if (parent->plat_type == PLAT_TYPE_NIU) {
8537 parent->num_ports = 2;
8538 } else {
7f7c4072
MW		 8539 parent->num_ports = niu_pci_vpd_get_nports(np);
8540 if (!parent->num_ports) {
8541 /* Fall back to SPROM as last resort.
8542 * This will fail on most cards.
8543 */
8544 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
8545 ESPC_NUM_PORTS_MACS_VAL;
8546
be0c007a
DM		 8547 /* All of the current probing methods fail on
8548 * Maramba on-board parts.
8549 */
7f7c4072 8550 if (!parent->num_ports)
be0c007a 8551 parent->num_ports = 4;
7f7c4072 8552 }
a3138df9
DM		 8553 }
8554 }
8555
a3138df9
DM		 8556 if (np->port >= parent->num_ports)
8557 return -ENODEV;
8558
8559 return 0;
8560}
8561
8562static int __devinit phy_record(struct niu_parent *parent,
8563 struct phy_probe_info *p,
8564 int dev_id_1, int dev_id_2, u8 phy_port,
8565 int type)
8566{
8567 u32 id = (dev_id_1 << 16) | dev_id_2;
8568 u8 idx;
8569
8570 if (dev_id_1 < 0 || dev_id_2 < 0)
8571 return 0;
8572 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
b0de8e40 8573 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
a5d6ab56
MW		 8574 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) &&
8575 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706))
a3138df9
DM		 8576 return 0;
8577 } else {
8578 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
8579 return 0;
8580 }
8581
8582 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8583 parent->index, id,
f10a1f2e
JP		 8584 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" :
8585 type == PHY_TYPE_PCS ? "PCS" : "MII",
a3138df9
DM		 8586 phy_port);
8587
8588 if (p->cur[type] >= NIU_MAX_PORTS) {
f10a1f2e 8589 pr_err("Too many PHY ports\n");
a3138df9
DM		 8590 return -EINVAL;
8591 }
8592 idx = p->cur[type];
8593 p->phy_id[type][idx] = id;
8594 p->phy_port[type][idx] = phy_port;
8595 p->cur[type] = idx + 1;
8596 return 0;
8597}
8598
8599static int __devinit port_has_10g(struct phy_probe_info *p, int port)
8600{
8601 int i;
8602
8603 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
8604 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8605 return 1;
8606 }
8607 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
8608 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8609 return 1;
8610 }
8611
8612 return 0;
8613}
8614
8615static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
8616{
8617 int port, cnt;
8618
8619 cnt = 0;
8620 *lowest = 32;
8621 for (port = 8; port < 32; port++) {
8622 if (port_has_10g(p, port)) {
8623 if (!cnt)
8624 *lowest = port;
8625 cnt++;
8626 }
8627 }
8628
8629 return cnt;
8630}
8631
8632static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
8633{
8634 *lowest = 32;
8635 if (p->cur[PHY_TYPE_MII])
8636 *lowest = p->phy_port[PHY_TYPE_MII][0];
8637
8638 return p->cur[PHY_TYPE_MII];
8639}
8640
8641static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
8642{
8643 int num_ports = parent->num_ports;
8644 int i;
8645
8646 for (i = 0; i < num_ports; i++) {
8647 parent->rxchan_per_port[i] = (16 / num_ports);
8648 parent->txchan_per_port[i] = (16 / num_ports);
8649
f10a1f2e 8650 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8651 parent->index, i,
8652 parent->rxchan_per_port[i],
8653 parent->txchan_per_port[i]);
8654 }
8655}
8656
8657static void __devinit niu_divide_channels(struct niu_parent *parent,
8658 int num_10g, int num_1g)
8659{
8660 int num_ports = parent->num_ports;
8661 int rx_chans_per_10g, rx_chans_per_1g;
8662 int tx_chans_per_10g, tx_chans_per_1g;
8663 int i, tot_rx, tot_tx;
8664
8665 if (!num_10g || !num_1g) {
8666 rx_chans_per_10g = rx_chans_per_1g =
8667 (NIU_NUM_RXCHAN / num_ports);
8668 tx_chans_per_10g = tx_chans_per_1g =
8669 (NIU_NUM_TXCHAN / num_ports);
8670 } else {
8671 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
8672 rx_chans_per_10g = (NIU_NUM_RXCHAN -
8673 (rx_chans_per_1g * num_1g)) /
8674 num_10g;
8675
8676 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
8677 tx_chans_per_10g = (NIU_NUM_TXCHAN -
8678 (tx_chans_per_1g * num_1g)) /
8679 num_10g;
8680 }
8681
8682 tot_rx = tot_tx = 0;
8683 for (i = 0; i < num_ports; i++) {
8684 int type = phy_decode(parent->port_phy, i);
8685
8686 if (type == PORT_TYPE_10G) {
8687 parent->rxchan_per_port[i] = rx_chans_per_10g;
8688 parent->txchan_per_port[i] = tx_chans_per_10g;
8689 } else {
8690 parent->rxchan_per_port[i] = rx_chans_per_1g;
8691 parent->txchan_per_port[i] = tx_chans_per_1g;
8692 }
f10a1f2e 8693 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
a3138df9
DM		 8694 parent->index, i,
8695 parent->rxchan_per_port[i],
8696 parent->txchan_per_port[i]);
8697 tot_rx += parent->rxchan_per_port[i];
8698 tot_tx += parent->txchan_per_port[i];
8699 }
8700
8701 if (tot_rx > NIU_NUM_RXCHAN) {
f10a1f2e 8702 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
a3138df9
DM		 8703 parent->index, tot_rx);
8704 for (i = 0; i < num_ports; i++)
8705 parent->rxchan_per_port[i] = 1;
8706 }
8707 if (tot_tx > NIU_NUM_TXCHAN) {
f10a1f2e 8708 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
a3138df9
DM		 8709 parent->index, tot_tx);
8710 for (i = 0; i < num_ports; i++)
8711 parent->txchan_per_port[i] = 1;
8712 }
8713 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
f10a1f2e
JP		 8714 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8715 parent->index, tot_rx, tot_tx);
a3138df9
DM		 8716 }
8717}
8718
8719static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
8720 int num_10g, int num_1g)
8721{
8722 int i, num_ports = parent->num_ports;
8723 int rdc_group, rdc_groups_per_port;
8724 int rdc_channel_base;
8725
8726 rdc_group = 0;
8727 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
8728
8729 rdc_channel_base = 0;
8730
8731 for (i = 0; i < num_ports; i++) {
8732 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
8733 int grp, num_channels = parent->rxchan_per_port[i];
8734 int this_channel_offset;
8735
8736 tp->first_table_num = rdc_group;
8737 tp->num_tables = rdc_groups_per_port;
8738 this_channel_offset = 0;
8739 for (grp = 0; grp < tp->num_tables; grp++) {
8740 struct rdc_table *rt = &tp->tables[grp];
8741 int slot;
8742
f10a1f2e 8743 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
a3138df9
DM		 8744 parent->index, i, tp->first_table_num + grp);
8745 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
8746 rt->rxdma_channel[slot] =
8747 rdc_channel_base + this_channel_offset;
8748
f10a1f2e 8749 pr_cont("%d ", rt->rxdma_channel[slot]);
a3138df9
DM		 8750
8751 if (++this_channel_offset == num_channels)
8752 this_channel_offset = 0;
8753 }
f10a1f2e 8754 pr_cont("]\n");
a3138df9
DM		 8755 }
8756
8757 parent->rdc_default[i] = rdc_channel_base;
8758
8759 rdc_channel_base += num_channels;
8760 rdc_group += rdc_groups_per_port;
8761 }
8762}
8763
8764static int __devinit fill_phy_probe_info(struct niu *np,
8765 struct niu_parent *parent,
8766 struct phy_probe_info *info)
8767{
8768 unsigned long flags;
8769 int port, err;
8770
8771 memset(info, 0, sizeof(*info));
8772
8773 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8774 niu_lock_parent(np, flags);
8775 err = 0;
8776 for (port = 8; port < 32; port++) {
8777 int dev_id_1, dev_id_2;
8778
8779 dev_id_1 = mdio_read(np, port,
8780 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
8781 dev_id_2 = mdio_read(np, port,
8782 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
8783 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8784 PHY_TYPE_PMA_PMD);
8785 if (err)
8786 break;
8787 dev_id_1 = mdio_read(np, port,
8788 NIU_PCS_DEV_ADDR, MII_PHYSID1);
8789 dev_id_2 = mdio_read(np, port,
8790 NIU_PCS_DEV_ADDR, MII_PHYSID2);
8791 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8792 PHY_TYPE_PCS);
8793 if (err)
8794 break;
8795 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8796 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8797 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8798 PHY_TYPE_MII);
8799 if (err)
8800 break;
8801 }
8802 niu_unlock_parent(np, flags);
8803
8804 return err;
8805}
8806
8807static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
8808{
8809 struct phy_probe_info *info = &parent->phy_probe_info;
8810 int lowest_10g, lowest_1g;
8811 int num_10g, num_1g;
8812 u32 val;
8813 int err;
8814
e3e081e1
SB		 8815 num_10g = num_1g = 0;
8816
f9af8574
MW		 8817 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) ||
8818 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) {
5fbd7e24
MW		 8819 num_10g = 0;
8820 num_1g = 2;
8821 parent->plat_type = PLAT_TYPE_ATCA_CP3220;
8822 parent->num_ports = 4;
8823 val = (phy_encode(PORT_TYPE_1G, 0) |
8824 phy_encode(PORT_TYPE_1G, 1) |
a3138df9
DM		 8825 phy_encode(PORT_TYPE_1G, 2) |
8826 phy_encode(PORT_TYPE_1G, 3));
f9af8574 8827 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) {
a5d6ab56
MW		 8828 num_10g = 2;
8829 num_1g = 0;
8830 parent->num_ports = 2;
8831 val = (phy_encode(PORT_TYPE_10G, 0) |
8832 phy_encode(PORT_TYPE_10G, 1));
e3e081e1
SB		 8833 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) &&
8834 (parent->plat_type == PLAT_TYPE_NIU)) {
8835 /* this is the Monza case */
8836 if (np->flags & NIU_FLAGS_10G) {
8837 val = (phy_encode(PORT_TYPE_10G, 0) |
8838 phy_encode(PORT_TYPE_10G, 1));
8839 } else {
8840 val = (phy_encode(PORT_TYPE_1G, 0) |
8841 phy_encode(PORT_TYPE_1G, 1));
8842 }
5fbd7e24
MW		 8843 } else {
8844 err = fill_phy_probe_info(np, parent, info);
8845 if (err)
8846 return err;
a3138df9 8847
5fbd7e24
MW		 8848 num_10g = count_10g_ports(info, &lowest_10g);
8849 num_1g = count_1g_ports(info, &lowest_1g);
a3138df9 8850
5fbd7e24
MW		 8851 switch ((num_10g << 4) | num_1g) {
8852 case 0x24:
8853 if (lowest_1g == 10)
8854 parent->plat_type = PLAT_TYPE_VF_P0;
8855 else if (lowest_1g == 26)
8856 parent->plat_type = PLAT_TYPE_VF_P1;
8857 else
8858 goto unknown_vg_1g_port;
a3138df9 8859
5fbd7e24
MW		 8860 /* fallthru */
8861 case 0x22:
a3138df9 8862 val = (phy_encode(PORT_TYPE_10G, 0) |
a3138df9
DM		 8863 phy_encode(PORT_TYPE_10G, 1) |
8864 phy_encode(PORT_TYPE_1G, 2) |
8865 phy_encode(PORT_TYPE_1G, 3));
5fbd7e24 8866 break;
a3138df9 8867
5fbd7e24
MW		 8868 case 0x20:
8869 val = (phy_encode(PORT_TYPE_10G, 0) |
8870 phy_encode(PORT_TYPE_10G, 1));
8871 break;
a3138df9 8872
5fbd7e24
MW		 8873 case 0x10:
8874 val = phy_encode(PORT_TYPE_10G, np->port);
8875 break;
a3138df9 8876
5fbd7e24
MW		 8877 case 0x14:
8878 if (lowest_1g == 10)
8879 parent->plat_type = PLAT_TYPE_VF_P0;
8880 else if (lowest_1g == 26)
8881 parent->plat_type = PLAT_TYPE_VF_P1;
8882 else
8883 goto unknown_vg_1g_port;
8884
8885 /* fallthru */
8886 case 0x13:
8887 if ((lowest_10g & 0x7) == 0)
8888 val = (phy_encode(PORT_TYPE_10G, 0) |
8889 phy_encode(PORT_TYPE_1G, 1) |
8890 phy_encode(PORT_TYPE_1G, 2) |
8891 phy_encode(PORT_TYPE_1G, 3));
8892 else
8893 val = (phy_encode(PORT_TYPE_1G, 0) |
8894 phy_encode(PORT_TYPE_10G, 1) |
8895 phy_encode(PORT_TYPE_1G, 2) |
8896 phy_encode(PORT_TYPE_1G, 3));
8897 break;
8898
8899 case 0x04:
8900 if (lowest_1g == 10)
8901 parent->plat_type = PLAT_TYPE_VF_P0;
8902 else if (lowest_1g == 26)
8903 parent->plat_type = PLAT_TYPE_VF_P1;
8904 else
8905 goto unknown_vg_1g_port;
8906
8907 val = (phy_encode(PORT_TYPE_1G, 0) |
8908 phy_encode(PORT_TYPE_1G, 1) |
8909 phy_encode(PORT_TYPE_1G, 2) |
8910 phy_encode(PORT_TYPE_1G, 3));
8911 break;
8912
8913 default:
f10a1f2e 8914 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
5fbd7e24
MW		 8915 num_10g, num_1g);
8916 return -EINVAL;
8917 }
a3138df9
DM		 8918 }
8919
8920 parent->port_phy = val;
8921
8922 if (parent->plat_type == PLAT_TYPE_NIU)
8923 niu_n2_divide_channels(parent);
8924 else
8925 niu_divide_channels(parent, num_10g, num_1g);
8926
8927 niu_divide_rdc_groups(parent, num_10g, num_1g);
8928
8929 return 0;
8930
8931unknown_vg_1g_port:
f10a1f2e 8932 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g);
a3138df9
DM		 8933 return -EINVAL;
8934}
8935
8936static int __devinit niu_probe_ports(struct niu *np)
8937{
8938 struct niu_parent *parent = np->parent;
8939 int err, i;
8940
a3138df9
DM		 8941 if (parent->port_phy == PORT_PHY_UNKNOWN) {
8942 err = walk_phys(np, parent);
8943 if (err)
8944 return err;
8945
8946 niu_set_ldg_timer_res(np, 2);
8947 for (i = 0; i <= LDN_MAX; i++)
8948 niu_ldn_irq_enable(np, i, 0);
8949 }
8950
8951 if (parent->port_phy == PORT_PHY_INVALID)
8952 return -EINVAL;
8953
8954 return 0;
8955}
8956
8957static int __devinit niu_classifier_swstate_init(struct niu *np)
8958{
8959 struct niu_classifier *cp = &np->clas;
8960
2d96cf8c
SB		 8961 cp->tcam_top = (u16) np->port;
8962 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports;
a3138df9
DM		 8963 cp->h1_init = 0xffffffff;
8964 cp->h2_init = 0xffff;
8965
8966 return fflp_early_init(np);
8967}
8968
8969static void __devinit niu_link_config_init(struct niu *np)
8970{
8971 struct niu_link_config *lp = &np->link_config;
8972
8973 lp->advertising = (ADVERTISED_10baseT_Half |
8974 ADVERTISED_10baseT_Full |
8975 ADVERTISED_100baseT_Half |
8976 ADVERTISED_100baseT_Full |
8977 ADVERTISED_1000baseT_Half |
8978 ADVERTISED_1000baseT_Full |
8979 ADVERTISED_10000baseT_Full |
8980 ADVERTISED_Autoneg);
8981 lp->speed = lp->active_speed = SPEED_INVALID;
38bb045d
CB		 8982 lp->duplex = DUPLEX_FULL;
8983 lp->active_duplex = DUPLEX_INVALID;
8984 lp->autoneg = 1;
a3138df9
DM		 8985#if 0
8986 lp->loopback_mode = LOOPBACK_MAC;
8987 lp->active_speed = SPEED_10000;
8988 lp->active_duplex = DUPLEX_FULL;
8989#else
8990 lp->loopback_mode = LOOPBACK_DISABLED;
8991#endif
8992}
8993
8994static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
8995{
8996 switch (np->port) {
8997 case 0:
8998 np->mac_regs = np->regs + XMAC_PORT0_OFF;
8999 np->ipp_off = 0x00000;
9000 np->pcs_off = 0x04000;
9001 np->xpcs_off = 0x02000;
9002 break;
9003
9004 case 1:
9005 np->mac_regs = np->regs + XMAC_PORT1_OFF;
9006 np->ipp_off = 0x08000;
9007 np->pcs_off = 0x0a000;
9008 np->xpcs_off = 0x08000;
9009 break;
9010
9011 case 2:
9012 np->mac_regs = np->regs + BMAC_PORT2_OFF;
9013 np->ipp_off = 0x04000;
9014 np->pcs_off = 0x0e000;
9015 np->xpcs_off = ~0UL;
9016 break;
9017
9018 case 3:
9019 np->mac_regs = np->regs + BMAC_PORT3_OFF;
9020 np->ipp_off = 0x0c000;
9021 np->pcs_off = 0x12000;
9022 np->xpcs_off = ~0UL;
9023 break;
9024
9025 default:
f10a1f2e 9026 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
a3138df9
DM		 9027 return -EINVAL;
9028 }
9029
9030 return 0;
9031}
9032
9033static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
9034{
9035 struct msix_entry msi_vec[NIU_NUM_LDG];
9036 struct niu_parent *parent = np->parent;
9037 struct pci_dev *pdev = np->pdev;
9038 int i, num_irqs, err;
9039 u8 first_ldg;
9040
9041 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9042 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
9043 ldg_num_map[i] = first_ldg + i;
9044
9045 num_irqs = (parent->rxchan_per_port[np->port] +
9046 parent->txchan_per_port[np->port] +
9047 (np->port == 0 ? 3 : 1));
9048 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
9049
9050retry:
9051 for (i = 0; i < num_irqs; i++) {
9052 msi_vec[i].vector = 0;
9053 msi_vec[i].entry = i;
9054 }
9055
9056 err = pci_enable_msix(pdev, msi_vec, num_irqs);
9057 if (err < 0) {
9058 np->flags &= ~NIU_FLAGS_MSIX;
9059 return;
9060 }
9061 if (err > 0) {
9062 num_irqs = err;
9063 goto retry;
9064 }
9065
9066 np->flags |= NIU_FLAGS_MSIX;
9067 for (i = 0; i < num_irqs; i++)
9068 np->ldg[i].irq = msi_vec[i].vector;
9069 np->num_ldg = num_irqs;
9070}
9071
9072static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
9073{
9074#ifdef CONFIG_SPARC64
2dc11581 9075 struct platform_device *op = np->op;
a3138df9
DM		 9076 const u32 *int_prop;
9077 int i;
9078
61c7a080 9079 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL);
a3138df9
DM		 9080 if (!int_prop)
9081 return -ENODEV;
9082
1636f8ac 9083 for (i = 0; i < op->archdata.num_irqs; i++) {
a3138df9 9084 ldg_num_map[i] = int_prop[i];
1636f8ac 9085 np->ldg[i].irq = op->archdata.irqs[i];
a3138df9
DM		 9086 }
9087
1636f8ac 9088 np->num_ldg = op->archdata.num_irqs;
a3138df9
DM		 9089
9090 return 0;
9091#else
9092 return -EINVAL;
9093#endif
9094}
9095
9096static int __devinit niu_ldg_init(struct niu *np)
9097{
9098 struct niu_parent *parent = np->parent;
9099 u8 ldg_num_map[NIU_NUM_LDG];
9100 int first_chan, num_chan;
9101 int i, err, ldg_rotor;
9102 u8 port;
9103
9104 np->num_ldg = 1;
9105 np->ldg[0].irq = np->dev->irq;
9106 if (parent->plat_type == PLAT_TYPE_NIU) {
9107 err = niu_n2_irq_init(np, ldg_num_map);
9108 if (err)
9109 return err;
9110 } else
9111 niu_try_msix(np, ldg_num_map);
9112
9113 port = np->port;
9114 for (i = 0; i < np->num_ldg; i++) {
9115 struct niu_ldg *lp = &np->ldg[i];
9116
9117 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
9118
9119 lp->np = np;
9120 lp->ldg_num = ldg_num_map[i];
9121 lp->timer = 2; /* XXX */
9122
9123 /* On N2 NIU the firmware has setup the SID mappings so they go
9124 * to the correct values that will route the LDG to the proper
9125 * interrupt in the NCU interrupt table.
9126 */
9127 if (np->parent->plat_type != PLAT_TYPE_NIU) {
9128 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9129 if (err)
9130 return err;
9131 }
9132 }
9133
9134 /* We adopt the LDG assignment ordering used by the N2 NIU
9135 * 'interrupt' properties because that simplifies a lot of
9136 * things. This ordering is:
9137 *
9138 * MAC
9139 * MIF (if port zero)
9140 * SYSERR (if port zero)
9141 * RX channels
9142 * TX channels
9143 */
9144
9145 ldg_rotor = 0;
9146
9147 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9148 LDN_MAC(port));
9149 if (err)
9150 return err;
9151
9152 ldg_rotor++;
9153 if (ldg_rotor == np->num_ldg)
9154 ldg_rotor = 0;
9155
9156 if (port == 0) {
9157 err = niu_ldg_assign_ldn(np, parent,
9158 ldg_num_map[ldg_rotor],
9159 LDN_MIF);
9160 if (err)
9161 return err;
9162
9163 ldg_rotor++;
9164 if (ldg_rotor == np->num_ldg)
9165 ldg_rotor = 0;
9166
9167 err = niu_ldg_assign_ldn(np, parent,
9168 ldg_num_map[ldg_rotor],
9169 LDN_DEVICE_ERROR);
9170 if (err)
9171 return err;
9172
9173 ldg_rotor++;
9174 if (ldg_rotor == np->num_ldg)
9175 ldg_rotor = 0;
9176
9177 }
9178
9179 first_chan = 0;
9180 for (i = 0; i < port; i++)
9181 first_chan += parent->rxchan_per_port[port];
9182 num_chan = parent->rxchan_per_port[port];
9183
9184 for (i = first_chan; i < (first_chan + num_chan); i++) {
9185 err = niu_ldg_assign_ldn(np, parent,
9186 ldg_num_map[ldg_rotor],
9187 LDN_RXDMA(i));
9188 if (err)
9189 return err;
9190 ldg_rotor++;
9191 if (ldg_rotor == np->num_ldg)
9192 ldg_rotor = 0;
9193 }
9194
9195 first_chan = 0;
9196 for (i = 0; i < port; i++)
9197 first_chan += parent->txchan_per_port[port];
9198 num_chan = parent->txchan_per_port[port];
9199 for (i = first_chan; i < (first_chan + num_chan); i++) {
9200 err = niu_ldg_assign_ldn(np, parent,
9201 ldg_num_map[ldg_rotor],
9202 LDN_TXDMA(i));
9203 if (err)
9204 return err;
9205 ldg_rotor++;
9206 if (ldg_rotor == np->num_ldg)
9207 ldg_rotor = 0;
9208 }
9209
9210 return 0;
9211}
9212
9213static void __devexit niu_ldg_free(struct niu *np)
9214{
9215 if (np->flags & NIU_FLAGS_MSIX)
9216 pci_disable_msix(np->pdev);
9217}
9218
9219static int __devinit niu_get_of_props(struct niu *np)
9220{
9221#ifdef CONFIG_SPARC64
9222 struct net_device *dev = np->dev;
9223 struct device_node *dp;
9224 const char *phy_type;
9225 const u8 *mac_addr;
f9af8574 9226 const char *model;
a3138df9
DM		 9227 int prop_len;
9228
9229 if (np->parent->plat_type == PLAT_TYPE_NIU)
61c7a080 9230 dp = np->op->dev.of_node;
a3138df9
DM		 9231 else
9232 dp = pci_device_to_OF_node(np->pdev);
9233
9234 phy_type = of_get_property(dp, "phy-type", &prop_len);
9235 if (!phy_type) {
f10a1f2e
JP		 9236 netdev_err(dev, "%s: OF node lacks phy-type property\n",
9237 dp->full_name);
a3138df9
DM		 9238 return -EINVAL;
9239 }
9240
9241 if (!strcmp(phy_type, "none"))
9242 return -ENODEV;
9243
9244 strcpy(np->vpd.phy_type, phy_type);
9245
9246 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
f10a1f2e
JP		 9247 netdev_err(dev, "%s: Illegal phy string [%s]\n",
9248 dp->full_name, np->vpd.phy_type);
a3138df9
DM		 9249 return -EINVAL;
9250 }
9251
9252 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
9253 if (!mac_addr) {
f10a1f2e
JP		 9254 netdev_err(dev, "%s: OF node lacks local-mac-address property\n",
9255 dp->full_name);
a3138df9
DM		 9256 return -EINVAL;
9257 }
9258 if (prop_len != dev->addr_len) {
f10a1f2e
JP		 9259 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n",
9260 dp->full_name, prop_len);
a3138df9
DM		 9261 }
9262 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
9263 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
f10a1f2e
JP		 9264 netdev_err(dev, "%s: OF MAC address is invalid\n",
9265 dp->full_name);
9266 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr);
a3138df9
DM		 9267 return -EINVAL;
9268 }
9269
9270 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
f9af8574
MW		 9271
9272 model = of_get_property(dp, "model", &prop_len);
9273
9274 if (model)
9275 strcpy(np->vpd.model, model);
a3138df9 9276
9c5cd670
TC		 9277 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) {
9278 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER |
9279 NIU_FLAGS_HOTPLUG_PHY);
9280 }
9281
a3138df9
DM		 9282 return 0;
9283#else
9284 return -EINVAL;
9285#endif
9286}
9287
9288static int __devinit niu_get_invariants(struct niu *np)
9289{
9290 int err, have_props;
9291 u32 offset;
9292
9293 err = niu_get_of_props(np);
9294 if (err == -ENODEV)
9295 return err;
9296
9297 have_props = !err;
9298
a3138df9
DM		 9299 err = niu_init_mac_ipp_pcs_base(np);
9300 if (err)
9301 return err;
9302
7f7c4072
MW		 9303 if (have_props) {
9304 err = niu_get_and_validate_port(np);
9305 if (err)
9306 return err;
9307
9308 } else {
a3138df9
DM		 9309 if (np->parent->plat_type == PLAT_TYPE_NIU)
9310 return -EINVAL;
9311
9312 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9313 offset = niu_pci_vpd_offset(np);
f10a1f2e
JP		 9314 netif_printk(np, probe, KERN_DEBUG, np->dev,
9315 "%s() VPD offset [%08x]\n", __func__, offset);
a3138df9
DM		 9316 if (offset)
9317 niu_pci_vpd_fetch(np, offset);
9318 nw64(ESPC_PIO_EN, 0);
9319
7f7c4072 9320 if (np->flags & NIU_FLAGS_VPD_VALID) {
a3138df9 9321 niu_pci_vpd_validate(np);
7f7c4072
MW		 9322 err = niu_get_and_validate_port(np);
9323 if (err)
9324 return err;
9325 }
a3138df9
DM		 9326
9327 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7f7c4072
MW		 9328 err = niu_get_and_validate_port(np);
9329 if (err)
9330 return err;
a3138df9
DM		 9331 err = niu_pci_probe_sprom(np);
9332 if (err)
9333 return err;
9334 }
9335 }
9336
9337 err = niu_probe_ports(np);
9338 if (err)
9339 return err;
9340
9341 niu_ldg_init(np);
9342
9343 niu_classifier_swstate_init(np);
9344 niu_link_config_init(np);
9345
9346 err = niu_determine_phy_disposition(np);
9347 if (!err)
9348 err = niu_init_link(np);
9349
9350 return err;
9351}
9352
9353static LIST_HEAD(niu_parent_list);
9354static DEFINE_MUTEX(niu_parent_lock);
9355static int niu_parent_index;
9356
9357static ssize_t show_port_phy(struct device *dev,
9358 struct device_attribute *attr, char *buf)
9359{
9360 struct platform_device *plat_dev = to_platform_device(dev);
9361 struct niu_parent *p = plat_dev->dev.platform_data;
9362 u32 port_phy = p->port_phy;
9363 char *orig_buf = buf;
9364 int i;
9365
9366 if (port_phy == PORT_PHY_UNKNOWN ||
9367 port_phy == PORT_PHY_INVALID)
9368 return 0;
9369
9370 for (i = 0; i < p->num_ports; i++) {
9371 const char *type_str;
9372 int type;
9373
9374 type = phy_decode(port_phy, i);
9375 if (type == PORT_TYPE_10G)
9376 type_str = "10G";
9377 else
9378 type_str = "1G";
9379 buf += sprintf(buf,
9380 (i == 0) ? "%s" : " %s",
9381 type_str);
9382 }
9383 buf += sprintf(buf, "\n");
9384 return buf - orig_buf;
9385}
9386
9387static ssize_t show_plat_type(struct device *dev,
9388 struct device_attribute *attr, char *buf)
9389{
9390 struct platform_device *plat_dev = to_platform_device(dev);
9391 struct niu_parent *p = plat_dev->dev.platform_data;
9392 const char *type_str;
9393
9394 switch (p->plat_type) {
9395 case PLAT_TYPE_ATLAS:
9396 type_str = "atlas";
9397 break;
9398 case PLAT_TYPE_NIU:
9399 type_str = "niu";
9400 break;
9401 case PLAT_TYPE_VF_P0:
9402 type_str = "vf_p0";
9403 break;
9404 case PLAT_TYPE_VF_P1:
9405 type_str = "vf_p1";
9406 break;
9407 default:
9408 type_str = "unknown";
9409 break;
9410 }
9411
9412 return sprintf(buf, "%s\n", type_str);
9413}
9414
9415static ssize_t __show_chan_per_port(struct device *dev,
9416 struct device_attribute *attr, char *buf,
9417 int rx)
9418{
9419 struct platform_device *plat_dev = to_platform_device(dev);
9420 struct niu_parent *p = plat_dev->dev.platform_data;
9421 char *orig_buf = buf;
9422 u8 *arr;
9423 int i;
9424
9425 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
9426
9427 for (i = 0; i < p->num_ports; i++) {
9428 buf += sprintf(buf,
9429 (i == 0) ? "%d" : " %d",
9430 arr[i]);
9431 }
9432 buf += sprintf(buf, "\n");
9433
9434 return buf - orig_buf;
9435}
9436
9437static ssize_t show_rxchan_per_port(struct device *dev,
9438 struct device_attribute *attr, char *buf)
9439{
9440 return __show_chan_per_port(dev, attr, buf, 1);
9441}
9442
9443static ssize_t show_txchan_per_port(struct device *dev,
9444 struct device_attribute *attr, char *buf)
9445{
9446 return __show_chan_per_port(dev, attr, buf, 1);
9447}
9448
9449static ssize_t show_num_ports(struct device *dev,
9450 struct device_attribute *attr, char *buf)
9451{
9452 struct platform_device *plat_dev = to_platform_device(dev);
9453 struct niu_parent *p = plat_dev->dev.platform_data;
9454
9455 return sprintf(buf, "%d\n", p->num_ports);
9456}
9457
9458static struct device_attribute niu_parent_attributes[] = {
9459 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
9460 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
9461 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
9462 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
9463 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
9464 {}
9465};
9466
9467static struct niu_parent * __devinit niu_new_parent(struct niu *np,
9468 union niu_parent_id *id,
9469 u8 ptype)
9470{
9471 struct platform_device *plat_dev;
9472 struct niu_parent *p;
9473 int i;
9474
a3138df9
DM		 9475 plat_dev = platform_device_register_simple("niu", niu_parent_index,
9476 NULL, 0);
58f3e0a8 9477 if (IS_ERR(plat_dev))
a3138df9
DM		 9478 return NULL;
9479
9480 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
9481 int err = device_create_file(&plat_dev->dev,
9482 &niu_parent_attributes[i]);
9483 if (err)
9484 goto fail_unregister;
9485 }
9486
9487 p = kzalloc(sizeof(*p), GFP_KERNEL);
9488 if (!p)
9489 goto fail_unregister;
9490
9491 p->index = niu_parent_index++;
9492
9493 plat_dev->dev.platform_data = p;
9494 p->plat_dev = plat_dev;
9495
9496 memcpy(&p->id, id, sizeof(*id));
9497 p->plat_type = ptype;
9498 INIT_LIST_HEAD(&p->list);
9499 atomic_set(&p->refcnt, 0);
9500 list_add(&p->list, &niu_parent_list);
9501 spin_lock_init(&p->lock);
9502
9503 p->rxdma_clock_divider = 7500;
9504
9505 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
9506 if (p->plat_type == PLAT_TYPE_NIU)
9507 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
9508
9509 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
9510 int index = i - CLASS_CODE_USER_PROG1;
9511
9512 p->tcam_key[index] = TCAM_KEY_TSEL;
9513 p->flow_key[index] = (FLOW_KEY_IPSA |
9514 FLOW_KEY_IPDA |
9515 FLOW_KEY_PROTO |
9516 (FLOW_KEY_L4_BYTE12 <<
9517 FLOW_KEY_L4_0_SHIFT) |
9518 (FLOW_KEY_L4_BYTE12 <<
9519 FLOW_KEY_L4_1_SHIFT));
9520 }
9521
9522 for (i = 0; i < LDN_MAX + 1; i++)
9523 p->ldg_map[i] = LDG_INVALID;
9524
9525 return p;
9526
9527fail_unregister:
9528 platform_device_unregister(plat_dev);
9529 return NULL;
9530}
9531
9532static struct niu_parent * __devinit niu_get_parent(struct niu *np,
9533 union niu_parent_id *id,
9534 u8 ptype)
9535{
9536 struct niu_parent *p, *tmp;
9537 int port = np->port;
9538
a3138df9
DM		 9539 mutex_lock(&niu_parent_lock);
9540 p = NULL;
9541 list_for_each_entry(tmp, &niu_parent_list, list) {
9542 if (!memcmp(id, &tmp->id, sizeof(*id))) {
9543 p = tmp;
9544 break;
9545 }
9546 }
9547 if (!p)
9548 p = niu_new_parent(np, id, ptype);
9549
9550 if (p) {
9551 char port_name[6];
9552 int err;
9553
9554 sprintf(port_name, "port%d", port);
9555 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9556 &np->device->kobj,
9557 port_name);
9558 if (!err) {
9559 p->ports[port] = np;
9560 atomic_inc(&p->refcnt);
9561 }
9562 }
9563 mutex_unlock(&niu_parent_lock);
9564
9565 return p;
9566}
9567
9568static void niu_put_parent(struct niu *np)
9569{
9570 struct niu_parent *p = np->parent;
9571 u8 port = np->port;
9572 char port_name[6];
9573
9574 BUG_ON(!p || p->ports[port] != np);
9575
f10a1f2e
JP		 9576 netif_printk(np, probe, KERN_DEBUG, np->dev,
9577 "%s() port[%u]\n", __func__, port);
a3138df9
DM		 9578
9579 sprintf(port_name, "port%d", port);
9580
9581 mutex_lock(&niu_parent_lock);
9582
9583 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
9584
9585 p->ports[port] = NULL;
9586 np->parent = NULL;
9587
9588 if (atomic_dec_and_test(&p->refcnt)) {
9589 list_del(&p->list);
9590 platform_device_unregister(p->plat_dev);
9591 }
9592
9593 mutex_unlock(&niu_parent_lock);
9594}
9595
9596static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
9597 u64 *handle, gfp_t flag)
9598{
9599 dma_addr_t dh;
9600 void *ret;
9601
9602 ret = dma_alloc_coherent(dev, size, &dh, flag);
9603 if (ret)
9604 *handle = dh;
9605 return ret;
9606}
9607
9608static void niu_pci_free_coherent(struct device *dev, size_t size,
9609 void *cpu_addr, u64 handle)
9610{
9611 dma_free_coherent(dev, size, cpu_addr, handle);
9612}
9613
9614static u64 niu_pci_map_page(struct device *dev, struct page *page,
9615 unsigned long offset, size_t size,
9616 enum dma_data_direction direction)
9617{
9618 return dma_map_page(dev, page, offset, size, direction);
9619}
9620
9621static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
9622 size_t size, enum dma_data_direction direction)
9623{
a08b32df 9624 dma_unmap_page(dev, dma_address, size, direction);
a3138df9
DM		 9625}
9626
9627static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
9628 size_t size,
9629 enum dma_data_direction direction)
9630{
9631 return dma_map_single(dev, cpu_addr, size, direction);
9632}
9633
9634static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
9635 size_t size,
9636 enum dma_data_direction direction)
9637{
9638 dma_unmap_single(dev, dma_address, size, direction);
9639}
9640
9641static const struct niu_ops niu_pci_ops = {
9642 .alloc_coherent = niu_pci_alloc_coherent,
9643 .free_coherent = niu_pci_free_coherent,
9644 .map_page = niu_pci_map_page,
9645 .unmap_page = niu_pci_unmap_page,
9646 .map_single = niu_pci_map_single,
9647 .unmap_single = niu_pci_unmap_single,
9648};
9649
9650static void __devinit niu_driver_version(void)
9651{
9652 static int niu_version_printed;
9653
9654 if (niu_version_printed++ == 0)
9655 pr_info("%s", version);
9656}
9657
9658static struct net_device * __devinit niu_alloc_and_init(
9659 struct device *gen_dev, struct pci_dev *pdev,
2dc11581 9660 struct platform_device *op, const struct niu_ops *ops,
a3138df9
DM		 9661 u8 port)
9662{
b4c21639 9663 struct net_device *dev;
a3138df9
DM		 9664 struct niu *np;
9665
b4c21639 9666 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN);
a3138df9 9667 if (!dev) {
f10a1f2e 9668 dev_err(gen_dev, "Etherdev alloc failed, aborting\n");
a3138df9
DM		 9669 return NULL;
9670 }
9671
9672 SET_NETDEV_DEV(dev, gen_dev);
9673
9674 np = netdev_priv(dev);
9675 np->dev = dev;
9676 np->pdev = pdev;
9677 np->op = op;
9678 np->device = gen_dev;
9679 np->ops = ops;
9680
9681 np->msg_enable = niu_debug;
9682
9683 spin_lock_init(&np->lock);
9684 INIT_WORK(&np->reset_task, niu_reset_task);
9685
9686 np->port = port;
9687
9688 return dev;
9689}
9690
2c9171d4
SH		 9691static const struct net_device_ops niu_netdev_ops = {
9692 .ndo_open = niu_open,
9693 .ndo_stop = niu_close,
00829823 9694 .ndo_start_xmit = niu_start_xmit,
2c9171d4
SH		 9695 .ndo_get_stats = niu_get_stats,
9696 .ndo_set_multicast_list = niu_set_rx_mode,
9697 .ndo_validate_addr = eth_validate_addr,
9698 .ndo_set_mac_address = niu_set_mac_addr,
9699 .ndo_do_ioctl = niu_ioctl,
9700 .ndo_tx_timeout = niu_tx_timeout,
9701 .ndo_change_mtu = niu_change_mtu,
9702};
9703
a3138df9
DM		 9704static void __devinit niu_assign_netdev_ops(struct net_device *dev)
9705{
2c9171d4 9706 dev->netdev_ops = &niu_netdev_ops;
a3138df9
DM		 9707 dev->ethtool_ops = &niu_ethtool_ops;
9708 dev->watchdog_timeo = NIU_TX_TIMEOUT;
a3138df9
DM		 9709}
9710
9711static void __devinit niu_device_announce(struct niu *np)
9712{
9713 struct net_device *dev = np->dev;
a3138df9 9714
e174961c 9715 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr);
a3138df9 9716
5fbd7e24
MW		 9717 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) {
9718 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9719 dev->name,
9720 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9721 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
9722 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"),
9723 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9724 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9725 np->vpd.phy_type);
9726 } else {
9727 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9728 dev->name,
9729 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
9730 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
e3e081e1
SB		 9731 (np->flags & NIU_FLAGS_FIBER ? "FIBER" :
9732 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" :
9733 "COPPER")),
5fbd7e24
MW		 9734 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
9735 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
9736 np->vpd.phy_type);
9737 }
a3138df9
DM		 9738}
9739
3cfa856d
DM		 9740static void __devinit niu_set_basic_features(struct net_device *dev)
9741{
9742 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM |
9743 NETIF_F_GRO | NETIF_F_RXHASH);
9744}
9745
a3138df9
DM		 9746static int __devinit niu_pci_init_one(struct pci_dev *pdev,
9747 const struct pci_device_id *ent)
9748{
a3138df9
DM		 9749 union niu_parent_id parent_id;
9750 struct net_device *dev;
9751 struct niu *np;
9752 int err, pos;
9753 u64 dma_mask;
9754 u16 val16;
9755
9756 niu_driver_version();
9757
9758 err = pci_enable_device(pdev);
9759 if (err) {
f10a1f2e 9760 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
a3138df9
DM		 9761 return err;
9762 }
9763
9764 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
9765 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
f10a1f2e 9766 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n");
a3138df9
DM		 9767 err = -ENODEV;
9768 goto err_out_disable_pdev;
9769 }
9770
9771 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9772 if (err) {
f10a1f2e 9773 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
a3138df9
DM		 9774 goto err_out_disable_pdev;
9775 }
9776
9777 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9778 if (pos <= 0) {
f10a1f2e 9779 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n");
a3138df9
DM		 9780 goto err_out_free_res;
9781 }
9782
9783 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
9784 &niu_pci_ops, PCI_FUNC(pdev->devfn));
9785 if (!dev) {
9786 err = -ENOMEM;
9787 goto err_out_free_res;
9788 }
9789 np = netdev_priv(dev);
9790
9791 memset(&parent_id, 0, sizeof(parent_id));
9792 parent_id.pci.domain = pci_domain_nr(pdev->bus);
9793 parent_id.pci.bus = pdev->bus->number;
9794 parent_id.pci.device = PCI_SLOT(pdev->devfn);
9795
9796 np->parent = niu_get_parent(np, &parent_id,
9797 PLAT_TYPE_ATLAS);
9798 if (!np->parent) {
9799 err = -ENOMEM;
9800 goto err_out_free_dev;
9801 }
9802
9803 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
9804 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
9805 val16 |= (PCI_EXP_DEVCTL_CERE |
9806 PCI_EXP_DEVCTL_NFERE |
9807 PCI_EXP_DEVCTL_FERE |
9808 PCI_EXP_DEVCTL_URRE |
9809 PCI_EXP_DEVCTL_RELAX_EN);
9810 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
9811
8cbd9623 9812 dma_mask = DMA_BIT_MASK(44);
a3138df9
DM		 9813 err = pci_set_dma_mask(pdev, dma_mask);
9814 if (!err) {
9815 dev->features |= NETIF_F_HIGHDMA;
9816 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9817 if (err) {
f10a1f2e 9818 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
a3138df9
DM		 9819 goto err_out_release_parent;
9820 }
9821 }
284901a9
YH		 9822 if (err || dma_mask == DMA_BIT_MASK(32)) {
9823 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
a3138df9 9824 if (err) {
f10a1f2e 9825 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
a3138df9
DM		 9826 goto err_out_release_parent;
9827 }
9828 }
9829
3cfa856d 9830 niu_set_basic_features(dev);
a3138df9 9831
19ecb6ba 9832 np->regs = pci_ioremap_bar(pdev, 0);
a3138df9 9833 if (!np->regs) {
f10a1f2e 9834 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 9835 err = -ENOMEM;
9836 goto err_out_release_parent;
9837 }
9838
9839 pci_set_master(pdev);
9840 pci_save_state(pdev);
9841
9842 dev->irq = pdev->irq;
9843
9844 niu_assign_netdev_ops(dev);
9845
9846 err = niu_get_invariants(np);
9847 if (err) {
9848 if (err != -ENODEV)
f10a1f2e 9849 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 9850 goto err_out_iounmap;
9851 }
9852
9853 err = register_netdev(dev);
9854 if (err) {
f10a1f2e 9855 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 9856 goto err_out_iounmap;
9857 }
9858
9859 pci_set_drvdata(pdev, dev);
9860
9861 niu_device_announce(np);
9862
9863 return 0;
9864
9865err_out_iounmap:
9866 if (np->regs) {
9867 iounmap(np->regs);
9868 np->regs = NULL;
9869 }
9870
9871err_out_release_parent:
9872 niu_put_parent(np);
9873
9874err_out_free_dev:
9875 free_netdev(dev);
9876
9877err_out_free_res:
9878 pci_release_regions(pdev);
9879
9880err_out_disable_pdev:
9881 pci_disable_device(pdev);
9882 pci_set_drvdata(pdev, NULL);
9883
9884 return err;
9885}
9886
9887static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
9888{
9889 struct net_device *dev = pci_get_drvdata(pdev);
9890
9891 if (dev) {
9892 struct niu *np = netdev_priv(dev);
9893
9894 unregister_netdev(dev);
9895 if (np->regs) {
9896 iounmap(np->regs);
9897 np->regs = NULL;
9898 }
9899
9900 niu_ldg_free(np);
9901
9902 niu_put_parent(np);
9903
9904 free_netdev(dev);
9905 pci_release_regions(pdev);
9906 pci_disable_device(pdev);
9907 pci_set_drvdata(pdev, NULL);
9908 }
9909}
9910
9911static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
9912{
9913 struct net_device *dev = pci_get_drvdata(pdev);
9914 struct niu *np = netdev_priv(dev);
9915 unsigned long flags;
9916
9917 if (!netif_running(dev))
9918 return 0;
9919
9920 flush_scheduled_work();
9921 niu_netif_stop(np);
9922
9923 del_timer_sync(&np->timer);
9924
9925 spin_lock_irqsave(&np->lock, flags);
9926 niu_enable_interrupts(np, 0);
9927 spin_unlock_irqrestore(&np->lock, flags);
9928
9929 netif_device_detach(dev);
9930
9931 spin_lock_irqsave(&np->lock, flags);
9932 niu_stop_hw(np);
9933 spin_unlock_irqrestore(&np->lock, flags);
9934
9935 pci_save_state(pdev);
9936
9937 return 0;
9938}
9939
9940static int niu_resume(struct pci_dev *pdev)
9941{
9942 struct net_device *dev = pci_get_drvdata(pdev);
9943 struct niu *np = netdev_priv(dev);
9944 unsigned long flags;
9945 int err;
9946
9947 if (!netif_running(dev))
9948 return 0;
9949
9950 pci_restore_state(pdev);
9951
9952 netif_device_attach(dev);
9953
9954 spin_lock_irqsave(&np->lock, flags);
9955
9956 err = niu_init_hw(np);
9957 if (!err) {
9958 np->timer.expires = jiffies + HZ;
9959 add_timer(&np->timer);
9960 niu_netif_start(np);
9961 }
9962
9963 spin_unlock_irqrestore(&np->lock, flags);
9964
9965 return err;
9966}
9967
9968static struct pci_driver niu_pci_driver = {
9969 .name = DRV_MODULE_NAME,
9970 .id_table = niu_pci_tbl,
9971 .probe = niu_pci_init_one,
9972 .remove = __devexit_p(niu_pci_remove_one),
9973 .suspend = niu_suspend,
9974 .resume = niu_resume,
9975};
9976
9977#ifdef CONFIG_SPARC64
9978static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
9979 u64 *dma_addr, gfp_t flag)
9980{
9981 unsigned long order = get_order(size);
9982 unsigned long page = __get_free_pages(flag, order);
9983
9984 if (page == 0UL)
9985 return NULL;
9986 memset((char *)page, 0, PAGE_SIZE << order);
9987 *dma_addr = __pa(page);
9988
9989 return (void *) page;
9990}
9991
9992static void niu_phys_free_coherent(struct device *dev, size_t size,
9993 void *cpu_addr, u64 handle)
9994{
9995 unsigned long order = get_order(size);
9996
9997 free_pages((unsigned long) cpu_addr, order);
9998}
9999
10000static u64 niu_phys_map_page(struct device *dev, struct page *page,
10001 unsigned long offset, size_t size,
10002 enum dma_data_direction direction)
10003{
10004 return page_to_phys(page) + offset;
10005}
10006
10007static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
10008 size_t size, enum dma_data_direction direction)
10009{
10010 /* Nothing to do. */
10011}
10012
10013static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
10014 size_t size,
10015 enum dma_data_direction direction)
10016{
10017 return __pa(cpu_addr);
10018}
10019
10020static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
10021 size_t size,
10022 enum dma_data_direction direction)
10023{
10024 /* Nothing to do. */
10025}
10026
10027static const struct niu_ops niu_phys_ops = {
10028 .alloc_coherent = niu_phys_alloc_coherent,
10029 .free_coherent = niu_phys_free_coherent,
10030 .map_page = niu_phys_map_page,
10031 .unmap_page = niu_phys_unmap_page,
10032 .map_single = niu_phys_map_single,
10033 .unmap_single = niu_phys_unmap_single,
10034};
10035
2dc11581 10036static int __devinit niu_of_probe(struct platform_device *op,
a3138df9
DM		 10037 const struct of_device_id *match)
10038{
10039 union niu_parent_id parent_id;
10040 struct net_device *dev;
10041 struct niu *np;
10042 const u32 *reg;
10043 int err;
10044
10045 niu_driver_version();
10046
61c7a080 10047 reg = of_get_property(op->dev.of_node, "reg", NULL);
a3138df9 10048 if (!reg) {
f10a1f2e 10049 dev_err(&op->dev, "%s: No 'reg' property, aborting\n",
61c7a080 10050 op->dev.of_node->full_name);
a3138df9
DM		 10051 return -ENODEV;
10052 }
10053
10054 dev = niu_alloc_and_init(&op->dev, NULL, op,
10055 &niu_phys_ops, reg[0] & 0x1);
10056 if (!dev) {
10057 err = -ENOMEM;
10058 goto err_out;
10059 }
10060 np = netdev_priv(dev);
10061
10062 memset(&parent_id, 0, sizeof(parent_id));
61c7a080 10063 parent_id.of = of_get_parent(op->dev.of_node);
a3138df9
DM		 10064
10065 np->parent = niu_get_parent(np, &parent_id,
10066 PLAT_TYPE_NIU);
10067 if (!np->parent) {
10068 err = -ENOMEM;
10069 goto err_out_free_dev;
10070 }
10071
3cfa856d 10072 niu_set_basic_features(dev);
a3138df9
DM		 10073
10074 np->regs = of_ioremap(&op->resource[1], 0,
6f0e0135 10075 resource_size(&op->resource[1]),
a3138df9
DM		 10076 "niu regs");
10077 if (!np->regs) {
f10a1f2e 10078 dev_err(&op->dev, "Cannot map device registers, aborting\n");
a3138df9
DM		 10079 err = -ENOMEM;
10080 goto err_out_release_parent;
10081 }
10082
10083 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
6f0e0135 10084 resource_size(&op->resource[2]),
a3138df9
DM		 10085 "niu vregs-1");
10086 if (!np->vir_regs_1) {
f10a1f2e 10087 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n");
a3138df9
DM		 10088 err = -ENOMEM;
10089 goto err_out_iounmap;
10090 }
10091
10092 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
6f0e0135 10093 resource_size(&op->resource[3]),
a3138df9
DM		 10094 "niu vregs-2");
10095 if (!np->vir_regs_2) {
f10a1f2e 10096 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n");
a3138df9
DM		 10097 err = -ENOMEM;
10098 goto err_out_iounmap;
10099 }
10100
10101 niu_assign_netdev_ops(dev);
10102
10103 err = niu_get_invariants(np);
10104 if (err) {
10105 if (err != -ENODEV)
f10a1f2e 10106 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n");
a3138df9
DM		 10107 goto err_out_iounmap;
10108 }
10109
10110 err = register_netdev(dev);
10111 if (err) {
f10a1f2e 10112 dev_err(&op->dev, "Cannot register net device, aborting\n");
a3138df9
DM		 10113 goto err_out_iounmap;
10114 }
10115
10116 dev_set_drvdata(&op->dev, dev);
10117
10118 niu_device_announce(np);
10119
10120 return 0;
10121
10122err_out_iounmap:
10123 if (np->vir_regs_1) {
10124 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10125 resource_size(&op->resource[2]));
a3138df9
DM		 10126 np->vir_regs_1 = NULL;
10127 }
10128
10129 if (np->vir_regs_2) {
10130 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10131 resource_size(&op->resource[3]));
a3138df9
DM		 10132 np->vir_regs_2 = NULL;
10133 }
10134
10135 if (np->regs) {
10136 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10137 resource_size(&op->resource[1]));
a3138df9
DM		 10138 np->regs = NULL;
10139 }
10140
10141err_out_release_parent:
10142 niu_put_parent(np);
10143
10144err_out_free_dev:
10145 free_netdev(dev);
10146
10147err_out:
10148 return err;
10149}
10150
2dc11581 10151static int __devexit niu_of_remove(struct platform_device *op)
a3138df9
DM		 10152{
10153 struct net_device *dev = dev_get_drvdata(&op->dev);
10154
10155 if (dev) {
10156 struct niu *np = netdev_priv(dev);
10157
10158 unregister_netdev(dev);
10159
10160 if (np->vir_regs_1) {
10161 of_iounmap(&op->resource[2], np->vir_regs_1,
6f0e0135 10162 resource_size(&op->resource[2]));
a3138df9
DM		 10163 np->vir_regs_1 = NULL;
10164 }
10165
10166 if (np->vir_regs_2) {
10167 of_iounmap(&op->resource[3], np->vir_regs_2,
6f0e0135 10168 resource_size(&op->resource[3]));
a3138df9
DM		 10169 np->vir_regs_2 = NULL;
10170 }
10171
10172 if (np->regs) {
10173 of_iounmap(&op->resource[1], np->regs,
6f0e0135 10174 resource_size(&op->resource[1]));
a3138df9
DM		 10175 np->regs = NULL;
10176 }
10177
10178 niu_ldg_free(np);
10179
10180 niu_put_parent(np);
10181
10182 free_netdev(dev);
10183 dev_set_drvdata(&op->dev, NULL);
10184 }
10185 return 0;
10186}
10187
fd098316 10188static const struct of_device_id niu_match[] = {
a3138df9
DM		 10189 {
10190 .name = "network",
10191 .compatible = "SUNW,niusl",
10192 },
10193 {},
10194};
10195MODULE_DEVICE_TABLE(of, niu_match);
10196
10197static struct of_platform_driver niu_of_driver = {
4018294b
GL		 10198 .driver = {
10199 .name = "niu",
10200 .owner = THIS_MODULE,
10201 .of_match_table = niu_match,
10202 },
a3138df9
DM		 10203 .probe = niu_of_probe,
10204 .remove = __devexit_p(niu_of_remove),
10205};
10206
10207#endif /* CONFIG_SPARC64 */
10208
10209static int __init niu_init(void)
10210{
10211 int err = 0;
10212
81429973 10213 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
a3138df9
DM		 10214
10215 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
10216
10217#ifdef CONFIG_SPARC64
1ab1d63a 10218 err = of_register_platform_driver(&niu_of_driver);
a3138df9
DM		 10219#endif
10220
10221 if (!err) {
10222 err = pci_register_driver(&niu_pci_driver);
10223#ifdef CONFIG_SPARC64
10224 if (err)
1ab1d63a 10225 of_unregister_platform_driver(&niu_of_driver);
a3138df9
DM		 10226#endif
10227 }
10228
10229 return err;
10230}
10231
10232static void __exit niu_exit(void)
10233{
10234 pci_unregister_driver(&niu_pci_driver);
10235#ifdef CONFIG_SPARC64
1ab1d63a 10236 of_unregister_platform_driver(&niu_of_driver);
a3138df9
DM		 10237#endif
10238}
10239
10240module_init(niu_init);
10241module_exit(niu_exit);
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